diff --git a/.gitignore b/.gitignore index 6db91c9c8d..d2e86666cb 100644 --- a/.gitignore +++ b/.gitignore @@ -40,5 +40,7 @@ coverage tools/ruby-gems/udb/ext/z3/**/*.so tools/ruby-gems/udb/ext/z3/VERSION +# LLM Extraction Tool local artifacts (regenerable, not stored in git) + # emacs backup files *~ diff --git a/tools/llm-extraction/configs/__init__.py b/tools/llm-extraction/configs/__init__.py new file mode 100644 index 0000000000..5e8ce4fa53 --- /dev/null +++ b/tools/llm-extraction/configs/__init__.py @@ -0,0 +1,9 @@ +""" +configs/ — pipeline configuration package. + +Exports +------- + config — path constants, logging, chunking vocabulary + taxonomy — parameter classes / types / file categories (YAML-backed) + schema_rules — filter keyword lists for spec_chunker (YAML-backed) +""" diff --git a/tools/llm-extraction/configs/config.py b/tools/llm-extraction/configs/config.py new file mode 100644 index 0000000000..52252f29ed --- /dev/null +++ b/tools/llm-extraction/configs/config.py @@ -0,0 +1,147 @@ +""" +Purpose: + Central configuration for the RISC-V UDB LLM-extraction pipeline. + Defines all path constants, logging setup, and high-level chunking vocabulary. + +Pipeline Stage: + all (imported by every pipeline module) + +Inputs: + - spec/schemas/schema_defs.json (loaded once for $ref resolution) + +Outputs: + - (none — configuration only) + +Core Responsibilities: + - Resolve TOOL_DIR, DATA_DIR, REPO_ROOT from __file__ + - Declare ISA source paths (PARAM_DIR, CSR_DIR, EXT_DIR, PROSE_DIR) + - Declare output paths (OUTPUT_DIR, CORPUS_PATH, DB_DIR, etc.) + - Provide CHUNK_KEYWORDS and DIR_TO_CHUNK_TYPE for broad intent routing + - Load SCHEMA_DEFS_DATA once at import time + +Key Assumptions: + - This file lives at llm-extraction/configs/config.py + - REPO_ROOT is always riscv-unified-db/ (4 levels up from this file) + - All runtime artefacts are written under DATA_DIR, not alongside source + +Failure Modes: + - SCHEMA_DEFS_DATA silently becomes {} if schema_defs.json is missing + - Wrong REPO_ROOT if directory structure is changed + +Notes: + - Fine-grained filter keyword lists live in schema_rules.yaml, not here + - Taxonomy enumerations live in taxonomy.yaml, not here +""" + +from pathlib import Path +from ruamel.yaml import YAML +import json +import logging + +# --------------------------------------------------------------------------- +# Logging +# --------------------------------------------------------------------------- + +logging.basicConfig(level=logging.INFO, format="%(levelname)s: %(message)s") +logger = logging.getLogger("udb") + +# --------------------------------------------------------------------------- +# Directory layout +# --------------------------------------------------------------------------- + +CONFIGS_DIR = Path(__file__).parent.resolve() # llm-extraction/configs/ +TOOL_DIR = CONFIGS_DIR.parent # llm-extraction/ +REPO_ROOT = TOOL_DIR.parent.parent.parent # riscv-unified-db/ + +DATA_DIR = TOOL_DIR / "data" + +# --------------------------------------------------------------------------- +# ISA source paths (inside the riscv-unified-db repository) +# --------------------------------------------------------------------------- + +PARAM_DIR = REPO_ROOT / "spec" / "std" / "isa" / "param" +CSR_DIR = REPO_ROOT / "spec" / "std" / "isa" / "csr" +EXT_DIR = REPO_ROOT / "spec" / "std" / "isa" / "ext" +PROSE_DIR = REPO_ROOT / "spec" / "std" / "isa" / "prose" +SCHEMA_DEFS = REPO_ROOT / "spec" / "schemas" / "schema_defs.json" + +# --------------------------------------------------------------------------- +# ISA manual (external, shallow-cloned into data/) +# --------------------------------------------------------------------------- + +ISA_MANUAL_REPO_URL = "https://github.com/riscv/riscv-isa-manual.git" +ISA_MANUAL_DIR = DATA_DIR / "riscv-isa-manual" + +# --------------------------------------------------------------------------- +# Output paths (all under data/output/) +# --------------------------------------------------------------------------- + +OUTPUT_DIR = DATA_DIR / "output" +CORPUS_PATH = OUTPUT_DIR / "param_corpus.json" +ANALYSIS_CORPUS_PATH = OUTPUT_DIR / "param_analysis_corpus.json" +REPORT_PATH = OUTPUT_DIR / "UDB_PARAMETER_DATABASE_REPORT.md" +GRAPH_PATH = OUTPUT_DIR / "dependency_graph.json" +CHUNKS_PATH = OUTPUT_DIR / "chunks.json" +CHUNKS_REPO_PATH = OUTPUT_DIR / "chunks_repo.json" +PARAMETER_DATASET_PATH = OUTPUT_DIR / "parameter_dataset.csv" +FILTER_STATS_PATH = OUTPUT_DIR / "filter_stats.md" +RAW_CHUNKS_DIR = OUTPUT_DIR / "raw_chunks" + +# --------------------------------------------------------------------------- +# ChromaDB vector index (data/chroma_db/) +# --------------------------------------------------------------------------- + +DB_DIR = DATA_DIR / "chroma_db" + +# --------------------------------------------------------------------------- +# Misc constants +# --------------------------------------------------------------------------- + +MOCK_PREFIX = "MOCK_" + +CSR_IDL_KEYS = { + "sw_write(csr_value)", + "type()", + "reset_value()", + "legal?(csr_value)", + "sw_read()", +} + +# --------------------------------------------------------------------------- +# Chunking vocabulary (high-level; file-type routing and broad keyword groups) +# Fine-grained filter vocabulary lives in configs/schema_rules.yaml. +# --------------------------------------------------------------------------- + +# Maps source-file directory extension → chunk type label stored in output JSON. +DIR_TO_CHUNK_TYPE: dict[str, str] = { + "adoc": "adoc_prose", # AsciiDoc ISA manual prose + "yaml": "yaml_schema", # UDB parameter / CSR YAML schemas + "json": "json_schema", # JSON schema definitions +} + +# Broad keyword families used by the chunker for quick intent classification. +# Detailed keyword lists (frozensets) are loaded from schema_rules.yaml at +# runtime by spec_chunker.py to allow tuning without code changes. +CHUNK_KEYWORDS: dict[str, list[str]] = { + "normative_strong": ["[#norm:"], + "normative_words": ["may", "must", "should", "shall"], + "parameter_flags": ["warl", "wlrl", "legal", "implementation-defined", "configurable"], +} + +# --------------------------------------------------------------------------- +# YAML helper (shared across pipeline modules) +# --------------------------------------------------------------------------- + +yaml = YAML() +yaml.preserve_quotes = True + +# --------------------------------------------------------------------------- +# Schema definitions (loaded once at import time) +# --------------------------------------------------------------------------- + +try: + with open(SCHEMA_DEFS, "r", encoding="utf-8") as _f: + SCHEMA_DEFS_DATA = json.load(_f) +except Exception as _e: + logger.warning(f"Could not load schema_defs.json: {_e}") + SCHEMA_DEFS_DATA = {} diff --git a/tools/llm-extraction/configs/schema_rules.yaml b/tools/llm-extraction/configs/schema_rules.yaml new file mode 100644 index 0000000000..8baa6b8cb5 --- /dev/null +++ b/tools/llm-extraction/configs/schema_rules.yaml @@ -0,0 +1,350 @@ +# configs/schema_rules.yaml +# ────────────────────────────────────────────────────────────────────────────── +# Filter keyword lists for the RISC-V UDB spec_chunker.py pipeline. +# +# This file externalises every frozenset / vocabulary constant that was +# previously hardcoded in spec_chunker.py so they can be tuned, reviewed, or +# audited without touching Python source. +# +# Sections +# -------- +# signals — keyword lists that BOOST a sentence (keep signals) +# noise — keyword lists that SUPPRESS a sentence (drop signals) +# intent — mode-specific intent keyword groups +# regex_constants — notes on compiled regex patterns (informational only; +# regexes themselves stay in Python for safety) +# +# All lists are lowercased. Trailing spaces (e.g. "may ") are intentional — +# they prevent matching substrings like "maybe", "mayor", "whenever". +# ────────────────────────────────────────────────────────────────────────────── + + +# ── 1. Keep signals ────────────────────────────────────────────────────────── + +signals: + + # Hard normative modals. "must not" and "shall not" both match because the + # parent token ("must", "shall") is normative regardless of negation. + strong_modals: + - must + - shall + + # Permission / recommendation modals. "can" and "either" are deliberately + # absent — too common in non-normative prose. + # Note: "may " has a trailing space to avoid "maybe", "mayor" etc. + weak_modals: + - should + - "may " + - need not + - is not required to + + # Named CSR identifiers and RISC-V-specific register names. + # Bare "register" is intentionally absent (causes false positives in prose). + csr_vocab: + - csr + - warl + - wpri + - wlrl + - mstatus + - sstatus + - ustatus + - mtvec + - stvec + - utvec + - mepc + - sepc + - uepc + - mcause + - scause + - ucause + - mtval + - stval + - utval + - mip + - mie + - sip + - sie + - satp + - hgatp + - vsatp + - hstatus + - vsstatus + - vsie + - vsip + - vsepc + - vstval + - pmpcfg + - pmpaddr + - mhpmcounter + - mhpmevent + - mcounteren + - scounteren + - hcounteren + - menvcfg + - senvcfg + - henvcfg + - mideleg + - medeleg + - sideleg + - sedeleg + - mscratch + - sscratch + - mhartid + - mvendorid + - marchid + - mimpid + - fcsr + - fflags + - frm + - vstart + - vxsat + - vxrm + - vcsr + - vl + - vtype + - vlenb + - tselect + - tdata1 + - tdata2 + - tdata3 + - dcsr + - dpc + - dscratch0 + - dscratch1 + + # Used only for section-name context boosting, NOT sentence classification. + register_context_vocab: + - csr + - register + - control register + - status register + + # Bit / field structure vocabulary. + # "bit" and "bits" alone are omitted; pair with bit_constraint for explicit rules. + field_vocab: + - field + - encoded + - value of + - sign-extended + - zero-extended + - upper bits + - lower bits + - most significant + - least significant + + # Used jointly with field_vocab for _has_explicit_bit_rule(). + bit_constraint_vocab: + - bit + - bits + + # Range / numeric constraint vocabulary. + # Bare digit matching is intentionally omitted (causes raw-chunk explosion). + range_vocab: + - greater than + - less than + - no greater than + - no less than + - at least + - at most + - equal to + - not equal + - maximum + - minimum + - in the range + - xlen-bit + - xlen bits + + # Condition / trap vocabulary. + # "if " and "when " have trailing spaces to avoid "differs", "whenever". + condition_vocab: + - "if " + - "when " + - "unless " + - provided that + - in the case + - trap + - exception + - fault + - interrupt + - illegal instruction + + # Precise boolean-state vocabulary. + # "set" and "clear" alone are omitted (appear in non-normative prose). + binary_state_vocab: + - enabled + - disabled + - set to 0 + - set to 1 + - set to zero + - set to one + - cleared to + - cleared when + - asserted + - deasserted + - read-only zero + - hardwired to zero + - hardwired to one + - active-low + - active-high + + # CSR field access-mode vocabulary. + access_vocab: + - read-only + - write-only + - read/write + - writable + - write-1-to-clear + - write-1-to-set + + # Normative intent vocabulary used in the general extract mode. + normative_intent_vocab: + - determined by + - depends on + - computed from + - not permitted + - illegal instruction + - raise + - raises + - results in + - is extended to + - are extended to + + +# ── 2. Drop signals ────────────────────────────────────────────────────────── + +noise: + + # Non-normative narrative patterns. + # A sentence matching any of these is rejected UNLESS a strong modal is present. + narrative_patterns: + - for example + - for instance + - e.g. + - i.e. + - we propose + - we proposed + - it is suggested + - this allows + - this avoids + - this ensures + - is designed to + - intended to + - intended for + - useful in + - useful for + - can often + - in practice + - typically + - in general + - note that + - "note:" + - rationale + - as an example + + # Pure-computation patterns — no constraint implied. + computation_patterns: + - expands to + - is performed + - the result is + - are arithmetic + - are instructions + - contains instructions + - are crucial + - are essential + + # AsciiDoc / diagram artefacts that survive text cleaning. + noise_patterns: + - wavedrom + - "..." + - we propose + - we proposed + - "rationale:" + - "introduction:" + + # Soft-rationale patterns — rejected when no strong modal is present. + soft_rationale_patterns: + - can often + - can be used to + - is useful + - are useful + - "because " + - this avoids + - this allows + - this ensures + - in some implementations + - designed to + - intended to + - is important + - are important + - is crucial + - are crucial + - is intended + - are intended + + +# ── 3. Intent vocabularies (mode-specific) ──────────────────────────────────── + +intent: + + # process_formal — memory-model / formal sections. + formal: + - ordering + - constraint + - visible + - execution + - allowed + - observed + - memory + - operation + - po + - rf + - co + - fr + - happens-before + - program order + + # process_profile — profile requirement sections. + profile: + - requires + - must include + - mandatory + - optional + - profile + - extension + - shall support + - ratified + - mandated + + # process_docs — naming / intro / preface sections. + docs: + - must be + - format + - naming + - encoding + - structure + + +# ── 4. Regex constants (informational) ──────────────────────────────────────── +# These regexes are compiled in Python (spec_chunker.py) for performance; +# they are documented here for auditability and cross-referencing. + +regex_constants: + note_block: '\[NOTE\]\s*\n====.*?====\s*\n' + equal_runs: '={2,}' + anchor: '\[\[.*?\]\]' + norm_attr: '\[#?norm:[^\]]+\]#?' + index_term: '\(\(\(.*?\)\)\)' + xref: '<<[^>]+>>' + table: '\|===.*?\|===' + percent_attr: '\[%.*?\]' + block_comment: '/\*.*?\*/' + list_bullet: '^[\*\-]\s+' + whitespace: '\s+' + section_hdr: '^(=+)\s+(.+)$' + split_sentence: '(?<=[.;])\s+(?=[A-Z][a-z])' + split_conditional: '(?=\b(?:If|When|Unless|Otherwise)\b)' + tag_pair: '<[^>]{1,80}>' + numeric_constraint: > + \b\d+\s*(?:bits?|bytes?|words?|xlen|mxlen|ilen)\b + |\b(?:at least|at most|no (?:greater|less) than)\s+\d + |\b\d+(?:-bit|-byte)\b diff --git a/tools/llm-extraction/configs/taxonomy.yaml b/tools/llm-extraction/configs/taxonomy.yaml new file mode 100644 index 0000000000..9b8d269ee5 --- /dev/null +++ b/tools/llm-extraction/configs/taxonomy.yaml @@ -0,0 +1,94 @@ +# configs/taxonomy.yaml +# ────────────────────────────────────────────────────────────────────────────── +# Structural taxonomy for the RISC-V UDB parameter-extraction pipeline. +# +# Three top-level sections: +# parameter_classes — _classify_parameter_class() output labels +# parameter_types — _classify_parameter_type() output labels +# ignore_file_categories — file-classification rules for classify_file() +# +# Edit this file to add new labels or ignore-rules; no Python code changes needed. +# ────────────────────────────────────────────────────────────────────────────── + +# ── 1. Parameter classes ────────────────────────────────────────────────────── +# Priority order is significant: first match wins in _classify_parameter_class(). +parameter_classes: + - name: CSR_controlled + description: > + Parameter value is controlled by a named CSR, or is a WARL/WPRI/WLRL + field with an explicit access-mode constraint. + priority: 1 + + - name: SW_rule + description: > + Software-visible rule: fence, ABI, calling-convention, supervisor/ + machine-mode software, hypervisor, or OS constraint. + priority: 2 + + - name: non_CSR_parameter + description: > + Implementation-defined or architectural constraint not tied to a + specific CSR: instruction semantics, memory model rules, + unpredictable/unspecified behaviour, numeric hardware constraints. + priority: 3 + + - name: unknown + description: > + No recognisable classification signal; kept for human review. + priority: 4 + +# ── 2. Parameter types ──────────────────────────────────────────────────────── +# Priority order: first match wins in _classify_parameter_type(). +parameter_types: + - name: binary + description: > + Explicit boolean state: enabled/disabled, hardwired-to-zero/one, + set-to-0/1, asserted/deasserted, active-low/high, read-only zero. + + - name: range + description: > + Concrete numeric or bit-width bound: at-least/at-most, minimum/maximum, + in-the-range, XLEN-bit, no-greater/less-than. + + - name: enum + description: > + Mode or encoding selection from a fixed enumerated set: privilege level, + access mode, addressing mode, CSR field encoding. + + - name: unknown + description: > + No type signal found; kept for human review. + +# ── 3. File-classification rules ────────────────────────────────────────────── +# Used by classify_file() in spec_chunker.py to decide how each .adoc is handled. +ignore_file_categories: + + # Files skipped entirely — no chunks emitted. + ignored_exact: + - bibliography.adoc + - contributors.adoc + - license.adoc + - index.adoc + - riscv-spec.adoc + + # Memory-model / formal sections — processed in light mode. + formal_files: + - mm-formal.adoc + - mm-explanatory.adoc + + # Files whose path includes this prefix → process_profile mode. + profile_prefix: "profiles/" + + # Naming / intro / preface sections → process_docs mode. + doc_files: + - naming.adoc + - intro.adoc + - preface.adoc + + # Mapping mode name → ignored-category bucket used in the report. + mode_to_category: + ignore: docs + process_formal: formal + process_profile: profiles + process_docs: docs + process: ~ # null → main corpus, not placed in an ignored bucket diff --git a/tools/llm-extraction/data/evaluation/report_adoc_chunker.md b/tools/llm-extraction/data/evaluation/report_adoc_chunker.md new file mode 100644 index 0000000000..4782e95c47 --- /dev/null +++ b/tools/llm-extraction/data/evaluation/report_adoc_chunker.md @@ -0,0 +1,226 @@ +# AsciiDoc Spec Chunker Full Analysis Report + +## Executive Summary +- Total Files: 136 +- Processed Files: 131 +- Skipped Files: 5 +- Total Raw Chunks: 10529 +- Final Chunks (in dataset): 4311 +- Reduction: 59.06% + + +## Filter Breakdown (Why chunks were dropped) +- low_signal: 3092 +- truncated: 897 +- non_normative: 461 +- noise: 443 +- note: 378 +- bullet: 313 +- instruction_description: 139 +- doc_filtered: 93 +- soft_rationale: 85 +- profile_filtered: 83 +- synopsis_header: 81 +- broken_reference: 66 +- formal_reference_tag: 42 +- computation_description: 33 +- formal_filtered: 12 + +## Confidence Distribution +- high: 3258 (75.6%) +- medium: 546 (12.7%) +- very_high: 507 (11.8%) + +## Parameter Classification Summary +- unknown: 1637 (38.0%) +- CSR_controlled: 1382 (32.1%) +- non_CSR_parameter: 1038 (24.1%) +- SW_rule: 254 (5.9%) + +## Parameter Type Summary +- enum: 2011 (46.6%) +- unknown: 1374 (31.9%) +- range: 569 (13.2%) +- binary: 357 (8.3%) + +## Per-file Chunk Selection Analysis +| S.No | File | Raw Candidates | Selected Final Chunks | Dropped | +|---|---|---|---|---| +| 1 | `src/scalar-crypto.adoc` | 1075 | 233 | 842 | +| 2 | `src/v-st-ext.adoc` | 1440 | 625 | 815 | +| 3 | `src/vector-crypto.adoc` | 670 | 117 | 553 | +| 4 | `src/b-st-ext.adoc` | 591 | 40 | 551 | +| 5 | `src/unpriv/mm-explanatory.adoc` | 447 | 171 | 276 | +| 6 | `src/priv/machine.adoc` | 791 | 590 | 201 | +| 7 | `src/priv/hypervisor.adoc` | 585 | 426 | 159 | +| 8 | `src/unpriv/zcmp.adoc` | 200 | 51 | 149 | +| 9 | `src/intro.adoc` | 143 | 5 | 138 | +| 10 | `src/unpriv/cmo.adoc` | 202 | 64 | 138 | +| 11 | `src/priv/supervisor.adoc` | 403 | 286 | 117 | +| 12 | `src/unpriv/zcb.adoc` | 115 | 13 | 102 | +| 13 | `src/unpriv/mm-formal.adoc` | 248 | 148 | 100 | +| 14 | `src/unpriv/cfi.adoc` | 160 | 64 | 96 | +| 15 | `src/unpriv/zca.adoc` | 159 | 63 | 96 | +| 16 | `src/profiles/rva23.adoc` | 95 | 3 | 92 | +| 17 | `src/profiles/intro.adoc` | 116 | 25 | 91 | +| 18 | `src/profiles/rva22.adoc` | 87 | 3 | 84 | +| 19 | `src/rv32.adoc` | 152 | 71 | 81 | +| 20 | `src/profiles/rvb23.adoc` | 84 | 6 | 78 | +| 21 | `src/naming.adoc` | 82 | 8 | 74 | +| 22 | `src/priv/zpm.adoc` | 109 | 35 | 74 | +| 23 | `src/priv/preface.adoc` | 75 | 5 | 70 | +| 24 | `src/unpriv/preface.adoc` | 75 | 5 | 70 | +| 25 | `src/unpriv/rvwmo.adoc` | 167 | 99 | 68 | +| 26 | `src/priv/smctr.adoc` | 273 | 209 | 64 | +| 27 | `src/priv/csrs.adoc` | 126 | 65 | 61 | +| 28 | `src/profiles/rva20.adoc` | 60 | 2 | 58 | +| 29 | `src/unpriv/zcmt.adoc` | 71 | 23 | 48 | +| 30 | `src/unpriv/rationale.adoc` | 60 | 14 | 46 | +| 31 | `src/priv/intro.adoc` | 44 | 0 | 44 | +| 32 | `src/profiles/rvi20.adoc` | 43 | 1 | 42 | +| 33 | `src/unpriv/zclsd.adoc` | 44 | 9 | 35 | +| 34 | `src/unpriv/rv-32-64g.adoc` | 38 | 6 | 32 | +| 35 | `src/rv64.adoc` | 50 | 20 | 30 | +| 36 | `src/unpriv/zalasr.adoc` | 33 | 7 | 26 | +| 37 | `src/priv/cfi.adoc` | 69 | 44 | 25 | +| 38 | `src/unpriv/zilsd.adoc` | 38 | 15 | 23 | +| 39 | `src/unpriv/zvfbfmin.adoc` | 23 | 1 | 22 | +| 40 | `src/unpriv/zfbfmin.adoc` | 22 | 3 | 19 | +| 41 | `src/unpriv/zicond.adoc` | 36 | 17 | 19 | +| 42 | `src/priv/smstateen.adoc` | 94 | 76 | 18 | +| 43 | `src/unpriv/f-st-ext.adoc` | 84 | 66 | 18 | +| 44 | `src/unpriv/zacas.adoc` | 37 | 19 | 18 | +| 45 | `src/unpriv/zvfbfwma.adoc` | 19 | 1 | 18 | +| 46 | `src/priv/rationale.adoc` | 35 | 18 | 17 | +| 47 | `src/priv/ssqosid.adoc` | 28 | 12 | 16 | +| 48 | `src/unpriv/vector-examples.adoc` | 27 | 11 | 16 | +| 49 | `src/unpriv/zabha.adoc` | 20 | 4 | 16 | +| 50 | `src/priv/svpbmt.adoc` | 29 | 14 | 15 | +| 51 | `src/unpriv/zfa.adoc` | 49 | 34 | 15 | +| 52 | `src/priv/smepmp.adoc` | 20 | 6 | 14 | +| 53 | `src/unpriv/q-st-ext.adoc` | 19 | 5 | 14 | +| 54 | `src/unpriv/zalrsc.adoc` | 34 | 20 | 14 | +| 55 | `src/unpriv/zawrs.adoc` | 26 | 12 | 14 | +| 56 | `src/priv/smcdeleg.adoc` | 39 | 26 | 13 | +| 57 | `src/unpriv/bitmanip-examples.adoc` | 16 | 3 | 13 | +| 58 | `src/unpriv/zimop.adoc` | 17 | 4 | 13 | +| 59 | `src/unpriv/za.adoc` | 15 | 3 | 12 | +| 60 | `src/unpriv/zcmop.adoc` | 13 | 1 | 12 | +| 61 | `src/unpriv/zihintntl.adoc` | 21 | 9 | 12 | +| 62 | `src/unpriv/zfh.adoc` | 21 | 10 | 11 | +| 63 | `src/priv/smcntrpmf.adoc` | 24 | 15 | 9 | +| 64 | `src/unpriv/m-st-ext.adoc` | 18 | 9 | 9 | +| 65 | `src/unpriv/zcf.adoc` | 17 | 8 | 9 | +| 66 | `src/priv/smrnmi.adoc` | 50 | 42 | 8 | +| 67 | `src/priv/svinval.adoc` | 17 | 9 | 8 | +| 68 | `src/profiles/preface.adoc` | 9 | 1 | 8 | +| 69 | `src/unpriv/zaamo.adoc` | 16 | 8 | 8 | +| 70 | `src/unpriv/zf.adoc` | 8 | 0 | 8 | +| 71 | `src/unpriv/ziccif.adoc` | 11 | 3 | 8 | +| 72 | `src/priv/sscofpmf.adoc` | 39 | 32 | 7 | +| 73 | `src/unpriv/zcd.adoc` | 14 | 7 | 7 | +| 74 | `src/unpriv/zicntr.adoc` | 22 | 15 | 7 | +| 75 | `src/unpriv/zicsr.adoc` | 50 | 43 | 7 | +| 76 | `src/unpriv/zifencei.adoc` | 9 | 2 | 7 | +| 77 | `src/priv/smcsrind.adoc` | 58 | 53 | 5 | +| 78 | `src/unpriv/d-st-ext.adoc` | 27 | 22 | 5 | +| 79 | `src/unpriv/zc.adoc` | 7 | 2 | 5 | +| 80 | `src/images/graphviz/litmus_sample.adoc` | 4 | 0 | 4 | +| 81 | `src/priv/smdbltrp.adoc` | 7 | 3 | 4 | +| 82 | `src/priv/ssdbltrp.adoc` | 6 | 2 | 4 | +| 83 | `src/priv/svnapot.adoc` | 9 | 5 | 4 | +| 84 | `src/rv32e.adoc` | 5 | 1 | 4 | +| 85 | `src/unpriv/c-st-ext.adoc` | 6 | 2 | 4 | +| 86 | `src/unpriv/memory-models.adoc` | 4 | 0 | 4 | +| 87 | `src/unpriv/zfhmin.adoc` | 7 | 3 | 4 | +| 88 | `src/priv/insns.adoc` | 3 | 0 | 3 | +| 89 | `src/unpriv/zce.adoc` | 4 | 1 | 3 | +| 90 | `src/unpriv/zfinx.adoc` | 27 | 24 | 3 | +| 91 | `src/unpriv/zi.adoc` | 4 | 1 | 3 | +| 92 | `src/unpriv/zicclsm.adoc` | 5 | 2 | 3 | +| 93 | `src/unpriv/zmmul.adoc` | 3 | 0 | 3 | +| 94 | `src/unpriv/ztso.adoc` | 6 | 3 | 3 | +| 95 | `src/priv/sh.adoc` | 2 | 0 | 2 | +| 96 | `src/priv/sha.adoc` | 2 | 0 | 2 | +| 97 | `src/priv/sm.adoc` | 2 | 0 | 2 | +| 98 | `src/priv/ss.adoc` | 2 | 0 | 2 | +| 99 | `src/priv/sstc.adoc` | 7 | 5 | 2 | +| 100 | `src/priv/sv.adoc` | 2 | 0 | 2 | +| 101 | `src/priv/svadu.adoc` | 7 | 5 | 2 | +| 102 | `src/unpriv/zp.adoc` | 2 | 0 | 2 | +| 103 | `src/priv/svrsw60t59b.adoc` | 3 | 2 | 1 | +| 104 | `src/unpriv/a-st-ext.adoc` | 1 | 0 | 1 | +| 105 | `src/unpriv/code-examples.adoc` | 1 | 0 | 1 | +| 106 | `src/unpriv/mm-appendix.adoc` | 1 | 0 | 1 | +| 107 | `src/unpriv/zars.adoc` | 3 | 2 | 1 | +| 108 | `src/unpriv/zihpm.adoc` | 7 | 6 | 1 | +| 109 | `src/priv/priv.adoc` | 0 | 0 | 0 | +| 110 | `src/priv/shcounterenw.adoc` | 1 | 1 | 0 | +| 111 | `src/priv/shgatpa.adoc` | 2 | 2 | 0 | +| 112 | `src/priv/shtvala.adoc` | 1 | 1 | 0 | +| 113 | `src/priv/shvsatpa.adoc` | 1 | 1 | 0 | +| 114 | `src/priv/shvstvala.adoc` | 1 | 1 | 0 | +| 115 | `src/priv/shvstvecd.adoc` | 2 | 2 | 0 | +| 116 | `src/priv/ssccptr.adoc` | 1 | 1 | 0 | +| 117 | `src/priv/sscounterenw.adoc` | 1 | 1 | 0 | +| 118 | `src/priv/ssstrict.adoc` | 2 | 2 | 0 | +| 119 | `src/priv/sstvala.adoc` | 2 | 2 | 0 | +| 120 | `src/priv/sstvecd.adoc` | 2 | 2 | 0 | +| 121 | `src/priv/ssu64xl.adoc` | 1 | 1 | 0 | +| 122 | `src/priv/svvptc.adoc` | 1 | 1 | 0 | +| 123 | `src/profiles/profiles.adoc` | 0 | 0 | 0 | +| 124 | `src/symbols.adoc` | 0 | 0 | 0 | +| 125 | `src/unpriv.adoc` | 0 | 0 | 0 | +| 126 | `src/unpriv/zama.adoc` | 2 | 2 | 0 | +| 127 | `src/unpriv/zic64b.adoc` | 1 | 1 | 0 | +| 128 | `src/unpriv/ziccamoa.adoc` | 1 | 1 | 0 | +| 129 | `src/unpriv/ziccamoc.adoc` | 1 | 1 | 0 | +| 130 | `src/unpriv/ziccrse.adoc` | 1 | 1 | 0 | +| 131 | `src/unpriv/zihintpause.adoc` | 3 | 3 | 0 | + +## Complete Extracted Parameters List (AsciiDoc) + +> _Showing a randomized sample (up to 10 chunks per parameter class)._ + +| Section | Parameter_Class | Text | Confidence | +|---|---|---|---| +| Preamble > "H" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Return | CSR_controlled | The MRET instruction is used to return from a trap taken into M-mode. MRET first determines what the new privilege mode will be according to the values of MPP and MPV in `mstatus` or `mstatush`, as en... | high | +| Preamble > "Sscofpmf" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control > Supervisor Count Overflow (`scountovf`) Register | CSR_controlled | This extension adds the `scountovf` CSR, a 32-bit read-only register that contains shadow copies of the OF bits in the 29 mhpmevent CSRs (mhpmevent3 - mhpmevent31) - where scountovf bit X corresponds ... | high | +| Preamble > "H" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest Physical Address Translation | CSR_controlled | When `hgatp`.MODE specifies a translation scheme of Sv32x4, Sv39x4, Sv48x4, or Sv57x4, G-stage address translation is a variation on the usual page-based virtual address translation scheme of Sv32, Sv... | high | +| Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Value (`stval`) Register | CSR_controlled | The `stval` CSR is an SXLEN-bit read-write register formatted as shown in .... | high | +| Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Double Trap Control in `sstatus` Register | CSR_controlled | The `mtval2` register is then set to what would be otherwise written into the `mcause` register by the unexpected trap.... | high | +| Preamble > "Smrnmi" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI Operation | CSR_controlled | If the hart encounters an exception while executing in M-mode with the `mnstatus`.NMIE bit clear, the actions taken are the same as if the exception had occurred while `mnstatus`.NMIE were set, except... | high | +| Preamble > "H" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs | CSR_controlled | Some standard supervisor CSRs (`senvcfg`, `scounteren`, and `scontext`, possibly others) have no matching VS CSR.... | high | +| Preamble > "H" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Interrupt (`vsip` and `vsie`) Registers | CSR_controlled | If the Shlcofideleg extension is implemented, `hideleg` bit 13 is writable; otherwise, it is read-only zero.... | high | +| Preamble > Sscounterenw Extension for Counter-Enable Writability, Version 1.0 | CSR_controlled | If the Sscounterenw extension is implemented, then for any `hpmcounter` that is not read-only zero, the corresponding bit in `scounteren` must be writable.... | very_high | +| Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register | CSR_controlled | The Zicbom extension adds the `CBCFE` (Cache Block Clean and Flush instruction Enable) field to `menvcfg`.... | high | +| Preamble > RVWMO Explanatory Material > Why RVWMO? | SW_rule | However, these fences must remain present in the code if compatibility with non-Ztso implementations is desired.... | very_high | +| Preamble > Control and Status Registers (CSRs) > CSR Field Specifications > Reserved Writes Preserve Values, Reads Ignore Values (WPRI) | SW_rule | Software should ignore the values read from these fields, and should preserve the values held in these fields when writing values to other fields of the same register.... | high | +| Preamble > "Smstateen/Ssstateen" Extensions, Version 1.0 | SW_rule | The problem occurs when an extension adds processor state -- usually explicit registers, but possibly other forms of state -- that the main OS or hypervisor is unaware of (and hence won't context-swit... | high | +| Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > I/O Ordering | SW_rule | To enforce ordering between I/O operations and main memory operations, code must use a FENCE with PI, PO, SI, and/or SO, plus PR, PW, SR, and/or SW.... | very_high | +| Preamble > "Svrsw60t59b" Extension for PTE Reserved-for-Software Bits 60-59, Version 1.0 | SW_rule | If the Svrsw60t59b extension is implemented, then bits 60-59 of the page table entries (PTEs) are reserved for use by supervisor software and are ignored by the implementation.... | high | +| Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Background > Memory and Caches | SW_rule | Implementation techniques such as speculative execution or hardware prefetching may cause a given cache to allocate or deallocate a copy of a cache block at any time, provided the corresponding physic... | medium | +| Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Explicit Synchronization (<>) | SW_rule | Using the same examples, the ordering between the loads and stores in the critical section and the "Arbitrary unrelated store" at the end of the code snippet is enforced only by the FENCE RW,W in , no... | medium | +| Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests | SW_rule | In almost all cases, a hardware entropy source must implement appropriate security controls to guarantee unpredictability, prevent leakage, detect attacks, and deny adversarial control over the entrop... | very_high | +| Preamble > "H" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register | SW_rule | When HU=0, all hypervisor instructions cause an illegal-instruction exception in U-mode.... | high | +| Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register | SW_rule | To improve performance, the user-mode extension can define additional instructions to allow user-mode software to return the unit to an initial state or even to turn off the unit.... | high | +| Preamble > Shtvala Extension for Trap Value Reporting, Version 1.0 | non_CSR_parameter | If the Shtvala extension is implemented, `htval` must be written with the faulting guest physical address in all circumstances permitted by the ISA.... | very_high | +| Preamble > "V" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Prestart, Active, Inactive, Body, and Tail Element Definitions | non_CSR_parameter | The active elements can raise exceptions and update the destination vector register group.... | high | +| Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > NIST SP 800-90B | non_CSR_parameter | If NIST SP 800-90B certification is chosen, the entropy source should implement at least the health tests defined in Section 4.4 of cite:[TuBaKe:18]: the repetition count test and adaptive proportion ... | high | +| Preamble > "Smcsrind/Sscsrind" Indirect CSR Access, Version 1.0 > Introduction > Machine-level CSRs | non_CSR_parameter | The `miselect` register may be read-only zero if there are no extensions implemented that utilize it.... | high | +| Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection | non_CSR_parameter | When two-stage address translation is in use, an explicit access may cause both VS-stage and G-stage PTEs to be updated.... | high | +| Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvkg` - Vector GCM/GMAC | non_CSR_parameter | To help avoid side-channel timing attacks, these instructions shall be implemented with data-independent timing.... | very_high | +| Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popret | non_CSR_parameter | switch (rlist){ case 4: \{reglist="ra"; xreglist="x1";} case 5: \{reglist="ra, s0"; xreglist="x1, x8";} case 6: \{reglist="ra, s0-s1"; xreglist="x1, x8-x9";} case 7: \{reglist="ra, s0-s2"; xreglist="x... | very_high | +| Preamble > RV64I Base Integer Instruction Set, Version 2.1 > Load and Store Instructions | non_CSR_parameter | The LW instruction loads a 32-bit value from memory and sign-extends this to 64 bits before storing it in register rd for RV64I.... | high | +| Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.zext.h | non_CSR_parameter | Zbb is also required. // //32-bit equivalent: // // from Zbb... | medium | +| Preamble > "Smctr" Control Transfer Records Extension, Version 1.0 > CSRs > Custom Extensions | non_CSR_parameter | All custom status fields, and standard status fields whose behavior is altered by the custom extension, must revert to standard behavior when the custom bits hold zero.... | very_high | +| Preamble > Introduction > Components of a Profile > RVA Profiles Rationale | unknown | The RISC-V International ISA extension ratification process ensures that all processor vendors have agreed to the specification of a standard extension if present.... | high | +| Preamble > "V" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-1-down Instruction | unknown | If XLEN < SEW, the value is sign-extended to SEW bits.... | high | +| Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model | unknown | The term `acquire` refers to an instruction (or its memory operation) with the acquire-RCpc or acquire-RCsc annotation.... | medium | +| Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Value (`stval`) Register | unknown | the actual faulting instruction * the first ILEN bits of the faulting instruction * the first SXLEN bits of the faulting instruction... | high | +| Preamble > "V" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping for LMUL = 1 | unknown | The element index is given in hexadecimal and is shown placed at the least-significant byte of the stored element.... | high | +| Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Instruction Instance State | unknown | Now, an instruction instance i is said to have fully determined data if for every register read r from regreads, the register writes that r reads from are fully determined.... | high | +| Preamble > "V" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Floating-Point Scalar Move Instructions | unknown | The floating-point scalar read/write instructions transfer a single value between a scalar `f` register and element 0 of a vector register.... | high | +| Preamble > "Zfinx", "Zdinx", "Zhinx", "Zhinxmin" Extensions for Floating-Point in Integer Registers, Version 1.0 > Processing of Narrower Values > Processing of Wider Values | unknown | Use of misaligned (odd-numbered) registers for double-width floating-point operands is reserved.... | high | +| Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesem.[vv,vs] | unknown | foreach (i from egstart to eglen-1) { let keyelem = if suffix "vv" then i else 0; let state : bits(128) = getvelem(vd, EGW=128, i); let rkey : bits(128) = getvelem(vs2, EGW=128, keyelem); let sb : bit... | high | +| Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Counter-Enable (`mcounteren`) Register | unknown | The settings in this register only control accessibility.... | high | diff --git a/tools/llm-extraction/data/evaluation/report_udb_chunker.md b/tools/llm-extraction/data/evaluation/report_udb_chunker.md new file mode 100644 index 0000000000..cb1bb6c43b --- /dev/null +++ b/tools/llm-extraction/data/evaluation/report_udb_chunker.md @@ -0,0 +1,835 @@ +# UDB YAML Chunker Analysis Report + +## Executive Summary +- Total UDB Chunks Produced: 2078 + +## Source Breakdown +- udb_csr_field: 1297 +- udb_csr: 396 +- udb_param: 223 +- udb_ext: 162 + +## Parameter Class Summary +- CSR_controlled: 1693 +- non_CSR_parameter: 385 + +## Parameter Type Summary +- csr_field: 1297 +- csr_register: 396 +- extension: 162 +- binary: 122 +- enum: 65 +- range: 33 +- unknown: 3 + +## Per-file Chunk Generation Analysis +| S.No | Source File | Chunks Generated | +|---|---|---| +| 1 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/S/scounteren.yaml` | 33 | +| 2 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/hcounteren.yaml` | 33 | +| 3 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/mcounteren.yaml` | 33 | +| 4 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zicntr/mcountinhibit.yaml` | 32 | +| 5 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Sscofpmf/scountovf.yaml` | 30 | +| 6 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstatus.yaml` | 25 | +| 7 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smctr/mctrctl.yaml` | 23 | +| 8 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smctr/sctrctl.yaml` | 21 | +| 9 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smctr/vsctrctl.yaml` | 21 | +| 10 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hedeleg.yaml` | 20 | +| 11 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/medeleg.yaml` | 20 | +| 12 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/dcsr.yaml` | 19 | +| 13 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/misa.yaml` | 15 | +| 14 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstateen0.yaml` | 13 | +| 15 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/vsstatus.yaml` | 12 | +| 16 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mideleg.yaml` | 12 | +| 17 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/sstatus.yaml` | 12 | +| 18 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mip.yaml` | 12 | +| 19 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mie.yaml` | 12 | +| 20 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hstateen0.yaml` | 11 | +| 21 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hstatus.yaml` | 11 | +| 22 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstateen0h.yaml` | 10 | +| 23 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/menvcfg.yaml` | 9 | +| 24 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg8.yaml` | 9 | +| 25 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg4.yaml` | 9 | +| 26 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg6.yaml` | 9 | +| 27 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/henvcfg.yaml` | 9 | +| 28 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg2.yaml` | 9 | +| 29 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg14.yaml` | 9 | +| 30 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg12.yaml` | 9 | +| 31 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg10.yaml` | 9 | +| 32 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg0.yaml` | 9 | +| 33 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent18.yaml` | 8 | +| 34 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent16h.yaml` | 8 | +| 35 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent17.yaml` | 8 | +| 36 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent17h.yaml` | 8 | +| 37 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent19.yaml` | 8 | +| 38 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent18h.yaml` | 8 | +| 39 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent15h.yaml` | 8 | +| 40 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent19h.yaml` | 8 | +| 41 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent20.yaml` | 8 | +| 42 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent20h.yaml` | 8 | +| 43 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent16.yaml` | 8 | +| 44 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent14h.yaml` | 8 | +| 45 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent15.yaml` | 8 | +| 46 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent14.yaml` | 8 | +| 47 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent13h.yaml` | 8 | +| 48 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent13.yaml` | 8 | +| 49 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent12h.yaml` | 8 | +| 50 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent12.yaml` | 8 | +| 51 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent11h.yaml` | 8 | +| 52 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent11.yaml` | 8 | +| 53 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent10h.yaml` | 8 | +| 54 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent10.yaml` | 8 | +| 55 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent21h.yaml` | 8 | +| 56 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent21.yaml` | 8 | +| 57 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent24h.yaml` | 8 | +| 58 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent22.yaml` | 8 | +| 59 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent6h.yaml` | 8 | +| 60 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent3h.yaml` | 8 | +| 61 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent4.yaml` | 8 | +| 62 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent22h.yaml` | 8 | +| 63 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent5.yaml` | 8 | +| 64 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent5h.yaml` | 8 | +| 65 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent6.yaml` | 8 | +| 66 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent7.yaml` | 8 | +| 67 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent31.yaml` | 8 | +| 68 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent7h.yaml` | 8 | +| 69 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent8.yaml` | 8 | +| 70 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent8h.yaml` | 8 | +| 71 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent9.yaml` | 8 | +| 72 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent9h.yaml` | 8 | +| 73 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hstateen0h.yaml` | 8 | +| 74 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent31h.yaml` | 8 | +| 75 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent4h.yaml` | 8 | +| 76 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent30h.yaml` | 8 | +| 77 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent27.yaml` | 8 | +| 78 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent24.yaml` | 8 | +| 79 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent23.yaml` | 8 | +| 80 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent30.yaml` | 8 | +| 81 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent25.yaml` | 8 | +| 82 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent25h.yaml` | 8 | +| 83 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent26h.yaml` | 8 | +| 84 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent26.yaml` | 8 | +| 85 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent27h.yaml` | 8 | +| 86 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent28.yaml` | 8 | +| 87 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent28h.yaml` | 8 | +| 88 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent29.yaml` | 8 | +| 89 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent29h.yaml` | 8 | +| 90 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent3.yaml` | 8 | +| 91 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent23h.yaml` | 8 | +| 92 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/F/fcsr.yaml` | 7 | +| 93 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/V/vtype.yaml` | 6 | +| 94 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/senvcfg.yaml` | 6 | +| 95 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstatush.yaml` | 6 | +| 96 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcntrpmf/mcyclecfg.yaml` | 6 | +| 97 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/F/fflags.yaml` | 6 | +| 98 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcntrpmf/minstretcfg.yaml` | 6 | +| 99 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcntrpmf/mcyclecfgh.yaml` | 6 | +| 100 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcntrpmf/minstretcfgh.yaml` | 6 | +| 101 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smrnmi/mnstatus.yaml` | 5 | +| 102 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/sie.yaml` | 5 | +| 103 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg1.yaml` | 5 | +| 104 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/sip.yaml` | 5 | +| 105 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg9.yaml` | 5 | +| 106 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg7.yaml` | 5 | +| 107 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg5.yaml` | 5 | +| 108 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg3.yaml` | 5 | +| 109 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg15.yaml` | 5 | +| 110 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg13.yaml` | 5 | +| 111 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg11.yaml` | 5 | +| 112 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/hgatp.yaml` | 4 | +| 113 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/vsatp.yaml` | 4 | +| 114 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/menvcfgh.yaml` | 4 | +| 115 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/satp.yaml` | 4 | +| 116 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/tdata1.yaml` | 4 | +| 117 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/sstateen0.yaml` | 4 | +| 118 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/henvcfgh.yaml` | 4 | +| 119 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mcause.yaml` | 3 | +| 120 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/vstvec.yaml` | 3 | +| 121 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/vscause.yaml` | 3 | +| 122 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mtvec.yaml` | 3 | +| 123 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mvendorid.yaml` | 3 | +| 124 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/stvec.yaml` | 3 | +| 125 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/scause.yaml` | 3 | +| 126 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/jvt.yaml` | 3 | +| 127 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/V/vcsr.yaml` | 3 | +| 128 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smrnmi/mncause.yaml` | 3 | +| 129 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Ssqosid/srmcfg.yaml` | 3 | +| 130 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/V/vlenb.yaml` | 2 | +| 131 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr7.yaml` | 2 | +| 132 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter15h.yaml` | 2 | +| 133 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter16.yaml` | 2 | +| 134 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter16h.yaml` | 2 | +| 135 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter17.yaml` | 2 | +| 136 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter17h.yaml` | 2 | +| 137 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcsrind/vsiselect.yaml` | 2 | +| 138 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter18.yaml` | 2 | +| 139 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr9.yaml` | 2 | +| 140 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr8.yaml` | 2 | +| 141 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcsrind/vsireg6.yaml` | 2 | +| 142 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcsrind/vsireg5.yaml` | 2 | +| 143 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter18h.yaml` | 2 | +| 144 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcsrind/sireg2.yaml` | 2 | +| 145 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcsrind/vsireg4.yaml` | 2 | +| 146 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcsrind/vsireg3.yaml` | 2 | +| 147 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcsrind/vsireg2.yaml` | 2 | +| 148 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcsrind/vsireg.yaml` | 2 | +| 149 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcsrind/siselect.yaml` | 2 | +| 150 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr63.yaml` | 2 | +| 151 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter19.yaml` | 2 | +| 152 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr62.yaml` | 2 | +| 153 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter19h.yaml` | 2 | +| 154 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcsrind/sireg6.yaml` | 2 | +| 155 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcsrind/sireg3.yaml` | 2 | +| 156 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter14h.yaml` | 2 | +| 157 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter15.yaml` | 2 | +| 158 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/V/vstart.yaml` | 2 | +| 159 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcsrind/mireg4.yaml` | 2 | +| 160 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/V/vl.yaml` | 2 | +| 161 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcsrind/mireg3.yaml` | 2 | +| 162 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcsrind/mireg2.yaml` | 2 | +| 163 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/V/vxrm.yaml` | 2 | +| 164 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcsrind/mireg.yaml` | 2 | +| 165 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/V/vxsat.yaml` | 2 | +| 166 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcsrind/mireg5.yaml` | 2 | +| 167 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter10.yaml` | 2 | +| 168 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcsrind/mireg6.yaml` | 2 | +| 169 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter10h.yaml` | 2 | +| 170 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcsrind/miselect.yaml` | 2 | +| 171 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcsrind/sireg5.yaml` | 2 | +| 172 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter11.yaml` | 2 | +| 173 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter11h.yaml` | 2 | +| 174 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smrnmi/mnscratch.yaml` | 2 | +| 175 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smrnmi/mnepc.yaml` | 2 | +| 176 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter12.yaml` | 2 | +| 177 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter12h.yaml` | 2 | +| 178 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter13.yaml` | 2 | +| 179 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcsrind/sireg.yaml` | 2 | +| 180 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter13h.yaml` | 2 | +| 181 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter14.yaml` | 2 | +| 182 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcsrind/sireg4.yaml` | 2 | +| 183 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter5.yaml` | 2 | +| 184 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter20.yaml` | 2 | +| 185 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter26.yaml` | 2 | +| 186 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter31.yaml` | 2 | +| 187 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter30h.yaml` | 2 | +| 188 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter30.yaml` | 2 | +| 189 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter3.yaml` | 2 | +| 190 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter29h.yaml` | 2 | +| 191 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter29.yaml` | 2 | +| 192 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter28h.yaml` | 2 | +| 193 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter28.yaml` | 2 | +| 194 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter27h.yaml` | 2 | +| 195 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter27.yaml` | 2 | +| 196 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter26h.yaml` | 2 | +| 197 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter25h.yaml` | 2 | +| 198 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter3h.yaml` | 2 | +| 199 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter25.yaml` | 2 | +| 200 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter24h.yaml` | 2 | +| 201 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter24.yaml` | 2 | +| 202 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter23h.yaml` | 2 | +| 203 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter23.yaml` | 2 | +| 204 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter22h.yaml` | 2 | +| 205 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter22.yaml` | 2 | +| 206 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter21h.yaml` | 2 | +| 207 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter21.yaml` | 2 | +| 208 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter20h.yaml` | 2 | +| 209 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter20.yaml` | 2 | +| 210 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter31h.yaml` | 2 | +| 211 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter4.yaml` | 2 | +| 212 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter19.yaml` | 2 | +| 213 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/dpc.yaml` | 2 | +| 214 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/instreth.yaml` | 2 | +| 215 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/instret.yaml` | 2 | +| 216 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hstateen3h.yaml` | 2 | +| 217 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hstateen3.yaml` | 2 | +| 218 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hstateen2h.yaml` | 2 | +| 219 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hstateen2.yaml` | 2 | +| 220 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hstateen1h.yaml` | 2 | +| 221 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hstateen1.yaml` | 2 | +| 222 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hcontext.yaml` | 2 | +| 223 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/dscratch1.yaml` | 2 | +| 224 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/dscratch0.yaml` | 2 | +| 225 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/cycleh.yaml` | 2 | +| 226 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter4h.yaml` | 2 | +| 227 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/cycle.yaml` | 2 | +| 228 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter9h.yaml` | 2 | +| 229 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter9.yaml` | 2 | +| 230 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter8h.yaml` | 2 | +| 231 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter8.yaml` | 2 | +| 232 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter7h.yaml` | 2 | +| 233 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter7.yaml` | 2 | +| 234 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter6h.yaml` | 2 | +| 235 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter6.yaml` | 2 | +| 236 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter5h.yaml` | 2 | +| 237 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter5.yaml` | 2 | +| 238 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter19h.yaml` | 2 | +| 239 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter18h.yaml` | 2 | +| 240 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter20h.yaml` | 2 | +| 241 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter27.yaml` | 2 | +| 242 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter3h.yaml` | 2 | +| 243 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter31h.yaml` | 2 | +| 244 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter31.yaml` | 2 | +| 245 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter30h.yaml` | 2 | +| 246 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter30.yaml` | 2 | +| 247 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter3.yaml` | 2 | +| 248 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter29h.yaml` | 2 | +| 249 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter29.yaml` | 2 | +| 250 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter28h.yaml` | 2 | +| 251 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter28.yaml` | 2 | +| 252 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter27h.yaml` | 2 | +| 253 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter26h.yaml` | 2 | +| 254 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter4h.yaml` | 2 | +| 255 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter26.yaml` | 2 | +| 256 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter25h.yaml` | 2 | +| 257 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter25.yaml` | 2 | +| 258 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mconfigptr.yaml` | 2 | +| 259 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter24.yaml` | 2 | +| 260 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter23h.yaml` | 2 | +| 261 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter23.yaml` | 2 | +| 262 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter22h.yaml` | 2 | +| 263 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter22.yaml` | 2 | +| 264 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter21h.yaml` | 2 | +| 265 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter21.yaml` | 2 | +| 266 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter4.yaml` | 2 | +| 267 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr60.yaml` | 2 | +| 268 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter18.yaml` | 2 | +| 269 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter12.yaml` | 2 | +| 270 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter17h.yaml` | 2 | +| 271 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter17.yaml` | 2 | +| 272 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter16h.yaml` | 2 | +| 273 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter16.yaml` | 2 | +| 274 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter15h.yaml` | 2 | +| 275 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter15.yaml` | 2 | +| 276 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter14h.yaml` | 2 | +| 277 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter14.yaml` | 2 | +| 278 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter13h.yaml` | 2 | +| 279 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter13.yaml` | 2 | +| 280 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter12h.yaml` | 2 | +| 281 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter11h.yaml` | 2 | +| 282 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter5h.yaml` | 2 | +| 283 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter11.yaml` | 2 | +| 284 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter10h.yaml` | 2 | +| 285 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter10.yaml` | 2 | +| 286 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter9h.yaml` | 2 | +| 287 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter9.yaml` | 2 | +| 288 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter8h.yaml` | 2 | +| 289 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter8.yaml` | 2 | +| 290 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter7h.yaml` | 2 | +| 291 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter7.yaml` | 2 | +| 292 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter6h.yaml` | 2 | +| 293 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter6.yaml` | 2 | +| 294 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr61.yaml` | 2 | +| 295 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter24h.yaml` | 2 | +| 296 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr6.yaml` | 2 | +| 297 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mscratch.yaml` | 2 | +| 298 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/minstreth.yaml` | 2 | +| 299 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/minstret.yaml` | 2 | +| 300 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mimpid.yaml` | 2 | +| 301 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mhartid.yaml` | 2 | +| 302 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mepc.yaml` | 2 | +| 303 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mcycleh.yaml` | 2 | +| 304 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mcycle.yaml` | 2 | +| 305 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mcontext.yaml` | 2 | +| 306 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/F/frm.yaml` | 2 | +| 307 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/htimedelta.yaml` | 2 | +| 308 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/htimedeltah.yaml` | 2 | +| 309 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/htinst.yaml` | 2 | +| 310 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/htval.yaml` | 2 | +| 311 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/mtinst.yaml` | 2 | +| 312 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/mtval2.yaml` | 2 | +| 313 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr0.yaml` | 2 | +| 314 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr1.yaml` | 2 | +| 315 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr10.yaml` | 2 | +| 316 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr11.yaml` | 2 | +| 317 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr12.yaml` | 2 | +| 318 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr13.yaml` | 2 | +| 319 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mscontext.yaml` | 2 | +| 320 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstateen1.yaml` | 2 | +| 321 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr15.yaml` | 2 | +| 322 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstateen1h.yaml` | 2 | +| 323 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr59.yaml` | 2 | +| 324 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/vstval.yaml` | 2 | +| 325 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/vsepc.yaml` | 2 | +| 326 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/tselect.yaml` | 2 | +| 327 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/timeh.yaml` | 2 | +| 328 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/time.yaml` | 2 | +| 329 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/tdata3.yaml` | 2 | +| 330 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/tdata2.yaml` | 2 | +| 331 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/stval.yaml` | 2 | +| 332 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/sstateen3.yaml` | 2 | +| 333 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/sstateen2.yaml` | 2 | +| 334 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/sstateen1.yaml` | 2 | +| 335 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/ssp.yaml` | 2 | +| 336 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/sscratch.yaml` | 2 | +| 337 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/sepc.yaml` | 2 | +| 338 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/scontext.yaml` | 2 | +| 339 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mtval.yaml` | 2 | +| 340 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstateen3h.yaml` | 2 | +| 341 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstateen3.yaml` | 2 | +| 342 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstateen2h.yaml` | 2 | +| 343 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstateen2.yaml` | 2 | +| 344 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr14.yaml` | 2 | +| 345 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr45.yaml` | 2 | +| 346 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr16.yaml` | 2 | +| 347 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr38.yaml` | 2 | +| 348 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr4.yaml` | 2 | +| 349 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr40.yaml` | 2 | +| 350 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr41.yaml` | 2 | +| 351 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr42.yaml` | 2 | +| 352 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr43.yaml` | 2 | +| 353 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr44.yaml` | 2 | +| 354 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/marchid.yaml` | 2 | +| 355 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr46.yaml` | 2 | +| 356 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr47.yaml` | 2 | +| 357 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr48.yaml` | 2 | +| 358 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr49.yaml` | 2 | +| 359 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr5.yaml` | 2 | +| 360 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr50.yaml` | 2 | +| 361 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr51.yaml` | 2 | +| 362 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr53.yaml` | 2 | +| 363 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr54.yaml` | 2 | +| 364 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr55.yaml` | 2 | +| 365 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr56.yaml` | 2 | +| 366 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr57.yaml` | 2 | +| 367 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr17.yaml` | 2 | +| 368 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr58.yaml` | 2 | +| 369 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr39.yaml` | 2 | +| 370 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr52.yaml` | 2 | +| 371 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr22.yaml` | 2 | +| 372 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr29.yaml` | 2 | +| 373 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr18.yaml` | 2 | +| 374 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr2.yaml` | 2 | +| 375 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr20.yaml` | 2 | +| 376 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr21.yaml` | 2 | +| 377 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr23.yaml` | 2 | +| 378 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr24.yaml` | 2 | +| 379 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr25.yaml` | 2 | +| 380 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr26.yaml` | 2 | +| 381 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr27.yaml` | 2 | +| 382 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr28.yaml` | 2 | +| 383 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr19.yaml` | 2 | +| 384 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr3.yaml` | 2 | +| 385 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr33.yaml` | 2 | +| 386 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr30.yaml` | 2 | +| 387 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr36.yaml` | 2 | +| 388 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr35.yaml` | 2 | +| 389 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr34.yaml` | 2 | +| 390 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr37.yaml` | 2 | +| 391 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr32.yaml` | 2 | +| 392 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr31.yaml` | 2 | +| 393 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zicboz.yaml` | 1 | +| 394 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zicntr.yaml` | 1 | +| 395 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Ziccamoa.yaml` | 1 | +| 396 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Ziccamoc.yaml` | 1 | +| 397 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Ziccif.yaml` | 1 | +| 398 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zicclsm.yaml` | 1 | +| 399 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Ziccrse.yaml` | 1 | +| 400 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zicfilp.yaml` | 1 | +| 401 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zicfiss.yaml` | 1 | +| 402 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zicond.yaml` | 1 | +| 403 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zilsd.yaml` | 1 | +| 404 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zicsr.yaml` | 1 | +| 405 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zifencei.yaml` | 1 | +| 406 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zihintntl.yaml` | 1 | +| 407 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zimop.yaml` | 1 | +| 408 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zihintpause.yaml` | 1 | +| 409 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zihpm.yaml` | 1 | +| 410 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zcb.yaml` | 1 | +| 411 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zdinx.yaml` | 1 | +| 412 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zicbop.yaml` | 1 | +| 413 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zicbom.yaml` | 1 | +| 414 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zca.yaml` | 1 | +| 415 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zkn.yaml` | 1 | +| 416 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zce.yaml` | 1 | +| 417 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zcf.yaml` | 1 | +| 418 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zclsd.yaml` | 1 | +| 419 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zcmop.yaml` | 1 | +| 420 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zcmp.yaml` | 1 | +| 421 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zcmt.yaml` | 1 | +| 422 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zcd.yaml` | 1 | +| 423 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zfa.yaml` | 1 | +| 424 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zfbfmin.yaml` | 1 | +| 425 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zfh.yaml` | 1 | +| 426 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zfhmin.yaml` | 1 | +| 427 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zfinx.yaml` | 1 | +| 428 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zhinx.yaml` | 1 | +| 429 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zhinxmin.yaml` | 1 | +| 430 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zic64b.yaml` | 1 | +| 431 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zk.yaml` | 1 | +| 432 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zvkb.yaml` | 1 | +| 433 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zknd.yaml` | 1 | +| 434 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zbkx.yaml` | 1 | +| 435 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zvkn.yaml` | 1 | +| 436 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zvknc.yaml` | 1 | +| 437 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zvkned.yaml` | 1 | +| 438 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zvkng.yaml` | 1 | +| 439 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zvknha.yaml` | 1 | +| 440 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zvknhb.yaml` | 1 | +| 441 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zvks.yaml` | 1 | +| 442 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zvksc.yaml` | 1 | +| 443 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zvksed.yaml` | 1 | +| 444 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zvksg.yaml` | 1 | +| 445 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zvksh.yaml` | 1 | +| 446 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zvkt.yaml` | 1 | +| 447 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zvl1024b.yaml` | 1 | +| 448 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zvl128b.yaml` | 1 | +| 449 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zvl256b.yaml` | 1 | +| 450 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zvl32b.yaml` | 1 | +| 451 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zvl512b.yaml` | 1 | +| 452 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zvkg.yaml` | 1 | +| 453 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zvfhmin.yaml` | 1 | +| 454 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zkne.yaml` | 1 | +| 455 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zvfh.yaml` | 1 | +| 456 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zknh.yaml` | 1 | +| 457 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zkr.yaml` | 1 | +| 458 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zks.yaml` | 1 | +| 459 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zksed.yaml` | 1 | +| 460 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zksh.yaml` | 1 | +| 461 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zkt.yaml` | 1 | +| 462 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zmmul.yaml` | 1 | +| 463 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Ztso.yaml` | 1 | +| 464 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zvbb.yaml` | 1 | +| 465 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zvbc.yaml` | 1 | +| 466 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zve32f.yaml` | 1 | +| 467 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zve32x.yaml` | 1 | +| 468 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zve64d.yaml` | 1 | +| 469 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zve64f.yaml` | 1 | +| 470 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zve64x.yaml` | 1 | +| 471 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zvfbfmin.yaml` | 1 | +| 472 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zvfbfwma.yaml` | 1 | +| 473 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zbs.yaml` | 1 | +| 474 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Svade.yaml` | 1 | +| 475 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zbkc.yaml` | 1 | +| 476 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Shvsatpa.yaml` | 1 | +| 477 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Shvstvecd.yaml` | 1 | +| 478 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Sm.yaml` | 1 | +| 479 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Smaia.yaml` | 1 | +| 480 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Smcdeleg.yaml` | 1 | +| 481 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Smcntrpmf.yaml` | 1 | +| 482 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Smcsrind.yaml` | 1 | +| 483 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Smctr.yaml` | 1 | +| 484 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Smdbltrp.yaml` | 1 | +| 485 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Smepmp.yaml` | 1 | +| 486 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Smmpm.yaml` | 1 | +| 487 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Smnpm.yaml` | 1 | +| 488 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Smrnmi.yaml` | 1 | +| 489 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Smstateen.yaml` | 1 | +| 490 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Ssccfg.yaml` | 1 | +| 491 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Ssccptr.yaml` | 1 | +| 492 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Sscofpmf.yaml` | 1 | +| 493 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Sscounterenw.yaml` | 1 | +| 494 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Shvstvala.yaml` | 1 | +| 495 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Shtvala.yaml` | 1 | +| 496 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zbkb.yaml` | 1 | +| 497 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Shgatpa.yaml` | 1 | +| 498 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/medelegh.yaml` | 1 | +| 499 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mseccfg.yaml` | 1 | +| 500 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mseccfgh.yaml` | 1 | +| 501 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/A.yaml` | 1 | +| 502 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/B.yaml` | 1 | +| 503 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/C.yaml` | 1 | +| 504 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/D.yaml` | 1 | +| 505 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/F.yaml` | 1 | +| 506 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/H.yaml` | 1 | +| 507 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/I.yaml` | 1 | +| 508 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/M.yaml` | 1 | +| 509 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Q.yaml` | 1 | +| 510 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/S.yaml` | 1 | +| 511 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Sdext.yaml` | 1 | +| 512 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Sdtrig.yaml` | 1 | +| 513 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Sha.yaml` | 1 | +| 514 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Shcounterenw.yaml` | 1 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`/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Za64rs.yaml` | 1 | +| 526 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zaamo.yaml` | 1 | +| 527 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zabha.yaml` | 1 | +| 528 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zacas.yaml` | 1 | +| 529 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zalasr.yaml` | 1 | +| 530 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zalrsc.yaml` | 1 | +| 531 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zama16b.yaml` | 1 | +| 532 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zawrs.yaml` | 1 | +| 533 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zba.yaml` | 1 | +| 534 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zbb.yaml` | 1 | +| 535 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zbc.yaml` | 1 | +| 536 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Svnapot.yaml` | 1 | +| 537 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Svinval.yaml` | 1 | +| 538 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Svbare.yaml` | 1 | +| 539 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Sstvecv.yaml` | 1 | +| 540 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Sspm.yaml` | 1 | +| 541 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Ssqosid.yaml` | 1 | +| 542 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Ssstateen.yaml` | 1 | +| 543 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Ssstrict.yaml` | 1 | +| 544 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Sstc.yaml` | 1 | +| 545 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Sstvala.yaml` | 1 | +| 546 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Sstvecd.yaml` | 1 | +| 547 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Ssu32xl.yaml` | 1 | +| 548 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Svadu.yaml` | 1 | +| 549 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Ssu64xl.yaml` | 1 | +| 550 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Ssube.yaml` | 1 | +| 551 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Supm.yaml` | 1 | +| 552 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Sv32.yaml` | 1 | +| 553 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Sv39.yaml` | 1 | +| 554 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Sv48.yaml` | 1 | +| 555 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Sv57.yaml` | 1 | +| 556 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Ssaia.yaml` | 1 | +| 557 | `std/isa/param/ARCH_ID_VALUE.yaml` | 1 | +| 558 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hedelegh.yaml` | 1 | +| 559 | `std/isa/param/ASID_WIDTH.yaml` | 1 | +| 560 | `std/isa/param/MUTABLE_MISA_B.yaml` | 1 | +| 561 | `std/isa/param/MUTABLE_MISA_A.yaml` | 1 | +| 562 | `std/isa/param/MTVEC_MODES.yaml` | 1 | +| 563 | `std/isa/param/MTVEC_ILLEGAL_WRITE_BEHAVIOR.yaml` | 1 | +| 564 | `std/isa/param/MTVEC_BASE_ALIGNMENT_VECTORED.yaml` | 1 | +| 565 | `std/isa/param/MTVEC_BASE_ALIGNMENT_DIRECT.yaml` | 1 | +| 566 | `std/isa/param/MTVEC_ACCESS.yaml` | 1 | +| 567 | `std/isa/param/MTVAL_WIDTH.yaml` | 1 | +| 568 | `std/isa/param/MSTATUS_VS_LEGAL_VALUES.yaml` | 1 | +| 569 | `std/isa/param/MSTATUS_TVM_IMPLEMENTED.yaml` | 1 | +| 570 | `std/isa/param/MSTATUS_FS_LEGAL_VALUES.yaml` | 1 | +| 571 | `std/isa/param/MSTATEEN_JVT_TYPE.yaml` | 1 | +| 572 | `std/isa/param/MSTATEEN_IMSIC_TYPE.yaml` | 1 | +| 573 | `std/isa/param/MSTATEEN_ENVCFG_TYPE.yaml` | 1 | +| 574 | `std/isa/param/MSTATEEN_CSRIND_TYPE.yaml` | 1 | +| 575 | `std/isa/param/MSTATEEN_CONTEXT_TYPE.yaml` | 1 | +| 576 | `std/isa/param/MSTATEEN_AIA_TYPE.yaml` | 1 | +| 577 | `std/isa/param/MISA_CSR_IMPLEMENTED.yaml` | 1 | +| 578 | `std/isa/param/MISALIGNED_SPLIT_STRATEGY.yaml` | 1 | +| 579 | `std/isa/param/MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE.yaml` | 1 | +| 580 | `std/isa/param/MISALIGNED_LDST_EXCEPTION_PRIORITY.yaml` | 1 | +| 581 | `std/isa/param/MISALIGNED_LDST.yaml` | 1 | +| 582 | `std/isa/param/MISALIGNED_AMO.yaml` | 1 | +| 583 | `std/isa/param/MIMPID_IMPLEMENTED.yaml` | 1 | +| 584 | `std/isa/param/MCTRCTL_TRETINH_IMPLEMENTED.yaml` | 1 | +| 585 | `std/isa/param/MUTABLE_MISA_C.yaml` | 1 | +| 586 | `std/isa/param/MUTABLE_MISA_D.yaml` | 1 | +| 587 | `std/isa/param/MUTABLE_MISA_F.yaml` | 1 | +| 588 | `std/isa/param/PMP_GRANULARITY.yaml` | 1 | +| 589 | `std/isa/param/REPORT_ENCODING_IN_VSTVAL_ON_ILLEGAL_INSTRUCTION.yaml` | 1 | +| 590 | `std/isa/param/REPORT_ENCODING_IN_STVAL_ON_ILLEGAL_INSTRUCTION.yaml` | 1 | +| 591 | `std/isa/param/REPORT_ENCODING_IN_MTVAL_ON_ILLEGAL_INSTRUCTION.yaml` | 1 | +| 592 | `std/isa/param/REPORT_CAUSE_IN_VSTVAL_ON_SHADOW_STACK_SOFTWARE_CHECK.yaml` | 1 | +| 593 | `std/isa/param/REPORT_CAUSE_IN_VSTVAL_ON_LANDING_PAD_SOFTWARE_CHECK.yaml` | 1 | +| 594 | `std/isa/param/REPORT_CAUSE_IN_STVAL_ON_SHADOW_STACK_SOFTWARE_CHECK.yaml` | 1 | +| 595 | `std/isa/param/REPORT_CAUSE_IN_STVAL_ON_LANDING_PAD_SOFTWARE_CHECK.yaml` | 1 | +| 596 | `std/isa/param/REPORT_CAUSE_IN_MTVAL_ON_SHADOW_STACK_SOFTWARE_CHECK.yaml` | 1 | +| 597 | `std/isa/param/REPORT_CAUSE_IN_MTVAL_ON_LANDING_PAD_SOFTWARE_CHECK.yaml` | 1 | +| 598 | `std/isa/param/RCID_WIDTH.yaml` | 1 | +| 599 | `std/isa/param/PRECISE_SYNCHRONOUS_EXCEPTIONS.yaml` | 1 | +| 600 | `std/isa/param/PMLEN.yaml` | 1 | +| 601 | `std/isa/param/MUTABLE_MISA_H.yaml` | 1 | +| 602 | `std/isa/param/PMA_GRANULARITY.yaml` | 1 | +| 603 | `std/isa/param/PHYS_ADDR_WIDTH.yaml` | 1 | +| 604 | `std/isa/param/NUM_PMP_ENTRIES.yaml` | 1 | +| 605 | `std/isa/param/NUM_EXTERNAL_GUEST_INTERRUPTS.yaml` | 1 | +| 606 | `std/isa/param/M_MODE_ENDIANNESS.yaml` | 1 | +| 607 | `std/isa/param/MXLEN.yaml` | 1 | +| 608 | `std/isa/param/MUTABLE_MISA_V.yaml` | 1 | +| 609 | `std/isa/param/MUTABLE_MISA_U.yaml` | 1 | +| 610 | `std/isa/param/MUTABLE_MISA_S.yaml` | 1 | +| 611 | `std/isa/param/MUTABLE_MISA_Q.yaml` | 1 | +| 612 | `std/isa/param/MUTABLE_MISA_M.yaml` | 1 | +| 613 | `std/isa/param/MCTRCTL_TKBRINH_IMPLEMENTED.yaml` | 1 | +| 614 | `std/isa/param/MCTRCTL_STE_IMPLEMENTED.yaml` | 1 | +| 615 | `std/isa/param/MCTRCTL_RETINH_IMPLEMENTED.yaml` | 1 | +| 616 | `std/isa/param/GSTAGE_MODE_BARE.yaml` | 1 | +| 617 | `std/isa/param/HW_MSTATUS_FS_DIRTY_UPDATE.yaml` | 1 | +| 618 | `std/isa/param/HSTATEEN_JVT_TYPE.yaml` | 1 | +| 619 | `std/isa/param/HSTATEEN_IMSIC_TYPE.yaml` | 1 | +| 620 | `std/isa/param/HSTATEEN_ENVCFG_TYPE.yaml` | 1 | +| 621 | `std/isa/param/HSTATEEN_CSRIND_TYPE.yaml` | 1 | +| 622 | `std/isa/param/HSTATEEN_CONTEXT_TYPE.yaml` | 1 | +| 623 | `std/isa/param/HSTATEEN_AIA_TYPE.yaml` | 1 | +| 624 | `std/isa/param/HPM_EVENTS.yaml` | 1 | +| 625 | `std/isa/param/HPM_COUNTER_EN.yaml` | 1 | +| 626 | `std/isa/param/HCOUNTENABLE_EN.yaml` | 1 | +| 627 | `std/isa/param/HCONTEXT_AVAILABLE.yaml` | 1 | +| 628 | `std/isa/param/FORCE_UPGRADE_CBO_INVAL_TO_FLUSH.yaml` | 1 | +| 629 | `std/isa/param/IGNORE_INVALID_VSATP_MODE_WRITES_WHEN_V_EQ_ZERO.yaml` | 1 | +| 630 | `std/isa/param/FOLLOW_VTYPE_RESET_RECOMMENDATION.yaml` | 1 | +| 631 | `std/isa/param/ELEN.yaml` | 1 | +| 632 | `std/isa/param/DCSR_STOPTIME_TYPE.yaml` | 1 | +| 633 | `std/isa/param/DCSR_STOPCOUNT_TYPE.yaml` | 1 | +| 634 | `std/isa/param/DCSR_STEPIE_TYPE.yaml` | 1 | +| 635 | `std/isa/param/DCSR_MPRVEN_TYPE.yaml` | 1 | +| 636 | `std/isa/param/DBG_SCONTEXT_WIDTH.yaml` | 1 | +| 637 | `std/isa/param/DBG_HCONTEXT_WIDTH.yaml` | 1 | +| 638 | `std/isa/param/COUNTINHIBIT_EN.yaml` | 1 | +| 639 | `std/isa/param/CONFIG_PTR_ADDRESS.yaml` | 1 | +| 640 | `std/isa/param/CACHE_BLOCK_SIZE.yaml` | 1 | +| 641 | `std/isa/param/HW_MSTATUS_VS_DIRTY_UPDATE.yaml` | 1 | +| 642 | `std/isa/param/IMPRECISE_VECTOR_TRAP_SETTABLE.yaml` | 1 | +| 643 | `std/isa/param/MCTRCTL_RASEMU_IMPLEMENTED.yaml` | 1 | +| 644 | `std/isa/param/MCTRCTL_CORSWAPINH_IMPLEMENTED.yaml` | 1 | +| 645 | `std/isa/param/MCTRCTL_NTBREN_IMPLEMENTED.yaml` | 1 | +| 646 | `std/isa/param/MCTRCTL_MTE_IMPLEMENTED.yaml` | 1 | +| 647 | `std/isa/param/MCTRCTL_INTRINH_IMPLEMENTED.yaml` | 1 | +| 648 | `std/isa/param/MCTRCTL_INDLJMPINH_IMPLEMENTED.yaml` | 1 | +| 649 | `std/isa/param/MCTRCTL_INDJMPINH_IMPLEMENTED.yaml` | 1 | +| 650 | `std/isa/param/MCTRCTL_INDCALLINH_IMPLEMENTED.yaml` | 1 | +| 651 | `std/isa/param/MCTRCTL_EXCINH_IMPLEMENTED.yaml` | 1 | +| 652 | `std/isa/param/MCTRCTL_DIRLJMPINH_IMPLEMENTED.yaml` | 1 | +| 653 | `std/isa/param/MCTRCTL_DIRJMPINH_IMPLEMENTED.yaml` | 1 | +| 654 | `std/isa/param/MCTRCTL_DIRCALLINH_IMPLEMENTED.yaml` | 1 | +| 655 | `std/isa/param/MCTRCTL_CUSTOM_IMPLEMENTED.yaml` | 1 | +| 656 | `std/isa/param/MCOUNTENABLE_EN.yaml` | 1 | +| 657 | `std/isa/param/IMP_ID_VALUE.yaml` | 1 | +| 658 | `std/isa/param/MCONTEXT_AVAILABLE.yaml` | 1 | +| 659 | `std/isa/param/MCID_WIDTH.yaml` | 1 | +| 660 | `std/isa/param/MARCHID_IMPLEMENTED.yaml` | 1 | +| 661 | `std/isa/param/LRSC_RESERVATION_STRATEGY.yaml` | 1 | +| 662 | `std/isa/param/LRSC_MISALIGNED_BEHAVIOR.yaml` | 1 | +| 663 | `std/isa/param/LRSC_FAIL_ON_VA_SYNONYM.yaml` | 1 | +| 664 | `std/isa/param/LRSC_FAIL_ON_NON_EXACT_LRSC.yaml` | 1 | +| 665 | `std/isa/param/LEGAL_VSTART.yaml` | 1 | +| 666 | `std/isa/param/JVT_READ_ONLY.yaml` | 1 | +| 667 | `std/isa/param/JVT_BASE_TYPE.yaml` | 1 | +| 668 | `std/isa/param/JVT_BASE_MASK.yaml` | 1 | +| 669 | `std/isa/param/REPORT_ENCODING_IN_VSTVAL_ON_VIRTUAL_INSTRUCTION.yaml` | 1 | +| 670 | `std/isa/param/REPORT_GPA_IN_HTVAL_ON_GUEST_PAGE_FAULT.yaml` | 1 | +| 671 | `std/isa/param/REPORT_GPA_IN_TVAL_ON_INSTRUCTION_GUEST_PAGE_FAULT.yaml` | 1 | +| 672 | `std/isa/param/TINST_VALUE_ON_VIRTUAL_INSTRUCTION.yaml` | 1 | +| 673 | `std/isa/param/TRAP_ON_UNIMPLEMENTED_INSTRUCTION.yaml` | 1 | +| 674 | `std/isa/param/TRAP_ON_UNIMPLEMENTED_CSR.yaml` | 1 | +| 675 | `std/isa/param/TRAP_ON_SFENCE_VMA_WHEN_SATP_MODE_IS_READ_ONLY.yaml` | 1 | +| 676 | `std/isa/param/TRAP_ON_RESERVED_INSTRUCTION.yaml` | 1 | +| 677 | `std/isa/param/TRAP_ON_ILLEGAL_WLRL.yaml` | 1 | +| 678 | `std/isa/param/TRAP_ON_ECALL_FROM_VS.yaml` | 1 | +| 679 | `std/isa/param/TRAP_ON_ECALL_FROM_U.yaml` | 1 | +| 680 | `std/isa/param/TRAP_ON_ECALL_FROM_S.yaml` | 1 | +| 681 | `std/isa/param/TRAP_ON_ECALL_FROM_M.yaml` | 1 | +| 682 | `std/isa/param/TRAP_ON_EBREAK.yaml` | 1 | +| 683 | `std/isa/param/TINST_VALUE_ON_VSCALL.yaml` | 1 | +| 684 | `std/isa/param/TINST_VALUE_ON_UCALL.yaml` | 1 | +| 685 | `std/isa/param/U_MODE_ENDIANNESS.yaml` | 1 | +| 686 | `std/isa/param/TINST_VALUE_ON_STORE_AMO_PAGE_FAULT.yaml` | 1 | +| 687 | `std/isa/param/TINST_VALUE_ON_STORE_AMO_ADDRESS_MISALIGNED.yaml` | 1 | +| 688 | `std/isa/param/TINST_VALUE_ON_STORE_AMO_ACCESS_FAULT.yaml` | 1 | +| 689 | `std/isa/param/TINST_VALUE_ON_SCALL.yaml` | 1 | +| 690 | `std/isa/param/TINST_VALUE_ON_MCALL.yaml` | 1 | +| 691 | `std/isa/param/TINST_VALUE_ON_LOAD_PAGE_FAULT.yaml` | 1 | +| 692 | `std/isa/param/TINST_VALUE_ON_LOAD_ADDRESS_MISALIGNED.yaml` | 1 | +| 693 | `std/isa/param/TINST_VALUE_ON_LOAD_ACCESS_FAULT.yaml` | 1 | +| 694 | `std/isa/param/TINST_VALUE_ON_INSTRUCTION_ADDRESS_MISALIGNED.yaml` | 1 | +| 695 | `std/isa/param/TINST_VALUE_ON_FINAL_STORE_AMO_GUEST_PAGE_FAULT.yaml` | 1 | +| 696 | `std/isa/param/TINST_VALUE_ON_FINAL_LOAD_GUEST_PAGE_FAULT.yaml` | 1 | +| 697 | `std/isa/param/UXLEN.yaml` | 1 | +| 698 | `std/isa/param/VECTOR_FF_NO_EXCEPTION_TRIM.yaml` | 1 | +| 699 | `std/isa/param/TINST_VALUE_ON_BREAKPOINT.yaml` | 1 | +| 700 | `std/isa/param/VFREDUSUM_NODE_ROUNDING_BEHAVIOR.yaml` | 1 | +| 701 | `std/isa/param/VU_MODE_ENDIANNESS.yaml` | 1 | +| 702 | `std/isa/param/VUXLEN.yaml` | 1 | +| 703 | `std/isa/param/VS_MODE_ENDIANNESS.yaml` | 1 | +| 704 | `std/isa/param/VSXLEN.yaml` | 1 | +| 705 | `std/isa/param/VSTVEC_MODE_VECTORED.yaml` | 1 | +| 706 | `std/isa/param/VSTVEC_MODE_DIRECT.yaml` | 1 | +| 707 | `std/isa/param/VSSTATUS_VS_EXISTS.yaml` | 1 | +| 708 | `std/isa/param/VSSTAGE_MODE_BARE.yaml` | 1 | +| 709 | `std/isa/param/VMID_WIDTH.yaml` | 1 | +| 710 | `std/isa/param/VLEN.yaml` | 1 | +| 711 | `std/isa/param/VILL_SET_ON_RESERVED_VTYPE.yaml` | 1 | +| 712 | `std/isa/param/VFREDUSUM_NAN.yaml` | 1 | +| 713 | `std/isa/param/VECTOR_FF_SEG_EXCEPTION_PARTIAL_LOAD.yaml` | 1 | +| 714 | `std/isa/param/VFREDUSUM_INACTIVE_NODE_ELEMENT_BEHAVIOR.yaml` | 1 | +| 715 | `std/isa/param/VFREDUSUM_FINAL_NODE_ELEMENT_BEHAVIOR.yaml` | 1 | +| 716 | `std/isa/param/VENDOR_ID_OFFSET.yaml` | 1 | +| 717 | `std/isa/param/VENDOR_ID_BANK.yaml` | 1 | +| 718 | `std/isa/param/VECTOR_LS_WHOLEREG_MISALIGNED_LEGAL.yaml` | 1 | +| 719 | `std/isa/param/VECTOR_LS_SEG_PARTIAL_ACCESS.yaml` | 1 | +| 720 | `std/isa/param/VECTOR_LS_MISALIGNED_LEGAL.yaml` | 1 | +| 721 | `std/isa/param/VECTOR_LS_INDEX_MAX_EEW.yaml` | 1 | +| 722 | `std/isa/param/VECTOR_LOAD_SEG_FF_OVERWRITE_ELEMENTS_AFTER_FAULT.yaml` | 1 | +| 723 | `std/isa/param/VECTOR_LOAD_PAST_TRAP.yaml` | 1 | +| 724 | `std/isa/param/VECTOR_FF_UPDATE_PAST_TRIM.yaml` | 1 | +| 725 | `std/isa/param/TINST_VALUE_ON_FINAL_INSTRUCTION_GUEST_PAGE_FAULT.yaml` | 1 | +| 726 | `std/isa/param/TIME_CSR_IMPLEMENTED.yaml` | 1 | +| 727 | `std/isa/param/REPORT_GPA_IN_TVAL_ON_INTERMEDIATE_GUEST_PAGE_FAULT.yaml` | 1 | +| 728 | `std/isa/param/REPORT_VA_IN_STVAL_ON_BREAKPOINT.yaml` | 1 | +| 729 | `std/isa/param/REPORT_VA_IN_VSTVAL_ON_INSTRUCTION_ACCESS_FAULT.yaml` | 1 | +| 730 | `std/isa/param/REPORT_VA_IN_VSTVAL_ON_BREAKPOINT.yaml` | 1 | +| 731 | `std/isa/param/REPORT_VA_IN_STVAL_ON_STORE_AMO_PAGE_FAULT.yaml` | 1 | +| 732 | `std/isa/param/REPORT_VA_IN_STVAL_ON_STORE_AMO_MISALIGNED.yaml` | 1 | +| 733 | `std/isa/param/REPORT_VA_IN_STVAL_ON_STORE_AMO_ACCESS_FAULT.yaml` | 1 | +| 734 | `std/isa/param/REPORT_VA_IN_STVAL_ON_LOAD_PAGE_FAULT.yaml` | 1 | +| 735 | `std/isa/param/REPORT_VA_IN_STVAL_ON_LOAD_MISALIGNED.yaml` | 1 | +| 736 | `std/isa/param/REPORT_VA_IN_STVAL_ON_LOAD_ACCESS_FAULT.yaml` | 1 | +| 737 | `std/isa/param/REPORT_VA_IN_STVAL_ON_INSTRUCTION_PAGE_FAULT.yaml` | 1 | +| 738 | `std/isa/param/REPORT_VA_IN_STVAL_ON_INSTRUCTION_MISALIGNED.yaml` | 1 | +| 739 | `std/isa/param/REPORT_VA_IN_STVAL_ON_INSTRUCTION_ACCESS_FAULT.yaml` | 1 | +| 740 | `std/isa/param/REPORT_VA_IN_MTVAL_ON_STORE_AMO_PAGE_FAULT.yaml` | 1 | +| 741 | `std/isa/param/REPORT_VA_IN_VSTVAL_ON_INSTRUCTION_PAGE_FAULT.yaml` | 1 | +| 742 | `std/isa/param/REPORT_VA_IN_MTVAL_ON_STORE_AMO_MISALIGNED.yaml` | 1 | +| 743 | `std/isa/param/REPORT_VA_IN_MTVAL_ON_STORE_AMO_ACCESS_FAULT.yaml` | 1 | +| 744 | `std/isa/param/REPORT_VA_IN_MTVAL_ON_LOAD_PAGE_FAULT.yaml` | 1 | +| 745 | `std/isa/param/REPORT_VA_IN_MTVAL_ON_LOAD_MISALIGNED.yaml` | 1 | +| 746 | `std/isa/param/REPORT_VA_IN_MTVAL_ON_LOAD_ACCESS_FAULT.yaml` | 1 | +| 747 | `std/isa/param/REPORT_VA_IN_MTVAL_ON_INSTRUCTION_PAGE_FAULT.yaml` | 1 | +| 748 | `std/isa/param/REPORT_VA_IN_MTVAL_ON_INSTRUCTION_MISALIGNED.yaml` | 1 | +| 749 | `std/isa/param/REPORT_VA_IN_MTVAL_ON_INSTRUCTION_ACCESS_FAULT.yaml` | 1 | +| 750 | `std/isa/param/REPORT_VA_IN_MTVAL_ON_BREAKPOINT.yaml` | 1 | +| 751 | `std/isa/param/REPORT_GPA_IN_TVAL_ON_STORE_AMO_GUEST_PAGE_FAULT.yaml` | 1 | +| 752 | `std/isa/param/REPORT_GPA_IN_TVAL_ON_LOAD_GUEST_PAGE_FAULT.yaml` | 1 | +| 753 | `std/isa/param/REPORT_VA_IN_VSTVAL_ON_INSTRUCTION_MISALIGNED.yaml` | 1 | +| 754 | `std/isa/param/REPORT_VA_IN_VSTVAL_ON_LOAD_ACCESS_FAULT.yaml` | 1 | +| 755 | `std/isa/param/S_MODE_ENDIANNESS.yaml` | 1 | +| 756 | `std/isa/param/STVEC_MODE_DIRECT.yaml` | 1 | +| 757 | `std/isa/param/SXLEN.yaml` | 1 | +| 758 | `std/isa/param/SV57_VSMODE_TRANSLATION.yaml` | 1 | +| 759 | `std/isa/param/SV57X4_TRANSLATION.yaml` | 1 | +| 760 | `std/isa/param/SV48_VSMODE_TRANSLATION.yaml` | 1 | +| 761 | `std/isa/param/SV48X4_TRANSLATION.yaml` | 1 | +| 762 | `std/isa/param/SV39_VSMODE_TRANSLATION.yaml` | 1 | +| 763 | `std/isa/param/SV39X4_TRANSLATION.yaml` | 1 | +| 764 | `std/isa/param/SV32_VSMODE_TRANSLATION.yaml` | 1 | +| 765 | `std/isa/param/SV32X4_TRANSLATION.yaml` | 1 | +| 766 | `std/isa/param/SUPPORT_FRACTIONAL_LMUL_BEYOND_REQUIRED.yaml` | 1 | +| 767 | `std/isa/param/STVEC_MODE_VECTORED.yaml` | 1 | +| 768 | `std/isa/param/STVAL_WIDTH.yaml` | 1 | +| 769 | `std/isa/param/REPORT_VA_IN_VSTVAL_ON_LOAD_MISALIGNED.yaml` | 1 | +| 770 | `std/isa/param/SSTATEEN_JVT_TYPE.yaml` | 1 | +| 771 | `std/isa/param/SEW_MIN.yaml` | 1 | +| 772 | `std/isa/param/SCOUNTENABLE_EN.yaml` | 1 | +| 773 | `std/isa/param/SATP_MODE_BARE.yaml` | 1 | +| 774 | `std/isa/param/RVV_VL_WHEN_AVL_LT_DOUBLE_VLMAX.yaml` | 1 | +| 775 | `std/isa/param/RESERVED_VSET_X0X0_VLMAX_CHANGE.yaml` | 1 | +| 776 | `std/isa/param/RESERVED_VSET_X0X0_VILL_SET.yaml` | 1 | +| 777 | `std/isa/param/REPORT_VA_IN_VSTVAL_ON_STORE_AMO_PAGE_FAULT.yaml` | 1 | +| 778 | `std/isa/param/REPORT_VA_IN_VSTVAL_ON_STORE_AMO_MISALIGNED.yaml` | 1 | +| 779 | `std/isa/param/REPORT_VA_IN_VSTVAL_ON_STORE_AMO_ACCESS_FAULT.yaml` | 1 | +| 780 | `std/isa/param/REPORT_VA_IN_VSTVAL_ON_LOAD_PAGE_FAULT.yaml` | 1 | +| 781 | `/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zvl64b.yaml` | 1 | + +## Complete Extracted Parameters List (UDB) + +> _Showing a randomized sample (up to 10 chunks per parameter class)._ + +| Section | Parameter_Class | Text | Confidence | +|---|---|---|---| +| mhpmevent7.OF | CSR_controlled | CSR mhpmevent7 field OF (bits=63) Overflow status and interrupt disable. The OF bit is set when the corresponding hpmcounter overflows, and remains set until written by software. Since hpmcounter val... | high | +| vsstatus.UBE | CSR_controlled | CSR vsstatus field UBE (bits=6) *VU-mode Big Endian* Controls the endianness of VU-mode (0 = little, 1 = big). [when,"VU_MODE_ENDIANNESS == 'little'"] Since the CPU does not support big endian, this... | high | +| mstateen3 | CSR_controlled | CSR mstateen3 (address=783, priv=M): Each bit of a `stateen` CSR controls less-privileged access to an extension’s state, or an extension that was not deemed "worthy" of a full XS field in `sstatus` l... | high | +| mhpmevent30.MINH | CSR_controlled | CSR mhpmevent30 field MINH (bits=62) When set, mhpmcounter30 does not increment while the hart in operating in M-mode. type: if (HPM_COUNTER_EN[30]) { reset: if (HPM_COUNTER_EN[30]) {... | high | +| hstateen0h.SE0 | CSR_controlled | CSR hstateen0h field SE0 (bits=31) The SE0 bit in `hstateen0h` controls access to the `sstateen0` CSR. type: RW reset: UNDEFINED_LEGAL... | high | +| vsatp.MODE | CSR_controlled | CSR vsatp field MODE (bits=rv32=31 rv64=63-60) *Translation Mode* Controls the current translation mode in VS-mode according to the table below. [separator="!",%autowidth] !=== ! Value ! Name ! Desc... | high | +| mie.SSIE | CSR_controlled | CSR mie field SSIE (bits=1) Enables Supervisor Software Interrupts. type: RW... | high | +| sie.SEIE | CSR_controlled | CSR sie field SEIE (bits=9) Supervisor External Interrupt Enable type: RW reset: UNDEFINED_LEGAL... | high | +| mhpmevent25.MINH | CSR_controlled | CSR mhpmevent25 field MINH (bits=62) When set, mhpmcounter25 does not increment while the hart in operating in M-mode. type: if (HPM_COUNTER_EN[25]) { reset: if (HPM_COUNTER_EN[25]) {... | high | +| htinst | CSR_controlled | CSR htinst (address=1610, priv=S): When a trap is taken into HS-mode, mtinst is written with a value that, if nonzero, provides information about the instruction that trapped, to assist software in ha... | high | +| Sstvala | non_CSR_parameter | Extension Sstvala (Supervisor Trap Value provides all needed values) [ratified] `stval` must be written with the faulting virtual address for load, store, and instruction page-fault, access-fault, and... | high | +| Smmpm | non_CSR_parameter | Extension Smmpm (Pointer masking for M-mode) [ratified] A machine-level extension that provides pointer masking for M-mode.... | high | +| Zvbc | non_CSR_parameter | Extension Zvbc (Vector Carryless Multiplication) [ratified] General purpose carryless multiplication instructions which are commonly used in cryptography and hashing (e.g., Elliptic curve cryptography... | high | +| Zicfiss | non_CSR_parameter | Extension Zicfiss (Shadow Stack) [ratified] TODO... | high | +| MCTRCTL_STE_IMPLEMENTED | non_CSR_parameter | Parameter MCTRCTL_STE_IMPLEMENTED Whether or not mctrctl.STE is implemented. When not implemented mctrctl.STE will be read-only-zero. Schema: type=boolean. Defined by: Smctr.... | high | +| Zvks | non_CSR_parameter | Extension Zvks (ShangMi Algorithm Suite) [ratified] This extension is shorthand for the following set of other extensions: * `Zvksed` * `Zvksh` * `Zvkb` * `Zvkt`... | high | +| LEGAL_VSTART | non_CSR_parameter | Parameter LEGAL_VSTART Implementations may raise illegal-instruction exceptions for vector instructions that specify a `vstart` value the implementation can never produce under the same `vtype` config... | high | +| REPORT_GPA_IN_TVAL_ON_INTERMEDIATE_GUEST_PAGE_FAULT | non_CSR_parameter | Parameter REPORT_GPA_IN_TVAL_ON_INTERMEDIATE_GUEST_PAGE_FAULT Whether or not GPA >> 2 is written into htval/mtval2 when a guest page fault occurs while walking a VS-mode page table. If false, 0 will ... | high | +| Zvksg | non_CSR_parameter | Extension Zvksg (ShangMi Algorithm Suite with GCM) [ratified] This extension is shorthand for the following set of other extensions: * `Zvks` * `Zvkg`... | high | +| Shtvala | non_CSR_parameter | Extension Shtvala (Hypervisor Trap Value provides all needed values) [ratified] htval must be written with the faulting guest physical address in all circumstances permitted by the ISA. [NOTE] This e... | high | diff --git a/tools/llm-extraction/data/output/adoc_report_data.json b/tools/llm-extraction/data/output/adoc_report_data.json new file mode 100644 index 0000000000..a71ecf7e11 --- /dev/null +++ b/tools/llm-extraction/data/output/adoc_report_data.json @@ -0,0 +1,879 @@ +{ + "global": { + "total_files": 136, + "processed_files": 131, + "skipped_files": 5, + "total_raw_chunks": 10529, + "total_final_chunks": 4311, + "reduction_percent": 59.06, + "isa_manual_commit": "dca12d638b140d86441ad0b067997c70d2017017" + }, + "files": { + "src/b-st-ext.adoc": { + "raw_chunks": 591, + "final_chunks": 40, + "dropped": 551 + }, + "src/images/graphviz/litmus_sample.adoc": { + "raw_chunks": 4, + "final_chunks": 0, + "dropped": 4 + }, + "src/intro.adoc": { + "raw_chunks": 143, + "final_chunks": 5, + "dropped": 138 + }, + "src/naming.adoc": { + "raw_chunks": 82, + "final_chunks": 8, + "dropped": 74 + }, + "src/priv/cfi.adoc": { + "raw_chunks": 69, + "final_chunks": 44, + "dropped": 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be interpreted as an unsigned word.", + "However, where the shift-logical instructions shift in zeros, the rotate instructions shift in the bits that were shifted out of the other side of the value.", + "One use-case is string-processing functions, such as *strlen* and *strcpy*, which can use *orc.b* to test for the terminating zero byte by counting the set bits in leading non-zero bytes in a word.", + "Elements in rs1 are replaced by the indexed element in rs2, or zero if the index into rs2 is out of bounds.", + "foreach (i from 0 to (xlen - 1) by 1) { output = if ((rs2val >> i) & 1) then output ^ (rs1val << i); else output; }", + "foreach (i from 1 to xlen by 1) { output = if ((rs2val >> i) & 1) then output ^ (rs1val >> (xlen - i)); else output; }", + "foreach (i from 0 to (xlen - 1) by 1) { output = if ((rs2val >> i) & 1) then output ^ (rs1val >> (xlen - i - 1)); else output; }", + "Accordingly, if the input is 0, the output is XLEN, and if the most-significant bit of the input is a 1, the output is 0.", + "function HighestSetBit x = { foreach (i from (xlen - 1) to 0 by 1 in dec) if [x[i]] 0b1 then return(i) else (); return -1; }" + ] + } +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/chunks_repo.json b/tools/llm-extraction/data/output/chunks_repo.json new file mode 100644 index 0000000000..2f56527932 --- /dev/null +++ b/tools/llm-extraction/data/output/chunks_repo.json @@ -0,0 +1,56605 @@ +[ + { + "file": "src/b-st-ext.adoc", + "chunks": [ + { + "chunk_id": "chunk_72400c97", + "text": "Thus, when implementing extensions with overlapping instructions, there is no redundancy in logic or encoding.", + "source_file": "src/b-st-ext.adoc", + "section": "Preamble > Bit Manipulation Extensions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 7, + 9 + ] + }, + { + "chunk_id": "chunk_72f0e68d", + "text": "The bitmanip extension follows the convention in RV64 that w-suffixed instructions (without a dot before the w) ignore the upper 32 bits of their inputs, operate on the least-significant 32 bits as signed values, and produce a 32-bit signed result that is sign-extended to XLEN.", + "source_file": "src/b-st-ext.adoc", + "section": "Preamble > Bit Manipulation Extensions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 13, + 13 + ] + }, + { + "chunk_id": "chunk_6f482888", + "text": "Bitmanip instructions with the suffix .uw have one operand that is an unsigned 32-bit value that is extracted from the least-significant 32 bits of the specified register.", + "source_file": "src/b-st-ext.adoc", + "section": "Preamble > Bit Manipulation Extensions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 15, + 15 + ] + }, + { + "chunk_id": "chunk_6cde1763", + "text": "Bitmanip instructions with the suffixes .b, .h, and .w only look at the least-significant 8 bits, 16 bits, and 32 bits of the input (respectively) and produce an XLEN-wide result that is sign-extended or zero-extended, based on the specific instruction.", + "source_file": "src/b-st-ext.adoc", + "section": "Preamble > Bit Manipulation Extensions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 17, + 17 + ] + }, + { + "chunk_id": "chunk_8ae4c463", + "text": "The slli.uw -- added in this extension -- can be used when the index is to be interpreted as an unsigned word.", + "source_file": "src/b-st-ext.adoc", + "section": "Preamble > Bit Manipulation Extensions > Zba: Extension for Address generation, Version 1.0.0", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 102, + 102 + ] + }, + { + "chunk_id": "chunk_3bc70eec", + "text": "These instructions perform the sign extension or zero extension of the least-significant 8 bits or 16 bits of the source register.", + "source_file": "src/b-st-ext.adoc", + "section": "Preamble > Bit Manipulation Extensions > ext:zbb[] Extension for Basic bit-manipulation, Version 1.0.0 > Sign extension and zero extension", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 278, + 278 + ] + }, + { + "chunk_id": "chunk_ade33c39", + "text": "However, where the shift-logical instructions shift in zeros, the rotate instructions shift in the bits that were shifted out of the other side of the value.", + "source_file": "src/b-st-ext.adoc", + "section": "Preamble > Bit Manipulation Extensions > ext:zbb[] Extension for Basic bit-manipulation, Version 1.0.0 > Bitwise rotation", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 307, + 309 + ] + }, + { + "chunk_id": "chunk_b800648f", + "text": "One use-case is string-processing functions, such as *strlen* and *strcpy*, which can use *orc.b* to test for the terminating zero byte by counting the set bits in leading non-zero bytes in a word.", + "source_file": "src/b-st-ext.adoc", + "section": "Preamble > Bit Manipulation Extensions > ext:zbb[] Extension for Basic bit-manipulation, Version 1.0.0 > OR Combine", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 362, + 362 + ] + }, + { + "chunk_id": "chunk_2d7318b2", + "text": "These instructions implement a \"lookup table\" for 4 and 8 bit elements inside the general purpose registers. rs1 is used as a vector of N-bit words, and rs2 as a vector of N-bit indices into rs1.", + "source_file": "src/b-st-ext.adoc", + "section": "Preamble > Bit Manipulation Extensions > Zbkx: Extension for Crossbar permutations, Version 1.0.0", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 593, + 598 + ] + }, + { + "chunk_id": "chunk_07a81f9e", + "text": "Elements in rs1 are replaced by the indexed element in rs2, or zero if the index into rs2 is out of bounds.", + "source_file": "src/b-st-ext.adoc", + "section": "Preamble > Bit Manipulation Extensions > Zbkx: Extension for Crossbar permutations, Version 1.0.0", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 593, + 598 + ] + }, + { + "chunk_id": "chunk_6f7ecc59", + "text": "foreach (i from 0 to (xlen - 1) by 1) { output = if ((rs2val >> i) & 1) then output ^ (rs1val << i); else output; }", + "source_file": "src/b-st-ext.adoc", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > clmul", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1213, + 1217 + ] + }, + { + "chunk_id": "chunk_9119292b", + "text": "foreach (i from 1 to xlen by 1) { output = if ((rs2val >> i) & 1) then output ^ (rs1val >> (xlen - i)); else output; }", + "source_file": "src/b-st-ext.adoc", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > clmulh", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1273, + 1277 + ] + }, + { + "chunk_id": "chunk_9f291ed8", + "text": "foreach (i from 0 to (xlen - 1) by 1) { output = if ((rs2val >> i) & 1) then output ^ (rs1val >> (xlen - i - 1)); else output; }", + "source_file": "src/b-st-ext.adoc", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > clmulr", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1335, + 1339 + ] + }, + { + "chunk_id": "chunk_c467946b", + "text": "Accordingly, if the input is 0, the output is XLEN, and if the most-significant bit of the input is a 1, the output is 0.", + "source_file": "src/b-st-ext.adoc", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > clz", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1389, + 1390 + ] + }, + { + "chunk_id": "chunk_c6b7c07b", + "text": "function HighestSetBit x = { foreach (i from (xlen - 1) to 0 by 1 in dec) if [x[i]] 0b1 then return(i) else (); return -1; }", + "source_file": "src/b-st-ext.adoc", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > clz", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1398, + 1402 + ] + }, + { + "chunk_id": "chunk_39d5e5ae", + "text": "function HighestSetBit32 x = { foreach (i from 31 to 0 by 1 in dec) if [x[i]] 0b1 then return(i) else (); return -1; }", + "source_file": "src/b-st-ext.adoc", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > clzw", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1454, + 1458 + ] + }, + { + "chunk_id": "chunk_3448113b", + "text": "foreach (i from 0 to (xlen - 1) in inc) if rs[i] 0b1 then bitcount = bitcount + 1 else ();", + "source_file": "src/b-st-ext.adoc", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > cpop", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1509, + 1510 + ] + }, + { + "chunk_id": "chunk_0c22b02e", + "text": "foreach (i from 0 to 31 in inc) if val[i] 0b1 then bitcount = bitcount + 1 else ();", + "source_file": "src/b-st-ext.adoc", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > cpopw", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1569, + 1570 + ] + }, + { + "chunk_id": "chunk_3abf2f8d", + "text": "Accordingly, if the input is 0, the output is XLEN, and if the least-significant bit of the input is a 1, the output is 0.", + "source_file": "src/b-st-ext.adoc", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > ctz", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1611, + 1613 + ] + }, + { + "chunk_id": "chunk_4586d663", + "text": "function LowestSetBit x = { foreach (i from 0 to (xlen - 1) by 1 in dec) if [x[i]] 0b1 then return(i) else (); return xlen; }", + "source_file": "src/b-st-ext.adoc", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > ctz", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1621, + 1625 + ] + }, + { + "chunk_id": "chunk_3e8b7f15", + "text": "Accordingly, if the least-significant word is 0, the output is 32, and if the least-significant bit of the input is a 1, the output is 0.", + "source_file": "src/b-st-ext.adoc", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > ctzw", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1667, + 1668 + ] + }, + { + "chunk_id": "chunk_7ac216f1", + "text": "function LowestSetBit32 x = { foreach (i from 0 to 31 by 1 in dec) if [x[i]] 0b1 then return(i) else (); return 32; }", + "source_file": "src/b-st-ext.adoc", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > ctzw", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1676, + 1680 + ] + }, + { + "chunk_id": "chunk_8547b17a", + "text": "let result = if rs1val Bit Manipulation Extensions > Instructions (in alphabetical order) > max", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1732, + 1734 + ] + }, + { + "chunk_id": "chunk_da7e0a08", + "text": "let result = if rs1val Bit Manipulation Extensions > Instructions (in alphabetical order) > maxu", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1795, + 1797 + ] + }, + { + "chunk_id": "chunk_21ef0738", + "text": "let result = if rs1val Bit Manipulation Extensions > Instructions (in alphabetical order) > min", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1848, + 1850 + ] + }, + { + "chunk_id": "chunk_68c32239", + "text": "let result = if rs1val Bit Manipulation Extensions > Instructions (in alphabetical order) > minu", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1901, + 1903 + ] + }, + { + "chunk_id": "chunk_ac3abf3b", + "text": "This sets the bits of each byte in the result rd to all zeros if no bit within the respective byte of rs is set, or to all ones if any bit within the respective byte of rs is set.", + "source_file": "src/b-st-ext.adoc", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > orc.b", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1943, + 1945 + ] + }, + { + "chunk_id": "chunk_8367c35b", + "text": "foreach (i from 0 to (xlen - 8) by 8) { output[(i + 7)..i] = if input[(i + 7)..i] 0 then 0b00000000 else 0b11111111; }", + "source_file": "src/b-st-ext.adoc", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > orc.b", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1954, + 1958 + ] + }, + { + "chunk_id": "chunk_a13aaf9e", + "text": "Hence, for RV32, any extension that contains the `pack` instruction also contains the `zext.h` instruction (but not necessarily the `c.zext.h` instruction, which is only guaranteed to exist if both the Zcb and Zbb extensions are implemented).", + "source_file": "src/b-st-ext.adoc", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > pack", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2074, + 2079 + ] + }, + { + "chunk_id": "chunk_9d078cff", + "text": "Hence, for RV64, any extension that contains the `packw` instruction also contains the `zext.h` instruction (but not necessarily the `c.zext.h` instruction, which is only guaranteed to exist if both the Zcb and Zbb extensions are implemented).", + "source_file": "src/b-st-ext.adoc", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > packw", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2182, + 2187 + ] + }, + { + "chunk_id": "chunk_3fa701c7", + "text": "Operation:: [source,sail] -- let shamt = if xlen 32 then X(rs2)[4..0] else X(rs2)[5..0]; let result = (X(rs1) (xlen - shamt));", + "source_file": "src/b-st-ext.adoc", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > rol", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2351, + 2358 + ] + }, + { + "chunk_id": "chunk_5d1d4830", + "text": "The resulting word value is sign-extended by copying bit 31 to all of the more-significant bits.", + "source_file": "src/b-st-ext.adoc", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > rolw", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 2403, + 2405 + ] + }, + { + "chunk_id": "chunk_94adf6c4", + "text": "Operation:: [source,sail] -- let shamt = if xlen 32 then X(rs2)[4..0] else X(rs2)[5..0]; let result = (X(rs1) >> shamt) | (X(rs1) << (xlen - shamt));", + "source_file": "src/b-st-ext.adoc", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > ror", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2460, + 2467 + ] + }, + { + "chunk_id": "chunk_724c674f", + "text": "Operation:: [source,sail] -- let shamt = if xlen 32 then shamt[4..0] else shamt[5..0]; let result = (X(rs1) >> shamt) | (X(rs1) << (xlen - shamt));", + "source_file": "src/b-st-ext.adoc", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > rori", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2530, + 2537 + ] + }, + { + "chunk_id": "chunk_6c1bc4c4", + "text": "The resulting word value is sign-extended by copying bit 31 to all of the more-significant bits.", + "source_file": "src/b-st-ext.adoc", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > roriw", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 2582, + 2587 + ] + }, + { + "chunk_id": "chunk_3c467591", + "text": "The resultant word is sign-extended by copying bit 31 to all of the more-significant bits.", + "source_file": "src/b-st-ext.adoc", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > rorw", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 2639, + 2641 + ] + }, + { + "chunk_id": "chunk_d381403f", + "text": "The rs1 register contains a vector of XLEN/8 8-bit elements.", + "source_file": "src/b-st-ext.adoc", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > xperm8", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 3241, + 3246 + ] + }, + { + "chunk_id": "chunk_e09be124", + "text": "The rs2 register contains a vector of XLEN/8 8-bit indexes.", + "source_file": "src/b-st-ext.adoc", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > xperm8", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 3241, + 3246 + ] + }, + { + "chunk_id": "chunk_0c7247ac", + "text": "The rs1 register contains a vector of XLEN/4 4-bit elements.", + "source_file": "src/b-st-ext.adoc", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > xperm4", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 3303, + 3308 + ] + }, + { + "chunk_id": "chunk_e09dbd4b", + "text": "The rs2 register contains a vector of XLEN/4 4-bit indexes.", + "source_file": "src/b-st-ext.adoc", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > xperm4", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 3303, + 3308 + ] + } + ] + }, + { + "file": "src/intro.adoc", + "chunks": [ + { + "chunk_id": "chunk_a7b3ed7d", + "text": "A RISC-V ISA is defined as a base integer ISA, which must be present in any implementation, plus optional extensions to the base ISA.", + "source_file": "src/intro.adoc", + "section": "Preamble > Introduction > RISC-V ISA Overview", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 146, + 155 + ] + }, + { + "chunk_id": "chunk_934647e2", + "text": "For this purpose, we divide each RISC-V instruction-set encoding space (and related encoding spaces such as the CSRs) into three disjoint categories: standard, reserved, and custom.", + "source_file": "src/intro.adoc", + "section": "Preamble > Introduction > RISC-V ISA Overview", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 172, + 192 + ] + }, + { + "chunk_id": "chunk_6db06846", + "text": "Custom encodings shall never be used for standard extensions and are made available for vendor-specific non-standard extensions.", + "source_file": "src/intro.adoc", + "section": "Preamble > Introduction > RISC-V ISA Overview", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 172, + 192 + ] + }, + { + "chunk_id": "chunk_9ee31d36", + "text": "The base RISC-V ISA has fixed-length 32-bit instructions that must be naturally aligned on 32-bit boundaries.", + "source_file": "src/intro.adoc", + "section": "Preamble > Introduction > Base Instruction-Length Encoding", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 313, + 322 + ] + }, + { + "chunk_id": "chunk_545961c8", + "text": "Instruction encodings that are not defined here and not defined by some other means may cause a fatal trap.", + "source_file": "src/intro.adoc", + "section": "Preamble > Introduction > Exceptions, Traps, and Interrupts", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 439, + 446 + ] + } + ] + }, + { + "file": "src/naming.adoc", + "chunks": [ + { + "chunk_id": "chunk_fa950ca0", + "text": "All multi-letter extensions, including those with the \"Z\" prefix, must be separated from other multi-letter extensions by an underscore, e.g., \"RV32IMACZicsrZifencei\".", + "source_file": "src/naming.adoc", + "section": "Preamble > ISA Extension Naming Conventions > Additional Standard Unprivileged Extension Names", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 65, + 67 + ] + }, + { + "chunk_id": "chunk_529b547b", + "text": "Standard user-level extensions should be listed after standard unprivileged extensions, and like other multi-letter extensions, must be separated from other multi-letter extensions by an underscore.", + "source_file": "src/naming.adoc", + "section": "Preamble > ISA Extension Naming Conventions > User-Level Instruction-Set Extension Names", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 74, + 77 + ] + }, + { + "chunk_id": "chunk_59a5d0ad", + "text": "Standard supervisor-level extensions should be listed after standard unprivileged and user-level extensions, and like other multi-letter extensions, must be separated from other multi-letter extensions by an underscore.", + "source_file": "src/naming.adoc", + "section": "Preamble > ISA Extension Naming Conventions > Supervisor-Level Instruction-Set Extension Names", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 92, + 96 + ] + }, + { + "chunk_id": "chunk_fea06266", + "text": "Standard hypervisor-level extensions should be listed after standard unprivileged, user-level and supervisor-level extensions, and like other multi-letter extensions, must be separated from other multi-letter extensions by an underscore.", + "source_file": "src/naming.adoc", + "section": "Preamble > ISA Extension Naming Conventions > Hypervisor-Level Instruction-Set Extension Names", + "confidence": "very_high", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 103, + 107 + ] + }, + { + "chunk_id": "chunk_2a35f724", + "text": "Standard machine-level extensions should be listed after standard lesser-privileged extensions, and like other multi-letter extensions, must be separated from other multi-letter extensions by an underscore.", + "source_file": "src/naming.adoc", + "section": "Preamble > ISA Extension Naming Conventions > Machine-Level Instruction-Set Extension Names", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 120, + 123 + ] + }, + { + "chunk_id": "chunk_be42535c", + "text": "Non-standard extensions must be listed after all standard extensions, and, like other multi-letter extensions, must be separated from other multi-letter extensions by an underscore.", + "source_file": "src/naming.adoc", + "section": "Preamble > ISA Extension Naming Conventions > Non-Standard Extension Names", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 132, + 135 + ] + }, + { + "chunk_id": "chunk_3b6a96d7", + "text": "Because the \"P\" extension for Packed SIMD can be confused for the decimal point in a version number, it must be preceded by an underscore if it follows another extension with a version number.", + "source_file": "src/naming.adoc", + "section": "Preamble > ISA Extension Naming Conventions > Version Numbers", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 149, + 153 + ] + }, + { + "chunk_id": "chunk_fbb0d188", + "text": "Changes in major version numbers imply a loss of backwards compatibility, whereas changes in only the minor version number must be backwards-compatible.", + "source_file": "src/naming.adoc", + "section": "Preamble > ISA Extension Naming Conventions > Version Numbers", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 155, + 160 + ] + } + ] + }, + { + "file": "src/priv/cfi.adoc", + "chunks": [ + { + "chunk_id": "chunk_efe787ec", + "text": "The term `xLPE` is used to determine if forward-edge CFI using landing pads provided by the Zicfilp extension is enabled at a privilege mode.", + "source_file": "src/priv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing-Pad-Enabled (LPE) State", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 18, + 19 + ] + }, + { + "chunk_id": "chunk_59acce82", + "text": "When S-mode is implemented, it is determined as follows:", + "source_file": "src/priv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing-Pad-Enabled (LPE) State", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 21, + 21 + ] + }, + { + "chunk_id": "chunk_e3dcab7c", + "text": "When S-mode is not implemented, it is determined as follows:", + "source_file": "src/priv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing-Pad-Enabled (LPE) State", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 34, + 34 + ] + }, + { + "chunk_id": "chunk_4895ad36", + "text": "A trap may need to be delivered to the same or to a higher privilege mode upon completion of `JALR`/`C.JALR`/`C.JR`, but before the instruction at the target of indirect call/jump was decoded, due to:", + "source_file": "src/priv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing-Pad-Enabled (LPE) State > Preserving Expected Landing Pad State on Traps", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 50, + 52 + ] + }, + { + "chunk_id": "chunk_6e558ddf", + "text": "Asynchronous interrupts. * Synchronous exceptions with priority higher than that of a software-check exception with `xtval` set to \"landing pad fault (code=2)\" (See of Privileged Specification).", + "source_file": "src/priv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing-Pad-Enabled (LPE) State > Preserving Expected Landing Pad State on Traps", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 54, + 57 + ] + }, + { + "chunk_id": "chunk_f4d03112", + "text": "The software-check exception caused by Zicfilp has higher priority than an illegal-instruction exception but lower priority than instruction access-fault.", + "source_file": "src/priv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing-Pad-Enabled (LPE) State > Preserving Expected Landing Pad State on Traps", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 59, + 61 + ] + }, + { + "chunk_id": "chunk_e3544eaf", + "text": "The software-check exception due to the instruction not being an `LPAD` instruction when `ELP` is `LPEXPECTED` or a software-check exception caused by the `LPAD` instruction itself leads to a trap being delivered to the same or to a higher privilege mode.", + "source_file": "src/priv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing-Pad-Enabled (LPE) State > Preserving Expected Landing Pad State on Traps", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 63, + 67 + ] + }, + { + "chunk_id": "chunk_46ce2b58", + "text": "In such cases, the `ELP` prior to the trap, the previous `ELP`, must be preserved by the trap delivery such that it can be restored on a return from the trap.", + "source_file": "src/priv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing-Pad-Enabled (LPE) State > Preserving Expected Landing Pad State on Traps", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 69, + 77 + ] + }, + { + "chunk_id": "chunk_2afc3f0c", + "text": "To store the previous `ELP` state on trap delivery to M-mode, an `MPELP` bit is provided in the `mstatus` CSR.", + "source_file": "src/priv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing-Pad-Enabled (LPE) State > Preserving Expected Landing Pad State on Traps", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 69, + 77 + ] + }, + { + "chunk_id": "chunk_841fe5d9", + "text": "To store the previous `ELP` state on trap delivery to S/HS-mode, an `SPELP` bit is provided in the `mstatus` CSR.", + "source_file": "src/priv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing-Pad-Enabled (LPE) State > Preserving Expected Landing Pad State on Traps", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 69, + 77 + ] + }, + { + "chunk_id": "chunk_430ad9ab", + "text": "The `SPELP` bit in `mstatus` can be accessed through the `sstatus` CSR.", + "source_file": "src/priv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing-Pad-Enabled (LPE) State > Preserving Expected Landing Pad State on Traps", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 69, + 77 + ] + }, + { + "chunk_id": "chunk_947c4270", + "text": "To store the previous `ELP` state on traps to VS-mode, a `SPELP` bit is defined in the `vsstatus` (VS-modes version of `sstatus`).", + "source_file": "src/priv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing-Pad-Enabled (LPE) State > Preserving Expected Landing Pad State on Traps", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 69, + 77 + ] + }, + { + "chunk_id": "chunk_6dabd988", + "text": "To store the previous `ELP` state on transition to Debug Mode, a `pelp` bit is defined in the `dcsr` register.", + "source_file": "src/priv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing-Pad-Enabled (LPE) State > Preserving Expected Landing Pad State on Traps", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 69, + 77 + ] + }, + { + "chunk_id": "chunk_ec92d094", + "text": "When a trap is taken into privilege mode `x`, the `xPELP` is set to `ELP` and `ELP` is set to `NOLPEXPECTED`.", + "source_file": "src/priv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing-Pad-Enabled (LPE) State > Preserving Expected Landing Pad State on Traps", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 79, + 81 + ] + }, + { + "chunk_id": "chunk_304cdc22", + "text": "An `MRET` or `SRET` instruction is used to return from a trap in M-mode or S-mode, respectively.", + "source_file": "src/priv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing-Pad-Enabled (LPE) State > Preserving Expected Landing Pad State on Traps", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 83, + 88 + ] + }, + { + "chunk_id": "chunk_1c7e4dde", + "text": "Upon entry into Debug Mode, the `pelp` bit in `dcsr` is updated with the `ELP` at the privilege level the hart was previously in, and the `ELP` is set to `NOLPEXPECTED`.", + "source_file": "src/priv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing-Pad-Enabled (LPE) State > Preserving Expected Landing Pad State on Traps", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 90, + 95 + ] + }, + { + "chunk_id": "chunk_66ffceca", + "text": "See also for semantics added to the RNMI trap and the MNRET instruction when this extension is implemented.", + "source_file": "src/priv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing-Pad-Enabled (LPE) State > Preserving Expected Landing Pad State on Traps", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 97, + 98 + ] + }, + { + "chunk_id": "chunk_b72e9503", + "text": "Attempts to access the `ssp` CSR may result in either an illegal-instruction exception or a virtual-instruction exception, contingent upon the state of the *x*`envcfg.SSE` fields.", + "source_file": "src/priv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Pointer (`ssp`) CSR access control", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 109, + 112 + ] + }, + { + "chunk_id": "chunk_8a6ad9f0", + "text": "If the privilege mode is less than M and `menvcfg.SSE` is 0, an illegal-instruction exception is raised. *", + "source_file": "src/priv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Pointer (`ssp`) CSR access control", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 114, + 122 + ] + }, + { + "chunk_id": "chunk_cb449656", + "text": "Otherwise, if in U-mode and `senvcfg.SSE` is 0, an illegal-instruction exception is raised. *", + "source_file": "src/priv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Pointer (`ssp`) CSR access control", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 114, + 122 + ] + }, + { + "chunk_id": "chunk_a5ab2e84", + "text": "Otherwise, if in VS-mode and `henvcfg.SSE` is 0, a virtual-instruction exception is raised. *", + "source_file": "src/priv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Pointer (`ssp`) CSR access control", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 114, + 122 + ] + }, + { + "chunk_id": "chunk_9b132194", + "text": "Otherwise, if in VU-mode and either `henvcfg.SSE` or `senvcfg.SSE` is 0, a virtual-instruction exception is raised. *", + "source_file": "src/priv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Pointer (`ssp`) CSR access control", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 114, + 122 + ] + }, + { + "chunk_id": "chunk_d0a9ffe4", + "text": "Otherwise, the access is allowed.", + "source_file": "src/priv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Pointer (`ssp`) CSR access control", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 114, + 122 + ] + }, + { + "chunk_id": "chunk_674b797a", + "text": "The term `xSSE` is used to determine if backward-edge CFI using shadow stacks provided by the Zicfiss extension is enabled at a privilege mode.", + "source_file": "src/priv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow-Stack-Enabled (SSE) State", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 126, + 127 + ] + }, + { + "chunk_id": "chunk_73e96a24", + "text": "When S-mode is implemented, it is determined as follows:", + "source_file": "src/priv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow-Stack-Enabled (SSE) State", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 129, + 129 + ] + }, + { + "chunk_id": "chunk_220a4e5f", + "text": "When S-mode is not implemented, then `xSSE` is 0 at both M and U privilege modes.", + "source_file": "src/priv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow-Stack-Enabled (SSE) State", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 142, + 143 + ] + }, + { + "chunk_id": "chunk_dfde7c23", + "text": "When `menvcfg.SSE=0`, this encoding remains reserved.", + "source_file": "src/priv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Memory Protection", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 153, + 157 + ] + }, + { + "chunk_id": "chunk_7f4b2a9c", + "text": "Similarly, when `V=1` and `henvcfg.SSE=0`, this encoding remains reserved at `VS` and `VU` levels.", + "source_file": "src/priv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Memory Protection", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 153, + 157 + ] + }, + { + "chunk_id": "chunk_7cb98c59", + "text": "If `satp.MODE` (or `vsatp.MODE` when `V=1`) is set to `Bare` and the effective privilege mode is less than M, shadow stack instructions raise a store/AMO access-fault exception.", + "source_file": "src/priv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Memory Protection", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 159, + 162 + ] + }, + { + "chunk_id": "chunk_a0d66d71", + "text": "When the effective privilege mode is M, memory access by an `SSAMOSWAP.W/D` instruction results in a store/AMO access-fault exception.", + "source_file": "src/priv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Memory Protection", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 159, + 162 + ] + }, + { + "chunk_id": "chunk_cf57eff0", + "text": "Attempts will raise a store/AMO access-fault exception.", + "source_file": "src/priv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Memory Protection", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 164, + 171 + ] + }, + { + "chunk_id": "chunk_08a7c3f9", + "text": "Access to a SS page using cache-block operation (`CBO.*`) instructions is not permitted.", + "source_file": "src/priv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Memory Protection", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 164, + 171 + ] + }, + { + "chunk_id": "chunk_4fa24c19", + "text": "Such accesses will raise a store/AMO access-fault exception.", + "source_file": "src/priv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Memory Protection", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 164, + 171 + ] + }, + { + "chunk_id": "chunk_3147dcff", + "text": "Implicit accesses, including instruction fetches to an SS page, are not permitted.", + "source_file": "src/priv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Memory Protection", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 164, + 171 + ] + }, + { + "chunk_id": "chunk_c1f2e8e4", + "text": "Such accesses will raise an access-fault exception appropriate to the access type.", + "source_file": "src/priv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Memory Protection", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 164, + 171 + ] + }, + { + "chunk_id": "chunk_301e1065", + "text": "If a shadow stack (SS) instruction raises an access-fault, page-fault, or guest-page-fault exception that is supposed to indicate the original instruction type (load or store/AMO), then the reported exception cause is respectively a store/AMO access fault (code 7), a store/AMO page fault (code 15), or a store/AMO guest-page fault (code 23).", + "source_file": "src/priv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Memory Protection", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 173, + 180 + ] + }, + { + "chunk_id": "chunk_20916096", + "text": "Should a shadow stack instruction access a page that is not designated as a shadow stack page and is not marked as read-only (`pte.xwr=001`), a store/AMO access-fault exception will be invoked.", + "source_file": "src/priv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Memory Protection", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 182, + 187 + ] + }, + { + "chunk_id": "chunk_5b44518a", + "text": "Conversely, if the page being accessed by a shadow stack instruction is a read-only page, a store/AMO page-fault exception will be triggered.", + "source_file": "src/priv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Memory Protection", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 182, + 187 + ] + }, + { + "chunk_id": "chunk_8edde9db", + "text": "If the virtual address in `ssp` is not `XLEN` aligned, then the `SSPUSH`/ `C.SSPUSH`/`SSPOPCHK`/`C.SSPOPCHK` instructions cause a store/AMO access-fault exception.", + "source_file": "src/priv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Memory Protection", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 191, + 194 + ] + }, + { + "chunk_id": "chunk_4d03ceda", + "text": "If the memory referenced by `SSPUSH`/`C.SSPUSH`/`SSPOPCHK`/`C.SSPOPCHK`/`SSAMOSWAP.W/D` instructions is not idempotent, then the instructions cause a store/AMO access-fault exception.", + "source_file": "src/priv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Memory Protection", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 196, + 199 + ] + }, + { + "chunk_id": "chunk_8f51959d", + "text": "When G-stage page tables are active, the shadow stack instructions that access memory require the G-stage page table to have read-write permission for the accessed memory; else a store/AMO guest-page-fault exception is raised.", + "source_file": "src/priv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Memory Protection", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 206, + 210 + ] + }, + { + "chunk_id": "chunk_2f23258e", + "text": "The PMA checks are extended to require memory referenced by shadow stack instructions to be idempotent.", + "source_file": "src/priv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Memory Protection", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 214, + 218 + ] + }, + { + "chunk_id": "chunk_2b6e5817", + "text": "The PMP checks are extended to require read-write permission for memory accessed by shadow stack instructions.", + "source_file": "src/priv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Memory Protection", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 214, + 218 + ] + }, + { + "chunk_id": "chunk_e1318df1", + "text": "If the PMP does not provide read-write permissions or if the accessed memory is not idempotent then a store/AMO access-fault exception is raised.", + "source_file": "src/priv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Memory Protection", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 214, + 218 + ] + } + ] + }, + { + "file": "src/priv/csrs.adoc", + "chunks": [ + { + "chunk_id": "chunk_8973f82e", + "text": "The SYSTEM major opcode is used to encode all privileged instructions in the RISC-V ISA.", + "source_file": "src/priv/csrs.adoc", + "section": "Preamble > Control and Status Registers (CSRs)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 3, + 9 + ] + }, + { + "chunk_id": "chunk_1761e9f7", + "text": "These can be divided into two main classes: those that atomically read-modify-write control and status registers (CSRs), which are defined in the Zicsr extension, and all other privileged instructions.", + "source_file": "src/priv/csrs.adoc", + "section": "Preamble > Control and Status Registers (CSRs)", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 3, + 9 + ] + }, + { + "chunk_id": "chunk_23a6edb1", + "text": "The privileged architecture requires the Zicsr extension; which other privileged instructions are required depends on the privileged-architecture feature set.", + "source_file": "src/priv/csrs.adoc", + "section": "Preamble > Control and Status Registers (CSRs)", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 3, + 9 + ] + }, + { + "chunk_id": "chunk_195e0171", + "text": "In addition to the unprivileged state described in Volume I of this manual, an implementation may contain additional CSRs, accessible by some subset of the privilege levels using the CSR instructions described in .", + "source_file": "src/priv/csrs.adoc", + "section": "Preamble > Control and Status Registers (CSRs)", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 11, + 19 + ] + }, + { + "chunk_id": "chunk_c9e91ae1", + "text": "In this chapter, we map out the CSR address space.", + "source_file": "src/priv/csrs.adoc", + "section": "Preamble > Control and Status Registers (CSRs)", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 11, + 19 + ] + }, + { + "chunk_id": "chunk_69affc30", + "text": "The following chapters describe the function of each of the CSRs according to privilege level, as well as the other privileged instructions which are generally closely associated with a particular privilege level.", + "source_file": "src/priv/csrs.adoc", + "section": "Preamble > Control and Status Registers (CSRs)", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 11, + 19 + ] + }, + { + "chunk_id": "chunk_b708cd0f", + "text": "Standard CSRs do not have side effects on reads but may have side effects on writes.", + "source_file": "src/priv/csrs.adoc", + "section": "Preamble > Control and Status Registers (CSRs)", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 21, + 22 + ] + }, + { + "chunk_id": "chunk_8515789d", + "text": "The standard RISC-V ISA sets aside a 12-bit encoding space (csr[11:0]) for up to 4,096 CSRs.", + "source_file": "src/priv/csrs.adoc", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Address Mapping Conventions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 26, + 30 + ] + }, + { + "chunk_id": "chunk_5f25609a", + "text": "Instructions that access a non-existent CSR are reserved.", + "source_file": "src/priv/csrs.adoc", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Address Mapping Conventions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 32, + 38 + ] + }, + { + "chunk_id": "chunk_7952e257", + "text": "Attempts to access a CSR without appropriate privilege level raise illegal-instruction exceptions or, as described in , virtual-instruction exceptions.", + "source_file": "src/priv/csrs.adoc", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Address Mapping Conventions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 32, + 38 + ] + }, + { + "chunk_id": "chunk_2f29d175", + "text": "Attempts to write a read-only register raise illegal-instruction exceptions. A read/write register might also contain some bits that are read-only, in which case writes to the read-only bits are ignored.", + "source_file": "src/priv/csrs.adoc", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Address Mapping Conventions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "unknown", + "line_range": [ + 32, + 38 + ] + }, + { + "chunk_id": "chunk_6aa4f4cf", + "text": "also indicates the convention to allocate CSR addresses between standard and custom uses.", + "source_file": "src/priv/csrs.adoc", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Address Mapping Conventions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 40, + 43 + ] + }, + { + "chunk_id": "chunk_4031e959", + "text": "The CSR addresses designated for custom uses will not be redefined by future standard extensions.", + "source_file": "src/priv/csrs.adoc", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Address Mapping Conventions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 40, + 43 + ] + }, + { + "chunk_id": "chunk_b4453927", + "text": "Machine-mode standard read-write CSRs `0x7A0`-`0x7BF` are reserved for use by the debug system.", + "source_file": "src/priv/csrs.adoc", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Address Mapping Conventions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 45, + 50 + ] + }, + { + "chunk_id": "chunk_e415d9c1", + "text": "Of these CSRs, `0x7A0`-`0x7AF` are accessible to machine mode, whereas `0x7B0`-`0x7BF` are only visible to debug mode.", + "source_file": "src/priv/csrs.adoc", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Address Mapping Conventions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 45, + 50 + ] + }, + { + "chunk_id": "chunk_c8e046d9", + "text": "Implementations should raise illegal-instruction exceptions on machine-mode access to the latter set of registers.", + "source_file": "src/priv/csrs.adoc", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Address Mapping Conventions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 45, + 50 + ] + }, + { + "chunk_id": "chunk_06922558", + "text": "list the CSRs that have currently been allocated CSR addresses.", + "source_file": "src/priv/csrs.adoc", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 107, + 111 + ] + }, + { + "chunk_id": "chunk_6cfe6753", + "text": "The timers, counters, and floating-point CSRs are standard unprivileged CSRs.", + "source_file": "src/priv/csrs.adoc", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 107, + 111 + ] + }, + { + "chunk_id": "chunk_31441a1a", + "text": "The other registers are used by privileged code, as described in the following chapters.", + "source_file": "src/priv/csrs.adoc", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 107, + 111 + ] + }, + { + "chunk_id": "chunk_32e53083", + "text": "4+^|Unprivileged Zicfiss extension CSR |`0x011` + |URW + |`ssp` + |Shadow Stack Pointer. +", + "source_file": "src/priv/csrs.adoc", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V unprivileged CSR addresses", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 166, + 170 + ] + }, + { + "chunk_id": "chunk_3826acc6", + "text": "4+^|Unprivileged Entropy Source Extension CSR |`0x015` + |URW + |`seed` + |Seed for cryptographic random bit generators. +", + "source_file": "src/priv/csrs.adoc", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V unprivileged CSR addresses", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 172, + 176 + ] + }, + { + "chunk_id": "chunk_a41af058", + "text": "|`0xC00` + `0xC01` + `0xC02` + `0xC03` + `0xC04` + {nbsp} + `0xC1F` + `0xC80` + `0xC81` + `0xC82` + `0xC83` + `0xC84` + {nbsp} + `0xC9F` |URO + URO + URO + URO + URO + {nbsp} + URO + URO + URO + URO + URO + URO + {nbsp} + URO |`cycle` + `time` + `instret` + `hpmcounter3` + `hpmcounter4` + {vertical-ellipsis} + `hpmcounter31` + `cycleh` + `timeh` + `instreth` + `hpmcounter3h` + `hpmcounter4h` + {vertical-ellipsis} + `hpmcounter31h` |Cycle counter for RDCYCLE instruction. + Timer for RDTIME instruction. + Instructions-retired counter for RDINSTRET instruction. + Performance-monitoring counter. + Performance-monitoring counter. + {nbsp} + Performance-monitoring counter. + Upper 32 bits of `cycle`, RV32 only. + Upper 32 bits of `time`, RV32 only. + Upper 32 bits of `instret`, RV32 only. + Upper 32 bits of `hpmcounter3`, RV32 only. + Upper 32 bits of `hpmcounter4`, RV32 only. + {nbsp} + Upper 32 bits of `hpmcounter31`, RV32 only. |", + "source_file": "src/priv/csrs.adoc", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V unprivileged CSR addresses", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 186, + 242 + ] + }, + { + "chunk_id": "chunk_071fe19c", + "text": "|`0x10A` |SRW |`senvcfg` |Supervisor environment configuration register.", + "source_file": "src/priv/csrs.adoc", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V supervisor-level CSR addresses", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 274, + 274 + ] + }, + { + "chunk_id": "chunk_4b18d62a", + "text": "|`0x120` |SRW |`scountinhibit` |Supervisor counter-inhibit register.", + "source_file": "src/priv/csrs.adoc", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V supervisor-level CSR addresses", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 278, + 278 + ] + }, + { + "chunk_id": "chunk_0ef5e8e1", + "text": "|`0x180` |SRW |`satp` |Supervisor address translation and protection.", + "source_file": "src/priv/csrs.adoc", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V supervisor-level CSR addresses", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 340, + 340 + ] + }, + { + "chunk_id": "chunk_2d327a9c", + "text": "|`0x14D` + `0x15D` |SRW + SRW |`stimecmp` + `stimecmph` |Supervisor timer compare. + Upper 32 bits of `stimecmp`, RV32 only.", + "source_file": "src/priv/csrs.adoc", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V supervisor-level CSR addresses", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 344, + 351 + ] + }, + { + "chunk_id": "chunk_ad9b9893", + "text": "|`0x5A8` |SRW |`scontext` |Supervisor-mode context register.", + "source_file": "src/priv/csrs.adoc", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V supervisor-level CSR addresses", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 355, + 355 + ] + }, + { + "chunk_id": "chunk_9fea1677", + "text": "4+^|Supervisor Resource Management Configuration |`0x181` |SRW |`srmcfg` |Supervisor Resource Management Configuration.", + "source_file": "src/priv/csrs.adoc", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V supervisor-level CSR addresses", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 357, + 358 + ] + }, + { + "chunk_id": "chunk_8bb4e513", + "text": "|`0x643` + `0x644` + `0x645` + `0x64A` + `0xE12` |HRW + HRW + HRW + HRW + HRO |`htval` + `hip` + `hvip` + `htinst` + `hgeip` |Hypervisor trap value. + Hypervisor interrupt pending. + Hypervisor virtual interrupt pending. + Hypervisor trap instruction (transformed). + Hypervisor guest external interrupt pending.", + "source_file": "src/priv/csrs.adoc", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V hypervisor and VS CSR addresses", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 436, + 455 + ] + }, + { + "chunk_id": "chunk_aa44c34d", + "text": "|`0x680` |HRW |`hgatp` |Hypervisor guest address translation and protection.", + "source_file": "src/priv/csrs.adoc", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V hypervisor and VS CSR addresses", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 470, + 470 + ] + }, + { + "chunk_id": "chunk_af5d8ec8", + "text": "|`0x6A8` |HRW |`hcontext` |Hypervisor-mode context register.", + "source_file": "src/priv/csrs.adoc", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V hypervisor and VS CSR addresses", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 474, + 474 + ] + }, + { + "chunk_id": "chunk_778dc272", + "text": "|`0x605` + `0x615` |HRW + HRW |`htimedelta` + `htimedeltah` |Delta for VS/VU-mode timer. + Upper 32 bits of `htimedelta`, RV32 only.", + "source_file": "src/priv/csrs.adoc", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V hypervisor and VS CSR addresses", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 478, + 485 + ] + }, + { + "chunk_id": "chunk_f3a3ec8c", + "text": "|`0x24D` + `0x25D` |HRW + HRW |`vstimecmp` + `vstimecmph` |Virtual supervisor timer compare. + Upper 32 bits of `vstimecmp`, RV32 only.", + "source_file": "src/priv/csrs.adoc", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V hypervisor and VS CSR addresses", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 593, + 600 + ] + }, + { + "chunk_id": "chunk_32483a30", + "text": "|`0xF11` + `0xF12` + `0xF13` + `0xF14` + `0xF15` |MRO + MRO + MRO + MRO + MRO |`mvendorid` + `marchid` + `mimpid` + `mhartid` + `mconfigptr` |Vendor ID. + Architecture ID. + Implementation ID. + Hardware thread ID. + Pointer to configuration data structure.", + "source_file": "src/priv/csrs.adoc", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V machine-level CSR addresses", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 622, + 641 + ] + }, + { + "chunk_id": "chunk_d86a030e", + "text": "|`0xB00` + `0xB02` + `0xB03` + `0xB04` + {nbsp} + `0xB1F` + `0xB80` + `0xB82` + `0xB83` + `0xB84` + {nbsp} + `0xB9F` |MRW + MRW + MRW + MRW + {nbsp} + MRW + MRW + MRW + MRW + MRW + {nbsp} + MRW + |`mcycle` + `minstret` + `mhpmcounter3` + `mhpmcounter4` + {vertical-ellipsis} + `mhpmcounter31` + `mcycleh` + `minstreth` + `mhpmcounter3h` + `mhpmcounter4h` + {vertical-ellipsis} + `mhpmcounter31h` |Machine cycle counter. + Machine instructions-retired counter. + Machine performance-monitoring counter. + Machine performance-monitoring counter. + {nbsp} + Machine performance-monitoring counter. + Upper 32 bits of `mcycle`, RV32 only. + Upper 32 bits of `minstret`, RV32 only. + Upper 32 bits of `mhpmcounter3`, RV32 only. + Upper 32 bits of `mhpmcounter4`, RV32 only. + {nbsp} + Upper 32 bits of `mhpmcounter31`, RV32 only.", + "source_file": "src/priv/csrs.adoc", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V machine-level CSR addresses", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 865, + 912 + ] + }, + { + "chunk_id": "chunk_c6c8e934", + "text": "|`0x7A0` + `0x7A1` + `0x7A2` + `0x7A3` + `0x7A4` + `0x7A5` + `0x7A8` |MRW + MRW + MRW + MRW + MRW + MRW + MRW |`tselect` + `tdata1` + `tdata2` + `tdata3` + `tinfo` + `tcontrol` + `mcontext`", + "source_file": "src/priv/csrs.adoc", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V machine-level CSR addresses", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 977, + 997 + ] + }, + { + "chunk_id": "chunk_ba07850f", + "text": "The following definitions and abbreviations are used in specifying the behavior of fields within the CSRs.", + "source_file": "src/priv/csrs.adoc", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Field Specifications", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1111, + 1112 + ] + }, + { + "chunk_id": "chunk_1fbc611a", + "text": "Some whole read/write fields are reserved for future use.", + "source_file": "src/priv/csrs.adoc", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Field Specifications > Reserved Writes Preserve Values, Reads Ignore Values (WPRI)", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1116, + 1121 + ] + }, + { + "chunk_id": "chunk_abb3faf2", + "text": "Software should ignore the values read from these fields, and should preserve the values held in these fields when writing values to other fields of the same register.", + "source_file": "src/priv/csrs.adoc", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Field Specifications > Reserved Writes Preserve Values, Reads Ignore Values (WPRI)", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 1116, + 1121 + ] + }, + { + "chunk_id": "chunk_14450f18", + "text": "For forward compatibility, implementations that do not furnish these fields must make them read-only zero.", + "source_file": "src/priv/csrs.adoc", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Field Specifications > Reserved Writes Preserve Values, Reads Ignore Values (WPRI)", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 1116, + 1121 + ] + }, + { + "chunk_id": "chunk_03a2da4f", + "text": "These fields are labeled *WPRI* in the register descriptions.", + "source_file": "src/priv/csrs.adoc", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Field Specifications > Reserved Writes Preserve Values, Reads Ignore Values (WPRI)", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1116, + 1121 + ] + }, + { + "chunk_id": "chunk_d8593f3b", + "text": "Some read/write CSR fields specify behavior for only a subset of possible bit encodings, with other bit encodings reserved.", + "source_file": "src/priv/csrs.adoc", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Field Specifications > Write/Read Only Legal Values (WLRL)", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1125, + 1132 + ] + }, + { + "chunk_id": "chunk_fa70d9e3", + "text": "These fields are labeled *WLRL* in the register descriptions.", + "source_file": "src/priv/csrs.adoc", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Field Specifications > Write/Read Only Legal Values (WLRL)", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1125, + 1132 + ] + }, + { + "chunk_id": "chunk_7562b968", + "text": "Implementations are permitted but not required to raise an illegal-instruction exception if an instruction attempts to write a non-supported value to a *WLRL* field.", + "source_file": "src/priv/csrs.adoc", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Field Specifications > Write/Read Only Legal Values (WLRL)", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1134, + 1140 + ] + }, + { + "chunk_id": "chunk_20b33988", + "text": "Implementations can return arbitrary bit patterns on the read of a *WLRL* field when the last write was of an illegal value, but the value returned should deterministically depend on the illegal written value and the value of the field prior to the write.", + "source_file": "src/priv/csrs.adoc", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Field Specifications > Write/Read Only Legal Values (WLRL)", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1134, + 1140 + ] + }, + { + "chunk_id": "chunk_7ee5d986", + "text": "Some read/write CSR fields are only defined for a subset of bit encodings, but allow any value to be written while guaranteeing to return a legal value whenever read.", + "source_file": "src/priv/csrs.adoc", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Field Specifications > Write Any Values, Reads Legal Values (WARL)", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1144, + 1149 + ] + }, + { + "chunk_id": "chunk_1a19fc57", + "text": "Assuming that writing the CSR has no other side effects, the range of supported values can be determined by attempting to write a desired setting then reading to see if the value was retained.", + "source_file": "src/priv/csrs.adoc", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Field Specifications > Write Any Values, Reads Legal Values (WARL)", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1144, + 1149 + ] + }, + { + "chunk_id": "chunk_53d8f04a", + "text": "These fields are labeled *WARL* in the register descriptions.", + "source_file": "src/priv/csrs.adoc", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Field Specifications > Write Any Values, Reads Legal Values (WARL)", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1144, + 1149 + ] + }, + { + "chunk_id": "chunk_0bf5f0a3", + "text": "Implementations will not raise an exception on writes of unsupported values to a *WARL* field.", + "source_file": "src/priv/csrs.adoc", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Field Specifications > Write Any Values, Reads Legal Values (WARL)", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1151, + 1155 + ] + }, + { + "chunk_id": "chunk_ef21f46d", + "text": "Implementations can return any legal value on the read of a *WARL* field when the last write was of an illegal value, but the legal value returned should deterministically depend on the illegal written value and the architectural state of the hart.", + "source_file": "src/priv/csrs.adoc", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Field Specifications > Write Any Values, Reads Legal Values (WARL)", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1151, + 1155 + ] + }, + { + "chunk_id": "chunk_b64d2a9a", + "text": "If a write to one CSR changes the set of legal values allowed for a field of a second CSR, then unless specified otherwise, the second CSR's field immediately gets an `UNSPECIFIED` value from among its new legal values.", + "source_file": "src/priv/csrs.adoc", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Field Modulation", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1160, + 1165 + ] + }, + { + "chunk_id": "chunk_cb7e1ef1", + "text": "This is true even if the field's value before the write remains legal after the write; the value of the field may be changed in consequence of the write to the controlling CSR.", + "source_file": "src/priv/csrs.adoc", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Field Modulation", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1160, + 1165 + ] + }, + { + "chunk_id": "chunk_90cd85d3", + "text": "A change to the value of a CSR for this reason is not a write to the affected CSR and thus does not trigger any side effects specified for that CSR.", + "source_file": "src/priv/csrs.adoc", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Field Modulation", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1167, + 1169 + ] + }, + { + "chunk_id": "chunk_4c5b98e0", + "text": "Unless otherwise specified, the value returned by an implicit read of a CSR is the same value that would have been returned by an explicit read of the CSR, using a CSR-access instruction in a sufficient privilege mode.", + "source_file": "src/priv/csrs.adoc", + "section": "Preamble > Control and Status Registers (CSRs) > Implicit Reads of CSRs", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1173, + 1178 + ] + }, + { + "chunk_id": "chunk_07c6b7c0", + "text": "The value of the previous-width CSR is copied to a temporary register of the same width. .", + "source_file": "src/priv/csrs.adoc", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Width Modulation", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1189, + 1200 + ] + }, + { + "chunk_id": "chunk_5ca0363f", + "text": "For the read-only bits of the previous-width CSR, the bits at the same positions in the temporary register are set to zeros. .", + "source_file": "src/priv/csrs.adoc", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Width Modulation", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 1189, + 1200 + ] + }, + { + "chunk_id": "chunk_c71ffae5", + "text": "The width of the temporary register is changed to the new width.", + "source_file": "src/priv/csrs.adoc", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Width Modulation", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1189, + 1200 + ] + }, + { + "chunk_id": "chunk_fe6d10f9", + "text": "If the new width W is narrower than the previous width, the least-significant W bits of the temporary register are retained and the more-significant bits are discarded.", + "source_file": "src/priv/csrs.adoc", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Width Modulation", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1189, + 1200 + ] + }, + { + "chunk_id": "chunk_95385ee7", + "text": "If the new width is wider than the previous width, the temporary register is zero-extended to the wider width. .", + "source_file": "src/priv/csrs.adoc", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Width Modulation", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 1189, + 1200 + ] + }, + { + "chunk_id": "chunk_5d2561dc", + "text": "Each writable field of the new-width CSR takes the value of the bits at the same positions in the temporary register.", + "source_file": "src/priv/csrs.adoc", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Width Modulation", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1189, + 1200 + ] + }, + { + "chunk_id": "chunk_0a6e8125", + "text": "Changing the width of a CSR is not a read or write of the CSR and thus does not trigger any side effects.", + "source_file": "src/priv/csrs.adoc", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Width Modulation", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1202, + 1203 + ] + }, + { + "chunk_id": "chunk_44ae5740", + "text": "If a standard CSR is wider than XLEN bits, then an explicit read of the CSR returns the register's least-significant XLEN bits, and an explicit write to the CSR modifies only the register's least-significant XLEN bits, leaving the upper bits unchanged.", + "source_file": "src/priv/csrs.adoc", + "section": "Preamble > Control and Status Registers (CSRs) > Explicit Accesses to CSRs Wider than XLEN", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 1207, + 1210 + ] + }, + { + "chunk_id": "chunk_150dc5ef", + "text": "Some standard CSRs, such as the counter CSRs of extension Zicntr, are always 64 bits, even when XLEN=32 (RV32).", + "source_file": "src/priv/csrs.adoc", + "section": "Preamble > Control and Status Registers (CSRs) > Explicit Accesses to CSRs Wider than XLEN", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 1212, + 1219 + ] + }, + { + "chunk_id": "chunk_a99f7976", + "text": "The high-half CSR aliases bits 63:32 of its namesake 64-bit CSR, thus providing a way for RV32 software to read and modify the otherwise-unreachable 32 bits.", + "source_file": "src/priv/csrs.adoc", + "section": "Preamble > Control and Status Registers (CSRs) > Explicit Accesses to CSRs Wider than XLEN", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 1212, + 1219 + ] + }, + { + "chunk_id": "chunk_17883028", + "text": "Standard high-half CSRs are accessible only when the base RISC-V instruction set is RV32 (XLEN=32).", + "source_file": "src/priv/csrs.adoc", + "section": "Preamble > Control and Status Registers (CSRs) > Explicit Accesses to CSRs Wider than XLEN", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1221, + 1225 + ] + } + ] + }, + { + "file": "src/priv/hypervisor.adoc", + "chunks": [ + { + "chunk_id": "chunk_978f94ca", + "text": "The hypervisor extension also adds another stage of address translation, from guest physical addresses to supervisor physical addresses, to virtualize the memory and memory-mapped I/O subsystems for a guest operating system. HS-mode acts the same as S-mode, but with additional instructions and CSRs that control the new stage of address translation and support hosting a guest OS in virtual S-mode (VS-mode).", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 3, + 16 + ] + }, + { + "chunk_id": "chunk_f8e9c67f", + "text": "The hypervisor extension depends on an \"I\" base integer ISA with 32 `x` registers (RV32I or RV64I), not RV32E or RV64E, which have only 16 `x` registers. CSR `mtval` must not be read-only zero, and standard page-based address translation must be supported, either Sv32 for RV32, or a minimum of Sv39 for RV64.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 22, + 27 + ] + }, + { + "chunk_id": "chunk_0772dc6e", + "text": "The hypervisor extension is enabled by setting bit 7 in the `misa` CSR, which corresponds to the letter H. RISC-V harts that implement the hypervisor extension are encouraged not to hardwire `misa`[7], so that the extension may be disabled.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 29, + 32 + ] + }, + { + "chunk_id": "chunk_fec2dc68", + "text": "When V=1, the hart is either in virtual S-mode (VS-mode), or in virtual U-mode (VU-mode) atop a guest OS running in VS-mode.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Privilege Modes", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 36, + 43 + ] + }, + { + "chunk_id": "chunk_dd3c76fa", + "text": "When V=0, the hart is either in M-mode, in HS-mode, or in U-mode atop an OS running in HS-mode.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Privilege Modes", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 36, + 43 + ] + }, + { + "chunk_id": "chunk_0bf19a46", + "text": "HS-mode is more privileged than VS-mode, and VS-mode is more privileged than VU-mode. VS-mode interrupts are globally disabled when executing in U-mode.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Privilege Modes", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 84, + 86 + ] + }, + { + "chunk_id": "chunk_df991e2a", + "text": "An OS or hypervisor running in HS-mode uses the supervisor CSRs to interact with the exception, interrupt, and address-translation subsystems.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 90, + 96 + ] + }, + { + "chunk_id": "chunk_9233c38a", + "text": "Additional CSRs are provided to HS-mode, but not to VS-mode, to manage two-stage address translation and to control the behavior of a VS-mode guest: `hstatus`, `hedeleg`, `hideleg`, `hvip`, `hip`, `hie`, `hgeip`, `hgeie`, `henvcfg`, `henvcfgh`, `hcounteren`, `htimedelta`, `htimedeltah`, `htval`, `htinst`, and `hgatp`.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 90, + 96 + ] + }, + { + "chunk_id": "chunk_9547554a", + "text": "Furthermore, several virtual supervisor CSRs (VS CSRs) are replicas of the normal supervisor CSRs.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 98, + 100 + ] + }, + { + "chunk_id": "chunk_27ede16e", + "text": "When V=1, the VS CSRs substitute for the corresponding supervisor CSRs, taking over all functions of the usual supervisor CSRs except as specified otherwise.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 102, + 112 + ] + }, + { + "chunk_id": "chunk_7fa9df86", + "text": "Instructions that normally read or modify a supervisor CSR shall instead access the corresponding VS CSR.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 102, + 112 + ] + }, + { + "chunk_id": "chunk_6cb618c4", + "text": "When V=1, an attempt to read or write a VS CSR directly by its own separate CSR address causes a virtual-instruction exception. (Attempts from U-mode cause an illegal-instruction exception as usual.) The VS CSRs can be accessed as themselves only from M-mode or HS-mode.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 102, + 112 + ] + }, + { + "chunk_id": "chunk_a55dd77e", + "text": "While V=1, the normal HS-level supervisor CSRs that are replaced by VS CSRs retain their values but do not affect the behavior of the machine unless specifically documented to do so.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 114, + 119 + ] + }, + { + "chunk_id": "chunk_abcc9cc8", + "text": "Conversely, when V=0, the VS CSRs do not ordinarily affect the behavior of the machine other than being readable and writable by CSR instructions.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 114, + 119 + ] + }, + { + "chunk_id": "chunk_ee27cde6", + "text": "Some standard supervisor CSRs (`senvcfg`, `scounteren`, and `scontext`, possibly others) have no matching VS CSR.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 121, + 127 + ] + }, + { + "chunk_id": "chunk_60eb6058", + "text": "These supervisor CSRs continue to have their usual function and accessibility even when V=1, except with VS-mode and VU-mode substituting for HS-mode and U-mode.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 121, + 127 + ] + }, + { + "chunk_id": "chunk_613537f6", + "text": "Hypervisor software is expected to manually swap the contents of these registers as needed.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 121, + 127 + ] + }, + { + "chunk_id": "chunk_09143b61", + "text": "In this chapter, we use the term HSXLEN to refer to the effective XLEN when executing in HS-mode, and VSXLEN to refer to the effective XLEN when executing in VS-mode.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 129, + 131 + ] + }, + { + "chunk_id": "chunk_0ae2358b", + "text": "The `hstatus` register is an HSXLEN-bit read/write register formatted as shown in when HSXLEN=32 and when HSXLEN=64.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 136, + 141 + ] + }, + { + "chunk_id": "chunk_ba4e5934", + "text": "The `hstatus` register provides facilities analogous to the `mstatus` register for tracking and controlling the exception behavior of a VS-mode guest.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 136, + 141 + ] + }, + { + "chunk_id": "chunk_c468caa2", + "text": "The VSXL field controls the effective XLEN for VS-mode (known as VSXLEN), which may differ from the XLEN for HS-mode (HSXLEN).", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 189, + 195 + ] + }, + { + "chunk_id": "chunk_6a9021d4", + "text": "When HSXLEN=32, the VSXL field does not exist, and VSXLEN=32.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 189, + 195 + ] + }, + { + "chunk_id": "chunk_ae7d7dc2", + "text": "When HSXLEN=64, VSXL is a *WARL* field that is encoded the same as the MXL field of `misa`, shown in .", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 189, + 195 + ] + }, + { + "chunk_id": "chunk_03f4910a", + "text": "In particular, an implementation may make VSXL be a read-only field whose value always ensures that VSXLEN=HSXLEN.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 189, + 195 + ] + }, + { + "chunk_id": "chunk_d82a1e36", + "text": "If HSXLEN is changed from 32 to a wider width, and if field VSXL is not restricted to a single value, it gets the value corresponding to the widest supported width not wider than the new HSXLEN.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 197, + 200 + ] + }, + { + "chunk_id": "chunk_5204d0f7", + "text": "The `hstatus` fields VTSR, VTW, and VTVM are defined analogously to the `mstatus` fields TSR, TW, and TVM, but affect execution only in VS-mode, and cause virtual-instruction exceptions instead of illegal-instruction exceptions.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 202, + 217 + ] + }, + { + "chunk_id": "chunk_b0afdd82", + "text": "When VTSR=1, an attempt in VS-mode to execute SRET raises a virtual-instruction exception.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 202, + 217 + ] + }, + { + "chunk_id": "chunk_b4adc736", + "text": "When VTW=1 (and assuming `mstatus`.TW=0), an attempt in VS-mode to execute WFI raises a virtual-instruction exception if the WFI does not complete within an implementation-specific, bounded time limit.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 202, + 217 + ] + }, + { + "chunk_id": "chunk_c87d27b0", + "text": "An implementation may have WFI always raise a virtual-instruction exception in VS-mode when VTW=1 (and `mstatus`.TW=0), even if there are pending globally-disabled interrupts when the instruction is executed.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 202, + 217 + ] + }, + { + "chunk_id": "chunk_84216ba4", + "text": "When VTVM=1, an attempt in VS-mode to execute SFENCE.VMA or SINVAL.VMA or to access CSR `satp` raises a virtual-instruction exception.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 202, + 217 + ] + }, + { + "chunk_id": "chunk_282eb716", + "text": "The VGEIN (Virtual Guest External Interrupt Number) field selects a guest external interrupt source for VS-level external interrupts. VGEIN is a *WLRL* field that must be able to hold values between zero and the maximum guest external interrupt number (known as GEILEN), inclusive.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 219, + 228 + ] + }, + { + "chunk_id": "chunk_f4be8e69", + "text": "When VGEIN=0, no guest external interrupt source is selected for VS-level external interrupts. GEILEN may be zero, in which case VGEIN may be read-only zero.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 219, + 228 + ] + }, + { + "chunk_id": "chunk_7e766ea5", + "text": "Guest external interrupts are explained in , and the use of VGEIN is covered further in .", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 219, + 228 + ] + }, + { + "chunk_id": "chunk_587ab908", + "text": "Field HU (Hypervisor in U-mode) controls whether the virtual-machine load/store instructions, HLV, HLVX, and HSV, can be used also in U-mode.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 230, + 235 + ] + }, + { + "chunk_id": "chunk_25c54336", + "text": "When HU=1, these instructions can be executed in U-mode the same as in HS-mode.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 230, + 235 + ] + }, + { + "chunk_id": "chunk_f0bf0b8d", + "text": "When HU=0, all hypervisor instructions cause an illegal-instruction exception in U-mode.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 230, + 235 + ] + }, + { + "chunk_id": "chunk_e7acfd3c", + "text": "When the Ssnpm extension is not implemented, the `HUPMM` field is read-only zero.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 237, + 246 + ] + }, + { + "chunk_id": "chunk_3c929465", + "text": "The `HUPMM` field is read-only zero for RV32.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 237, + 246 + ] + }, + { + "chunk_id": "chunk_213dabf9", + "text": "The SPV bit (Supervisor Previous Virtualization mode) is written by the implementation whenever a trap is taken into HS-mode.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 248, + 253 + ] + }, + { + "chunk_id": "chunk_1ac4c804", + "text": "Just as the SPP bit in `sstatus` is set to the (nominal) privilege mode at the time of the trap, the SPV bit in `hstatus` is set to the value of the virtualization mode V at the time of the trap.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 248, + 253 + ] + }, + { + "chunk_id": "chunk_11341b3a", + "text": "When an SRET instruction is executed when V=0, V is set to SPV.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 248, + 253 + ] + }, + { + "chunk_id": "chunk_c9168e52", + "text": "When V=1 and a trap is taken into HS-mode, bit SPVP (Supervisor Previous Virtual Privilege) is set to the nominal privilege mode at the time of the trap, the same as `sstatus`.SPP.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 255, + 261 + ] + }, + { + "chunk_id": "chunk_f171ae1f", + "text": "But if V=0 before a trap, SPVP is left unchanged on trap entry. SPVP controls the effective privilege of explicit memory accesses made by the virtual-machine load/store instructions, HLV, HLVX, and HSV.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 255, + 261 + ] + }, + { + "chunk_id": "chunk_f7fd13ab", + "text": "Field GVA (Guest Virtual Address) is written by the implementation whenever a trap is taken into HS-mode.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 263, + 268 + ] + }, + { + "chunk_id": "chunk_75e3bfd1", + "text": "For any trap (breakpoint, address misaligned, access fault, page fault, or guest-page fault) that writes a guest virtual address to `stval`, GVA is set to 1.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 263, + 268 + ] + }, + { + "chunk_id": "chunk_917dfca7", + "text": "For any other trap into HS-mode, GVA is set to 0.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 263, + 268 + ] + }, + { + "chunk_id": "chunk_dc452d7b", + "text": "The VSBE bit is a *WARL* field that controls the endianness of explicit memory accesses made from VS-mode.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 270, + 277 + ] + }, + { + "chunk_id": "chunk_97f67b28", + "text": "If VSBE=0, explicit load and store memory accesses made from VS-mode are little-endian, and if VSBE=1, they are big-endian. VSBE also controls the endianness of all implicit accesses to VS-level memory management data structures, such as page tables.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 270, + 277 + ] + }, + { + "chunk_id": "chunk_e96531a2", + "text": "An implementation may make VSBE a read-only field that always specifies the same endianness as HS-mode.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 270, + 277 + ] + }, + { + "chunk_id": "chunk_0d9405e9", + "text": "Register `hedeleg` is a 64-bit read/write register, formatted as shown in .", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Delegation (`hedeleg` and `hideleg`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 281, + 289 + ] + }, + { + "chunk_id": "chunk_860016c2", + "text": "Register `hideleg` is an HSXLEN-bit read/write register, formatted as shown in .", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Delegation (`hedeleg` and `hideleg`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 281, + 289 + ] + }, + { + "chunk_id": "chunk_ef20713e", + "text": "By default, all traps at any privilege level are handled in M-mode, though M-mode usually uses the `medeleg` and `mideleg` CSRs to delegate some traps to HS-mode.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Delegation (`hedeleg` and `hideleg`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 281, + 289 + ] + }, + { + "chunk_id": "chunk_473b8484", + "text": "The `hedeleg` and `hideleg` CSRs allow these traps to be further delegated to a VS-mode guest; their layout is the same as `medeleg` and `mideleg`.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Delegation (`hedeleg` and `hideleg`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 281, + 289 + ] + }, + { + "chunk_id": "chunk_dbadc194", + "text": "A synchronous trap that has been delegated to HS-mode (using `medeleg`) is further delegated to VS-mode if V=1 before the trap and the corresponding `hedeleg` bit is set.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Delegation (`hedeleg` and `hideleg`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 299, + 307 + ] + }, + { + "chunk_id": "chunk_7207d33f", + "text": "Each bit of `hedeleg` shall be either writable or read-only zero.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Delegation (`hedeleg` and `hideleg`) Registers", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 299, + 307 + ] + }, + { + "chunk_id": "chunk_a2418fac", + "text": "Many bits of `hedeleg` are required specifically to be writable or zero, as enumerated in .", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Delegation (`hedeleg` and `hideleg`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "unknown", + "line_range": [ + 299, + 307 + ] + }, + { + "chunk_id": "chunk_7da2366e", + "text": "Bit 0, corresponding to instruction address-misaligned exceptions, must be writable if IALIGN=32.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Delegation (`hedeleg` and `hideleg`) Registers", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 299, + 307 + ] + }, + { + "chunk_id": "chunk_478a81a9", + "text": "When XLEN=32, `hedelegh` is a 32-bit read/write register that aliases bits 63:32 of `hedeleg`.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Delegation (`hedeleg` and `hideleg`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 309, + 312 + ] + }, + { + "chunk_id": "chunk_38ab83c6", + "text": "Register `hedelegh` does not exist when XLEN=64.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Delegation (`hedeleg` and `hideleg`) Registers", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 309, + 312 + ] + }, + { + "chunk_id": "chunk_1e91f319", + "text": "An interrupt that has been delegated to HS-mode (using `mideleg`) is further delegated to VS-mode if the corresponding `hideleg` bit is set.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Delegation (`hedeleg` and `hideleg`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 314, + 318 + ] + }, + { + "chunk_id": "chunk_e24ee0ef", + "text": "Among bits 15:0 of `hideleg`, bits 10, 6, and 2 (corresponding to the standard VS-level interrupts) are writable, and bits 12, 9, 5, and 1 (corresponding to the standard S-level interrupts) are read-only zeros.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Delegation (`hedeleg` and `hideleg`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 314, + 318 + ] + }, + { + "chunk_id": "chunk_ea32b351", + "text": "When a virtual supervisor external interrupt (code 10) is delegated to VS-mode, it is automatically translated by the machine into a supervisor external interrupt (code 9) for VS-mode, including the value written to `vscause` on an interrupt trap.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Delegation (`hedeleg` and `hideleg`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 320, + 329 + ] + }, + { + "chunk_id": "chunk_6ebcd725", + "text": "Likewise, a virtual supervisor timer interrupt (6) is translated into a supervisor timer interrupt (5) for VS-mode, and a virtual supervisor software interrupt (2) is translated into a supervisor software interrupt (1) for VS-mode.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Delegation (`hedeleg` and `hideleg`) Registers", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 320, + 329 + ] + }, + { + "chunk_id": "chunk_50dad419", + "text": "Similar translations may or may not be done for platform interrupt causes (codes 16 and above).", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Delegation (`hedeleg` and `hideleg`) Registers", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 320, + 329 + ] + }, + { + "chunk_id": "chunk_af3e8801", + "text": "Bits of `hvip` that are not writable are read-only zeros.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 407, + 410 + ] + }, + { + "chunk_id": "chunk_3279daec", + "text": "The standard portion (bits 15:0) of `hvip` is formatted as shown in .", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 416, + 421 + ] + }, + { + "chunk_id": "chunk_5bf211fa", + "text": "Bits VSEIP, VSTIP, and VSSIP of `hvip` are writable.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 416, + 421 + ] + }, + { + "chunk_id": "chunk_00bc912b", + "text": "Setting VSEIP=1 in `hvip` asserts a VS-level external interrupt; setting VSTIP asserts a VS-level timer interrupt; and setting VSSIP asserts a VS-level software interrupt.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 416, + 421 + ] + }, + { + "chunk_id": "chunk_f6dedaae", + "text": "Registers `hip` and `hie` are HSXLEN-bit read/write registers that supplement HS-level\u2019s `sip` and `sie` respectively.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 427, + 430 + ] + }, + { + "chunk_id": "chunk_60678899", + "text": "The `hip` register indicates pending VS-level and hypervisor-specific interrupts, while `hie` contains enable bits for the same interrupts.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 427, + 430 + ] + }, + { + "chunk_id": "chunk_54d27c3d", + "text": "For each writable bit in `sie`, the corresponding bit shall be read-only zero in both `hip` and `hie`.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 440, + 443 + ] + }, + { + "chunk_id": "chunk_d2856ad9", + "text": "Hence, the nonzero bits in `sie` and `hie` are always mutually exclusive, and likewise for `sip` and `hip`.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 440, + 443 + ] + }, + { + "chunk_id": "chunk_b43173ba", + "text": "An interrupt i will trap to HS-mode whenever all of the following are true: (a) either the current operating mode is HS-mode and the SIE bit in the `sstatus` register is set, or the current operating mode has less privilege than HS-mode; (b) bit i is set in both `sip` and `sie`, or in both `hip` and `hie`; and (c) bit i is not set in `hideleg`.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 445, + 450 + ] + }, + { + "chunk_id": "chunk_ce60e658", + "text": "If bit i of `sie` is read-only zero, the same bit in register `hip` may be writable or may be read-only.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 452, + 460 + ] + }, + { + "chunk_id": "chunk_bda1083e", + "text": "When bit i in `hip` is writable, a pending interrupt i can be cleared by writing 0 to this bit.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "unknown", + "line_range": [ + 452, + 460 + ] + }, + { + "chunk_id": "chunk_11f13a4f", + "text": "If interrupt i can become pending in `hip` but bit i in `hip` is read-only, then either the interrupt can be cleared by clearing bit i of `hvip`, or the implementation must provide some other mechanism for clearing the pending interrupt (which may involve a call to the execution environment).", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 452, + 460 + ] + }, + { + "chunk_id": "chunk_20cc37b8", + "text": "A bit in `hie` shall be writable if the corresponding interrupt can ever become pending in `hip`.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 462, + 465 + ] + }, + { + "chunk_id": "chunk_cac016a5", + "text": "Bits of `hie` that are not writable shall be read-only zero.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 462, + 465 + ] + }, + { + "chunk_id": "chunk_a97b8e16", + "text": "The standard portions (bits 15:0) of registers `hip` and `hie` are formatted as shown in and respectively.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 467, + 468 + ] + }, + { + "chunk_id": "chunk_f8b09508", + "text": "Bits `hip`.VSEIP and `hie`.VSEIE are the interrupt-pending and interrupt-enable bits for VS-level external interrupts. VSEIP is read-only in `hip`, and is the logical-OR of these interrupt sources:", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "unknown", + "line_range": [ + 485, + 488 + ] + }, + { + "chunk_id": "chunk_f635a34d", + "text": "bit VSEIP of `hvip`; * the bit of `hgeip` selected by `hstatus`.VGEIN; and * any other platform-specific external interrupt signal directed to VS-level.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 490, + 493 + ] + }, + { + "chunk_id": "chunk_46e206e8", + "text": "Bits `hip`.VSTIP and `hie`.VSTIE are the interrupt-pending and interrupt-enable bits for VS-level timer interrupts. VSTIP is read-only in `hip`, and is the logical-OR of `hvip`.VSTIP and, when the Sstc extension is implemented, the timer interrupt signal resulting from `vstimecmp`.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "unknown", + "line_range": [ + 495, + 503 + ] + }, + { + "chunk_id": "chunk_7a63e393", + "text": "The `hip`.VSTIP bit, in response to timer interrupts generated by `vstimecmp`, is set by writing `vstimecmp` with a value that is less than or equal to the sum of `time` and `htimedelta`, truncated to 64 bits; it is cleared by writing `vstimecmp` with a greater value.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 495, + 503 + ] + }, + { + "chunk_id": "chunk_8ee96054", + "text": "The `hip`.VSTIP bit remains defined while V=0 as well as V=1.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 495, + 503 + ] + }, + { + "chunk_id": "chunk_4b1e5ff3", + "text": "Bits `hip`.VSSIP and `hie`.VSSIE are the interrupt-pending and interrupt-enable bits for VS-level software interrupts. VSSIP in `hip` is an alias (writable) of the same bit in `hvip`.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 505, + 508 + ] + }, + { + "chunk_id": "chunk_ceb13eee", + "text": "Multiple simultaneous interrupts destined for HS-mode are handled in the following decreasing priority order: SEI, SSI, STI, SGEI, VSEI, VSSI, VSTI, LCOFI.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 510, + 513 + ] + }, + { + "chunk_id": "chunk_ebfc1a5c", + "text": "The `hgeip` register is an HSXLEN-bit read-only register, formatted as shown in , that indicates pending guest external interrupts for this hart.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest External Interrupt Registers (`hgeip` and `hgeie`)", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 518, + 525 + ] + }, + { + "chunk_id": "chunk_752a82b3", + "text": "The `hgeie` register is an HSXLEN-bit read/write register, formatted as shown in , that contains enable bits for the guest external interrupts at this hart.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest External Interrupt Registers (`hgeip` and `hgeie`)", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 518, + 525 + ] + }, + { + "chunk_id": "chunk_7f7ed18a", + "text": "Guest external interrupt number i corresponds with bit i in both `hgeip` and `hgeie`.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest External Interrupt Registers (`hgeip` and `hgeie`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 518, + 525 + ] + }, + { + "chunk_id": "chunk_6b44d8d5", + "text": "Guest external interrupts represent interrupts directed to individual virtual machines at VS-level.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest External Interrupt Registers (`hgeip` and `hgeie`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 535, + 544 + ] + }, + { + "chunk_id": "chunk_f594f86d", + "text": "Each bit of `hgeip` summarizes all pending interrupts directed to one virtual hart, as collected and reported by an interrupt controller.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest External Interrupt Registers (`hgeip` and `hgeie`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 535, + 544 + ] + }, + { + "chunk_id": "chunk_dd80bf5e", + "text": "To distinguish specific pending interrupts from multiple devices, software must query the interrupt controller.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest External Interrupt Registers (`hgeip` and `hgeie`)", + "confidence": "very_high", + "parameter_class": "SW_rule", + "parameter_type": "binary", + "line_range": [ + 535, + 544 + ] + }, + { + "chunk_id": "chunk_99c9a65d", + "text": "The number of bits implemented in `hgeip` and `hgeie` for guest external interrupts is UNSPECIFIED and may be zero.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest External Interrupt Registers (`hgeip` and `hgeie`)", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 546, + 552 + ] + }, + { + "chunk_id": "chunk_d71021bd", + "text": "This number is known as GEILEN.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest External Interrupt Registers (`hgeip` and `hgeie`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 546, + 552 + ] + }, + { + "chunk_id": "chunk_7b3b1dda", + "text": "The least-significant bits are implemented first, apart from bit 0.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest External Interrupt Registers (`hgeip` and `hgeie`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 546, + 552 + ] + }, + { + "chunk_id": "chunk_117d05f7", + "text": "Hence, if GEILEN is nonzero, bits GEILEN:1 shall be writable in `hgeie`, and all other bit positions shall be read-only zeros in both `hgeip` and `hgeie`.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest External Interrupt Registers (`hgeip` and `hgeie`)", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 546, + 552 + ] + }, + { + "chunk_id": "chunk_8a8aac3e", + "text": "Register `hgeie` selects the subset of guest external interrupts that cause a supervisor-level (HS-level) guest external interrupt.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest External Interrupt Registers (`hgeip` and `hgeie`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 554, + 558 + ] + }, + { + "chunk_id": "chunk_45d737e4", + "text": "The enable bits in `hgeie` do not affect the VS-level external interrupt signal selected from `hgeip` by `hstatus`.VGEIN.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest External Interrupt Registers (`hgeip` and `hgeie`)", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 554, + 558 + ] + }, + { + "chunk_id": "chunk_608bb538", + "text": "The `henvcfg` CSR is a 64-bit read/write register, formatted as shown in , that controls certain characteristics of the execution environment when virtualization mode V=1.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 564, + 568 + ] + }, + { + "chunk_id": "chunk_96e3672e", + "text": "If bit FIOM (Fence of I/O implies Memory) is set to one in `henvcfg`, FENCE instructions executed when V=1 are modified so the requirement to order accesses to device I/O implies also the requirement to order main memory accesses. details the modified interpretation of FENCE instruction bits PI, PO, SI, and SO when FIOM=1 and V=1.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 593, + 599 + ] + }, + { + "chunk_id": "chunk_50c4380b", + "text": "Similarly, when FIOM=1 and V=1, if an atomic instruction that accesses a region ordered as device I/O has its aq and/or rl bit set, then that instruction is ordered as though it accesses both device I/O and memory.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 601, + 604 + ] + }, + { + "chunk_id": "chunk_18ba4999", + "text": "The PBMTE bit controls whether the Svpbmt extension is available for use in VS-stage address translation.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 621, + 626 + ] + }, + { + "chunk_id": "chunk_64924240", + "text": "When PBMTE=1, Svpbmt is available for VS-stage address translation.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 621, + 626 + ] + }, + { + "chunk_id": "chunk_5bd544b3", + "text": "When PBMTE=0, the implementation behaves as though Svpbmt were not implemented for VS-stage address translation.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 621, + 626 + ] + }, + { + "chunk_id": "chunk_4e253681", + "text": "If Svpbmt is not implemented, PBMTE is read-only zero.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 621, + 626 + ] + }, + { + "chunk_id": "chunk_25cf2b6c", + "text": "If the Svadu extension is implemented, the ADUE bit controls whether hardware updating of PTE A/D bits is enabled for VS-stage address translation.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 628, + 636 + ] + }, + { + "chunk_id": "chunk_09c44b1e", + "text": "When ADUE=1, hardware updating of PTE A/D bits is enabled during VS-stage address translation, and the implementation behaves as though the Svade extension were not implemented for VS-mode address translation.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 628, + 636 + ] + }, + { + "chunk_id": "chunk_0bc2487b", + "text": "When ADUE=0, the implementation behaves as though Svade were implemented for VS-stage address translation.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 628, + 636 + ] + }, + { + "chunk_id": "chunk_476f4922", + "text": "If Svadu is not implemented, ADUE is read-only zero.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 628, + 636 + ] + }, + { + "chunk_id": "chunk_d3d819d2", + "text": "The Sstc extension adds the `STCE` (STimecmp Enable) bit to `henvcfg` CSR.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 638, + 644 + ] + }, + { + "chunk_id": "chunk_dfe403b1", + "text": "When the Sstc extension is not implemented, `STCE` is read-only zero.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 638, + 644 + ] + }, + { + "chunk_id": "chunk_04b7efc4", + "text": "The `STCE` bit enables `vstimecmp` for VS-mode when set to one.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 638, + 644 + ] + }, + { + "chunk_id": "chunk_5e58890b", + "text": "When `STCE` bit is `henvcfg` is zero, an attempt to access `stimecmp` (really `vstimecmp`) when V=1 raises a virtual-instruction exception, and `VSTIP` in `hip` reverts to its defined behavior as if this extension is not implemented.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 638, + 644 + ] + }, + { + "chunk_id": "chunk_32c61aed", + "text": "The Zicboz extension adds the `CBZE` (Cache Block Zero instruction enable) field to `henvcfg`.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 646, + 654 + ] + }, + { + "chunk_id": "chunk_dd133a83", + "text": "The `CBZE` field applies to execution of the cache block zero instruction (`CBO.ZERO`) in privilege modes VS and VU, and only when the instruction is HS-qualified.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 646, + 654 + ] + }, + { + "chunk_id": "chunk_cd2e3cf0", + "text": "If the instruction is not HS-qualified, it raises an illegal-instruction exception.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 646, + 654 + ] + }, + { + "chunk_id": "chunk_c43d7172", + "text": "If the instruction is HS-qualified and the `CBZE` field is set to 1, the instruction is enabled for execution; otherwise, if the `CBZE` field is set to 0, it raises a virtual-instruction exception.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 646, + 654 + ] + }, + { + "chunk_id": "chunk_a15c3b9a", + "text": "When the Zicboz extension is not implemented, `CBZE` is read-only zero.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 646, + 654 + ] + }, + { + "chunk_id": "chunk_ff7af1e3", + "text": "The Zicbom extension adds the `CBCFE` (Cache Block Clean and Flush instruction Enable) field to `henvcfg`.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 656, + 663 + ] + }, + { + "chunk_id": "chunk_c35d4aac", + "text": "When V=1, if the `CBO.CLEAN` and `CBO.FLUSH` instructions are not HS-qualified, they raise an illegal-instruction exception.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 656, + 663 + ] + }, + { + "chunk_id": "chunk_23002ca2", + "text": "If the instructions are HS-qualified and the `CBCFE` field is set to 1, the instructions are enabled for execution; otherwise, if the `CBCFE` field is set to 0, they raise a virtual-instruction exception.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 656, + 663 + ] + }, + { + "chunk_id": "chunk_d9e45d9b", + "text": "When the Zicbom extension is not implemented, `CBCFE` is read-only zero.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 656, + 663 + ] + }, + { + "chunk_id": "chunk_146ae25e", + "text": "The Zicbom extension adds the `CBIE` (Cache Block Invalidate instruction Enable) WARL field to `henvcfg`.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 665, + 670 + ] + }, + { + "chunk_id": "chunk_9fef964e", + "text": "The `CBIE` field controls execution of the cache block invalidate instruction (`CBO.INVAL`) in privilege modes VS and VU.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 665, + 670 + ] + }, + { + "chunk_id": "chunk_ecd09231", + "text": "The encoding `10b` is reserved.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 665, + 670 + ] + }, + { + "chunk_id": "chunk_31f743c4", + "text": "When the Zicbom extension is not implemented, `CBIE` is read-only zero.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 665, + 670 + ] + }, + { + "chunk_id": "chunk_850145f6", + "text": "When V=1, if the `CBO.INVAL` instruction is not HS-qualified, it raises an illegal-instruction exception.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 672, + 676 + ] + }, + { + "chunk_id": "chunk_939df81e", + "text": "If the instruction is HS-qualified and the `CBIE` field is set to `01b` or `11b`, the instruction is enabled for execution; otherwise, it raises a virtual-instruction exception.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 672, + 676 + ] + }, + { + "chunk_id": "chunk_29fd661a", + "text": "If `CBO.INVAL` is enabled in HS-mode to perform a flush operation, then when the instruction is enabled in VS- or VU-mode it performs a flush operation, even if `CBIE` is set to `11b`.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 678, + 681 + ] + }, + { + "chunk_id": "chunk_ffc66722", + "text": "Otherwise, when the instruction is enabled for execution, its behavior depends on the `CBIE` encoding, as follows:", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 678, + 681 + ] + }, + { + "chunk_id": "chunk_54f4a7b6", + "text": "`01b` -- The instruction is executed and performs a flush operation, even if configured by VS-mode to perform an invalidate operation. * `11b` -- The instruction is executed and performs an invalidate operation, unless configured by VS-mode to perform a flush operation.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 683, + 686 + ] + }, + { + "chunk_id": "chunk_8e27cece", + "text": "When the Ssnpm extension is not implemented, the `PMM` field is read-only zero.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 688, + 692 + ] + }, + { + "chunk_id": "chunk_7d1cfb98", + "text": "The `PMM` field is read-only zero for RV32.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 688, + 692 + ] + }, + { + "chunk_id": "chunk_a1f1a0b8", + "text": "The Zicfilp extension adds the `LPE` field in `henvcfg`.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 706, + 710 + ] + }, + { + "chunk_id": "chunk_54725403", + "text": "When the `LPE` field is set to 1, the Zicfilp extension is enabled in VS-mode.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 706, + 710 + ] + }, + { + "chunk_id": "chunk_f01e8945", + "text": "When the `LPE` field is 0, the Zicfilp extension is not enabled in VS-mode and the following rules apply to VS-mode:", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 706, + 710 + ] + }, + { + "chunk_id": "chunk_d1697df4", + "text": "The hart does not update the `ELP` state; it remains as `NOLPEXPECTED`. * The `LPAD` instruction operates as a no-op.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 712, + 713 + ] + }, + { + "chunk_id": "chunk_12d848e2", + "text": "The Zicfiss extension adds the `SSE` field in `henvcfg`.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 715, + 719 + ] + }, + { + "chunk_id": "chunk_371bb40a", + "text": "If the `SSE` field is set to 1, the Zicfiss extension is activated in VS-mode.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 715, + 719 + ] + }, + { + "chunk_id": "chunk_2326b45d", + "text": "When the `SSE` field is 0, the Zicfiss extension remains inactive in VS-mode, and the following rules apply when `V=1`:", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 715, + 719 + ] + }, + { + "chunk_id": "chunk_4496f889", + "text": "32-bit Zicfiss instructions will revert to their behavior as defined by Zimop. * 16-bit Zicfiss instructions will revert to their behavior as defined by Zcmop. * The `pte.xwr=010b` encoding in VS-stage page tables becomes reserved. * The `senvcfg.SSE` field will read as zero and is read-only. *", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 721, + 726 + ] + }, + { + "chunk_id": "chunk_1e335585", + "text": "When `menvcfg.SSE` is one, `SSAMOSWAP.W/D` raises a virtual-instruction exception.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 721, + 726 + ] + }, + { + "chunk_id": "chunk_51116589", + "text": "The Ssdbltrp extension adds the double-trap-enable (`DTE`) field in `henvcfg`.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 728, + 731 + ] + }, + { + "chunk_id": "chunk_e0b190af", + "text": "When `henvcfg.DTE` is zero, the implementation behaves as though Ssdbltrp is not implemented for VS-mode and the `vsstatus.SDT` bit is read-only zero.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 728, + 731 + ] + }, + { + "chunk_id": "chunk_e5433e71", + "text": "When XLEN=32, `henvcfgh` is a 32-bit read/write register that aliases bits 63:32 of `henvcfg`.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 733, + 737 + ] + }, + { + "chunk_id": "chunk_934e063b", + "text": "Register `henvcfgh` does not exist when XLEN=64.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 733, + 737 + ] + }, + { + "chunk_id": "chunk_7bcaae3b", + "text": "The counter-enable register `hcounteren` is a 32-bit register that controls the availability of the hardware performance monitoring counters to the guest virtual machine.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Counter-Enable (`hcounteren`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 741, + 744 + ] + }, + { + "chunk_id": "chunk_dd736d8d", + "text": "When the CY, TM, IR, or HPMn bit in the `hcounteren` register is clear, attempts to read the `cycle`, `time`, `instret`, or `hpmcounter` n register while V=1 will cause a virtual-instruction exception if the same bit in `mcounteren` is 1.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Counter-Enable (`hcounteren`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 749, + 757 + ] + }, + { + "chunk_id": "chunk_42d052b5", + "text": "When one of these bits is set, access to the corresponding register is permitted when V=1, unless prevented for some other reason.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Counter-Enable (`hcounteren`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 749, + 757 + ] + }, + { + "chunk_id": "chunk_005eeb1a", + "text": "In VU-mode, a counter is not readable unless the applicable bits are set in both `hcounteren` and `scounteren`.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Counter-Enable (`hcounteren`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 749, + 757 + ] + }, + { + "chunk_id": "chunk_89399b82", + "text": "In addition, when the TM bit in the `hcounteren` register is clear, attempts to access the `vstimecmp` register (via `stimecmp`) while executing in VS-mode will cause a virtual-instruction exception if the same bit in `mcounteren` is set.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Counter-Enable (`hcounteren`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 759, + 764 + ] + }, + { + "chunk_id": "chunk_32832064", + "text": "When this bit and the same bit in `mcounteren` are both set, access to the `vstimecmp` register (if implemented) is permitted in VS-mode.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Counter-Enable (`hcounteren`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 759, + 764 + ] + }, + { + "chunk_id": "chunk_5d742cad", + "text": "`hcounteren` must be implemented.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Counter-Enable (`hcounteren`) Register", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 766, + 769 + ] + }, + { + "chunk_id": "chunk_8ce0725a", + "text": "However, any of the bits may be read-only zero, indicating reads to the corresponding counter will cause an exception when V=1.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Counter-Enable (`hcounteren`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 766, + 769 + ] + }, + { + "chunk_id": "chunk_88c9779d", + "text": "Hence, they are effectively *WARL* fields.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Counter-Enable (`hcounteren`) Register", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 766, + 769 + ] + }, + { + "chunk_id": "chunk_f1ab6623", + "text": "The `htimedelta` CSR is a 64-bit read/write register that contains the delta between the value of the `time` CSR and the value returned in VS-mode or VU-mode.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Time Delta (`htimedelta`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 773, + 777 + ] + }, + { + "chunk_id": "chunk_040c8eed", + "text": "That is, reading the `time` CSR in VS or VU mode returns the sum of the contents of `htimedelta` and the actual value of `time`.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Time Delta (`htimedelta`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 773, + 777 + ] + }, + { + "chunk_id": "chunk_598e08ca", + "text": "When XLEN=32, `htimedeltah` is a 32-bit read/write register that aliases bits 63:32 of `htimedelta`.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Time Delta (`htimedelta`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 782, + 785 + ] + }, + { + "chunk_id": "chunk_2fe9d5d8", + "text": "Register `htimedeltah` does not exist when XLEN=64.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Time Delta (`htimedelta`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 782, + 785 + ] + }, + { + "chunk_id": "chunk_b0c36f3f", + "text": "If the `time` CSR is implemented, `htimedelta` (and `htimedeltah` for XLEN=32) must be implemented.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Time Delta (`htimedelta`) Register", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 787, + 789 + ] + }, + { + "chunk_id": "chunk_8dbfe785", + "text": "The `htval` register is an HSXLEN-bit read/write register formatted as shown in .", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Value (`htval`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 793, + 797 + ] + }, + { + "chunk_id": "chunk_20300779", + "text": "When a trap is taken into HS-mode, `htval` is written with additional exception-specific information, alongside `stval`, to assist software in handling the trap.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Value (`htval`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 793, + 797 + ] + }, + { + "chunk_id": "chunk_f1c80786", + "text": "When a guest-page-fault trap is taken into HS-mode, `htval` is written with either zero or the guest physical address that faulted, shifted right by 2 bits.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Value (`htval`) Register", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 803, + 807 + ] + }, + { + "chunk_id": "chunk_ee471d2e", + "text": "For other traps, `htval` is set to zero, but a future standard or extension may redefine `htval's` setting for other traps.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Value (`htval`) Register", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 803, + 807 + ] + }, + { + "chunk_id": "chunk_5c253946", + "text": "Otherwise, for misaligned loads and stores that cause guest-page faults, a nonzero guest physical address in `htval` corresponds to the faulting portion of the access as indicated by the virtual address in `stval`.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Value (`htval`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 818, + 823 + ] + }, + { + "chunk_id": "chunk_1e095ede", + "text": "For instruction guest-page faults on systems with variable-length instructions, a nonzero `htval` corresponds to the faulting portion of the instruction as indicated by the virtual address in `stval`.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Value (`htval`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 818, + 823 + ] + }, + { + "chunk_id": "chunk_347e7e23", + "text": "`htval` is a *WARL* register that must be able to hold zero and may be capable of holding only an arbitrary subset of other 2-bit-shifted guest physical addresses, if any.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Value (`htval`) Register", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 825, + 828 + ] + }, + { + "chunk_id": "chunk_873d0da8", + "text": "The `htinst` register is an HSXLEN-bit read/write register formatted as shown in .", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Instruction (`htinst`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 832, + 838 + ] + }, + { + "chunk_id": "chunk_80e6148a", + "text": "When a trap is taken into HS-mode, `htinst` is written with a value that, if nonzero, provides information about the instruction that trapped, to assist software in handling the trap.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Instruction (`htinst`) Register", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 832, + 838 + ] + }, + { + "chunk_id": "chunk_e4cf4d7e", + "text": "The values that may be written to `htinst` on a trap are documented in .", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Instruction (`htinst`) Register", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 832, + 838 + ] + }, + { + "chunk_id": "chunk_32c3747c", + "text": "`htinst` is a *WARL* register that need only be able to hold the values that the implementation may automatically write to it on a trap.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Instruction (`htinst`) Register", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 844, + 846 + ] + }, + { + "chunk_id": "chunk_8b31d901", + "text": "Similar to CSR `satp`, this register holds the physical page number (PPN) of the guest-physical root page table; a virtual machine identifier (VMID), which facilitates address-translation fences on a per-virtual-machine basis; and the MODE field, which selects the address-translation scheme for guest physical addresses.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest Address Translation and Protection (`hgatp`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 851, + 862 + ] + }, + { + "chunk_id": "chunk_afc7c99b", + "text": "When `mstatus`.TVM=1, attempts to read or write `hgatp` while executing in HS-mode will raise an illegal-instruction exception.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest Address Translation and Protection (`hgatp`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 851, + 862 + ] + }, + { + "chunk_id": "chunk_fb5ee0d0", + "text": "shows the encodings of the MODE field when HSXLEN=32 and HSXLEN=64.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest Address Translation and Protection (`hgatp`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 872, + 880 + ] + }, + { + "chunk_id": "chunk_e81e27d1", + "text": "When MODE=Bare, guest physical addresses are equal to supervisor physical addresses, and there is no further memory protection for a guest virtual machine beyond the physical memory protection scheme described in .", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest Address Translation and Protection (`hgatp`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "range", + "line_range": [ + 872, + 880 + ] + }, + { + "chunk_id": "chunk_34c1340b", + "text": "In this case, software must write zero to the remaining fields in `hgatp`.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest Address Translation and Protection (`hgatp`) Register", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 872, + 880 + ] + }, + { + "chunk_id": "chunk_835440b2", + "text": "Attempting to select MODE=Bare with a nonzero pattern in the remaining fields has an UNSPECIFIED effect on the value that the remaining fields assume and an UNSPECIFIED effect on G-stage address translation and protection behavior.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest Address Translation and Protection (`hgatp`) Register", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 872, + 880 + ] + }, + { + "chunk_id": "chunk_72e15c5a", + "text": "When HSXLEN=32, the only other valid setting for MODE is Sv32x4, which is a modification of the usual Sv32 paged virtual-memory scheme, extended to support 34-bit guest physical addresses.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest Address Translation and Protection (`hgatp`) Register", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 882, + 889 + ] + }, + { + "chunk_id": "chunk_ac8932ec", + "text": "When HSXLEN=64, modes Sv39x4, Sv48x4, and Sv57x4 are defined as modifications of the Sv39, Sv48, and Sv57 paged virtual-memory schemes.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest Address Translation and Protection (`hgatp`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 882, + 889 + ] + }, + { + "chunk_id": "chunk_83ee18a6", + "text": "All of these paged virtual-memory schemes are described in .", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest Address Translation and Protection (`hgatp`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 882, + 889 + ] + }, + { + "chunk_id": "chunk_aaa1d1bb", + "text": "The remaining MODE settings when HSXLEN=64 are reserved for future use and may define different interpretations of the other fields in `hgatp`.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest Address Translation and Protection (`hgatp`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 891, + 892 + ] + }, + { + "chunk_id": "chunk_cac1b60b", + "text": "Implementations are not required to support all defined MODE settings when HSXLEN=64.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest Address Translation and Protection (`hgatp`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 932, + 933 + ] + }, + { + "chunk_id": "chunk_f7e06f06", + "text": "A write to `hgatp` with an unsupported MODE value is not ignored as it is for `satp`.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest Address Translation and Protection (`hgatp`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 935, + 938 + ] + }, + { + "chunk_id": "chunk_b937205d", + "text": "Instead, the fields of `hgatp` are *WARL* in the normal way, when so indicated.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest Address Translation and Protection (`hgatp`) Register", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 935, + 938 + ] + }, + { + "chunk_id": "chunk_1ae63359", + "text": "As explained in , for the paged virtual-memory schemes (Sv32x4, Sv39x4, Sv48x4, and Sv57x4), the root page table is 16 KiB and must be aligned to a 16-KiB boundary.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest Address Translation and Protection (`hgatp`) Register", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 940, + 947 + ] + }, + { + "chunk_id": "chunk_35bc382c", + "text": "In these modes, the lowest two bits of the physical page number (PPN) in `hgatp` always read as zeros.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest Address Translation and Protection (`hgatp`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 940, + 947 + ] + }, + { + "chunk_id": "chunk_1a65328e", + "text": "An implementation that supports only the defined paged virtual-memory schemes and/or Bare may make PPN[1:0] read-only zero.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest Address Translation and Protection (`hgatp`) Register", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 940, + 947 + ] + }, + { + "chunk_id": "chunk_406e6cdd", + "text": "The number of VMID bits is UNSPECIFIED and may be zero.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest Address Translation and Protection (`hgatp`) Register", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 949, + 956 + ] + }, + { + "chunk_id": "chunk_8e1a8e23", + "text": "The number of implemented VMID bits, termed VMIDLEN, may be determined by writing one to every bit position in the VMID field, then reading back the value in `hgatp` to see which bit positions in the VMID field hold a one.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest Address Translation and Protection (`hgatp`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 949, + 956 + ] + }, + { + "chunk_id": "chunk_9a74d120", + "text": "The maximal value of VMIDLEN, termed VMIDMAX, is 7 for Sv32x4 or 14 for Sv39x4, Sv48x4, and Sv57x4.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest Address Translation and Protection (`hgatp`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 949, + 956 + ] + }, + { + "chunk_id": "chunk_23986a0c", + "text": "The `hgatp` register is considered active for the purposes of the address-translation algorithm unless the effective privilege mode is U and `hstatus`.HU=0.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest Address Translation and Protection (`hgatp`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 958, + 960 + ] + }, + { + "chunk_id": "chunk_465e9d0a", + "text": "The `vsstatus` register is a VSXLEN-bit read/write register that is VS-mode\u2019s version of supervisor register `sstatus`, formatted as shown in when VSXLEN=32 and when VSXLEN=64.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Status (`vsstatus`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 972, + 978 + ] + }, + { + "chunk_id": "chunk_252d1f6c", + "text": "When V=1, `vsstatus` substitutes for the usual `sstatus`, so instructions that normally read or modify `sstatus` actually access `vsstatus` instead.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Status (`vsstatus`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 972, + 978 + ] + }, + { + "chunk_id": "chunk_1c2abfcf", + "text": "The UXL field controls the effective XLEN for VU-mode, which may differ from the XLEN for VS-mode (VSXLEN).", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Status (`vsstatus`) Register", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1036, + 1040 + ] + }, + { + "chunk_id": "chunk_77c37a5f", + "text": "When VSXLEN=32, the UXL field does not exist, and VU-mode XLEN=32.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Status (`vsstatus`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 1036, + 1040 + ] + }, + { + "chunk_id": "chunk_e66d7cb3", + "text": "When VSXLEN=64, UXL is a *WARL* field that is encoded the same as the MXL field of `misa`, shown in .", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Status (`vsstatus`) Register", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1036, + 1040 + ] + }, + { + "chunk_id": "chunk_31126ac3", + "text": "In particular, an implementation may make UXL be a read-only copy of field VSXL of `hstatus`, forcing VU-mode XLEN=VSXLEN.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Status (`vsstatus`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1036, + 1040 + ] + }, + { + "chunk_id": "chunk_8f9cb3f9", + "text": "If VSXLEN is changed from 32 to a wider width, and if field UXL is not restricted to a single value, it gets the value corresponding to the widest supported width not wider than the new VSXLEN.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Status (`vsstatus`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 1042, + 1045 + ] + }, + { + "chunk_id": "chunk_d7ce4e40", + "text": "When V=1, both `vsstatus`.FS and the HS-level `sstatus`.FS are in effect.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Status (`vsstatus`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1047, + 1051 + ] + }, + { + "chunk_id": "chunk_0facaac2", + "text": "Attempts to execute a floating-point instruction when either field is 0 (Off) raise an illegal-instruction exception.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Status (`vsstatus`) Register", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1047, + 1051 + ] + }, + { + "chunk_id": "chunk_574473fb", + "text": "Modifying the floating-point state when V=1 causes both fields to be set to 3 (Dirty).", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Status (`vsstatus`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 1047, + 1051 + ] + }, + { + "chunk_id": "chunk_da23ff96", + "text": "Similarly, when V=1, both `vsstatus`.VS and the HS-level `sstatus`.VS are in effect.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Status (`vsstatus`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1053, + 1057 + ] + }, + { + "chunk_id": "chunk_b838a66a", + "text": "Attempts to execute a vector instruction when either field is 0 (Off) raise an illegal-instruction exception.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Status (`vsstatus`) Register", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1053, + 1057 + ] + }, + { + "chunk_id": "chunk_5bcb2703", + "text": "Modifying the vector state when V=1 causes both fields to be set to 3 (Dirty).", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Status (`vsstatus`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 1053, + 1057 + ] + }, + { + "chunk_id": "chunk_60c57b9c", + "text": "Read-only fields SD and XS summarize the extension context status as it is visible to VS-mode only.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Status (`vsstatus`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1059, + 1062 + ] + }, + { + "chunk_id": "chunk_498f6576", + "text": "An implementation may make field UBE be a read-only copy of `hstatus`.VSBE.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Status (`vsstatus`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1064, + 1066 + ] + }, + { + "chunk_id": "chunk_a5782905", + "text": "When V=0, `vsstatus` does not directly affect the behavior of the machine, unless a virtual-machine load/store (HLV, HLVX, or HSV) or the MPRV feature in the `mstatus` register is used to execute a load or store as though V=1.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Status (`vsstatus`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1068, + 1072 + ] + }, + { + "chunk_id": "chunk_f0948c10", + "text": "The Zicfilp extension adds the `SPELP` field that holds the previous `ELP`, and is updated as specified in .", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Status (`vsstatus`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 1074, + 1077 + ] + }, + { + "chunk_id": "chunk_678fad21", + "text": "The `SPELP` field is encoded as follows:", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Status (`vsstatus`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 1074, + 1077 + ] + }, + { + "chunk_id": "chunk_c7ab5d22", + "text": "0 - `NOLPEXPECTED` - no landing pad instruction expected. * 1 - `LPEXPECTED` - a landing pad instruction is expected.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Status (`vsstatus`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1079, + 1080 + ] + }, + { + "chunk_id": "chunk_4bd54f44", + "text": "The `vsip` and `vsie` registers are VSXLEN-bit read/write registers that are VS-mode\u2019s versions of supervisor CSRs `sip` and `sie`, formatted as shown in and respectively.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Interrupt (`vsip` and `vsie`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 1088, + 1096 + ] + }, + { + "chunk_id": "chunk_3c83c464", + "text": "When V=1, `vsip` and `vsie` substitute for the usual `sip` and `sie`, so instructions that normally read or modify `sip`/`sie` actually access `vsip`/`vsie` instead.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Interrupt (`vsip` and `vsie`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1088, + 1096 + ] + }, + { + "chunk_id": "chunk_7d72f218", + "text": "However, interrupts directed to HS-level continue to be indicated in the HS-level `sip` register, not in `vsip`, when V=1.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Interrupt (`vsip` and `vsie`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1088, + 1096 + ] + }, + { + "chunk_id": "chunk_df5f04f4", + "text": "The standard portions (bits 15:0) of registers `vsip` and `vsie` are formatted as shown in and respectively.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Interrupt (`vsip` and `vsie`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1106, + 1108 + ] + }, + { + "chunk_id": "chunk_18ac463a", + "text": "Extension Shlcofideleg supports delegating LCOFI interrupts to VS-mode.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Interrupt (`vsip` and `vsie`) Registers", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1118, + 1125 + ] + }, + { + "chunk_id": "chunk_10fe54f2", + "text": "If the Shlcofideleg extension is implemented, `hideleg` bit 13 is writable; otherwise, it is read-only zero.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Interrupt (`vsip` and `vsie`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 1118, + 1125 + ] + }, + { + "chunk_id": "chunk_a4ffa420", + "text": "When bit 13 of `hideleg` is zero, `vsip`.LCOFIP and `vsie`.LCOFIE are read-only zeros.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Interrupt (`vsip` and `vsie`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 1118, + 1125 + ] + }, + { + "chunk_id": "chunk_02647939", + "text": "Else, `vsip`.LCOFIP and `vsie`.LCOFIE are aliases of `sip`.LCOFIP and `sie`.LCOFIE.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Interrupt (`vsip` and `vsie`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1118, + 1125 + ] + }, + { + "chunk_id": "chunk_2a39cc54", + "text": "When bit 10 of `hideleg` is zero, `vsip`.SEIP and `vsie`.SEIE are read-only zeros.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Interrupt (`vsip` and `vsie`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 1127, + 1130 + ] + }, + { + "chunk_id": "chunk_23d8580e", + "text": "Else, `vsip`.SEIP and `vsie`.SEIE are aliases of `hip`.VSEIP and `hie`.VSEIE.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Interrupt (`vsip` and `vsie`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1127, + 1130 + ] + }, + { + "chunk_id": "chunk_1193d40d", + "text": "When bit 6 of `hideleg` is zero, `vsip`.STIP and `vsie`.STIE are read-only zeros.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Interrupt (`vsip` and `vsie`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 1132, + 1135 + ] + }, + { + "chunk_id": "chunk_fada99dc", + "text": "Else, `vsip`.STIP and `vsie`.STIE are aliases of `hip`.VSTIP and `hie`.VSTIE.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Interrupt (`vsip` and `vsie`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1132, + 1135 + ] + }, + { + "chunk_id": "chunk_3f083a5f", + "text": "When bit 2 of `hideleg` is zero, `vsip`.SSIP and `vsie`.SSIE are read-only zeros.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Interrupt (`vsip` and `vsie`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 1137, + 1140 + ] + }, + { + "chunk_id": "chunk_185a33d2", + "text": "Else, `vsip`.SSIP and `vsie`.SSIE are aliases of `hip`.VSSIP and `hie`.VSSIE.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Interrupt (`vsip` and `vsie`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1137, + 1140 + ] + }, + { + "chunk_id": "chunk_abb5e991", + "text": "The `vstvec` register is a VSXLEN-bit read/write register that is VS-mode\u2019s version of supervisor register `stvec`, formatted as shown in .", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Trap Vector Base Address (`vstvec`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 1144, + 1150 + ] + }, + { + "chunk_id": "chunk_b048dc7a", + "text": "When V=1, `vstvec` substitutes for the usual `stvec`, so instructions that normally read or modify `stvec` actually access `vstvec` instead.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Trap Vector Base Address (`vstvec`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1144, + 1150 + ] + }, + { + "chunk_id": "chunk_5e549c3e", + "text": "When V=0, `vstvec` does not directly affect the behavior of the machine.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Trap Vector Base Address (`vstvec`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1144, + 1150 + ] + }, + { + "chunk_id": "chunk_374ffb0f", + "text": "The `vsscratch` register is a VSXLEN-bit read/write register that is VS-mode\u2019s version of supervisor register `sscratch`, formatted as shown in .", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Scratch (`vsscratch`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 1158, + 1164 + ] + }, + { + "chunk_id": "chunk_39e35545", + "text": "When V=1, `vsscratch` substitutes for the usual `sscratch`, so instructions that normally read or modify `sscratch` actually access `vsscratch` instead.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Scratch (`vsscratch`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1158, + 1164 + ] + }, + { + "chunk_id": "chunk_d4f16131", + "text": "The contents of `vsscratch` never directly affect the behavior of the machine.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Scratch (`vsscratch`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1158, + 1164 + ] + }, + { + "chunk_id": "chunk_dc319ad9", + "text": "The `vsepc` register is a VSXLEN-bit read/write register that is VS-mode\u2019s version of supervisor register `sepc`, formatted as shown in .", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Exception Program Counter (`vsepc`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 1172, + 1178 + ] + }, + { + "chunk_id": "chunk_b80d0104", + "text": "When V=1, `vsepc` substitutes for the usual `sepc`, so instructions that normally read or modify `sepc` actually access `vsepc` instead.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Exception Program Counter (`vsepc`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1172, + 1178 + ] + }, + { + "chunk_id": "chunk_f39131fb", + "text": "When V=0, `vsepc` does not directly affect the behavior of the machine.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Exception Program Counter (`vsepc`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1172, + 1178 + ] + }, + { + "chunk_id": "chunk_4ad5ed93", + "text": "`vsepc` is a *WARL* register that must be able to hold the same set of values that `sepc` can hold.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Exception Program Counter (`vsepc`) Register", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1180, + 1182 + ] + }, + { + "chunk_id": "chunk_95eed6ca", + "text": "The `vscause` register is a VSXLEN-bit read/write register that is VS-mode\u2019s version of supervisor register `scause`, formatted as shown in .", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Cause (`vscause`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 1190, + 1196 + ] + }, + { + "chunk_id": "chunk_6f4d9f2d", + "text": "When V=1, `vscause` substitutes for the usual `scause`, so instructions that normally read or modify `scause` actually access `vscause` instead.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Cause (`vscause`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1190, + 1196 + ] + }, + { + "chunk_id": "chunk_a9f8b4fa", + "text": "When V=0, `vscause` does not directly affect the behavior of the machine.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Cause (`vscause`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1190, + 1196 + ] + }, + { + "chunk_id": "chunk_89ea1976", + "text": "`vscause` is a *WLRL* register that must be able to hold the same set of values that `scause` can hold.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Cause (`vscause`) Register", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1198, + 1200 + ] + }, + { + "chunk_id": "chunk_d1f523a0", + "text": "The `vstval` register is a VSXLEN-bit read/write register that is VS-mode\u2019s version of supervisor register `stval`, formatted as shown in .", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Trap Value (`vstval`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 1208, + 1214 + ] + }, + { + "chunk_id": "chunk_05a26484", + "text": "When V=1, `vstval` substitutes for the usual `stval`, so instructions that normally read or modify `stval` actually access `vstval` instead.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Trap Value (`vstval`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1208, + 1214 + ] + }, + { + "chunk_id": "chunk_e5ac1ecb", + "text": "When V=0, `vstval` does not directly affect the behavior of the machine.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Trap Value (`vstval`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1208, + 1214 + ] + }, + { + "chunk_id": "chunk_517503bb", + "text": "`vstval` is a *WARL* register that must be able to hold the same set of values that `stval` can hold.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Trap Value (`vstval`) Register", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1216, + 1218 + ] + }, + { + "chunk_id": "chunk_ac4984b6", + "text": "The `vsatp` register is a VSXLEN-bit read/write register that is VS-mode\u2019s version of supervisor register `satp`, formatted as shown in for VSXLEN=32 and for VSXLEN=64.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Address Translation and Protection (`vsatp`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 1226, + 1234 + ] + }, + { + "chunk_id": "chunk_2806be78", + "text": "The `vsatp` register is considered active for the purposes of the address-translation algorithm unless the effective privilege mode is U and `hstatus`.HU=0.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Address Translation and Protection (`vsatp`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1244, + 1248 + ] + }, + { + "chunk_id": "chunk_483bef9e", + "text": "However, even when `vsatp` is active, VS-stage page-table entries\u2019 A bits must not be set as a result of speculative execution, unless the effective privilege mode is VS or VU.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Address Translation and Protection (`vsatp`) Register", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1244, + 1248 + ] + }, + { + "chunk_id": "chunk_8e232382", + "text": "When V=0, a write to `vsatp` with an unsupported MODE value is either ignored as it is for `satp`, or the fields of `vsatp` are treated as *WARL* in the normal way.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Address Translation and Protection (`vsatp`) Register", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1250, + 1253 + ] + }, + { + "chunk_id": "chunk_53368c6a", + "text": "However, when V=1, a write to `satp` with an unsupported MODE value is ignored and no write to `vsatp` is effected.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Address Translation and Protection (`vsatp`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1250, + 1253 + ] + }, + { + "chunk_id": "chunk_5f9bd659", + "text": "When V=0, `vsatp` does not directly affect the behavior of the machine, unless a virtual-machine load/store (HLV, HLVX, or HSV) or the MPRV feature in the `mstatus` register is used to execute a load or store as though V=1.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Address Translation and Protection (`vsatp`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1255, + 1259 + ] + }, + { + "chunk_id": "chunk_6a7019b9", + "text": "The `vstimecmp` CSR is a 64-bit register and has 64-bit precision on all RV32 and RV64 systems.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Timer (`vstimecmp`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 1264, + 1267 + ] + }, + { + "chunk_id": "chunk_9f6a680e", + "text": "In RV32 only, accesses to the `vstimecmp` CSR access the low 32 bits, while accesses to the `vstimecmph` CSR access the high 32 bits of `vstimecmp`.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Timer (`vstimecmp`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 1264, + 1267 + ] + }, + { + "chunk_id": "chunk_4d000fef", + "text": "If the result of this comparison changes, it is guaranteed to be reflected in VSTIP eventually, but not necessarily immediately.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Timer (`vstimecmp`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1269, + 1278 + ] + }, + { + "chunk_id": "chunk_38fd7041", + "text": "The interrupt will be taken based on the standard interrupt enable and delegation rules while V=1.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Timer (`vstimecmp`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1269, + 1278 + ] + }, + { + "chunk_id": "chunk_50b9b79d", + "text": "The hypervisor virtual-machine load and store instructions are valid only in M-mode or HS-mode, or in U-mode when `hstatus`.HU=1.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Virtual-Machine Load and Store Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1289, + 1302 + ] + }, + { + "chunk_id": "chunk_d59339ab", + "text": "The effective privilege mode of the explicit memory access is VU when `hstatus`.SPVP=0, and VS when `hstatus`.SPVP=1.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Virtual-Machine Load and Store Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1289, + 1302 + ] + }, + { + "chunk_id": "chunk_7f885b9e", + "text": "As usual for VS-mode and VU-mode, two-stage address translation is applied, and the HS-level `sstatus`.SUM is ignored. HS-level `sstatus`.MXR makes execute-only pages readable by explicit loads for both stages of address translation (VS-stage and G-stage), whereas `vsstatus`.MXR affects only the first translation stage (VS-stage).", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Virtual-Machine Load and Store Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1289, + 1302 + ] + }, + { + "chunk_id": "chunk_2dd6a687", + "text": "That is, the memory being read must be executable in both stages of address translation, but read permission is not required.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Virtual-Machine Load and Store Instructions", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1312, + 1322 + ] + }, + { + "chunk_id": "chunk_b1e08634", + "text": "For the supervisor physical address that results from address translation, the supervisor physical memory attributes must grant both execute and read permissions. (The supervisor physical memory attributes are the machine\u2019s physical memory attributes as modified by physical memory protection, , for supervisor level.)", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Virtual-Machine Load and Store Instructions", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1312, + 1322 + ] + }, + { + "chunk_id": "chunk_f1e1db40", + "text": "HLVX.WU is valid for RV32, even though LWU and HLV.WU are not. (For RV32, HLVX.WU can be considered a variant of HLV.W, as sign extension is irrelevant for 32-bit values.)", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Virtual-Machine Load and Store Instructions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 1324, + 1327 + ] + }, + { + "chunk_id": "chunk_e45ad577", + "text": "Attempts to execute a virtual-machine load/store instruction (HLV, HLVX, or HSV) when V=1 cause a virtual-instruction exception.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Virtual-Machine Load and Store Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1332, + 1335 + ] + }, + { + "chunk_id": "chunk_5ad25264", + "text": "Attempts to execute one of these same instructions from U-mode when `hstatus`.HU=0 cause an illegal-instruction exception.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Virtual-Machine Load and Store Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1332, + 1335 + ] + }, + { + "chunk_id": "chunk_d40c865d", + "text": "The hypervisor memory-management fence instructions, HFENCE.VVMA and HFENCE.GVMA, perform a function similar to SFENCE.VMA (), except applying to the VS-level memory-management data structures controlled by CSR `vsatp` (HFENCE.VVMA) or the guest-physical memory-management data structures controlled by CSR `hgatp` (HFENCE.GVMA).", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Memory-Management Fence Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1342, + 1350 + ] + }, + { + "chunk_id": "chunk_925c88bf", + "text": "Instruction SFENCE.VMA applies only to the memory-management data structures controlled by the current `satp` (either the HS-level `satp` when V=0 or `vsatp` when V=1).", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Memory-Management Fence Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1342, + 1350 + ] + }, + { + "chunk_id": "chunk_61bead2e", + "text": "are subsequent to the HFENCE.VVMA, and * execute when `hgatp`.VMID has the same setting as it did when HFENCE.VVMA executed.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Memory-Management Fence Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1359, + 1361 + ] + }, + { + "chunk_id": "chunk_da9c6bc5", + "text": "Implicit reads need not be ordered when `hgatp`.VMID is different than at the time HFENCE.VVMA executed.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Memory-Management Fence Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1363, + 1365 + ] + }, + { + "chunk_id": "chunk_7bf6fa95", + "text": "If operand rs1!=`x0`, it specifies a single guest virtual address, and if operand rs2!=`x0`, it specifies a single guest address-space identifier (ASID).", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Memory-Management Fence Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1363, + 1365 + ] + }, + { + "chunk_id": "chunk_478d466a", + "text": "When rs2!=`x0`, bits XLEN-1:ASIDMAX of the value held in rs2 are reserved for future standard use.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Memory-Management Fence Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1367, + 1373 + ] + }, + { + "chunk_id": "chunk_578e8358", + "text": "Until their use is defined by a standard extension, they should be zeroed by software and ignored by current implementations.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Memory-Management Fence Instructions", + "confidence": "medium", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 1367, + 1373 + ] + }, + { + "chunk_id": "chunk_241bcec5", + "text": "Furthermore, if ASIDLEN < ASIDMAX, the implementation shall ignore bits ASIDMAX-1:ASIDLEN of the value held in rs2.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Memory-Management Fence Instructions", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 1367, + 1373 + ] + }, + { + "chunk_id": "chunk_9dd42bf9", + "text": "Neither `mstatus`.TVM nor `hstatus`.VTVM causes HFENCE.VVMA to trap.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Memory-Management Fence Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1375, + 1376 + ] + }, + { + "chunk_id": "chunk_42043311", + "text": "HFENCE.GVMA is valid only in HS-mode when `mstatus`.TVM=0, or in M-mode (irrespective of `mstatus`.TVM).", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Memory-Management Fence Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1378, + 1387 + ] + }, + { + "chunk_id": "chunk_50e98a2d", + "text": "If operand rs1!=`x0`, it specifies a single guest physical address, shifted right by 2 bits, and if operand rs2!=`x0`, it specifies a single virtual machine identifier (VMID).", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Memory-Management Fence Instructions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 1378, + 1387 + ] + }, + { + "chunk_id": "chunk_be067f66", + "text": "When rs2!=`x0`, bits XLEN-1:VMIDMAX of the value held in rs2 are reserved for future standard use.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Memory-Management Fence Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1389, + 1395 + ] + }, + { + "chunk_id": "chunk_dae36684", + "text": "Until their use is defined by a standard extension, they should be zeroed by software and ignored by current implementations.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Memory-Management Fence Instructions", + "confidence": "medium", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 1389, + 1395 + ] + }, + { + "chunk_id": "chunk_5b23e1a5", + "text": "Furthermore, if VMIDLEN < VMIDMAX, the implementation shall ignore bits VMIDMAX-1:VMIDLEN of the value held in rs2.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Memory-Management Fence Instructions", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 1389, + 1395 + ] + }, + { + "chunk_id": "chunk_3692eb35", + "text": "If `hgatp`.MODE is changed for a given VMID, an HFENCE.GVMA with rs1=`x0` (and rs2 set to either `x0` or the VMID) must be executed to order subsequent guest translations with the MODE change\u2014even if the old MODE or new MODE is Bare.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Memory-Management Fence Instructions", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1397, + 1401 + ] + }, + { + "chunk_id": "chunk_74b59b73", + "text": "Attempts to execute HFENCE.VVMA or HFENCE.GVMA when V=1 cause a virtual-instruction exception, while attempts to do the same in U-mode cause an illegal-instruction exception.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Memory-Management Fence Instructions", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 1403, + 1407 + ] + }, + { + "chunk_id": "chunk_6e680c28", + "text": "Attempting to execute HFENCE.GVMA in HS-mode when `mstatus`.TVM=1 also causes an illegal-instruction exception.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Memory-Management Fence Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1403, + 1407 + ] + }, + { + "chunk_id": "chunk_81a709fb", + "text": "The hypervisor extension augments or modifies machine CSRs `mstatus`, `mstatush`, `mideleg`, `mip`, and `mie`, and adds CSRs `mtval2` and `mtinst`.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1411, + 1413 + ] + }, + { + "chunk_id": "chunk_7b60d1f7", + "text": "The hypervisor extension adds two fields, MPV and GVA, to the machine-level `mstatus` or `mstatush` CSR, and modifies the behavior of several existing `mstatus` fields. shows the modified `mstatus` register when the hypervisor extension is implemented and MXLEN=64.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1417, + 1426 + ] + }, + { + "chunk_id": "chunk_416e3f0d", + "text": "When MXLEN=32, the hypervisor extension adds MPV and GVA not to `mstatus` but to `mstatush`. shows the `mstatush` register when the hypervisor extension is implemented and MXLEN=32.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1417, + 1426 + ] + }, + { + "chunk_id": "chunk_710c7584", + "text": "The format of `mstatus` is unchanged for RV32. include::images/bytefield/hypv-mstatush.edn[]", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1432, + 1434 + ] + }, + { + "chunk_id": "chunk_fc9ef296", + "text": "The MPV bit (Machine Previous Virtualization Mode) is written by the implementation whenever a trap is taken into M-mode.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1436, + 1442 + ] + }, + { + "chunk_id": "chunk_832e30d4", + "text": "Just as the MPP field is set to the (nominal) privilege mode at the time of the trap, the MPV bit is set to the value of the virtualization mode V at the time of the trap.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 1436, + 1442 + ] + }, + { + "chunk_id": "chunk_b17f9a4f", + "text": "When an MRET instruction is executed, the virtualization mode V is set to MPV, unless MPP=3, in which case V remains 0.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1436, + 1442 + ] + }, + { + "chunk_id": "chunk_1afa2ffe", + "text": "Field GVA (Guest Virtual Address) is written by the implementation whenever a trap is taken into M-mode.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 1444, + 1449 + ] + }, + { + "chunk_id": "chunk_7c362052", + "text": "For any trap (breakpoint, address misaligned, access fault, page fault, or guest-page fault) that writes a guest virtual address to `mtval`, GVA is set to 1.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 1444, + 1449 + ] + }, + { + "chunk_id": "chunk_ced2f115", + "text": "For any other trap into M-mode, GVA is set to 0.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 1444, + 1449 + ] + }, + { + "chunk_id": "chunk_6dddad15", + "text": "The TSR and TVM fields of `mstatus` affect execution only in HS-mode, not in VS-mode.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1451, + 1454 + ] + }, + { + "chunk_id": "chunk_d5a01f59", + "text": "The TW field affects execution in all modes except M-mode.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 1451, + 1454 + ] + }, + { + "chunk_id": "chunk_63218cf1", + "text": "Setting TVM=1 prevents HS-mode from accessing `hgatp` or executing HFENCE.GVMA or HINVAL.GVMA, but has no effect on accesses to `vsatp` or instructions HFENCE.VVMA or HINVAL.VVMA.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1456, + 1459 + ] + }, + { + "chunk_id": "chunk_0f363f65", + "text": "The hypervisor extension changes the behavior of the Modify Privilege field, MPRV, of `mstatus`.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1461, + 1467 + ] + }, + { + "chunk_id": "chunk_f2128774", + "text": "When MPRV=0, translation and protection behave as normal.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1461, + 1467 + ] + }, + { + "chunk_id": "chunk_00269fc4", + "text": "When MPRV=1, explicit memory accesses are translated and protected, and endianness is applied, as though the current virtualization mode were set to MPV and the current nominal privilege mode were set to MPP. enumerates the cases.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 1461, + 1467 + ] + }, + { + "chunk_id": "chunk_17906cbd", + "text": "|1 |0 |0 |U-level access with HS-level translation and protection only.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1476, + 1476 + ] + }, + { + "chunk_id": "chunk_8d322266", + "text": "|1 |0 |1 |HS-level access with HS-level translation and protection only.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1478, + 1478 + ] + }, + { + "chunk_id": "chunk_e568182e", + "text": "|1 |- |3 |M-level access with no translation.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1480, + 1480 + ] + }, + { + "chunk_id": "chunk_f84de12f", + "text": "|1 |1 |0 |VU-level access with two-stage translation and protection.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1482, + 1485 + ] + }, + { + "chunk_id": "chunk_382f875f", + "text": "The HS-level MXR bit makes any executable page readable. `vsstatus`.MXR makes readable those pages marked executable at the VS translation stage, but only if readable at the guest-physical translation stage.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1482, + 1485 + ] + }, + { + "chunk_id": "chunk_2ddf2fe5", + "text": "|1 |1 |1 |VS-level access with two-stage translation and protection.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1487, + 1492 + ] + }, + { + "chunk_id": "chunk_c210b6c0", + "text": "The HS-level MXR bit makes any executable page readable. `vsstatus`.MXR makes readable those pages marked executable at the VS translation stage, but only if readable at the guest-physical translation stage. `vsstatus`.SUM applies instead of the HS-level SUM bit. |", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1487, + 1492 + ] + }, + { + "chunk_id": "chunk_15e20f00", + "text": "MPRV does not affect the virtual-machine load/store instructions, HLV, HLVX, and HSV.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1494, + 1498 + ] + }, + { + "chunk_id": "chunk_875a74cb", + "text": "The explicit loads and stores of these instructions always act as though V=1 and the nominal privilege mode were `hstatus`.SPVP, overriding MPRV.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1494, + 1498 + ] + }, + { + "chunk_id": "chunk_5c58504f", + "text": "The `mstatus` register is a superset of the HS-level `sstatus` register but is not a superset of `vsstatus`.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1500, + 1501 + ] + }, + { + "chunk_id": "chunk_f95c4773", + "text": "When the hypervisor extension is implemented, bits 10, 6, and 2 of `mideleg` (corresponding to the standard VS-level interrupts) are each read-only one.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Interrupt Delegation (`mideleg`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1505, + 1512 + ] + }, + { + "chunk_id": "chunk_b5ea0401", + "text": "Furthermore, if any guest external interrupts are implemented (GEILEN is nonzero), bit 12 of `mideleg` (corresponding to supervisor-level guest external interrupts) is also read-only one. VS-level interrupts and guest external interrupts are always delegated past M-mode to HS-mode.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Interrupt Delegation (`mideleg`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1505, + 1512 + ] + }, + { + "chunk_id": "chunk_a7b9e527", + "text": "For bits of `mideleg` that are zero, the corresponding bits in `hideleg`, `hip`, and `hie` are read-only zeros.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Interrupt Delegation (`mideleg`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 1514, + 1516 + ] + }, + { + "chunk_id": "chunk_da29e809", + "text": "The hypervisor extension gives registers `mip` and `mie` additional active bits for the hypervisor-added interrupts. and show the standard portions (bits 15:0) of registers `mip` and `mie` when the hypervisor extension is implemented.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1520, + 1524 + ] + }, + { + "chunk_id": "chunk_8b4571db", + "text": "Bits SGEIP, VSEIP, VSTIP, and VSSIP in `mip` are aliases for the same bits in hypervisor CSR `hip`, while SGEIE, VSEIE, VSTIE, and VSSIE in `mie` are aliases for the same bits in `hie`.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1534, + 1537 + ] + }, + { + "chunk_id": "chunk_fe493137", + "text": "The `mtval2` register is an MXLEN-bit read/write register formatted as shown in .", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Second Trap Value (`mtval2`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 1541, + 1545 + ] + }, + { + "chunk_id": "chunk_4b675bb9", + "text": "When a trap is taken into M-mode, `mtval2` is written with additional exception-specific information, alongside `mtval`, to assist software in handling the trap.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Second Trap Value (`mtval2`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1541, + 1545 + ] + }, + { + "chunk_id": "chunk_7cc21a12", + "text": "When a guest-page-fault trap is taken into M-mode, `mtval2` is written with either zero or the guest physical address that faulted, shifted right by 2 bits.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Second Trap Value (`mtval2`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 1551, + 1555 + ] + }, + { + "chunk_id": "chunk_5c95a968", + "text": "For other traps, `mtval2` is set to zero, but a future standard or extension may redefine `mtval2's` setting for other traps.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Second Trap Value (`mtval2`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 1551, + 1555 + ] + }, + { + "chunk_id": "chunk_55c0cc71", + "text": "If a guest-page fault is due to an implicit memory access during first-stage (VS-stage) address translation, a guest physical address written to `mtval2` is that of the implicit memory access that faulted.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Second Trap Value (`mtval2`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1557, + 1562 + ] + }, + { + "chunk_id": "chunk_9eccbcb3", + "text": "Additional information is provided in CSR `mtinst` to disambiguate such situations.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Second Trap Value (`mtval2`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1557, + 1562 + ] + }, + { + "chunk_id": "chunk_b4ccc89f", + "text": "Otherwise, for misaligned loads and stores that cause guest-page faults, a nonzero guest physical address in `mtval2` corresponds to the faulting portion of the access as indicated by the virtual address in `mtval`.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Second Trap Value (`mtval2`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1564, + 1570 + ] + }, + { + "chunk_id": "chunk_5789f21d", + "text": "For instruction guest-page faults on systems with variable-length instructions, a nonzero `mtval2` corresponds to the faulting portion of the instruction as indicated by the virtual address in `mtval`.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Second Trap Value (`mtval2`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1564, + 1570 + ] + }, + { + "chunk_id": "chunk_c6da0336", + "text": "`mtval2` is a *WARL* register that must be able to hold zero and may be capable of holding only an arbitrary subset of other 2-bit-shifted guest physical addresses, if any.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Second Trap Value (`mtval2`) Register", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 1572, + 1575 + ] + }, + { + "chunk_id": "chunk_ca921bc7", + "text": "The `mtinst` register is an MXLEN-bit read/write register formatted as shown in .", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Trap Instruction (`mtinst`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 1584, + 1590 + ] + }, + { + "chunk_id": "chunk_9bebe7e3", + "text": "When a trap is taken into M-mode, `mtinst` is written with a value that, if nonzero, provides information about the instruction that trapped, to assist software in handling the trap.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Trap Instruction (`mtinst`) Register", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 1584, + 1590 + ] + }, + { + "chunk_id": "chunk_e07ad9d3", + "text": "The values that may be written to `mtinst` on a trap are documented in .", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Trap Instruction (`mtinst`) Register", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1584, + 1590 + ] + }, + { + "chunk_id": "chunk_b61ada3f", + "text": "`mtinst` is a *WARL* register that need only be able to hold the values that the implementation may automatically write to it on a trap.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Trap Instruction (`mtinst`) Register", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1596, + 1598 + ] + }, + { + "chunk_id": "chunk_a2530cb4", + "text": "For any virtual memory access, the original virtual address is converted in the first stage by VS-level address translation, as controlled by the `vsatp` register, into a guest physical address.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1603, + 1614 + ] + }, + { + "chunk_id": "chunk_32db608b", + "text": "The guest physical address is then converted in the second stage by guest physical address translation, as controlled by the `hgatp` register, into a supervisor physical address.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1603, + 1614 + ] + }, + { + "chunk_id": "chunk_7b0b0112", + "text": "Although there is no option to disable two-stage address translation when V=1, either stage of translation can be effectively disabled by zeroing the corresponding `vsatp` or `hgatp` register.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 1603, + 1614 + ] + }, + { + "chunk_id": "chunk_9bb20607", + "text": "The `vsstatus` field MXR, which makes execute-only pages readable by explicit loads, only overrides VS-stage page protection.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1616, + 1620 + ] + }, + { + "chunk_id": "chunk_bd1e0cad", + "text": "When V=1, memory accesses that would normally bypass address translation are subject to G-stage address translation alone.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1622, + 1626 + ] + }, + { + "chunk_id": "chunk_269bb636", + "text": "The mapping of guest physical addresses to supervisor physical addresses is controlled by CSR `hgatp` ().", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest Physical Address Translation", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1635, + 1636 + ] + }, + { + "chunk_id": "chunk_599e7525", + "text": "When the address translation scheme selected by the MODE field of `hgatp` is Bare, guest physical addresses are equal to supervisor physical addresses without modification, and no memory protection applies in the trivial translation of guest physical addresses to supervisor physical addresses.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest Physical Address Translation", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 1638, + 1643 + ] + }, + { + "chunk_id": "chunk_342abb64", + "text": "When `hgatp`.MODE specifies a translation scheme of Sv32x4, Sv39x4, Sv48x4, or Sv57x4, G-stage address translation is a variation on the usual page-based virtual address translation scheme of Sv32, Sv39, Sv48, or Sv57, respectively.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest Physical Address Translation", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1645, + 1657 + ] + }, + { + "chunk_id": "chunk_f2a0152c", + "text": "In each case, the size of the incoming address is widened by 2 bits (to 34, 41, 50, or 59 bits).", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest Physical Address Translation", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 1645, + 1657 + ] + }, + { + "chunk_id": "chunk_f6fcdf64", + "text": "Matching its larger size, the root page table also must be aligned to a 16 KiB boundary instead of the usual 4 KiB page boundary.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest Physical Address Translation", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1645, + 1657 + ] + }, + { + "chunk_id": "chunk_30518d9b", + "text": "Address bits 63:41 must all be zeros, or else a guest-page-fault exception occurs.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest Physical Address Translation", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 1674, + 1678 + ] + }, + { + "chunk_id": "chunk_bbd9acb6", + "text": "Address bits 63:50 must all be zeros, or else a guest-page-fault exception occurs.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest Physical Address Translation", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 1684, + 1690 + ] + }, + { + "chunk_id": "chunk_b2b32942", + "text": "Address bits 63:59 must all be zeros, or else a guest-page-fault exception occurs.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest Physical Address Translation", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 1696, + 1702 + ] + }, + { + "chunk_id": "chunk_6b372605", + "text": "`hgatp` substitutes for the usual `satp`; * for the translation to begin, the effective privilege mode must be VS-mode or VU-mode; * when checking the U bit, the current privilege mode is always taken to be U-mode; and * guest-page-fault exceptions are raised instead of regular page-fault exceptions.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest Physical Address Translation", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1714, + 1720 + ] + }, + { + "chunk_id": "chunk_1f606eb7", + "text": "Access type permissions\u2014readable, writable, or executable\u2014are checked during G-stage translation the same as for VS-stage translation.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest Physical Address Translation", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1722, + 1733 + ] + }, + { + "chunk_id": "chunk_c830f541", + "text": "For a memory access made to support VS-stage address translation (such as to read/write a VS-level page table), permissions and the need to set A and/or D bits at the G-stage level are checked as though for an implicit load or store, not for the original access type.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest Physical Address Translation", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "unknown", + "line_range": [ + 1722, + 1733 + ] + }, + { + "chunk_id": "chunk_0419f649", + "text": "However, any exception is always reported for the original access type (instruction, load, or store/AMO).", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest Physical Address Translation", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1722, + 1733 + ] + }, + { + "chunk_id": "chunk_2d7471f8", + "text": "Until its use is defined by a standard extension, it should be cleared by software for forward compatibility, and must be ignored by hardware.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest Physical Address Translation", + "confidence": "very_high", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 1735, + 1738 + ] + }, + { + "chunk_id": "chunk_369b03a0", + "text": "Guest-page-fault traps may be delegated from M-mode to HS-mode under the control of CSR `medeleg`, but cannot be delegated to other privilege modes.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest-Page Faults", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1742, + 1750 + ] + }, + { + "chunk_id": "chunk_26de2edd", + "text": "On a guest-page fault, CSR `mtval` or `stval` is written with the faulting guest virtual address as usual, and `mtval2` or `htval` is written either with zero or with the faulting guest physical address, shifted right by 2 bits. CSR `mtinst` or `htinst` may also be written with information about the faulting instruction or other reason for the access, as explained in .", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest-Page Faults", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 1742, + 1750 + ] + }, + { + "chunk_id": "chunk_47eb33f9", + "text": "When an instruction fetch or a misaligned memory access straddles a page boundary, two different address translations are involved.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest-Page Faults", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1752, + 1760 + ] + }, + { + "chunk_id": "chunk_386c9d17", + "text": "When a guest-page fault occurs in such a circumstance, the faulting virtual address written to `mtval`/`stval` is the same as would be required for a regular page fault.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest-Page Faults", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1752, + 1760 + ] + }, + { + "chunk_id": "chunk_87b440f0", + "text": "Thus, the faulting virtual address may be a page-boundary address that is higher than the instruction's original virtual address, if the byte at that page boundary is among the accessed bytes.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest-Page Faults", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1752, + 1760 + ] + }, + { + "chunk_id": "chunk_6023d93a", + "text": "When a guest-page fault is not due to an implicit memory access for VS-stage address translation, a nonzero guest physical address written to `mtval2`/`htval` shall correspond to the exact virtual address written to `mtval`/`stval`.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest-Page Faults", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1762, + 1766 + ] + }, + { + "chunk_id": "chunk_31bc138b", + "text": "When V=0, the virtual-address argument is an HS-level virtual address, and the ASID argument is an HS-level ASID.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Memory-Management Fences", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1771, + 1776 + ] + }, + { + "chunk_id": "chunk_84ddae0e", + "text": "When V=1, the virtual-address argument to SFENCE.VMA is a guest virtual address within the current virtual machine, and the ASID argument is a VS-level ASID within the current virtual machine.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Memory-Management Fences", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 1778, + 1787 + ] + }, + { + "chunk_id": "chunk_a589e043", + "text": "The current virtual machine is identified by the VMID field of CSR `hgatp`, and the effective ASID can be considered to be the combination of this VMID with the VS-level ASID.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Memory-Management Fences", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1778, + 1787 + ] + }, + { + "chunk_id": "chunk_a68aafcc", + "text": "It is noted there that, when PMP settings are modified in a manner that affects either the physical memory that holds page tables or the physical memory to which page tables point, M-mode software must synchronize the PMP settings with the virtual memory system.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Memory-Management Fences", + "confidence": "very_high", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 1793, + 1806 + ] + }, + { + "chunk_id": "chunk_71119529", + "text": "For HS-level address translation, this is accomplished by executing in M-mode an SFENCE.VMA instruction with rs1=`x0` and rs2=`x0`, after the PMP CSRs are written.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Memory-Management Fences", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1793, + 1806 + ] + }, + { + "chunk_id": "chunk_d245a42b", + "text": "Similarly, if the setting of the PBMTE or ADUE bits in `menvcfg` are changed, an HFENCE.GVMA instruction with rs1=`x0` and rs2=`x0` suffices to synchronize with respect to the altered interpretation of G-stage and VS-stage PTEs' PBMT and A/D bit fields, respectively.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Memory-Management Fences", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1808, + 1811 + ] + }, + { + "chunk_id": "chunk_478c5876", + "text": "By contrast, if the PBMTE or ADUE bits in `henvcfg` are changed, executing an HFENCE.VVMA with rs1=`x0` and rs2=`x0` suffices to synchronize with respect to the altered interpretation of VS-stage PTEs' PBMT and A/D bit fields for the currently active VMID.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Memory-Management Fences", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1813, + 1816 + ] + }, + { + "chunk_id": "chunk_ef9751d6", + "text": "Hence, to prevent speculative execution causing one guest's VS-stage translations to be cached under another guest's VMID, world-switch code should zero `vsatp`, then swap `hgatp`, then finally write the new `vsatp` value.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Memory-Management Fences", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1818, + 1824 + ] + }, + { + "chunk_id": "chunk_fa44f06d", + "text": "Similarly, if `henvcfg`.PBMTE/ADUE need be world-switched, they should be switched after zeroing `vsatp` but before writing the new `vsatp` value, obviating the need to execute an HFENCE.VVMA instruction.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Memory-Management Fences", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1818, + 1824 + ] + }, + { + "chunk_id": "chunk_ffbf9280", + "text": "Guest physical addresses (GPAs) are 2 bits wider than the corresponding virtual address translation modes, resulting in additional address translation schemes Sv32x4, Sv39x4, Sv48x4, and Sv57x4 for translating guest physical addresses to supervisor physical addresses.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Interaction with Pointer Masking", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 1829, + 1835 + ] + }, + { + "chunk_id": "chunk_fc06d024", + "text": "When running with virtualization in VS/VU mode with `vsatp.MODE` = Bare, this means that those two bits may be subject to pointer masking, depending on `hgatp.MODE` and `senvcfg.PMM`/`henvcfg.PMM` (for VU/VS mode).", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Interaction with Pointer Masking", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1829, + 1835 + ] + }, + { + "chunk_id": "chunk_ef4cce0b", + "text": "If `vsatp.MODE` != BARE, this issue does *not* apply.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Interaction with Pointer Masking", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1829, + 1835 + ] + }, + { + "chunk_id": "chunk_dca7c426", + "text": "To support implementations where (XLEN-PMLEN) can be less than the GPA width supported by `hgatp.MODE`, hypervisors should execute an `HFENCE.GVMA` with rs1=`x0` if the `henvcfg.PMM` is changed from or to a value where (XLEN-PMLEN) is less than GPA width supported by the `hgatp` translation mode of that guest.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Interaction with Pointer Masking", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 1837, + 1841 + ] + }, + { + "chunk_id": "chunk_5f5bdda9", + "text": "`PMLEN=7` and `hgatp.MODE=sv57x4` * `PMLEN=16` and `hgatp.MODE=sv57x4` * `PMLEN=16` and `hgatp.MODE=sv48x4`", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Interaction with Pointer Masking", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1843, + 1845 + ] + }, + { + "chunk_id": "chunk_be4a5ca9", + "text": "Implementation of an address-specific `HFENCE.GVMA` should either ignore the address argument, or should ignore the top masked GPA bits of entries when comparing for an address match.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Interaction with Pointer Masking", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 1847, + 1849 + ] + }, + { + "chunk_id": "chunk_f4dad70c", + "text": "The hypervisor extension augments the trap cause encoding. lists the possible M-mode and HS-mode trap cause codes when the hypervisor extension is implemented.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 1856, + 1865 + ] + }, + { + "chunk_id": "chunk_eaa6c765", + "text": "Codes are added for VS-level interrupts (interrupts 2, 6, 10), for supervisor-level guest external interrupts (interrupt 12), for virtual-instruction exceptions (exception 22), and for guest-page faults (exceptions 20, 21, 23).", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1856, + 1865 + ] + }, + { + "chunk_id": "chunk_dd5b99e4", + "text": "An instruction is HS-qualified if it would be valid to execute in HS-mode (for some values of the instruction's register operands), assuming fields TSR and TVM of CSR `mstatus` are both zero.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 2010, + 2018 + ] + }, + { + "chunk_id": "chunk_81ab7a59", + "text": "A special rule applies for CSR instructions that access 32-bit high-half CSRs such as `cycleh` and `htimedeltah`.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 2020, + 2027 + ] + }, + { + "chunk_id": "chunk_0cc21555", + "text": "Specifically, a virtual-instruction exception is raised for the following cases:", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 2029, + 2030 + ] + }, + { + "chunk_id": "chunk_06ee4487", + "text": "in VS-mode, attempts to access a non-high-half counter CSR when the corresponding bit in `hcounteren` is 0 and the same bit in `mcounteren` is 1;", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 2032, + 2034 + ] + }, + { + "chunk_id": "chunk_8997343a", + "text": "in VS-mode, if XLEN=32, attempts to access a high-half counter CSR when the corresponding bit in `hcounteren` is 0 and the same bit in `mcounteren` is 1;", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 2036, + 2038 + ] + }, + { + "chunk_id": "chunk_ff8b535a", + "text": "in VU-mode, attempts to access a non-high-half counter CSR when the corresponding bit in either `hcounteren` or `scounteren` is 0 and the same bit in `mcounteren` is 1;", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 2040, + 2042 + ] + }, + { + "chunk_id": "chunk_9f42f1f3", + "text": "in VU-mode, if XLEN=32, attempts to access a high-half counter CSR when the corresponding bit in either `hcounteren` or `scounteren` is 0 and the same bit in `mcounteren` is 1;", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 2044, + 2046 + ] + }, + { + "chunk_id": "chunk_fde5fa8d", + "text": "in VS-mode or VU-mode, attempts to access an implemented non-high-half hypervisor CSR or VS CSR when the same access (read/write) would be allowed in HS-mode, assuming `mstatus`.TVM=0;", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 2051, + 2053 + ] + }, + { + "chunk_id": "chunk_db911038", + "text": "in VS-mode or VU-mode, if XLEN=32, attempts to access an implemented high-half hypervisor CSR or high-half VS CSR when the same access (read/write) to the CSR\"s low-half partner would be allowed in HS-mode, assuming `mstatus`.TVM=0;", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 2055, + 2058 + ] + }, + { + "chunk_id": "chunk_d2c6ed2a", + "text": "in VU-mode, attempts to execute WFI when `mstatus`.TW=0, or to execute a supervisor instruction (SRET or SFENCE);", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 2060, + 2062 + ] + }, + { + "chunk_id": "chunk_0e1df0bc", + "text": "in VU-mode, attempts to access an implemented non-high-half supervisor CSR when the same access (read/write) would be allowed in HS-mode, assuming `mstatus`.TVM=0;", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 2064, + 2066 + ] + }, + { + "chunk_id": "chunk_491c6f29", + "text": "in VU-mode, if XLEN=32, attempts to access an implemented high-half supervisor CSR when the same access to the CSR's low-half partner would be allowed in HS-mode, assuming `mstatus`.TVM=0;", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 2068, + 2070 + ] + }, + { + "chunk_id": "chunk_29238bfa", + "text": "in VS-mode, attempts to execute WFI when `hstatus`.VTW=1 and `mstatus`.TW=0, unless the instruction completes within an implementation-specific, bounded time;", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 2072, + 2074 + ] + }, + { + "chunk_id": "chunk_53eff9c5", + "text": "in VS-mode, attempts to execute SRET when `hstatus`.VTSR=1; and", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 2076, + 2076 + ] + }, + { + "chunk_id": "chunk_0ccec86f", + "text": "in VS-mode, attempts to execute an SFENCE.VMA or SINVAL.VMA instruction or to access `satp`, when `hstatus`.VTVM=1.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 2078, + 2079 + ] + }, + { + "chunk_id": "chunk_701ba8a4", + "text": "Other extensions to the RISC-V Privileged Architecture may add to the set of circumstances that cause a virtual-instruction exception when V=1.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 2081, + 2083 + ] + }, + { + "chunk_id": "chunk_e777f3f0", + "text": "On a virtual-instruction trap, `mtval` or `stval` is written the same as for an illegal-instruction trap.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 2085, + 2087 + ] + }, + { + "chunk_id": "chunk_a6e433ca", + "text": "Fields FS and VS in registers `sstatus` and `vsstatus` deviate from the usual HS-qualified rule.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 2089, + 2094 + ] + }, + { + "chunk_id": "chunk_5775df11", + "text": "| .>|12, 20, 1 |During instruction address translation: + {nbsp}{nbsp}{nbsp}First encountered page fault, guest-page fault, or access fault", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2105, + 2107 + ] + }, + { + "chunk_id": "chunk_3734ffc5", + "text": "| .>|1 |With physical address for instruction: + {nbsp}{nbsp}{nbsp}Instruction access fault", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2109, + 2110 + ] + }, + { + "chunk_id": "chunk_b4e86448", + "text": "| |2 + 22 + 0 + 8, 9, 10, 11 + 3 + 3|Illegal instruction + Virtual instruction + Instruction address misaligned + Environment call + Environment break + {nbsp}{nbsp}{nbsp}Load/store/AMO address breakpoint", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 2112, + 2122 + ] + }, + { + "chunk_id": "chunk_1c8084c3", + "text": "| .>|13, 15, 21, 23, 5, 7 |During address translation for an explicit memory access: + {nbsp}{nbsp}{nbsp}First encountered page fault, guest-page fault, or access fault", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2127, + 2129 + ] + }, + { + "chunk_id": "chunk_612fb897", + "text": "| .>|5, 7 |With physical address for an explicit memory access: + {nbsp}{nbsp}{nbsp}Load/store/AMO access fault", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2131, + 2132 + ] + }, + { + "chunk_id": "chunk_c51ebb0f", + "text": "If not higher priority: + {nbsp}{nbsp}{nbsp}Load/store/AMO address misaligned |", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2134, + 2136 + ] + }, + { + "chunk_id": "chunk_fb76568a", + "text": "If an instruction may raise multiple synchronous exceptions, the decreasing priority order of indicates which exception is taken and reported in `mcause` or `scause`.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 2138, + 2141 + ] + }, + { + "chunk_id": "chunk_24fc34ea", + "text": "When a trap occurs in HS-mode or U-mode, it goes to M-mode, unless delegated by `medeleg` or `mideleg`, in which case it goes to HS-mode.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Entry", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 2145, + 2151 + ] + }, + { + "chunk_id": "chunk_a5a5d2dc", + "text": "When a trap occurs in VS-mode or VU-mode, it goes to M-mode, unless delegated by `medeleg` or `mideleg`, in which case it goes to HS-mode, unless further delegated by `hedeleg` or `hideleg`, in which case it goes to VS-mode.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Entry", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 2145, + 2151 + ] + }, + { + "chunk_id": "chunk_a73d2a82", + "text": "When a trap is taken into M-mode, virtualization mode V gets set to 0, and fields MPV and MPP in `mstatus` (or `mstatush`) are set according to . A trap into M-mode also writes fields GVA, MPIE, and MIE in `mstatus`/`mstatush` and writes CSRs `mepc`, `mcause`, `mtval`, `mtval2`, and `mtinst`.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Entry", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 2153, + 2158 + ] + }, + { + "chunk_id": "chunk_9b199fb3", + "text": "Upon trap return, MPV is ignored when MPP=3. | |Previous Mode |MPV |MPP |U-mode + HS-mode + M-mode|0 + 0 + 0|0 + 1 + 3 |VU-mode + VS-mode|1 + 1|0 + 1 |", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Entry", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2160, + 2176 + ] + }, + { + "chunk_id": "chunk_8f18df7e", + "text": "When a trap is taken into HS-mode, virtualization mode V is set to 0, and `hstatus`.SPV and `sstatus`.SPP are set according to .", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Entry", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 2178, + 2185 + ] + }, + { + "chunk_id": "chunk_5bbd5b3f", + "text": "If V was 1 before the trap, field SPVP in `hstatus` is set the same as `sstatus`.SPP; otherwise, SPVP is left unchanged. A trap into HS-mode also writes field GVA in `hstatus`, fields SPIE and SIE in `sstatus`, and CSRs `sepc`, `scause`, `stval`, `htval`, and `htinst`.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Entry", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 2178, + 2185 + ] + }, + { + "chunk_id": "chunk_068959bb", + "text": "When a trap is taken into VS-mode, `vsstatus`.SPP is set according to .", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Entry", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 2202, + 2207 + ] + }, + { + "chunk_id": "chunk_be568592", + "text": "Register `hstatus` and the HS-level `sstatus` are not modified, and the virtualization mode V remains 1. A trap into VS-mode also writes fields SPIE and SIE in `vsstatus` and writes CSRs `vsepc`, `vscause`, and `vstval`.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Entry", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 2202, + 2207 + ] + }, + { + "chunk_id": "chunk_c5afdc44", + "text": "On any trap into M-mode or HS-mode, one of these values is written automatically into the appropriate trap instruction CSR, `mtinst` or `htinst`:", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 2222, + 2225 + ] + }, + { + "chunk_id": "chunk_e893690b", + "text": "zero; * a transformation of the trapping instruction; * a custom value (allowed only if the trapping instruction is non-standard); or * a special pseudoinstruction.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2227, + 2231 + ] + }, + { + "chunk_id": "chunk_df7fc916", + "text": "Except when a pseudoinstruction value is required (described later), the value written to `mtinst` or `htinst` may always be zero, indicating that the hardware is providing no information in the register for this particular trap.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 2233, + 2236 + ] + }, + { + "chunk_id": "chunk_16c619bf", + "text": "On an interrupt, the value written to the trap instruction register is always zero.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2238, + 2241 + ] + }, + { + "chunk_id": "chunk_24cc76a6", + "text": "On a synchronous exception, if a nonzero value is written, one of the following shall be true about the value:", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 2238, + 2241 + ] + }, + { + "chunk_id": "chunk_394c6ef8", + "text": "The instruction that trapped is a non-standard instruction.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2243, + 2261 + ] + }, + { + "chunk_id": "chunk_80469efb", + "text": "These three cases exclude a large number of other possible values, such as all those having bits 1:0 equal to binary `10`. A future standard or extension may define additional cases, thus allowing values that are currently excluded.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 2263, + 2267 + ] + }, + { + "chunk_id": "chunk_149ceadf", + "text": "Software may safely treat an unrecognized value in a trap instruction register the same as zero.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 2263, + 2267 + ] + }, + { + "chunk_id": "chunk_bef5959a", + "text": "shows the values that may be automatically written to the trap instruction register for each standard exception cause.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 2269, + 2277 + ] + }, + { + "chunk_id": "chunk_745587fd", + "text": "For exceptions that prevent the fetching of an instruction, only zero or a pseudoinstruction value may be written. A custom value may be automatically written only if the instruction that traps is non-standard. A future standard or extension may permit other values to be written, chosen from the set of allowed values established earlier.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 2269, + 2277 + ] + }, + { + "chunk_id": "chunk_8c1069c2", + "text": "As enumerated in the table, a synchronous exception may write to the trap instruction register a standard transformation of the trapping instruction only for exceptions that arise from explicit memory accesses (from loads, stores, and AMO instructions).", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 2366, + 2374 + ] + }, + { + "chunk_id": "chunk_5ef16e19", + "text": "If a synchronous trap occurs for a standard instruction for which no transformation has been defined, the trap instruction register shall be written with zero (or, under certain circumstances, with a special pseudoinstruction value).", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 2366, + 2374 + ] + }, + { + "chunk_id": "chunk_8647653d", + "text": "All fields are the same as the trapping instruction except bits 19:15, Addr.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 2396, + 2398 + ] + }, + { + "chunk_id": "chunk_8432733c", + "text": "All fields are the same as the trapping instruction except bits 19:15, Addr.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 2402, + 2404 + ] + }, + { + "chunk_id": "chunk_bba5be3c", + "text": "Offset field that replaces the instruction\u2019s rs1 field in bits 19:15 is the positive difference between the faulting virtual address (written to `mtval` or `stval`) and the original virtual address.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 2406, + 2412 + ] + }, + { + "chunk_id": "chunk_48220cff", + "text": "For a standard compressed instruction (16-bit size), the transformed instruction is found as follows:", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 2414, + 2415 + ] + }, + { + "chunk_id": "chunk_eceff6b1", + "text": "Expand the compressed instruction to its 32-bit equivalent. .", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 2417, + 2419 + ] + }, + { + "chunk_id": "chunk_e3d04ea6", + "text": "Transform the 32-bit equivalent instruction. .", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 2417, + 2419 + ] + }, + { + "chunk_id": "chunk_212bc87d", + "text": "Bits 1:0 of a transformed standard instruction will be binary `01` if the trapping instruction is compressed and `11` if not.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2421, + 2430 + ] + }, + { + "chunk_id": "chunk_fffc4541", + "text": "For guest-page faults, the trap instruction register is written with a special pseudoinstruction value if: (a) the fault is caused by an implicit memory access for VS-stage address translation, and (b) a nonzero value (the faulting guest physical address) is written to `mtval2` or `htval`.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 2421, + 2430 + ] + }, + { + "chunk_id": "chunk_2b6cc690", + "text": "If both conditions are met, the value written to `mtinst` or `htinst` must be taken from ; zero is not allowed.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 2421, + 2430 + ] + }, + { + "chunk_id": "chunk_9a304863", + "text": "The RV32 values are used when VSXLEN=32, and the RV64 values when VSXLEN=64. | |Value |Meaning |`0x00002000` + `0x00002020` |32-bit read for VS-stage address translation (RV32) + 32-bit write for VS-stage address translation (RV32)", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 2432, + 2440 + ] + }, + { + "chunk_id": "chunk_21b709a3", + "text": "|`0x00003000` + `0x00003020` |64-bit read for VS-stage address translation (RV64) + 64-bit write for VS-stage address translation (RV64) |", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 2442, + 2446 + ] + }, + { + "chunk_id": "chunk_1487f3e0", + "text": "If a machine never automatically updates bits A or D in VS-level page tables (leaving this to software), the write case will never arise.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 2468, + 2476 + ] + }, + { + "chunk_id": "chunk_8b7badfd", + "text": "The fact that such a page table update must actually be atomic, not just a simple write, is ignored for the pseudoinstruction.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 2468, + 2476 + ] + }, + { + "chunk_id": "chunk_0ba95008", + "text": "The MRET instruction is used to return from a trap taken into M-mode. MRET first determines what the new privilege mode will be according to the values of MPP and MPV in `mstatus` or `mstatush`, as encoded in . MRET then in `mstatus`/`mstatush` sets MPV=0, MPP=0, MIE=MPIE, and MPIE=1.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Return", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 2480, + 2486 + ] + }, + { + "chunk_id": "chunk_82a02977", + "text": "Lastly, MRET sets the privilege mode as previously determined, and sets `pc`=`mepc`.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Return", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 2480, + 2486 + ] + }, + { + "chunk_id": "chunk_4b5c75c2", + "text": "The SRET instruction is used to return from a trap taken into HS-mode or VS-mode.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Return", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2488, + 2490 + ] + }, + { + "chunk_id": "chunk_e351ea1c", + "text": "Lastly, SRET sets the privilege mode as previously determined, and sets `pc`=`sepc`.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Return", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 2492, + 2498 + ] + }, + { + "chunk_id": "chunk_8816ee5b", + "text": "If the Ssdbltrp extension is implemented, when `SRET` is executed in HS-mode, if the new privilege mode is VU, the `SRET` instruction sets `vsstatus.SDT` to 0.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Return", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 2505, + 2508 + ] + }, + { + "chunk_id": "chunk_b1f4ca1d", + "text": "When executed in VS-mode, `vsstatus.SDT` is set to 0.", + "source_file": "src/priv/hypervisor.adoc", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Return", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 2505, + 2508 + ] + } + ] + }, + { + "file": "src/priv/machine.adoc", + "chunks": [ + { + "chunk_id": "chunk_e9a76ac0", + "text": "In addition to the machine-level CSRs described in this section, M-mode code can access all CSRs at lower privilege levels.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 14, + 15 + ] + }, + { + "chunk_id": "chunk_6f06d230", + "text": "The `misa` CSR is a *WARL* read-write register reporting the ISA supported by the hart.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 20, + 22 + ] + }, + { + "chunk_id": "chunk_9819937e", + "text": "This register must be readable in any implementation, but a value of zero can be returned to indicate the `misa` register has not been implemented, requiring that CPU capabilities be determined through a separate non-standard mechanism.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register", + "confidence": "very_high", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 20, + 22 + ] + }, + { + "chunk_id": "chunk_4c7438f4", + "text": "The MXL (Machine XLEN) field encodes the native base integer ISA width as shown in .", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 28, + 34 + ] + }, + { + "chunk_id": "chunk_4d93702e", + "text": "The MXL field is read-only.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 28, + 34 + ] + }, + { + "chunk_id": "chunk_fc2a1c69", + "text": "If `misa` is nonzero, the MXL field indicates the effective XLEN in M-mode, a constant termed MXLEN. XLEN is never greater than MXLEN, but XLEN might be smaller than MXLEN in less-privileged modes.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "range", + "line_range": [ + 28, + 34 + ] + }, + { + "chunk_id": "chunk_22a2b799", + "text": "The `misa` CSR is MXLEN bits wide.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 49, + 49 + ] + }, + { + "chunk_id": "chunk_36d79ce7", + "text": "The Extensions field encodes the presence of the standard extensions, with a single bit per letter of the alphabet (bit 0 encodes presence of extension \"A\" , bit 1 encodes presence of extension \"B\", through to bit 25 which encodes \"Z\").", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 51, + 60 + ] + }, + { + "chunk_id": "chunk_991a2ee1", + "text": "The \"I\" bit will be set for the RV32I and RV64I base ISAs, and the \"E\" bit will be set for RV32E and RV64E.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 51, + 60 + ] + }, + { + "chunk_id": "chunk_c8664878", + "text": "The Extensions field is a *WARL* field that can contain writable bits where the implementation allows the supported ISA to be modified.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 51, + 60 + ] + }, + { + "chunk_id": "chunk_76b3c6e2", + "text": "At reset, the Extensions field shall contain the maximal set of supported extensions, and \"I\" shall be selected over \"E\" if both are available.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 51, + 60 + ] + }, + { + "chunk_id": "chunk_862bd1c1", + "text": "When a standard extension is disabled by clearing its bit in `misa`, the instructions and CSRs defined or modified by the extension revert to their defined or reserved behaviors as if the extension is not implemented.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 62, + 66 + ] + }, + { + "chunk_id": "chunk_30c90b78", + "text": "All bits that are reserved for future use must return zero when read.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 68, + 68 + ] + }, + { + "chunk_id": "chunk_f7970e21", + "text": "The \"X\" bit will be set if there are any non-standard extensions.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 103, + 103 + ] + }, + { + "chunk_id": "chunk_a0845f35", + "text": "When the \"B\" bit is 1, the implementation supports the instructions provided by the Zba, Zbb, and Zbs extensions.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 105, + 107 + ] + }, + { + "chunk_id": "chunk_cb848c3e", + "text": "When the \"B\" bit is 0, it indicates that the implementation might not support one or more of the Zba, Zbb, or Zbs extensions.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 105, + 107 + ] + }, + { + "chunk_id": "chunk_4aa6eded", + "text": "When the \"M\" bit is 1, the implementation supports all multiply and division instructions defined by the M extension.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 109, + 114 + ] + }, + { + "chunk_id": "chunk_e9e6c591", + "text": "When the \"M\" bit is 0, it indicates that the implementation might not support those instructions.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 109, + 114 + ] + }, + { + "chunk_id": "chunk_5f0a7a28", + "text": "However if the Zmmul extension is supported then the multiply instructions it specifies are supported irrespective of the value of the \"M\" bit.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 109, + 114 + ] + }, + { + "chunk_id": "chunk_ca9cd033", + "text": "When the \"S\" bit is 1, the implementation supports supervisor mode.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 116, + 117 + ] + }, + { + "chunk_id": "chunk_7ba8af4b", + "text": "When the \"S\" bit is 0, the implementation might not support supervisor mode.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 116, + 117 + ] + }, + { + "chunk_id": "chunk_edfbe79f", + "text": "When the \"U\" bit is 1, the implementation supports user mode.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 119, + 120 + ] + }, + { + "chunk_id": "chunk_d9961f7f", + "text": "When the \"U\" bit is 0, the implementation might not support user mode.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 119, + 120 + ] + }, + { + "chunk_id": "chunk_90269600", + "text": "Unless `misa` is all read-only zero, the \"E\" bit always reads as the complement of the \"I\" bit.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 122, + 126 + ] + }, + { + "chunk_id": "chunk_c0e72d8d", + "text": "If an execution environment supports both RV32E and RV32I, software can select RV32E by clearing the \"I\" bit.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 122, + 126 + ] + }, + { + "chunk_id": "chunk_dd12ae84", + "text": "If an ISA feature x depends on an ISA feature y, then attempting to enable feature x but disable feature y results in both features being disabled.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 128, + 132 + ] + }, + { + "chunk_id": "chunk_aa9c505e", + "text": "Similarly, setting \"U\"=0 and \"S\"=1\" results in both \"U\" and \"S\" being cleared.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 128, + 132 + ] + }, + { + "chunk_id": "chunk_718b7630", + "text": "An implementation may impose additional constraints on the collective setting of two or more `misa` fields, in which case they function collectively as a single *WARL* field.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 134, + 136 + ] + }, + { + "chunk_id": "chunk_bacd4e20", + "text": "An attempt to write an unsupported combination causes those bits to be set to some supported combination.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 134, + 136 + ] + }, + { + "chunk_id": "chunk_8e940445", + "text": "If an instruction that would write `misa` increases IALIGN, and the subsequent instruction's address is not IALIGN-bit aligned, the write to `misa` is suppressed, leaving `misa` unchanged.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 138, + 141 + ] + }, + { + "chunk_id": "chunk_8588ac0f", + "text": "When software enables an extension that was previously disabled, then all state uniquely associated with that extension is UNSPECIFIED, unless otherwise specified by that extension.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "binary", + "line_range": [ + 143, + 144 + ] + }, + { + "chunk_id": "chunk_db151edd", + "text": "This follows from the fact that, when a feature is not implemented, the corresponding opcodes and CSRs become reserved, not necessarily illegal.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 146, + 151 + ] + }, + { + "chunk_id": "chunk_672576dc", + "text": "The `mvendorid` CSR is a 32-bit read-only register providing the JEDEC manufacturer ID of the provider of the core.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Vendor ID (`mvendorid`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 155, + 158 + ] + }, + { + "chunk_id": "chunk_6abd382e", + "text": "This register must be readable in any implementation, but a value of 0 can be returned to indicate the field is not implemented or that this is a non-commercial implementation.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Vendor ID (`mvendorid`) Register", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 155, + 158 + ] + }, + { + "chunk_id": "chunk_c3bcd73f", + "text": "JEDEC manufacturer IDs are ordinarily encoded as a sequence of one-byte continuation codes `0x7f`, terminated by a one-byte ID not equal to `0x7f`, with an odd parity bit in the most-significant bit of each byte. `mvendorid` encodes the number of one-byte continuation codes in the Bank field, and encodes the final byte in the Offset field, discarding the parity bit.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Vendor ID (`mvendorid`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 163, + 171 + ] + }, + { + "chunk_id": "chunk_1fbed088", + "text": "The `marchid` CSR is an MXLEN-bit read-only register encoding the base microarchitecture of the hart.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Architecture ID (`marchid`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 175, + 179 + ] + }, + { + "chunk_id": "chunk_e002291a", + "text": "This register must be readable in any implementation, but a value of 0 can be returned to indicate the field is not implemented.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Architecture ID (`marchid`) Register", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 175, + 179 + ] + }, + { + "chunk_id": "chunk_e7e593be", + "text": "The combination of `mvendorid` and `marchid` should uniquely identify the type of hart microarchitecture that is implemented.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Architecture ID (`marchid`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 175, + 179 + ] + }, + { + "chunk_id": "chunk_d1f138cb", + "text": "Open-source project architecture IDs are allocated globally by RISC-V International, and have non-zero architecture IDs with a zero most-significant-bit (MSB).", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Architecture ID (`marchid`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 184, + 188 + ] + }, + { + "chunk_id": "chunk_2a9fbcfa", + "text": "Commercial architecture IDs are allocated by each commercial vendor independently, but must have the MSB set and cannot contain zero in the remaining MXLEN-1 bits.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Architecture ID (`marchid`) Register", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 184, + 188 + ] + }, + { + "chunk_id": "chunk_a84843ca", + "text": "The `mimpid` CSR provides a unique encoding of the version of the processor implementation.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Implementation ID (`mimpid`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 192, + 196 + ] + }, + { + "chunk_id": "chunk_d6caf0d6", + "text": "This register must be readable in any implementation, but a value of 0 can be returned to indicate that the field is not implemented.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Implementation ID (`mimpid`) Register", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 192, + 196 + ] + }, + { + "chunk_id": "chunk_2d95a171", + "text": "The Implementation value should reflect the design of the RISC-V processor itself and not any surrounding system.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Implementation ID (`mimpid`) Register", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 192, + 196 + ] + }, + { + "chunk_id": "chunk_35df174f", + "text": "The `mhartid` CSR is an MXLEN-bit read-only register containing the integer ID of the hardware thread running the code.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Hart ID (`mhartid`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 203, + 208 + ] + }, + { + "chunk_id": "chunk_d3452757", + "text": "This register must be readable in any implementation.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Hart ID (`mhartid`) Register", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 203, + 208 + ] + }, + { + "chunk_id": "chunk_86db0f32", + "text": "Hart IDs might not necessarily be numbered contiguously in a multiprocessor system, but one hart must have a hart ID of zero.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Hart ID (`mhartid`) Register", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 203, + 208 + ] + }, + { + "chunk_id": "chunk_314a1b37", + "text": "Hart IDs must be unique within the execution environment.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Hart ID (`mhartid`) Register", + "confidence": "very_high", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 203, + 208 + ] + }, + { + "chunk_id": "chunk_71fa0660", + "text": "The `mstatus` register is an MXLEN-bit read/write register formatted as shown in for RV32 and for RV64.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 216, + 219 + ] + }, + { + "chunk_id": "chunk_2134a124", + "text": "The `mstatus` register keeps track of and controls the hart\u2019s current operating state. A restricted view of `mstatus` appears as the `sstatus` register in the S-level ISA.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 216, + 219 + ] + }, + { + "chunk_id": "chunk_10cb3454", + "text": "For RV32 only, `mstatush` is a 32-bit read/write register formatted as shown in .", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 229, + 230 + ] + }, + { + "chunk_id": "chunk_1682a7ed", + "text": "Bits 30:4 of `mstatush` generally contain the same fields found in bits 62:36 of `mstatus` for RV64.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 229, + 230 + ] + }, + { + "chunk_id": "chunk_30970987", + "text": "Fields SD, SXL, and UXL do not exist in `mstatush`.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 229, + 230 + ] + }, + { + "chunk_id": "chunk_35778d61", + "text": "Global interrupt-enable bits, MIE and SIE, are provided for M-mode and S-mode respectively.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Privilege and Global Interrupt-Enable Stack in `mstatus` register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 239, + 241 + ] + }, + { + "chunk_id": "chunk_31a835a3", + "text": "These bits are primarily used to guarantee atomicity with respect to interrupt handlers in the current privilege mode.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Privilege and Global Interrupt-Enable Stack in `mstatus` register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 239, + 241 + ] + }, + { + "chunk_id": "chunk_a6b200b1", + "text": "When a hart is executing in privilege mode x, interrupts are globally enabled when xIE=1 and globally disabled when xIE=0.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Privilege and Global Interrupt-Enable Stack in `mstatus` register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 243, + 253 + ] + }, + { + "chunk_id": "chunk_0130fe70", + "text": "Interrupts for lower-privilege modes, w Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Privilege and Global Interrupt-Enable Stack in `mstatus` register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 243, + 253 + ] + }, + { + "chunk_id": "chunk_94f1efa9", + "text": "Interrupts for higher-privilege modes, y>x, are always globally enabled regardless of the setting of the global yIE bit for the higher-privilege mode.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Privilege and Global Interrupt-Enable Stack in `mstatus` register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 243, + 253 + ] + }, + { + "chunk_id": "chunk_0b5a78e3", + "text": "Higher-privilege-level code can use separate per-interrupt enable bits to disable selected higher-privilege-mode interrupts before ceding control to a lower-privilege mode.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Privilege and Global Interrupt-Enable Stack in `mstatus` register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 243, + 253 + ] + }, + { + "chunk_id": "chunk_bbb39e07", + "text": "If supervisor mode is not implemented, then SIE and SPIE are read-only 0.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Privilege and Global Interrupt-Enable Stack in `mstatus` register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 243, + 253 + ] + }, + { + "chunk_id": "chunk_da8ed0de", + "text": "To support nested traps, each privilege mode x that can respond to interrupts has a two-level stack of interrupt-enable bits and privilege modes. xPIE holds the value of the interrupt-enable bit active prior to the trap, and xPP holds the previous privilege mode.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Privilege and Global Interrupt-Enable Stack in `mstatus` register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 255, + 263 + ] + }, + { + "chunk_id": "chunk_609c79f5", + "text": "The xPP fields can only hold privilege modes up to x, so MPP is two bits wide and SPP is one bit wide.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Privilege and Global Interrupt-Enable Stack in `mstatus` register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 255, + 263 + ] + }, + { + "chunk_id": "chunk_cc5270a8", + "text": "When a trap is taken from privilege mode y into privilege mode x, xPIE is set to the value of xIE; xIE is set to 0; and xPP is set to y.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Privilege and Global Interrupt-Enable Stack in `mstatus` register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 255, + 263 + ] + }, + { + "chunk_id": "chunk_2749fc79", + "text": "An MRET or SRET instruction is used to return from a trap in M-mode or S-mode respectively.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Privilege and Global Interrupt-Enable Stack in `mstatus` register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 265, + 270 + ] + }, + { + "chunk_id": "chunk_72ff488f", + "text": "When executing an xRET instruction, supposing xPP holds the value y, xIE is set to xPIE; the privilege mode is changed to y; xPIE is set to 1; and xPP is set to the least-privileged supported mode (U if U-mode is implemented, else M).", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Privilege and Global Interrupt-Enable Stack in `mstatus` register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 265, + 270 + ] + }, + { + "chunk_id": "chunk_46fb9761", + "text": "If y{ne}M, xRET also sets MPRV=0.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Privilege and Global Interrupt-Enable Stack in `mstatus` register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 265, + 270 + ] + }, + { + "chunk_id": "chunk_351dd344", + "text": "xPP fields are *WARL* fields that can hold only privilege mode x and any implemented privilege mode lower than x.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Privilege and Global Interrupt-Enable Stack in `mstatus` register", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 272, + 273 + ] + }, + { + "chunk_id": "chunk_ebedc1a9", + "text": "If privilege mode x is not implemented, then xPP must be read-only 0.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Privilege and Global Interrupt-Enable Stack in `mstatus` register", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 272, + 273 + ] + }, + { + "chunk_id": "chunk_a7ea798a", + "text": "This non-reentrancy usually occurs in the early phase of trap handling, wherein the trap handler has not yet preserved the necessary state to handle and resume from the trap.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 278, + 290 + ] + }, + { + "chunk_id": "chunk_e04aa34c", + "text": "The occurrence of a trap during this phase can lead to an overwrite of critical state information, resulting in the loss of data needed to recover from the initial trap.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 278, + 290 + ] + }, + { + "chunk_id": "chunk_19960020", + "text": "The trap that caused this critical error condition is henceforth called the unexpected trap.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 278, + 290 + ] + }, + { + "chunk_id": "chunk_02166ef0", + "text": "However, managing Hardware-Error exceptions, which may occur unpredictably, presents significant challenges in trap handler implementation due to the potential risk of a double trap.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 278, + 290 + ] + }, + { + "chunk_id": "chunk_d92018ea", + "text": "The M-mode-disable-trap (`MDT`) bit is a WARL field introduced by the Smdbltrp extension.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 292, + 300 + ] + }, + { + "chunk_id": "chunk_c600edad", + "text": "Upon reset, the `MDT` field is set to 1.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 292, + 300 + ] + }, + { + "chunk_id": "chunk_bc3a8d4d", + "text": "When the `MDT` bit is set to 1 by an explicit CSR write, the `MIE` (Machine Interrupt Enable) bit is cleared to 0.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 292, + 300 + ] + }, + { + "chunk_id": "chunk_4a445d7c", + "text": "For RV64, this clearing occurs regardless of the value written, if any, to the `MIE` bit by the same write.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 292, + 300 + ] + }, + { + "chunk_id": "chunk_03fcbbf7", + "text": "The `MIE` bit can only be set to 1 by an explicit CSR write if the `MDT` bit is already 0 or, for RV64, is being set to 0 by the same write (For RV32, the `MDT` bit is in `mstatush` and the `MIE` bit in `mstatus` register).", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 292, + 300 + ] + }, + { + "chunk_id": "chunk_1a182aaa", + "text": "When a trap is to be taken into M-mode, if the `MDT` bit is currently 0, it is then set to 1, and the trap is delivered as expected.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 302, + 309 + ] + }, + { + "chunk_id": "chunk_1fecd47e", + "text": "However, if `MDT` is already set to 1, then this is an unexpected trap.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 302, + 309 + ] + }, + { + "chunk_id": "chunk_e020ed27", + "text": "When the Smrnmi extension is implemented, a trap caused by an RNMI is not considered an unexpected trap irrespective of the state of the `MDT` bit. A trap caused by an RNMI does not set the `MDT` bit.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 302, + 309 + ] + }, + { + "chunk_id": "chunk_073212d6", + "text": "However, a trap that occurs when executing in M-mode with `mnstatus.NMIE` set to 0 is an unexpected trap.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 302, + 309 + ] + }, + { + "chunk_id": "chunk_b595cf2e", + "text": "In the event of a unexpected trap, the handling is as follows:", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 311, + 311 + ] + }, + { + "chunk_id": "chunk_6ba95d38", + "text": "When the Smrnmi extension is implemented and `mnstatus.NMIE` is 1, the hart traps to the RNMI handler.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 313, + 318 + ] + }, + { + "chunk_id": "chunk_184a4598", + "text": "To deliver this trap, the `mnepc` and `mncause` registers are written with the values that the unexpected trap would have written to the `mepc` and `mcause` registers respectively.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 313, + 318 + ] + }, + { + "chunk_id": "chunk_380d0cb2", + "text": "The privilege mode information fields in the `mnstatus` register are written to indicate M-mode and its `NMIE` field is set to 0.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 313, + 318 + ] + }, + { + "chunk_id": "chunk_b77fa1e6", + "text": "When the Smrnmi extension is not implemented, or if the Smrnmi extension is implemented and `mnstatus.NMIE` is 0, the hart enters a critical-error state without updating any architectural state, including the `pc`.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 320, + 325 + ] + }, + { + "chunk_id": "chunk_e460edb6", + "text": "This state involves ceasing execution, disabling all interrupts (including NMIs), and asserting a `critical-error` signal to the platform.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 320, + 325 + ] + }, + { + "chunk_id": "chunk_e0437150", + "text": "Whether performance counters and timers are updated in the critical-error state is UNSPECIFIED.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 320, + 325 + ] + }, + { + "chunk_id": "chunk_0247cb47", + "text": "When the Smdbltrp extension is implemented, executing an `MRET` instruction, or executing an `SRET` instruction while the current privilege mode is M, has the following additional effects.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 327, + 332 + ] + }, + { + "chunk_id": "chunk_8696b437", + "text": "The `MDT` bit is set to 0.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 327, + 332 + ] + }, + { + "chunk_id": "chunk_bf6ee958", + "text": "If the Ssdbltrp extension is also implemented, and the new privilege mode is U, VS, or VU, then `sstatus.SDT` is also set to 0.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 327, + 332 + ] + }, + { + "chunk_id": "chunk_d57a0235", + "text": "Additionally, if it is VU, then `vsstatus.SDT` is also set to 0.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 327, + 332 + ] + }, + { + "chunk_id": "chunk_b09dc8dd", + "text": "When the Smdbltrp extension is implemented, the `MNRET` instruction, provided by the Smrnmi extension, sets the `MDT` bit to 0 if the new privilege mode is not M.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 334, + 336 + ] + }, + { + "chunk_id": "chunk_8d52acae", + "text": "If the Ssdbltrp extension is also implemented, and the new privilege mode is U, VS, or VU, then `sstatus.SDT` is also set to 0.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 334, + 336 + ] + }, + { + "chunk_id": "chunk_47c7f685", + "text": "Additionally, if it is VU, then `vsstatus.SDT` is also set to 0.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 334, + 336 + ] + }, + { + "chunk_id": "chunk_a1b012e3", + "text": "For RV64 harts, the SXL and UXL fields are *WARL* fields that control the value of XLEN for S-mode and U-mode, respectively.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Base ISA Control in `mstatus` Register", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 341, + 344 + ] + }, + { + "chunk_id": "chunk_3a138f63", + "text": "The encoding of these fields is the same as the MXL field of `misa`, shown in .", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Base ISA Control in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 341, + 344 + ] + }, + { + "chunk_id": "chunk_ff6c63e4", + "text": "The effective XLEN in S-mode and U-mode are termed SXLEN and UXLEN, respectively.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Base ISA Control in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 341, + 344 + ] + }, + { + "chunk_id": "chunk_946ccc8c", + "text": "When MXLEN=32, the SXL and UXL fields do not exist, and SXLEN=32 and UXLEN=32.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Base ISA Control in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 346, + 347 + ] + }, + { + "chunk_id": "chunk_eafe42d2", + "text": "When MXLEN=64, if S-mode is not supported, then SXL is read-only zero.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Base ISA Control in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 349, + 352 + ] + }, + { + "chunk_id": "chunk_baf0fbc7", + "text": "Otherwise, it is a *WARL* field that encodes the current value of SXLEN.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Base ISA Control in `mstatus` Register", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 349, + 352 + ] + }, + { + "chunk_id": "chunk_9e5e553b", + "text": "In particular, an implementation may make SXL be a read-only field whose value always ensures that SXLEN=MXLEN.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Base ISA Control in `mstatus` Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 349, + 352 + ] + }, + { + "chunk_id": "chunk_aec67cce", + "text": "When MXLEN=64, if U-mode is not supported, then UXL is read-only zero.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Base ISA Control in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 354, + 357 + ] + }, + { + "chunk_id": "chunk_3685ed6f", + "text": "Otherwise, it is a *WARL* field that encodes the current value of UXLEN.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Base ISA Control in `mstatus` Register", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 354, + 357 + ] + }, + { + "chunk_id": "chunk_2cf32d37", + "text": "In particular, an implementation may make UXL be a read-only field whose value always ensures that UXLEN=MXLEN or UXLEN=SXLEN.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Base ISA Control in `mstatus` Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 354, + 357 + ] + }, + { + "chunk_id": "chunk_e129cc9c", + "text": "If S-mode is implemented, the set of legal values that the UXL field may assume excludes those that would cause UXLEN to be greater than SXLEN.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Base ISA Control in `mstatus` Register", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 359, + 361 + ] + }, + { + "chunk_id": "chunk_4d4a9656", + "text": "Whenever XLEN in any mode is set to a value less than the widest supported XLEN, all operations must ignore source operand register bits above the configured XLEN, and must sign-extend results to fill the entire widest supported XLEN in the destination register.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Base ISA Control in `mstatus` Register", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 363, + 369 + ] + }, + { + "chunk_id": "chunk_c78bec76", + "text": "Similarly, `pc` bits above XLEN are ignored, and when the `pc` is written, it is sign-extended to fill the widest supported XLEN.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Base ISA Control in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 363, + 369 + ] + }, + { + "chunk_id": "chunk_e2d7e143", + "text": "When such a HINT is executed with XLEN < MXLEN and bits MXLEN..XLEN of the destination register not all equal to bit XLEN-1, it is implementation-defined whether bits MXLEN..XLEN of the destination register are unchanged or are overwritten with copies of bit XLEN-1.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Base ISA Control in `mstatus` Register", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 371, + 378 + ] + }, + { + "chunk_id": "chunk_48ebcb18", + "text": "The implementation choice is observable only by privilege modes with an XLEN setting greater than the current XLEN; it is invisible to the current privilege mode.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Base ISA Control in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "range", + "line_range": [ + 380, + 386 + ] + }, + { + "chunk_id": "chunk_6d2d35a6", + "text": "When MPRV=0, explicit memory accesses behave as normal, using the translation and protection mechanisms of the current privilege mode.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Memory Privilege in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 390, + 399 + ] + }, + { + "chunk_id": "chunk_62353e79", + "text": "When MPRV=1, load and store memory addresses are translated and protected, and endianness is applied, as though the current privilege mode were set to MPP.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Memory Privilege in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 390, + 399 + ] + }, + { + "chunk_id": "chunk_9d60b6e8", + "text": "Instruction address-translation and protection are unaffected by the setting of MPRV. MPRV is read-only 0 if U-mode is not supported.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Memory Privilege in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 390, + 399 + ] + }, + { + "chunk_id": "chunk_cfc2ea64", + "text": "An MRET or SRET instruction that changes the privilege mode to a mode less privileged than M also sets MPRV=0.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Memory Privilege in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 401, + 402 + ] + }, + { + "chunk_id": "chunk_34d3623c", + "text": "The MXR (Make eXecutable Readable) bit modifies the privilege with which loads access virtual memory.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Memory Privilege in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 404, + 408 + ] + }, + { + "chunk_id": "chunk_71fc36af", + "text": "When MXR=0, only loads from pages marked readable (R=1 in ) will succeed.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Memory Privilege in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 404, + 408 + ] + }, + { + "chunk_id": "chunk_fb6571cf", + "text": "When MXR=1, loads from pages marked either readable or executable (R=1 or X=1) will succeed. MXR has no effect when page-based virtual memory is not in effect. MXR is read-only 0 if S-mode is not supported.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Memory Privilege in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 404, + 408 + ] + }, + { + "chunk_id": "chunk_f63b2089", + "text": "The SUM (permit Supervisor User Memory access) bit modifies the privilege with which S-mode loads and stores access virtual memory.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Memory Privilege in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 410, + 417 + ] + }, + { + "chunk_id": "chunk_9065dcbb", + "text": "When SUM=0, S-mode memory accesses to pages that are accessible by U-mode (U=1 in ) will fault.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Memory Privilege in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 410, + 417 + ] + }, + { + "chunk_id": "chunk_72e75926", + "text": "When SUM=1, these accesses are permitted. SUM has no effect when page-based virtual memory is not in effect.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Memory Privilege in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 410, + 417 + ] + }, + { + "chunk_id": "chunk_7d4c7b1c", + "text": "The MXR and SUM mechanisms only affect the interpretation of permissions encoded in page-table entries.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Memory Privilege in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 419, + 422 + ] + }, + { + "chunk_id": "chunk_f93d3c8d", + "text": "In particular, they have no impact on whether access-fault exceptions are raised due to PMAs or PMP.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Memory Privilege in `mstatus` Register", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 419, + 422 + ] + }, + { + "chunk_id": "chunk_e2d37e88", + "text": "The MBE, SBE, and UBE bits in `mstatus` and `mstatush` are *WARL* fields that control the endianness of memory accesses other than instruction fetches.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Endianness Control in `mstatus` and `mstatush` Registers", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 426, + 428 + ] + }, + { + "chunk_id": "chunk_6ead09ae", + "text": "Instruction fetches are always little-endian.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Endianness Control in `mstatus` and `mstatush` Registers", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 426, + 428 + ] + }, + { + "chunk_id": "chunk_14c469a4", + "text": "MBE controls whether non-instruction-fetch memory accesses made from M-mode (assuming `mstatus`.MPRV=0) are little-endian (MBE=0) or big-endian (MBE=1).", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Endianness Control in `mstatus` and `mstatush` Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 430, + 433 + ] + }, + { + "chunk_id": "chunk_d40c9bce", + "text": "If S-mode is not supported, SBE is read-only 0.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Endianness Control in `mstatus` and `mstatush` Registers", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 435, + 438 + ] + }, + { + "chunk_id": "chunk_1544547e", + "text": "Otherwise, SBE controls whether explicit load and store memory accesses made from S-mode are little-endian (SBE=0) or big-endian (SBE=1).", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Endianness Control in `mstatus` and `mstatush` Registers", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 435, + 438 + ] + }, + { + "chunk_id": "chunk_abc95956", + "text": "If U-mode is not supported, UBE is read-only 0.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Endianness Control in `mstatus` and `mstatush` Registers", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 440, + 443 + ] + }, + { + "chunk_id": "chunk_f7bd115a", + "text": "Otherwise, UBE controls whether explicit load and store memory accesses made from U-mode are little-endian (UBE=0) or big-endian (UBE=1).", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Endianness Control in `mstatus` and `mstatush` Registers", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 440, + 443 + ] + }, + { + "chunk_id": "chunk_c3daa802", + "text": "For implicit accesses to supervisor-level memory management data structures, such as page tables, endianness is always controlled by SBE.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Endianness Control in `mstatus` and `mstatush` Registers", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 445, + 450 + ] + }, + { + "chunk_id": "chunk_78a11b95", + "text": "Since changing SBE alters the implementation\u2019s interpretation of these data structures, if any such data structures remain in use across a change to SBE, M-mode software must follow such a change to SBE by executing an SFENCE.VMA instruction with rs1=`x0` and rs2=`x0`.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Endianness Control in `mstatus` and `mstatush` Registers", + "confidence": "very_high", + "parameter_class": "SW_rule", + "parameter_type": "binary", + "line_range": [ + 445, + 450 + ] + }, + { + "chunk_id": "chunk_9106cc6f", + "text": "If S-mode is supported, an implementation may make SBE be a read-only copy of MBE.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Endianness Control in `mstatus` and `mstatush` Registers", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 452, + 455 + ] + }, + { + "chunk_id": "chunk_ffd4982b", + "text": "If U-mode is supported, an implementation may make UBE be a read-only copy of either MBE or SBE.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Endianness Control in `mstatus` and `mstatush` Registers", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 452, + 455 + ] + }, + { + "chunk_id": "chunk_47aebbd0", + "text": "The TVM (Trap Virtual Memory) bit is a *WARL* field that supports intercepting supervisor virtual-memory management operations.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Virtualization Support in `mstatus` Register", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 460, + 466 + ] + }, + { + "chunk_id": "chunk_c5327415", + "text": "When TVM=1, attempts to read or write the `satp` CSR or execute an SFENCE.VMA or SINVAL.VMA instruction while executing in S-mode will raise an illegal-instruction exception.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Virtualization Support in `mstatus` Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 460, + 466 + ] + }, + { + "chunk_id": "chunk_9dee9a7c", + "text": "When TVM=0, these operations are permitted in S-mode. TVM is read-only 0 when S-mode is not supported.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Virtualization Support in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 460, + 466 + ] + }, + { + "chunk_id": "chunk_50316df6", + "text": "When TW=0, the WFI instruction may execute in modes less privileged than M when not prevented for some other reason.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Virtualization Support in `mstatus` Register", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 468, + 480 + ] + }, + { + "chunk_id": "chunk_fc1a5149", + "text": "When TW=1, then if WFI is executed in any less-privileged mode, and it does not complete within an implementation-specific, bounded time limit, the WFI instruction causes an illegal-instruction exception.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Virtualization Support in `mstatus` Register", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 468, + 480 + ] + }, + { + "chunk_id": "chunk_cad1ac2e", + "text": "An implementation may have WFI always raise an illegal-instruction exception in modes less privileged than M when TW=1, even if there are pending globally-disabled interrupts when the instruction is executed. TW is read-only 0 when there are no modes less privileged than M.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Virtualization Support in `mstatus` Register", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 468, + 480 + ] + }, + { + "chunk_id": "chunk_351767e6", + "text": "When S-mode is implemented, then executing WFI in U-mode causes an illegal-instruction exception, regardless of the value of the TW bit, unless the instruction completes within an implementation-specific, bounded time limit.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Virtualization Support in `mstatus` Register", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 482, + 484 + ] + }, + { + "chunk_id": "chunk_61926087", + "text": "The TSR (Trap SRET) bit is a *WARL* field that supports intercepting the supervisor exception return instruction, SRET.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Virtualization Support in `mstatus` Register", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 486, + 491 + ] + }, + { + "chunk_id": "chunk_fc7dcdf1", + "text": "When TSR=1, attempts to execute SRET while executing in S-mode will raise an illegal-instruction exception.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Virtualization Support in `mstatus` Register", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 486, + 491 + ] + }, + { + "chunk_id": "chunk_10ffba0c", + "text": "When TSR=0, this operation is permitted in S-mode. TSR is read-only 0 when S-mode is not supported.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Virtualization Support in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 486, + 491 + ] + }, + { + "chunk_id": "chunk_100bf3d9", + "text": "Supporting substantial extensions is one of the primary goals of RISC-V, and hence we define a standard interface to allow unchanged privileged-mode code, particularly a supervisor-level OS, to support arbitrary user-mode state extensions.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 495, + 498 + ] + }, + { + "chunk_id": "chunk_a17aa295", + "text": "The FS[1:0] and VS[1:0] *WARL* fields and the XS[1:0] read-only field are used to reduce the cost of context save and restore by setting and tracking the current state of the floating-point unit and any other user-mode extensions respectively.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 500, + 517 + ] + }, + { + "chunk_id": "chunk_d23c4559", + "text": "The FS field encodes the status of the floating-point unit state, including the floating-point registers `f0`\u2013`f31` and the CSRs `fcsr`, `frm`, and `fflags`.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 500, + 517 + ] + }, + { + "chunk_id": "chunk_cfa4f4cd", + "text": "The VS field encodes the status of the vector extension state, including the vector registers `v0`\u2013`v31` and the CSRs `vcsr`, `vxrm`, `vxsat`, `vstart`, `vl`, `vtype`, and `vlenb`.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 500, + 517 + ] + }, + { + "chunk_id": "chunk_989c0a49", + "text": "The XS field encodes the status of additional user-mode extensions and associated state.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 500, + 517 + ] + }, + { + "chunk_id": "chunk_d6c57a2e", + "text": "These fields can be checked by a context switch routine to quickly determine whether a state save or restore is required.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 500, + 517 + ] + }, + { + "chunk_id": "chunk_2a6076a9", + "text": "The FS, VS, and XS fields use the same status encoding as shown in , with the four possible status values being Off, Initial, Clean, and Dirty.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 519, + 521 + ] + }, + { + "chunk_id": "chunk_0684048e", + "text": "If the F extension is implemented, the FS field shall not be read-only zero.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 542, + 543 + ] + }, + { + "chunk_id": "chunk_e1e1eb9f", + "text": "If neither the F extension nor S-mode is implemented, then FS is read-only zero.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 545, + 547 + ] + }, + { + "chunk_id": "chunk_72bdee1e", + "text": "If S-mode is implemented but the F extension is not, FS may optionally be read-only zero.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 545, + 547 + ] + }, + { + "chunk_id": "chunk_c66ba3f4", + "text": "If the `v` registers are implemented, the VS field shall not be read-only zero.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 549, + 550 + ] + }, + { + "chunk_id": "chunk_9af5df91", + "text": "If neither the `v` registers nor S-mode is implemented, then VS is read-only zero.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 552, + 555 + ] + }, + { + "chunk_id": "chunk_5060ccc5", + "text": "If S-mode is implemented but the `v` registers are not, VS may optionally be read-only zero.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 552, + 555 + ] + }, + { + "chunk_id": "chunk_719bff2a", + "text": "In harts without additional user extensions requiring new state, the XS field is read-only zero.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 557, + 562 + ] + }, + { + "chunk_id": "chunk_3dd742ab", + "text": "Every additional extension with state provides a CSR field that encodes the equivalent of the XS states.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 557, + 562 + ] + }, + { + "chunk_id": "chunk_d467dc7b", + "text": "The XS field represents a summary of all extensions' status as shown in .", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 557, + 562 + ] + }, + { + "chunk_id": "chunk_62d171a7", + "text": "The SD bit is a read-only bit that summarizes whether either the FS, VS, or XS fields signal the presence of some dirty state that will require saving extended user context to memory.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 564, + 568 + ] + }, + { + "chunk_id": "chunk_b0d2a550", + "text": "If FS, XS, and VS are all read-only zero, then SD is also always zero.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 564, + 568 + ] + }, + { + "chunk_id": "chunk_6f32dc69", + "text": "When an extension's status is set to Off, any instruction that attempts to read or write the corresponding state will cause an illegal-instruction exception.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 570, + 579 + ] + }, + { + "chunk_id": "chunk_c03874a5", + "text": "When the status is Initial, the corresponding state should have an initial constant value.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 570, + 579 + ] + }, + { + "chunk_id": "chunk_52848716", + "text": "When the status is Clean, the corresponding state is potentially different from the initial value, but matches the last value stored on a context swap.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 570, + 579 + ] + }, + { + "chunk_id": "chunk_b892e66b", + "text": "When the status is Dirty, the corresponding state has potentially been modified since the last context save.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 570, + 579 + ] + }, + { + "chunk_id": "chunk_a8626944", + "text": "During a context save, the responsible privileged code need only write out the corresponding state if its status is Dirty, and can then reset the extension's status to Clean.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 581, + 589 + ] + }, + { + "chunk_id": "chunk_d3cc2786", + "text": "During a context restore, the context need only be loaded from memory if the status is Clean (it should never be Dirty at restore).", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 581, + 589 + ] + }, + { + "chunk_id": "chunk_d140aeec", + "text": "If the status is Initial, the context must be set to an initial constant value on context restore to avoid a security hole, but this can be done without accessing memory.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 581, + 589 + ] + }, + { + "chunk_id": "chunk_0129e0ad", + "text": "The FS and XS fields are read by the privileged code before saving the context.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 591, + 596 + ] + }, + { + "chunk_id": "chunk_588da1df", + "text": "The FS field is set directly by privileged code when resuming a user context, while the XS field is set indirectly by writing to the status register of the individual extensions.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 591, + 596 + ] + }, + { + "chunk_id": "chunk_2f74b83c", + "text": "The status fields will also be updated during execution of instructions, regardless of privilege mode.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 591, + 596 + ] + }, + { + "chunk_id": "chunk_b0b87ad3", + "text": "Extensions to the user-mode ISA often include additional user-mode state, and this state can be considerably larger than the base integer registers.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 598, + 604 + ] + }, + { + "chunk_id": "chunk_436175c7", + "text": "The extensions might only be used for some applications, or might only be needed for short phases within a single application.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 598, + 604 + ] + }, + { + "chunk_id": "chunk_e56b6a0c", + "text": "To improve performance, the user-mode extension can define additional instructions to allow user-mode software to return the unit to an initial state or even to turn off the unit.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 598, + 604 + ] + }, + { + "chunk_id": "chunk_f3636b32", + "text": "The unconfigured state would be represented as the Initial state for context save.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 606, + 614 + ] + }, + { + "chunk_id": "chunk_b7653af0", + "text": "Executing a user-mode instruction to disable a unit and place it into the Off state will cause an illegal-instruction exception to be raised if any subsequent instruction tries to use the unit before it is turned back on. A user-mode instruction to turn a unit on must also ensure the unit's state is properly initialized, as the unit might have been used by another context meantime.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 616, + 621 + ] + }, + { + "chunk_id": "chunk_fa9dc3be", + "text": "Changing the setting of FS has no effect on the contents of the floating-point register state.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 623, + 628 + ] + }, + { + "chunk_id": "chunk_1d9af2f0", + "text": "In particular, setting FS=Off does not destroy the state, nor does setting FS=Initial clear the contents.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 623, + 628 + ] + }, + { + "chunk_id": "chunk_ffc61c8e", + "text": "Similarly, the setting of VS has no effect on the contents of the vector register state.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 623, + 628 + ] + }, + { + "chunk_id": "chunk_1b88bbce", + "text": "Other extensions, however, might not preserve state when set to Off.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 623, + 628 + ] + }, + { + "chunk_id": "chunk_8a97197e", + "text": "Implementations may choose to track the dirtiness of the floating-point register state imprecisely by reporting the state to be dirty even when it has not been modified.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 630, + 639 + ] + }, + { + "chunk_id": "chunk_6afc95af", + "text": "On some implementations, some instructions that do not mutate the floating-point state may cause the state to transition from Initial or Clean to Dirty.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 630, + 639 + ] + }, + { + "chunk_id": "chunk_d692b836", + "text": "On other implementations, dirtiness might not be tracked at all, in which case the valid FS states are Off and Dirty, and an attempt to set FS to Initial or Clean causes it to be set to Dirty.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 630, + 639 + ] + }, + { + "chunk_id": "chunk_966e351f", + "text": "If an instruction explicitly or implicitly writes a floating-point register or the `fcsr` but does not alter its contents, and FS=Initial or FS=Clean, it is implementation-defined whether FS transitions to Dirty.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 641, + 644 + ] + }, + { + "chunk_id": "chunk_4fee64ca", + "text": "Implementations may choose to track the dirtiness of the vector register state in an analogous imprecise fashion, including possibly setting VS to Dirty when software attempts to set VS=Initial or VS=Clean.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 646, + 651 + ] + }, + { + "chunk_id": "chunk_6177f235", + "text": "When VS=Initial or VS=Clean, it is implementation-defined whether an instruction that writes a vector register or vector CSR but does not alter its contents causes VS to transition to Dirty.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 646, + 651 + ] + }, + { + "chunk_id": "chunk_440c0271", + "text": "shows all the possible state transitions for the FS, VS, or XS status bits.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 653, + 656 + ] + }, + { + "chunk_id": "chunk_c937eee4", + "text": "[width=75,align=center,float=center,cols=\"<,<,<,<,<\"] | 5+^|At context save in privileged code", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 668, + 670 + ] + }, + { + "chunk_id": "chunk_dac566d1", + "text": "|Save state? + Next state |No + Off |No + Initial |No + Clean |Yes + Clean |", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 672, + 682 + ] + }, + { + "chunk_id": "chunk_5397685e", + "text": "[width=75,align=center,float=center,cols=\"<,<,<,<,<\"] | 5+^|At context restore in privileged code", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 684, + 686 + ] + }, + { + "chunk_id": "chunk_9f4e4282", + "text": "|Restore state? + Next state |No + Off |Yes, to initial + Initial |Yes, from memory + Clean |N/A + N/A |", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 688, + 698 + ] + }, + { + "chunk_id": "chunk_ec8ecfa4", + "text": "[width=75,align=center,float=center,cols=\"<,<,<,<,<\"] | 5+^|Execute instruction to read state", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 700, + 702 + ] + }, + { + "chunk_id": "chunk_917169fc", + "text": "|Action? + Next state |Exception + Off |Execute + Initial |Execute + Clean |Execute + Dirty |", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 704, + 714 + ] + }, + { + "chunk_id": "chunk_1ab2ddac", + "text": "[width=75,align=center,float=center,cols=\"<,<,<,<,<\"] | 5+^|Execute instruction that possibly modifies state, including configuration", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 716, + 718 + ] + }, + { + "chunk_id": "chunk_ad0876b7", + "text": "|Action? + Next state |Exception + Off |Execute + Dirty |Execute + Dirty |Execute + Dirty |", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 720, + 730 + ] + }, + { + "chunk_id": "chunk_bfb06166", + "text": "[width=75,align=center,float=center,cols=\"<,<,<,<,<\"] | 5+^|Execute instruction to unconfigure unit", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 732, + 734 + ] + }, + { + "chunk_id": "chunk_1cd88952", + "text": "|Action? + Next state |Exception + Off |Execute + Initial |Execute + Initial |Execute + Initial |", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 736, + 746 + ] + }, + { + "chunk_id": "chunk_3cafd6f1", + "text": "[width=75,align=center,float=center,cols=\"<,<,<,<,<\"] | 5+^|Execute instruction to disable unit", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 748, + 750 + ] + }, + { + "chunk_id": "chunk_289f8f4c", + "text": "|Action? + Next state |Execute + Off |Execute + Off |Execute + Off |Execute + Off |", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 752, + 762 + ] + }, + { + "chunk_id": "chunk_4172ff3d", + "text": "[width=75,align=center,float=center,cols=\"<,<,<,<,<\"] | 5+^|Execute instruction to enable unit", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 764, + 766 + ] + }, + { + "chunk_id": "chunk_e7d34a1b", + "text": "|Action? + Next state |Execute + Initial |Execute + Initial |Execute + Initial |Execute + Initial |", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 768, + 778 + ] + }, + { + "chunk_id": "chunk_e89be2e8", + "text": "Standard privileged instructions to initialize, save, and restore extension state are provided to insulate privileged code from details of the added extension state by treating the state as an opaque object.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 780, + 782 + ] + }, + { + "chunk_id": "chunk_8f7b962b", + "text": "The XS field provides a summary of all added extension state, but additional microarchitectural bits might be maintained in the extension to further reduce context save and restore overhead.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 784, + 786 + ] + }, + { + "chunk_id": "chunk_5beffcc5", + "text": "The floating-point unit state is always initialized, saved, and restored using standard instructions (F, D, and/or Q), and privileged code must be aware of FLEN to determine the appropriate space to reserve for each `f` register.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 793, + 796 + ] + }, + { + "chunk_id": "chunk_e7897050", + "text": "Machine and Supervisor modes share a single copy of the FS, VS, and XS bits.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 798, + 803 + ] + }, + { + "chunk_id": "chunk_a213a100", + "text": "Supervisor-level software normally uses the FS, VS, and XS bits directly to record the status with respect to the supervisor-level saved context.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 798, + 803 + ] + }, + { + "chunk_id": "chunk_e951506a", + "text": "Machine-level software must be more conservative in saving and restoring the extension state in their corresponding version of the context.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "confidence": "very_high", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 798, + 803 + ] + }, + { + "chunk_id": "chunk_73c2549a", + "text": "The Zicfilp extension adds the `SPELP` and `MPELP` fields that hold the previous `ELP`, and are updated as specified in .", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Previous Expected Landing Pad (ELP) State in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 807, + 809 + ] + }, + { + "chunk_id": "chunk_568f2c06", + "text": "The *x*`PELP` fields are encoded as follows:", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Previous Expected Landing Pad (ELP) State in `mstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 807, + 809 + ] + }, + { + "chunk_id": "chunk_ea60f834", + "text": "The `mtvec` register is an MXLEN-bit *WARL* read/write register that holds trap vector configuration, consisting of a vector base address (BASE) and a vector mode (MODE).", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap-Vector Base-Address (`mtvec`) Register", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 817, + 819 + ] + }, + { + "chunk_id": "chunk_f047c73f", + "text": "The `mtvec` register must always be implemented, but can contain a read-only value.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap-Vector Base-Address (`mtvec`) Register", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 825, + 835 + ] + }, + { + "chunk_id": "chunk_05da97e7", + "text": "If `mtvec` is writable, the set of values the register may hold can vary by implementation.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap-Vector Base-Address (`mtvec`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 825, + 835 + ] + }, + { + "chunk_id": "chunk_7f24c6fc", + "text": "The value in the BASE field must always be aligned on a 4-byte boundary, and the MODE setting may impose additional alignment constraints on the value in the BASE field.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap-Vector Base-Address (`mtvec`) Register", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 825, + 835 + ] + }, + { + "chunk_id": "chunk_b5c6215c", + "text": "When used as an address, the lower two bits are filled with zeroes to obtain an XLEN-bit address that is always aligned on a 4-byte boundary.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap-Vector Base-Address (`mtvec`) Register", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 825, + 835 + ] + }, + { + "chunk_id": "chunk_ee78fe45", + "text": "The encoding of the MODE field is shown in .", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap-Vector Base-Address (`mtvec`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 853, + 860 + ] + }, + { + "chunk_id": "chunk_f847aa6a", + "text": "When MODE=Direct, all traps into machine mode cause the `pc` to be set to the address in the BASE field.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap-Vector Base-Address (`mtvec`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 853, + 860 + ] + }, + { + "chunk_id": "chunk_043f6209", + "text": "When MODE=Vectored, all synchronous exceptions into machine mode cause the `pc` to be set to the address in the BASE field, whereas interrupts cause the `pc` to be set to the address in the BASE field plus four times the interrupt cause number.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap-Vector Base-Address (`mtvec`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 853, + 860 + ] + }, + { + "chunk_id": "chunk_0997ae61", + "text": "An implementation may have different alignment constraints for different modes.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap-Vector Base-Address (`mtvec`) Register", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 862, + 864 + ] + }, + { + "chunk_id": "chunk_5614962a", + "text": "In particular, MODE=Vectored may have stricter alignment constraints than MODE=Direct.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap-Vector Base-Address (`mtvec`) Register", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 862, + 864 + ] + }, + { + "chunk_id": "chunk_44f96bcf", + "text": "By default, all traps at any privilege level are handled in machine mode, though a machine-mode handler can redirect traps back to the appropriate level with the MRET instruction ().", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Delegation (`medeleg` and `mideleg`) Registers", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 868, + 876 + ] + }, + { + "chunk_id": "chunk_fdebccfe", + "text": "To increase performance, implementations can provide individual read/write bits within `medeleg` and `mideleg` to indicate that certain exceptions and interrupts should be processed directly by a lower privilege level.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Delegation (`medeleg` and `mideleg`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 868, + 876 + ] + }, + { + "chunk_id": "chunk_6b83fe4a", + "text": "The machine exception delegation register (`medeleg`) is a 64-bit read/write register.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Delegation (`medeleg` and `mideleg`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 868, + 876 + ] + }, + { + "chunk_id": "chunk_2a87bcf3", + "text": "The machine interrupt delegation (`mideleg`) register is an MXLEN-bit read/write register.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Delegation (`medeleg` and `mideleg`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 868, + 876 + ] + }, + { + "chunk_id": "chunk_18ad37ff", + "text": "In harts with S-mode, the `medeleg` and `mideleg` registers must exist, and setting a bit in `medeleg` or `mideleg` will delegate the corresponding trap, when occurring in S-mode or U-mode, to the S-mode trap handler.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Delegation (`medeleg` and `mideleg`) Registers", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 878, + 882 + ] + }, + { + "chunk_id": "chunk_5f254348", + "text": "In harts without S-mode, the `medeleg` and `mideleg` registers should not exist.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Delegation (`medeleg` and `mideleg`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 878, + 882 + ] + }, + { + "chunk_id": "chunk_6c8748bf", + "text": "When a trap is delegated to S-mode, the `scause` register is written with the trap cause; the `sepc` register is written with the virtual address of the instruction that took the trap; the `stval` register is written with an exception-specific datum; the SPP field of `mstatus` is written with the active privilege mode at the time of the trap; the SPIE field of `mstatus` is written with the value of the SIE field at the time of the trap; and the SIE field of `mstatus` is cleared.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Delegation (`medeleg` and `mideleg`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 884, + 893 + ] + }, + { + "chunk_id": "chunk_149fb50f", + "text": "The `mcause`, `mepc`, and `mtval` registers and the MPP and MPIE fields of `mstatus` are not written.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Delegation (`medeleg` and `mideleg`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 884, + 893 + ] + }, + { + "chunk_id": "chunk_20b10e8f", + "text": "An implementation can choose to subset the delegatable traps, with the supported delegatable bits found by writing one to every bit location, then reading back the value in `medeleg` or `mideleg` to see which bit positions hold a one.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Delegation (`medeleg` and `mideleg`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 895, + 898 + ] + }, + { + "chunk_id": "chunk_7a6ffcef", + "text": "An implementation shall not have any bits of `medeleg` be read-only one, i.e., any synchronous trap that can be delegated must support not being delegated.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Delegation (`medeleg` and `mideleg`) Registers", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 900, + 905 + ] + }, + { + "chunk_id": "chunk_022eb3c5", + "text": "Similarly, an implementation shall not fix as read-only one any bits of `mideleg` corresponding to machine-level interrupts (but may do so for lower-level interrupts).", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Delegation (`medeleg` and `mideleg`) Registers", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 900, + 905 + ] + }, + { + "chunk_id": "chunk_27edf377", + "text": "Traps never transition from a more-privileged mode to a less-privileged mode.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Delegation (`medeleg` and `mideleg`) Registers", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 907, + 914 + ] + }, + { + "chunk_id": "chunk_45e80975", + "text": "By contrast, traps may be taken horizontally.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Delegation (`medeleg` and `mideleg`) Registers", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 907, + 914 + ] + }, + { + "chunk_id": "chunk_debc397f", + "text": "Using the same example, if M-mode has delegated illegal-instruction exceptions to S-mode, and S-mode software later executes an illegal instruction, the trap is taken in S-mode.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Delegation (`medeleg` and `mideleg`) Registers", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 907, + 914 + ] + }, + { + "chunk_id": "chunk_bc1cf57d", + "text": "Delegated interrupts result in the interrupt being masked at the delegator privilege level.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Delegation (`medeleg` and `mideleg`) Registers", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 916, + 921 + ] + }, + { + "chunk_id": "chunk_13ce9b57", + "text": "By contrast, if `mideleg`[5] is clear, STIs can be taken in any mode and regardless of current mode will transfer control to M-mode.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Delegation (`medeleg` and `mideleg`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 916, + 921 + ] + }, + { + "chunk_id": "chunk_62276a87", + "text": "When XLEN=32, `medelegh` is a 32-bit read/write register that aliases bits 63:32 of `medeleg`.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Delegation (`medeleg` and `mideleg`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 933, + 935 + ] + }, + { + "chunk_id": "chunk_5fd8225e", + "text": "The `medelegh` register does not exist when XLEN=64.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Delegation (`medeleg` and `mideleg`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 933, + 935 + ] + }, + { + "chunk_id": "chunk_75711217", + "text": "For exceptions that cannot occur in less privileged modes, the corresponding `medeleg` bits should be read-only zero.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Delegation (`medeleg` and `mideleg`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 945, + 947 + ] + }, + { + "chunk_id": "chunk_0d125a7d", + "text": "In particular, `medeleg`[11] is read-only zero.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Delegation (`medeleg` and `mideleg`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 945, + 947 + ] + }, + { + "chunk_id": "chunk_cde33edf", + "text": "The `medeleg`[16] is read-only zero as double trap is not delegatable.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Delegation (`medeleg` and `mideleg`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 949, + 949 + ] + }, + { + "chunk_id": "chunk_afc7a9e4", + "text": "The `mip` register is an MXLEN-bit read/write register containing information on pending interrupts, while `mie` is the corresponding MXLEN-bit read/write register containing interrupt enable bits.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 953, + 959 + ] + }, + { + "chunk_id": "chunk_8f4d107b", + "text": "Interrupt cause number i (as reported in CSR `mcause`, ) corresponds with bit i in both `mip` and `mie`.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 953, + 959 + ] + }, + { + "chunk_id": "chunk_ad33922a", + "text": "Bits 15:0 are allocated to standard interrupt causes only, while bits 16 and above are designated for platform use.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 953, + 959 + ] + }, + { + "chunk_id": "chunk_aabb9955", + "text": "An interrupt i will trap to M-mode (causing the privilege mode to change to M-mode) if all of the following are true: (a) either the current privilege mode is M and the MIE bit in the `mstatus` register is set, or the current privilege mode has less privilege than M-mode; (b) bit i is set in both `mip` and `mie`; and (c) if register `mideleg` exists, bit i is not set in `mideleg`.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 972, + 977 + ] + }, + { + "chunk_id": "chunk_c2e1138f", + "text": "These conditions for an interrupt trap to occur must be evaluated in a bounded amount of time from when an interrupt becomes, or ceases to be, pending in `mip`, and must also be evaluated immediately following the execution of an xRET instruction or an explicit write to a CSR on which these interrupt trap conditions expressly depend (including `mip`, `mie`, `mstatus`, and `mideleg`).", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 979, + 984 + ] + }, + { + "chunk_id": "chunk_bb4ee897", + "text": "Interrupts to M-mode take priority over any interrupts to lower privilege modes.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 986, + 987 + ] + }, + { + "chunk_id": "chunk_73a69f90", + "text": "Each individual bit in register `mip` may be writable or may be read-only.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 989, + 993 + ] + }, + { + "chunk_id": "chunk_99271441", + "text": "When bit i in `mip` is writable, a pending interrupt i can be cleared by writing 0 to this bit.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 989, + 993 + ] + }, + { + "chunk_id": "chunk_bf4e1876", + "text": "If interrupt i can become pending but bit i in `mip` is read-only, the implementation must provide some other mechanism for clearing the pending interrupt.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 989, + 993 + ] + }, + { + "chunk_id": "chunk_4645bc7f", + "text": "A bit in `mie` must be writable if the corresponding interrupt can ever become pending.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 995, + 996 + ] + }, + { + "chunk_id": "chunk_a317f98e", + "text": "Bits of `mie` that are not writable must be read-only zero.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 995, + 996 + ] + }, + { + "chunk_id": "chunk_665e5c10", + "text": "The standard portions (bits 15:0) of the `mip` and `mie` registers are formatted as shown in and respectively.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 998, + 999 + ] + }, + { + "chunk_id": "chunk_b9a51f08", + "text": "Bits `mip`.MEIP and `mie`.MEIE are the interrupt-pending and interrupt-enable bits for machine-level external interrupts. MEIP is read-only in `mip`, and is set and cleared by a platform-specific interrupt controller.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1009, + 1012 + ] + }, + { + "chunk_id": "chunk_5c0af0c2", + "text": "Bits `mip`.MTIP and `mie`.MTIE are the interrupt-pending and interrupt-enable bits for machine timer interrupts. MTIP is read-only in the `mip` register, and is cleared by writing to the memory-mapped machine-mode timer compare register.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1014, + 1017 + ] + }, + { + "chunk_id": "chunk_7d31576a", + "text": "Bits `mip`.MSIP and `mie`.MSIE are the interrupt-pending and interrupt-enable bits for machine-level software interrupts. MSIP is read-only in `mip`, and is written by accesses to memory-mapped control registers, which are used to provide machine-level interprocessor interrupts.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1019, + 1022 + ] + }, + { + "chunk_id": "chunk_acaae705", + "text": "A hart's memory-mapped `msip` register is a 32-bit read/write register, where bits 31--1 read as zero and bit 0 contains the MSIP bit.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 1024, + 1031 + ] + }, + { + "chunk_id": "chunk_2720da7b", + "text": "When the memory-mapped `msip` register changes, it is guaranteed to be reflected in `mip`.MSIP eventually, but not necessarily immediately.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1024, + 1031 + ] + }, + { + "chunk_id": "chunk_052e4f52", + "text": "If a system has only one hart, or if a platform standard supports the delivery of machine-level interprocessor interrupts through external interrupts (MEI) instead, then `mip`.MSIP and `mie`.MSIE may both be read-only zeros.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 1024, + 1031 + ] + }, + { + "chunk_id": "chunk_02c683bf", + "text": "If supervisor mode is not implemented, bits SEIP, STIP, and SSIP of `mip` and SEIE, STIE, and SSIE of `mie` are read-only zeros.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 1033, + 1034 + ] + }, + { + "chunk_id": "chunk_de20dc96", + "text": "If supervisor mode is implemented, bits `mip`.SEIP and `mie`.SEIE are the interrupt-pending and interrupt-enable bits for supervisor-level external interrupts. SEIP is writable in `mip`, and may be written by M-mode software to indicate to S-mode that an external interrupt is pending.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1036, + 1049 + ] + }, + { + "chunk_id": "chunk_9f2de32d", + "text": "Additionally, the platform-level interrupt controller may generate supervisor-level external interrupts.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1036, + 1049 + ] + }, + { + "chunk_id": "chunk_df8119c0", + "text": "Supervisor-level external interrupts are made pending based on the logical-OR of the software-writable SEIP bit and the signal from the external interrupt controller.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "unknown", + "line_range": [ + 1036, + 1049 + ] + }, + { + "chunk_id": "chunk_34847606", + "text": "When `mip` is read with a CSR instruction, the value of the SEIP bit returned in the `rd` destination register is the logical-OR of the software-writable bit and the interrupt signal from the interrupt controller, but the signal from the interrupt controller is not used to calculate the value written to SEIP.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1036, + 1049 + ] + }, + { + "chunk_id": "chunk_f816d1c7", + "text": "Only the software-writable SEIP bit participates in the read-modify-write sequence of a CSRRS or CSRRC instruction.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1036, + 1049 + ] + }, + { + "chunk_id": "chunk_175de799", + "text": "If supervisor mode is implemented, its `mip`.STIP and `mie`.STIE are the interrupt-pending and interrupt-enable bits for supervisor-level timer interrupts.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1051, + 1058 + ] + }, + { + "chunk_id": "chunk_c6528dd5", + "text": "If the stimecmp register is not implemented, STIP is writable in mip, and may be written by M-mode software to deliver timer interrupts to S-mode.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1051, + 1058 + ] + }, + { + "chunk_id": "chunk_bcf865e1", + "text": "If the `stimecmp` (supervisor-mode timer compare) register is implemented, STIP is read-only in mip and reflects the supervisor-level timer interrupt signal resulting from stimecmp.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1051, + 1058 + ] + }, + { + "chunk_id": "chunk_7e415153", + "text": "This timer interrupt signal is cleared by writing `stimecmp` with a value greater than the current time value.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "range", + "line_range": [ + 1051, + 1058 + ] + }, + { + "chunk_id": "chunk_48370bce", + "text": "If supervisor mode is implemented, bits `mip`.SSIP and `mie`.SSIE are the interrupt-pending and interrupt-enable bits for supervisor-level software interrupts. SSIP is writable in `mip` and may also be set to 1 by a platform-specific interrupt controller.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 1060, + 1063 + ] + }, + { + "chunk_id": "chunk_2fcb736a", + "text": "If the Sscofpmf extension is implemented, bits `mip`.LCOFIP and `mie`.LCOFIE are the interrupt-pending and interrupt-enable bits for local-counter-overflow interrupts. LCOFIP is read-write in `mip` and reflects the occurrence of a local counter-overflow overflow interrupt request resulting from any of the `mhpmeventn`.OF bits being set.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1065, + 1070 + ] + }, + { + "chunk_id": "chunk_c89ff2b9", + "text": "If the Sscofpmf extension is not implemented, `mip`.LCOFIP and `mie`.LCOFIE are read-only zeros.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 1065, + 1070 + ] + }, + { + "chunk_id": "chunk_4f54e58a", + "text": "Multiple simultaneous interrupts destined for M-mode are handled in the following decreasing priority order: MEI, MSI, MTI, SEI, SSI, STI, LCOFI.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1072, + 1073 + ] + }, + { + "chunk_id": "chunk_02680a48", + "text": "Restricted views of the `mip` and `mie` registers appear as the `sip` and `sie` registers for supervisor level.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1075, + 1079 + ] + }, + { + "chunk_id": "chunk_b19698c6", + "text": "If an interrupt is delegated to S-mode by setting a bit in the `mideleg` register, it becomes visible in the `sip` register and is maskable using the `sie` register.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1075, + 1079 + ] + }, + { + "chunk_id": "chunk_d6768a36", + "text": "Otherwise, the corresponding bits in `sip` and `sie` are read-only zero.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 1075, + 1079 + ] + }, + { + "chunk_id": "chunk_bf331c5a", + "text": "M-mode includes a basic hardware performance-monitoring facility.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Hardware Performance Monitor", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1083, + 1087 + ] + }, + { + "chunk_id": "chunk_28843ab6", + "text": "The `mcycle` CSR counts the number of clock cycles executed by the processor core on which the hart is running.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Hardware Performance Monitor", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1083, + 1087 + ] + }, + { + "chunk_id": "chunk_fa498d97", + "text": "The `minstret` CSR counts the number of instructions the hart has retired.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Hardware Performance Monitor", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1083, + 1087 + ] + }, + { + "chunk_id": "chunk_def4c87f", + "text": "The `mcycle` and `minstret` registers have 64-bit precision on all RV32 and RV64 harts.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Hardware Performance Monitor", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 1083, + 1087 + ] + }, + { + "chunk_id": "chunk_89beb2c1", + "text": "The counter registers have an arbitrary value after the hart is reset, and can be written with a given value.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Hardware Performance Monitor", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1089, + 1095 + ] + }, + { + "chunk_id": "chunk_31e379cc", + "text": "Any CSR write takes effect after the writing instruction has otherwise completed.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Hardware Performance Monitor", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1089, + 1095 + ] + }, + { + "chunk_id": "chunk_a1d94f46", + "text": "The `mcycle` CSR may be shared between harts on the same core, in which case writes to `mcycle` will be visible to those harts.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Hardware Performance Monitor", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1089, + 1095 + ] + }, + { + "chunk_id": "chunk_d642867e", + "text": "The platform should provide a mechanism to indicate which harts share an `mcycle` CSR.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Hardware Performance Monitor", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1089, + 1095 + ] + }, + { + "chunk_id": "chunk_25bfdec6", + "text": "The hardware performance monitor includes 29 additional 64-bit event counters, `mhpmcounter3`-`mhpmcounter31`.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Hardware Performance Monitor", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 1097, + 1105 + ] + }, + { + "chunk_id": "chunk_cbc5e064", + "text": "The event selector CSRs, `mhpmevent3`-`mhpmevent31`, are 64-bit *WARL* registers that control which event causes the corresponding counter to increment.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Hardware Performance Monitor", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 1097, + 1105 + ] + }, + { + "chunk_id": "chunk_a0d4e58a", + "text": "The meaning of these events is defined by the platform, but event 0 is defined to mean \"no event.\" All counters should be implemented, but a legal implementation is to make both the counter and its corresponding event selector be read-only 0.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Hardware Performance Monitor", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1097, + 1105 + ] + }, + { + "chunk_id": "chunk_c3b9c545", + "text": "The `mhpmcounters` are *WARL* registers that support up to 64 bits of precision on RV32 and RV64.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Hardware Performance Monitor", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 1110, + 1111 + ] + }, + { + "chunk_id": "chunk_10faa860", + "text": "When XLEN=32, reads of the `mcycle`, `minstret`, `mhpmcountern`, and `mhpmeventn` CSRs return bitj 31-0 of the corresponding register, and writes change only bits 31-0; reads of the `mcycleh`, `minstreth`, `mhpmcounternh`, and `mhpmeventnh` CSRs return bits 63-32 of the corresponding register, and writes change only bits 63-32.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Hardware Performance Monitor", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1113, + 1117 + ] + }, + { + "chunk_id": "chunk_6574111b", + "text": "The `mhpmeventnh` CSRs are provided only if the Sscofpmf extension is implemented.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Hardware Performance Monitor", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1113, + 1117 + ] + }, + { + "chunk_id": "chunk_1f0ee636", + "text": "The counter-enable `mcounteren` register is a 32-bit register that controls the availability of the hardware performance-monitoring counters to the next-lower privileged mode.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Counter-Enable (`mcounteren`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 1122, + 1124 + ] + }, + { + "chunk_id": "chunk_336159c2", + "text": "The settings in this register only control accessibility.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Counter-Enable (`mcounteren`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1130, + 1132 + ] + }, + { + "chunk_id": "chunk_bd565d3e", + "text": "The act of reading or writing this register does not affect the underlying counters, which continue to increment even when not accessible.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Counter-Enable (`mcounteren`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1130, + 1132 + ] + }, + { + "chunk_id": "chunk_448ffd84", + "text": "When the CY, TM, IR, or HPMn bit in the `mcounteren` register is clear, attempts to read the `cycle`, `time`, `instret`, or `hpmcountern` register while executing in S-mode or U-mode will cause an illegal-instruction exception.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Counter-Enable (`mcounteren`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1134, + 1140 + ] + }, + { + "chunk_id": "chunk_a76bcb84", + "text": "When one of these bits is set, access to the corresponding register is permitted in the next implemented privilege mode (S-mode if implemented, otherwise U-mode).", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Counter-Enable (`mcounteren`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 1134, + 1140 + ] + }, + { + "chunk_id": "chunk_f737b3c9", + "text": "In addition, when the TM bit in the `mcounteren` register is clear, attempts to access the `stimecmp` or `vstimecmp` register while executing in a mode less privileged than M will cause an illegal-instruction exception.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Counter-Enable (`mcounteren`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1142, + 1148 + ] + }, + { + "chunk_id": "chunk_0d64f639", + "text": "When this bit is set, access to the `stimecmp` or `vstimecmp` register is permitted in S-mode if implemented, and access to the `vstimecmp` register (via `stimecmp`) is permitted in VS-mode if implemented and not otherwise prevented by the TM bit in `hcounteren`.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Counter-Enable (`mcounteren`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1142, + 1148 + ] + }, + { + "chunk_id": "chunk_02d4a97d", + "text": "The `cycle`, `instret`, and `hpmcountern` CSRs are read-only shadows of `mcycle`, `minstret`, and `mhpmcounter n`, respectively.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Counter-Enable (`mcounteren`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1150, + 1156 + ] + }, + { + "chunk_id": "chunk_279fed9a", + "text": "The `time` CSR is a read-only shadow of the memory-mapped `mtime` register.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Counter-Enable (`mcounteren`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1150, + 1156 + ] + }, + { + "chunk_id": "chunk_748e7efb", + "text": "Analogously, when XLEN=32, the `cycleh`, `instreth` and `hpmcounternh` CSRs are read-only shadows of `mcycleh`, `minstreth` and `mhpmcounternh`, respectively.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Counter-Enable (`mcounteren`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1150, + 1156 + ] + }, + { + "chunk_id": "chunk_9d412348", + "text": "When XLEN=32, the `timeh` CSR is a read-only shadow of the upper 32 bits of the memory-mapped `mtime` register, while `time` shadows only the lower 32 bits of `mtime`.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Counter-Enable (`mcounteren`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 1150, + 1156 + ] + }, + { + "chunk_id": "chunk_d70331a3", + "text": "In harts with U-mode, the `mcounteren` must be implemented, but all fields are *WARL* and may be read-only zero, indicating reads to the corresponding counter will cause an illegal-instruction exception when executing in a less-privileged mode.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Counter-Enable (`mcounteren`) Register", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 1158, + 1163 + ] + }, + { + "chunk_id": "chunk_ad7adaf0", + "text": "In harts without U-mode, the `mcounteren` register should not exist.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Counter-Enable (`mcounteren`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1158, + 1163 + ] + }, + { + "chunk_id": "chunk_46e15e4b", + "text": "The counter-inhibit register `mcountinhibit` is a 32-bit *WARL* register that controls which of the hardware performance-monitoring counters increment.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Counter-Inhibit (`mcountinhibit`) Register", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 1171, + 1175 + ] + }, + { + "chunk_id": "chunk_6ec94bf3", + "text": "The settings in this register only control whether the counters increment; their accessibility is not affected by the setting of this register.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Counter-Inhibit (`mcountinhibit`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1171, + 1175 + ] + }, + { + "chunk_id": "chunk_645c1ceb", + "text": "When the CY, IR, or HPMn bit in the `mcountinhibit` register is clear, the `mcycle`, `minstret`, or `mhpmcountern` register increments as usual.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Counter-Inhibit (`mcountinhibit`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1177, + 1180 + ] + }, + { + "chunk_id": "chunk_5dbe48e8", + "text": "When the CY, IR, or HPMn bit is set, the corresponding counter does not increment.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Counter-Inhibit (`mcountinhibit`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1177, + 1180 + ] + }, + { + "chunk_id": "chunk_93ff94a8", + "text": "The `mcycle` CSR may be shared between harts on the same core, in which case the `mcountinhibit.CY` field is also shared between those harts, and so writes to `mcountinhibit.CY` will be visible to those harts.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Counter-Inhibit (`mcountinhibit`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1182, + 1184 + ] + }, + { + "chunk_id": "chunk_4a5ca476", + "text": "If the `mcountinhibit` register is not implemented, the implementation behaves as though the register were set to zero.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Counter-Inhibit (`mcountinhibit`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 1186, + 1187 + ] + }, + { + "chunk_id": "chunk_0f23ff77", + "text": "The `mscratch` register is an MXLEN-bit read/write register dedicated for use by machine mode.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Scratch (`mscratch`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 1191, + 1194 + ] + }, + { + "chunk_id": "chunk_33769378", + "text": "`mepc` is an MXLEN-bit read/write register formatted as shown in .", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Exception Program Counter (`mepc`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 1202, + 1203 + ] + }, + { + "chunk_id": "chunk_894c0c7e", + "text": "The low bit of `mepc` (`mepc[0]`) is always zero.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Exception Program Counter (`mepc`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1202, + 1203 + ] + }, + { + "chunk_id": "chunk_c78bea8c", + "text": "This masking occurs also for the implicit read by the MRET instruction.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Exception Program Counter (`mepc`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1205, + 1209 + ] + }, + { + "chunk_id": "chunk_400d5857", + "text": "Though masked, `mepc[1]` remains writable when IALIGN=32.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Exception Program Counter (`mepc`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1205, + 1209 + ] + }, + { + "chunk_id": "chunk_a3273ca0", + "text": "`mepc` is a *WARL* register that must be able to hold all valid virtual addresses.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Exception Program Counter (`mepc`) Register", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1211, + 1214 + ] + }, + { + "chunk_id": "chunk_9e9d6e72", + "text": "It need not be capable of holding all possible invalid addresses.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Exception Program Counter (`mepc`) Register", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1211, + 1214 + ] + }, + { + "chunk_id": "chunk_7e79b09c", + "text": "Prior to writing `mepc`, implementations may convert an invalid address into some other invalid address that `mepc` is capable of holding.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Exception Program Counter (`mepc`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1211, + 1214 + ] + }, + { + "chunk_id": "chunk_2ce18db2", + "text": "When a trap is taken into M-mode, `mepc` is written with the virtual address of the instruction that was interrupted or that encountered the exception.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Exception Program Counter (`mepc`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1216, + 1219 + ] + }, + { + "chunk_id": "chunk_79085299", + "text": "Otherwise, `mepc` is never written by the implementation, though it may be explicitly written by software.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Exception Program Counter (`mepc`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1216, + 1219 + ] + }, + { + "chunk_id": "chunk_974d8b2b", + "text": "The `mcause` register is an MXLEN-bit read-write register formatted as shown in .", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Cause (`mcause`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 1228, + 1233 + ] + }, + { + "chunk_id": "chunk_cd2a0388", + "text": "When a trap is taken into M-mode, `mcause` is written with a code indicating the event that caused the trap.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Cause (`mcause`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1228, + 1233 + ] + }, + { + "chunk_id": "chunk_3225e09a", + "text": "Otherwise, `mcause` is never written by the implementation, though it may be explicitly written by software.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Cause (`mcause`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1228, + 1233 + ] + }, + { + "chunk_id": "chunk_7f146307", + "text": "The Interrupt bit in the `mcause` register is set if the trap was caused by an interrupt.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Cause (`mcause`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1235, + 1240 + ] + }, + { + "chunk_id": "chunk_90c085b1", + "text": "The Exception Code field contains a code identifying the last exception or interrupt. lists the possible machine-level exception codes.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Cause (`mcause`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 1235, + 1240 + ] + }, + { + "chunk_id": "chunk_1a7a51a1", + "text": "The Exception Code is a *WLRL* field, so is only guaranteed to hold supported exception codes.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Cause (`mcause`) Register", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1235, + 1240 + ] + }, + { + "chunk_id": "chunk_f7fe7e88", + "text": "If an instruction may raise multiple synchronous exceptions, the decreasing priority order of indicates which exception is taken and reported in `mcause`.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Cause (`mcause`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1250, + 1253 + ] + }, + { + "chunk_id": "chunk_a01cd9ba", + "text": "The priority of any custom synchronous exceptions is implementation-defined.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Cause (`mcause`) Register", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 1250, + 1253 + ] + }, + { + "chunk_id": "chunk_dc4b8d54", + "text": "|1 + 1 + 1 + 1 |4 + 5 + 6 + 7 |Reserved + Supervisor timer interrupt + Reserved + Machine timer interrupt |1 + 1 + 1 + 1 |8 + 9 + 10 + 11 |Reserved + Supervisor external interrupt + Reserved + Machine external interrupt |1 + 1 + 1 + 1 |12 + 13 + 14-15 + {ge}16 |Reserved + Counter-overflow interrupt + Reserved + Designated for platform use |0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 |0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 11 + 12 + 13 + 14 + 15 + 16 + 17 + 18 + 19 + 20-23 + 24-31 + 32-47 + 48-63 + {ge}64 |Instruction address misaligned + Instruction access fault + Illegal instruction + Breakpoint + Load address misaligned + Load access fault + Store/AMO address misaligned + Store/AMO access fault + Environment call from U-mode + Environment call from S-mode + Reserved + Environment call from M-mode + Instruction page fault + Load page fault + Reserved + Store/AMO page fault + Double trap + Reserved + Software check + Hardware error + Reserved + Designated for custom use + Reserved + Designated for custom use + Reserved |", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Cause (`mcause`) Register", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 1275, + 1386 + ] + }, + { + "chunk_id": "chunk_59198742", + "text": "| .>|2 + 0 + 8,9,11 + 3 + 3 .<|Illegal instruction + Instruction address misaligned + Environment call + Environment break + Load/store/AMO address breakpoint", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Cause (`mcause`) Register", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 1401, + 1409 + ] + }, + { + "chunk_id": "chunk_01630f9a", + "text": "If not higher priority: + Load/store/AMO address misaligned |", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Cause (`mcause`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1411, + 1419 + ] + }, + { + "chunk_id": "chunk_7d41c0f4", + "text": "When a virtual address is translated into a physical address, the address translation algorithm determines what specific exception may be raised.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Cause (`mcause`) Register", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1421, + 1423 + ] + }, + { + "chunk_id": "chunk_8b2ae533", + "text": "Load/store/AMO address-misaligned exceptions may have either higher or lower priority than load/store/AMO page-fault and access-fault exceptions.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Cause (`mcause`) Register", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1425, + 1426 + ] + }, + { + "chunk_id": "chunk_b3de19a0", + "text": "The `mtval` register is an MXLEN-bit read-write register formatted as shown in .", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 1430, + 1442 + ] + }, + { + "chunk_id": "chunk_c6bb5c39", + "text": "When a trap is taken into M-mode, `mtval` is either set to zero or written with exception-specific information to assist software in handling the trap.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 1430, + 1442 + ] + }, + { + "chunk_id": "chunk_926a2a42", + "text": "Otherwise, `mtval` is never written by the implementation, though it may be explicitly written by software.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1430, + 1442 + ] + }, + { + "chunk_id": "chunk_86032fce", + "text": "The hardware platform will specify which exceptions must set `mtval` informatively, which may unconditionally set it to zero, and which may exhibit either behavior, depending on the underlying event that caused the exception.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1430, + 1442 + ] + }, + { + "chunk_id": "chunk_793ceab0", + "text": "If the hardware platform specifies that no exceptions set `mtval` to a nonzero value, then `mtval` is read-only zero.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 1430, + 1442 + ] + }, + { + "chunk_id": "chunk_534a4458", + "text": "If `mtval` is written with a nonzero value when a breakpoint, address-misaligned, access-fault, page-fault, or hardware-error exception occurs on an instruction fetch, load, or store, then `mtval` will contain the faulting virtual address.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1444, + 1447 + ] + }, + { + "chunk_id": "chunk_4e9f7500", + "text": "On a breakpoint exception raised by an EBREAK or C.EBREAK instruction, `mtval` is written with either zero or the virtual address of the instruction.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1449, + 1450 + ] + }, + { + "chunk_id": "chunk_781d6ea8", + "text": "Recording the same address in `mtval` is redundant; the option is provided for backwards compatibility.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1452, + 1455 + ] + }, + { + "chunk_id": "chunk_79005a81", + "text": "When page-based virtual memory is enabled, `mtval` is written with the faulting virtual address, even for physical-memory access-fault exceptions.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 1457, + 1460 + ] + }, + { + "chunk_id": "chunk_4aa9808b", + "text": "This design reduces datapath cost for most implementations, particularly those with hardware page-table walkers.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1457, + 1460 + ] + }, + { + "chunk_id": "chunk_4a820417", + "text": "If `mtval` is written with a nonzero value when a misaligned load or store causes an access-fault, page-fault, or hardware-error exception, then `mtval` will contain the virtual address of the portion of the access that caused the fault.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1466, + 1468 + ] + }, + { + "chunk_id": "chunk_eae12ebf", + "text": "If `mtval` is written with a nonzero value when an instruction access-fault, page-fault, or hardware-error exception occurs on a hart with variable-length instructions, then `mtval` will contain the virtual address of the portion of the instruction that caused the fault, while `mepc` will point to the beginning of the instruction.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1470, + 1474 + ] + }, + { + "chunk_id": "chunk_517a9e58", + "text": "The `mtval` register can optionally also be used to return the faulting instruction bits on an illegal-instruction exception (`mepc` points to the faulting instruction in memory).", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1476, + 1480 + ] + }, + { + "chunk_id": "chunk_f212f1d7", + "text": "If `mtval` is written with a nonzero value when an illegal-instruction exception occurs, then `mtval` will contain the shortest of:", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1476, + 1480 + ] + }, + { + "chunk_id": "chunk_96e13513", + "text": "the first ILEN bits of the faulting instruction", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1485, + 1485 + ] + }, + { + "chunk_id": "chunk_5bd38fb8", + "text": "the first MXLEN bits of the faulting instruction", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "range", + "line_range": [ + 1487, + 1487 + ] + }, + { + "chunk_id": "chunk_7ae3e0e3", + "text": "The value loaded into `mtval` on an illegal-instruction exception is right-justified and all unused upper bits are cleared to zero.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 1489, + 1490 + ] + }, + { + "chunk_id": "chunk_b4ad84cb", + "text": "On a trap caused by a software-check exception, the `mtval` register holds the cause for the exception.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1492, + 1493 + ] + }, + { + "chunk_id": "chunk_7fddd41d", + "text": "Defined by the Zicfilp extension (). * 3 - Shadow Stack Fault.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1495, + 1498 + ] + }, + { + "chunk_id": "chunk_b357cf49", + "text": "Defined by the Zicfiss extension ().", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1495, + 1498 + ] + }, + { + "chunk_id": "chunk_01ce2592", + "text": "For other traps, `mtval` is set to zero, but a future standard may redefine `mtval`\u2019s setting for other traps.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 1500, + 1501 + ] + }, + { + "chunk_id": "chunk_222a5514", + "text": "If `mtval` is not read-only zero, it is a *WARL* register that must be able to hold all valid virtual addresses and the value zero.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 1503, + 1510 + ] + }, + { + "chunk_id": "chunk_d6a14e20", + "text": "It need not be capable of holding all possible invalid addresses.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1503, + 1510 + ] + }, + { + "chunk_id": "chunk_7158f972", + "text": "Prior to writing `mtval`, implementations may convert an invalid address into some other invalid address that `mtval` is capable of holding.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1503, + 1510 + ] + }, + { + "chunk_id": "chunk_26152e75", + "text": "If the feature to return the faulting instruction bits is implemented, `mtval` must also be able to hold all values less than 2^N^, where N is the smaller of MXLEN and ILEN.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 1503, + 1510 + ] + }, + { + "chunk_id": "chunk_0e2bd3cd", + "text": "The `mconfigptr` register is an MXLEN-bit read-only CSR formatted as shown in , that holds the physical address of a configuration data structure.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Configuration Pointer (`mconfigptr`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 1514, + 1517 + ] + }, + { + "chunk_id": "chunk_b37b4366", + "text": "Software can traverse this data structure to discover information about the harts, the platform, and their configuration.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Configuration Pointer (`mconfigptr`) Register", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 1514, + 1517 + ] + }, + { + "chunk_id": "chunk_fa8f1791", + "text": "The pointer alignment in bits must be no smaller than MXLEN: i.e., if MXLEN is 8{times}n, then `mconfigptr`[log~2n~-1:0] must be zero.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Configuration Pointer (`mconfigptr`) Register", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 1523, + 1524 + ] + }, + { + "chunk_id": "chunk_f759daba", + "text": "The `mconfigptr` register must be implemented, but it may be zero to indicate the configuration data structure does not exist or that an alternative mechanism must be used to locate it.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Configuration Pointer (`mconfigptr`) Register", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1526, + 1529 + ] + }, + { + "chunk_id": "chunk_6b5d94e6", + "text": "The `menvcfg` CSR is a 64-bit read/write register, formatted as shown in , that controls certain characteristics of the execution environment for modes less privileged than M.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 1534, + 1537 + ] + }, + { + "chunk_id": "chunk_b26cd47f", + "text": "If bit FIOM (Fence of I/O implies Memory) is set to one in `menvcfg`, FENCE instructions executed in modes less privileged than M are modified so the requirement to order accesses to device I/O implies also the requirement to order main memory accesses. details the modified interpretation of FENCE instruction bits PI, PO, SI, and SO for modes less privileged than M when FIOM=1.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 1543, + 1548 + ] + }, + { + "chunk_id": "chunk_c6bedfde", + "text": "Similarly, for modes less privileged than M when FIOM=1, if an atomic instruction that accesses a region ordered as device I/O has its aq and/or rl bit set, then that instruction is ordered as though it accesses both device I/O and memory.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1550, + 1553 + ] + }, + { + "chunk_id": "chunk_1a819b2c", + "text": "If S-mode is not supported, or if `satp`.MODE is read-only zero (always Bare), the implementation may make FIOM read-only zero.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 1555, + 1556 + ] + }, + { + "chunk_id": "chunk_b5c82b97", + "text": "When PBMTE=1, Svpbmt is available for S-mode and G-stage address translation.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1573, + 1581 + ] + }, + { + "chunk_id": "chunk_c7535f8e", + "text": "When PBMTE=0, the implementation behaves as though Svpbmt were not implemented.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1573, + 1581 + ] + }, + { + "chunk_id": "chunk_5d6cfd13", + "text": "If Svpbmt is not implemented, PBMTE is read-only zero.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 1573, + 1581 + ] + }, + { + "chunk_id": "chunk_01e2e285", + "text": "Furthermore, for implementations with the hypervisor extension, `henvcfg`.PBMTE is read-only zero if `menvcfg`.PBMTE is zero.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 1573, + 1581 + ] + }, + { + "chunk_id": "chunk_9177ce98", + "text": "After changing `menvcfg`.PBMTE, executing an SFENCE.VMA instruction with rs1=`x0` and rs2=`x0` suffices to synchronize address-translation caches with respect to the altered interpretation of page-table entries' PBMT fields.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1583, + 1587 + ] + }, + { + "chunk_id": "chunk_63b376fc", + "text": "See for additional synchronization requirements when the hypervisor extension is implemented.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 1583, + 1587 + ] + }, + { + "chunk_id": "chunk_2ea06bc7", + "text": "If the Svadu extension is implemented, the ADUE bit controls whether hardware updating of PTE A/D bits is enabled for S-mode and G-stage address translations.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 1589, + 1602 + ] + }, + { + "chunk_id": "chunk_32026e87", + "text": "When ADUE=1, hardware updating of PTE A/D bits is enabled during S-mode address translation, and the implementation behaves as though the Svade extension were not implemented for S-mode address translation.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 1589, + 1602 + ] + }, + { + "chunk_id": "chunk_1c2cd140", + "text": "When the hypervisor extension is implemented, if ADUE=1, hardware updating of PTE A/D bits is enabled during G-stage address translation, and the implementation behaves as though the Svade extension were not implemented for G-stage address translation.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "binary", + "line_range": [ + 1589, + 1602 + ] + }, + { + "chunk_id": "chunk_63e6cf67", + "text": "When ADUE=0, the implementation behaves as though Svade were implemented for S-mode and G-stage address translation.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1589, + 1602 + ] + }, + { + "chunk_id": "chunk_1713000e", + "text": "If Svadu is not implemented, ADUE is read-only zero.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 1589, + 1602 + ] + }, + { + "chunk_id": "chunk_8c077b4e", + "text": "Furthermore, for implementations with the hypervisor extension, `henvcfg`.ADUE is read-only zero if `menvcfg`.ADUE is zero.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 1589, + 1602 + ] + }, + { + "chunk_id": "chunk_959d9d23", + "text": "After changing `menvcfg`.ADUE, executing an SFENCE.VMA instruction with rs1=`x0` and rs2=`x0` suffices to synchronize address-translation caches with respect to the altered interpretation of page-table entries' A/D bits.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1604, + 1608 + ] + }, + { + "chunk_id": "chunk_8e0f208d", + "text": "See for additional synchronization requirements when the hypervisor extension is implemented.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 1604, + 1608 + ] + }, + { + "chunk_id": "chunk_02ef84a2", + "text": "If the Smcdeleg extension is implemented, the CDE (Counter Delegation Enable) bit controls whether Zicntr and Zihpm counters can be delegated to S-mode.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 1613, + 1616 + ] + }, + { + "chunk_id": "chunk_c2cae747", + "text": "When CDE=0, the Smcdeleg and Ssccfg extensions appear to be not implemented.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1613, + 1616 + ] + }, + { + "chunk_id": "chunk_19f6cc0e", + "text": "If Smcdeleg is not implemented, CDE is read-only zero.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 1613, + 1616 + ] + }, + { + "chunk_id": "chunk_6eea3e76", + "text": "The Sstc extension adds the `STCE` (STimecmp Enable) bit to `menvcfg` CSR.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1618, + 1626 + ] + }, + { + "chunk_id": "chunk_fbe0044a", + "text": "When the Sstc extension is not implemented, `STCE` is read-only zero.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 1618, + 1626 + ] + }, + { + "chunk_id": "chunk_9acac6ae", + "text": "The `STCE` bit enables `stimecmp` for S-mode when set to one.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 1618, + 1626 + ] + }, + { + "chunk_id": "chunk_418c4aa9", + "text": "When this extension is implemented and `STCE` in `menvcfg` is zero, an attempt to access `stimecmp` in a mode other than M-mode raises an illegal-instruction exception, `STCE` in `henvcfg` is read-only zero, and `STIP` in `mip` and `sip` reverts to its defined behavior as if this extension is not implemented.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 1618, + 1626 + ] + }, + { + "chunk_id": "chunk_bf49779f", + "text": "Further, if the H extension is implemented, then `hip`.VSTIP also reverts its defined behavior as if this extension is not implemented.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1618, + 1626 + ] + }, + { + "chunk_id": "chunk_32c01454", + "text": "The Zicboz extension adds the `CBZE` (Cache Block Zero instruction enable) field to `menvcfg`.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1628, + 1633 + ] + }, + { + "chunk_id": "chunk_b0abffbc", + "text": "When the `CBZE` field is set to 1, it enables execution of the cache block zero instruction, `CBO.ZERO`, in modes less privileged than M.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 1628, + 1633 + ] + }, + { + "chunk_id": "chunk_daa32a31", + "text": "Otherwise, the instruction raises an illegal-instruction exception in modes less privileged than M.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 1628, + 1633 + ] + }, + { + "chunk_id": "chunk_dee85240", + "text": "When the Zicboz extension is not implemented, `CBZE` is read-only zero.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 1628, + 1633 + ] + }, + { + "chunk_id": "chunk_e87db62f", + "text": "The Zicbom extension adds the `CBCFE` (Cache Block Clean and Flush instruction Enable) field to `menvcfg`.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1635, + 1640 + ] + }, + { + "chunk_id": "chunk_6347d506", + "text": "When the `CBCFE` field is set to 1, it enables execution of the cache block clean instruction (`CBO.CLEAN`) and the cache block flush instruction (`CBO.FLUSH`) in modes less privileged than M.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 1635, + 1640 + ] + }, + { + "chunk_id": "chunk_33bcce79", + "text": "Otherwise, these instructions raise an illegal-instruction exception in modes less privileged than M.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 1635, + 1640 + ] + }, + { + "chunk_id": "chunk_15592db1", + "text": "When the Zicbom extension is not implemented, `CBCFE` is read-only zero.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 1635, + 1640 + ] + }, + { + "chunk_id": "chunk_3c696e69", + "text": "The Zicbom extension adds the `CBIE` (Cache Block Invalidate instruction Enable) WARL field to `menvcfg` to control execution of the cache block invalidate instruction (`CBO.INVAL`) in modes less privileged than M.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1642, + 1651 + ] + }, + { + "chunk_id": "chunk_f8bb0d24", + "text": "When `CBIE` is set to `00b`, the instruction raises an illegal-instruction exception in modes less privileged than M.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 1642, + 1651 + ] + }, + { + "chunk_id": "chunk_c9bfe064", + "text": "When the Zicbom extension is not implemented, `CBIE` is read-only zero.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 1642, + 1651 + ] + }, + { + "chunk_id": "chunk_be418e42", + "text": "The encoding `10b` is reserved.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 1642, + 1651 + ] + }, + { + "chunk_id": "chunk_f992dc0a", + "text": "When `CBIE` is set to `01b` or `11b`, and when enabled for execution in modes less privileged than M, it behaves as follows:", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 1642, + 1651 + ] + }, + { + "chunk_id": "chunk_68bcc158", + "text": "If Smnpm is not implemented, `PMM` is read-only zero.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 1660, + 1665 + ] + }, + { + "chunk_id": "chunk_2d2afed6", + "text": "The `PMM` field is read-only zero for RV32.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 1660, + 1665 + ] + }, + { + "chunk_id": "chunk_8d373a3d", + "text": "The Zicfilp extension adds the `LPE` field in `menvcfg`.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1678, + 1683 + ] + }, + { + "chunk_id": "chunk_b1cf0b58", + "text": "When the `LPE` field is set to 1 and S-mode is implemented, the Zicfilp extension is enabled in S-mode.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 1678, + 1683 + ] + }, + { + "chunk_id": "chunk_70faa1c2", + "text": "If `LPE` field is set to 1 and S-mode is not implemented, the Zicfilp extension is enabled in U-mode.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 1678, + 1683 + ] + }, + { + "chunk_id": "chunk_269adcd5", + "text": "When the `LPE` field is 0, the Zicfilp extension is not enabled in S-mode, and the following rules apply to S-mode.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 1678, + 1683 + ] + }, + { + "chunk_id": "chunk_b8f6606f", + "text": "If the `LPE` field is 0 and S-mode is not implemented, then the same rules apply to U-mode.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 1678, + 1683 + ] + }, + { + "chunk_id": "chunk_a8b987e5", + "text": "The Zicfiss extension adds the `SSE` field to `menvcfg`.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1689, + 1691 + ] + }, + { + "chunk_id": "chunk_91215264", + "text": "When the `SSE` field is set to 1 the Zicfiss extension is activated in S-mode.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 1689, + 1691 + ] + }, + { + "chunk_id": "chunk_d2e9f392", + "text": "When `SSE` field is 0, the following rules apply to privilege modes that are less than M:", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "range", + "line_range": [ + 1689, + 1691 + ] + }, + { + "chunk_id": "chunk_98301486", + "text": "When `menvcfg.SSE` is 0, the `henvcfg.SSE` and `senvcfg.SSE` fields are read-only zero.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 1699, + 1700 + ] + }, + { + "chunk_id": "chunk_5ae49243", + "text": "The Ssdbltrp extension adds the double-trap-enable (`DTE`) field in `menvcfg`.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1702, + 1705 + ] + }, + { + "chunk_id": "chunk_2947ff05", + "text": "When `menvcfg.DTE` is zero, the implementation behaves as though Ssdbltrp is not implemented.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1702, + 1705 + ] + }, + { + "chunk_id": "chunk_4c4e0154", + "text": "When Ssdbltrp is not implemented `sstatus.SDT`, `vsstatus.SDT`, and `henvcfg.DTE` bits are read-only zero.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 1702, + 1705 + ] + }, + { + "chunk_id": "chunk_5097ea49", + "text": "When XLEN=32, `menvcfgh` is a 32-bit read/write register that aliases bits 63:32 of `menvcfg`.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 1707, + 1709 + ] + }, + { + "chunk_id": "chunk_f2a9aeca", + "text": "The `menvcfgh` register does not exist when XLEN=64.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1707, + 1709 + ] + }, + { + "chunk_id": "chunk_0c666e52", + "text": "If U-mode is not supported, then registers `menvcfg` and `menvcfgh` do not exist.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1711, + 1712 + ] + }, + { + "chunk_id": "chunk_ba5dab71", + "text": "`mseccfg` is a 64-bit read/write register, formatted as shown in , that controls security features.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 1718, + 1720 + ] + }, + { + "chunk_id": "chunk_bd90e5f9", + "text": "It exists if any extension that adds a field to `mseccfg` is implemented.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 1718, + 1720 + ] + }, + { + "chunk_id": "chunk_c30b6906", + "text": "Otherwise, it is reserved.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1718, + 1720 + ] + }, + { + "chunk_id": "chunk_bf73c9ea", + "text": "The Zkr extension adds the `SSEED` and `USEED` fields to the `mseccfg` CSR to control access to the `seed` CSR from modes less privileged than M.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1726, + 1728 + ] + }, + { + "chunk_id": "chunk_4b4ffe32", + "text": "When `USEED` is 0, access to the `seed` CSR in U-mode raises an illegal-instruction exception.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1730, + 1734 + ] + }, + { + "chunk_id": "chunk_fc2f2afc", + "text": "When `USEED` is 1, read-write access to the `seed` CSR from U-mode is allowed; all other types of accesses raise an illegal-instruction exception.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1730, + 1734 + ] + }, + { + "chunk_id": "chunk_9fb7b0b0", + "text": "If Zkr or U-mode is not implemented, `USEED` is read-only zero.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 1730, + 1734 + ] + }, + { + "chunk_id": "chunk_977fa0d9", + "text": "When `SSEED` is 0, access to the `seed` CSR from S-/HS-mode raises an illegal-instruction exception.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1736, + 1740 + ] + }, + { + "chunk_id": "chunk_bbc65491", + "text": "When `SSEED` is 1, read-write access to the `seed` CSR from S-/HS-mode is allowed; all other types of accesses raise an illegal-instruction exception.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1736, + 1740 + ] + }, + { + "chunk_id": "chunk_fa844029", + "text": "If Zkr or S-mode is not implemented, `SSEED` is read-only zero.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 1736, + 1740 + ] + }, + { + "chunk_id": "chunk_10bc0f07", + "text": "When the H extension is also implemented, access to the `seed` CSR from an HS-qualified instruction leads to a virtual-instruction exception in VS and VU modes; all other types of accesses raise an illegal-instruction exception.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1742, + 1745 + ] + }, + { + "chunk_id": "chunk_18bfe2c7", + "text": "No exception is raised for read-write. | S/HS | `0` | - | Any `seed` CSR access raises an illegal-instruction exception. | S/HS | `1` | - | The `seed` CSR is accessible as normal.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1747, + 1770 + ] + }, + { + "chunk_id": "chunk_482b8a7e", + "text": "No exception is raised for read-write. | VS/VU | `0` | - | Any `seed` CSR access raises an illegal-instruction exception. | VS/VU | `1` | - | A read-write `seed` access raises a virtual-instruction exception, while other access conditions raise an illegal-instruction exception. |", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1747, + 1770 + ] + }, + { + "chunk_id": "chunk_ef244b8f", + "text": "The Smepmp extension adds the `RLB`, `MMWP`, and the `MML` fields in `mseccfg`.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 1772, + 1774 + ] + }, + { + "chunk_id": "chunk_f2035520", + "text": "When `mseccfg.RLB` (Rule Locking Bypass) a WARL field that provides a mechanism to temporarily modify *Locked* PMP rules.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1776, + 1782 + ] + }, + { + "chunk_id": "chunk_0c2a37d0", + "text": "When `mseccfg.RLB` is 1, locked PMP rules may be removed or modified and locked PMP rules may be edited.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1776, + 1782 + ] + }, + { + "chunk_id": "chunk_b412b8e1", + "text": "When `mseccfg.RLB` is 0 and `pmpcfg.L` is 1 in any rule or entry (including disabled entries), then `mseccfg.RLB` remains 0 and any further modifications to `mseccfg.RLB` are ignored until a *PMP reset*.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 1776, + 1782 + ] + }, + { + "chunk_id": "chunk_b7608473", + "text": "The `mseccfg.MMWP` (Machine-Mode Allowlist Policy) is a WARL field.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1784, + 1790 + ] + }, + { + "chunk_id": "chunk_ca67e96a", + "text": "This field changes the default PMP policy for Machine mode when accessing memory regions that don't have a matching PMP rule.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 1784, + 1790 + ] + }, + { + "chunk_id": "chunk_35ed255e", + "text": "This is a sticky bit, meaning that once set it cannot be unset until a *PMP reset*.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1784, + 1790 + ] + }, + { + "chunk_id": "chunk_de2ac11f", + "text": "When set it changes the default PMP policy for M-mode when accessing memory regions that don\u2019t have a matching *PMP rule*, to *denied* instead of *ignored*.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1784, + 1790 + ] + }, + { + "chunk_id": "chunk_9d4a853a", + "text": "The `mseccfg.MML` (Machine Mode Lockdown) is a WARL field.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1792, + 1796 + ] + }, + { + "chunk_id": "chunk_4f10e145", + "text": "The `MML` bit changes the interpretation of the `pmpcfg.L` bit defined in .", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1792, + 1796 + ] + }, + { + "chunk_id": "chunk_3e56a5dc", + "text": "This is a sticky bit, meaning that once set it cannot be unset until a *PMP reset*.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1792, + 1796 + ] + }, + { + "chunk_id": "chunk_7f8150d9", + "text": "When `mseccfg.MML` is set the system's behavior changes in the following way:", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1792, + 1796 + ] + }, + { + "chunk_id": "chunk_4f692d0e", + "text": "The meaning of `pmpcfg.L` changes: Instead of marking a rule as *locked* and *enforced* in all modes, it now marks a rule as *M-mode-only* when set and *S/U-mode-only* when unset.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1798, + 1814 + ] + }, + { + "chunk_id": "chunk_f400c8d8", + "text": "The formerly reserved encoding of `pmpcfg.RW=01`, and the encoding `pmpcfg.LRWX=1111`, now encode a *Shared-Region*. + + An M-mode-only rule is *enforced* on Machine mode and *denied* in Supervisor or User mode.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1798, + 1814 + ] + }, + { + "chunk_id": "chunk_810446a6", + "text": "A Shared-Region rule where `pmpcfg.L` is not set can be used for sharing data between M-mode and S/U-mode, so is not executable. M-mode has read/write access to that region, and S/U-mode has read access if `pmpcfg.X` is not set, or read/write access if `pmpcfg.X` is set. + * A Shared-Region rule where `pmpcfg.L` is set can be used for sharing code between M-mode and S/U-mode, so is not writable.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1816, + 1832 + ] + }, + { + "chunk_id": "chunk_95dcaca5", + "text": "Both M-mode and S/U-mode have execute access on the region, and M-mode also has read access if `pmpcfg.X` is set.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1816, + 1832 + ] + }, + { + "chunk_id": "chunk_27199825", + "text": "The rule remains *locked* so that any further modifications to its associated configuration or address registers are ignored until a *PMP reset*, unless `mseccfg.RLB` is set.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1816, + 1832 + ] + }, + { + "chunk_id": "chunk_c219f1f2", + "text": "Adding a rule with executable privileges that either is *M-mode-only* or a *locked* *Shared-Region* is not possible and such `pmpcfg` writes are ignored, leaving `pmpcfg` unchanged.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1834, + 1837 + ] + }, + { + "chunk_id": "chunk_3903bbd9", + "text": "Executing code with Machine mode privileges is only possible from memory regions with a matching *M-mode-only* rule or a *locked* *Shared-Region* rule with executable privileges.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1839, + 1842 + ] + }, + { + "chunk_id": "chunk_8e06b98c", + "text": "Executing code from a region without a matching rule or with a matching S/U-mode-only rule is *denied*.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1839, + 1842 + ] + }, + { + "chunk_id": "chunk_a39d18cd", + "text": "If `mseccfg.MML` is not set, the combination of `pmpcfg.RW=01` remains reserved for future standard use.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1844, + 1845 + ] + }, + { + "chunk_id": "chunk_593f6985", + "text": "If Smmpm is not implemented, `PMM` is read-only zero.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 1847, + 1851 + ] + }, + { + "chunk_id": "chunk_d24af57b", + "text": "The `PMM` field is read-only zero for RV32.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 1847, + 1851 + ] + }, + { + "chunk_id": "chunk_64ea3a7c", + "text": "The Zicfilp extension adds the `MLPE` field in `mseccfg`.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 1864, + 1867 + ] + }, + { + "chunk_id": "chunk_ebd343ec", + "text": "When `MLPE` field is 1, Zicfilp extension is enabled in M-mode.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 1864, + 1867 + ] + }, + { + "chunk_id": "chunk_dba9a7c1", + "text": "When the `MLPE` field is 0, the Zicfilp extension is not enabled in M-mode and the following rules apply to M-mode.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 1864, + 1867 + ] + }, + { + "chunk_id": "chunk_eefb9289", + "text": "When XLEN=32 only, `mseccfgh` is a 32-bit read/write register that aliases bits 63:32 of `mseccfg`.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 1873, + 1876 + ] + }, + { + "chunk_id": "chunk_892519ce", + "text": "Register `mseccfgh` exists when XLEN=32 and `mseccfg` is implemented; it does not exist when XLEN=64.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1873, + 1876 + ] + }, + { + "chunk_id": "chunk_65b21959", + "text": "Platforms provide a real-time counter, exposed as a memory-mapped machine-mode read-write register, `mtime`. `mtime` must increment at constant frequency, and the platform must provide a mechanism for determining the period of an `mtime` tick.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level Memory-Mapped Registers > Machine Timer (`mtime` and `mtimecmp`) Registers", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1882, + 1887 + ] + }, + { + "chunk_id": "chunk_7800d79c", + "text": "The `mtime` register will wrap around if the count overflows.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level Memory-Mapped Registers > Machine Timer (`mtime` and `mtimecmp`) Registers", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1882, + 1887 + ] + }, + { + "chunk_id": "chunk_97e21d90", + "text": "The `mtime` register has a 64-bit precision on all RV32 and RV64 systems.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level Memory-Mapped Registers > Machine Timer (`mtime` and `mtimecmp`) Registers", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 1889, + 1898 + ] + }, + { + "chunk_id": "chunk_54ecfd74", + "text": "Platforms provide a 64-bit memory-mapped machine-mode timer compare register (`mtimecmp`). A machine timer interrupt becomes pending whenever `mtime` contains a value greater than or equal to `mtimecmp`, treating the values as unsigned integers.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level Memory-Mapped Registers > Machine Timer (`mtime` and `mtimecmp`) Registers", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 1889, + 1898 + ] + }, + { + "chunk_id": "chunk_90307464", + "text": "The interrupt will only be taken if interrupts are enabled and the MTIE bit is set in the `mie` register.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level Memory-Mapped Registers > Machine Timer (`mtime` and `mtimecmp`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 1889, + 1898 + ] + }, + { + "chunk_id": "chunk_a1e92fba", + "text": "If the result of the comparison between `mtime` and `mtimecmp` changes, it is guaranteed to be reflected in MTIP eventually, but not necessarily immediately.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level Memory-Mapped Registers > Machine Timer (`mtime` and `mtimecmp`) Registers", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1908, + 1909 + ] + }, + { + "chunk_id": "chunk_79f3e2fa", + "text": "In RV32, memory-mapped writes to `mtimecmp` modify only one 32-bit part of the register.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level Memory-Mapped Registers > Machine Timer (`mtime` and `mtimecmp`) Registers", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 1911, + 1914 + ] + }, + { + "chunk_id": "chunk_7f162edb", + "text": "The following code sequence sets a 64-bit `mtimecmp` value without spuriously generating a timer interrupt due to the intermediate value of the comparand:", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level Memory-Mapped Registers > Machine Timer (`mtime` and `mtimecmp`) Registers", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 1911, + 1914 + ] + }, + { + "chunk_id": "chunk_24712c10", + "text": "For RV64, naturally aligned 64-bit memory accesses to the `mtime` and `mtimecmp` registers are additionally supported and are atomic.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level Memory-Mapped Registers > Machine Timer (`mtime` and `mtimecmp`) Registers", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 1916, + 1917 + ] + }, + { + "chunk_id": "chunk_2e11952f", + "text": "The `time` CSR is a read-only shadow of the memory-mapped `mtime` register.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level Memory-Mapped Registers > Machine Timer (`mtime` and `mtimecmp`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1929, + 1934 + ] + }, + { + "chunk_id": "chunk_006b0259", + "text": "When XLEN=32, the `timeh` CSR is a read-only shadow of the upper 32 bits of the memory-mapped `mtime` register, while `time` shadows only the lower 32 bits of `mtime`.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level Memory-Mapped Registers > Machine Timer (`mtime` and `mtimecmp`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 1929, + 1934 + ] + }, + { + "chunk_id": "chunk_7791f5a5", + "text": "When `mtime` changes, it is guaranteed to be reflected in `time` and `timeh` eventually, but not necessarily immediately.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level Memory-Mapped Registers > Machine Timer (`mtime` and `mtimecmp`) Registers", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1929, + 1934 + ] + }, + { + "chunk_id": "chunk_edb19234", + "text": "When executed in U-mode, S-mode, or M-mode, it generates an environment-call-from-U-mode exception, environment-call-from-S-mode exception, or environment-call-from-M-mode exception, respectively, and performs no other operation.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Mode Privileged Instructions > Environment Call and Breakpoint", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1943, + 1948 + ] + }, + { + "chunk_id": "chunk_b34539c3", + "text": "Unless overridden by an external debug environment, EBREAK raises a breakpoint exception and performs no other operation.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Mode Privileged Instructions > Environment Call and Breakpoint", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 1950, + 1954 + ] + }, + { + "chunk_id": "chunk_ff65dbc6", + "text": "As ECALL and EBREAK cause synchronous exceptions, they are not considered to retire, and should not increment the `minstret` CSR.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Mode Privileged Instructions > Environment Call and Breakpoint", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1956, + 1961 + ] + }, + { + "chunk_id": "chunk_aff32645", + "text": "Instructions to return from trap are encoded under the PRIV minor opcode.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Mode Privileged Instructions > Trap-Return Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 1966, + 1967 + ] + }, + { + "chunk_id": "chunk_04fc3024", + "text": "To return after handling a trap, there are separate trap return instructions per privilege level, MRET and SRET. MRET is always provided. SRET must be provided if supervisor mode is supported, and should raise an illegal-instruction exception otherwise. SRET should also raise an illegal-instruction exception when TSR=1 in `mstatus`, as described in .", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Mode Privileged Instructions > Trap-Return Instructions", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1972, + 1984 + ] + }, + { + "chunk_id": "chunk_b472bbc9", + "text": "An xRET instruction can be executed in privilege mode x or higher, where executing a lower-privilege xRET instruction will pop the relevant lower-privilege interrupt enable and privilege mode stack.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Mode Privileged Instructions > Trap-Return Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 1972, + 1984 + ] + }, + { + "chunk_id": "chunk_e0ca707b", + "text": "Attempting to execute an xRET instruction in a mode less privileged than x will raise an illegal-instruction exception.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Mode Privileged Instructions > Trap-Return Instructions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 1972, + 1984 + ] + }, + { + "chunk_id": "chunk_45390cc1", + "text": "If the Zalrsc extension is supported, the xRET instruction is allowed to clear any outstanding LR address reservation but is not required to.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Mode Privileged Instructions > Trap-Return Instructions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1989, + 1992 + ] + }, + { + "chunk_id": "chunk_0f05e3d9", + "text": "The Wait for Interrupt instruction (WFI) informs the implementation that the current hart can be stalled until an interrupt might need servicing.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Mode Privileged Instructions > Wait for Interrupt", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1997, + 2005 + ] + }, + { + "chunk_id": "chunk_03c4951a", + "text": "Execution of the WFI instruction can also be used to inform the hardware platform that suitable interrupts should preferentially be routed to this hart. WFI is available in all privileged modes, and optionally available to U-mode.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Mode Privileged Instructions > Wait for Interrupt", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1997, + 2005 + ] + }, + { + "chunk_id": "chunk_b65aadba", + "text": "This instruction may raise an illegal-instruction exception when TW=1 in `mstatus`, as described in .", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Mode Privileged Instructions > Wait for Interrupt", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1997, + 2005 + ] + }, + { + "chunk_id": "chunk_00a8dd91", + "text": "Implementations are permitted to resume execution for any reason, even if an enabled interrupt has not become pending.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Mode Privileged Instructions > Wait for Interrupt", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 2014, + 2016 + ] + }, + { + "chunk_id": "chunk_9c93ef29", + "text": "The WFI instruction can also be executed when interrupts are disabled.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Mode Privileged Instructions > Wait for Interrupt", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 2018, + 2027 + ] + }, + { + "chunk_id": "chunk_e5b652e9", + "text": "The operation of WFI must be unaffected by the global interrupt bits in `mstatus` (MIE and SIE) and the delegation register `mideleg` (i.e., the hart must resume if a locally enabled interrupt becomes pending, even if it has been delegated to a less-privileged mode), but should honor the individual interrupt enables (e.g, MTIE) (i.e., implementations should avoid resuming the hart if the interrupt is pending but not individually enabled). WFI is also required to resume execution for locally enabled interrupts pending at any privilege level, regardless of the global interrupt enable at each privilege level.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Mode Privileged Instructions > Wait for Interrupt", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 2018, + 2027 + ] + }, + { + "chunk_id": "chunk_df1342f6", + "text": "If the event that causes the hart to resume execution does not cause an interrupt to be taken, execution will resume at `pc` + 4, and software must determine what action to take, including looping back to repeat the WFI if there was no actionable event.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Mode Privileged Instructions > Wait for Interrupt", + "confidence": "very_high", + "parameter_class": "SW_rule", + "parameter_type": "binary", + "line_range": [ + 2029, + 2032 + ] + }, + { + "chunk_id": "chunk_25fda74a", + "text": "It is recommended that these instructions use bits 29:28 to designate the minimum required privilege mode, as do other SYSTEM instructions.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Mode Privileged Instructions > Custom SYSTEM Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "range", + "line_range": [ + 2036, + 2037 + ] + }, + { + "chunk_id": "chunk_1c8c97b6", + "text": "The `mstatus` fields MIE and MPRV are reset to 0.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Reset", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 2046, + 2063 + ] + }, + { + "chunk_id": "chunk_186ccbca", + "text": "If little-endian memory accesses are supported, the `mstatus`/`mstatush` field MBE is reset to 0.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Reset", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 2046, + 2063 + ] + }, + { + "chunk_id": "chunk_b8c74e12", + "text": "The `mcause` register is set to a value indicating the cause of the reset.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Reset", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 2046, + 2063 + ] + }, + { + "chunk_id": "chunk_93700694", + "text": "Writable PMP registers\u2019 A and L fields are set to 0, unless the platform mandates a different reset value for some PMP registers\u2019 A and L fields.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Reset", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 2046, + 2063 + ] + }, + { + "chunk_id": "chunk_480c0e35", + "text": "If the hypervisor extension is implemented, the `hgatp`.MODE and `vsatp`.MODE fields are reset to 0.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Reset", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 2046, + 2063 + ] + }, + { + "chunk_id": "chunk_dd88cbd0", + "text": "If the Smrnmi extension is implemented, the `mnstatus`.NMIE field is reset to 0.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Reset", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 2046, + 2063 + ] + }, + { + "chunk_id": "chunk_11c7f5e7", + "text": "No *WARL* field contains an illegal value.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Reset", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 2046, + 2063 + ] + }, + { + "chunk_id": "chunk_eca283a6", + "text": "If the Zicfilp extension is implemented, the `mseccfg`.MLPE field is reset to 0.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Reset", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 2046, + 2063 + ] + }, + { + "chunk_id": "chunk_b9ee0be9", + "text": "The `MML`, `MMWP`, and `RLB` fields of the `mseccfg` register are set to 0, unless the platform mandates a different reset value.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Reset", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 2065, + 2066 + ] + }, + { + "chunk_id": "chunk_9a10caea", + "text": "The `mcause` values after reset have implementation-specific interpretation, but the value 0 should be returned on implementations that do not distinguish different reset conditions.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Reset", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 2068, + 2072 + ] + }, + { + "chunk_id": "chunk_1a2848d5", + "text": "Implementations that distinguish different reset conditions should only use 0 to indicate the most complete reset.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Reset", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 2068, + 2072 + ] + }, + { + "chunk_id": "chunk_fa505870", + "text": "The `USEED` and `SSEED` fields of the `mseccfg` CSR must have defined reset values.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Reset", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 2074, + 2076 + ] + }, + { + "chunk_id": "chunk_f3258bf2", + "text": "The system must not allow them to be in an undefined state after reset.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Reset", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 2074, + 2076 + ] + }, + { + "chunk_id": "chunk_fa97c770", + "text": "Non-maskable interrupts (NMIs) are only used for hardware error conditions, and cause an immediate jump to an implementation-defined NMI vector running in M-mode regardless of the state of a hart\u2019s interrupt enable bits.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Non-Maskable Interrupts", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 2081, + 2087 + ] + }, + { + "chunk_id": "chunk_712fbb13", + "text": "The `mepc` register is written with the virtual address of the instruction that was interrupted, and `mcause` is set to a value indicating the source of the NMI.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Non-Maskable Interrupts", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 2081, + 2087 + ] + }, + { + "chunk_id": "chunk_54ad5d46", + "text": "The NMI can thus overwrite state in an active machine-mode interrupt handler.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Non-Maskable Interrupts", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2081, + 2087 + ] + }, + { + "chunk_id": "chunk_653548de", + "text": "The values written to `mcause` on an NMI are implementation-defined.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Non-Maskable Interrupts", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 2089, + 2093 + ] + }, + { + "chunk_id": "chunk_43254bed", + "text": "The high Interrupt bit of `mcause` should be set to indicate that this was an interrupt.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Non-Maskable Interrupts", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 2089, + 2093 + ] + }, + { + "chunk_id": "chunk_21daabb2", + "text": "An Exception Code of 0 is reserved to mean \"unknown cause\" and implementations that do not distinguish sources of NMIs via the `mcause` register should return 0 in the Exception Code.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Non-Maskable Interrupts", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 2089, + 2093 + ] + }, + { + "chunk_id": "chunk_4dc84b16", + "text": "While many other architectures specify some PMAs in the virtual memory page tables and use the TLB to inform the pipeline of these properties, this approach injects platform-specific information into a virtualized layer and can cause system errors unless attributes are correctly initialized in each page-table entry for each physical memory region.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2129, + 2141 + ] + }, + { + "chunk_id": "chunk_c43827a6", + "text": "To aid in system debugging, we strongly recommend that, where possible, RISC-V processors precisely trap physical memory accesses that fail PMA checks.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2143, + 2161 + ] + }, + { + "chunk_id": "chunk_b87799a4", + "text": "Precisely trapped PMA violations manifest as instruction, load, or store access-fault exceptions, distinct from virtual-memory page-fault exceptions.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2143, + 2161 + ] + }, + { + "chunk_id": "chunk_2818e023", + "text": "In this case, error responses from peripheral devices will be reported as imprecise bus-error interrupts.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2143, + 2161 + ] + }, + { + "chunk_id": "chunk_f64e8f25", + "text": "PMAs must also be readable by software to correctly access certain devices or to correctly configure other hardware components that access memory, such as DMA engines.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes", + "confidence": "very_high", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 2163, + 2173 + ] + }, + { + "chunk_id": "chunk_9cf0e652", + "text": "Some devices, particularly legacy buses, do not support discovery of PMAs and so will give error responses or time out if an unsupported access is attempted.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2163, + 2173 + ] + }, + { + "chunk_id": "chunk_cc33ae7e", + "text": "Access types specify which access widths, from 8-bit byte to long multi-word burst, are supported, and also whether misaligned accesses are supported for each access width.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Supported Access Type PMAs", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 2199, + 2201 + ] + }, + { + "chunk_id": "chunk_15791c2c", + "text": "For each level of support, naturally aligned AMOs of a given width are supported if the underlying memory region supports reads and writes of that width.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Atomicity PMAs > AMO PMA", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2221, + 2230 + ] + }, + { + "chunk_id": "chunk_ba6ed978", + "text": "Main memory and I/O regions may only support a subset or none of the processor-supported atomic operations.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Atomicity PMAs > AMO PMA", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 2221, + 2230 + ] + }, + { + "chunk_id": "chunk_a9aff880", + "text": "This PMA, if present, specifies the size of a misaligned atomicity granule, a naturally aligned power-of-two number of bytes.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Misaligned Atomicity Granule PMA", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2276, + 2282 + ] + }, + { + "chunk_id": "chunk_69e8598b", + "text": "If a misaligned AMO accesses a region that does not specify a misaligned atomicity granule PMA, or if not all accessed bytes lie within the same misaligned atomicity granule, then an exception is raised.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Misaligned Atomicity Granule PMA", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 2292, + 2300 + ] + }, + { + "chunk_id": "chunk_1f538eb5", + "text": "For regular loads and stores that access such a region or for which not all accessed bytes lie within the same atomicity granule, then either an exception is raised, or the access proceeds but is not guaranteed to be atomic.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Misaligned Atomicity Granule PMA", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 2292, + 2300 + ] + }, + { + "chunk_id": "chunk_27842136", + "text": "Implementations may raise access-fault exceptions instead of address-misaligned exceptions for some misaligned accesses, indicating the instruction should not be emulated by a trap handler.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Misaligned Atomicity Granule PMA", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 2292, + 2300 + ] + }, + { + "chunk_id": "chunk_d0db9795", + "text": "Vector memory accesses are also unaffected, so might execute non-atomically even when contained within a misaligned atomicity granule.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Misaligned Atomicity Granule PMA", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2302, + 2306 + ] + }, + { + "chunk_id": "chunk_2107401a", + "text": "Accesses by one hart to an I/O region are observable not only by other harts and bus mastering devices but also by the targeted I/O devices, and I/O regions may be accessed with either relaxed or strong ordering.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Memory-Ordering PMAs", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 2325, + 2334 + ] + }, + { + "chunk_id": "chunk_e2552b54", + "text": "The cacheability of a memory region should not affect the software view of the region except for differences reflected in other PMAs, such as main memory versus I/O classification, memory ordering, supported accesses and atomic operations, and coherence.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Coherence and Cacheability PMAs", + "confidence": "medium", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 2371, + 2376 + ] + }, + { + "chunk_id": "chunk_df341b31", + "text": "Where a platform supports configurable cacheability settings for a memory region, a platform-specific machine-mode routine will change the settings and flush caches if necessary, so the system is only incoherent during the transition between cacheability settings.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Coherence and Cacheability PMAs", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 2378, + 2382 + ] + }, + { + "chunk_id": "chunk_5c7fec53", + "text": "This transitory state should not be visible to lower privilege levels.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Coherence and Cacheability PMAs", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 2378, + 2382 + ] + }, + { + "chunk_id": "chunk_97d0b08a", + "text": "If a PMA indicates non-cacheability, then accesses to that region must be satisfied by the memory itself, not by any caches.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Coherence and Cacheability PMAs", + "confidence": "very_high", + "parameter_class": "SW_rule", + "parameter_type": "binary", + "line_range": [ + 2384, + 2385 + ] + }, + { + "chunk_id": "chunk_27164f05", + "text": "If accesses are non-idempotent, i.e., there is potentially a side effect on any read or write access, then speculative or redundant accesses must be avoided.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Idempotency PMAs", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 2389, + 2394 + ] + }, + { + "chunk_id": "chunk_3d3b8d47", + "text": "For non-idempotent regions, implicit reads and writes must not be performed early or speculatively, with the following exceptions.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Idempotency PMAs", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 2400, + 2413 + ] + }, + { + "chunk_id": "chunk_36b74aa7", + "text": "The results of these additional reads may be used to satisfy subsequent early or speculative implicit reads.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Idempotency PMAs", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 2400, + 2413 + ] + }, + { + "chunk_id": "chunk_9cfc895a", + "text": "The size of these naturally aligned power-of-2 regions is implementation-defined, but, for systems with page-based virtual memory, must not exceed the smallest supported page size.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Idempotency PMAs", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 2400, + 2413 + ] + }, + { + "chunk_id": "chunk_02c83330", + "text": "To support secure processing and contain faults, it is desirable to limit the physical addresses accessible by software running on a hart.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 2418, + 2424 + ] + }, + { + "chunk_id": "chunk_cfb7ad97", + "text": "PMP checks are applied to all accesses whose effective privilege mode is S or U, including instruction fetches and data accesses in S and U mode, and data accesses in M-mode when the MPRV bit in `mstatus` is set and the MPP field in `mstatus` contains S or U. PMP checks are also applied to page-table accesses for virtual-address translation, for which the effective privilege mode is S.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 2432, + 2442 + ] + }, + { + "chunk_id": "chunk_d07a7e9c", + "text": "Optionally, PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection", + "confidence": "medium", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 2432, + 2442 + ] + }, + { + "chunk_id": "chunk_fbcd883c", + "text": "In effect, PMP can grant permissions to S and U modes, which by default have none, and can revoke permissions from M-mode, which by default has full permissions.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2432, + 2442 + ] + }, + { + "chunk_id": "chunk_66a4b598", + "text": "PMP violations are always trapped precisely at the processor.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2444, + 2444 + ] + }, + { + "chunk_id": "chunk_39adcd66", + "text": "PMP entries are described by an 8-bit configuration register and one MXLEN-bit address register.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 2448, + 2454 + ] + }, + { + "chunk_id": "chunk_c7415812", + "text": "Some PMP settings additionally use the address register associated with the preceding PMP entry.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2448, + 2454 + ] + }, + { + "chunk_id": "chunk_37be932e", + "text": "Up to 64 PMP entries are supported.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2448, + 2454 + ] + }, + { + "chunk_id": "chunk_b0840b21", + "text": "Implementations may implement zero, 16, or 64 PMP entries; the lowest-numbered PMP entries must be implemented first.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 2448, + 2454 + ] + }, + { + "chunk_id": "chunk_315d20eb", + "text": "All PMP CSR fields are *WARL* and may be read-only zero. PMP CSRs are only accessible to M-mode.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 2448, + 2454 + ] + }, + { + "chunk_id": "chunk_d3babf96", + "text": "The PMP configuration registers are densely packed into CSRs to minimize context-switch time.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 2456, + 2464 + ] + }, + { + "chunk_id": "chunk_b88f7218", + "text": "For RV32, sixteen CSRs, `pmpcfg0`\u2013`pmpcfg15`, hold the configurations `pmp0cfg`\u2013`pmp63cfg` for the 64 PMP entries, as shown in .", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 2456, + 2464 + ] + }, + { + "chunk_id": "chunk_c910668e", + "text": "For RV64, eight even-numbered CSRs, `pmpcfg0`, `pmpcfg2`, \u2026, `pmpcfg14`, hold the configurations for the 64 PMP entries, as shown in .", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 2456, + 2464 + ] + }, + { + "chunk_id": "chunk_029134cb", + "text": "For RV64, the odd-numbered configuration registers, `pmpcfg1`, `pmpcfg3`, \u2026, `pmpcfg15`, are illegal.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 2456, + 2464 + ] + }, + { + "chunk_id": "chunk_c33146c3", + "text": "The PMP address registers are CSRs named `pmpaddr0`-`pmpaddr63`.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 2474, + 2480 + ] + }, + { + "chunk_id": "chunk_b10d3bfe", + "text": "Each PMP address register encodes bits 33-2 of a 34-bit physical address for RV32, as shown in .", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 2474, + 2480 + ] + }, + { + "chunk_id": "chunk_a7037147", + "text": "For RV64, each PMP address register encodes bits 55-2 of a 56-bit physical address, as shown in .", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 2474, + 2480 + ] + }, + { + "chunk_id": "chunk_f3d4cf8f", + "text": "Not all physical address bits may be implemented, and so the `pmpaddr` registers are *WARL*.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 2474, + 2480 + ] + }, + { + "chunk_id": "chunk_8f6c8459", + "text": "shows the layout of a PMP configuration register.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2490, + 2495 + ] + }, + { + "chunk_id": "chunk_bb75a842", + "text": "The R, W, and X bits, when set, indicate that the PMP entry permits read, write, and instruction execution, respectively.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2490, + 2495 + ] + }, + { + "chunk_id": "chunk_17fe049a", + "text": "When one of these bits is clear, the corresponding access type is denied.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 2490, + 2495 + ] + }, + { + "chunk_id": "chunk_4fdb3d75", + "text": "The R, W, and X fields form a collective *WARL* field for which the combinations with R=0 and W=1 are reserved.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 2490, + 2495 + ] + }, + { + "chunk_id": "chunk_e187dd03", + "text": "The remaining two fields, A and L, are described in the following sections.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 2490, + 2495 + ] + }, + { + "chunk_id": "chunk_b7e0171b", + "text": "Attempting to fetch an instruction from a PMP region that does not have execute permissions raises an instruction access-fault exception.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 2501, + 2508 + ] + }, + { + "chunk_id": "chunk_044bc19c", + "text": "Attempting to execute a load, load-reserved, or cache-block management instruction which accesses a physical address within a PMP region without read permissions raises a load access-fault exception.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 2501, + 2508 + ] + }, + { + "chunk_id": "chunk_df8eacd0", + "text": "Attempting to execute a store, store-conditional, AMO, or cache-block zero instruction which accesses a physical address within a PMP region without write permissions raises a store access-fault exception.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 2501, + 2508 + ] + }, + { + "chunk_id": "chunk_b225f014", + "text": "The A field in a PMP entry's configuration register encodes the address-matching mode of the associated PMP address register.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Address Matching", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 2514, + 2521 + ] + }, + { + "chunk_id": "chunk_be99f1eb", + "text": "The encoding of this field is shown in .", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Address Matching", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 2514, + 2521 + ] + }, + { + "chunk_id": "chunk_589b512e", + "text": "When A=0, this PMP entry is disabled and matches no addresses.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Address Matching", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 2514, + 2521 + ] + }, + { + "chunk_id": "chunk_2c0aad10", + "text": "Two other address-matching modes are supported: naturally aligned power-of-2 regions (NAPOT), including the special case of naturally aligned four-byte regions (NA4); and the top boundary of an arbitrary range (TOR).", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Address Matching", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2514, + 2521 + ] + }, + { + "chunk_id": "chunk_1f3345ca", + "text": "These modes support four-byte granularity.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Address Matching", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2514, + 2521 + ] + }, + { + "chunk_id": "chunk_2b93d05a", + "text": "NAPOT ranges make use of the low-order bits of the associated address register to encode the size of the range, as shown in .", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Address Matching", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2543, + 2545 + ] + }, + { + "chunk_id": "chunk_6cbd5943", + "text": "If TOR is selected, the associated address register forms the top of the address range, and the preceding PMP address register forms the bottom of the address range.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Address Matching", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 2581, + 2585 + ] + }, + { + "chunk_id": "chunk_e5722906", + "text": "If PMP entry i's A field is set to TOR, the entry matches any address y such that `pmpaddr~i-1~`{le}y<``pmpaddr~i~`` (irrespective of the value of `pmpcfg~i-1~`).", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Address Matching", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 2581, + 2585 + ] + }, + { + "chunk_id": "chunk_e8eb7f06", + "text": "If PMP entry 0's A field is set to TOR, zero is used for the lower bound, and so it matches any address `y Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Address Matching", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 2581, + 2585 + ] + }, + { + "chunk_id": "chunk_e147c61d", + "text": "Although the PMP mechanism supports regions as small as four bytes, platforms may specify coarser PMP regions.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Address Matching", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 2587, + 2602 + ] + }, + { + "chunk_id": "chunk_ed876d35", + "text": "In general, the PMP grain is 2^G+2^ bytes and must be the same across all PMP regions.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Address Matching", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 2587, + 2602 + ] + }, + { + "chunk_id": "chunk_4fb93a2b", + "text": "When G {ge} 1, the NA4 mode is not selectable.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Address Matching", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 2587, + 2602 + ] + }, + { + "chunk_id": "chunk_292e2019", + "text": "Although changing pmpcfg~i~.A[1] affects the value read from pmpaddr~i~, it does not affect the underlying value stored in that register\u2014in particular, pmpaddr~i~[G-1] retains its original value when pmpcfg~i~.A is changed from NAPOT to TOR/OFF then back to NAPOT.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Address Matching", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 2587, + 2602 + ] + }, + { + "chunk_id": "chunk_36f74c78", + "text": "Locked PMP entries remain locked until the hart is reset.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Locking and Privilege Mode", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2607, + 2612 + ] + }, + { + "chunk_id": "chunk_6aa5df8a", + "text": "If PMP entry i is locked, writes to ``pmp``i``cfg`` and ``pmpaddr``i are ignored.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Locking and Privilege Mode", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 2607, + 2612 + ] + }, + { + "chunk_id": "chunk_0876d10c", + "text": "Additionally, if PMP entry i is locked and ``pmp``i``cfg.A`` is set to TOR, writes to ``pmpaddr``i-1 are ignored.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Locking and Privilege Mode", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 2607, + 2612 + ] + }, + { + "chunk_id": "chunk_f77c4075", + "text": "In addition to locking the PMP entry, the L bit indicates whether the R/W/X permissions are additionally enforced on M-mode accesses.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Locking and Privilege Mode", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2614, + 2619 + ] + }, + { + "chunk_id": "chunk_2b3b76c0", + "text": "When the L bit is set, these permissions are enforced for all privilege modes.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Locking and Privilege Mode", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 2614, + 2619 + ] + }, + { + "chunk_id": "chunk_56ab5df8", + "text": "When the L bit is clear, any M-mode access matching the PMP entry will succeed; the R/W/X permissions apply only to S and U modes.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Locking and Privilege Mode", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2614, + 2619 + ] + }, + { + "chunk_id": "chunk_4a738f29", + "text": "On some implementations, misaligned loads, stores, and instruction fetches may be decomposed into multiple memory operations, some of which may succeed before an access-fault exception occurs, as described in the RVWMO specification. PMP checking is performed on each memory operation independently.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Priority and Matching Logic", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 2623, + 2630 + ] + }, + { + "chunk_id": "chunk_a77473e2", + "text": "In particular, a portion of a misaligned store that passes the PMP check may become visible, even if another portion fails the PMP check.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Priority and Matching Logic", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 2623, + 2630 + ] + }, + { + "chunk_id": "chunk_10ce2509", + "text": "PMP entries are statically prioritized.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Priority and Matching Logic", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2632, + 2639 + ] + }, + { + "chunk_id": "chunk_63aa1c7a", + "text": "The lowest-numbered PMP entry that matches any byte of a memory operation determines whether that operation succeeds or fails.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Priority and Matching Logic", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2632, + 2639 + ] + }, + { + "chunk_id": "chunk_56fef4bd", + "text": "The matching PMP entry must match all bytes of a memory operation, or the operation fails, irrespective of the L, R, W, and X bits.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Priority and Matching Logic", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 2632, + 2639 + ] + }, + { + "chunk_id": "chunk_d334ea0d", + "text": "If a PMP entry matches all bytes of a memory operation, then the L, R, W, and X bits determine whether the operation succeeds or fails.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Priority and Matching Logic", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2641, + 2646 + ] + }, + { + "chunk_id": "chunk_9f8880aa", + "text": "If the L bit is clear and the privilege mode of the access is M, the operation succeeds.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Priority and Matching Logic", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 2641, + 2646 + ] + }, + { + "chunk_id": "chunk_207b6df6", + "text": "Otherwise, if the L bit is set or the privilege mode of the access is S or U, then the operation succeeds only if the R, W, or X bit corresponding to the access type is set.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Priority and Matching Logic", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 2641, + 2646 + ] + }, + { + "chunk_id": "chunk_f8e9da60", + "text": "If no PMP entry matches an M-mode memory operation, the operation succeeds.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Priority and Matching Logic", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2648, + 2650 + ] + }, + { + "chunk_id": "chunk_a0fe55e7", + "text": "If no PMP entry matches an S-mode or U-mode memory operation, but at least one PMP entry is implemented, the operation fails.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Priority and Matching Logic", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "range", + "line_range": [ + 2648, + 2650 + ] + }, + { + "chunk_id": "chunk_8eeaa6dd", + "text": "Failed memory operations generate an instruction, load, or store access-fault exception.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Priority and Matching Logic", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2652, + 2658 + ] + }, + { + "chunk_id": "chunk_4efc87e7", + "text": "An access-fault exception is generated if at least one memory operation generated by an instruction fails, though other memory operations generated by that instruction may succeed with visible side effects.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Priority and Matching Logic", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 2652, + 2658 + ] + }, + { + "chunk_id": "chunk_74d14c90", + "text": "Notably, instructions that reference virtual memory are decomposed into multiple memory operations.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Priority and Matching Logic", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2652, + 2658 + ] + }, + { + "chunk_id": "chunk_fb9695f4", + "text": "When paging is enabled, instructions that access virtual memory may result in multiple physical-memory accesses, including implicit references to the page tables.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection and Paging", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 2664, + 2670 + ] + }, + { + "chunk_id": "chunk_9df68475", + "text": "The PMP settings for the resulting physical address may be checked (and possibly cached) at any point between the address translation and the explicit memory access.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection and Paging", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 2672, + 2685 + ] + }, + { + "chunk_id": "chunk_fcd39486", + "text": "Hence, when the PMP settings are modified, M-mode software must synchronize the PMP settings with the virtual memory system and any PMP or address-translation caches.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection and Paging", + "confidence": "very_high", + "parameter_class": "SW_rule", + "parameter_type": "binary", + "line_range": [ + 2672, + 2685 + ] + }, + { + "chunk_id": "chunk_491400db", + "text": "This is accomplished by executing an SFENCE.VMA instruction with rs1=`x0` and rs2=`x0`, after the PMP CSRs are written.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection and Paging", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 2672, + 2685 + ] + }, + { + "chunk_id": "chunk_a3728ac9", + "text": "See for additional synchronization requirements when the hypervisor extension is implemented.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection and Paging", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 2672, + 2685 + ] + }, + { + "chunk_id": "chunk_d385b92d", + "text": "If page-based virtual memory is not implemented, memory accesses check the PMP settings synchronously, so no SFENCE.VMA is needed.", + "source_file": "src/priv/machine.adoc", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection and Paging", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 2687, + 2688 + ] + } + ] + }, + { + "file": "src/priv/preface.adoc", + "chunks": [ + { + "chunk_id": "chunk_b6092f08", + "text": "Defined the `misa`.B field to reflect that the B extension has been implemented. * Defined the `misa`.V field to reflect that the V extension has been implemented. * Defined the RV32-only `medelegh` and `hedelegh` CSRs. * Defined the misaligned atomicity granule PMA, superseding the proposed Zam extension. * Allocated interrupt 13 for Sscofpmf LCOFI interrupt. * Defined hardware-error and software-check exception codes. * Specified synchronization requirements when changing the PBMTE and ADUE fields in `menvcfg` and `henvcfg`. * Exposed count-overflow interrupts to VS-mode via the Shlcofideleg extension. * Relaxed behavior of some HINTs when MXLEN > XLEN. * Defined the format of the memory-mapped `msip` registers.", + "source_file": "src/priv/preface.adoc", + "section": "Preamble > Preface", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 233, + 246 + ] + }, + { + "chunk_id": "chunk_b84b62b5", + "text": "The previous specification implied that PPO rules other than fences and acquire/release annotations did not apply. * Constrained the LR/SC reservation set size and shape when using page-based virtual memory. * PMP changes require an SFENCE.VMA on any hart that implements page-based virtual memory, even if VM is not currently enabled. * Allowed for speculative updates of page table entry A bits. * Clarify that if the address-translation algorithm non-speculatively reaches a PTE in which a bit reserved for future standard use is set, a page-fault exception must be raised.", + "source_file": "src/priv/preface.adoc", + "section": "Preamble > Preface", + "confidence": "very_high", + "parameter_class": "SW_rule", + "parameter_type": "binary", + "line_range": [ + 291, + 305 + ] + }, + { + "chunk_id": "chunk_4bf4c453", + "text": "Removed the N extension. * Defined the mandatory RV32-only CSR `mstatush`, which contains most of the same fields as the upper 32 bits of RV64\u2019s `mstatus`. * Defined the mandatory CSR `mconfigptr`, which if nonzero contains the address of a configuration data structure. * Defined `mseccfg` and `mseccfgh` CSRs, which control the machine\u2019s security configuration. * Defined `menvcfg`, `henvcfg`, and `senvcfg` CSRs (and RV32-only `menvcfgh` and `henvcfgh` CSRs), which control various characteristics of the execution environment. * Designated part of SYSTEM major opcode for custom use. * Permitted the unconditional delegation of less-privileged interrupts. * Added optional big-endian and bi-endian support. * Made priority of load/store/AMO address-misaligned exceptions implementation-defined relative to load/store/AMO page-fault and access-fault exceptions. * PMP reset values are now platform-defined. * An additional 48 optional PMP registers have been defined. * Slightly relaxed the atomicity requirement for A and D bit updates performed by the implementation. * Clarify the architectural behavior of address-translation caches * Added Sv57 and Sv57x4 address translation modes. * Software breakpoint exceptions are permitted to write either 0 or the `pc` to `xtval`. * Clarified that bare S-mode need not support the SFENCE.VMA instruction. * Specified relaxed constraints for implicit reads of non-idempotent regions. * Added the Svnapot Standard Extension, along with the N bit in Sv39, Sv48, and Sv57 PTEs. * Added the Svpbmt Standard Extension, along with the PBMT bits in Sv39, Sv48, and Sv57 PTEs. * Added the Svinval Standard Extension and associated instructions.", + "source_file": "src/priv/preface.adoc", + "section": "Preamble > Preface", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 310, + 342 + ] + }, + { + "chunk_id": "chunk_e57d1083", + "text": "The encoding space has been reserved and may be repurposed at a later date. * A mechanism to improve virtualization performance by trapping S-mode virtual-memory management operations has been added. * The Supervisor Binary Interface (SBI) chapter has been removed, so that it can be maintained as a separate specification.", + "source_file": "src/priv/preface.adoc", + "section": "Preamble > Preface", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 399, + 455 + ] + }, + { + "chunk_id": "chunk_efd41272", + "text": "Numerous additions and improvements to the commentary sections. * Change configuration string proposal to be use a search process that supports various formats including Device Tree String and flattened Device Tree. * Made `misa` optionally writable to support modifying base and supported ISA extensions. CSR address of `misa` changed. * Added description of debug mode and debug CSRs. * Added a hardware performance monitoring scheme.", + "source_file": "src/priv/preface.adoc", + "section": "Preamble > Preface", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 462, + 472 + ] + } + ] + }, + { + "file": "src/priv/rationale.adoc", + "chunks": [ + { + "chunk_id": "chunk_6b04766d", + "text": "Since a CSR for security and / or global PMP behavior settings is not available with the current spec, we needed to define a new `mseccfg` CSR.", + "source_file": "src/priv/rationale.adoc", + "section": "Preamble > Historical Rationale for Extensions > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 17, + 17 + ] + }, + { + "chunk_id": "chunk_935cb5e2", + "text": "This new CSR will allow us to add further security configuration options in the future and also allow developers to verify the existence of the new mechanisms defined on this extension.", + "source_file": "src/priv/rationale.adoc", + "section": "Preamble > Historical Rationale for Extensions > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 17, + 17 + ] + }, + { + "chunk_id": "chunk_58464ad0", + "text": "This is a waste of PMP rules and since it\u2019s only needed during boot, ``mseccfg.RLB`` is a simple workaround that can be used temporarily and then disabled and locked down. + Also when ``mseccfg.MML`` is set, according to 4b it\u2019s not possible to add a Shared-Region rule with executable privileges.", + "source_file": "src/priv/rationale.adoc", + "section": "Preamble > Historical Rationale for Extensions > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 19, + 32 + ] + }, + { + "chunk_id": "chunk_300be726", + "text": "If developers / vendors have no use for such functionality, they should never set ``mseccfg.RLB`` and if possible hard-wire it to 0.", + "source_file": "src/priv/rationale.adoc", + "section": "Preamble > Historical Rationale for Extensions > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 19, + 32 + ] + }, + { + "chunk_id": "chunk_ac7e0ee8", + "text": "In any case *RLB should be disabled and locked as soon as possible*. + + [IMPORTANT] Since PMP rules with a higher priority override rules with a lower priority, locked rules must precede non-locked rules.", + "source_file": "src/priv/rationale.adoc", + "section": "Preamble > Historical Rationale for Extensions > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 19, + 32 + ] + }, + { + "chunk_id": "chunk_8c7ab6c7", + "text": "With the current spec M-mode can access any memory region unless restricted by a PMP rule with the ``pmpcfg.L`` bit set.", + "source_file": "src/priv/rationale.adoc", + "section": "Preamble > Historical Rationale for Extensions > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 34, + 34 + ] + }, + { + "chunk_id": "chunk_350815ba", + "text": "Having the option to block anything by default, and use PMP as an allowlist for M-mode is considered a safer approach.", + "source_file": "src/priv/rationale.adoc", + "section": "Preamble > Historical Rationale for Extensions > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 34, + 34 + ] + }, + { + "chunk_id": "chunk_3a4d7f68", + "text": "This functionality may be used during the boot process or upon *PMP reset*, using initial register settings. +", + "source_file": "src/priv/rationale.adoc", + "section": "Preamble > Historical Rationale for Extensions > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 34, + 34 + ] + }, + { + "chunk_id": "chunk_89dfbe07", + "text": "The current dual meaning of the ``pmpcfg.L`` bit that marks a rule as Locked and *enforced* on all modes is neither flexible nor clean.", + "source_file": "src/priv/rationale.adoc", + "section": "Preamble > Historical Rationale for Extensions > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 36, + 36 + ] + }, + { + "chunk_id": "chunk_0342c8ec", + "text": "With the introduction of Machine Mode Lock-down the ``pmpcfg.L`` bit distinguishes between rules that are *enforced* *only* in M-mode (M-mode-only) or *only* in S/U-modes (S/U-mode-only).", + "source_file": "src/priv/rationale.adoc", + "section": "Preamble > Historical Rationale for Extensions > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 36, + 36 + ] + }, + { + "chunk_id": "chunk_af1423d0", + "text": "The rule locking becomes part of the definition of an M-mode-only rule, since when a rule is added in M mode, if not locked, can be modified or removed in a few instructions.", + "source_file": "src/priv/rationale.adoc", + "section": "Preamble > Historical Rationale for Extensions > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 36, + 36 + ] + }, + { + "chunk_id": "chunk_2e78e7bf", + "text": "This separation between M-mode-only and S/U-mode-only rules also allows us to distinguish which regions are to be used by processes in Machine mode (``pmpcfg.L 1``) and which by Supervisor or User mode processes (``pmpcfg.L 0``), in the same way the U bit on the Virtual Memory\u2019s PTEs marks which Virtual Memory pages are to be used by User mode applications (U=1) and which by the Supervisor / OS (U=0).", + "source_file": "src/priv/rationale.adoc", + "section": "Preamble > Historical Rationale for Extensions > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 38, + 42 + ] + }, + { + "chunk_id": "chunk_34f5a83a", + "text": "With this distinction in place we are able to implement memory access and execution prevention in M-mode for any physical memory region that is not M-mode-only. + An attacker that manages to tamper with a memory region used by S/U mode, even after successfully tricking a process running in M-mode to use or execute that region, will fail to perform a successful attack since that region will be S/U-mode-only hence any access when in M-mode will trigger an access exception. + +", + "source_file": "src/priv/rationale.adoc", + "section": "Preamble > Historical Rationale for Extensions > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 38, + 42 + ] + }, + { + "chunk_id": "chunk_9b8de246", + "text": "This is similar to the vDSO approach followed on Linux, that allows user space code to execute kernel code without having to perform a system call. + To make sure that shared data regions can\u2019t be executed and shared code regions can\u2019t be modified, the encoding changes the meaning of the ``pmpcfg.X bit``.", + "source_file": "src/priv/rationale.adoc", + "section": "Preamble > Historical Rationale for Extensions > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 44, + 51 + ] + }, + { + "chunk_id": "chunk_e6a2f20e", + "text": "In case of shared data regions, with the exception of the ``pmpcfg.LRWX=1111`` encoding, the ``pmpcfg.X`` bit marks the capability of S/U-mode to write to that region, so it\u2019s not possible to encode an executable shared data region.", + "source_file": "src/priv/rationale.adoc", + "section": "Preamble > Historical Rationale for Extensions > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 44, + 51 + ] + }, + { + "chunk_id": "chunk_f3468413", + "text": "In case of shared code regions, the ``pmpcfg.X`` bit marks the capability of M-mode to read from that region, and since ``pmpcfg.RW=01`` is used for encoding the shared region, it\u2019s not possible to encode a shared writable code region. + + + ..", + "source_file": "src/priv/rationale.adoc", + "section": "Preamble > Historical Rationale for Extensions > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 44, + 51 + ] + }, + { + "chunk_id": "chunk_7e181d60", + "text": "Since we want to limit the attack surface of the system as much as possible, it makes sense to disallow any new code regions which may include malicious code, to be added/executed in M-mode.", + "source_file": "src/priv/rationale.adoc", + "section": "Preamble > Historical Rationale for Extensions > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 44, + 51 + ] + }, + { + "chunk_id": "chunk_e0c0cd63", + "text": "We are only using the encoding ``pmpcfg.RW=01`` together with ``mseccfg.MML``, if ``mseccfg.MML`` is not set the encoding remains usable for future use.", + "source_file": "src/priv/rationale.adoc", + "section": "Preamble > Historical Rationale for Extensions > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 55, + 55 + ] + } + ] + }, + { + "file": "src/priv/shcounterenw.adoc", + "chunks": [ + { + "chunk_id": "chunk_2ec682e0", + "text": "If the Shcounterenw extension is implemented, then for any `hpmcounter` that is not read-only zero, the corresponding bit in `hcounteren` must be writable.", + "source_file": "src/priv/shcounterenw.adoc", + "section": "Preamble > Shcounterenw Extension for Counter-Enable Writability, Version 1.0", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 3, + 4 + ] + } + ] + }, + { + "file": "src/priv/shgatpa.adoc", + "chunks": [ + { + "chunk_id": "chunk_e037e8ad", + "text": "If the Shgatpa extension is implemented, then for each supported virtual memory scheme SvNN supported in `satp`, the corresponding hgatp SvNNx4 mode must be supported.", + "source_file": "src/priv/shgatpa.adoc", + "section": "Preamble > Shgatpa Extension for Translation Mode Support, Version 1.0", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 3, + 6 + ] + }, + { + "chunk_id": "chunk_0044086f", + "text": "Furthermore, the `hgatp` mode Bare must also be supported.", + "source_file": "src/priv/shgatpa.adoc", + "section": "Preamble > Shgatpa Extension for Translation Mode Support, Version 1.0", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 3, + 6 + ] + } + ] + }, + { + "file": "src/priv/shtvala.adoc", + "chunks": [ + { + "chunk_id": "chunk_382de062", + "text": "If the Shtvala extension is implemented, `htval` must be written with the faulting guest physical address in all circumstances permitted by the ISA.", + "source_file": "src/priv/shtvala.adoc", + "section": "Preamble > Shtvala Extension for Trap Value Reporting, Version 1.0", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 3, + 4 + ] + } + ] + }, + { + "file": "src/priv/shvsatpa.adoc", + "chunks": [ + { + "chunk_id": "chunk_43523cc0", + "text": "If the Shvsatpa extension is implemented, all translation modes supported in `satp` must be supported in `vsatp`.", + "source_file": "src/priv/shvsatpa.adoc", + "section": "Preamble > Shvsatpa Extension for Translation Mode Support, Version 1.0", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 3, + 4 + ] + } + ] + }, + { + "file": "src/priv/shvstvala.adoc", + "chunks": [ + { + "chunk_id": "chunk_ccce9266", + "text": "If the Shvstvala extension is implemented, `vstval` must be written in all cases described in for `stval`.", + "source_file": "src/priv/shvstvala.adoc", + "section": "Preamble > Shvstvala Extension for Trap Value Reporting, Version 1.0", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 3, + 4 + ] + } + ] + }, + { + "file": "src/priv/shvstvecd.adoc", + "chunks": [ + { + "chunk_id": "chunk_3b1276de", + "text": "If the Shvstvecd extension is implemented, then `vstvec.MODE` must be capable of holding the value 0 (Direct).", + "source_file": "src/priv/shvstvecd.adoc", + "section": "Preamble > Shvstvecd Extension for Direct Trap Vectoring, Version 1.0", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 3, + 6 + ] + }, + { + "chunk_id": "chunk_3c2beeae", + "text": "Furthermore, when `vstvec.MODE`=Direct, `vstvec.BASE` must be capable of holding any valid four-byte-aligned address.", + "source_file": "src/priv/shvstvecd.adoc", + "section": "Preamble > Shvstvecd Extension for Direct Trap Vectoring, Version 1.0", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 3, + 6 + ] + } + ] + }, + { + "file": "src/priv/smcdeleg.adoc", + "chunks": [ + { + "chunk_id": "chunk_83134a3e", + "text": "Counters may be configured with differing scopes, in some cases counting events system-wide, while in others counting events on behalf of a single virtual machine or application.", + "source_file": "src/priv/smcdeleg.adoc", + "section": "Preamble > \"Smcdeleg/Ssccfg\" Counter Delegation Extensions, Version 1.0", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 3, + 9 + ] + }, + { + "chunk_id": "chunk_e74fe235", + "text": "These extensions also defines one new CSR, scountinhibit.", + "source_file": "src/priv/smcdeleg.adoc", + "section": "Preamble > \"Smcdeleg/Ssccfg\" Counter Delegation Extensions, Version 1.0", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 16, + 20 + ] + }, + { + "chunk_id": "chunk_e4ca12e3", + "text": "For a Machine-level environment, extension *Smcdeleg* (\u2018Sm\u2019 for Privileged architecture and Machine-level extension, \u2018cdeleg\u2019 for Counter Delegation) encompasses all added CSRs and all behavior modifications for a hart, over all privilege levels.", + "source_file": "src/priv/smcdeleg.adoc", + "section": "Preamble > \"Smcdeleg/Ssccfg\" Counter Delegation Extensions, Version 1.0", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 22, + 29 + ] + }, + { + "chunk_id": "chunk_62671138", + "text": "For a Supervisor-level environment, extension *Ssccfg* (\u2018Ss\u2019 for Privileged architecture and Supervisor-level extension, \u2018ccfg\u2019 for Counter Configuration) provides access to delegated counters, and to new supervisor-level state.For a RISC-V hardware platform, Smcdeleg and Ssccfg must always be implemented in tandem.", + "source_file": "src/priv/smcdeleg.adoc", + "section": "Preamble > \"Smcdeleg/Ssccfg\" Counter Delegation Extensions, Version 1.0", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 22, + 29 + ] + }, + { + "chunk_id": "chunk_49857356", + "text": "The Smcdeleg and Ssccfg extensions both depend on the Sscsrind extension.", + "source_file": "src/priv/smcdeleg.adoc", + "section": "Preamble > \"Smcdeleg/Ssccfg\" Counter Delegation Extensions, Version 1.0", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 31, + 31 + ] + }, + { + "chunk_id": "chunk_4aa7cee0", + "text": "The `mcounteren` register allows M-mode to provide the next-lower privilege mode with read access to select counters.", + "source_file": "src/priv/smcdeleg.adoc", + "section": "Preamble > \"Smcdeleg/Ssccfg\" Counter Delegation Extensions, Version 1.0 > Counter Delegation", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 35, + 36 + ] + }, + { + "chunk_id": "chunk_dcb1006e", + "text": "When the Smcdeleg/Ssccfg extensions are enabled (`menvcfg`.CDE=1), it further allows M-mode to delegate select counters to S-mode.", + "source_file": "src/priv/smcdeleg.adoc", + "section": "Preamble > \"Smcdeleg/Ssccfg\" Counter Delegation Extensions, Version 1.0 > Counter Delegation", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 35, + 36 + ] + }, + { + "chunk_id": "chunk_878ae6ef", + "text": "The counter state accessible via alias CSRs is shown in the table below.", + "source_file": "src/priv/smcdeleg.adoc", + "section": "Preamble > \"Smcdeleg/Ssccfg\" Counter Delegation Extensions, Version 1.0 > Counter Delegation", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 38, + 43 + ] + }, + { + "chunk_id": "chunk_748f83d3", + "text": "`hpmeventi` may represent a subset of the state accessed by the `mhpmeventi` register.", + "source_file": "src/priv/smcdeleg.adoc", + "section": "Preamble > \"Smcdeleg/Ssccfg\" Counter Delegation Extensions, Version 1.0 > Counter Delegation", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 63, + 64 + ] + }, + { + "chunk_id": "chunk_10c5066c", + "text": "Specifically, if Sscofpmf is implemented, event selector bit 62 (MINH) is read-only 0 when accessed through `sireg*`.", + "source_file": "src/priv/smcdeleg.adoc", + "section": "Preamble > \"Smcdeleg/Ssccfg\" Counter Delegation Extensions, Version 1.0 > Counter Delegation", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 63, + 64 + ] + }, + { + "chunk_id": "chunk_5f477f61", + "text": "Likewise, `cyclecfg` and `instretcfg` may represent a subset of the state accessed by the `mcyclecfg` and `minstretcfg` registers, respectively.", + "source_file": "src/priv/smcdeleg.adoc", + "section": "Preamble > \"Smcdeleg/Ssccfg\" Counter Delegation Extensions, Version 1.0 > Counter Delegation", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 66, + 67 + ] + }, + { + "chunk_id": "chunk_ce83bbfc", + "text": "If Smcntrpmf is implemented, counter configuration register bit 62 (MINH) is read-only 0 when accessed through `sireg*`.", + "source_file": "src/priv/smcdeleg.adoc", + "section": "Preamble > \"Smcdeleg/Ssccfg\" Counter Delegation Extensions, Version 1.0 > Counter Delegation", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "unknown", + "line_range": [ + 66, + 67 + ] + }, + { + "chunk_id": "chunk_6f1ab629", + "text": "If extension Smstateen is implemented, refer to extensions Smcsrind/Sscsrind () for how setting bit 60 of CSR `mstateen0` to zero prevents access to registers `siselect`, `sireg*`, `vsiselect`, and `vsireg*` from privileged modes less privileged than M-mode, and likewise how setting bit 60 of `hstateen0` to zero prevents access to `siselect` and `sireg*` (really `vsiselect` and `vsireg*`) from VS-mode.", + "source_file": "src/priv/smcdeleg.adoc", + "section": "Preamble > \"Smcdeleg/Ssccfg\" Counter Delegation Extensions, Version 1.0 > Counter Delegation", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 69, + 74 + ] + }, + { + "chunk_id": "chunk_f6f3bd57", + "text": "The remaining rules of this section apply only when access to a CSR is not blocked by `mstateen0`[60] = 0 or `hstateen0`[60] = 0.", + "source_file": "src/priv/smcdeleg.adoc", + "section": "Preamble > \"Smcdeleg/Ssccfg\" Counter Delegation Extensions, Version 1.0 > Counter Delegation", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 76, + 77 + ] + }, + { + "chunk_id": "chunk_6db73c0a", + "text": "While the privilege mode is M or S and `siselect` holds a value in the range 0x40-0x5F, illegal-instruction exceptions are raised for the following cases:", + "source_file": "src/priv/smcdeleg.adoc", + "section": "Preamble > \"Smcdeleg/Ssccfg\" Counter Delegation Extensions, Version 1.0 > Counter Delegation", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 79, + 81 + ] + }, + { + "chunk_id": "chunk_fc355b31", + "text": "attempts to access any `sireg*` when `menvcfg`.CDE = 0; * attempts to access `sireg3` or `sireg6`; * attempts to access `sireg4` or `sireg5` when XLEN = 64; * attempts to access `sireg*` when `siselect` = 0x41, or when the counter selected by `siselect` is not delegated to S-mode (the corresponding bit in `mcounteren` = 0).", + "source_file": "src/priv/smcdeleg.adoc", + "section": "Preamble > \"Smcdeleg/Ssccfg\" Counter Delegation Extensions, Version 1.0 > Counter Delegation", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 83, + 88 + ] + }, + { + "chunk_id": "chunk_c32f9869", + "text": "If any extension upon which the underlying state depends is not implemented, an attempt from M or S mode to access the given state through `sireg*` raises an illegal-instruction exception.", + "source_file": "src/priv/smcdeleg.adoc", + "section": "Preamble > \"Smcdeleg/Ssccfg\" Counter Delegation Extensions, Version 1.0 > Counter Delegation", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 94, + 96 + ] + }, + { + "chunk_id": "chunk_d610cf5e", + "text": "If the hypervisor (H) extension is also implemented, then as specified by extensions Smcsrind/Sscsrind, a virtual-instruction exception is raised for attempts from VS-mode or VU-mode to directly access `vsiselect` or `vsireg*`, or attempts from VU-mode to access `siselect` or `sireg*`.", + "source_file": "src/priv/smcdeleg.adoc", + "section": "Preamble > \"Smcdeleg/Ssccfg\" Counter Delegation Extensions, Version 1.0 > Counter Delegation", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 98, + 102 + ] + }, + { + "chunk_id": "chunk_48900364", + "text": "An attempt to access any `vsireg*` from M or S mode raises an illegal-instruction exception. * An attempt from VS-mode to access any `sireg*` (really `vsireg*`) raises an illegal-instruction exception if `menvcfg`.CDE = 0, or a virtual-instruction exception if `menvcfg`.CDE = 1.", + "source_file": "src/priv/smcdeleg.adoc", + "section": "Preamble > \"Smcdeleg/Ssccfg\" Counter Delegation Extensions, Version 1.0 > Counter Delegation", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 104, + 105 + ] + }, + { + "chunk_id": "chunk_fd5c0600", + "text": "Smcdeleg/Ssccfg defines a new `scountinhibit` register, a masked alias of `mcountinhibit`.", + "source_file": "src/priv/smcdeleg.adoc", + "section": "Preamble > \"Smcdeleg/Ssccfg\" Counter Delegation Extensions, Version 1.0 > Counter Delegation > Supervisor Counter Inhibit (`scountinhibit`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 109, + 109 + ] + }, + { + "chunk_id": "chunk_ca239e01", + "text": "For counters delegated to S-mode, the associated `mcountinhibit` bits can be accessed via `scountinhibit`.For counters not delegated to S-mode, the associated bits in `scountinhibit` are read-only zero.", + "source_file": "src/priv/smcdeleg.adoc", + "section": "Preamble > \"Smcdeleg/Ssccfg\" Counter Delegation Extensions, Version 1.0 > Counter Delegation > Supervisor Counter Inhibit (`scountinhibit`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 109, + 109 + ] + }, + { + "chunk_id": "chunk_279d9af9", + "text": "When `menvcfg`.CDE=0, attempts to access `scountinhibit` raise an illegal-instruction exception.", + "source_file": "src/priv/smcdeleg.adoc", + "section": "Preamble > \"Smcdeleg/Ssccfg\" Counter Delegation Extensions, Version 1.0 > Counter Delegation > Supervisor Counter Inhibit (`scountinhibit`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 111, + 113 + ] + }, + { + "chunk_id": "chunk_db81802b", + "text": "When Supervisor Counter Delegation is enabled, attempts to access `scountinhibit` from VS-mode or VU-mode raise a virtual-instruction exception.", + "source_file": "src/priv/smcdeleg.adoc", + "section": "Preamble > \"Smcdeleg/Ssccfg\" Counter Delegation Extensions, Version 1.0 > Counter Delegation > Supervisor Counter Inhibit (`scountinhibit`) Register", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 111, + 113 + ] + }, + { + "chunk_id": "chunk_ecf8e9ed", + "text": "For implementations that support Smcdeleg/Ssccfg, Sscofpmf, and the H extension, when `menvcfg`.CDE=1, attempts to read `scountovf` from VS-mode or VU-mode raise a virtual-instruction exception.", + "source_file": "src/priv/smcdeleg.adoc", + "section": "Preamble > \"Smcdeleg/Ssccfg\" Counter Delegation Extensions, Version 1.0 > Counter Delegation > Virtualizing `scountovf`", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 118, + 121 + ] + }, + { + "chunk_id": "chunk_c7ac1bbc", + "text": "For implementations that support Smcdeleg, Sscofpmf, and Smaia, the local-counter-overflow interrupt (LCOFI) bit (bit 13) in each of CSRs `mvip` and `mvien` is implemented and writable.", + "source_file": "src/priv/smcdeleg.adoc", + "section": "Preamble > \"Smcdeleg/Ssccfg\" Counter Delegation Extensions, Version 1.0 > Counter Delegation > Virtualizing Local-Counter-Overflow Interrupts", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 125, + 128 + ] + }, + { + "chunk_id": "chunk_fd5d0c71", + "text": "For implementations that support Smcdeleg/Ssccfg, Sscofpmf, Smaia/Ssaia, and the H extension, the LCOFI bit (bit 13) in each of `hvip` and `hvien` is implemented and writable.", + "source_file": "src/priv/smcdeleg.adoc", + "section": "Preamble > \"Smcdeleg/Ssccfg\" Counter Delegation Extensions, Version 1.0 > Counter Delegation > Virtualizing Local-Counter-Overflow Interrupts", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "unknown", + "line_range": [ + 130, + 133 + ] + } + ] + }, + { + "file": "src/priv/smcntrpmf.adoc", + "chunks": [ + { + "chunk_id": "chunk_d0c03ac9", + "text": "mcyclecfg and minstretcfg are 64-bit registers that configure privilege mode filtering for the cycle and instret counters, respectively.", + "source_file": "src/priv/smcntrpmf.adoc", + "section": "Preamble > \"Smcntrpmf\" Cycle and Instret Privilege Mode Filtering, Version 1.0 > Introduction > CSRs > Machine Counter Configuration (`mcyclecfg`, `minstretcfg`) Registers", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 17, + 17 + ] + }, + { + "chunk_id": "chunk_00dba3fc", + "text": "[cols=\"^1,^1,^1,^1,^1,^1,^5\",stripes=even,options=\"header\"] | |63 |62 |61 |60 |59 |58 |57:0 |0 |MINH |SINH |UINH |VSINH |VUINH |WPRI |", + "source_file": "src/priv/smcntrpmf.adoc", + "section": "Preamble > \"Smcntrpmf\" Cycle and Instret Privilege Mode Filtering, Version 1.0 > Introduction > CSRs > Machine Counter Configuration (`mcyclecfg`, `minstretcfg`) Registers", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 19, + 23 + ] + }, + { + "chunk_id": "chunk_18b409dc", + "text": "[cols=\"15%,85%\",options=\"header\"] | | Field | Description | MINH |", + "source_file": "src/priv/smcntrpmf.adoc", + "section": "Preamble > \"Smcntrpmf\" Cycle and Instret Privilege Mode Filtering, Version 1.0 > Introduction > CSRs > Machine Counter Configuration (`mcyclecfg`, `minstretcfg`) Registers", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 25, + 33 + ] + }, + { + "chunk_id": "chunk_e666e66f", + "text": "If set, then counting of events in M-mode is inhibited | SINH |", + "source_file": "src/priv/smcntrpmf.adoc", + "section": "Preamble > \"Smcntrpmf\" Cycle and Instret Privilege Mode Filtering, Version 1.0 > Introduction > CSRs > Machine Counter Configuration (`mcyclecfg`, `minstretcfg`) Registers", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 25, + 33 + ] + }, + { + "chunk_id": "chunk_38ac7f97", + "text": "If set, then counting of events in S/HS-mode is inhibited | UINH |", + "source_file": "src/priv/smcntrpmf.adoc", + "section": "Preamble > \"Smcntrpmf\" Cycle and Instret Privilege Mode Filtering, Version 1.0 > Introduction > CSRs > Machine Counter Configuration (`mcyclecfg`, `minstretcfg`) Registers", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 25, + 33 + ] + }, + { + "chunk_id": "chunk_6e5f5b35", + "text": "If set, then counting of events in U-mode is inhibited | VSINH |", + "source_file": "src/priv/smcntrpmf.adoc", + "section": "Preamble > \"Smcntrpmf\" Cycle and Instret Privilege Mode Filtering, Version 1.0 > Introduction > CSRs > Machine Counter Configuration (`mcyclecfg`, `minstretcfg`) Registers", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 25, + 33 + ] + }, + { + "chunk_id": "chunk_9ed49eda", + "text": "If set, then counting of events in VS-mode is inhibited | VUINH |", + "source_file": "src/priv/smcntrpmf.adoc", + "section": "Preamble > \"Smcntrpmf\" Cycle and Instret Privilege Mode Filtering, Version 1.0 > Introduction > CSRs > Machine Counter Configuration (`mcyclecfg`, `minstretcfg`) Registers", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 25, + 33 + ] + }, + { + "chunk_id": "chunk_d239895c", + "text": "If set, then counting of events in VU-mode is inhibited |", + "source_file": "src/priv/smcntrpmf.adoc", + "section": "Preamble > \"Smcntrpmf\" Cycle and Instret Privilege Mode Filtering, Version 1.0 > Introduction > CSRs > Machine Counter Configuration (`mcyclecfg`, `minstretcfg`) Registers", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 25, + 33 + ] + }, + { + "chunk_id": "chunk_d57e784f", + "text": "When all xINH bits are zero, event counting is enabled in all modes.", + "source_file": "src/priv/smcntrpmf.adoc", + "section": "Preamble > \"Smcntrpmf\" Cycle and Instret Privilege Mode Filtering, Version 1.0 > Introduction > CSRs > Machine Counter Configuration (`mcyclecfg`, `minstretcfg`) Registers", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 35, + 35 + ] + }, + { + "chunk_id": "chunk_9762522c", + "text": "For each bit in 61:58, if the associated privilege mode is not implemented, the bit is read-only zero.", + "source_file": "src/priv/smcntrpmf.adoc", + "section": "Preamble > \"Smcntrpmf\" Cycle and Instret Privilege Mode Filtering, Version 1.0 > Introduction > CSRs > Machine Counter Configuration (`mcyclecfg`, `minstretcfg`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 37, + 37 + ] + }, + { + "chunk_id": "chunk_3554f327", + "text": "For RV32, bits 63:32 of mcyclecfg can be accessed via the mcyclecfgh CSR, and bits 63:32 of minstretcfg can be accessed via the minstretcfgh CSR.", + "source_file": "src/priv/smcntrpmf.adoc", + "section": "Preamble > \"Smcntrpmf\" Cycle and Instret Privilege Mode Filtering, Version 1.0 > Introduction > CSRs > Machine Counter Configuration (`mcyclecfg`, `minstretcfg`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 39, + 39 + ] + }, + { + "chunk_id": "chunk_22201705", + "text": "The content of these registers may be accessible from Supervisor level if the Smcdeleg/Ssccfg extensions are implemented.", + "source_file": "src/priv/smcntrpmf.adoc", + "section": "Preamble > \"Smcntrpmf\" Cycle and Instret Privilege Mode Filtering, Version 1.0 > Introduction > CSRs > Machine Counter Configuration (`mcyclecfg`, `minstretcfg`) Registers", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 41, + 41 + ] + }, + { + "chunk_id": "chunk_f10a10c9", + "text": "Mode transition operations (traps and trap returns) may take multiple clock cycles, and the change of privilege mode may be reported as occurring in any one of those cycles (possibly different for each occurrence of a trap or trap return).", + "source_file": "src/priv/smcntrpmf.adoc", + "section": "Preamble > \"Smcntrpmf\" Cycle and Instret Privilege Mode Filtering, Version 1.0 > Introduction > Counter Behavior", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 48, + 49 + ] + }, + { + "chunk_id": "chunk_12eecd33", + "text": "There are two types of instructions that can affect a privilege mode change: instructions that cause synchronous exceptions to a more privileged mode, and xRET instructions that return to a less privileged mode.", + "source_file": "src/priv/smcntrpmf.adoc", + "section": "Preamble > \"Smcntrpmf\" Cycle and Instret Privilege Mode Filtering, Version 1.0 > Introduction > Counter Behavior", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 51, + 52 + ] + }, + { + "chunk_id": "chunk_34a84a41", + "text": "The latter do retire, and should increment instret only if the originating privilege mode is not inhibited.", + "source_file": "src/priv/smcntrpmf.adoc", + "section": "Preamble > \"Smcntrpmf\" Cycle and Instret Privilege Mode Filtering, Version 1.0 > Introduction > Counter Behavior", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 51, + 52 + ] + } + ] + }, + { + "file": "src/priv/smcsrind.adoc", + "chunks": [ + { + "chunk_id": "chunk_99412fe5", + "text": "Smcsrind/Sscsrind is an ISA extension that extends the indirect CSR access mechanism originally defined as part of the https://github.com/riscv/riscv-aia[[.underline]Smaia/Ssaia extensions], in order to make it available for use by other extensions without creating an unnecessary dependence on Smaia/Ssaia.", + "source_file": "src/priv/smcsrind.adoc", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 5, + 9 + ] + }, + { + "chunk_id": "chunk_2dcada5e", + "text": "It provides a means to access an array of registers via CSRs without requiring allocation of large chunks of the limited CSR address space.", + "source_file": "src/priv/smcsrind.adoc", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 13, + 14 + ] + }, + { + "chunk_id": "chunk_442f8c71", + "text": "It enables software to access each of an array of registers by index, without requiring a switch statement with a case for each register.", + "source_file": "src/priv/smcsrind.adoc", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 16, + 17 + ] + }, + { + "chunk_id": "chunk_410c7637", + "text": "The machine-level extension *Smcsrind* encompasses all added CSRs and all behavior modifications for a hart, over all privilege levels.", + "source_file": "src/priv/smcsrind.adoc", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 19, + 24 + ] + }, + { + "chunk_id": "chunk_7a181ac2", + "text": "For a supervisor-level environment, extension *Sscsrind* is essentially the same as Smcsrind except excluding the machine-level CSRs and behavior not directly visible to supervisor level.", + "source_file": "src/priv/smcsrind.adoc", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 19, + 24 + ] + }, + { + "chunk_id": "chunk_8b8b93ed", + "text": "[width=\"100%\",cols=\"15%,12%,12%,15%,46%\",options=\"header\",] | |*Number* |*Privilege* |*Width* |*Name* |*Description* |0x350 |MRW |XLEN |`miselect` |Machine indirect register select |0x351 |MRW |XLEN |`mireg` |Machine indirect register alias |0x352 |MRW |XLEN |`mireg2` |Machine indirect register alias 2 |0x353 |MRW |XLEN |`mireg3` |Machine indirect register alias 3 |0x355 |MRW |XLEN |`mireg4` |Machine indirect register alias 4 |0x356 |MRW |XLEN |`mireg5` |Machine indirect register alias 5 |0x357 |MRW |XLEN |`mireg6` |Machine indirect register alias 6 |", + "source_file": "src/priv/smcsrind.adoc", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Machine-level CSRs", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 29, + 39 + ] + }, + { + "chunk_id": "chunk_4807eaa9", + "text": "The CSRs listed in the table above provide a window for accessing register state indirectly.", + "source_file": "src/priv/smcsrind.adoc", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Machine-level CSRs", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 41, + 48 + ] + }, + { + "chunk_id": "chunk_a42124f7", + "text": "The value of `miselect` determines which register is accessed upon read or write of each of the machine indirect alias CSRs (`mireg*`). `miselect` value ranges are allocated to dependent extensions, which specify the register state accessible via each `miregi` register, for each `miselect` value. `miselect` is a WARL register.", + "source_file": "src/priv/smcsrind.adoc", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Machine-level CSRs", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 41, + 48 + ] + }, + { + "chunk_id": "chunk_1a8ce64a", + "text": "The `miselect` register implements at least enough bits to support all implemented `miselect` values (corresponding to the implemented extensions that utilize `miselect`/`mireg*` to indirectly access register state).", + "source_file": "src/priv/smcsrind.adoc", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Machine-level CSRs", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "range", + "line_range": [ + 50, + 54 + ] + }, + { + "chunk_id": "chunk_e777efac", + "text": "The `miselect` register may be read-only zero if there are no extensions implemented that utilize it.", + "source_file": "src/priv/smcsrind.adoc", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Machine-level CSRs", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 50, + 54 + ] + }, + { + "chunk_id": "chunk_0ee28202", + "text": "Values of `miselect` with the most-significant bit set (bit XLEN - 1 = 1) are designated only for custom use, presumably for accessing custom registers through the alias CSRs.", + "source_file": "src/priv/smcsrind.adoc", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Machine-level CSRs", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 56, + 63 + ] + }, + { + "chunk_id": "chunk_6c4d9909", + "text": "Values of `miselect` with the most-significant bit clear are designated only for standard use and are reserved until allocated to a standard architecture extension.", + "source_file": "src/priv/smcsrind.adoc", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Machine-level CSRs", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 56, + 63 + ] + }, + { + "chunk_id": "chunk_3f2cfa85", + "text": "If XLEN is changed, the most-significant bit of `miselect` moves to the new position, retaining its value from before.", + "source_file": "src/priv/smcsrind.adoc", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Machine-level CSRs", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 56, + 63 + ] + }, + { + "chunk_id": "chunk_af8c65b2", + "text": "The behavior upon accessing `mireg*` from M-mode, while `miselect` holds a value that is not implemented, is UNSPECIFIED.", + "source_file": "src/priv/smcsrind.adoc", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Machine-level CSRs", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 65, + 67 + ] + }, + { + "chunk_id": "chunk_28d8c52c", + "text": "Attempts to access `mireg*` while `miselect` holds a number in an allocated and implemented range results in a specific behavior that, for each combination of `miselect` and `miregi`, is defined by the extension to which the `miselect` value is allocated.", + "source_file": "src/priv/smcsrind.adoc", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Machine-level CSRs", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 69, + 74 + ] + }, + { + "chunk_id": "chunk_99378fd8", + "text": "[width=\"100%\",cols=\"15%,12%,12%,15%,46%\",options=\"header\",] | |*Number* |*Privilege* |*Width* |*Name* |*Description* |0x150 |SRW |XLEN |`siselect` |Supervisor indirect register select |0x151 |SRW |XLEN |`sireg` |Supervisor indirect register alias |0x152 |SRW |XLEN |`sireg2` |Supervisor indirect register alias 2 |0x153 |SRW |XLEN |`sireg3` |Supervisor indirect register alias 3 |0x155 |SRW |XLEN |`sireg4` |Supervisor indirect register alias 4 |0x156 |SRW |XLEN |`sireg5` |Supervisor indirect register alias 5 |0x157 |SRW |XLEN |`sireg6` |Supervisor indirect register alias 6 |", + "source_file": "src/priv/smcsrind.adoc", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Supervisor-level CSRs", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 80, + 90 + ] + }, + { + "chunk_id": "chunk_c6334109", + "text": "The CSRs in the table above are required if S-mode is implemented.", + "source_file": "src/priv/smcsrind.adoc", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Supervisor-level CSRs", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 92, + 92 + ] + }, + { + "chunk_id": "chunk_01318e78", + "text": "The `siselect` register will support the value range 0..0xFFF at a minimum. A future extension may define a value range outside of this minimum range.", + "source_file": "src/priv/smcsrind.adoc", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Supervisor-level CSRs", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 94, + 97 + ] + }, + { + "chunk_id": "chunk_ec84c31f", + "text": "Only if such an extension is implemented will `siselect` be required to support larger values.", + "source_file": "src/priv/smcsrind.adoc", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Supervisor-level CSRs", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 94, + 97 + ] + }, + { + "chunk_id": "chunk_da50edfe", + "text": "Values of `siselect` with the most-significant bit set (bit XLEN - 1 = 1) are designated only for custom use, presumably for accessing custom registers through the alias CSRs.", + "source_file": "src/priv/smcsrind.adoc", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Supervisor-level CSRs", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 99, + 107 + ] + }, + { + "chunk_id": "chunk_fee5dcb5", + "text": "Values of `siselect` with the most-significant bit clear are designated only for standard use and are reserved until allocated to a standard architecture extension.", + "source_file": "src/priv/smcsrind.adoc", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Supervisor-level CSRs", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 99, + 107 + ] + }, + { + "chunk_id": "chunk_f5e7c146", + "text": "If XLEN is changed, the most-significant bit of `siselect` moves to the new position, retaining its value from before.", + "source_file": "src/priv/smcsrind.adoc", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Supervisor-level CSRs", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 99, + 107 + ] + }, + { + "chunk_id": "chunk_19c0635f", + "text": "The behavior upon accessing `sireg*` from M-mode or S-mode, while `siselect` holds a value that is not implemented at supervisor level, is UNSPECIFIED.", + "source_file": "src/priv/smcsrind.adoc", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Supervisor-level CSRs", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 109, + 111 + ] + }, + { + "chunk_id": "chunk_3572442b", + "text": "Otherwise, attempts to access `sireg*` from M-mode or S-mode while `siselect` holds a number in a standard-defined and implemented range result in specific behavior that, for each combination of `siselect` and `siregi`, is defined by the extension to which the `siselect` value is allocated.", + "source_file": "src/priv/smcsrind.adoc", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Supervisor-level CSRs", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 113, + 120 + ] + }, + { + "chunk_id": "chunk_55e2d6ea", + "text": "[width=\"100%\",cols=\"15%,12%,12%,15%,46%\",options=\"header\",] | |*Number* |*Privilege* |*Width* |*Name* |*Description* |0x250 |HRW |XLEN |`vsiselect` |Virtual supervisor indirect register select", + "source_file": "src/priv/smcsrind.adoc", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Virtual Supervisor-level CSRs", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 132, + 136 + ] + }, + { + "chunk_id": "chunk_0d3ddfcb", + "text": "|0x251 |HRW |XLEN |`vsireg` |Virtual supervisor indirect register alias", + "source_file": "src/priv/smcsrind.adoc", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Virtual Supervisor-level CSRs", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 138, + 138 + ] + }, + { + "chunk_id": "chunk_f151bffa", + "text": "|0x252 |HRW |XLEN |`vsireg2` |Virtual supervisor indirect register alias 2", + "source_file": "src/priv/smcsrind.adoc", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Virtual Supervisor-level CSRs", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 140, + 140 + ] + }, + { + "chunk_id": "chunk_e02e17c8", + "text": "|0x253 |HRW |XLEN |`vsireg3` |Virtual supervisor indirect register alias 3", + "source_file": "src/priv/smcsrind.adoc", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Virtual Supervisor-level CSRs", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 142, + 142 + ] + }, + { + "chunk_id": "chunk_e246e3d7", + "text": "|0x255 |HRW |XLEN |`vsireg4` |Virtual supervisor indirect register alias 4", + "source_file": "src/priv/smcsrind.adoc", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Virtual Supervisor-level CSRs", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 144, + 144 + ] + }, + { + "chunk_id": "chunk_50427e6b", + "text": "|0x256 |HRW |XLEN |`vsireg5` |Virtual supervisor indirect register alias 5", + "source_file": "src/priv/smcsrind.adoc", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Virtual Supervisor-level CSRs", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 146, + 146 + ] + }, + { + "chunk_id": "chunk_dae53d26", + "text": "|0x257 |HRW |XLEN |`vsireg6` |Virtual supervisor indirect register alias 6 |", + "source_file": "src/priv/smcsrind.adoc", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Virtual Supervisor-level CSRs", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 148, + 149 + ] + }, + { + "chunk_id": "chunk_0aed0a37", + "text": "The CSRs in the table above are required if the hypervisor extension is implemented.", + "source_file": "src/priv/smcsrind.adoc", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Virtual Supervisor-level CSRs", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 151, + 154 + ] + }, + { + "chunk_id": "chunk_1e9a6115", + "text": "These VS CSRs all match supervisor CSRs, and substitute for those supervisor CSRs when executing in a virtual machine (in VS-mode or VU-mode).", + "source_file": "src/priv/smcsrind.adoc", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Virtual Supervisor-level CSRs", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 151, + 154 + ] + }, + { + "chunk_id": "chunk_bb5e326c", + "text": "The `vsiselect` register will support the value range 0..0xFFF at a minimum. A future extension may define a value range outside of this minimum range.", + "source_file": "src/priv/smcsrind.adoc", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Virtual Supervisor-level CSRs", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 156, + 159 + ] + }, + { + "chunk_id": "chunk_d82fd6b3", + "text": "Only if such an extension is implemented will `vsiselect` be required to support larger values.", + "source_file": "src/priv/smcsrind.adoc", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Virtual Supervisor-level CSRs", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 156, + 159 + ] + }, + { + "chunk_id": "chunk_4e5ad7f5", + "text": "Values of `vsiselect` with the most-significant bit set (bit XLEN - 1 = 1) are designated only for custom use, presumably for accessing custom registers through the alias CSRs.", + "source_file": "src/priv/smcsrind.adoc", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Virtual Supervisor-level CSRs", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 161, + 169 + ] + }, + { + "chunk_id": "chunk_a048db28", + "text": "Values of `vsiselect` with the most-significant bit clear are designated only for standard use and are reserved until allocated to a standard architecture extension.", + "source_file": "src/priv/smcsrind.adoc", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Virtual Supervisor-level CSRs", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 161, + 169 + ] + }, + { + "chunk_id": "chunk_8229a054", + "text": "If XLEN is changed, the most-significant bit of `vsiselect` moves to the new position, retaining its value from before.", + "source_file": "src/priv/smcsrind.adoc", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Virtual Supervisor-level CSRs", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 161, + 169 + ] + }, + { + "chunk_id": "chunk_f3121074", + "text": "For alias CSRs `sireg*` and `vsireg*`, the hypervisor extension\u2019s usual rules for when to raise a virtual-instruction exception (based on whether an instruction is HS-qualified) are not applicable.", + "source_file": "src/priv/smcsrind.adoc", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Virtual Supervisor-level CSRs", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 171, + 177 + ] + }, + { + "chunk_id": "chunk_f67ac4da", + "text": "The rules given in this section for `sireg` and `vsireg` apply instead, unless overridden by the requirements specified in the section below, which take precedence over this section when extension Smstateen is also implemented.", + "source_file": "src/priv/smcsrind.adoc", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Virtual Supervisor-level CSRs", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 171, + 177 + ] + }, + { + "chunk_id": "chunk_69b8f6cf", + "text": "A virtual-instruction exception is raised for attempts from VS-mode or VU-mode to directly access `vsiselect` or `vsireg*`, or attempts from VU-mode to access `siselect` or `sireg*`.", + "source_file": "src/priv/smcsrind.adoc", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Virtual Supervisor-level CSRs", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 179, + 180 + ] + }, + { + "chunk_id": "chunk_dd05e6ac", + "text": "The behavior upon accessing `vsireg*` from M-mode or HS-mode, or accessing `sireg*` (really `vsireg*`) from VS-mode, while `vsiselect` holds a value that is not implemented at HS level, is UNSPECIFIED.", + "source_file": "src/priv/smcsrind.adoc", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Virtual Supervisor-level CSRs", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 182, + 182 + ] + }, + { + "chunk_id": "chunk_223ce912", + "text": "Otherwise, while `vsiselect` holds a number in a standard-defined and implemented range, attempts to access `vsireg*` from a sufficiently privileged mode, or to access `sireg*` (really `vsireg*`) from VS-mode, result in specific behavior that, for each combination of `vsiselect` and `vsiregi`, is defined by the extension to which the `vsiselect` value is allocated.", + "source_file": "src/priv/smcsrind.adoc", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Virtual Supervisor-level CSRs", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 184, + 191 + ] + }, + { + "chunk_id": "chunk_7c91d130", + "text": "Like `siselect` and `sireg*`, the widths of `vsiselect` and `vsireg*` are always the current XLEN rather than VSXLEN.", + "source_file": "src/priv/smcsrind.adoc", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Virtual Supervisor-level CSRs", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 193, + 199 + ] + }, + { + "chunk_id": "chunk_9e12b56b", + "text": "If extension Smstateen is implemented together with Smcsrind, bit 60 of state-enable register `mstateen0` controls access to `siselect`, `sireg*`, `vsiselect`, and `vsireg*`.", + "source_file": "src/priv/smcsrind.adoc", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Access control by the state-enable CSRs", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 203, + 210 + ] + }, + { + "chunk_id": "chunk_2f75b3b7", + "text": "When `mstateen0`[60]=0, an attempt to access one of these CSRs from a privilege mode less privileged than M-mode results in an illegal-instruction exception.", + "source_file": "src/priv/smcsrind.adoc", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Access control by the state-enable CSRs", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 203, + 210 + ] + }, + { + "chunk_id": "chunk_43fca7cc", + "text": "As always, the state-enable CSRs do not affect the accessibility of any state when in M-mode, only in less privileged modes.", + "source_file": "src/priv/smcsrind.adoc", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Access control by the state-enable CSRs", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 203, + 210 + ] + }, + { + "chunk_id": "chunk_b5d92640", + "text": "For more explanation, see the documentation for extension Smstateen in .", + "source_file": "src/priv/smcsrind.adoc", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Access control by the state-enable CSRs", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 203, + 210 + ] + }, + { + "chunk_id": "chunk_887c1d5a", + "text": "Other extensions may specify that certain mstateen bits control access to registers accessed indirectly through `siselect` + `sireg*`, and/or `vsiselect` + `vsireg*`.", + "source_file": "src/priv/smcsrind.adoc", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Access control by the state-enable CSRs", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 212, + 218 + ] + }, + { + "chunk_id": "chunk_58994864", + "text": "If the hypervisor extension is implemented, the same bit is defined also in hypervisor CSR `hstateen0`, but controls access to only `siselect` and `sireg*` (really `vsiselect` and `vsireg*`), which is the state potentially accessible to a virtual machine executing in VS or VU-mode.", + "source_file": "src/priv/smcsrind.adoc", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Access control by the state-enable CSRs", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 220, + 228 + ] + }, + { + "chunk_id": "chunk_29894ed4", + "text": "When `hstateen0`[60]=0 and `mstateen0`[60]=1, all attempts from VS or VU-mode to access `siselect` or `sireg*` raise a virtual-instruction exception, not an illegal-instruction exception, regardless of the value of `vsiselect` or any other mstateen bit.", + "source_file": "src/priv/smcsrind.adoc", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Access control by the state-enable CSRs", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 220, + 228 + ] + }, + { + "chunk_id": "chunk_93de1157", + "text": "Extension Ssstateen is defined as the supervisor-level view of Smstateen.", + "source_file": "src/priv/smcsrind.adoc", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Access control by the state-enable CSRs", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 230, + 233 + ] + }, + { + "chunk_id": "chunk_5fc36007", + "text": "Therefore, the combination of Sscsrind and Ssstateen incorporates the bit defined above for `hstateen0` but not that for `mstateen0`, since machine-level CSRs are not visible to supervisor level.", + "source_file": "src/priv/smcsrind.adoc", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Access control by the state-enable CSRs", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 230, + 233 + ] + } + ] + }, + { + "file": "src/priv/smctr.adoc", + "chunks": [ + { + "chunk_id": "chunk_f9b020e1", + "text": "Control flow transfers refer to jump instructions (including function calls and returns), taken branch instructions, traps, and trap returns.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 4, + 4 + ] + }, + { + "chunk_id": "chunk_790bd387", + "text": "Profiling tools, such as Linux perf, collect control transfer history when sampling software execution, thereby enabling tools, like AutoFDO, to identify hot paths for optimization.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 4, + 4 + ] + }, + { + "chunk_id": "chunk_41eae867", + "text": "Recorded transfers are inserted at the write pointer, which is then incremented, while older recorded transfers may be overwritten once the buffer is full.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 12, + 12 + ] + }, + { + "chunk_id": "chunk_e153672e", + "text": "The CTR buffer is accessible through an indirect CSR interface, such that software can specify which logical entry in the buffer it wishes to read or write.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 14, + 14 + ] + }, + { + "chunk_id": "chunk_1f1c0f5c", + "text": "The machine-level extension, *Smctr*, encompasses all newly added Control Status Registers (CSRs), instructions, and behavior modifications for a hart across all privilege levels.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 16, + 16 + ] + }, + { + "chunk_id": "chunk_a8861305", + "text": "Smctr and Ssctr depend on both the implementation of S-mode and the Sscsrind extension.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 18, + 18 + ] + }, + { + "chunk_id": "chunk_ba0955c4", + "text": "The `mctrctl` register is a 64-bit read/write register that enables and configures the CTR capability.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`)", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 24, + 24 + ] + }, + { + "chunk_id": "chunk_bb8c826e", + "text": "|RASEMU |Enables RAS (Return Address Stack) Emulation Mode.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 68, + 68 + ] + }, + { + "chunk_id": "chunk_a96a8a01", + "text": "|MTE |Enables recording of traps to M-mode when M=0.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 70, + 70 + ] + }, + { + "chunk_id": "chunk_2592483c", + "text": "|STE |Enables recording of traps to S-mode when S=0.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 72, + 72 + ] + }, + { + "chunk_id": "chunk_be3c8962", + "text": "|BPFRZ |Set `sctrstatus`.FROZEN on a breakpoint exception that traps to M-mode or S-mode.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 74, + 74 + ] + }, + { + "chunk_id": "chunk_af59dbda", + "text": "|LCOFIFRZ |Set `sctrstatus`.FROZEN on local-counter-overflow interrupt (LCOFI) that traps to M-mode or S-mode.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 76, + 76 + ] + }, + { + "chunk_id": "chunk_45f46ff7", + "text": "|EXCINH |Inhibit recording of exceptions.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 78, + 78 + ] + }, + { + "chunk_id": "chunk_79b24ba1", + "text": "|INTRINH |Inhibit recording of interrupts.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 80, + 80 + ] + }, + { + "chunk_id": "chunk_11ad52e8", + "text": "|TRETINH |Inhibit recording of trap returns.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 82, + 82 + ] + }, + { + "chunk_id": "chunk_ddcaabb5", + "text": "|NTBREN |Enable recording of not-taken branches.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 84, + 84 + ] + }, + { + "chunk_id": "chunk_6280ad1c", + "text": "|TKBRINH |Inhibit recording of taken branches.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 86, + 86 + ] + }, + { + "chunk_id": "chunk_43b14103", + "text": "|INDCALLINH |Inhibit recording of indirect calls.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 88, + 88 + ] + }, + { + "chunk_id": "chunk_ad2ce281", + "text": "|DIRCALLINH |Inhibit recording of direct calls.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 90, + 90 + ] + }, + { + "chunk_id": "chunk_92691a1d", + "text": "|INDJMPINH |Inhibit recording of indirect jumps (without linkage).", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 92, + 92 + ] + }, + { + "chunk_id": "chunk_128826e0", + "text": "|DIRJMPINH |Inhibit recording of direct jumps (without linkage).", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 94, + 94 + ] + }, + { + "chunk_id": "chunk_87cd7f1d", + "text": "|CORSWAPINH |Inhibit recording of co-routine swaps.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 96, + 96 + ] + }, + { + "chunk_id": "chunk_672bad5c", + "text": "|RETINH |Inhibit recording of function returns.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 98, + 98 + ] + }, + { + "chunk_id": "chunk_9c2c23c5", + "text": "|INDLJMPINH |Inhibit recording of other indirect jumps (with linkage).", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 100, + 100 + ] + }, + { + "chunk_id": "chunk_253b70fc", + "text": "|DIRLJMPINH |Inhibit recording of other direct jumps (with linkage).", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 102, + 104 + ] + }, + { + "chunk_id": "chunk_65789fe1", + "text": "The value 0 must correspond to standard behavior.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`)", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 102, + 104 + ] + }, + { + "chunk_id": "chunk_6be88f73", + "text": "-- All fields are optional except for M, S, U, and BPFRZ.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 106, + 109 + ] + }, + { + "chunk_id": "chunk_70cc9fe4", + "text": "All unimplemented fields are read-only 0, while all implemented fields are writable.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`)", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 106, + 109 + ] + }, + { + "chunk_id": "chunk_09dd034b", + "text": "If the Sscofpmf extension is implemented, LCOFIFRZ must be writable. --", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`)", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 106, + 109 + ] + }, + { + "chunk_id": "chunk_ea73c3e5", + "text": "The `sctrctl` register provides supervisor mode access to a subset of `mctrctl`.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Control Register (`sctrctl`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 113, + 113 + ] + }, + { + "chunk_id": "chunk_b0efef86", + "text": "Bits 2 and 9 in `sctrctl` are read-only 0.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Control Register (`sctrctl`)", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "unknown", + "line_range": [ + 115, + 115 + ] + }, + { + "chunk_id": "chunk_207f07ec", + "text": "As a result, the M and MTE fields in `mctrctl` are not accessible through `sctrctl`.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Control Register (`sctrctl`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 115, + 115 + ] + }, + { + "chunk_id": "chunk_7d718fb6", + "text": "All other `mctrctl` fields are accessible through `sctrctl`.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Control Register (`sctrctl`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 115, + 115 + ] + }, + { + "chunk_id": "chunk_d61a1e7b", + "text": "If the H extension is implemented, the `vsctrctl` register is a 64-bit read/write register that is VS-mode's version of supervisor register `sctrctl`.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Virtual Supervisor Control Transfer Records Control Register (`vsctrctl`)", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 119, + 119 + ] + }, + { + "chunk_id": "chunk_ad34e144", + "text": "When V=1, `vsctrctl` substitutes for the usual `sctrctl`, so instructions that normally read or modify `sctrctl` actually access `vsctrctl` instead.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Virtual Supervisor Control Transfer Records Control Register (`vsctrctl`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 119, + 119 + ] + }, + { + "chunk_id": "chunk_b21b52f2", + "text": "The optional fields implemented in `vsctrctl` should match those implemented in `sctrctl`. |", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Virtual Supervisor Control Transfer Records Control Register (`vsctrctl`)", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 154, + 165 + ] + }, + { + "chunk_id": "chunk_70a0279e", + "text": "[NOTE] Unlike the CTR status register or the CTR entry registers, the CTR control register has a VS-mode version.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Virtual Supervisor Control Transfer Records Control Register (`vsctrctl`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 167, + 171 + ] + }, + { + "chunk_id": "chunk_c2a13761", + "text": "The 32-bit `sctrdepth` register specifies the depth of the CTR buffer.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Depth Register (`sctrdepth`)", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 175, + 176 + ] + }, + { + "chunk_id": "chunk_87032c87", + "text": "The depth of the CTR buffer dictates the number of entries to which the hardware records transfers.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Depth Register (`sctrdepth`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 207, + 207 + ] + }, + { + "chunk_id": "chunk_9761bce1", + "text": "For a depth of N, the hardware records transfers to entries 0..N-1.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Depth Register (`sctrdepth`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 207, + 207 + ] + }, + { + "chunk_id": "chunk_25a75b38", + "text": "All read as '0' and are read-only when the selected entry is in the range N to 255.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Depth Register (`sctrdepth`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "range", + "line_range": [ + 207, + 207 + ] + }, + { + "chunk_id": "chunk_65865305", + "text": "When the depth is increased, the newly accessible entries contain unspecified but legal values.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Depth Register (`sctrdepth`)", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 207, + 207 + ] + }, + { + "chunk_id": "chunk_ba33e58d", + "text": "It is implementation-specific which DEPTH value(s) are supported. |", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Depth Register (`sctrdepth`)", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 209, + 210 + ] + }, + { + "chunk_id": "chunk_eee848d0", + "text": "Attempts to access `sctrdepth` from VS-mode or VU-mode raise a virtual-instruction exception, unless CTR state enable access restrictions apply.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Depth Register (`sctrdepth`)", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 212, + 212 + ] + }, + { + "chunk_id": "chunk_1fe7b524", + "text": "[NOTE] It is expected that operating systems (OSs) will access `sctrdepth` only at boot, to select the maximum supported depth value.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Depth Register (`sctrdepth`)", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "range", + "line_range": [ + 214, + 217 + ] + }, + { + "chunk_id": "chunk_5eda4df6", + "text": "More frequent accesses may result in reduced performance in virtualization scenarios, as a result of traps from VS-mode incurred.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Depth Register (`sctrdepth`)", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 214, + 217 + ] + }, + { + "chunk_id": "chunk_8bfca76c", + "text": "There may be scenarios where software chooses to operate on only a subset of the entries, to reduce overhead.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Depth Register (`sctrdepth`)", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 219, + 219 + ] + }, + { + "chunk_id": "chunk_e5b4be85", + "text": "In such cases tools may choose to read only the lower entries, and OSs may choose to save/restore only on the lower entries while using SCTRCLR to clear the others.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Depth Register (`sctrdepth`)", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 219, + 219 + ] + }, + { + "chunk_id": "chunk_8c6f0d48", + "text": "The value in configurable depth lies in supporting VM migration.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Depth Register (`sctrdepth`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 221, + 222 + ] + }, + { + "chunk_id": "chunk_fbc6879f", + "text": "It is expected that a platform spec may specify that one or more CTR depth values must be supported. A hypervisor may wish to restrict guests to using one of these required depths, in order to ensure that such guests can be migrated to any system that complies with the platform spec.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Depth Register (`sctrdepth`)", + "confidence": "very_high", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 221, + 222 + ] + }, + { + "chunk_id": "chunk_b85d17aa", + "text": "The trapping behavior specified for VS-mode accesses to `sctrdepth` ensures that the hypervisor can impose such restrictions.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Depth Register (`sctrdepth`)", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 221, + 222 + ] + }, + { + "chunk_id": "chunk_09c5ec6b", + "text": "The 32-bit `sctrstatus` register grants access to CTR status information and is updated by the hardware whenever CTR is active. CTR is active when the current privilege mode is enabled for recording and CTR is not frozen.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Status Register (`sctrstatus`)", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 226, + 226 + ] + }, + { + "chunk_id": "chunk_867243fd", + "text": "For a given CTR depth (where depth = 2^(DEPTH+4)^), WRPTR wraps to 0 on an increment when the value matches depth-1, and to depth-1 on a decrement when the value is 0.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Status Register (`sctrstatus`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 239, + 246 + ] + }, + { + "chunk_id": "chunk_82899a2a", + "text": "On depth changes, WRPTR holds an unspecified but legal value. |FROZEN |Inhibit transfer recording.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Status Register (`sctrstatus`)", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 239, + 246 + ] + }, + { + "chunk_id": "chunk_39b3c0b6", + "text": "Undefined bits in `sctrstatus` are WPRI.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Status Register (`sctrstatus`)", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 248, + 249 + ] + }, + { + "chunk_id": "chunk_31a4bac6", + "text": "Status fields may be added by future extensions, and software should ignore but preserve any fields that it does not recognize.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Status Register (`sctrstatus`)", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 248, + 249 + ] + }, + { + "chunk_id": "chunk_dec9d6be", + "text": "[NOTE] Logical entry 0, accessed via `sireg*` when `siselect`=0x200, is always the physical buffer entry preceding the WRPTR entry.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Status Register (`sctrstatus`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 251, + 259 + ] + }, + { + "chunk_id": "chunk_a6f13db6", + "text": "More generally, the physical buffer entry Y associated with logical entry X (X < depth) can be determined using the formula Y = (WRPTR - X - 1) % depth, where depth = 2^(DEPTH+4)^.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Status Register (`sctrstatus`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 251, + 259 + ] + }, + { + "chunk_id": "chunk_b2664905", + "text": "Software may wish to ensure that CTR is inactive before performing a read-modify-write, by ensuring that either `sctrstatus`.FROZEN=1, or that the current privilege mode is not enabled for recording.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Status Register (`sctrstatus`)", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "binary", + "line_range": [ + 251, + 259 + ] + }, + { + "chunk_id": "chunk_60fba317", + "text": "When restoring CTR state, `sctrstatus` should be written before CTR entry state is restored.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Status Register (`sctrstatus`)", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 261, + 262 + ] + }, + { + "chunk_id": "chunk_b8770ade", + "text": "[NOTE] Exposing the WRPTR provides a more efficient means for synthesizing CTR entries.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Status Register (`sctrstatus`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 264, + 267 + ] + }, + { + "chunk_id": "chunk_b0d2ef9d", + "text": "If a qualified control transfer is emulated, the emulator can simply increment the WRPTR, then write the synthesized record to logical entry 0.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Status Register (`sctrstatus`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 264, + 267 + ] + }, + { + "chunk_id": "chunk_7bfd925b", + "text": "If a qualified function return is emulated while RASEMU=1, the emulator can clear `ctrsource`.V for logical entry 0, then decrement the WRPTR.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Status Register (`sctrstatus`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 264, + 267 + ] + }, + { + "chunk_id": "chunk_ce238fb8", + "text": "Exposing the WRPTR may also allow support for Linux perf's https://lwn.net/Articles/802821[[.underline]stack stitching] capability.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Status Register (`sctrstatus`)", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 269, + 270 + ] + }, + { + "chunk_id": "chunk_26b49422", + "text": "If, in the future, it becomes desirable to remove this dependency, an extension could add `mctrdepth` and `mctrstatus` CSRs that reflect the same state as `sctrdepth` and `sctrstatus`, respectively.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Status Register (`sctrstatus`)", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 272, + 276 + ] + }, + { + "chunk_id": "chunk_477db704", + "text": "Further, such an extension should make CTR entries accessible via `miselect`/`mireg*`.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Status Register (`sctrstatus`)", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 272, + 276 + ] + }, + { + "chunk_id": "chunk_613a7fc9", + "text": "Control transfer records are stored in a CTR buffer, such that each buffer entry stores information about a single transfer.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 280, + 280 + ] + }, + { + "chunk_id": "chunk_a7259bee", + "text": "The CTR buffer entries are logically accessed via the indirect register access mechanism defined by the Sscsrind extension.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 280, + 280 + ] + }, + { + "chunk_id": "chunk_520ac0ce", + "text": "The `siselect` index range 0x200 through 0x2FF is reserved for CTR logical entries 0 through 255.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 280, + 280 + ] + }, + { + "chunk_id": "chunk_9d5b277b", + "text": "When `siselect` holds a value in this range, `sireg` provides access to `ctrsource`, `sireg2` provides access to `ctrtarget`, and `sireg3` provides access to `ctrdata`. `sireg4`, `sireg5`, and `sireg6` are read-only 0.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 280, + 280 + ] + }, + { + "chunk_id": "chunk_26bc344e", + "text": "When `vsiselect` holds a value in 0x200..0x2FF, the `vsireg*` registers provide access to the same CTR entry register state as the analogous `sireg*` registers.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 282, + 282 + ] + }, + { + "chunk_id": "chunk_d786fc3c", + "text": "There is not a separate set of entry registers for V=1.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 282, + 282 + ] + }, + { + "chunk_id": "chunk_f308fee0", + "text": "See for cases where CTR accesses from S-mode and VS-mode may be restricted.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 284, + 284 + ] + }, + { + "chunk_id": "chunk_7b5b4b73", + "text": "The `ctrsource` register contains the source program counter, which is the `pc` of the recorded control transfer instruction, or the epc of the recorded trap.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers > Control Transfer Record Source Register (`ctrsource`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 288, + 288 + ] + }, + { + "chunk_id": "chunk_8e2ff478", + "text": "The valid (V) bit is set by the hardware when a transfer is recorded in the selected CTR buffer entry, and implies that data in `ctrsource`, `ctrtarget`, and `ctrdata` is valid for this entry.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers > Control Transfer Record Source Register (`ctrsource`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 288, + 288 + ] + }, + { + "chunk_id": "chunk_ef76ea5c", + "text": "`ctrsource` is an MXLEN-bit WARL register that must be able to hold all valid virtual or physical addresses that can serve as a `pc`.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers > Control Transfer Record Source Register (`ctrsource`)", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 290, + 290 + ] + }, + { + "chunk_id": "chunk_6939fe47", + "text": "It need not be able to hold any invalid addresses; implementations may convert an invalid address into a valid address that the register is capable of holding.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers > Control Transfer Record Source Register (`ctrsource`)", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 290, + 290 + ] + }, + { + "chunk_id": "chunk_1e3b0fcf", + "text": "When XLEN < MXLEN, both explicit writes (by software) and implicit writes (for recorded transfers) will be zero-extended.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers > Control Transfer Record Source Register (`ctrsource`)", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 290, + 290 + ] + }, + { + "chunk_id": "chunk_9fddb3ae", + "text": "[NOTE] CTR entry registers are defined as MXLEN, despite the `xireg*` CSRs used to access them being XLEN, to ensure that entries recorded in RV64 are not truncated, as a result of CSR Width Modulation, on a transition to RV32.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers > Control Transfer Record Source Register (`ctrsource`)", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 302, + 306 + ] + }, + { + "chunk_id": "chunk_765711c1", + "text": "The `ctrtarget` register contains the target (destination) program counter of the recorded transfer.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers > Control Transfer Record Target Register (`ctrtarget`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 310, + 316 + ] + }, + { + "chunk_id": "chunk_31d4fd6a", + "text": "For a not-taken branch, `ctrtarget` holds the PC of the next sequential instruction following the branch.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers > Control Transfer Record Target Register (`ctrtarget`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 310, + 316 + ] + }, + { + "chunk_id": "chunk_b3b5f3d1", + "text": "The optional MISP bit is set by the hardware when the recorded transfer is an instruction whose target or taken/not-taken direction was mispredicted by the branch predictor. MISP is read-only 0 when not implemented.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers > Control Transfer Record Target Register (`ctrtarget`)", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "unknown", + "line_range": [ + 310, + 316 + ] + }, + { + "chunk_id": "chunk_15e34b2f", + "text": "`ctrtarget` is an MXLEN-bit WARL register that must be able to hold all valid virtual or physical addresses that can serve as a `pc`.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers > Control Transfer Record Target Register (`ctrtarget`)", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 318, + 318 + ] + }, + { + "chunk_id": "chunk_70281a0a", + "text": "It need not be able to hold any invalid addresses; implementations may convert an invalid address into a valid address that the register is capable of holding.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers > Control Transfer Record Target Register (`ctrtarget`)", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 318, + 318 + ] + }, + { + "chunk_id": "chunk_7fbe9ac5", + "text": "When XLEN < MXLEN, both explicit writes (by software) and implicit writes (by recorded transfers) will be zero-extended.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers > Control Transfer Record Target Register (`ctrtarget`)", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 318, + 318 + ] + }, + { + "chunk_id": "chunk_9eca8f29", + "text": "The `ctrdata` register contains metadata for the recorded transfer.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers > Control Transfer Record Metadata Register (`ctrdata`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 333, + 335 + ] + }, + { + "chunk_id": "chunk_53b2689d", + "text": "This register must be implemented, though all fields within it are optional.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers > Control Transfer Record Metadata Register (`ctrdata`)", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 333, + 335 + ] + }, + { + "chunk_id": "chunk_abfacf16", + "text": "Unimplemented fields are read-only 0. `ctrdata` is a 64-bit register.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers > Control Transfer Record Metadata Register (`ctrdata`)", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 333, + 335 + ] + }, + { + "chunk_id": "chunk_8f50de3e", + "text": "Implementations that do not support this field will report 0. |WARL", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers > Control Transfer Record Metadata Register (`ctrdata`)", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 350, + 357 + ] + }, + { + "chunk_id": "chunk_1d7a1b92", + "text": "|CC[15:0] |Cycle Count, composed of the Cycle Count Exponent (CCE, in CC[15:12]) and Cycle Count Mantissa (CCM, in CC[11:0]).", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers > Control Transfer Record Metadata Register (`ctrdata`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 361, + 364 + ] + }, + { + "chunk_id": "chunk_f115fcb6", + "text": "Undefined bits in `ctrdata` are WPRI.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers > Control Transfer Record Metadata Register (`ctrdata`)", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 366, + 366 + ] + }, + { + "chunk_id": "chunk_8738f8a6", + "text": "Undefined bits must be implemented as read-only 0, unless a is implemented and enabled.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers > Control Transfer Record Metadata Register (`ctrdata`)", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 366, + 366 + ] + }, + { + "chunk_id": "chunk_84b7ff90", + "text": "The SCTRCLR instruction performs the following operations:", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Instructions > Supervisor CTR Clear Instruction", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 388, + 388 + ] + }, + { + "chunk_id": "chunk_6f530c6d", + "text": "Any read of `ctrsource`, `ctrtarget`, or `ctrdata` that follows SCTRCLR, such that it precedes the next qualified control transfer, will return the value 0.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Instructions > Supervisor CTR Clear Instruction", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 393, + 393 + ] + }, + { + "chunk_id": "chunk_a8cef291", + "text": "Further, the first recorded transfer following SCTRCLR will have `ctrdata`.CCV=0.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Instructions > Supervisor CTR Clear Instruction", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 393, + 393 + ] + }, + { + "chunk_id": "chunk_95dbb71b", + "text": "SCTRCLR raises an illegal-instruction exception in U-mode, and a virtual-instruction exception in VU-mode, unless CTR state enable access restrictions apply.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Instructions > Supervisor CTR Clear Instruction", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 395, + 395 + ] + }, + { + "chunk_id": "chunk_fcaad9d8", + "text": "When Smstateen is implemented, the `mstateen0`.CTR bit controls access to CTR register state from privilege modes less privileged than M-mode.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > State Enable Access Control", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 399, + 399 + ] + }, + { + "chunk_id": "chunk_252b4e51", + "text": "When `mstateen0`.CTR=1, accesses to CTR register state behave as described in and above, while SCTRCLR behaves as described in .", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > State Enable Access Control", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 399, + 399 + ] + }, + { + "chunk_id": "chunk_afa970fa", + "text": "When `mstateen0`.CTR=0 and the privilege mode is less privileged than M-mode, the following operations raise an illegal-instruction exception:", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > State Enable Access Control", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 399, + 399 + ] + }, + { + "chunk_id": "chunk_d5a87d45", + "text": "Attempts to access `sctrctl`, `vsctrctl`, `sctrdepth`, or `sctrstatus` * Attempts to access `sireg*` when `siselect` is in 0x200..0x2FF, or `vsireg*` when `vsiselect` is in 0x200..0x2FF * Execution of the SCTRCLR instruction", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > State Enable Access Control", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 401, + 403 + ] + }, + { + "chunk_id": "chunk_ea199b0b", + "text": "When `mstateen0`.CTR=0, qualified control transfers executed in privilege modes less privileged than M-mode will continue to implicitly update entry registers and `sctrstatus`.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > State Enable Access Control", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 405, + 405 + ] + }, + { + "chunk_id": "chunk_64b89ea3", + "text": "If the H extension is implemented and `mstateen0`.CTR=1, the `hstateen0`.CTR bit controls access to supervisor CTR state when V=1.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > State Enable Access Control", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 407, + 407 + ] + }, + { + "chunk_id": "chunk_e9e1bc82", + "text": "This state includes `sctrctl` (really `vsctrctl`), `sctrstatus`, and `sireg*` (really `vsireg*`) when `siselect` (really `vsiselect`) is in 0x200..0x2FF. `hstateen0`.CTR is read-only 0 when `mstateen0`.CTR=0.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > State Enable Access Control", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 407, + 407 + ] + }, + { + "chunk_id": "chunk_08871923", + "text": "When `mstateen0`.CTR=1 and `hstateen0`.CTR=1, VS-mode accesses to supervisor CTR state behave as described in and above, while SCTRCLR behaves as described in .", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > State Enable Access Control", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 409, + 409 + ] + }, + { + "chunk_id": "chunk_8bfcdb23", + "text": "When `mstateen0`.CTR=1 and `hstateen0`.CTR=0, both VS-mode accesses to supervisor CTR state and VS-mode execution of SCTRCLR raise a virtual-instruction exception.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > State Enable Access Control", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 409, + 409 + ] + }, + { + "chunk_id": "chunk_2cb0a9b1", + "text": "[NOTE] `sctrdepth` is not included in the above list of supervisor CTR state controlled by `hstateen0`.CTR since accesses to `sctrdepth` from VS-mode raise a virtual-instruction exception regardless of the value of `hstateen0`.CTR.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > State Enable Access Control", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 411, + 415 + ] + }, + { + "chunk_id": "chunk_5a1159ee", + "text": "When `hstateen0`.CTR=0, qualified control transfers executed while V=1 will continue to implicitly update entry registers and `sctrstatus`.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > State Enable Access Control", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 417, + 417 + ] + }, + { + "chunk_id": "chunk_b4bf0e99", + "text": "[NOTE] See for how bit 60 in `mstateen0` and `hstateen0` can also restrict access to `sireg*`/`siselect` and `vsireg*`/`vsiselect` from privilege modes less privileged than M-mode.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > State Enable Access Control", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 419, + 423 + ] + }, + { + "chunk_id": "chunk_c341addb", + "text": "[NOTE] Implementations that support Smctr/Ssctr but not Smstateen/Ssstateen may observe reduced performance.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > State Enable Access Control", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 425, + 429 + ] + }, + { + "chunk_id": "chunk_3b94ebfc", + "text": "Without Smstateen/Ssstateen, a hypervisor is required to save/restore guest CTR state on every context switch.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > State Enable Access Control", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 425, + 429 + ] + }, + { + "chunk_id": "chunk_578499bf", + "text": "CTR records qualified control transfers.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 433, + 433 + ] + }, + { + "chunk_id": "chunk_48846170", + "text": "Control transfers are qualified if they meet the following criteria:", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 433, + 433 + ] + }, + { + "chunk_id": "chunk_e5afe181", + "text": "The current privilege mode is enabled * The transfer type is not inhibited * `sctrstatus`.FROZEN is not set * The transfer completes/retires", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 435, + 438 + ] + }, + { + "chunk_id": "chunk_60de82fb", + "text": "Such qualified transfers update the at logical entry 0.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 440, + 440 + ] + }, + { + "chunk_id": "chunk_a121a929", + "text": "As a result, older entries are pushed down the stack; the record previously in logical entry 0 moves to logical entry 1, the record in logical entry 1 moves to logical entry 2, and so on.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 440, + 440 + ] + }, + { + "chunk_id": "chunk_fb6ed0bb", + "text": "If the CTR buffer is full, the oldest recorded entry (previously at entry depth-1) is lost.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 440, + 440 + ] + }, + { + "chunk_id": "chunk_5af3bb8c", + "text": "Recorded transfers will set the `ctrsource`.V bit to 1, and will update all implemented record fields.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 442, + 442 + ] + }, + { + "chunk_id": "chunk_a52d9144", + "text": "Transfers that change the privilege mode are a special case.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 452, + 455 + ] + }, + { + "chunk_id": "chunk_193fea55", + "text": "What is recorded, if anything, depends on whether the source privilege mode and/or target privilege mode are enabled for recording, and on the transfer type (trap or trap return).", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 452, + 455 + ] + }, + { + "chunk_id": "chunk_fa54eddb", + "text": "Traps between enabled privilege modes are recorded as normal.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 457, + 457 + ] + }, + { + "chunk_id": "chunk_398704a7", + "text": "Traps from a disabled privilege mode to an enabled privilege mode are partially recorded, such that the `ctrsource`.PC is 0.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 457, + 457 + ] + }, + { + "chunk_id": "chunk_835321d7", + "text": "Traps from an enabled mode to a disabled mode, known as external traps, are not recorded by default.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 457, + 457 + ] + }, + { + "chunk_id": "chunk_23b00efd", + "text": "See for how they can be recorded.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 457, + 457 + ] + }, + { + "chunk_id": "chunk_ccb71808", + "text": "Trap returns have similar treatment.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 459, + 459 + ] + }, + { + "chunk_id": "chunk_b6fe3489", + "text": "Trap returns between enabled privilege modes are recorded as normal.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 459, + 459 + ] + }, + { + "chunk_id": "chunk_c24f54a8", + "text": "Trap returns from an enabled mode back to a disabled mode are partially recorded, such that `ctrtarget`.PC is 0.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 459, + 459 + ] + }, + { + "chunk_id": "chunk_d68ac1a6", + "text": "Trap returns from a disabled mode to an enabled mode are not recorded.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 459, + 459 + ] + }, + { + "chunk_id": "chunk_5f488a20", + "text": "Recording in Debug Mode is always inhibited.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 461, + 461 + ] + }, + { + "chunk_id": "chunk_d4425507", + "text": "Transfers into and out of Debug Mode are never recorded.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 461, + 461 + ] + }, + { + "chunk_id": "chunk_7324870a", + "text": "The table below provides details on recording of privilege mode transitions.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 463, + 463 + ] + }, + { + "chunk_id": "chunk_6e8efb9c", + "text": "Standard dependencies on FROZEN and transfer type inhibits also apply, but are not covered by the table.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 463, + 463 + ] + }, + { + "chunk_id": "chunk_400982ee", + "text": "|*Disabled* |Recorded, `ctrsource`.PC is 0. |Not recorded.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 473, + 473 + ] + }, + { + "chunk_id": "chunk_bb52246c", + "text": "Transitions between VS/VU-mode and M/HS-mode are unique in that they effect a change in the active CTR control register, and hence the CTR configuration.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions > Virtualization Mode Transitions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 482, + 482 + ] + }, + { + "chunk_id": "chunk_37147815", + "text": "What is recorded, if anything, on these virtualization mode transitions depends upon fields from both `[ms]ctrctl` and `vsctrctl`.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions > Virtualization Mode Transitions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 482, + 482 + ] + }, + { + "chunk_id": "chunk_c075602b", + "text": "External traps are traps from a privilege mode enabled for CTR recording to a privilege mode that is not enabled for CTR recording.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions > External Traps", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 491, + 491 + ] + }, + { + "chunk_id": "chunk_281639c6", + "text": "By default external traps are not recorded, but privileged software running in the target mode of the trap can opt-in to allowing CTR to record external traps into that mode.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions > External Traps", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 491, + 491 + ] + }, + { + "chunk_id": "chunk_c525952d", + "text": "The `xctrctl`.xTE bits allow M-mode, S-mode, and VS-mode to opt-in separately.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions > External Traps", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 491, + 491 + ] + }, + { + "chunk_id": "chunk_bccfbb3e", + "text": "External trap recording depends not only on the target mode, but on any intervening modes, which are modes that are more privileged than the source mode but less privileged than the target mode.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions > External Traps", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 493, + 493 + ] + }, + { + "chunk_id": "chunk_87af05a4", + "text": "Not only must the external trap enable bit for the target mode be set, but the external trap enable bit(s) for any intervening modes must also be set.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions > External Traps", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 493, + 493 + ] + }, + { + "chunk_id": "chunk_8c559435", + "text": "See the table below for details.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions > External Traps", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 493, + 493 + ] + }, + { + "chunk_id": "chunk_4908794a", + "text": "[NOTE] Requiring intervening modes to be enabled for external traps simplifies software management of CTR.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions > External Traps", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "binary", + "line_range": [ + 495, + 498 + ] + }, + { + "chunk_id": "chunk_fc4f897c", + "text": "Consider a scenario where S-mode software is configuring CTR for U-mode contexts A and B, such that external traps (to any mode) are enabled for A but not for B.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions > External Traps", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "binary", + "line_range": [ + 495, + 498 + ] + }, + { + "chunk_id": "chunk_d48cb815", + "text": "When switching between the two contexts, S-mode can simply toggle `sctrctl`.STE, rather than requiring a trap to M-mode to additionally toggle `mctrctl`.MTE.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions > External Traps", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 495, + 498 + ] + }, + { + "chunk_id": "chunk_9d36bd0d", + "text": "This method does not provide the flexibility to record external traps to a more privileged mode but not to all intervening mode(s).", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions > External Traps", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 500, + 501 + ] + }, + { + "chunk_id": "chunk_8182555b", + "text": "In records for external traps, the `ctrtarget`.PC is 0.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions > External Traps", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 518, + 518 + ] + }, + { + "chunk_id": "chunk_90a5dee2", + "text": "Thus, when external traps are enabled, both external interrupts and external exceptions are recorded.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions > External Traps", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 529, + 532 + ] + }, + { + "chunk_id": "chunk_849662d5", + "text": "STE allows recording of traps from U-mode to S-mode as well as from VS/VU-mode to HS-mode.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions > External Traps", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 534, + 535 + ] + }, + { + "chunk_id": "chunk_4e00e5c6", + "text": "The hypervisor can flip `sctrctl`.STE before entering a guest if it wants different behavior for U-to-S vs VS/VU-to-HS.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions > External Traps", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 534, + 535 + ] + }, + { + "chunk_id": "chunk_329f5aad", + "text": "If external trap recording is implemented, `mctrctl`.MTE and `sctrctl`.STE must be implemented, while `vsctrctl`.STE must be implemented if the H extension is implemented.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions > External Traps", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 537, + 537 + ] + }, + { + "chunk_id": "chunk_84b6f46f", + "text": "By setting transfer type filter bits, software can opt out of recording select transfer types, or opt into recording non-default operations.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Transfer Type Filtering", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 541, + 541 + ] + }, + { + "chunk_id": "chunk_81a04b71", + "text": "All transfer type filter bits are optional.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Transfer Type Filtering", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 541, + 541 + ] + }, + { + "chunk_id": "chunk_fcbe53a6", + "text": "Non-default operations require opt-in rather than opt-out.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Transfer Type Filtering", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 543, + 547 + ] + }, + { + "chunk_id": "chunk_987bbe9d", + "text": "For completeness, the definitions are reproduced below.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Transfer Type Filtering", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 549, + 551 + ] + }, + { + "chunk_id": "chunk_5a68aaa6", + "text": "Encodings 8 through 15 refer to various encodings of jump instructions.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Transfer Type Filtering", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 577, + 577 + ] + }, + { + "chunk_id": "chunk_58b9e033", + "text": "The types are distinguished as described below.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Transfer Type Filtering", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 577, + 577 + ] + }, + { + "chunk_id": "chunk_7f47089d", + "text": "If implementation of any transfer type filter bit results in reduced software performance, perhaps due to additional retirement restrictions, it is strongly recommended that this reduced performance apply only when the bit is set.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Transfer Type Filtering", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 606, + 610 + ] + }, + { + "chunk_id": "chunk_2473f6d8", + "text": "Alternatively, support for the bit may be omitted.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Transfer Type Filtering", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 606, + 610 + ] + }, + { + "chunk_id": "chunk_60d93379", + "text": "Maintaining software performance for the default CTR configuration, when all transfer type bits are cleared, is recommended.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Transfer Type Filtering", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 606, + 610 + ] + }, + { + "chunk_id": "chunk_680281cc", + "text": "The `ctrdata` register may optionally include a count of CPU cycles elapsed since the prior CTR record.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Cycle Counting", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 615, + 615 + ] + }, + { + "chunk_id": "chunk_a986df1b", + "text": "The elapsed cycle count value is represented by the CC field, which has a 12-bit mantissa component (Cycle Count Mantissa, or CCM) and a 4-bit exponent component (Cycle Count Exponent, or CCE).", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Cycle Counting", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 615, + 615 + ] + }, + { + "chunk_id": "chunk_ba90120b", + "text": "The elapsed cycle counter (CtrCycleCounter) increments at the same rate as the `mcycle` counter.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Cycle Counting", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 617, + 617 + ] + }, + { + "chunk_id": "chunk_9a9a7717", + "text": "Only cycles while CTR is active are counted, where active implies that the current privilege mode is enabled for recording and CTR is not frozen.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Cycle Counting", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 617, + 617 + ] + }, + { + "chunk_id": "chunk_8fb0ab8b", + "text": "The CC field is encoded such that CCE holds 0 if the CtrCycleCounter value is less than 4096, otherwise it holds the index of the most significant one bit in the CtrCycleCounter value, minus 11. CCM holds CtrCycleCounter bits CCE+10:CCE-1.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Cycle Counting", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "range", + "line_range": [ + 617, + 617 + ] + }, + { + "chunk_id": "chunk_fa6ad78d", + "text": "The elapsed cycle count can then be calculated by software using the following formula:", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Cycle Counting", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 619, + 619 + ] + }, + { + "chunk_id": "chunk_1d12c7b4", + "text": "[subs=\"specialchars,quotes\"] ---- if (CCE0): return CCM else: return (2^12^ + CCM) << CCE-1 endif ----", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Cycle Counting", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 621, + 629 + ] + }, + { + "chunk_id": "chunk_d5c71da1", + "text": "The CtrCycleCounter is reset on writes to `xctrctl`, and on execution of SCTRCLR, to ensure that any accumulated cycle counts do not persist across a context switch.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Cycle Counting", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 631, + 631 + ] + }, + { + "chunk_id": "chunk_ffa9783a", + "text": "An implementation that supports cycle counting must implement CCV and all CCM bits, but may implement 0..4 exponent bits in CCE.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Cycle Counting", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 633, + 638 + ] + }, + { + "chunk_id": "chunk_26c2d7dc", + "text": "Unimplemented CCE bits are read-only 0.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Cycle Counting", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "unknown", + "line_range": [ + 633, + 638 + ] + }, + { + "chunk_id": "chunk_7611551b", + "text": "For implementations that support transfer type filtering, it is recommended to implement at least 3 exponent bits.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Cycle Counting", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 633, + 638 + ] + }, + { + "chunk_id": "chunk_35a43031", + "text": "The size of the CtrCycleCounter required to support each CCE width is given in the table below.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Cycle Counting", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 640, + 640 + ] + }, + { + "chunk_id": "chunk_9425ee1f", + "text": "When CCE>1, the granularity of the reported cycle count is reduced.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Cycle Counting", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 654, + 657 + ] + }, + { + "chunk_id": "chunk_fdd45350", + "text": "As a result, the reported value represents an undercount of elapsed cycles for most cases (when the unreported bits are non-zero).", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Cycle Counting", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 654, + 657 + ] + }, + { + "chunk_id": "chunk_556be5a6", + "text": "On average, the undercount will be (2^CCE-1^-1)/2.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Cycle Counting", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 654, + 657 + ] + }, + { + "chunk_id": "chunk_0a310148", + "text": "Software can reduce the average undercount to 0 by adding (2^CCE-1^-1)/2 to each computed cycle count value when CCE>1.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Cycle Counting", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 654, + 657 + ] + }, + { + "chunk_id": "chunk_5f746d51", + "text": "Though this compressed method of representation results in some imprecision for larger cycle count values, it produces meaningful area savings, reducing storage per entry from 27 bits to 16.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Cycle Counting", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 659, + 660 + ] + }, + { + "chunk_id": "chunk_41dac95d", + "text": "The CC value saturates when all implemented bits in CCM and CCE are 1.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Cycle Counting", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 662, + 662 + ] + }, + { + "chunk_id": "chunk_2c23500d", + "text": "The CC value is valid only when the Cycle Count Valid (CCV) bit is set.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Cycle Counting", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 664, + 664 + ] + }, + { + "chunk_id": "chunk_6758bcca", + "text": "If CCV=0, the CC value might not hold the correct count of elapsed active cycles since the last recorded transfer.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Cycle Counting", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 664, + 664 + ] + }, + { + "chunk_id": "chunk_5fbe2386", + "text": "The next record will have CCV=0 after a write to `xctrctl`, or execution of SCTRCLR, since CtrCycleCounter is reset. CCV should additionally be cleared after any other implementation-specific scenarios where active cycles might not be counted in CtrCycleCounter.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Cycle Counting", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 664, + 664 + ] + }, + { + "chunk_id": "chunk_af12b971", + "text": "When the optional `xctrctl`.RASEMU bit is implemented and set to 1, transfer recording behavior is altered to emulate the behavior of a return-address stack (RAS).", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > RAS (Return Address Stack) Emulation Mode", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 668, + 668 + ] + }, + { + "chunk_id": "chunk_3cb64063", + "text": "Indirect and direct calls are recorded as normal * Function returns pop the most recent call, by decrementing the WRPTR then invalidating the WRPTR entry (by setting ctrsource.V=0).", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > RAS (Return Address Stack) Emulation Mode", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 670, + 675 + ] + }, + { + "chunk_id": "chunk_d7503270", + "text": "As a result, logical entry 0 is invalidated and moves to logical entry depth-1, while logical entries 1..depth-1 move to 0..depth-2. * Co-routine swaps affect both a return and a call.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > RAS (Return Address Stack) Emulation Mode", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 670, + 675 + ] + }, + { + "chunk_id": "chunk_a81de96d", + "text": "[NOTE] Profiling tools often collect call stacks along with each sample.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > RAS (Return Address Stack) Emulation Mode", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 677, + 684 + ] + }, + { + "chunk_id": "chunk_e1da1ea7", + "text": "With RAS emulation, tools can ask CTR hardware to save call stacks even for unmodified code.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > RAS (Return Address Stack) Emulation Mode", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 677, + 684 + ] + }, + { + "chunk_id": "chunk_4a6213a8", + "text": "CTR RAS emulation has limitations.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > RAS (Return Address Stack) Emulation Mode", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 686, + 686 + ] + }, + { + "chunk_id": "chunk_5d645f0b", + "text": "The CTR buffer will contain only partial stacks in cases where the call stack depth was greater than the CTR depth, CTR recording was enabled at a lower point in the call stack than main(), or where the CTR buffer was cleared since main().", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > RAS (Return Address Stack) Emulation Mode", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 686, + 686 + ] + }, + { + "chunk_id": "chunk_75556d1b", + "text": "[NOTE] As described in , when CCV=1, the CC field provides the elapsed cycles since the prior CTR entry was recorded.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > RAS (Return Address Stack) Emulation Mode", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 691, + 703 + ] + }, + { + "chunk_id": "chunk_4371650f", + "text": "The implication is that returns that pop a call entry not only do not reset the cycle counter, but instead add the CC field from the popped entry to the counter.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > RAS (Return Address Stack) Emulation Mode", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 691, + 703 + ] + }, + { + "chunk_id": "chunk_eadcb771", + "text": "For simplicity, an implementation may opt to record CCV=0 for all calls, or those whose parent call was popped, when RASEMU=1.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > RAS (Return Address Stack) Emulation Mode", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 691, + 703 + ] + }, + { + "chunk_id": "chunk_92caf200", + "text": "When `sctrstatus`.FROZEN=1, transfer recording is inhibited.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Freeze", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 707, + 707 + ] + }, + { + "chunk_id": "chunk_39f27071", + "text": "This bit can be set by hardware, as described below, or by software.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Freeze", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 707, + 707 + ] + }, + { + "chunk_id": "chunk_7bcf6eb2", + "text": "When `sctrctl`.LCOFIFRZ=1 and a local-counter-overflow interrupt (LCOFI) traps (as a result of an HPM counter overflow) to M-mode or to S-mode, `sctrstatus`.FROZEN is set by hardware.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Freeze", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 709, + 719 + ] + }, + { + "chunk_id": "chunk_aead4baa", + "text": "This inhibits CTR recording until software clears FROZEN.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Freeze", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 709, + 719 + ] + }, + { + "chunk_id": "chunk_dbb85987", + "text": "The LCOFI trap itself is not recorded. [NOTE] Freeze on LCOFI ensures that the execution path leading to the sampled instruction (`xepc`) is preserved, and that the local-counter-overflow interrupt (LCOFI) and associated Interrupt Service Routine (ISR) do not displace any recorded transfer history state.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Freeze", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 709, + 719 + ] + }, + { + "chunk_id": "chunk_11d2724b", + "text": "It is the responsibility of the ISR to clear FROZEN before xRET, if continued control transfer recording is desired.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Freeze", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 709, + 719 + ] + }, + { + "chunk_id": "chunk_df4d9463", + "text": "LCOFI refers only to architectural traps directly caused by a local counter overflow.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Freeze", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 721, + 723 + ] + }, + { + "chunk_id": "chunk_81833cde", + "text": "If a local-counter-overflow interrupt is recognized without a trap, FROZEN is not automatically set.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Freeze", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 721, + 723 + ] + }, + { + "chunk_id": "chunk_4ec90ff6", + "text": "As a result, some or all CTR history may be overwritten while handling the LCOFI.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Freeze", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 721, + 723 + ] + }, + { + "chunk_id": "chunk_f4e44b8f", + "text": "Similarly, on a breakpoint exception that traps to M-mode or S-mode with `sctrctl`.BPFRZ=1, FROZEN is set by hardware.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Freeze", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 721, + 723 + ] + }, + { + "chunk_id": "chunk_6f3a80e4", + "text": "The breakpoint exception itself is not recorded.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Freeze", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 721, + 723 + ] + }, + { + "chunk_id": "chunk_cbc842bc", + "text": "[NOTE] Breakpoint exception refers to synchronous exceptions with a cause value of Breakpoint (3), regardless of source (ebreak, c.ebreak, Sdtrig); it does not include entry into Debug Mode, even in cores where this is implemented as an exception.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Freeze", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 725, + 729 + ] + }, + { + "chunk_id": "chunk_6dfa8a5b", + "text": "If the H extension is implemented, freeze behavior for LCOFIs and breakpoint exceptions that trap to VS-mode is determined by the LCOFIFRZ and BPFRZ values, respectively, in `vsctrctl`.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Freeze", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 731, + 731 + ] + }, + { + "chunk_id": "chunk_29b1328b", + "text": "This includes virtual LCOFIs pended by a hypervisor.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Freeze", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 731, + 731 + ] + }, + { + "chunk_id": "chunk_27fac302", + "text": "When a guest uses the SBI Supervisor Software Events (SSE) extension, the LCOFI will trap to HS-mode, which will then invoke a registered VS-mode LCOFI handler routine.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Freeze", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 733, + 737 + ] + }, + { + "chunk_id": "chunk_4e51707f", + "text": "If `vsctrctl`.LCOFIFRZ=1, the HS-mode handler will need to emulate the freeze by setting `sctrstatus`.FROZEN=1 before invoking the registered handler routine.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Freeze", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 733, + 737 + ] + }, + { + "chunk_id": "chunk_7d2ccf89", + "text": "Any custom CTR extension must be associated with a non-zero value within the designated custom bits in `xctrctl`.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Custom Extensions", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 742, + 742 + ] + }, + { + "chunk_id": "chunk_22cd190e", + "text": "When the custom bits hold a non-zero value that enables a custom extension, the extension may alter standard CTR behavior, and may define new custom status fields within `sctrstatus` or the CTR .", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Custom Extensions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 742, + 742 + ] + }, + { + "chunk_id": "chunk_d4efda54", + "text": "All custom status fields, and standard status fields whose behavior is altered by the custom extension, must revert to standard behavior when the custom bits hold zero.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Custom Extensions", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 742, + 742 + ] + }, + { + "chunk_id": "chunk_3b99f8d0", + "text": "This includes read-only 0 behavior for any bits undefined by any implemented standard extensions.", + "source_file": "src/priv/smctr.adoc", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Custom Extensions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "unknown", + "line_range": [ + 742, + 742 + ] + } + ] + }, + { + "file": "src/priv/smdbltrp.adoc", + "chunks": [ + { + "chunk_id": "chunk_f5415624", + "text": "When the Smrnmi extension () is implemented, it enables invocation of the RNMI handler on a double trap in M-mode to handle the critical error.", + "source_file": "src/priv/smdbltrp.adoc", + "section": "Preamble > \"Smdbltrp\" Double Trap Extension, Version 1.0", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 3, + 9 + ] + }, + { + "chunk_id": "chunk_efc606e9", + "text": "If the Smrnmi extension is not implemented or if a double trap occurs during the RNMI handler's execution, this extension helps transition the hart to a critical error state and enables signaling the critical error to the platform.", + "source_file": "src/priv/smdbltrp.adoc", + "section": "Preamble > \"Smdbltrp\" Double Trap Extension, Version 1.0", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 3, + 9 + ] + }, + { + "chunk_id": "chunk_feba7989", + "text": "The extension introduces a mechanism to enter Debug Mode instead of asserting a critical-error signal to the platform when the hart is in a critical error state.", + "source_file": "src/priv/smdbltrp.adoc", + "section": "Preamble > \"Smdbltrp\" Double Trap Extension, Version 1.0", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 11, + 14 + ] + } + ] + }, + { + "file": "src/priv/smepmp.adoc", + "chunks": [ + { + "chunk_id": "chunk_8fb88904", + "text": "Being able to access the memory of a process running at a high privileged execution mode, such as the Supervisor or Machine mode, from a lower privileged mode such as the User mode, introduces an obvious attack vector since it allows for an attacker to perform privilege escalation, and tamper with the code and/or data of that process. A less obvious attack vector exists when the reverse happens, in which case an attacker instead of tampering with code and/or data that belong to a high-privileged process, can tamper with the memory of an unprivileged / less-privileged process and trick the high-privileged process to use or execute it.", + "source_file": "src/priv/smepmp.adoc", + "section": "Preamble > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode, Version 1.0", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 3, + 3 + ] + }, + { + "chunk_id": "chunk_e1251d7e", + "text": "The first one prevents the OS from accessing the memory of an unprivileged process unless a specific code path is followed, and the second one prevents the OS from executing the memory of an unprivileged process at all times. RISC-V already includes support for the former through the ``sstatus.SUM`` bit, and for the latter by always denying supervisor execution of virtual memory pages marked with the U bit.", + "source_file": "src/priv/smepmp.adoc", + "section": "Preamble > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode, Version 1.0", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 5, + 11 + ] + }, + { + "chunk_id": "chunk_57fdab67", + "text": "To address the threat model outlined in Section , this extension introduces the `RLB`, `MMWP`, and `MML` fields in the `mseccfg` CSR and their associated rules.", + "source_file": "src/priv/smepmp.adoc", + "section": "Preamble > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode, Version 1.0 > Threat model > Smepmp Physical Memory Protection Rules", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 25, + 28 + ] + }, + { + "chunk_id": "chunk_7e0aa8a0", + "text": "See for the detailed specification of these fields and the corresponding rules.", + "source_file": "src/priv/smepmp.adoc", + "section": "Preamble > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode, Version 1.0 > Threat model > Smepmp Physical Memory Protection Rules", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 25, + 28 + ] + }, + { + "chunk_id": "chunk_aec572a2", + "text": "The physical memory protection rules when `mseccfg.MML` is set to 1 are summarized in the truth table below.", + "source_file": "src/priv/smepmp.adoc", + "section": "Preamble > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode, Version 1.0 > Threat model > Smepmp Physical Memory Protection Rules", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 30, + 30 + ] + }, + { + "chunk_id": "chunk_b806a90c", + "text": "Since all fields defined in ``mseccfg`` as part of this extension are locked when set (``MMWP``/``MML``) or locked when cleared (``RLB``), software can't poll them for determining the presence of Smepmp.", + "source_file": "src/priv/smepmp.adoc", + "section": "Preamble > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode, Version 1.0 > Threat model > Smepmp software discovery", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 62, + 62 + ] + } + ] + }, + { + "file": "src/priv/smrnmi.adoc", + "chunks": [ + { + "chunk_id": "chunk_da96c693", + "text": "The base machine-level architecture supports only unresumable non-maskable interrupts (UNMIs), where the NMI jumps to a handler in machine mode, overwriting the current `mepc` and `mcause` register values.", + "source_file": "src/priv/smrnmi.adoc", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 3, + 8 + ] + }, + { + "chunk_id": "chunk_e5a96994", + "text": "If the hart had been executing machine-mode code in a trap handler, the previous values in `mepc` and `mcause` would not be recoverable and so execution is not generally resumable.", + "source_file": "src/priv/smrnmi.adoc", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 3, + 8 + ] + }, + { + "chunk_id": "chunk_83c991ab", + "text": "The Smrnmi extension adds support for resumable non-maskable interrupts (RNMIs) to RISC-V.", + "source_file": "src/priv/smrnmi.adoc", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 10, + 13 + ] + }, + { + "chunk_id": "chunk_bdbbcbcb", + "text": "The extension adds four new CSRs (`mnepc`, `mncause`, `mnstatus`, and `mnscratch`) to hold the interrupted state, and one new instruction, MNRET, to resume from the RNMI handler.", + "source_file": "src/priv/smrnmi.adoc", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 10, + 13 + ] + }, + { + "chunk_id": "chunk_5f64c535", + "text": "The `rnmi` interrupt signals are inputs to the hart.", + "source_file": "src/priv/smrnmi.adoc", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 17, + 20 + ] + }, + { + "chunk_id": "chunk_4f9b7705", + "text": "These interrupts have higher priority than any other interrupt or exception on the hart and cannot be disabled by software.", + "source_file": "src/priv/smrnmi.adoc", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "binary", + "line_range": [ + 17, + 20 + ] + }, + { + "chunk_id": "chunk_d0c694c2", + "text": "Specifically, they are not disabled by clearing the `mstatus`.MIE register.", + "source_file": "src/priv/smrnmi.adoc", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 17, + 20 + ] + }, + { + "chunk_id": "chunk_13b80bc1", + "text": "The RNMI interrupt trap handler address is implementation-defined.", + "source_file": "src/priv/smrnmi.adoc", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI Handler Addresses", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 24, + 24 + ] + }, + { + "chunk_id": "chunk_43cce05f", + "text": "RNMI also has an associated exception trap handler address, which is implementation defined.", + "source_file": "src/priv/smrnmi.adoc", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI Handler Addresses", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 26, + 27 + ] + }, + { + "chunk_id": "chunk_34c1a629", + "text": "This extension adds additional M-mode CSRs to enable a resumable non-maskable interrupt (RNMI).", + "source_file": "src/priv/smrnmi.adoc", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 34, + 35 + ] + }, + { + "chunk_id": "chunk_d593a6e4", + "text": "The `mnscratch` CSR holds an MXLEN-bit read-write register which enables the RNMI trap handler to save and restore the context that was interrupted.", + "source_file": "src/priv/smrnmi.adoc", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 40, + 42 + ] + }, + { + "chunk_id": "chunk_24226da1", + "text": "The `mnepc` CSR is an MXLEN-bit read-write register which on entry to the RNMI trap handler holds the PC of the instruction that took the interrupt.", + "source_file": "src/priv/smrnmi.adoc", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 47, + 49 + ] + }, + { + "chunk_id": "chunk_698c033f", + "text": "The low bit of `mnepc` (`mnepc[0]`) is always zero.", + "source_file": "src/priv/smrnmi.adoc", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 51, + 53 + ] + }, + { + "chunk_id": "chunk_8effac9b", + "text": "This masking occurs also for the implicit read by the MNRET instruction.", + "source_file": "src/priv/smrnmi.adoc", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 55, + 59 + ] + }, + { + "chunk_id": "chunk_c04f6355", + "text": "Though masked, `mnepc[1]` remains writable when IALIGN=32.", + "source_file": "src/priv/smrnmi.adoc", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 55, + 59 + ] + }, + { + "chunk_id": "chunk_8895fd7d", + "text": "`mnepc` is a *WARL* register that must be able to hold all valid virtual addresses.", + "source_file": "src/priv/smrnmi.adoc", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 61, + 65 + ] + }, + { + "chunk_id": "chunk_8488b26b", + "text": "It need not be capable of holding all possible invalid addresses.", + "source_file": "src/priv/smrnmi.adoc", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 61, + 65 + ] + }, + { + "chunk_id": "chunk_d230e57f", + "text": "Prior to writing `mnepc`, implementations may convert an invalid address into some other invalid address that `mnepc` is capable of holding.", + "source_file": "src/priv/smrnmi.adoc", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 61, + 65 + ] + }, + { + "chunk_id": "chunk_08264a8a", + "text": "The `mncause` CSR holds the reason for the RNMI.", + "source_file": "src/priv/smrnmi.adoc", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 71, + 79 + ] + }, + { + "chunk_id": "chunk_1d4ccac2", + "text": "If the reason is an interrupt, bit MXLEN-1 is set to 1, and the RNMI cause is encoded in the least-significant bits.", + "source_file": "src/priv/smrnmi.adoc", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 71, + 79 + ] + }, + { + "chunk_id": "chunk_6841b407", + "text": "If the reason is an interrupt and RNMI causes are not supported, bit MXLEN-1 is set to 1, and zero is written to the least-significant bits.", + "source_file": "src/priv/smrnmi.adoc", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 71, + 79 + ] + }, + { + "chunk_id": "chunk_67586a35", + "text": "If the reason is an exception within M-mode that results in a double trap as specified in the Smdbltrp extension, bit MXLEN-1 is set to 0 and the least-significant bits are set to the cause code corresponding to the exception that precipitated the double trap.", + "source_file": "src/priv/smrnmi.adoc", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 71, + 79 + ] + }, + { + "chunk_id": "chunk_1af0eedd", + "text": "The `mnstatus` CSR holds a two-bit field, MNPP, which on entry to the RNMI trap handler holds the privilege mode of the interrupted context, encoded in the same manner as `mstatus`.MPP.", + "source_file": "src/priv/smrnmi.adoc", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 85, + 91 + ] + }, + { + "chunk_id": "chunk_edf5180e", + "text": "If the H extension is also implemented, `mnstatus` also holds a one-bit field, MNPV, which on entry to the RNMI trap handler holds the virtualization mode of the interrupted context, encoded in the same manner as `mstatus`.MPV.", + "source_file": "src/priv/smrnmi.adoc", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 85, + 91 + ] + }, + { + "chunk_id": "chunk_15885066", + "text": "If the Zicfilp extension is implemented, `mnstatus` also holds the MNPELP field, which on entry to the RNMI trap handler holds the previous `ELP` state.", + "source_file": "src/priv/smrnmi.adoc", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 93, + 95 + ] + }, + { + "chunk_id": "chunk_afcd26b6", + "text": "When an RNMI trap is taken, MNPELP is set to `ELP` and `ELP` is set to 0.", + "source_file": "src/priv/smrnmi.adoc", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 93, + 95 + ] + }, + { + "chunk_id": "chunk_e41a6c7e", + "text": "`mnstatus` also holds the NMIE bit.", + "source_file": "src/priv/smrnmi.adoc", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 97, + 98 + ] + }, + { + "chunk_id": "chunk_b5684f3b", + "text": "When NMIE=1, non-maskable interrupts are enabled.", + "source_file": "src/priv/smrnmi.adoc", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 97, + 98 + ] + }, + { + "chunk_id": "chunk_ecc4122c", + "text": "When NMIE=0, all interrupts are disabled.", + "source_file": "src/priv/smrnmi.adoc", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 97, + 98 + ] + }, + { + "chunk_id": "chunk_de22693d", + "text": "When NMIE=0, the hart behaves as though `mstatus`.MPRV were clear, regardless of the current setting of `mstatus`.MPRV.", + "source_file": "src/priv/smrnmi.adoc", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 100, + 101 + ] + }, + { + "chunk_id": "chunk_ae0ab819", + "text": "Upon reset, NMIE contains the value 0.", + "source_file": "src/priv/smrnmi.adoc", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 103, + 103 + ] + }, + { + "chunk_id": "chunk_7d89266a", + "text": "Software can set NMIE to 1, but attempts to clear NMIE have no effect.", + "source_file": "src/priv/smrnmi.adoc", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 105, + 105 + ] + }, + { + "chunk_id": "chunk_b44ceea2", + "text": "For the purposes of the WFI instruction, NMIE is a global interrupt enable, meaning that the setting of NMIE does not affect the operation of the WFI instruction.", + "source_file": "src/priv/smrnmi.adoc", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 107, + 109 + ] + }, + { + "chunk_id": "chunk_92e788bd", + "text": "The other bits in `mnstatus` are reserved; software should write zeros and hardware implementations should return zeros.", + "source_file": "src/priv/smrnmi.adoc", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 111, + 112 + ] + }, + { + "chunk_id": "chunk_4c1c6aa7", + "text": "MNRET is an M-mode-only instruction that uses the values in `mnepc` and `mnstatus` to return to the program counter, privilege mode, and virtualization mode of the interrupted context.", + "source_file": "src/priv/smrnmi.adoc", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > MNRET Instruction", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 116, + 121 + ] + }, + { + "chunk_id": "chunk_49733ea8", + "text": "This instruction also sets `mnstatus`.NMIE.", + "source_file": "src/priv/smrnmi.adoc", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > MNRET Instruction", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 116, + 121 + ] + }, + { + "chunk_id": "chunk_550ae943", + "text": "If MNRET changes the privilege mode to a mode less privileged than M, it also sets `mstatus`.MPRV to 0.", + "source_file": "src/priv/smrnmi.adoc", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > MNRET Instruction", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 116, + 121 + ] + }, + { + "chunk_id": "chunk_0bfe971d", + "text": "When an RNMI interrupt is detected, the interrupted PC is written to the `mnepc` CSR, the type of RNMI to the `mncause` CSR, and the privilege mode of the interrupted context to the `mnstatus` CSR.", + "source_file": "src/priv/smrnmi.adoc", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI Operation", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 125, + 128 + ] + }, + { + "chunk_id": "chunk_333947ae", + "text": "The `mnstatus`.NMIE bit is cleared, masking all interrupts.", + "source_file": "src/priv/smrnmi.adoc", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI Operation", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 125, + 128 + ] + }, + { + "chunk_id": "chunk_1079042c", + "text": "The hart then enters machine-mode and jumps to the RNMI trap handler address.", + "source_file": "src/priv/smrnmi.adoc", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI Operation", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 130, + 131 + ] + }, + { + "chunk_id": "chunk_3442dbc0", + "text": "The RNMI handler can resume original execution using the new MNRET instruction, which restores the PC from `mnepc`, the privilege mode from `mnstatus`, and also sets `mnstatus`.NMIE, which re-enables interrupts.", + "source_file": "src/priv/smrnmi.adoc", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI Operation", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 133, + 135 + ] + }, + { + "chunk_id": "chunk_bfcb3a07", + "text": "If the hart encounters an exception while executing in M-mode with the `mnstatus`.NMIE bit clear, the actions taken are the same as if the exception had occurred while `mnstatus`.NMIE were set, except that the program counter is set to the RNMI exception trap handler address.", + "source_file": "src/priv/smrnmi.adoc", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI Operation", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 137, + 137 + ] + } + ] + }, + { + "file": "src/priv/smstateen.adoc", + "chunks": [ + { + "chunk_id": "chunk_938e0486", + "text": "The problem occurs when an extension adds processor state -- usually explicit registers, but possibly other forms of state -- that the main OS or hypervisor is unaware of (and hence won't context-switch) but that can be modified/written by one user thread or guest OS and perceived/examined/read by another.", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 3, + 9 + ] + }, + { + "chunk_id": "chunk_778a976d", + "text": "The `f` registers of the RISC-V floating-point extensions and the `v` registers of the vector extension would similarly be potential covert channels between user threads, except for the existence of the FS and VS fields in the `sstatus` register.", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 22, + 28 + ] + }, + { + "chunk_id": "chunk_f217d9c9", + "text": "Even if an OS is unaware of, say, the vector extension and its `v` registers, access to those registers is blocked when the VS field is initialized to zero, either at machine level or by the OS itself initializing `sstatus`.", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 22, + 28 + ] + }, + { + "chunk_id": "chunk_e480e4d5", + "text": "Obviously, one way to prevent the use of new user-level CSRs as covert channels would be to add to `mstatus` or `sstatus` an \"XS\" field for each relevant extension, paralleling the V extension's VS field.", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 30, + 41 + ] + }, + { + "chunk_id": "chunk_ee371de0", + "text": "However, this is not considered a general solution to the problem due to the number of potential future extensions that may add small amounts of state.", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 30, + 41 + ] + }, + { + "chunk_id": "chunk_5a00e8bd", + "text": "Even with a 64-bit `sstatus` (necessitating adding `sstatush` for RV32), it is not certain there are enough remaining bits in `sstatus` to accommodate all future user-level extensions.", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 30, + 41 + ] + }, + { + "chunk_id": "chunk_924e962e", + "text": "In any event, there is no need to strain `sstatus` (and add `sstatush`) for this purpose.", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 30, + 41 + ] + }, + { + "chunk_id": "chunk_72ae618c", + "text": "The \"enable\" flags that are needed to plug covert channels are not generally expected to require swapping on context switches of user threads, making them a less-than-compelling candidate for inclusion in `sstatus`.", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 30, + 41 + ] + }, + { + "chunk_id": "chunk_6898bf03", + "text": "The Smstateen extension specification comprises the mstateen*, sstateen*, and hstateen* CSRs and their functionality.", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 45, + 49 + ] + }, + { + "chunk_id": "chunk_6c4eaf2b", + "text": "The Ssstateen extension specification comprises only the sstateen* and hstateen* CSRs and their functionality.", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 45, + 49 + ] + }, + { + "chunk_id": "chunk_0baedc44", + "text": "For RV64 harts, this extension adds four new 64-bit CSRs at machine level: `mstateen0` (Machine State Enable 0), `mstateen1`, `mstateen2`, and `mstateen3`.", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 51, + 53 + ] + }, + { + "chunk_id": "chunk_1e3097be", + "text": "If supervisor mode is implemented, another four CSRs are defined at supervisor level: `sstateen0`, `sstateen1`, `sstateen2`, and `sstateen3`.", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 55, + 58 + ] + }, + { + "chunk_id": "chunk_5d4e42ce", + "text": "And if the hypervisor extension is implemented, another set of CSRs is added: `hstateen0`, `hstateen1`, `hstateen2`, and `hstateen3`.", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 60, + 62 + ] + }, + { + "chunk_id": "chunk_76350f1c", + "text": "For RV32, there are CSR addresses for accessing the upper 32 bits of corresponding machine-level and hypervisor CSRs: `mstateen0h`, `mstateen1h`, `mstateen2h`, `mstateen3h`, `hstateen0h`, `hstateen1h`, `hstateen2h`, and `hstateen3h`.", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 64, + 68 + ] + }, + { + "chunk_id": "chunk_f59172cd", + "text": "Each bit of a `stateen` CSR controls less-privileged access to an extension's state, for an extension that was not deemed \"worthy\" of a full XS field in `sstatus` like the FS and VS fields for the F and V extensions.", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 74, + 83 + ] + }, + { + "chunk_id": "chunk_3f1a0e13", + "text": "The exact number four is an attempted compromise between providing too few bits on the one hand and going overboard with CSRs that will never be used on the other. A possible future doubling of the number of `stateen` CSRs is covered later.", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 74, + 83 + ] + }, + { + "chunk_id": "chunk_9a0ae304", + "text": "This is analogous to how the existing `counteren` CSRs control access to performance counter registers.", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 85, + 94 + ] + }, + { + "chunk_id": "chunk_fd80e2a6", + "text": "Just as with the `counteren` CSRs, when a `stateen` CSR prevents access to state by less-privileged levels, an attempt in one of those privilege modes to execute an instruction that would read or write the protected state raises an illegal-instruction exception, or, if executing in VS or VU mode and the circumstances for a virtual-instruction exception apply, raises a virtual-instruction exception instead of an illegal-instruction exception.", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 85, + 94 + ] + }, + { + "chunk_id": "chunk_16aec837", + "text": "When this extension is not implemented, all state added by an extension is accessible as defined by that extension.", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 96, + 97 + ] + }, + { + "chunk_id": "chunk_90dacb87", + "text": "When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute in that privilege mode an instruction that implicitly updates the state without reading it may or may not raise an illegal-instruction or virtual-instruction exception.", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 99, + 104 + ] + }, + { + "chunk_id": "chunk_8f6c5b89", + "text": "Such cases must be disambiguated by being explicitly specified one way or the other.", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 99, + 104 + ] + }, + { + "chunk_id": "chunk_23686fd8", + "text": "In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the ISA extensions that introduce the controlled state.", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 106, + 107 + ] + }, + { + "chunk_id": "chunk_602c2c66", + "text": "Each bit of a supervisor-level `sstateen` CSR controls user-level access (from U-mode or VU-mode) to an extension's state.", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 109, + 112 + ] + }, + { + "chunk_id": "chunk_6139a2d6", + "text": "The intention is to allocate the bits of `sstateen` CSRs starting at the least-significant end, bit 0, through to bit 31, and then on to the next-higher-numbered `sstateen` CSR.", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 109, + 112 + ] + }, + { + "chunk_id": "chunk_4c2219d3", + "text": "For every bit with a defined purpose in an `sstateen` CSR, the same bit is defined in the matching `mstateen` CSR to control access below machine level to the same state.", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 114, + 126 + ] + }, + { + "chunk_id": "chunk_fd09fd7f", + "text": "The upper 32 bits of an `mstateen` CSR (or for RV32, the corresponding high-half CSR) control access to state that is inherently inaccessible to user level, so no corresponding enable bits in the supervisor-level `sstateen` CSR are applicable.", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 114, + 126 + ] + }, + { + "chunk_id": "chunk_0652f098", + "text": "The intention is to allocate bits for this purpose starting at the most-significant end, bit 63, through to bit 32, and then on to the next-higher `mstateen` CSR.", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 114, + 126 + ] + }, + { + "chunk_id": "chunk_7b5e69be", + "text": "If the rate that bits are being allocated from the least-significant end for `sstateen` CSRs is sufficiently low, allocation from the most-significant end of `mstateen` CSRs may be allowed to encroach on the lower 32 bits before jumping to the next-higher `mstateen` CSR.", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 114, + 126 + ] + }, + { + "chunk_id": "chunk_dc631047", + "text": "In that case, the bit positions of \"encroaching\" bits will remain forever read-only zeros in the matching `sstateen` CSRs.", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 114, + 126 + ] + }, + { + "chunk_id": "chunk_67d880bc", + "text": "With the hypervisor extension, the `hstateen` CSRs have identical encodings to the `mstateen` CSRs, except controlling accesses for a virtual machine (from VS and VU modes).", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 128, + 131 + ] + }, + { + "chunk_id": "chunk_5f25de74", + "text": "Each standard-defined bit of a `stateen` CSR is WARL and may be read-only zero or one, subject to the following conditions.", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 133, + 135 + ] + }, + { + "chunk_id": "chunk_c896b4c3", + "text": "Bits in any `stateen` CSR that are defined to control state that a hart doesn't implement are read-only zeros for that hart.", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 137, + 145 + ] + }, + { + "chunk_id": "chunk_f29d7205", + "text": "Likewise, all reserved bits not yet given a defined meaning are also read-only zeros.", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 137, + 145 + ] + }, + { + "chunk_id": "chunk_ed6462fb", + "text": "For every bit in an `mstateen` CSR that is zero (whether read-only zero or set to zero), the same bit appears as read-only zero in the matching `hstateen` and `sstateen` CSRs.", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 137, + 145 + ] + }, + { + "chunk_id": "chunk_270a99d3", + "text": "For every bit in an `hstateen` CSR that is zero (whether read-only zero or set to zero), the same bit appears as read-only zero in `sstateen` when accessed in VS-mode.", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 137, + 145 + ] + }, + { + "chunk_id": "chunk_1fd560f2", + "text": "A bit in a supervisor-level `sstateen` CSR cannot be read-only one unless the same bit is read-only one in the matching `mstateen` CSR and, if it exists, in the matching `hstateen` CSR. A bit in an `hstateen` CSR cannot be read-only one unless the same bit is read-only one in the matching `mstateen` CSR.", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 147, + 150 + ] + }, + { + "chunk_id": "chunk_adfeb87e", + "text": "On reset, all writable `mstateen` bits are initialized by the hardware to zeros.", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "unknown", + "line_range": [ + 152, + 159 + ] + }, + { + "chunk_id": "chunk_b489fb78", + "text": "If machine-level software changes these values, it is responsible for initializing the corresponding writable bits of the `hstateen` and `sstateen` CSRs to zeros too.", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 152, + 159 + ] + }, + { + "chunk_id": "chunk_224a83f3", + "text": "Software at each privilege level should set its respective `stateen` CSRs to indicate the state it is prepared to allow less-privileged software to access.", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 152, + 159 + ] + }, + { + "chunk_id": "chunk_00474514", + "text": "For each `mstateen` CSR, bit 63 is defined to control access to the matching `sstateen` and `hstateen` CSRs.", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 161, + 165 + ] + }, + { + "chunk_id": "chunk_18cb01d6", + "text": "Likewise, bit 63 of each `hstateen` correspondingly controls access to the matching `sstateen` CSR.", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 161, + 165 + ] + }, + { + "chunk_id": "chunk_9e6b8968", + "text": "A hypervisor may need this control over accesses to the `sstateen` CSRs if it ever must emulate for a virtual machine an extension that is supposed to be affected by a bit in an `sstateen` CSR.", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 167, + 170 + ] + }, + { + "chunk_id": "chunk_cc7217c0", + "text": "Even if such emulation is uncommon, it should not be excluded.", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 167, + 170 + ] + }, + { + "chunk_id": "chunk_558119ab", + "text": "That is, machine level needs control over accesses to the supervisor-level `sstateen` CSRs in order to emulate the `hstateen` CSRs, which have such control.", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 172, + 175 + ] + }, + { + "chunk_id": "chunk_fcd0897b", + "text": "Bit 63 of each `mstateen` CSR may be read-only zero only if the hypervisor extension is not implemented and the matching supervisor-level `sstateen` CSR is all read-only zeros.", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 177, + 182 + ] + }, + { + "chunk_id": "chunk_fb796634", + "text": "In that case, machine-level software should emulate attempts to access the affected `sstateen` CSR from S-mode, ignoring writes and returning zero for reads.", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 177, + 182 + ] + }, + { + "chunk_id": "chunk_592ee623", + "text": "Bit 63 of each `hstateen` CSR is always writable (not read-only).", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 177, + 182 + ] + }, + { + "chunk_id": "chunk_1e69cfad", + "text": "The C bit controls access to any and all custom state.", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions > State Enable 0 Registers", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 238, + 241 + ] + }, + { + "chunk_id": "chunk_f835e2f7", + "text": "The C bit of these registers is not custom state itself; it is a standard field of a standard CSR, either `mstateen0`, `hstateen0`, or `sstateen0`.", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions > State Enable 0 Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 238, + 241 + ] + }, + { + "chunk_id": "chunk_fccce0ed", + "text": "The FCSR bit controls access to `fcsr` for the case when floating-point instructions operate on `x` registers instead of `f` registers as specified by the Zfinx and related extensions (Zdinx, etc.). [mstateen0fcsrroz]Whenever `misa.F` = 1, FCSR bit of `mstateen0` is read-only zero (and hence read-only zero in `hstateen0` and `sstateen0` too).", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions > State Enable 0 Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 243, + 251 + ] + }, + { + "chunk_id": "chunk_75109212", + "text": "For convenience, when the `stateen` CSRs are implemented and `misa.F` = 0, then if the FCSR bit of a controlling `stateen0` CSR is zero, all floating-point instructions cause an illegal-instruction exception (or virtual-instruction exception, if relevant), as though they all access `fcsr`, regardless of whether they really do.", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions > State Enable 0 Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 243, + 251 + ] + }, + { + "chunk_id": "chunk_b642d77f", + "text": "The JVT bit controls access to the `jvt` CSR provided by the Zcmt extension.", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions > State Enable 0 Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 253, + 254 + ] + }, + { + "chunk_id": "chunk_5a34402e", + "text": "The SE0 bit in `mstateen0` controls access to the `hstateen0`, `hstateen0h`, and the `sstateen0` CSRs.", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions > State Enable 0 Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 256, + 258 + ] + }, + { + "chunk_id": "chunk_370407ad", + "text": "The SE0 bit in `hstateen0` controls access to the `sstateen0` CSR.", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions > State Enable 0 Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 256, + 258 + ] + }, + { + "chunk_id": "chunk_9b424a29", + "text": "The ENVCFG bit in `mstateen0` controls access to the `henvcfg`, `henvcfgh`, and the `senvcfg` CSRs.", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions > State Enable 0 Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 260, + 262 + ] + }, + { + "chunk_id": "chunk_c169c627", + "text": "The ENVCFG bit in `hstateen0` controls access to the `senvcfg` CSRs.", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions > State Enable 0 Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 260, + 262 + ] + }, + { + "chunk_id": "chunk_d0ffcb71", + "text": "The CSRIND bit in `mstateen0` controls access to the `siselect`, `sireg*`, `vsiselect`, and the `vsireg*` CSRs provided by the Sscsrind extensions.", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions > State Enable 0 Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 264, + 268 + ] + }, + { + "chunk_id": "chunk_44ddd04e", + "text": "The CSRIND bit in `hstateen0` controls access to the `siselect` and the `sireg*`, (really `vsiselect` and `vsireg*`) CSRs provided by the Sscsrind extensions.", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions > State Enable 0 Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 264, + 268 + ] + }, + { + "chunk_id": "chunk_5d160585", + "text": "The IMSIC bit in `mstateen0` controls access to the IMSIC state, including CSRs `stopei` and `vstopei`, provided by the Ssaia extension.", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions > State Enable 0 Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 270, + 273 + ] + }, + { + "chunk_id": "chunk_d7794bf3", + "text": "The IMSIC bit in `hstateen0` controls access to the guest IMSIC state, including CSRs `stopei` (really `vstopei`), provided by the Ssaia extension.", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions > State Enable 0 Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 270, + 273 + ] + }, + { + "chunk_id": "chunk_6b5a4da2", + "text": "The AIA bit in `mstateen0` controls access to all state introduced by the Ssaia extension and not controlled by either the CSRIND or the IMSIC bits.", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions > State Enable 0 Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 275, + 279 + ] + }, + { + "chunk_id": "chunk_3b3cb54d", + "text": "The AIA bit in `hstateen0` controls access to all state introduced by the Ssaia extension and not controlled by either the CSRIND or the IMSIC bits of `hstateen0`.", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions > State Enable 0 Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 275, + 279 + ] + }, + { + "chunk_id": "chunk_130df240", + "text": "The CONTEXT bit in `mstateen0` controls access to the `scontext` and `hcontext` CSRs provided by the Sdtrig extension.", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions > State Enable 0 Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 281, + 284 + ] + }, + { + "chunk_id": "chunk_00d41809", + "text": "The CONTEXT bit in `hstateen0` controls access to the `scontext` CSR provided by the Sdtrig extension.", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions > State Enable 0 Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 281, + 284 + ] + }, + { + "chunk_id": "chunk_204deed5", + "text": "The P1P13 bit in `mstateen0` controls access to the `hedelegh` introduced by Privileged Specification Version 1.13.", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions > State Enable 0 Registers", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 286, + 288 + ] + }, + { + "chunk_id": "chunk_45ed0a06", + "text": "The SRMCFG bit in `mstateen0` controls access to the `srmcfg` CSR introduced by the Ssqosid extension.", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions > State Enable 0 Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 290, + 292 + ] + }, + { + "chunk_id": "chunk_fafdbc35", + "text": "After the writable bits of the machine-level `mstateen` CSRs are initialized to zeros on reset, machine-level software can set bits in these registers to enable less-privileged access to the controlled state.", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions > Usage", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 296, + 304 + ] + }, + { + "chunk_id": "chunk_cd6942ae", + "text": "This may be either because machine-level software knows how to swap the state or, more likely, because machine-level software isn't swapping supervisor-level environments. (Recall that the main reason the `mstateen` CSRs must exist is so machine level can emulate the hypervisor extension.", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions > Usage", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 296, + 304 + ] + }, + { + "chunk_id": "chunk_854cc8a1", + "text": "When machine level isn't emulating the hypervisor extension, it is likely there will be no need to keep any implemented `mstateen` bits zero.)", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions > Usage", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 296, + 304 + ] + }, + { + "chunk_id": "chunk_072bab29", + "text": "If machine level sets any writable `mstateen` bits to nonzero, it must initialize the matching `hstateen` CSRs, if they exist, by writing zeros to them.", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions > Usage", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 306, + 311 + ] + }, + { + "chunk_id": "chunk_cc139555", + "text": "And if any `mstateen` bits that are set to one have matching bits in the `sstateen` CSRs, machine-level software must also initialize those `sstateen` CSRs by writing zeros to them.", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions > Usage", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 306, + 311 + ] + }, + { + "chunk_id": "chunk_0153048e", + "text": "Ordinarily, machine-level software will want to set bit 63 of all `mstateen` CSRs, necessitating that it write zero to all `hstateen` CSRs.", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions > Usage", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 306, + 311 + ] + }, + { + "chunk_id": "chunk_bed8f6e3", + "text": "Software should ensure that all writable bits of `sstateen` CSRs are initialized to zeros when an OS at supervisor level is first entered.", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions > Usage", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 313, + 316 + ] + }, + { + "chunk_id": "chunk_0c8f2b2f", + "text": "For the `sstateen` CSRs whose access by a guest OS is permitted by bit 63 of the corresponding `hstateen` CSRs, a hypervisor must include the `sstateen` CSRs in the context it swaps for a guest OS.", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions > Usage", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 318, + 322 + ] + }, + { + "chunk_id": "chunk_9a127dc0", + "text": "When it starts a new guest OS, it must ensure the writable bits of those `sstateen` CSRs are initialized to zeros, and it must emulate accesses to any other `sstateen` CSRs.", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions > Usage", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 318, + 322 + ] + }, + { + "chunk_id": "chunk_d5c477bb", + "text": "If software at any privilege level does not support multiple contexts for less-privilege levels, then it may choose to maximize less-privileged access to all state by writing a value of all ones to the `stateen` CSRs at its level (the `mstateen` CSRs for machine level, the `sstateen` CSRs for an OS, and the `hstateen` CSRs for a hypervisor), without knowing all the state to which it is granting access.", + "source_file": "src/priv/smstateen.adoc", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions > Usage", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 324, + 333 + ] + } + ] + }, + { + "file": "src/priv/ssccptr.adoc", + "chunks": [ + { + "chunk_id": "chunk_645ba08b", + "text": "If the Ssccptr extension is implemented, then main memory regions with both the cacheability and coherence PMAs must support hardware page-table reads.", + "source_file": "src/priv/ssccptr.adoc", + "section": "Preamble > Ssccptr Extension for Main Memory Page-Table Reads, Version 1.0", + "confidence": "very_high", + "parameter_class": "SW_rule", + "parameter_type": "binary", + "line_range": [ + 3, + 4 + ] + } + ] + }, + { + "file": "src/priv/sscofpmf.adoc", + "chunks": [ + { + "chunk_id": "chunk_38122cb5", + "text": "The current Privileged specification defines mhpmevent CSRs to select and control event counting by the associated hpmcounter CSRs, but provides no standardization of any fields within these CSRs.", + "source_file": "src/priv/sscofpmf.adoc", + "section": "Preamble > \"Sscofpmf\" Extension for Count Overflow and Mode-Based Filtering, Version 1.0", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 3, + 10 + ] + }, + { + "chunk_id": "chunk_4cd40f48", + "text": "This extension serves to accomplish exactly this within the existing mhpmevent CSRs (and correspondingly avoids the unnecessary creation of whole new sets of CSRs - past just one new CSR).", + "source_file": "src/priv/sscofpmf.adoc", + "section": "Preamble > \"Sscofpmf\" Extension for Count Overflow and Mode-Based Filtering, Version 1.0", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 12, + 14 + ] + }, + { + "chunk_id": "chunk_4c94a103", + "text": "The following bits are added to `mhpmevent`:", + "source_file": "src/priv/sscofpmf.adoc", + "section": "Preamble > \"Sscofpmf\" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 30, + 30 + ] + }, + { + "chunk_id": "chunk_1e59997e", + "text": "[cols=\"^1,^1,^1,^1,^1,^1,^1,^1\",stripes=even,options=\"header\"] | |63 |62 |61 |60 |59 |58 |57 |56 |OF |MINH |SINH |UINH |VSINH |VUINH |WPRI |WPRI |", + "source_file": "src/priv/sscofpmf.adoc", + "section": "Preamble > \"Sscofpmf\" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 32, + 36 + ] + }, + { + "chunk_id": "chunk_f0f6efc5", + "text": "[cols=\"15%,85%\",options=\"header\"] | | Field | Description | OF | Overflow status and interrupt disable bit that is set when counter overflows | MINH |", + "source_file": "src/priv/sscofpmf.adoc", + "section": "Preamble > \"Sscofpmf\" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 38, + 49 + ] + }, + { + "chunk_id": "chunk_a0a92c01", + "text": "If set, then counting of events in M-mode is inhibited | SINH |", + "source_file": "src/priv/sscofpmf.adoc", + "section": "Preamble > \"Sscofpmf\" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 38, + 49 + ] + }, + { + "chunk_id": "chunk_81feab7c", + "text": "If set, then counting of events in S/HS-mode is inhibited | UINH |", + "source_file": "src/priv/sscofpmf.adoc", + "section": "Preamble > \"Sscofpmf\" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 38, + 49 + ] + }, + { + "chunk_id": "chunk_a93cfc48", + "text": "If set, then counting of events in U-mode is inhibited | VSINH |", + "source_file": "src/priv/sscofpmf.adoc", + "section": "Preamble > \"Sscofpmf\" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 38, + 49 + ] + }, + { + "chunk_id": "chunk_08dc351d", + "text": "If set, then counting of events in VS-mode is inhibited | VUINH |", + "source_file": "src/priv/sscofpmf.adoc", + "section": "Preamble > \"Sscofpmf\" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 38, + 49 + ] + }, + { + "chunk_id": "chunk_4a00819f", + "text": "If set, then counting of events in VU-mode is inhibited | WPRI | Reserved | WPRI | Reserved |", + "source_file": "src/priv/sscofpmf.adoc", + "section": "Preamble > \"Sscofpmf\" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 38, + 49 + ] + }, + { + "chunk_id": "chunk_8b07ffdd", + "text": "For each ``x``INH bit, if the associated privilege mode is not implemented, the bit is read-only zero.", + "source_file": "src/priv/sscofpmf.adoc", + "section": "Preamble > \"Sscofpmf\" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 51, + 52 + ] + }, + { + "chunk_id": "chunk_5ec72fdd", + "text": "Each of the five ``x``INH bits, when set, inhibit counting of events while in privilege mode ``x``.", + "source_file": "src/priv/sscofpmf.adoc", + "section": "Preamble > \"Sscofpmf\" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 54, + 57 + ] + }, + { + "chunk_id": "chunk_130aea5f", + "text": "All-zeroes for these bits results in counting of events in all modes.", + "source_file": "src/priv/sscofpmf.adoc", + "section": "Preamble > \"Sscofpmf\" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 54, + 57 + ] + }, + { + "chunk_id": "chunk_dc9733f3", + "text": "The OF bit is set when the corresponding hpmcounter overflows, and remains set until written by software.", + "source_file": "src/priv/sscofpmf.adoc", + "section": "Preamble > \"Sscofpmf\" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 59, + 63 + ] + }, + { + "chunk_id": "chunk_b952b228", + "text": "Since hpmcounter values are unsigned values, overflow is defined as unsigned overflow of the implemented counter bits.", + "source_file": "src/priv/sscofpmf.adoc", + "section": "Preamble > \"Sscofpmf\" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 59, + 63 + ] + }, + { + "chunk_id": "chunk_05505729", + "text": "If supervisor mode is implemented, the 32-bit scountovf register contains read-only shadow copies of the OF bits in all 29 mhpmevent registers.", + "source_file": "src/priv/sscofpmf.adoc", + "section": "Preamble > \"Sscofpmf\" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 65, + 66 + ] + }, + { + "chunk_id": "chunk_41299b0f", + "text": "If an hpmcounter overflows while the associated OF bit is zero, then a \"count overflow interrupt request\" is generated.", + "source_file": "src/priv/sscofpmf.adoc", + "section": "Preamble > \"Sscofpmf\" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 68, + 72 + ] + }, + { + "chunk_id": "chunk_552be716", + "text": "If the OF bit is one, then no interrupt request is generated.", + "source_file": "src/priv/sscofpmf.adoc", + "section": "Preamble > \"Sscofpmf\" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 68, + 72 + ] + }, + { + "chunk_id": "chunk_57fd774b", + "text": "Consequently the OF bit also functions as a count overflow interrupt disable for the associated hpmcounter.", + "source_file": "src/priv/sscofpmf.adoc", + "section": "Preamble > \"Sscofpmf\" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 68, + 72 + ] + }, + { + "chunk_id": "chunk_c1263bcc", + "text": "Count overflow never results from writes to the mhpmcountern or mhpmeventn registers, only from hardware increments of counter registers.", + "source_file": "src/priv/sscofpmf.adoc", + "section": "Preamble > \"Sscofpmf\" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 74, + 76 + ] + }, + { + "chunk_id": "chunk_b82df2fb", + "text": "This count-overflow-interrupt-request signal is treated as a standard local interrupt that corresponds to bit 13 in the `mip`/`mie`/`sip`/`sie` registers.", + "source_file": "src/priv/sscofpmf.adoc", + "section": "Preamble > \"Sscofpmf\" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 78, + 82 + ] + }, + { + "chunk_id": "chunk_ded338b3", + "text": "The `mip`/`sip` LCOFIP and `mie`/`sie` LCOFIE bits are, respectively, the interrupt-pending and interrupt-enable bits for this interrupt. ('LCOFI' represents 'Local Count Overflow Interrupt'.)", + "source_file": "src/priv/sscofpmf.adoc", + "section": "Preamble > \"Sscofpmf\" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 78, + 82 + ] + }, + { + "chunk_id": "chunk_02796860", + "text": "Generation of a count-overflow-interrupt request by an `hpmcounter` sets the associated OF bit.", + "source_file": "src/priv/sscofpmf.adoc", + "section": "Preamble > \"Sscofpmf\" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 84, + 90 + ] + }, + { + "chunk_id": "chunk_dd7f2532", + "text": "When an OF bit is set, it eventually, but not necessarily immediately, sets the LCOFIP bit in the `mip`/`sip` registers.", + "source_file": "src/priv/sscofpmf.adoc", + "section": "Preamble > \"Sscofpmf\" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 84, + 90 + ] + }, + { + "chunk_id": "chunk_b5aa7906", + "text": "The LCOFIP bit is cleared by software before servicing the count overflow interrupt resulting from one or more count overflows.", + "source_file": "src/priv/sscofpmf.adoc", + "section": "Preamble > \"Sscofpmf\" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 84, + 90 + ] + }, + { + "chunk_id": "chunk_4100a2ea", + "text": "The `mideleg` register controls the delegation of this interrupt to S-mode versus M-mode.", + "source_file": "src/priv/sscofpmf.adoc", + "section": "Preamble > \"Sscofpmf\" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 84, + 90 + ] + }, + { + "chunk_id": "chunk_3d279abb", + "text": "This extension adds the `scountovf` CSR, a 32-bit read-only register that contains shadow copies of the OF bits in the 29 mhpmevent CSRs (mhpmevent3 - mhpmevent31) - where scountovf bit X corresponds to mhpmeventX.", + "source_file": "src/priv/sscofpmf.adoc", + "section": "Preamble > \"Sscofpmf\" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control > Supervisor Count Overflow (`scountovf`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 94, + 98 + ] + }, + { + "chunk_id": "chunk_d0a27286", + "text": "This register enables supervisor-level overflow interrupt handler software to quickly and easily determine which counter(s) have overflowed (without needing to make an execution environment call or series of calls ultimately up to M-mode).", + "source_file": "src/priv/sscofpmf.adoc", + "section": "Preamble > \"Sscofpmf\" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control > Supervisor Count Overflow (`scountovf`) Register", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 100, + 103 + ] + }, + { + "chunk_id": "chunk_252a37a6", + "text": "Read access to bit X is subject to the same mcounteren (or mcounteren and hcounteren) CSRs that mediate access to the hpmcounter CSRs by S-mode (or VS-mode).", + "source_file": "src/priv/sscofpmf.adoc", + "section": "Preamble > \"Sscofpmf\" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control > Supervisor Count Overflow (`scountovf`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 105, + 110 + ] + }, + { + "chunk_id": "chunk_88bcdb03", + "text": "In M-mode, scountovf bit X is always readable.", + "source_file": "src/priv/sscofpmf.adoc", + "section": "Preamble > \"Sscofpmf\" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control > Supervisor Count Overflow (`scountovf`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 105, + 110 + ] + }, + { + "chunk_id": "chunk_5ea06e91", + "text": "In S/HS-mode, scountovf bit X is readable when mcounteren bit X is set, and otherwise reads as zero.", + "source_file": "src/priv/sscofpmf.adoc", + "section": "Preamble > \"Sscofpmf\" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control > Supervisor Count Overflow (`scountovf`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 105, + 110 + ] + }, + { + "chunk_id": "chunk_6187dfa9", + "text": "Similarly, in VS mode, scountovf bit X is readable when mcounteren bit X and hcounteren bit X are both set, and otherwise reads as zero.", + "source_file": "src/priv/sscofpmf.adoc", + "section": "Preamble > \"Sscofpmf\" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control > Supervisor Count Overflow (`scountovf`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 105, + 110 + ] + } + ] + }, + { + "file": "src/priv/sscounterenw.adoc", + "chunks": [ + { + "chunk_id": "chunk_79a40914", + "text": "If the Sscounterenw extension is implemented, then for any `hpmcounter` that is not read-only zero, the corresponding bit in `scounteren` must be writable.", + "source_file": "src/priv/sscounterenw.adoc", + "section": "Preamble > Sscounterenw Extension for Counter-Enable Writability, Version 1.0", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 3, + 4 + ] + } + ] + }, + { + "file": "src/priv/ssdbltrp.adoc", + "chunks": [ + { + "chunk_id": "chunk_9be67576", + "text": "It enables HS-mode to invoke a critical error handler in a virtual machine on a double trap in VS-mode.", + "source_file": "src/priv/ssdbltrp.adoc", + "section": "Preamble > \"Ssdbltrp\" Double Trap Extension, Version 1.0", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 3, + 7 + ] + }, + { + "chunk_id": "chunk_1a45ecb6", + "text": "It also allows M-mode to invoke a critical error handler in the OS/Hypervisor on a double trap in S/HS-mode.", + "source_file": "src/priv/ssdbltrp.adoc", + "section": "Preamble > \"Ssdbltrp\" Double Trap Extension, Version 1.0", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 3, + 7 + ] + } + ] + }, + { + "file": "src/priv/ssqosid.adoc", + "chunks": [ + { + "chunk_id": "chunk_14c95ffe", + "text": "When multiple workloads execute concurrently on modern processors\u2014equipped with large core counts, multiple cache hierarchies, and multiple memory controllers\u2014 the performance of any given workload becomes less deterministic, or even non-deterministic, due to shared resource contention.", + "source_file": "src/priv/ssqosid.adoc", + "section": "Preamble > \"Ssqosid\" Extension for Quality-of-Service (QoS) Identifiers, Version 1.0", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 8, + 11 + ] + }, + { + "chunk_id": "chunk_4971e847", + "text": "For resource management, hardware should provide monitoring features that allow system software to profile workload resource consumption and allocate resources accordingly.", + "source_file": "src/priv/ssqosid.adoc", + "section": "Preamble > \"Ssqosid\" Extension for Quality-of-Service (QoS) Identifiers, Version 1.0", + "confidence": "medium", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 13, + 19 + ] + }, + { + "chunk_id": "chunk_a67581c7", + "text": "Resource controllers may use this metadata for differentiated service such as a different capacity allocation for code storage vs. data storage.", + "source_file": "src/priv/ssqosid.adoc", + "section": "Preamble > \"Ssqosid\" Extension for Quality-of-Service (QoS) Identifiers, Version 1.0", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 26, + 31 + ] + }, + { + "chunk_id": "chunk_0f7c8806", + "text": "The `srmcfg` register is an SXLEN-bit read/write register used to configure a Resource Control ID (`RCID`) and a Monitoring Counter ID (`MCID`).", + "source_file": "src/priv/ssqosid.adoc", + "section": "Preamble > \"Ssqosid\" Extension for Quality-of-Service (QoS) Identifiers, Version 1.0 > Supervisor Resource Management Configuration (`srmcfg`) register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 44, + 47 + ] + }, + { + "chunk_id": "chunk_ab60fe2b", + "text": "Both `RCID` and `MCID` are WARL fields.", + "source_file": "src/priv/ssqosid.adoc", + "section": "Preamble > \"Ssqosid\" Extension for Quality-of-Service (QoS) Identifiers, Version 1.0 > Supervisor Resource Management Configuration (`srmcfg`) register", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 44, + 47 + ] + }, + { + "chunk_id": "chunk_9ce9cb34", + "text": "The register is formatted as shown in when SXLEN=64 and when SXLEN=32.", + "source_file": "src/priv/ssqosid.adoc", + "section": "Preamble > \"Ssqosid\" Extension for Quality-of-Service (QoS) Identifiers, Version 1.0 > Supervisor Resource Management Configuration (`srmcfg`) register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 44, + 47 + ] + }, + { + "chunk_id": "chunk_665022e4", + "text": "The `RCID` and `MCID` accompany each request made by the hart to shared resource controllers.", + "source_file": "src/priv/ssqosid.adoc", + "section": "Preamble > \"Ssqosid\" Extension for Quality-of-Service (QoS) Identifiers, Version 1.0 > Supervisor Resource Management Configuration (`srmcfg`) register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 49, + 52 + ] + }, + { + "chunk_id": "chunk_822de12c", + "text": "The `MCID` is used to identify a counter to monitor resource usage.", + "source_file": "src/priv/ssqosid.adoc", + "section": "Preamble > \"Ssqosid\" Extension for Quality-of-Service (QoS) Identifiers, Version 1.0 > Supervisor Resource Management Configuration (`srmcfg`) register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 49, + 52 + ] + }, + { + "chunk_id": "chunk_bc2e8718", + "text": "The `RCID` and `MCID` configured in the `srmcfg` CSR apply to all privilege modes of software execution on that hart by default, but this behavior may be overridden by future extensions.", + "source_file": "src/priv/ssqosid.adoc", + "section": "Preamble > \"Ssqosid\" Extension for Quality-of-Service (QoS) Identifiers, Version 1.0 > Supervisor Resource Management Configuration (`srmcfg`) register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 80, + 82 + ] + }, + { + "chunk_id": "chunk_9df40c16", + "text": "If extension Smstateen is implemented together with Ssqosid, then Ssqosid also requires the SRMCFG bit in `mstateen0` to be implemented.", + "source_file": "src/priv/ssqosid.adoc", + "section": "Preamble > \"Ssqosid\" Extension for Quality-of-Service (QoS) Identifiers, Version 1.0 > Supervisor Resource Management Configuration (`srmcfg`) register", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 84, + 89 + ] + }, + { + "chunk_id": "chunk_3a72c478", + "text": "If `mstateen0`.SRMCFG is 0, attempts to access `srmcfg` in privilege modes less privileged than M-mode raise an illegal-instruction exception.", + "source_file": "src/priv/ssqosid.adoc", + "section": "Preamble > \"Ssqosid\" Extension for Quality-of-Service (QoS) Identifiers, Version 1.0 > Supervisor Resource Management Configuration (`srmcfg`) register", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 84, + 89 + ] + }, + { + "chunk_id": "chunk_2bc0efa4", + "text": "If `mstateen0`.SRMCFG is 1 or if extension Smstateen is not implemented, attempts to access `srmcfg` when `V=1` raise a virtual-instruction exception.", + "source_file": "src/priv/ssqosid.adoc", + "section": "Preamble > \"Ssqosid\" Extension for Quality-of-Service (QoS) Identifiers, Version 1.0 > Supervisor Resource Management Configuration (`srmcfg`) register", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 84, + 89 + ] + } + ] + }, + { + "file": "src/priv/ssstrict.adoc", + "chunks": [ + { + "chunk_id": "chunk_9ac14be5", + "text": "If the Ssstrict extension is implemented, then no non-conforming extensions are present.", + "source_file": "src/priv/ssstrict.adoc", + "section": "Preamble > Ssstrict Extension for Extension Conformance, Version 1.0", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 3, + 8 + ] + }, + { + "chunk_id": "chunk_efac294c", + "text": "Furthermore, attempts to execute unimplemented opcodes or access unimplemented CSRs in the standard or reserved encoding spaces raises an illegal instruction exception that results in a contained trap to the supervisor-mode trap handler.", + "source_file": "src/priv/ssstrict.adoc", + "section": "Preamble > Ssstrict Extension for Extension Conformance, Version 1.0", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 3, + 8 + ] + } + ] + }, + { + "file": "src/priv/sstc.adoc", + "chunks": [ + { + "chunk_id": "chunk_73f30ac9", + "text": "The current Privileged arch specification only defines a hardware mechanism for generating machine-mode timer interrupts (based on the mtime and mtimecmp registers).", + "source_file": "src/priv/sstc.adoc", + "section": "Preamble > \"Sstc\" Extension for Supervisor-mode Timer Interrupts, Version 1.0", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 3, + 10 + ] + }, + { + "chunk_id": "chunk_b1a7a46d", + "text": "With the resultant requirement that timer services for S-mode/HS-mode (and for VS-mode) have to all be provided by M-mode - via SBI calls from S/HS-mode up to M-mode (or VS-mode calls to HS-mode and then to M-mode). M-mode software then multiplexes these multiple logical timers onto its one physical M-mode timer facility, and the M-mode timer interrupt handler passes timer interrupts back down to the appropriate lower privilege mode.", + "source_file": "src/priv/sstc.adoc", + "section": "Preamble > \"Sstc\" Extension for Supervisor-mode Timer Interrupts, Version 1.0", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 3, + 10 + ] + }, + { + "chunk_id": "chunk_d23fd309", + "text": "This extension serves to provide supervisor mode with its own CSR-based timer interrupt facility that it can directly manage to provide its own timer service (in the form of having its own `stimecmp` register) - thus eliminating the large overheads for emulating S/HS-mode timers and timer interrupt generation up in M-mode.", + "source_file": "src/priv/sstc.adoc", + "section": "Preamble > \"Sstc\" Extension for Supervisor-mode Timer Interrupts, Version 1.0", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 12, + 17 + ] + }, + { + "chunk_id": "chunk_e641060d", + "text": "This extension adds the S-level `stimecmp` CSR () and the VS-level `vstimecmp` CSR ().", + "source_file": "src/priv/sstc.adoc", + "section": "Preamble > \"Sstc\" Extension for Supervisor-mode Timer Interrupts, Version 1.0", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 19, + 23 + ] + }, + { + "chunk_id": "chunk_27458ddc", + "text": "This extension adds the `STCE` bit to the `menvcfg` () and `henvcfg` () CSRs.", + "source_file": "src/priv/sstc.adoc", + "section": "Preamble > \"Sstc\" Extension for Supervisor-mode Timer Interrupts, Version 1.0", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 19, + 23 + ] + } + ] + }, + { + "file": "src/priv/sstvala.adoc", + "chunks": [ + { + "chunk_id": "chunk_57aa35ec", + "text": "If the Sstvala extension is implemented, then `stval` must be written with the faulting virtual address for load, store, and instruction page-fault, access-fault, and misaligned exceptions, and for breakpoint exceptions that are defined to write an address to stval, other than those caused by execution of the `EBREAK` or `C.EBREAK` instructions.", + "source_file": "src/priv/sstvala.adoc", + "section": "Preamble > Sstvala Extension for Trap Value Reporting, Version 1.0", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 3, + 9 + ] + }, + { + "chunk_id": "chunk_b78e9bc7", + "text": "For virtual-instruction and illegal-instruction exceptions, `stval` must be written with the faulting instruction.", + "source_file": "src/priv/sstvala.adoc", + "section": "Preamble > Sstvala Extension for Trap Value Reporting, Version 1.0", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 3, + 9 + ] + } + ] + }, + { + "file": "src/priv/sstvecd.adoc", + "chunks": [ + { + "chunk_id": "chunk_41405924", + "text": "If the Sstvecd extension is implemented, then `stvec.MODE` must be capable of holding the value 0 (Direct).", + "source_file": "src/priv/sstvecd.adoc", + "section": "Preamble > Sstvecd Extension for Direct Trap Vectoring, Version 1.0", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 3, + 6 + ] + }, + { + "chunk_id": "chunk_48cc8229", + "text": "Furthermore, when `stvec.MODE=Direct`, `stvec.BASE` must be capable of holding any valid four-byte-aligned address.", + "source_file": "src/priv/sstvecd.adoc", + "section": "Preamble > Sstvecd Extension for Direct Trap Vectoring, Version 1.0", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 3, + 6 + ] + } + ] + }, + { + "file": "src/priv/ssu64xl.adoc", + "chunks": [ + { + "chunk_id": "chunk_a1fc1e3b", + "text": "If the Ssu64xl extension is implemented, then `sstatus.UXL` must be capable of holding the value 2 (i.e., UXLEN=64 must be supported).", + "source_file": "src/priv/ssu64xl.adoc", + "section": "Preamble > Ssu64xl Extension for UXLEN=64 Support, Version 1.0", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 3, + 4 + ] + } + ] + }, + { + "file": "src/priv/supervisor.adoc", + "chunks": [ + { + "chunk_id": "chunk_f25654ae", + "text": "A number of CSRs are provided for the supervisor.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 9, + 9 + ] + }, + { + "chunk_id": "chunk_54181556", + "text": "The `sstatus` register is an SXLEN-bit read/write register formatted as shown in when SXLEN=32 and when SXLEN=64.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 14, + 18 + ] + }, + { + "chunk_id": "chunk_63e0692e", + "text": "The `sstatus` register keeps track of the processor's current operating state.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 14, + 18 + ] + }, + { + "chunk_id": "chunk_de778c2a", + "text": "The SPP bit indicates the privilege level at which a hart was executing before entering supervisor mode.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 76, + 83 + ] + }, + { + "chunk_id": "chunk_63987dc9", + "text": "When a trap is taken, SPP is set to 0 if the trap originated from user mode, or 1 otherwise.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 76, + 83 + ] + }, + { + "chunk_id": "chunk_71dbf032", + "text": "The SIE bit enables or disables all interrupts in supervisor mode.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 85, + 90 + ] + }, + { + "chunk_id": "chunk_aa5b09d7", + "text": "When SIE is clear, interrupts are not taken while in supervisor mode.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 85, + 90 + ] + }, + { + "chunk_id": "chunk_747cd038", + "text": "When the hart is running in user-mode, the value in SIE is ignored, and supervisor-level interrupts are enabled.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 85, + 90 + ] + }, + { + "chunk_id": "chunk_f3430c38", + "text": "The supervisor can disable individual interrupt sources using the `sie` CSR.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 85, + 90 + ] + }, + { + "chunk_id": "chunk_885fa826", + "text": "The SPIE bit indicates whether supervisor interrupts were enabled prior to trapping into supervisor mode.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 92, + 96 + ] + }, + { + "chunk_id": "chunk_835eed4b", + "text": "When a trap is taken into supervisor mode, SPIE is set to SIE, and SIE is set to 0.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 92, + 96 + ] + }, + { + "chunk_id": "chunk_7b81b37f", + "text": "When an SRET instruction is executed, SIE is set to SPIE, then SPIE is set to 1.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 92, + 96 + ] + }, + { + "chunk_id": "chunk_d67668e0", + "text": "The `sstatus` register is a subset of the `mstatus` register.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 98, + 98 + ] + }, + { + "chunk_id": "chunk_fe705b60", + "text": "The UXL field controls the value of XLEN for U-mode, termed UXLEN, which may differ from the value of XLEN for S-mode, termed SXLEN.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Base ISA Control in `sstatus` Register", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 102, + 106 + ] + }, + { + "chunk_id": "chunk_3fc59373", + "text": "The encoding of UXL is the same as that of the MXL field of `misa`, shown in .", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Base ISA Control in `sstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 102, + 106 + ] + }, + { + "chunk_id": "chunk_5997f0a7", + "text": "When SXLEN=32, the UXL field does not exist, and UXLEN=32.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Base ISA Control in `sstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 108, + 112 + ] + }, + { + "chunk_id": "chunk_8f23f2a7", + "text": "When SXLEN=64, it is a *WARL* field that encodes the current value of UXLEN.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Base ISA Control in `sstatus` Register", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 108, + 112 + ] + }, + { + "chunk_id": "chunk_65977b71", + "text": "In particular, an implementation may make UXL be a read-only field whose value always ensures that UXLEN=SXLEN.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Base ISA Control in `sstatus` Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 108, + 112 + ] + }, + { + "chunk_id": "chunk_da142b34", + "text": "If UXLEN!=SXLEN, instructions executed in the narrower mode must ignore source register operand bits above the configured XLEN, and must sign-extend results to fill the widest supported XLEN in the destination register.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Base ISA Control in `sstatus` Register", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 114, + 118 + ] + }, + { + "chunk_id": "chunk_5c7ca72c", + "text": "If UXLEN < SXLEN, user-mode instruction-fetch addresses and load and store effective addresses are taken modulo 2^UXLEN^.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Base ISA Control in `sstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 120, + 123 + ] + }, + { + "chunk_id": "chunk_edc7df9b", + "text": "When such a HINT is executed with XLEN < SXLEN and bits SXLEN..XLEN of the destination register not all equal to bit XLEN-1, it is implementation-defined whether bits SXLEN..XLEN of the destination register are unchanged or are overwritten with copies of bit XLEN-1.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Base ISA Control in `sstatus` Register", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 125, + 132 + ] + }, + { + "chunk_id": "chunk_e24766a0", + "text": "The implementation choice is observable only by S-mode with SXLEN > UXLEN; it is invisible to U-mode.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Base ISA Control in `sstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 134, + 138 + ] + }, + { + "chunk_id": "chunk_0250015b", + "text": "The MXR (Make eXecutable Readable) bit modifies the privilege with which loads access virtual memory.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Memory Privilege in `sstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 143, + 149 + ] + }, + { + "chunk_id": "chunk_cb5c0166", + "text": "When MXR=0, only loads from pages marked readable (R=1 in ) will succeed.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Memory Privilege in `sstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 143, + 149 + ] + }, + { + "chunk_id": "chunk_a44d7762", + "text": "When MXR=1, loads from pages marked either readable or executable (R=1 or X=1) will succeed. MXR has no effect when page-based virtual memory is not in effect.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Memory Privilege in `sstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 143, + 149 + ] + }, + { + "chunk_id": "chunk_50c3324c", + "text": "The SUM (permit Supervisor User Memory access) bit modifies the privilege with which S-mode loads and stores access virtual memory.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Memory Privilege in `sstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 151, + 159 + ] + }, + { + "chunk_id": "chunk_17a302c5", + "text": "When SUM=0, S-mode memory accesses to pages that are accessible by U-mode (U=1 in ) will fault.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Memory Privilege in `sstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 151, + 159 + ] + }, + { + "chunk_id": "chunk_cd21ff8c", + "text": "When SUM=1, these accesses are permitted. SUM has no effect when page-based virtual memory is not in effect, nor when executing in U-mode.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Memory Privilege in `sstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 151, + 159 + ] + }, + { + "chunk_id": "chunk_d93e9f16", + "text": "SUM is read-only 0 if `satp`.MODE is read-only 0.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Memory Privilege in `sstatus` Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 161, + 162 + ] + }, + { + "chunk_id": "chunk_92c68a14", + "text": "The UBE bit is a *WARL* field that controls the endianness of explicit memory accesses made from U-mode, which may differ from the endianness of memory accesses in S-mode.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Endianness Control in `sstatus` Register", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 166, + 170 + ] + }, + { + "chunk_id": "chunk_1a29bfb8", + "text": "An implementation may make UBE be a read-only field that always specifies the same endianness as for S-mode.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Endianness Control in `sstatus` Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 166, + 170 + ] + }, + { + "chunk_id": "chunk_75f4203b", + "text": "UBE controls whether explicit load and store memory accesses made from U-mode are little-endian (UBE=0) or big-endian (UBE=1).", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Endianness Control in `sstatus` Register", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 172, + 173 + ] + }, + { + "chunk_id": "chunk_1447b71c", + "text": "UBE has no effect on instruction fetches, which are implicit memory accesses that are always little-endian.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Endianness Control in `sstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 175, + 177 + ] + }, + { + "chunk_id": "chunk_4a83dc5c", + "text": "For implicit accesses to supervisor-level memory management data structures, such as page tables, S-mode endianness always applies and UBE is ignored.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Endianness Control in `sstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 179, + 181 + ] + }, + { + "chunk_id": "chunk_83157bc9", + "text": "Access to the `SPELP` field, added by Zicfilp, accesses the homonymous fields of `mstatus` when `V=0`, and the homonymous fields of `vsstatus` when `V=1`.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Previous Expected Landing Pad (ELP) State in `sstatus` Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 185, + 188 + ] + }, + { + "chunk_id": "chunk_17d9aa3a", + "text": "When the `SDT` bit is set to 1 by an explicit CSR write, the `SIE` (Supervisor Interrupt Enable) bit is cleared to 0.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Double Trap Control in `sstatus` Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 198, + 203 + ] + }, + { + "chunk_id": "chunk_15550752", + "text": "This clearing occurs regardless of the value written, if any, to the `SIE` bit by the same write.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Double Trap Control in `sstatus` Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 198, + 203 + ] + }, + { + "chunk_id": "chunk_b242f0d1", + "text": "The `SIE` bit can only be set to 1 by an explicit CSR write if the `SDT` bit is being set to 0 by the same write or is already 0.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Double Trap Control in `sstatus` Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 198, + 203 + ] + }, + { + "chunk_id": "chunk_40c9933b", + "text": "When a trap is to be taken into S-mode, if the `SDT` bit is currently 0, it is then set to 1, and the trap is delivered as expected.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Double Trap Control in `sstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 205, + 214 + ] + }, + { + "chunk_id": "chunk_84d67d22", + "text": "However, if `SDT` is already set to 1, then this is an unexpected trap.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Double Trap Control in `sstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 205, + 214 + ] + }, + { + "chunk_id": "chunk_3b054108", + "text": "In the event of an unexpected trap, a double-trap exception trap is delivered into M-mode.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Double Trap Control in `sstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 205, + 214 + ] + }, + { + "chunk_id": "chunk_c75db91f", + "text": "To deliver this trap, the hart writes registers, except `mcause` and `mtval2`, with the same information that the unexpected trap would have written if it was taken into M-mode.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Double Trap Control in `sstatus` Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 205, + 214 + ] + }, + { + "chunk_id": "chunk_d579b146", + "text": "The `mtval2` register is then set to what would be otherwise written into the `mcause` register by the unexpected trap.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Double Trap Control in `sstatus` Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 205, + 214 + ] + }, + { + "chunk_id": "chunk_7a4d3133", + "text": "The `mcause` register is set to 16, the double-trap exception code.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Double Trap Control in `sstatus` Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 205, + 214 + ] + }, + { + "chunk_id": "chunk_e8e5d179", + "text": "An `SRET` instruction sets the `SDT` bit to 0.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Double Trap Control in `sstatus` Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 216, + 217 + ] + }, + { + "chunk_id": "chunk_00231009", + "text": "The `stvec` register is an SXLEN-bit read/write register that holds trap vector configuration, consisting of a vector base address (BASE) and a vector mode (MODE).", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Vector Base Address (`stvec`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 221, + 224 + ] + }, + { + "chunk_id": "chunk_77594abf", + "text": "The BASE field in `stvec` is a field that can hold any valid virtual or physical address, subject to the following alignment constraints: the address must be 4-byte aligned, and MODE settings other than Direct might impose additional alignment constraints on the value in the BASE field.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Vector Base Address (`stvec`) Register", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 230, + 239 + ] + }, + { + "chunk_id": "chunk_a9728561", + "text": "When used as an address, the lower two bits are filled with zeroes to obtain an XLEN-bit address that is always aligned on a 4-byte boundary.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Vector Base Address (`stvec`) Register", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 230, + 239 + ] + }, + { + "chunk_id": "chunk_5a617a99", + "text": "The encoding of the MODE field is shown in .", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Vector Base Address (`stvec`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 256, + 265 + ] + }, + { + "chunk_id": "chunk_39b32a6a", + "text": "When MODE=Direct, all traps into supervisor mode cause the `pc` to be set to the address in the BASE field.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Vector Base Address (`stvec`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 256, + 265 + ] + }, + { + "chunk_id": "chunk_210ff355", + "text": "When MODE=Vectored, all synchronous exceptions into supervisor mode cause the `pc` to be set to the address in the BASE field, whereas interrupts cause the `pc` to be set to the address in the BASE field plus four times the interrupt cause number.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Vector Base Address (`stvec`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 256, + 265 + ] + }, + { + "chunk_id": "chunk_06b51d51", + "text": "Setting MODE=Vectored may impose a stricter alignment constraint on BASE.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Vector Base Address (`stvec`) Register", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 256, + 265 + ] + }, + { + "chunk_id": "chunk_3ba5c989", + "text": "The `sip` register is an SXLEN-bit read/write register containing information on pending interrupts, while `sie` is the corresponding SXLEN-bit read/write register containing interrupt enable bits.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 269, + 276 + ] + }, + { + "chunk_id": "chunk_02b70345", + "text": "Interrupt cause number i (as reported in CSR `scause`, ) corresponds with bit i in both `sip` and `sie`.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 269, + 276 + ] + }, + { + "chunk_id": "chunk_d6824594", + "text": "Bits 15:0 are allocated to standard interrupt causes only, while bits 16 and above are designated for platform use.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 269, + 276 + ] + }, + { + "chunk_id": "chunk_e26004db", + "text": "An interrupt i will trap to S-mode if both of the following are true: (a) either the current privilege mode is S and the SIE bit in the `sstatus` register is set, or the current privilege mode has less privilege than S-mode; and (b) bit i is set in both `sip` and `sie`.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 284, + 288 + ] + }, + { + "chunk_id": "chunk_e840808b", + "text": "These conditions for an interrupt trap to occur must be evaluated in a bounded amount of time from when an interrupt becomes, or ceases to be, pending in `sip`, and must also be evaluated immediately following the execution of an SRET instruction or an explicit write to a CSR on which these interrupt trap conditions expressly depend (including `sip`, `sie` and `sstatus`).", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 290, + 296 + ] + }, + { + "chunk_id": "chunk_1b0a0ccb", + "text": "Interrupts to S-mode take priority over any interrupts to lower privilege modes.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 298, + 300 + ] + }, + { + "chunk_id": "chunk_bba95e36", + "text": "Each individual bit in register `sip` may be writable or may be read-only.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 302, + 307 + ] + }, + { + "chunk_id": "chunk_2898268e", + "text": "When bit i in `sip` is writable, a pending interrupt i can be cleared by writing 0 to this bit.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 302, + 307 + ] + }, + { + "chunk_id": "chunk_66af41fd", + "text": "If interrupt i can become pending but bit i in `sip` is read-only, the implementation must provide some other mechanism for clearing the pending interrupt (which may involve a call to the execution environment).", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 302, + 307 + ] + }, + { + "chunk_id": "chunk_4d36b896", + "text": "A bit in `sie` must be writable if the corresponding interrupt can ever become pending.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 309, + 310 + ] + }, + { + "chunk_id": "chunk_f1ea7265", + "text": "Bits of `sie` that are not writable are read-only zero.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 309, + 310 + ] + }, + { + "chunk_id": "chunk_dfca4c2f", + "text": "The standard portions (bits 15:0) of registers `sip` and `sie` are formatted as shown in Figures and respectively.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 312, + 315 + ] + }, + { + "chunk_id": "chunk_9de9f2ad", + "text": "Bits `sip`.SEIP and `sie`.SEIE are the interrupt-pending and interrupt-enable bits for supervisor-level external interrupts.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 325, + 330 + ] + }, + { + "chunk_id": "chunk_0d622e7c", + "text": "Bits `sip`.STIP and `sie`.STIE are the interrupt-pending and interrupt-enable bits for supervisor-level timer interrupts.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 332, + 340 + ] + }, + { + "chunk_id": "chunk_5f722d8b", + "text": "If implemented, STIP is read-only in `sip`.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 332, + 340 + ] + }, + { + "chunk_id": "chunk_8e179382", + "text": "When the Sstc extension is not implemented, STIP is set and cleared by the execution environment.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 332, + 340 + ] + }, + { + "chunk_id": "chunk_13ac4f3f", + "text": "When the Sstc extension is implemented, STIP reflects the timer interrupt signal resulting from `stimecmp`.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 332, + 340 + ] + }, + { + "chunk_id": "chunk_8a6d9942", + "text": "The `sip`.STIP bit, in response to timer interrupts generated by `stimecmp`, is set by writing `stimecmp` with a value that is less than or equal to `time`, and is cleared by writing `stimecmp` with a value greater than `time`.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 332, + 340 + ] + }, + { + "chunk_id": "chunk_e286e6e6", + "text": "Bits `sip`.SSIP and `sie`.SSIE are the interrupt-pending and interrupt-enable bits for supervisor-level software interrupts.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 342, + 346 + ] + }, + { + "chunk_id": "chunk_687c427e", + "text": "If implemented, SSIP is writable in `sip` and may also be set to 1 by a platform-specific interrupt controller.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 342, + 346 + ] + }, + { + "chunk_id": "chunk_ce48dba0", + "text": "If the Sscofpmf extension is implemented, bits `sip`.LCOFIP and `sie`.LCOFIE are the interrupt-pending and interrupt-enable bits for local-counter-overflow interrupts. LCOFIP is read-write in `sip` and reflects the occurrence of a local counter-overflow overflow interrupt request resulting from any of the `mhpmeventn`.OF bits being set.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 348, + 356 + ] + }, + { + "chunk_id": "chunk_e5e80644", + "text": "If the Sscofpmf extension is not implemented, `sip`.LCOFIP and `sie`.LCOFIE are read-only zeros.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 348, + 356 + ] + }, + { + "chunk_id": "chunk_3ef8a2ea", + "text": "Each standard interrupt type (SEI, STI, SSI, or LCOFI) may not be implemented, in which case the corresponding interrupt-pending and interrupt-enable bits are read-only zeros.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 358, + 363 + ] + }, + { + "chunk_id": "chunk_f4e7f983", + "text": "All bits in `sip` and `sie` are *WARL* fields.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 358, + 363 + ] + }, + { + "chunk_id": "chunk_0a8b3905", + "text": "The implemented interrupts may be found by writing one to every bit location in `sie`, then reading back to see which bit positions hold a one.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 358, + 363 + ] + }, + { + "chunk_id": "chunk_d9e3a039", + "text": "Multiple simultaneous interrupts destined for supervisor mode are handled in the following decreasing priority order: SEI, SSI, STI, LCOFI.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 365, + 367 + ] + }, + { + "chunk_id": "chunk_f9d6825c", + "text": "Supervisor software uses the same hardware performance monitoring facility as user-mode software, including the `time`, `cycle`, and `instret` CSRs.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Timers and Performance Counters", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 372, + 375 + ] + }, + { + "chunk_id": "chunk_73704ba3", + "text": "The implementation should provide a mechanism to modify the counter values.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Timers and Performance Counters", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 372, + 375 + ] + }, + { + "chunk_id": "chunk_1bab23f3", + "text": "The implementation must provide a facility for scheduling timer interrupts in terms of the real-time counter, `time`.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Timers and Performance Counters", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 377, + 379 + ] + }, + { + "chunk_id": "chunk_e30c42e7", + "text": "The counter-enable (`scounteren`) CSR is a 32-bit register that controls the availability of the hardware performance monitoring counters to U-mode.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Counter-Enable (`scounteren`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 386, + 389 + ] + }, + { + "chunk_id": "chunk_a3836258", + "text": "When the CY, TM, IR, or HPMn bit in the `scounteren` register is clear, attempts to read the `cycle`, `time`, `instret`, or `hpmcountern` register while executing in U-mode will cause an illegal-instruction exception.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Counter-Enable (`scounteren`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 391, + 396 + ] + }, + { + "chunk_id": "chunk_630a5ab0", + "text": "When one of these bits is set, access to the corresponding register is permitted.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Counter-Enable (`scounteren`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 391, + 396 + ] + }, + { + "chunk_id": "chunk_36674757", + "text": "`scounteren` must be implemented.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Counter-Enable (`scounteren`) Register", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 398, + 402 + ] + }, + { + "chunk_id": "chunk_c0984d7c", + "text": "However, any of the bits may be read-only zero, indicating reads to the corresponding counter will cause an exception when executing in U-mode.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Counter-Enable (`scounteren`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 398, + 402 + ] + }, + { + "chunk_id": "chunk_af89893f", + "text": "Hence, they are effectively *WARL* fields.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Counter-Enable (`scounteren`) Register", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 398, + 402 + ] + }, + { + "chunk_id": "chunk_cb25cead", + "text": "The `sscratch` CSR is an SXLEN-bit read/write register, dedicated for use by the supervisor.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Scratch (`sscratch`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 406, + 413 + ] + }, + { + "chunk_id": "chunk_54fcf669", + "text": "At the beginning of a trap handler, software normally uses a CSRRW instruction to swap `sscratch` with an integer register to obtain an initial working register.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Scratch (`sscratch`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 406, + 413 + ] + }, + { + "chunk_id": "chunk_52c689a6", + "text": "`sepc` is an SXLEN-bit read/write CSR formatted as shown in .", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Exception Program Counter (`sepc`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 420, + 422 + ] + }, + { + "chunk_id": "chunk_2a06c1f4", + "text": "The low bit of `sepc` (`sepc[0]`) is always zero.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Exception Program Counter (`sepc`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 420, + 422 + ] + }, + { + "chunk_id": "chunk_41cf0693", + "text": "This masking occurs also for the implicit read by the SRET instruction.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Exception Program Counter (`sepc`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 424, + 429 + ] + }, + { + "chunk_id": "chunk_825b6a5c", + "text": "Though masked, `sepc[1]` remains writable when IALIGN=32.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Exception Program Counter (`sepc`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 424, + 429 + ] + }, + { + "chunk_id": "chunk_101f499a", + "text": "`sepc` is a *WARL* register that must be able to hold all valid virtual addresses.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Exception Program Counter (`sepc`) Register", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 431, + 436 + ] + }, + { + "chunk_id": "chunk_e444caf5", + "text": "It need not be capable of holding all possible invalid addresses.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Exception Program Counter (`sepc`) Register", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 431, + 436 + ] + }, + { + "chunk_id": "chunk_13c29364", + "text": "Prior to writing `sepc`, implementations may convert an invalid address into some other invalid address that `sepc` is capable of holding.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Exception Program Counter (`sepc`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 431, + 436 + ] + }, + { + "chunk_id": "chunk_6e028514", + "text": "When a trap is taken into S-mode, `sepc` is written with the virtual address of the instruction that was interrupted or that encountered the exception.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Exception Program Counter (`sepc`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 438, + 442 + ] + }, + { + "chunk_id": "chunk_159c42e7", + "text": "Otherwise, `sepc` is never written by the implementation, though it may be explicitly written by software.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Exception Program Counter (`sepc`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 438, + 442 + ] + }, + { + "chunk_id": "chunk_a50bbb18", + "text": "The `scause` CSR is an SXLEN-bit read-write register formatted as shown in .", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Cause (`scause`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 451, + 456 + ] + }, + { + "chunk_id": "chunk_67f5898e", + "text": "When a trap is taken into S-mode, `scause` is written with a code indicating the event that caused the trap.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Cause (`scause`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 451, + 456 + ] + }, + { + "chunk_id": "chunk_e96a903b", + "text": "Otherwise, `scause` is never written by the implementation, though it may be explicitly written by software.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Cause (`scause`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 451, + 456 + ] + }, + { + "chunk_id": "chunk_1d4f67c9", + "text": "The Interrupt bit in the `scause` register is set if the trap was caused by an interrupt.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Cause (`scause`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 458, + 465 + ] + }, + { + "chunk_id": "chunk_6bcd2f21", + "text": "The Exception Code field contains a code identifying the last exception or interrupt. lists the possible exception codes for the current supervisor ISAs.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Cause (`scause`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 458, + 465 + ] + }, + { + "chunk_id": "chunk_4b58b9ae", + "text": "The Exception Code is a *WLRL* field.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Cause (`scause`) Register", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 458, + 465 + ] + }, + { + "chunk_id": "chunk_a8e5c3cd", + "text": "It is required to hold the values 0\u201331 (i.e., bits 4\u20130 must be implemented), but otherwise it is only guaranteed to hold supported exception codes.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Cause (`scause`) Register", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 458, + 465 + ] + }, + { + "chunk_id": "chunk_7f6cc73e", + "text": "Synchronous exception priorities are given by . | |Interrupt |Exception Code |Description |1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 |0 + 1 + 2-4 + 5 + 6-8 + 9 + 10-12 + 13 + 14-15 + {ge}16 |Reserved + Supervisor software interrupt + Reserved + Supervisor timer interrupt + Reserved + Supervisor external interrupt + Reserved + Counter-overflow interrupt + Reserved + Designated for platform use", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Cause (`scause`) Register", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 471, + 505 + ] + }, + { + "chunk_id": "chunk_69ea684c", + "text": "|0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 |0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10-11 + 12 + 13 + 14 + 15 + 16-17 + 18 + 19 + 20-23 + 24-31 + 32-47 + 48-63 + {ge}64 |Instruction address misaligned + Instruction access fault + Illegal instruction + Breakpoint + Load address misaligned + Load access fault + Store/AMO address misaligned + Store/AMO access fault + Environment call from U-mode + Environment call from S-mode + Reserved + Instruction page fault + Load page fault + Reserved + Store/AMO page fault + Reserved + Software check + Hardware error + Reserved + Designated for custom use + Reserved + Designated for custom use + Reserved |", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Cause (`scause`) Register", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 507, + 576 + ] + }, + { + "chunk_id": "chunk_4d4b4f96", + "text": "The `stval` CSR is an SXLEN-bit read-write register formatted as shown in .", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Value (`stval`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 580, + 589 + ] + }, + { + "chunk_id": "chunk_02bf8bfb", + "text": "When a trap is taken into S-mode, `stval` is written with exception-specific information to assist software in handling the trap.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Value (`stval`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 580, + 589 + ] + }, + { + "chunk_id": "chunk_21d221cd", + "text": "Otherwise, `stval` is never written by the implementation, though it may be explicitly written by software.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Value (`stval`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 580, + 589 + ] + }, + { + "chunk_id": "chunk_a6011783", + "text": "The hardware platform will specify which exceptions must set `stval` informatively, which may unconditionally set it to zero, and which may exhibit either behavior, depending on the underlying event that caused the exception.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Value (`stval`) Register", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 580, + 589 + ] + }, + { + "chunk_id": "chunk_6e67ec91", + "text": "If `stval` is written with a nonzero value when a breakpoint, address-misaligned, access-fault, page-fault, or hardware-error exception occurs on an instruction fetch, load, or store, then `stval` will contain the faulting virtual address.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Value (`stval`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 591, + 596 + ] + }, + { + "chunk_id": "chunk_780a1717", + "text": "On a breakpoint exception raised by an EBREAK or C.EBREAK instruction, `stval` is written with either zero or the virtual address of the instruction.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Value (`stval`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 598, + 600 + ] + }, + { + "chunk_id": "chunk_2ac91267", + "text": "If `stval` is written with a nonzero value when a misaligned load or store causes an access-fault, page-fault, or hardware-error exception, then `stval` will contain the virtual address of the portion of the access that caused the fault.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Value (`stval`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 606, + 611 + ] + }, + { + "chunk_id": "chunk_8cb5831f", + "text": "If `stval` is written with a nonzero value when an instruction access-fault, page-fault, or hardware-error exception occurs on a hart with variable-length instructions, then `stval` will contain the virtual address of the portion of the instruction that caused the fault, while `sepc` will point to the beginning of the instruction.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Value (`stval`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 613, + 618 + ] + }, + { + "chunk_id": "chunk_4a4f76e5", + "text": "The `stval` register can optionally also be used to return the faulting instruction bits on an illegal-instruction exception (`sepc` points to the faulting instruction in memory).", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Value (`stval`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 620, + 625 + ] + }, + { + "chunk_id": "chunk_30d0f022", + "text": "If `stval` is written with a nonzero value when an illegal-instruction exception occurs, then `stval` will contain the shortest of:", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Value (`stval`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 620, + 625 + ] + }, + { + "chunk_id": "chunk_ae2004f7", + "text": "the actual faulting instruction * the first ILEN bits of the faulting instruction * the first SXLEN bits of the faulting instruction", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Value (`stval`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "range", + "line_range": [ + 627, + 629 + ] + }, + { + "chunk_id": "chunk_41abd606", + "text": "The value loaded into `stval` on an illegal-instruction exception is right-justified and all unused upper bits are cleared to zero.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Value (`stval`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 631, + 633 + ] + }, + { + "chunk_id": "chunk_0dd14fa7", + "text": "On a trap caused by a software-check exception, the `stval` register holds the cause for the exception.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Value (`stval`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 635, + 637 + ] + }, + { + "chunk_id": "chunk_dad0b092", + "text": "0 - No information provided. * 2 - Landing Pad Fault.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Value (`stval`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 639, + 641 + ] + }, + { + "chunk_id": "chunk_ec7b962f", + "text": "Defined by the Zicfilp extension (). * 3 - Shadow Stack Fault.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Value (`stval`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 639, + 641 + ] + }, + { + "chunk_id": "chunk_12252fac", + "text": "Defined by the Zicfiss extension ().", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Value (`stval`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 639, + 641 + ] + }, + { + "chunk_id": "chunk_fa28d3bf", + "text": "For other traps, `stval` is set to zero, but a future standard may redefine `stval`\u2019s setting for other traps.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Value (`stval`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 643, + 645 + ] + }, + { + "chunk_id": "chunk_d991b772", + "text": "`stval` is a *WARL* register that must be able to hold all valid virtual addresses and the value 0.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Value (`stval`) Register", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 647, + 655 + ] + }, + { + "chunk_id": "chunk_f3f8b7b1", + "text": "It need not be capable of holding all possible invalid addresses.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Value (`stval`) Register", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 647, + 655 + ] + }, + { + "chunk_id": "chunk_46567333", + "text": "Prior to writing `stval`, implementations may convert an invalid address into some other invalid address that `stval` is capable of holding.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Value (`stval`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 647, + 655 + ] + }, + { + "chunk_id": "chunk_dea5ba2c", + "text": "If the feature to return the faulting instruction bits is implemented, `stval` must also be able to hold all values less than 2^N^, where N is the smaller of SXLEN and ILEN.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Value (`stval`) Register", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 647, + 655 + ] + }, + { + "chunk_id": "chunk_bd58296d", + "text": "The `senvcfg` CSR is an SXLEN-bit read/write register, formatted as shown in , that controls certain characteristics of the U-mode execution environment.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 660, + 663 + ] + }, + { + "chunk_id": "chunk_9c2522d9", + "text": "If bit FIOM (Fence of I/O implies Memory) is set to one in `senvcfg`, FENCE instructions executed in U-mode are modified so the requirement to order accesses to device I/O implies also the requirement to order main memory accesses. details the modified interpretation of FENCE instruction bits PI, PO, SI, and SO in U-mode when FIOM=1.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 698, + 704 + ] + }, + { + "chunk_id": "chunk_ab8b5beb", + "text": "Similarly, for U-mode when FIOM=1, if an atomic instruction that accesses a region ordered as device I/O has its aq and/or rl bit set, then that instruction is ordered as though it accesses both device I/O and memory.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 706, + 710 + ] + }, + { + "chunk_id": "chunk_e19c23fe", + "text": "If `satp`.MODE is read-only zero (always Bare), the implementation may make FIOM read-only zero.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 712, + 714 + ] + }, + { + "chunk_id": "chunk_dca2802a", + "text": "The Zicboz extension adds the `CBZE` (Cache Block Zero instruction enable) field to `senvcfg`.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 731, + 737 + ] + }, + { + "chunk_id": "chunk_beedd315", + "text": "The `CBZE` field controls execution of the cache block zero instruction (`CBO.ZERO`) in U-mode.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 731, + 737 + ] + }, + { + "chunk_id": "chunk_de7a421e", + "text": "Execution of `CBO.ZERO` in U-mode is enabled only if execution of the instruction is enabled for use in S-mode and `CBZE` is set to 1; otherwise, an illegal-instruction exception is raised.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 731, + 737 + ] + }, + { + "chunk_id": "chunk_1d1e9393", + "text": "When the Zicboz extension is not implemented, `CBZE` is read-only zero.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 731, + 737 + ] + }, + { + "chunk_id": "chunk_a72a56ff", + "text": "The Zicbom extension adds the `CBCFE` (Cache Block Clean and Flush instruction Enable) field to `senvcfg` to control execution of the `CBO.CLEAN` and `CBO.FLUSH` instructions in U-mode.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 739, + 745 + ] + }, + { + "chunk_id": "chunk_703720bd", + "text": "Execution of these instructions in U-mode is enabled only if execution of these instructions is enabled for use in S-mode and `CBCFE` is set to 1; otherwise, an illegal-instruction exception is raised.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 739, + 745 + ] + }, + { + "chunk_id": "chunk_19023b2e", + "text": "When the Zicbom extension is not implemented, `CBCFE` is read-only zero.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 739, + 745 + ] + }, + { + "chunk_id": "chunk_b3c6c806", + "text": "The Zicbom extension adds the `CBIE` (Cache Block Invalidate instruction Enable) WARL field to `senvcfg` to control execution of the `CBO.INVAL` instruction in U-mode.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 747, + 754 + ] + }, + { + "chunk_id": "chunk_00cd15bd", + "text": "The encoding `10b` is reserved.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 747, + 754 + ] + }, + { + "chunk_id": "chunk_51f2b558", + "text": "When the Zicbom extension is not implemented, `CBIE` is read-only zero.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 747, + 754 + ] + }, + { + "chunk_id": "chunk_e53554b1", + "text": "Execution of `CBO.INVAL` in U-mode is enabled only if execution of the instruction is enabled for use in S-mode and `CBIE` is set to `01b` or `11b`; otherwise, an illegal-instruction exception is raised.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 747, + 754 + ] + }, + { + "chunk_id": "chunk_04d9d67a", + "text": "If `CBO.INVAL` is enabled in S-mode to perform a flush operation, then when the instruction is enabled in U-mode it performs a flush operation, even if `CBIE` is set to `11b`.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 756, + 759 + ] + }, + { + "chunk_id": "chunk_1913d647", + "text": "Otherwise, the instruction behaves as follows, depending on the `CBIE` encoding:", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 756, + 759 + ] + }, + { + "chunk_id": "chunk_8bff7acb", + "text": "`01b` -- The instruction is executed and performs a flush operation. * `11b` -- The instruction is executed and performs an invalidate operation.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 761, + 762 + ] + }, + { + "chunk_id": "chunk_a9027501", + "text": "If Ssnpm is not implemented, `PMM` is read-only zero.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 764, + 769 + ] + }, + { + "chunk_id": "chunk_169d0fd6", + "text": "The `PMM` field is read-only zero for RV32.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 764, + 769 + ] + }, + { + "chunk_id": "chunk_e41df48b", + "text": "The Zicfilp extension adds the `LPE` field in `senvcfg`.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 783, + 787 + ] + }, + { + "chunk_id": "chunk_d65e9566", + "text": "When the `LPE` field is set to 1, the Zicfilp extension is enabled in VU/U-mode.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 783, + 787 + ] + }, + { + "chunk_id": "chunk_06052883", + "text": "When the `LPE` field is 0, the Zicfilp extension is not enabled in VU/U-mode and the following rules apply to VU/U-mode:", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 783, + 787 + ] + }, + { + "chunk_id": "chunk_3dad2541", + "text": "The hart does not update the `ELP` state; it remains as `NOLPEXPECTED`. * The `LPAD` instruction operates as a no-op.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 789, + 790 + ] + }, + { + "chunk_id": "chunk_b19c7752", + "text": "The Zicfiss extension adds the `SSE` field in `senvcfg`.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 792, + 796 + ] + }, + { + "chunk_id": "chunk_a4c98d55", + "text": "When the `SSE` field is set to 1, the Zicfiss extension is activated in VU/U-mode.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 792, + 796 + ] + }, + { + "chunk_id": "chunk_a219612a", + "text": "When the `SSE` field is 0, the Zicfiss extension remains inactive in VU/U-mode, and the following rules apply:", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 792, + 796 + ] + }, + { + "chunk_id": "chunk_073a1e59", + "text": "32-bit Zicfiss instructions will revert to their behavior as defined by Zimop. * 16-bit Zicfiss instructions will revert to their behavior as defined by Zcmop. *", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 798, + 801 + ] + }, + { + "chunk_id": "chunk_031481d9", + "text": "When `menvcfg.SSE` is one, `SSAMOSWAP.W/D` raises an illegal-instruction exception in U-mode and a virtual-instruction exception in VU-mode.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 798, + 801 + ] + }, + { + "chunk_id": "chunk_b11dd896", + "text": "The `satp` CSR is an SXLEN-bit read/write register, formatted as shown in for SXLEN=32 and for SXLEN=64, which controls supervisor-mode address translation and protection.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Address Translation and Protection (`satp`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 806, + 816 + ] + }, + { + "chunk_id": "chunk_a9be8fa8", + "text": "Further details on the access to this register are described in .", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Address Translation and Protection (`satp`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 806, + 816 + ] + }, + { + "chunk_id": "chunk_6545c7e7", + "text": "shows the encodings of the MODE field when SXLEN=32 and SXLEN=64.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Address Translation and Protection (`satp`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 826, + 836 + ] + }, + { + "chunk_id": "chunk_f77f341e", + "text": "When MODE=Bare, supervisor virtual addresses are equal to supervisor physical addresses, and there is no additional memory protection beyond the physical memory protection scheme described in .", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Address Translation and Protection (`satp`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "range", + "line_range": [ + 826, + 836 + ] + }, + { + "chunk_id": "chunk_a56a26cb", + "text": "To select MODE=Bare, software must write zero to the remaining fields of `satp` (bits 30\u20130 when SXLEN=32, or bits 59\u20130 when SXLEN=64).", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Address Translation and Protection (`satp`) Register", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 826, + 836 + ] + }, + { + "chunk_id": "chunk_ef6056e2", + "text": "Attempting to select MODE=Bare with a nonzero pattern in the remaining fields has an UNSPECIFIED effect on the value that the remaining fields assume and an UNSPECIFIED effect on address translation and protection behavior.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Address Translation and Protection (`satp`) Register", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 826, + 836 + ] + }, + { + "chunk_id": "chunk_f30ec461", + "text": "When SXLEN=32, the `satp` encodings corresponding to MODE=Bare and ASID[8:7]=3 are designated for custom use, whereas the encodings corresponding to MODE=Bare and ASID[8:7]!=3 are reserved for future standard use.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Address Translation and Protection (`satp`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 838, + 842 + ] + }, + { + "chunk_id": "chunk_36cf0e92", + "text": "When SXLEN=64, all `satp` encodings corresponding to MODE=Bare are reserved for future standard use.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Address Translation and Protection (`satp`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 838, + 842 + ] + }, + { + "chunk_id": "chunk_f8790670", + "text": "If an implementation supports the Svbare extension, then the `satp` register's MODE field must be capable of holding the value Bare.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Address Translation and Protection (`satp`) Register", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 844, + 846 + ] + }, + { + "chunk_id": "chunk_1e0064c9", + "text": "When SXLEN=32, the only other valid setting for MODE is Sv32, a paged virtual-memory scheme described in .", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Address Translation and Protection (`satp`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 848, + 850 + ] + }, + { + "chunk_id": "chunk_df06bbd5", + "text": "When SXLEN=64, three paged virtual-memory schemes are defined: Sv39, Sv48, and Sv57, described in , , and , respectively.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Address Translation and Protection (`satp`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 852, + 858 + ] + }, + { + "chunk_id": "chunk_02733136", + "text": "One additional scheme, Sv64, will be defined in a later version of this specification.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Address Translation and Protection (`satp`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 852, + 858 + ] + }, + { + "chunk_id": "chunk_4e95ee24", + "text": "The remaining MODE settings are reserved for future use and may define different interpretations of the other fields in `satp`.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Address Translation and Protection (`satp`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 852, + 858 + ] + }, + { + "chunk_id": "chunk_1c14813c", + "text": "Implementations are not required to support all MODE settings, and if `satp` is written with an unsupported MODE, the entire write has no effect; no fields in `satp` are modified.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Address Translation and Protection (`satp`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 860, + 863 + ] + }, + { + "chunk_id": "chunk_312e1f10", + "text": "The number of ASID bits is UNSPECIFIED and may be zero.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Address Translation and Protection (`satp`) Register", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 865, + 873 + ] + }, + { + "chunk_id": "chunk_1b836177", + "text": "The number of implemented ASID bits, termed ASIDLEN, may be determined by writing one to every bit position in the ASID field, then reading back the value in `satp` to see which bit positions in the ASID field hold a one.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Address Translation and Protection (`satp`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 865, + 873 + ] + }, + { + "chunk_id": "chunk_3281511b", + "text": "The maximal value of ASIDLEN, termed ASIDMAX, is 9 for Sv32 or 16 for Sv39, Sv48, and Sv57.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Address Translation and Protection (`satp`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 865, + 873 + ] + }, + { + "chunk_id": "chunk_7bf25866", + "text": "The `satp` CSR is considered active when the effective privilege mode is S-mode or U-mode.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Address Translation and Protection (`satp`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 917, + 921 + ] + }, + { + "chunk_id": "chunk_537571f9", + "text": "Executions of the address-translation algorithm may only begin using a given value of `satp` when `satp` is active.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Address Translation and Protection (`satp`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 917, + 921 + ] + }, + { + "chunk_id": "chunk_468078d5", + "text": "The `stimecmp` CSR is a 64-bit register and has 64-bit precision on all RV32 and RV64 systems.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Timer (`stimecmp`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 935, + 938 + ] + }, + { + "chunk_id": "chunk_b32f1bad", + "text": "In RV32 only, accesses to the `stimecmp` CSR access the low 32 bits, while accesses to the `stimecmph` CSR access the high 32 bits of `stimecmp`.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Timer (`stimecmp`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 935, + 938 + ] + }, + { + "chunk_id": "chunk_a38dc791", + "text": "A supervisor timer interrupt becomes pending, as reflected in the STIP bit in the `mip` and `sip` registers whenever `time` contains a value greater than or equal to `stimecmp`, treating the values as unsigned integers.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Timer (`stimecmp`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 940, + 949 + ] + }, + { + "chunk_id": "chunk_539c94fa", + "text": "If the result of this comparison changes, it is guaranteed to be reflected in STIP eventually, but not necessarily immediately.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Timer (`stimecmp`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 940, + 949 + ] + }, + { + "chunk_id": "chunk_b341b1f2", + "text": "The interrupt will be taken based on the standard interrupt enable and delegation rules.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Timer (`stimecmp`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 940, + 949 + ] + }, + { + "chunk_id": "chunk_17a0f8d9", + "text": "The behavior of SFENCE.VMA depends on rs1 and rs2 as follows:", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction", + "confidence": "medium", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 977, + 983 + ] + }, + { + "chunk_id": "chunk_496e38fa", + "text": "If rs1=`x0` and rs2=`x0`, the fence orders all reads and writes made to any level of the page tables, for all address spaces.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 985, + 988 + ] + }, + { + "chunk_id": "chunk_6b47438c", + "text": "If rs1=`x0` and rs2{ne}``x0``, the fence orders all reads and writes made to any level of the page tables, but only for the address space identified by integer register rs2.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 990, + 996 + ] + }, + { + "chunk_id": "chunk_36d5504d", + "text": "If rs1{ne}``x0`` and rs2=`x0`, the fence orders only reads and writes made to leaf page table entries corresponding to the virtual address in rs1, for all address spaces.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 998, + 1003 + ] + }, + { + "chunk_id": "chunk_acb66772", + "text": "If rs1{ne}``x0`` and rs2{ne}``x0``, the fence orders only reads and writes made to leaf page table entries corresponding to the virtual address in rs1, for the address space identified by integer register rs2.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 1005, + 1012 + ] + }, + { + "chunk_id": "chunk_1f453b67", + "text": "If the value held in rs1 is not a valid virtual address, then the SFENCE.VMA instruction has no effect.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 1014, + 1017 + ] + }, + { + "chunk_id": "chunk_6426d50a", + "text": "No exception is raised in this case.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 1014, + 1017 + ] + }, + { + "chunk_id": "chunk_60a848de", + "text": "When rs2{ne}``x0``, bits SXLEN-1:ASIDMAX of the value held in rs2 are reserved for future standard use.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1019, + 1025 + ] + }, + { + "chunk_id": "chunk_2f2c6058", + "text": "Until their use is defined by a standard extension, they should be zeroed by software and ignored by current implementations.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction", + "confidence": "medium", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 1019, + 1025 + ] + }, + { + "chunk_id": "chunk_d67df9cc", + "text": "Furthermore, if ASIDLEN Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 1019, + 1025 + ] + }, + { + "chunk_id": "chunk_b9c1743d", + "text": "An implicit read of the memory-management data structures may return any translation for an address that was valid at any time since the most recent SFENCE.VMA that subsumes that address.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction", + "confidence": "medium", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 1027, + 1040 + ] + }, + { + "chunk_id": "chunk_c7f606c6", + "text": "These implicit loads also need not otherwise obey normal program order semantics with respect to prior loads or stores to the same address.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1027, + 1040 + ] + }, + { + "chunk_id": "chunk_0089507b", + "text": "Implementations must only perform implicit reads of the translation data structures pointed to by the current contents of the `satp` register or a subsequent valid (V=1) translation data structure entry, and must only raise exceptions for implicit accesses that are generated as a result of instruction execution, not those that are performed speculatively.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1042, + 1047 + ] + }, + { + "chunk_id": "chunk_32db1b59", + "text": "Changes to the `sstatus` fields SUM and MXR take effect immediately, without the need to execute an SFENCE.VMA instruction.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1049, + 1054 + ] + }, + { + "chunk_id": "chunk_9d004688", + "text": "Changing `satp`.MODE from Bare to other modes and vice versa also takes effect immediately, without the need to execute an SFENCE.VMA instruction.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1049, + 1054 + ] + }, + { + "chunk_id": "chunk_42ef9f79", + "text": "Likewise, changes to `satp`.ASID take effect immediately.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1049, + 1054 + ] + }, + { + "chunk_id": "chunk_c6432aaf", + "text": "If a hart employs an address-translation cache, that cache must appear to be private to that hart.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 1056, + 1060 + ] + }, + { + "chunk_id": "chunk_fbd42ad4", + "text": "In particular, the meaning of an ASID is local to a hart; software may choose to use the same ASID to refer to different address spaces on different harts.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction", + "confidence": "medium", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 1056, + 1060 + ] + }, + { + "chunk_id": "chunk_29b5dd44", + "text": "For implementations that make `satp`.MODE read-only zero (always Bare), attempts to execute an SFENCE.VMA instruction might raise an illegal-instruction exception.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 1062, + 1065 + ] + }, + { + "chunk_id": "chunk_17b51e81", + "text": "Sv32 implementations support a 32-bit virtual address space, divided into 4 KiB pages.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 1086, + 1098 + ] + }, + { + "chunk_id": "chunk_6e96c167", + "text": "When Sv32 virtual memory mode is selected in the MODE field of the `satp` register, supervisor virtual addresses are translated into supervisor physical addresses via a two-level page table.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1086, + 1098 + ] + }, + { + "chunk_id": "chunk_faf01682", + "text": "The 20-bit VPN is translated into a 22-bit physical page number (PPN), while the 12-bit page offset is untranslated.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 1086, + 1098 + ] + }, + { + "chunk_id": "chunk_de2359ad", + "text": "If necessary, supervisor-level physical addresses are zero-extended to the number of physical address bits found in the implementation.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 1086, + 1098 + ] + }, + { + "chunk_id": "chunk_3c81eded", + "text": "Sv32 page tables consist of 2^10^ page-table entries (PTEs), each of four bytes. A page table is exactly the size of a page and must always be aligned to a page boundary.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1104, + 1107 + ] + }, + { + "chunk_id": "chunk_9c96dfbe", + "text": "The physical page number of the root page table is stored in the `satp` register.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1104, + 1107 + ] + }, + { + "chunk_id": "chunk_15744a89", + "text": "The V bit indicates whether the PTE is valid; if it is 0, all other bits in the PTE are don\u2019t-cares and may be used freely by software.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 1117, + 1125 + ] + }, + { + "chunk_id": "chunk_325f20bf", + "text": "The permission bits, R, W, and X, indicate whether the page is readable, writable, and executable, respectively.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "unknown", + "line_range": [ + 1117, + 1125 + ] + }, + { + "chunk_id": "chunk_813c23c8", + "text": "When all three are zero, the PTE is a pointer to the next level of the page table; otherwise, it is a leaf PTE.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1117, + 1125 + ] + }, + { + "chunk_id": "chunk_28fda033", + "text": "Writable pages must also be marked readable; the contrary combinations are reserved for future use. summarizes the encoding of the permission bits.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1117, + 1125 + ] + }, + { + "chunk_id": "chunk_37f24126", + "text": "Attempting to fetch an instruction from a page that does not have execute permissions raises a fetch page-fault exception.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 1166, + 1173 + ] + }, + { + "chunk_id": "chunk_41900185", + "text": "Attempting to execute a load, load-reserved, or cache-block management instruction whose effective address lies within a page without read permissions raises a load page-fault exception.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 1166, + 1173 + ] + }, + { + "chunk_id": "chunk_e99af61b", + "text": "Attempting to execute a store, store-conditional, AMO, or cache-block zero instruction instruction whose effective address lies within a page without write permissions raises a store page-fault exception.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 1166, + 1173 + ] + }, + { + "chunk_id": "chunk_0a493f27", + "text": "The U bit indicates whether the page is accessible to user mode. U-mode software may only access the page when U=1.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 1175, + 1181 + ] + }, + { + "chunk_id": "chunk_5aad4584", + "text": "If the SUM bit in the `sstatus` register is set, supervisor mode software may also access pages with U=1.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1175, + 1181 + ] + }, + { + "chunk_id": "chunk_2a845d8f", + "text": "However, supervisor code normally operates with the SUM bit clear, in which case, supervisor code will fault on accesses to user-mode pages.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1175, + 1181 + ] + }, + { + "chunk_id": "chunk_f6cc4408", + "text": "Irrespective of SUM, the supervisor may not execute code on pages with U=1.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1175, + 1181 + ] + }, + { + "chunk_id": "chunk_14b76ccd", + "text": "The G bit designates a global mapping.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1183, + 1190 + ] + }, + { + "chunk_id": "chunk_17540267", + "text": "The RSW field is reserved for use by supervisor software; the implementation shall ignore this field.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "confidence": "very_high", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 1192, + 1193 + ] + }, + { + "chunk_id": "chunk_a413a6fd", + "text": "When the Svade extension is not implemented, the following scheme applies. + +", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1207, + 1249 + ] + }, + { + "chunk_id": "chunk_8951da72", + "text": "When a virtual page is accessed and the A bit is clear, the PTE is updated to set the A bit.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1207, + 1249 + ] + }, + { + "chunk_id": "chunk_3e560fe5", + "text": "When the virtual page is written and the D bit is clear, the PTE is updated to set the D bit.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1207, + 1249 + ] + }, + { + "chunk_id": "chunk_498a5dff", + "text": "When G-stage address translation is in use and is not Bare, the G-stage virtual pages may be accessed or written by implicit accesses to VS-level memory management data structures, such as page tables. + +", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1207, + 1249 + ] + }, + { + "chunk_id": "chunk_754c2dd8", + "text": "When two-stage address translation is in use, an explicit access may cause both VS-stage and G-stage PTEs to be updated.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1207, + 1249 + ] + }, + { + "chunk_id": "chunk_d22df458", + "text": "The following rules apply to all PTE updates caused by an explicit or an implicit memory accesses. + + The PTE update must be atomic with respect to other accesses to the PTE, and must atomically perform all page-table walk checks for that leaf PTE as part of, and before, conditionally updating the PTE value.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1207, + 1249 + ] + }, + { + "chunk_id": "chunk_32ffc581", + "text": "Updates of the A bit may be performed as a result of speculation, even if the associated memory access ultimately is not performed architecturally.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1207, + 1249 + ] + }, + { + "chunk_id": "chunk_af6c9656", + "text": "However, updates to the D bit, resulting from an explicit store, must be exact (i.e., non-speculative), and observed in program order by the local hart.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1207, + 1249 + ] + }, + { + "chunk_id": "chunk_f91d2b79", + "text": "When two-stage address translation is active, updates to the D bit in G-stage PTEs may be performed by an implicit access to a VS-stage PTE, if the G-stage PTE provides write permission, before any speculative access to the VS-stage PTE. + + The PTE update must appear in the global memory order before the memory access that caused the PTE update and before any subsequent explicit memory access to that virtual page by the local hart.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 1207, + 1249 + ] + }, + { + "chunk_id": "chunk_80f11ed7", + "text": "The ordering on loads and stores provided by FENCE instructions and the acquire/release bits on atomic instructions also orders the PTE updates associated with those loads and stores as observed by remote harts. + + The PTE update is not required to be atomic with respect to the memory access that caused the update and a trap may occur between the PTE update and the memory access that caused the PTE update.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 1207, + 1249 + ] + }, + { + "chunk_id": "chunk_3434b777", + "text": "If a trap occurs then the A and/or D bit may be updated but the memory access that caused the PTE update might not occur.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1207, + 1249 + ] + }, + { + "chunk_id": "chunk_a7bf66ff", + "text": "The hart must not perform the memory access that caused the PTE update before the PTE update is globally visible. + + The page tables must be located in memory with hardware page-table write access and RsrvEventual PMA.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1207, + 1249 + ] + }, + { + "chunk_id": "chunk_f31be6ec", + "text": "All harts in a system must employ the same PTE-update scheme as each other.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1251, + 1252 + ] + }, + { + "chunk_id": "chunk_744f9187", + "text": "Any level of PTE may be a leaf PTE, so in addition to 4 KiB pages, Sv32 supports 4 MiB megapages. A megapage must be virtually and physically aligned to a 4 MiB boundary; a page-fault exception is raised if the physical address is insufficiently aligned.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 1254, + 1257 + ] + }, + { + "chunk_id": "chunk_aab201fe", + "text": "Until their use is defined by a standard extension, they must be cleared by software for forward compatibility.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "confidence": "very_high", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 1259, + 1261 + ] + }, + { + "chunk_id": "chunk_ae9dae05", + "text": "For implementations with both page-based virtual memory and the \"A\" standard extension, the LR/SC reservation set must lie completely within a single base physical page (i.e., a naturally aligned 4 KiB physical-memory region).", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1263, + 1266 + ] + }, + { + "chunk_id": "chunk_8b568299", + "text": "On some implementations, misaligned loads, stores, and instruction fetches may also be decomposed into multiple accesses, some of which may succeed before a page-fault exception occurs.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1268, + 1274 + ] + }, + { + "chunk_id": "chunk_c899916f", + "text": "In particular, a portion of a misaligned store that passes the exception check may become visible, even if another portion fails the exception check.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1268, + 1274 + ] + }, + { + "chunk_id": "chunk_6c464627", + "text": "Let a be ``satp``.ppn\u00d7PAGESIZE, and let i=LEVELS-1. (For Sv32, PAGESIZE=2^12^ and LEVELS=2.) The `satp` register must be active, i.e., the effective privilege mode must be S-mode or U-mode.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1283, + 1284 + ] + }, + { + "chunk_id": "chunk_24313df8", + "text": "Let pte be the value of the PTE at address a+va.vpn[i]\u00d7PTESIZE. (For Sv32, PTESIZE=4.)", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 1286, + 1286 + ] + }, + { + "chunk_id": "chunk_523bf330", + "text": "If accessing pte violates a PMA or PMP check, raise an access-fault exception corresponding to the original access type.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 1286, + 1286 + ] + }, + { + "chunk_id": "chunk_e09616d4", + "text": "If pte.v=0, or if pte.r=0 and pte.w=1, or if any bits or encodings that are reserved for future standard use are set within pte, stop and raise a page-fault exception corresponding to the original access type.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1288, + 1288 + ] + }, + { + "chunk_id": "chunk_cac71583", + "text": "If pte.r=1 or pte.x=1, go to step 5.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1290, + 1291 + ] + }, + { + "chunk_id": "chunk_8d4ce2ab", + "text": "If i<0, stop and raise a page-fault exception corresponding to the original access type.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 1290, + 1291 + ] + }, + { + "chunk_id": "chunk_69644df2", + "text": "If i>0 and pte.ppn[i-1:0] != 0, this is a misaligned superpage; stop and raise a page-fault exception corresponding to the original access type.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 1293, + 1293 + ] + }, + { + "chunk_id": "chunk_5abde674", + "text": "Determine if the requested memory access is allowed by the pte.u bit, given the current privilege mode and the value of the SUM and MXR fields of the *mstatus* register.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1295, + 1295 + ] + }, + { + "chunk_id": "chunk_4727038e", + "text": "If not, stop and raise a page-fault exception corresponding to the original access type.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 1295, + 1295 + ] + }, + { + "chunk_id": "chunk_e945aaea", + "text": "Determine if the requested memory access is allowed by the pte.r, pte.w, and pte.x bits, given the Shadow Stack Memory Protection rules.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1297, + 1297 + ] + }, + { + "chunk_id": "chunk_fe1d67e1", + "text": "If not, stop and raise an access-fault exception.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 1297, + 1297 + ] + }, + { + "chunk_id": "chunk_7b5c5734", + "text": "Determine if the requested memory access is allowed by the pte.r, pte.w, and pte.x bits.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1299, + 1299 + ] + }, + { + "chunk_id": "chunk_86bd38e9", + "text": "If not, stop and raise a page-fault exception corresponding to the original access type.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 1299, + 1299 + ] + }, + { + "chunk_id": "chunk_69483509", + "text": "If pte.a=0, or if the original memory access is a store and pte.d=0:", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1301, + 1301 + ] + }, + { + "chunk_id": "chunk_9fd8d38f", + "text": "If the Svade extension is implemented, stop and raise a page-fault exception corresponding to the original access type. *", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 1303, + 1311 + ] + }, + { + "chunk_id": "chunk_264d174f", + "text": "If a store to the PTE at address a+va.vpn[i]\u00d7PTESIZE would violate a PMA or PMP check, raise an access-fault exception corresponding to the original access type. * Perform the following steps atomically: ** Compare pte to the value of the PTE at address a+va.vpn[i]\u00d7PTESIZE. **", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1303, + 1311 + ] + }, + { + "chunk_id": "chunk_afa22934", + "text": "If the values match, set pte.a to 1 and, if the original memory access is a store, also set pte.d to 1.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1303, + 1311 + ] + }, + { + "chunk_id": "chunk_69d3817c", + "text": "If the comparison fails, return to step 2.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1303, + 1311 + ] + }, + { + "chunk_id": "chunk_c2ff426c", + "text": "If i>0, then this is a superpage translation and pa.ppn[i-1:0] = va.vpn[i-1:0]. * pa.ppn[LEVELS-1:i] = pte.ppn[LEVELS-1:i].", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1313, + 1317 + ] + }, + { + "chunk_id": "chunk_9e32d6f3", + "text": "The results of implicit address-translation reads in step 2 may be held in a read-only, incoherent address-translation cache but not shared with other harts.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1322, + 1331 + ] + }, + { + "chunk_id": "chunk_6f492440", + "text": "The address-translation cache may hold an arbitrary number of entries, including an arbitrary number of entries for the same address and ASID.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1322, + 1331 + ] + }, + { + "chunk_id": "chunk_72605428", + "text": "Entries in the address-translation cache may then satisfy subsequent step 2 reads if the ASID associated with the entry matches the ASID loaded in step 0 or if the entry is associated with a global mapping.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1322, + 1331 + ] + }, + { + "chunk_id": "chunk_505d8512", + "text": "To ensure that implicit reads observe writes to the same memory locations, an SFENCE.VMA instruction must be executed after the writes to flush the relevant cached translations.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process", + "confidence": "very_high", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 1322, + 1331 + ] + }, + { + "chunk_id": "chunk_d28700cd", + "text": "The address-translation cache cannot be used in step 9; accessed and dirty bits may only be updated in memory directly.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1333, + 1339 + ] + }, + { + "chunk_id": "chunk_0946d34b", + "text": "Implementations may also execute the address-translation algorithm speculatively at any time, for any virtual address, as long as `satp` is active (as defined in ).", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1333, + 1339 + ] + }, + { + "chunk_id": "chunk_ca42fdc2", + "text": "Speculative executions of the address-translation algorithm behave as non-speculative executions of the algorithm do, except that they must not set the dirty bit for a PTE, they must not trigger an exception, and they must not create address-translation cache entries if those entries would have been invalidated by any SFENCE.VMA instruction executed by the hart since the speculative execution of the algorithm began.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process", + "confidence": "very_high", + "parameter_class": "SW_rule", + "parameter_type": "binary", + "line_range": [ + 1341, + 1346 + ] + }, + { + "chunk_id": "chunk_05a94186", + "text": "This section describes a simple paged virtual-memory system for SXLEN=64, which supports 39-bit virtual address spaces.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv39: Page-Based 39-bit Virtual-Memory System", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 1351, + 1354 + ] + }, + { + "chunk_id": "chunk_296d31c8", + "text": "Sv39 implementations support a 39-bit virtual address space, divided into 4 KiB pages.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv39: Page-Based 39-bit Virtual-Memory System > Addressing and Memory Protection", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 1359, + 1368 + ] + }, + { + "chunk_id": "chunk_fe810c78", + "text": "Instruction fetch addresses and load and store effective addresses, which are 64 bits, must have bits 63\u201339 all equal to bit 38, or else a page-fault exception will occur.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv39: Page-Based 39-bit Virtual-Memory System > Addressing and Memory Protection", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 1359, + 1368 + ] + }, + { + "chunk_id": "chunk_df00bbad", + "text": "The 27-bit VPN is translated into a 44-bit PPN via a three-level page table, while the 12-bit page offset is untranslated.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv39: Page-Based 39-bit Virtual-Memory System > Addressing and Memory Protection", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 1359, + 1368 + ] + }, + { + "chunk_id": "chunk_63f824d2", + "text": "Sv39 page tables contain 2^9^ page table entries (PTEs), eight bytes each. A page table is exactly the size of a page and must always be aligned to a page boundary.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv39: Page-Based 39-bit Virtual-Memory System > Addressing and Memory Protection", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1382, + 1387 + ] + }, + { + "chunk_id": "chunk_b151e915", + "text": "The physical page number of the root page table is stored in the `satp` register's PPN field.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv39: Page-Based 39-bit Virtual-Memory System > Addressing and Memory Protection", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1382, + 1387 + ] + }, + { + "chunk_id": "chunk_28164943", + "text": "If Svnapot is not implemented, bit 63 remains reserved and must be zeroed by software for forward compatibility, or else a page-fault exception is raised.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv39: Page-Based 39-bit Virtual-Memory System > Addressing and Memory Protection", + "confidence": "very_high", + "parameter_class": "SW_rule", + "parameter_type": "binary", + "line_range": [ + 1389, + 1403 + ] + }, + { + "chunk_id": "chunk_d2dbfb9b", + "text": "If Svpbmt is not implemented, bits 62-61 remain reserved and must be zeroed by software for forward compatibility, or else a page-fault exception is raised.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv39: Page-Based 39-bit Virtual-Memory System > Addressing and Memory Protection", + "confidence": "very_high", + "parameter_class": "SW_rule", + "parameter_type": "binary", + "line_range": [ + 1389, + 1403 + ] + }, + { + "chunk_id": "chunk_54bb3c07", + "text": "Bits 60-54 are reserved for future standard use and, until their use is defined by some standard extension, must be zeroed by software for forward compatibility.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv39: Page-Based 39-bit Virtual-Memory System > Addressing and Memory Protection", + "confidence": "very_high", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 1389, + 1403 + ] + }, + { + "chunk_id": "chunk_869b42cc", + "text": "If any of these bits are set, a page-fault exception is raised.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv39: Page-Based 39-bit Virtual-Memory System > Addressing and Memory Protection", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 1389, + 1403 + ] + }, + { + "chunk_id": "chunk_a6efeb0a", + "text": "Any level of PTE may be a leaf PTE, so in addition to 4 KiB pages, Sv39 supports 2 MiB megapages and 1 GiB gigapages, each of which must be virtually and physically aligned to a boundary equal to its size. A page-fault exception is raised if the physical address is insufficiently aligned.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv39: Page-Based 39-bit Virtual-Memory System > Addressing and Memory Protection", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 1405, + 1411 + ] + }, + { + "chunk_id": "chunk_f88ecfd1", + "text": "This section describes a simple paged virtual-memory system for SXLEN=64, which supports 48-bit virtual address spaces.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv48: Page-Based 48-bit Virtual-Memory System", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 1421, + 1427 + ] + }, + { + "chunk_id": "chunk_966da16d", + "text": "Implementations that support Sv48 must also support Sv39.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv48: Page-Based 48-bit Virtual-Memory System", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1429, + 1430 + ] + }, + { + "chunk_id": "chunk_c5a71c5e", + "text": "Sv48 implementations support a 48-bit virtual address space, divided into 4 KiB pages.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv48: Page-Based 48-bit Virtual-Memory System > Addressing and Memory Protection", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 1435, + 1444 + ] + }, + { + "chunk_id": "chunk_7a3726f1", + "text": "Instruction fetch addresses and load and store effective addresses, which are 64 bits, must have bits 63\u201348 all equal to bit 47, or else a page-fault exception will occur.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv48: Page-Based 48-bit Virtual-Memory System > Addressing and Memory Protection", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 1435, + 1444 + ] + }, + { + "chunk_id": "chunk_9d79fc84", + "text": "The 36-bit VPN is translated into a 44-bit PPN via a four-level page table, while the 12-bit page offset is untranslated.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv48: Page-Based 48-bit Virtual-Memory System > Addressing and Memory Protection", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 1435, + 1444 + ] + }, + { + "chunk_id": "chunk_3a54f8db", + "text": "Any level of PTE may be a leaf PTE, so in addition to 4 KiB pages, Sv48 supports 2 MiB megapages, 1 GiB gigapages, and 512 GiB terapages, each of which must be virtually and physically aligned to a boundary equal to its size. A page-fault exception is raised if the physical address is insufficiently aligned.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv48: Page-Based 48-bit Virtual-Memory System > Addressing and Memory Protection", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 1458, + 1467 + ] + }, + { + "chunk_id": "chunk_7a44760f", + "text": "This section describes a simple paged virtual-memory system designed for RV64 systems, which supports 57-bit virtual address spaces.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv57: Page-Based 57-bit Virtual-Memory System", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 1478, + 1484 + ] + }, + { + "chunk_id": "chunk_daf051ba", + "text": "Implementations that support Sv57 must also support Sv48.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv57: Page-Based 57-bit Virtual-Memory System", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1486, + 1487 + ] + }, + { + "chunk_id": "chunk_14820799", + "text": "Sv57 implementations support a 57-bit virtual address space, divided into 4 KiB pages.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv57: Page-Based 57-bit Virtual-Memory System > Addressing and Memory Protection", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 1492, + 1501 + ] + }, + { + "chunk_id": "chunk_9abb44f7", + "text": "Instruction fetch addresses and load and store effective addresses, which are 64 bits, must have bits 63\u201357 all equal to bit 56, or else a page-fault exception will occur.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv57: Page-Based 57-bit Virtual-Memory System > Addressing and Memory Protection", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 1492, + 1501 + ] + }, + { + "chunk_id": "chunk_e787bf9b", + "text": "The 45-bit VPN is translated into a 44-bit PPN via a five-level page table, while the 12-bit page offset is untranslated.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv57: Page-Based 57-bit Virtual-Memory System > Addressing and Memory Protection", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 1492, + 1501 + ] + }, + { + "chunk_id": "chunk_d81cf6eb", + "text": "Any level of PTE may be a leaf PTE, so in addition to 4 KiB pages, Sv57 supports 2 MiB megapages, 1 GiB gigapages, 512 GiB terapages, and 256 TiB petapages, each of which must be virtually and physically aligned to a boundary equal to its size. A page-fault exception is raised if the physical address is insufficiently aligned.", + "source_file": "src/priv/supervisor.adoc", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv57: Page-Based 57-bit Virtual-Memory System > Addressing and Memory Protection", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 1515, + 1524 + ] + } + ] + }, + { + "file": "src/priv/svadu.adoc", + "chunks": [ + { + "chunk_id": "chunk_8d249b33", + "text": "The Svadu extension adds support and CSR controls for hardware updating of PTE A/D bits.", + "source_file": "src/priv/svadu.adoc", + "section": "Preamble > \"Svadu\" Extension for Hardware Updating of A/D Bits, Version 1.0", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 3, + 3 + ] + }, + { + "chunk_id": "chunk_39cd4c4f", + "text": "If the Svadu extension is implemented, the `menvcfg`.ADUE field is writable.", + "source_file": "src/priv/svadu.adoc", + "section": "Preamble > \"Svadu\" Extension for Hardware Updating of A/D Bits, Version 1.0", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 5, + 8 + ] + }, + { + "chunk_id": "chunk_e8a5d8bc", + "text": "If the hypervisor extension is additionally implemented, the `henvcfg`.ADUE field is also writable.", + "source_file": "src/priv/svadu.adoc", + "section": "Preamble > \"Svadu\" Extension for Hardware Updating of A/D Bits, Version 1.0", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 5, + 8 + ] + }, + { + "chunk_id": "chunk_201b3816", + "text": "See and for the definitions of those fields.", + "source_file": "src/priv/svadu.adoc", + "section": "Preamble > \"Svadu\" Extension for Hardware Updating of A/D Bits, Version 1.0", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 5, + 8 + ] + }, + { + "chunk_id": "chunk_733de6c7", + "text": "When hardware updating of A/D bits is disabled, the Svade extension, which mandates exceptions when A/D bits need be set, instead takes effect.", + "source_file": "src/priv/svadu.adoc", + "section": "Preamble > \"Svadu\" Extension for Hardware Updating of A/D Bits, Version 1.0", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 10, + 13 + ] + } + ] + }, + { + "file": "src/priv/svinval.adoc", + "chunks": [ + { + "chunk_id": "chunk_92ddd2e2", + "text": "When executed in order (but not necessarily consecutively) by a single hart, the sequence SFENCE.W.INVAL, SINVAL.VMA, and SFENCE.INVAL.IR has the same effect as a hypothetical SFENCE.VMA instruction in which:", + "source_file": "src/priv/svinval.adoc", + "section": "Preamble > \"Svinval\" Extension for Fine-Grained Address-Translation Cache Invalidation, Version 1.0", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 29, + 31 + ] + }, + { + "chunk_id": "chunk_caad67f7", + "text": "If the hypervisor extension is implemented, the Svinval extension also provides two additional instructions: HINVAL.VVMA and HINVAL.GVMA.", + "source_file": "src/priv/svinval.adoc", + "section": "Preamble > \"Svinval\" Extension for Fine-Grained Address-Translation Cache Invalidation, Version 1.0", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 44, + 49 + ] + }, + { + "chunk_id": "chunk_a8944c07", + "text": "SINVAL.VMA, HINVAL.VVMA, and HINVAL.GVMA require the same permissions and raise the same exceptions as SFENCE.VMA, HFENCE.VVMA, and HFENCE.GVMA, respectively.", + "source_file": "src/priv/svinval.adoc", + "section": "Preamble > \"Svinval\" Extension for Fine-Grained Address-Translation Cache Invalidation, Version 1.0", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 51, + 62 + ] + }, + { + "chunk_id": "chunk_250539d5", + "text": "In particular, an attempt to execute any of these instructions in U-mode always raises an illegal-instruction exception.", + "source_file": "src/priv/svinval.adoc", + "section": "Preamble > \"Svinval\" Extension for Fine-Grained Address-Translation Cache Invalidation, Version 1.0", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 51, + 62 + ] + }, + { + "chunk_id": "chunk_4db70e23", + "text": "An attempt to execute SINVAL.VMA or HINVAL.GVMA in S-mode or HS-mode when `mstatus`.TVM=1 also raises an illegal-instruction exception.", + "source_file": "src/priv/svinval.adoc", + "section": "Preamble > \"Svinval\" Extension for Fine-Grained Address-Translation Cache Invalidation, Version 1.0", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 51, + 62 + ] + }, + { + "chunk_id": "chunk_e2aac167", + "text": "An attempt to execute HINVAL.VVMA or HINVAL.GVMA in VS-mode or VU-mode, or to execute SINVAL.VMA in VU-mode, raises a virtual-instruction exception.", + "source_file": "src/priv/svinval.adoc", + "section": "Preamble > \"Svinval\" Extension for Fine-Grained Address-Translation Cache Invalidation, Version 1.0", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 51, + 62 + ] + }, + { + "chunk_id": "chunk_331e379d", + "text": "When `hstatus`.VTVM=1, an attempt to execute SINVAL.VMA in VS-mode also raises a virtual-instruction exception.", + "source_file": "src/priv/svinval.adoc", + "section": "Preamble > \"Svinval\" Extension for Fine-Grained Address-Translation Cache Invalidation, Version 1.0", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 51, + 62 + ] + }, + { + "chunk_id": "chunk_3ceb82f7", + "text": "Attempting to execute SFENCE.W.INVAL or SFENCE.INVAL.IR in U-mode raises an illegal-instruction exception.", + "source_file": "src/priv/svinval.adoc", + "section": "Preamble > \"Svinval\" Extension for Fine-Grained Address-Translation Cache Invalidation, Version 1.0", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 64, + 68 + ] + }, + { + "chunk_id": "chunk_b05e4f51", + "text": "Doing so in VU-mode raises a virtual-instruction exception. SFENCE.W.INVAL and SFENCE.INVAL.IR are unaffected by the `mstatus`.TVM and `hstatus`.VTVM fields and hence are always permitted in S-mode and VS-mode.", + "source_file": "src/priv/svinval.adoc", + "section": "Preamble > \"Svinval\" Extension for Fine-Grained Address-Translation Cache Invalidation, Version 1.0", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 64, + 68 + ] + } + ] + }, + { + "file": "src/priv/svnapot.adoc", + "chunks": [ + { + "chunk_id": "chunk_ecd6f9de", + "text": "In Sv39, Sv48, and Sv57, when a PTE has N=1, the PTE represents a translation that is part of a range of contiguous virtual-to-physical translations with the same values for PTE bits 5\u20130.", + "source_file": "src/priv/svnapot.adoc", + "section": "Preamble > \"Svnapot\" Extension for NAPOT Translation Contiguity, Version 1.0", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 3, + 8 + ] + }, + { + "chunk_id": "chunk_66d2331c", + "text": "Such ranges must be of a naturally aligned power-of-2 (NAPOT) granularity larger than the base page size.", + "source_file": "src/priv/svnapot.adoc", + "section": "Preamble > \"Svnapot\" Extension for NAPOT Translation Contiguity, Version 1.0", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 3, + 8 + ] + }, + { + "chunk_id": "chunk_7202caf4", + "text": "If the encoding in pte is reserved according to , then a page-fault exception must be raised.", + "source_file": "src/priv/svnapot.adoc", + "section": "Preamble > \"Svnapot\" Extension for NAPOT Translation Contiguity, Version 1.0", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 48, + 56 + ] + }, + { + "chunk_id": "chunk_faa2188a", + "text": "Implicit reads of NAPOT page table entries may create address-translation cache entries mapping a + j\u00d7PTESIZE to a copy of pte in which pte.ppn[i][pte.napotbits-1:0] is replaced by vpn[i][pte.napotbits-1:0], for any or all j such that j >> napotbits = vpn[i] >> napotbits, all for the address space identified in satp as loaded by step 1.", + "source_file": "src/priv/svnapot.adoc", + "section": "Preamble > \"Svnapot\" Extension for NAPOT Translation Contiguity, Version 1.0", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 58, + 64 + ] + }, + { + "chunk_id": "chunk_0a841634", + "text": "If the hypervisor extension is also implemented, Svnapot is also supported in G-stage translation.", + "source_file": "src/priv/svnapot.adoc", + "section": "Preamble > \"Svnapot\" Extension for NAPOT Translation Contiguity, Version 1.0", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 66, + 68 + ] + } + ] + }, + { + "file": "src/priv/svpbmt.adoc", + "chunks": [ + { + "chunk_id": "chunk_949e305e", + "text": "The Svpbmt extension depends on the Sv39 extension.", + "source_file": "src/priv/svpbmt.adoc", + "section": "Preamble > \"Svpbmt\" Extension for Page-Based Memory Types, Version 1.0", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 8, + 8 + ] + }, + { + "chunk_id": "chunk_ce829e0a", + "text": "Implementations may override additional PMAs not explicitly listed in .", + "source_file": "src/priv/svpbmt.adoc", + "section": "Preamble > \"Svpbmt\" Extension for Page-Based Memory Types, Version 1.0", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 29, + 34 + ] + }, + { + "chunk_id": "chunk_2bf0ed54", + "text": "Until their use is defined by a standard extension, they must be cleared by software for forward compatibility, or else a page-fault exception is raised.", + "source_file": "src/priv/svpbmt.adoc", + "section": "Preamble > \"Svpbmt\" Extension for Page-Based Memory Types, Version 1.0", + "confidence": "very_high", + "parameter_class": "SW_rule", + "parameter_type": "binary", + "line_range": [ + 36, + 39 + ] + }, + { + "chunk_id": "chunk_7dc4d6dd", + "text": "Until this value is defined by a standard extension, using this reserved value in a leaf PTE raises a page-fault exception.", + "source_file": "src/priv/svpbmt.adoc", + "section": "Preamble > \"Svpbmt\" Extension for Page-Based Memory Types, Version 1.0", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 41, + 44 + ] + }, + { + "chunk_id": "chunk_9a0950c8", + "text": "When PBMT settings override a main memory page into I/O or vice versa, memory accesses to such pages obey the memory ordering rules of the final effective attribute, as follows.", + "source_file": "src/priv/svpbmt.adoc", + "section": "Preamble > \"Svpbmt\" Extension for Page-Based Memory Types, Version 1.0", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 46, + 48 + ] + }, + { + "chunk_id": "chunk_0a01fde2", + "text": "If the underlying physical memory attribute for a page is I/O, and the page has PBMT=NC, then accesses to that page obey RVWMO.", + "source_file": "src/priv/svpbmt.adoc", + "section": "Preamble > \"Svpbmt\" Extension for Page-Based Memory Types, Version 1.0", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 50, + 54 + ] + }, + { + "chunk_id": "chunk_3b9c65a4", + "text": "If the underlying physical memory attribute for a page is main memory, and the page has PBMT=IO, then accesses to that page obey strong channel 0 I/O ordering rules.", + "source_file": "src/priv/svpbmt.adoc", + "section": "Preamble > \"Svpbmt\" Extension for Page-Based Memory Types, Version 1.0", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 56, + 62 + ] + }, + { + "chunk_id": "chunk_7ee25014", + "text": "When Svpbmt is used with non-zero PBMT encodings, it is possible for multiple virtual aliases of the same physical page to exist simultaneously with different memory attributes.", + "source_file": "src/priv/svpbmt.adoc", + "section": "Preamble > \"Svpbmt\" Extension for Page-Based Memory Types, Version 1.0", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 64, + 72 + ] + }, + { + "chunk_id": "chunk_91dd53d1", + "text": "It is also possible for a U-mode or S-mode mapping through a PTE with Svpbmt enabled to observe different memory attributes for a given region of physical memory than a concurrent access to the same page performed by M-mode or when MODE=Bare.", + "source_file": "src/priv/svpbmt.adoc", + "section": "Preamble > \"Svpbmt\" Extension for Page-Based Memory Types, Version 1.0", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 64, + 72 + ] + }, + { + "chunk_id": "chunk_483457c4", + "text": "In such cases, the behaviors dictated by the attributes (including coherence, which is otherwise unaffected) may be violated.", + "source_file": "src/priv/svpbmt.adoc", + "section": "Preamble > \"Svpbmt\" Extension for Page-Based Memory Types, Version 1.0", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 64, + 72 + ] + }, + { + "chunk_id": "chunk_0e9cb553", + "text": "Accessing the same location using different cacheability attributes may cause loss of coherence.", + "source_file": "src/priv/svpbmt.adoc", + "section": "Preamble > \"Svpbmt\" Extension for Page-Based Memory Types, Version 1.0", + "confidence": "medium", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 82, + 88 + ] + }, + { + "chunk_id": "chunk_0ab2df1f", + "text": "When two-stage address translation is enabled within the H extension, the page-based memory types are also applied in two stages.", + "source_file": "src/priv/svpbmt.adoc", + "section": "Preamble > \"Svpbmt\" Extension for Page-Based Memory Types, Version 1.0", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 90, + 99 + ] + }, + { + "chunk_id": "chunk_c6573d85", + "text": "First, if `hgatp`.MODE is not equal to zero, non-zero G-stage PTE PBMT bits override the attributes in the PMA to produce an intermediate set of attributes.", + "source_file": "src/priv/svpbmt.adoc", + "section": "Preamble > \"Svpbmt\" Extension for Page-Based Memory Types, Version 1.0", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 90, + 99 + ] + }, + { + "chunk_id": "chunk_b3b02c59", + "text": "Second, if `vsatp`.MODE is not equal to zero, non-zero VS-stage PTE PBMT bits override the intermediate attributes to produce the final set of attributes used by accesses to the page in question.", + "source_file": "src/priv/svpbmt.adoc", + "section": "Preamble > \"Svpbmt\" Extension for Page-Based Memory Types, Version 1.0", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 90, + 99 + ] + } + ] + }, + { + "file": "src/priv/svrsw60t59b.adoc", + "chunks": [ + { + "chunk_id": "chunk_777716e1", + "text": "If the Svrsw60t59b extension is implemented, then bits 60-59 of the page table entries (PTEs) are reserved for use by supervisor software and are ignored by the implementation.", + "source_file": "src/priv/svrsw60t59b.adoc", + "section": "Preamble > \"Svrsw60t59b\" Extension for PTE Reserved-for-Software Bits 60-59, Version 1.0", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 3, + 5 + ] + }, + { + "chunk_id": "chunk_f9f6c4f7", + "text": "If the Hypervisor (H) extension is also implemented, then bits 60-59 of the G-stage PTEs are reserved for use by supervisor software and are ignored by the implementation.", + "source_file": "src/priv/svrsw60t59b.adoc", + "section": "Preamble > \"Svrsw60t59b\" Extension for PTE Reserved-for-Software Bits 60-59, Version 1.0", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 7, + 9 + ] + } + ] + }, + { + "file": "src/priv/svvptc.adoc", + "chunks": [ + { + "chunk_id": "chunk_7c0a003a", + "text": "When the Svvptc extension is implemented, explicit stores by a hart that update the Valid bit of leaf and/or non-leaf PTEs from 0 to 1 and are visible to a hart will eventually become visible within a bounded timeframe to subsequent implicit accesses by that hart to such PTEs.", + "source_file": "src/priv/svvptc.adoc", + "section": "Preamble > \"Svvptc\" Extension for Obviating Memory-Management Instructions after Marking PTEs Valid, Version 1.0", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 3, + 6 + ] + } + ] + }, + { + "file": "src/priv/zpm.adoc", + "chunks": [ + { + "chunk_id": "chunk_7a5af1ed", + "text": "RISC-V Pointer Masking (PM) is a feature that, when enabled, causes the CPU to ignore the upper bits of the effective address (these terms will be defined more precisely in the Background section).", + "source_file": "src/priv/zpm.adoc", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 5, + 5 + ] + }, + { + "chunk_id": "chunk_94721f37", + "text": "When an address is accessed, the tag stored in the masked bits can be compared against a range-based tag.", + "source_file": "src/priv/zpm.adoc", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 5, + 5 + ] + }, + { + "chunk_id": "chunk_78883db8", + "text": "HWASAN leverages tags in the upper bits of the address to identify memory errors such as use-after-free or buffer overflow errors.", + "source_file": "src/priv/zpm.adoc", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 7, + 7 + ] + }, + { + "chunk_id": "chunk_52100761", + "text": "By storing a *pointer tag* in the upper bits of the address and checking it against a *memory tag* stored in a side table, it can identify whether a pointer is pointing to a valid location.", + "source_file": "src/priv/zpm.adoc", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 7, + 7 + ] + }, + { + "chunk_id": "chunk_ebe5c58a", + "text": "If implemented in software, pointer masking still provides performance benefits since non-checked accesses do not need to transform the address before every memory access.", + "source_file": "src/priv/zpm.adoc", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 9, + 9 + ] + }, + { + "chunk_id": "chunk_aceb5398", + "text": "We anticipate that future extensions may build on pointer masking to support this functionality in hardware.", + "source_file": "src/priv/zpm.adoc", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 9, + 9 + ] + }, + { + "chunk_id": "chunk_fbc8d538", + "text": "It is worth mentioning that while HWASAN is the primary use-case for the current pointer masking extension, a number of other hardware/software features may be implemented leveraging Pointer Masking.", + "source_file": "src/priv/zpm.adoc", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction", + "confidence": "medium", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 11, + 11 + ] + }, + { + "chunk_id": "chunk_9422a2ab", + "text": "For a virtual address to be valid, all bits in the unused portion of the address must be the same as the Most Significant Bit (MSB) of the used portion.", + "source_file": "src/priv/zpm.adoc", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Definitions", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 29, + 29 + ] + }, + { + "chunk_id": "chunk_c8278984", + "text": "For example, when page-based 48-bit virtual memory (Sv48) is used, load/store effective addresses, which are 64 bits, must have bits 63\u201348 all set to bit 47, or else a page-fault exception will occur.", + "source_file": "src/priv/zpm.adoc", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Definitions", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 29, + 29 + ] + }, + { + "chunk_id": "chunk_3f6adea4", + "text": "For physical addresses, validity means that bits XLEN-1 to PABITS are zero, where PABITS is the number of physical address bits supported by the processor.", + "source_file": "src/priv/zpm.adoc", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Definitions", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 29, + 29 + ] + }, + { + "chunk_id": "chunk_0365e5ec", + "text": "For virtual addresses, it replaces the upper PMLEN bits with the sign extension of the PMLEN+1st bit.", + "source_file": "src/priv/zpm.adoc", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > The \u201cIgnore\u201d Transformation", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 38, + 38 + ] + }, + { + "chunk_id": "chunk_1c81162f", + "text": "Pointer masking with the same value of PMLEN always has the same effect for the same type of address (virtual or physical).", + "source_file": "src/priv/zpm.adoc", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > The \u201cIgnore\u201d Transformation", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 63, + 63 + ] + }, + { + "chunk_id": "chunk_99b6538c", + "text": "shows an example of the pointer masking transformation on a virtual address when PM is enabled for RV64 under Sv57 (PMLEN=7).", + "source_file": "src/priv/zpm.adoc", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Example", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 67, + 67 + ] + }, + { + "chunk_id": "chunk_898786fb", + "text": "If the address was a physical address rather than a virtual address with Sv57, the transformed address with PMLEN=7 would be 0x1FFFFFF12345678.", + "source_file": "src/priv/zpm.adoc", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Example", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 86, + 86 + ] + }, + { + "chunk_id": "chunk_4c79b038", + "text": "In particular, applying the above transformation is cheap if it covers only bits that are not used by **any** supported address translation mode (as it is equivalent to switching off validity checks).", + "source_file": "src/priv/zpm.adoc", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Determining the Value of PMLEN", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 90, + 90 + ] + }, + { + "chunk_id": "chunk_02d6eb76", + "text": "Masking NVBITS beyond those bits is more expensive as it requires ignoring them in the TLB tag, and even more expensive if the masked bits extend into the VBITS portion of the address (as it requires performing the actual sign extension).", + "source_file": "src/priv/zpm.adoc", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Determining the Value of PMLEN", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 90, + 90 + ] + }, + { + "chunk_id": "chunk_1c4eaa8a", + "text": "Similarly, when running in Bare or M mode, it is common for implementations to not use a particular number of bits at the top of the physical address range and fix them to zero.", + "source_file": "src/priv/zpm.adoc", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Determining the Value of PMLEN", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 90, + 90 + ] + }, + { + "chunk_id": "chunk_969c9b50", + "text": "Applying the ignore transformation to those bits is cheap as well, since it will result in a valid physical address with all the upper bits fixed to 0.", + "source_file": "src/priv/zpm.adoc", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Determining the Value of PMLEN", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 90, + 90 + ] + }, + { + "chunk_id": "chunk_c693c7f7", + "text": "In such future standards, different supported values of PMLEN may be defined for each privilege mode (U/VU, S/HS, and M).", + "source_file": "src/priv/zpm.adoc", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Determining the Value of PMLEN", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 92, + 92 + ] + }, + { + "chunk_id": "chunk_a6f133bc", + "text": "Different privilege modes may have different pointer masking settings active simultaneously and the hardware will automatically apply the pointer masking settings of the currently active privilege mode. A privilege mode's pointer masking setting is configured by bits in configuration registers of the next-higher privilege mode.", + "source_file": "src/priv/zpm.adoc", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Pointer Masking and Privilege Modes", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 96, + 96 + ] + }, + { + "chunk_id": "chunk_3a71c473", + "text": "For other extensions, pointer masking applies to all explicit memory accesses by default.", + "source_file": "src/priv/zpm.adoc", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Memory Accesses Subject to Pointer Masking", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 114, + 114 + ] + }, + { + "chunk_id": "chunk_d464fac8", + "text": "Future extensions may add specific language to indicate whether particular accesses are or are not included in pointer masking.", + "source_file": "src/priv/zpm.adoc", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Memory Accesses Subject to Pointer Masking", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 114, + 114 + ] + }, + { + "chunk_id": "chunk_606de516", + "text": "In other words, the accessed bytes should be identical to the bytes that would be accessed if the pointer masking transformation was individually applied to every byte of the access without pointer masking.", + "source_file": "src/priv/zpm.adoc", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Memory Accesses Subject to Pointer Masking", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 120, + 120 + ] + }, + { + "chunk_id": "chunk_5fbc989b", + "text": "No pointer masking operations are applied when software reads/writes to CSRs, including those meant to hold addresses.", + "source_file": "src/priv/zpm.adoc", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Memory Accesses Subject to Pointer Masking", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 122, + 122 + ] + }, + { + "chunk_id": "chunk_d5fa3ce8", + "text": "If software stores tagged addresses into such CSRs, data load or data store operations based on those addresses are subject to pointer masking only if they are explicit () and pointer masking is enabled for the privilege mode that performs the access.", + "source_file": "src/priv/zpm.adoc", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Memory Accesses Subject to Pointer Masking", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 122, + 122 + ] + }, + { + "chunk_id": "chunk_a1328fcc", + "text": "Pointer masking is also applied, when applicable, to the memory access address when matching address triggers in debug.", + "source_file": "src/priv/zpm.adoc", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Memory Accesses Subject to Pointer Masking", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 124, + 124 + ] + }, + { + "chunk_id": "chunk_2d2f10a5", + "text": "However, when delivering an exception, the hardware applies pointer masking to any address written into `stval` if pointer masking is applicable to that address.", + "source_file": "src/priv/zpm.adoc", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Memory Accesses Subject to Pointer Masking", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": 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"unknown", + "parameter_type": "enum", + "line_range": [ + 135, + 137 + ] + }, + { + "chunk_id": "chunk_abd2209d", + "text": "In RV32, trying to enable pointer masking will result in an illegal WARL write and not update the pointer masking configuration bits (see , , , and for details).", + "source_file": "src/priv/zpm.adoc", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Pointer Masking Extensions", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 146, + 146 + ] + }, + { + "chunk_id": "chunk_a63e63dc", + "text": "The same is the case on RV64 or larger systems when UXL/SXL/MXL is set to 1 for the corresponding privilege mode.", + "source_file": "src/priv/zpm.adoc", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Pointer Masking Extensions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 146, + 146 + ] + }, + { + "chunk_id": "chunk_68637b97", + "text": "As described in , the supported values of PMLEN may depend on the effective privilege mode.", + "source_file": "src/priv/zpm.adoc", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Number of Masked Bits", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 150, + 150 + ] + }, + { + "chunk_id": "chunk_211e7d6b", + "text": "The current standard only defines PMLEN=XLEN-48 and PMLEN=XLEN-57, but this assumption may be relaxed in future extensions and profiles.", + "source_file": "src/priv/zpm.adoc", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Number of Masked Bits", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 150, + 150 + ] + }, + { + "chunk_id": "chunk_9bc8489d", + "text": "Trying to enable pointer masking in an unsupported scenario represents an illegal write to the corresponding pointer masking enable bit and follows WARL semantics.", + "source_file": "src/priv/zpm.adoc", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Number of Masked Bits", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 150, + 150 + ] + }, + { + "chunk_id": "chunk_57183289", + "text": "Future profiles may choose to define certain combinations of privilege modes and supported values of PMLEN as mandatory.", + "source_file": "src/priv/zpm.adoc", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Number of Masked Bits", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 150, + 150 + ] + } + ] + }, + { + "file": "src/profiles/intro.adoc", + "chunks": [ + { + "chunk_id": "chunk_15e60371", + "text": "In addition, users may add their own custom extensions.", + "source_file": "src/profiles/intro.adoc", + "section": "Preamble > Introduction", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 2, + 12 + ] + }, + { + "chunk_id": "chunk_80de899b", + "text": "Similarly, hardware vendors should aim to structure their offerings around standard profiles to increase the likelihood their designs will have mainstream software support.", + "source_file": "src/profiles/intro.adoc", + "section": "Preamble > Introduction", + "confidence": "medium", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 18, + 29 + ] + }, + { + "chunk_id": "chunk_2770a245", + "text": "A profile family may be updated no more than annually, and the release calendar year is treated as part of the profile family name.", + "source_file": "src/profiles/intro.adoc", + "section": "Preamble > Introduction > Components of a Profile > Profile Family", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 100, + 101 + ] + }, + { + "chunk_id": "chunk_7d2c8e02", + "text": "A profile may specify that certain conditions will cause a requested trap (such as an `ecall` made in the highest-supported privilege mode) or fatal trap to the enclosing execution environment.", + "source_file": "src/profiles/intro.adoc", + "section": "Preamble > Introduction > Components of a Profile > Profile Privilege Mode", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 134, + 138 + ] + }, + { + "chunk_id": "chunk_2fbe7cda", + "text": "The profile does not specify the behavior of the enclosing execution environment in handling requested or fatal traps.", + "source_file": "src/profiles/intro.adoc", + "section": "Preamble > Introduction > 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options) contains extensions that may be added as options, and which are expected to be generally supported as options by the software ecosystem for this profile.", + "source_file": "src/profiles/intro.adoc", + "section": "Preamble > Introduction > Components of a Profile > Profile ISA Features", + "confidence": "medium", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 180, + 182 + ] + }, + { + "chunk_id": "chunk_b756df3c", + "text": "Users would expect that software claiming compatibility with a profile would make use of any available supported options, but as a bare minimum software should not report errors or warnings when supported options are present in a system.", + "source_file": "src/profiles/intro.adoc", + "section": "Preamble > Introduction > Components of a Profile > Profile ISA Features", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "range", + "line_range": [ + 184, + 189 + ] + }, + { + "chunk_id": "chunk_7e0a106d", + "text": "An optional extension may comprise many individually named and ratified extensions but a profile option requires all constituent extensions are present.", + "source_file": "src/profiles/intro.adoc", + "section": "Preamble > Introduction > Components of a Profile > Profile ISA Features", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 191, + 197 + ] + }, + { + "chunk_id": "chunk_96f9daf0", + "text": "In particular, unless explicitly listed as a profile option, individual extensions are not by themselves a profile option even when required as part of a profile option.", + "source_file": "src/profiles/intro.adoc", + "section": "Preamble > Introduction > Components of a Profile > Profile ISA Features", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 191, + 197 + ] + }, + { + "chunk_id": "chunk_9ffe54a6", + "text": "All components of a ratified profile must themselves have been ratified.", + "source_file": "src/profiles/intro.adoc", + "section": "Preamble > Introduction > Components of a Profile > Profile ISA Features", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 203, + 204 + ] + }, + { + "chunk_id": "chunk_247e3794", + "text": "Platforms may provide a discovery mechanism to determine what optional extensions are present.", + "source_file": "src/profiles/intro.adoc", + "section": "Preamble > Introduction > Components of a Profile > Profile ISA Features", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 206, + 207 + ] + }, + { + "chunk_id": "chunk_e369cd93", + "text": "RVI20U32 basic unprivileged instructions for RV32I - RVI20U64 basic unprivileged instructions for RV64I - RVA20U64, RVA20S64 64-bit application-processor profiles", + "source_file": "src/profiles/intro.adoc", + "section": "Preamble > Introduction > Components of a Profile > Profile Naming Convention", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 241, + 243 + ] + }, + { + "chunk_id": "chunk_80a99345", + "text": "The RISC-V International ISA extension ratification process ensures that all processor vendors have agreed to the specification of a standard extension if present.", + "source_file": "src/profiles/intro.adoc", + "section": "Preamble > Introduction > Components of a Profile > RVA Profiles Rationale", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 268, + 272 + ] + }, + { + "chunk_id": "chunk_e2e689f3", + "text": "Without proactive alignment through RVA profiles, RISC-V will be uncompetitive, as even if a particular vendor implements a certain feature, if other vendors do not, then binary distributions will not generally use that feature and all implementations will suffer.", + "source_file": "src/profiles/intro.adoc", + "section": "Preamble > Introduction > Components of a Profile > RVA Profiles Rationale", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 279, + 294 + ] + }, + { + "chunk_id": "chunk_f2406c1c", + "text": "While certain features may be discoverable, and alternate code provided in case of presence/absence of a feature, the added cost to support such options is only justified for certain limited cases, and binary app markets will not support a wide range of optional features, particularly for the nascent RISC-V binary app ecosystems.", + "source_file": "src/profiles/intro.adoc", + "section": "Preamble > Introduction > Components of a Profile > RVA Profiles Rationale", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 279, + 294 + ] + }, + { + "chunk_id": "chunk_8d010d53", + "text": "To maintain alignment and increase RISC-V competitiveness over time, the mandatory set of extensions must increase over time in successive generations of RVA profile. (RVA profiles may eventually have to deprecate previously mandatory instructions, but that is unlikely in the near future.) Note that the RISC-V ISA will continue to evolve, regardless of whether a given software ecosystem settles on a certain generation of profile as the baseline for their ecosystem for many years or even decades.", + "source_file": "src/profiles/intro.adoc", + "section": "Preamble > Introduction > Components of a Profile > RVA Profiles Rationale", + "confidence": "very_high", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 296, + 309 + ] + }, + { + "chunk_id": "chunk_a6e7f95f", + "text": "Processor vendors and software toolchain providers will have varying development schedules, and providing an optional phase in a new extension's lifecycle provides some flexibility while maintaining overall alignment, and is particularly appropriate when hardware or software development for the extension is complex.", + "source_file": "src/profiles/intro.adoc", + "section": "Preamble > Introduction > Components of a Profile > RVA Profiles Rationale", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 323, + 333 + ] + }, + { + "chunk_id": "chunk_26d28117", + "text": "Denoting an extension as a development option signals to the community that development should be prioritized for such extensions as they will become mandatory.", + "source_file": "src/profiles/intro.adoc", + "section": "Preamble > Introduction > Components of a Profile > RVA Profiles Rationale", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 323, + 333 + ] + }, + { + "chunk_id": "chunk_3e279dae", + "text": "The third kind of optional extension are expansion options, which are those that may have a large implementation cost but are not always needed in a particular platform, and which can be readily handled by discovery.", + "source_file": "src/profiles/intro.adoc", + "section": "Preamble > Introduction > Components of a Profile > RVA Profiles Rationale", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 335, + 345 + ] + }, + { + "chunk_id": "chunk_26341481", + "text": "Some unprivileged extensions that may fall into this category are possible future matrix extensions.", + "source_file": "src/profiles/intro.adoc", + "section": "Preamble > Introduction > Components of a Profile > RVA Profiles Rationale", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 335, + 345 + ] + }, + { + "chunk_id": "chunk_79555281", + "text": "The fourth kind of optional extensions are transitory options, where it is not clear if the extension will change to a mandatory, localized, or expansion option, or be possibly dropped over time.", + "source_file": "src/profiles/intro.adoc", + "section": "Preamble > Introduction > Components of a Profile > RVA Profiles Rationale", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 347, + 359 + ] + }, + { + "chunk_id": "chunk_997e100b", + "text": "Denoting an option as transitory signals to the community that this extension may be removed in a future profile, though the time scale may span many years.", + "source_file": "src/profiles/intro.adoc", + "section": "Preamble > Introduction > Components of a Profile > RVA Profiles Rationale", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 347, + 359 + ] + }, + { + "chunk_id": "chunk_c80eb3e8", + "text": "Binary distributions of applications willing to invest in discovery can use an optional extension, and customers compiling their own applications can take advantage of the feature on a particular implementation, even when that system is mostly running binary distributions that ignore the new extension.", + "source_file": "src/profiles/intro.adoc", + "section": "Preamble > Introduction > Components of a Profile > RVA Profiles Rationale", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 361, + 370 + ] + } + ] + }, + { + "file": "src/profiles/preface.adoc", + "chunks": [ + { + "chunk_id": "chunk_b5b626cd", + "text": "Clarified that profile name can be used as ISA base string - Renamed Ssptead to Svade - Fixed Ssu64xl to make supporting UXL=64 mandatory - Added section listing new extension names in profiles document - Added new extension name Sscounterenw - Removed outdated text on Zicntr/Zihpm ratification plan", + "source_file": "src/profiles/preface.adoc", + "section": "Preamble > Preface", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 33, + 38 + ] + } + ] + }, + { + "file": "src/profiles/rva20.adoc", + "chunks": [ + { + "chunk_id": "chunk_0fda19b9", + "text": "The RVA20U64 profile specifies the ISA features available to user-mode execution environments in 64-bit applications processors.", + "source_file": "src/profiles/rva20.adoc", + "section": "Preamble > RVA20 Profiles > RVA20U64 Profile", + "confidence": "medium", + "parameter_class": "SW_rule", + "parameter_type": "range", + "line_range": [ + 21, + 24 + ] + }, + { + "chunk_id": "chunk_155d4f9b", + "text": "The RVA20S64 profile specifies the ISA features available to a supervisor-mode execution environment in 64-bit applications processors. RVA20S64 is based on privileged architecture version 1.11.", + "source_file": "src/profiles/rva20.adoc", + "section": "Preamble > RVA20 Profiles > RVA20S64 Profile", + "confidence": "medium", + "parameter_class": "SW_rule", + "parameter_type": "range", + "line_range": [ + 120, + 123 + ] + } + ] + }, + { + "file": "src/profiles/rva22.adoc", + "chunks": [ + { + "chunk_id": "chunk_4168f1ab", + "text": "The RVA22U64 profile specifies the ISA features available to user-mode execution environments in 64-bit applications processors.", + "source_file": "src/profiles/rva22.adoc", + "section": "Preamble > RVA22 Profiles > RVA22U64 Profile", + "confidence": "medium", + "parameter_class": "SW_rule", + "parameter_type": "range", + "line_range": [ + 8, + 11 + ] + }, + { + "chunk_id": "chunk_a68349fe", + "text": "Profile implementers should provide all of the instructions in a given algorithm suite as part of the Zkn or Zks supported options.", + "source_file": "src/profiles/rva22.adoc", + "section": "Preamble > RVA22 Profiles > RVA22U64 Profile > RVA22U64 Optional Extensions", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 128, + 132 + ] + }, + { + "chunk_id": "chunk_dda53980", + "text": "The RVA22S64 profile specifies the ISA features available to a supervisor-mode execution environment in 64-bit applications processors. RVA22S64 is based on privileged architecture version 1.12.", + "source_file": "src/profiles/rva22.adoc", + "section": "Preamble > RVA22 Profiles > RVA22S64 Profile", + "confidence": "medium", + "parameter_class": "SW_rule", + "parameter_type": "range", + "line_range": [ + 153, + 156 + ] + } + ] + }, + { + "file": "src/profiles/rva23.adoc", + "chunks": [ + { + "chunk_id": "chunk_44b8fbfe", + "text": "The RVA23U64 profile specifies the ISA features available to user-mode execution environments in 64-bit applications processors.", + "source_file": "src/profiles/rva23.adoc", + "section": "Preamble > RVA23 Profiles > RVA23U64 Profile", + "confidence": "medium", + "parameter_class": "SW_rule", + "parameter_type": "range", + "line_range": [ + 15, + 18 + ] + }, + { + "chunk_id": "chunk_8ef0b68d", + "text": "These are implied by presence of F. - Base counters and timers. - Hardware performance counters. - Main memory regions with both the cacheability and coherence PMAs must support instruction fetch, and any instruction fetches of naturally aligned power-of-2 sizes up to min(ILEN,XLEN) (i.e., 32 bits for RVA23) are atomic. - Main memory regions with both the cacheability and coherence PMAs must support RsrvEventual. - Main memory regions with both the cacheability and coherence PMAs must support all atomics in the Zaamo extension. - Misaligned loads and stores to main memory regions with both the cacheability and coherence PMAs must be supported. - Reservation sets are contiguous, naturally aligned, and a maximum of 64 bytes. - Pause hint. - Cache blocks must be 64 bytes in size, naturally aligned in the address space. - Cache-block management instructions. - Cache-block prefetch instructions. - Cache-Block Zero Instructions. - ext:zfhmin[] Half-precision floating-point. - Data-independent execution latency.", + "source_file": "src/profiles/rva23.adoc", + "section": "Preamble > RVA23 Profiles > RVA23U64 Profile > RVA23U64 Mandatory Extensions", + "confidence": "very_high", + "parameter_class": "SW_rule", + "parameter_type": "range", + "line_range": [ + 30, + 58 + ] + }, + { + "chunk_id": "chunk_374cbbf6", + "text": "The RVA23S64 profile specifies the ISA features available to a supervisor-mode execution environment in 64-bit applications processors. RVA23S64 is based on privileged architecture version 1.13.", + "source_file": "src/profiles/rva23.adoc", + "section": "Preamble > RVA23 Profiles > RVA23S64 Profile", + "confidence": "medium", + "parameter_class": "SW_rule", + "parameter_type": "range", + "line_range": [ + 160, + 163 + ] + } + ] + }, + { + "file": "src/profiles/rvb23.adoc", + "chunks": [ + { + "chunk_id": "chunk_2ad5f49d", + "text": "However, individual software ecosystems may build upon RVB profiles to produce a more targeted standard interface for a certain market.", + "source_file": "src/profiles/rvb23.adoc", + "section": "Preamble > RVB23 Profiles", + "confidence": "medium", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 13, + 17 + ] + }, + { + "chunk_id": "chunk_c81064e0", + "text": "The RVB23U64 profile specifies the ISA features available to user-mode execution environments in 64-bit RVB applications processors.", + "source_file": "src/profiles/rvb23.adoc", + "section": "Preamble > RVB23 Profiles > RVB23U64 Profile", + "confidence": "medium", + "parameter_class": "SW_rule", + "parameter_type": "range", + "line_range": [ + 24, + 25 + ] + }, + { + "chunk_id": "chunk_e06353df", + "text": "These are implied by presence of F. - Base counters and timers. - Hardware performance counters. - Main memory regions with both the cacheability and coherence PMAs must support instruction fetch, and any instruction fetches of naturally aligned power-of-2 sizes up to min(ILEN,XLEN) (i.e., 32 bits for RVB23) are atomic. - Main memory regions with both the cacheability and coherence PMAs must support RsrvEventual. - Main memory regions with both the cacheability and coherence PMAs must support all atomics in the Zaamo extension. - Misaligned loads and stores to main memory regions with both the cacheability and coherence PMAs must be supported. - Reservation sets are contiguous, naturally aligned, and a maximum of 64 bytes. - Pause hint. - Cache blocks must be 64 bytes in size, naturally aligned in the address space. - Cache-block management instructions. - Cache-block prefetch instructions. - Cache-block zero instructions. - Data-independent execution latency.", + "source_file": "src/profiles/rvb23.adoc", + "section": "Preamble > RVB23 Profiles > RVB23U64 Profile > RVB23U64 Mandatory Extensions", + "confidence": "very_high", + "parameter_class": "SW_rule", + "parameter_type": "range", + "line_range": [ + 38, + 65 + ] + }, + { + "chunk_id": "chunk_b2aa2c8c", + "text": "The RVB23S64 profile specifies the ISA features available to a supervisor-mode execution environment in 64-bit applications processors. RVB23S64 is based on privileged architecture version 1.13.", + "source_file": "src/profiles/rvb23.adoc", + "section": "Preamble > RVB23 Profiles > RVB23S64 Profile", + "confidence": "medium", + "parameter_class": "SW_rule", + "parameter_type": "range", + "line_range": [ + 163, + 165 + ] + }, + { + "chunk_id": "chunk_45997cfd", + "text": "When the hypervisor extension is implemented, the following are also mandatory:", + "source_file": "src/profiles/rvb23.adoc", + "section": "Preamble > RVB23 Profiles > RVB23S64 Profile > RVB23S64 Optional Extensions > Expansion Options", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 262, + 262 + ] + }, + { + "chunk_id": "chunk_1a2d97bd", + "text": "If the hypervisor extension is implemented and pointer masking (Ssnpm) is supported then `henvcfg.PMM` must support at minimum, settings PMLEN=0 and PMLEN=7.", + "source_file": "src/profiles/rvb23.adoc", + "section": "Preamble > RVB23 Profiles > RVB23S64 Profile > RVB23S64 Optional Extensions > Expansion Options", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 264, + 266 + ] + } + ] + }, + { + "file": "src/profiles/rvi20.adoc", + "chunks": [ + { + "chunk_id": "chunk_9593181a", + "text": "Code using this profile can run in any privilege mode, and so requested and fatal traps may be horizontal traps into an execution environment running in the same privilege mode.", + "source_file": "src/profiles/rvi20.adoc", + "section": "Preamble > RVI20 Profiles", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 8, + 12 + ] + } + ] + }, + { + "file": "src/rv32.adoc", + "chunks": [ + { + "chunk_id": "chunk_dde43ce4", + "text": "All are a fixed 32 bits in length.", + "source_file": "src/rv32.adoc", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Base Instruction Formats", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 59, + 66 + ] + }, + { + "chunk_id": "chunk_72a433ee", + "text": "The base ISA has `IALIGN=32`, meaning that instructions must be aligned on a four-byte boundary in memory.", + "source_file": "src/rv32.adoc", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Base Instruction Formats", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 59, + 66 + ] + }, + { + "chunk_id": "chunk_f8060209", + "text": "An instruction-address-misaligned exception is generated on a taken branch or unconditional jump if the target address is not `IALIGN-bit` aligned.", + "source_file": "src/rv32.adoc", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Base Instruction Formats", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 59, + 66 + ] + }, + { + "chunk_id": "chunk_e7a49c43", + "text": "This exception is reported on the branch or jump instruction, not on the target instruction.", + "source_file": "src/rv32.adoc", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Base Instruction Formats", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 59, + 66 + ] + }, + { + "chunk_id": "chunk_3a4aa590", + "text": "No instruction-address-misaligned exception is generated for a conditional branch that is not taken.", + "source_file": "src/rv32.adoc", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Base Instruction Formats", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 59, + 66 + ] + }, + { + "chunk_id": "chunk_9319c030", + "text": "Except for the 5-bit immediates used in , immediates are always sign-extended, and are generally packed towards the leftmost available bits in the instruction and have been allocated to reduce hardware complexity.", + "source_file": "src/rv32.adoc", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Base Instruction Formats", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 70, + 77 + ] + }, + { + "chunk_id": "chunk_4594bc74", + "text": "In particular, the sign bit for all immediates is always in bit 31 of the instruction to speed sign-extension circuitry.", + "source_file": "src/rv32.adoc", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Base Instruction Formats", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 70, + 77 + ] + }, + { + "chunk_id": "chunk_0fbea2de", + "text": "The only difference between the S and B formats is that the 12-bit immediate field is used to encode branch offsets in multiples of 2 in the B format.", + "source_file": "src/rv32.adoc", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Immediate Encoding Variants", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 91, + 96 + ] + }, + { + "chunk_id": "chunk_0a395b3c", + "text": "Similarly, the only difference between the U and J formats is that the 20-bit immediate is shifted left by 12 bits to form U immediates and by 1 bit to form J immediates.", + "source_file": "src/rv32.adoc", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Immediate Encoding Variants", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 98, + 102 + ] + }, + { + "chunk_id": "chunk_b05bec50", + "text": "The fields are labeled with the instruction bits used to construct their value.", + "source_file": "src/rv32.adoc", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Immediate Encoding Variants", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 120, + 120 + ] + }, + { + "chunk_id": "chunk_ad69f5da", + "text": "Integer computational instructions are either encoded as register-immediate operations using the I-type format or as register-register operations using the R-type format.", + "source_file": "src/rv32.adoc", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 126, + 132 + ] + }, + { + "chunk_id": "chunk_49059c53", + "text": "No integer computational instructions cause arithmetic exceptions.", + "source_file": "src/rv32.adoc", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 126, + 132 + ] + }, + { + "chunk_id": "chunk_94ce4b43", + "text": "ADDI adds the sign-extended 12-bit immediate to register rs1.", + "source_file": "src/rv32.adoc", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Immediate Instructions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 139, + 141 + ] + }, + { + "chunk_id": "chunk_84b1ff1d", + "text": "ANDI, ORI, XORI are logical operations that perform bitwise AND, OR, and XOR on register rs1 and the sign-extended 12-bit immediate and place the result in rd.", + "source_file": "src/rv32.adoc", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Immediate Instructions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 151, + 154 + ] + }, + { + "chunk_id": "chunk_4b7c9b86", + "text": "Shifts by a constant are encoded as a specialization of the I-type format.", + "source_file": "src/rv32.adoc", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Immediate Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 160, + 166 + ] + }, + { + "chunk_id": "chunk_12f0b8cc", + "text": "The operand to be shifted is in rs1, and the shift amount is encoded in the lower 5 bits of the I-immediate field.", + "source_file": "src/rv32.adoc", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Immediate Instructions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 160, + 166 + ] + }, + { + "chunk_id": "chunk_e620a15d", + "text": "The right-shift type is encoded in bit 30. SLLI is a logical left shift (zeros are shifted into the lower bits); SRLI is a logical right shift (zeros are shifted into the upper bits); and SRAI is an arithmetic right shift (the original sign bit is copied into the vacated upper bits).", + "source_file": "src/rv32.adoc", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Immediate Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 160, + 166 + ] + }, + { + "chunk_id": "chunk_b359ead1", + "text": "LUI (load upper immediate) is used to build 32-bit constants and uses the U-type format. LUI places the 32-bit U-immediate value into the destination register rd, filling in the lowest 12 bits with zeros.", + "source_file": "src/rv32.adoc", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Immediate Instructions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 172, + 174 + ] + }, + { + "chunk_id": "chunk_ce0e4a7b", + "text": "AUIPC (add upper immediate to `pc`) is used to build `pc`-relative addresses and uses the U-type format. AUIPC forms a 32-bit offset from the U-immediate, filling in the lowest 12 bits with zeros, adds this offset to the address of the AUIPC instruction, then places the result in register rd.", + "source_file": "src/rv32.adoc", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Immediate Instructions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 176, + 181 + ] + }, + { + "chunk_id": "chunk_915f6f0d", + "text": "RV32I defines several arithmetic R-type operations.", + "source_file": "src/rv32.adoc", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Register Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 185, + 187 + ] + }, + { + "chunk_id": "chunk_bdfe71e4", + "text": "All operations read the rs1 and rs2 registers as source operands and write the result into register rd.", + "source_file": "src/rv32.adoc", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Register Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 185, + 187 + ] + }, + { + "chunk_id": "chunk_7b519a6d", + "text": "The funct7 and funct3 fields select the type of operation.", + "source_file": "src/rv32.adoc", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Register Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 185, + 187 + ] + }, + { + "chunk_id": "chunk_34f52cee", + "text": "ADD performs the addition of rs1 and rs2. SUB performs the subtraction of rs2 from rs1.", + "source_file": "src/rv32.adoc", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Register Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 193, + 200 + ] + }, + { + "chunk_id": "chunk_2bfdf820", + "text": "Overflows are ignored and the low XLEN bits of results are written to the destination rd. SLT and SLTU perform signed and unsigned compares respectively, writing 1 to rd if rs1 < rs2, 0 otherwise.", + "source_file": "src/rv32.adoc", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Register Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "range", + "line_range": [ + 193, + 200 + ] + }, + { + "chunk_id": "chunk_1905f0e5", + "text": "SLL, SRL, and SRA perform logical left, logical right, and arithmetic right shifts on the value in register rs1 by the shift amount held in the lower 5 bits of register rs2.", + "source_file": "src/rv32.adoc", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Register Instructions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 202, + 204 + ] + }, + { + "chunk_id": "chunk_f37f2594", + "text": "The NOP instruction does not change any architecturally visible state, except for advancing the `pc` and incrementing any applicable performance counters. NOP is encoded as ADDI x0, x0, 0.", + "source_file": "src/rv32.adoc", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > NOP Instruction", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 212, + 214 + ] + }, + { + "chunk_id": "chunk_ec88eefb", + "text": "If an instruction access-fault or instruction page-fault exception occurs on the target of a jump or taken branch, the exception is reported on the target instruction, not on the jump or branch instruction.", + "source_file": "src/rv32.adoc", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Control Transfer Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 223, + 225 + ] + }, + { + "chunk_id": "chunk_d81dc38f", + "text": "The jump and link (JAL) instruction uses the J-type format, where the J-immediate encodes a signed offset in multiples of 2 bytes.", + "source_file": "src/rv32.adoc", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Control Transfer Instructions > Unconditional Jumps", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 228, + 235 + ] + }, + { + "chunk_id": "chunk_917bdbde", + "text": "The offset is sign-extended and added to the address of the jump instruction to form the jump target address.", + "source_file": "src/rv32.adoc", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Control Transfer Instructions > Unconditional Jumps", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 228, + 235 + ] + }, + { + "chunk_id": "chunk_01cc4f0c", + "text": "Plain unconditional jumps (assembler pseudoinstruction J) are encoded as a JAL with rd=`x0`.", + "source_file": "src/rv32.adoc", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Control Transfer Instructions > Unconditional Jumps", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 237, + 238 + ] + }, + { + "chunk_id": "chunk_e8acee9e", + "text": "The target address is obtained by adding the sign-extended 12-bit I-immediate to the register rs1, then setting the least-significant bit of the result to zero.", + "source_file": "src/rv32.adoc", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Control Transfer Instructions > Unconditional Jumps", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 244, + 251 + ] + }, + { + "chunk_id": "chunk_ece4ef36", + "text": "Plain unconditional indirect jumps (assembler pseudoinstruction JR) are encoded as a JALR with rd=`x0`.", + "source_file": "src/rv32.adoc", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Control Transfer Instructions > Unconditional Jumps", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 253, + 257 + ] + }, + { + "chunk_id": "chunk_9ecf4a48", + "text": "Procedure returns in the standard calling convention (assembler pseudoinstruction RET) are encoded as a JALR with rd=`x0`, rs1=`x1`, and imm=0.", + "source_file": "src/rv32.adoc", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Control Transfer Instructions > Unconditional Jumps", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 253, + 257 + ] + }, + { + "chunk_id": "chunk_dfe1ce09", + "text": "The JAL and JALR instructions will generate an instruction-address-misaligned exception if the target address is not aligned to a four-byte boundary.", + "source_file": "src/rv32.adoc", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Control Transfer Instructions > Unconditional Jumps", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 263, + 266 + ] + }, + { + "chunk_id": "chunk_9f5519b1", + "text": "For RISC-V, hints as to the instructions' usage are encoded implicitly via the register numbers used. A JAL instruction should push the return address onto a return-address stack (RAS) only when rd is `x1` or `x5`. JALR instructions should push/pop a RAS as shown in .", + "source_file": "src/rv32.adoc", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Control Transfer Instructions > Unconditional Jumps", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 268, + 274 + ] + }, + { + "chunk_id": "chunk_f184ab33", + "text": "The 12-bit B-immediate encodes signed offsets in multiples of 2 bytes.", + "source_file": "src/rv32.adoc", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Control Transfer Instructions > Conditional Branches", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 295, + 298 + ] + }, + { + "chunk_id": "chunk_44817fbd", + "text": "The offset is sign-extended and added to the address of the branch instruction to give the target address.", + "source_file": "src/rv32.adoc", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Control Transfer Instructions > Conditional Branches", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 295, + 298 + ] + }, + { + "chunk_id": "chunk_9914be09", + "text": "Branch instructions compare two registers. BEQ and BNE take the branch if registers rs1 and rs2 are equal or unequal respectively. BLT and BLTU take the branch if rs1 is less than rs2, using signed and unsigned comparison respectively. BGE and BGEU take the branch if rs1 is greater than or equal to rs2, using signed and unsigned comparison respectively.", + "source_file": "src/rv32.adoc", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Control Transfer Instructions > Conditional Branches", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "range", + "line_range": [ + 304, + 311 + ] + }, + { + "chunk_id": "chunk_69267ea6", + "text": "Software should be optimized such that the sequential code path is the most common path, with less-frequently taken code paths placed out of line.", + "source_file": "src/rv32.adoc", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Control Transfer Instructions > Conditional Branches", + "confidence": "medium", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 313, + 318 + ] + }, + { + "chunk_id": "chunk_bbd08a71", + "text": "Software should also assume that backward branches will be predicted taken and forward branches as not taken, at least the first time they are encountered.", + "source_file": "src/rv32.adoc", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Control Transfer Instructions > Conditional Branches", + "confidence": "medium", + "parameter_class": "SW_rule", + "parameter_type": "range", + "line_range": [ + 313, + 318 + ] + }, + { + "chunk_id": "chunk_c1aeac41", + "text": "Dynamic predictors should quickly learn any predictable branch behavior.", + "source_file": "src/rv32.adoc", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Control Transfer Instructions > Conditional Branches", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 313, + 318 + ] + }, + { + "chunk_id": "chunk_33e4b2e1", + "text": "Unlike some other architectures, the RISC-V jump (JAL with rd=`x0`) instruction should always be used for unconditional branches instead of a conditional branch instruction with an always-true condition. RISC-V jumps are also PC-relative and support a much wider offset range than branches, and will not pollute conditional-branch prediction tables.", + "source_file": "src/rv32.adoc", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Control Transfer Instructions > Conditional Branches", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 320, + 324 + ] + }, + { + "chunk_id": "chunk_c28b211b", + "text": "The conditional branch instructions will generate an instruction-address-misaligned exception if the target address is not aligned to a four-byte boundary and the branch condition evaluates to true.", + "source_file": "src/rv32.adoc", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Control Transfer Instructions > Conditional Branches", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 326, + 330 + ] + }, + { + "chunk_id": "chunk_e7513289", + "text": "If the branch condition evaluates to false, the instruction-address-misaligned exception will not be raised.", + "source_file": "src/rv32.adoc", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Control Transfer Instructions > Conditional Branches", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 326, + 330 + ] + }, + { + "chunk_id": "chunk_ca8fd2de", + "text": "RV32I is a load-store architecture, where only load and store instructions access memory and arithmetic instructions only operate on CPU registers. RV32I provides a 32-bit address space that is byte-addressed.", + "source_file": "src/rv32.adoc", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Load and Store Instructions", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 335, + 343 + ] + }, + { + "chunk_id": "chunk_ae16cad0", + "text": "Loads with a destination of `x0` must still raise any exceptions and cause any other side effects even though the load value is discarded.", + "source_file": "src/rv32.adoc", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Load and Store Instructions", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 335, + 343 + ] + }, + { + "chunk_id": "chunk_5569c979", + "text": "Loads are encoded in the I-type format and stores are S-type.", + "source_file": "src/rv32.adoc", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Load and Store Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 352, + 357 + ] + }, + { + "chunk_id": "chunk_2a8af18e", + "text": "The effective address is obtained by adding register rs1 to the sign-extended 12-bit offset.", + "source_file": "src/rv32.adoc", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Load and Store Instructions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 352, + 357 + ] + }, + { + "chunk_id": "chunk_4da3d9dc", + "text": "The LW instruction loads a 32-bit value from memory into rd. LH loads a 16-bit value from memory, then sign-extends to 32-bits before storing in rd. LHU loads a 16-bit value from memory but then zero extends to 32-bits before storing in rd. LB and LBU are defined analogously for 8-bit values.", + "source_file": "src/rv32.adoc", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Load and Store Instructions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 359, + 366 + ] + }, + { + "chunk_id": "chunk_57fdf6ef", + "text": "The SW, SH, and SB instructions store 32-bit, 16-bit, and 8-bit values from the low bits of register rs2 to memory.", + "source_file": "src/rv32.adoc", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Load and Store Instructions", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 359, + 366 + ] + }, + { + "chunk_id": "chunk_d8c7e353", + "text": "Regardless of EEI, loads and stores whose effective addresses are naturally aligned shall not raise an address-misaligned exception.", + "source_file": "src/rv32.adoc", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Load and Store Instructions", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 368, + 372 + ] + }, + { + "chunk_id": "chunk_ae37b9d2", + "text": "An EEI may guarantee that misaligned loads and stores are fully supported, and so the software running inside the execution environment will never experience a contained or fatal address-misaligned trap.", + "source_file": "src/rv32.adoc", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Load and Store Instructions", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 374, + 379 + ] + }, + { + "chunk_id": "chunk_260889fa", + "text": "In this case, the misaligned loads and stores can be handled in hardware, or via an invisible trap into the execution environment implementation, or possibly a combination of hardware and invisible trap depending on address.", + "source_file": "src/rv32.adoc", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Load and Store Instructions", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 374, + 379 + ] + }, + { + "chunk_id": "chunk_55916c7b", + "text": "An EEI may not guarantee misaligned loads and stores are handled invisibly.", + "source_file": "src/rv32.adoc", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Load and Store Instructions", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 381, + 394 + ] + }, + { + "chunk_id": "chunk_ae5fb4ba", + "text": "In this case, loads and stores that are not naturally aligned may either complete execution successfully or raise an exception.", + "source_file": "src/rv32.adoc", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Load and Store Instructions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 381, + 394 + ] + }, + { + "chunk_id": "chunk_e1beb254", + "text": "The exception raised can be either an address-misaligned exception or an access-fault exception.", + "source_file": "src/rv32.adoc", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Load and Store Instructions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 381, + 394 + ] + }, + { + "chunk_id": "chunk_6cd82589", + "text": "When an EEI does not guarantee misaligned loads and stores are handled invisibly, the EEI must define if exceptions caused by address misalignment result in a contained trap (allowing software running inside the execution environment to handle the trap) or a fatal trap (terminating execution).", + "source_file": "src/rv32.adoc", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Load and Store Instructions", + "confidence": "very_high", + "parameter_class": "SW_rule", + "parameter_type": "binary", + "line_range": [ + 381, + 394 + ] + }, + { + "chunk_id": "chunk_37e765b8", + "text": "Any combination of device input (I), device output (O), memory reads \\(R), and memory writes (W) may be ordered with respect to any combination of the same.", + "source_file": "src/rv32.adoc", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Memory Ordering Instructions", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 410, + 418 + ] + }, + { + "chunk_id": "chunk_aaf24c03", + "text": "The EEI will define what I/O operations are possible, and in particular, which memory addresses when accessed by load and store instructions will be treated and ordered as device input and device output operations respectively rather than memory reads and writes.", + "source_file": "src/rv32.adoc", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Memory Ordering Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 425, + 433 + ] + }, + { + "chunk_id": "chunk_e40002b0", + "text": "[float=\"center\",align=\"center\",cols=\"^1,^1,<3\",options=\"header\"] .Fence mode encoding | |fm field |Mnemonic suffix|Meaning |0000 |none |Normal Fence |1000 |.TSO |With `FENCE RW,RW`: exclude write-to-read ordering; otherwise: Reserved for future use. |other|other |Reserved for future use. |", + "source_file": "src/rv32.adoc", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Memory Ordering Instructions", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 435, + 443 + ] + }, + { + "chunk_id": "chunk_0e740e7a", + "text": "The FENCE mode field fm defines the semantics of the FENCE instruction. A `FENCE` (with fm=`0000`) orders all memory operations in its predecessor set before all memory operations in its successor set.", + "source_file": "src/rv32.adoc", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Memory Ordering Instructions", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 445, + 448 + ] + }, + { + "chunk_id": "chunk_1a58f3c1", + "text": "A `FENCE.TSO` instruction is encoded as a FENCE instruction with fm=`1000`, predecessor=`RW`, and successor=`RW`. `FENCE.TSO` orders all load operations in its predecessor set before all memory operations in its successor set, and all store operations in its predecessor set before all store operations in its successor set.", + "source_file": "src/rv32.adoc", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Memory Ordering Instructions", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 450, + 457 + ] + }, + { + "chunk_id": "chunk_6b260b03", + "text": "The unused fields in the FENCE instructions--rs1 and rd--are reserved for finer-grain fences in future extensions.", + "source_file": "src/rv32.adoc", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Memory Ordering Instructions", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 459, + 467 + ] + }, + { + "chunk_id": "chunk_6d645c2d", + "text": "For forward compatibility, base implementations shall ignore these fields, and standard software shall zero these fields.", + "source_file": "src/rv32.adoc", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Memory Ordering Instructions", + "confidence": "very_high", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 459, + 467 + ] + }, + { + "chunk_id": "chunk_ed1e2d3c", + "text": "Base implementations shall treat all such reserved configurations as `FENCE` instructions (with fm=`0000`), and standard software shall use only non-reserved configurations.", + "source_file": "src/rv32.adoc", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Memory Ordering Instructions", + "confidence": "very_high", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 459, + 467 + ] + }, + { + "chunk_id": "chunk_bdd6d9f3", + "text": "`SYSTEM` instructions are used to access system functionality that might require privileged access and are encoded using the I-type instruction format.", + "source_file": "src/rv32.adoc", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Environment Call and Breakpoints", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 472, + 478 + ] + }, + { + "chunk_id": "chunk_9a736d87", + "text": "These can be divided into two main classes: those that atomically read-modify-write control and status registers (CSRs), and all other potentially privileged instructions. CSR instructions are described in , and the base unprivileged instructions are described in the following section.", + "source_file": "src/rv32.adoc", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Environment Call and Breakpoints", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 472, + 478 + ] + }, + { + "chunk_id": "chunk_761f8a99", + "text": "These two instructions cause a precise requested trap to the supporting execution environment.", + "source_file": "src/rv32.adoc", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Environment Call and Breakpoints", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 484, + 485 + ] + }, + { + "chunk_id": "chunk_eb9fbe58", + "text": "Implementations are always allowed to ignore the encoded hints.", + "source_file": "src/rv32.adoc", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > HINT Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 500, + 505 + ] + }, + { + "chunk_id": "chunk_e33f8e72", + "text": "Most RV32I HINTs are encoded as integer computational instructions with rd=`x0`.", + "source_file": "src/rv32.adoc", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > HINT Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 507, + 509 + ] + }, + { + "chunk_id": "chunk_c3d6c8d0", + "text": "The other RV32I HINTs are encoded as FENCE instructions with a null predecessor or successor set and with fm=0.", + "source_file": "src/rv32.adoc", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > HINT Instructions", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 507, + 509 + ] + } + ] + }, + { + "file": "src/rv32e.adoc", + "chunks": [ + { + "chunk_id": "chunk_42c80d6c", + "text": "This chapter only outlines the differences between RV32E/RV64E and RV32I/RV64I, and so should be read after and .", + "source_file": "src/rv32e.adoc", + "section": "Preamble > RV32E and RV64E Base Integer Instruction Sets, Version 2.0", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 3, + 9 + ] + } + ] + }, + { + "file": "src/rv64.adoc", + "chunks": [ + { + "chunk_id": "chunk_705a2320", + "text": "This chapter presents only the differences with RV32I, so should be read in conjunction with the earlier chapter.", + "source_file": "src/rv64.adoc", + "section": "Preamble > RV64I Base Integer Instruction Set, Version 2.1", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 3, + 6 + ] + }, + { + "chunk_id": "chunk_93b43291", + "text": "RV64I widens the integer registers and supported user address space to 64 bits (XLEN=64 in ).", + "source_file": "src/rv64.adoc", + "section": "Preamble > RV64I Base Integer Instruction Set, Version 2.1 > Register State", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 10, + 11 + ] + }, + { + "chunk_id": "chunk_f3a36c8b", + "text": "Additional instruction variants are provided to manipulate 32-bit values in RV64I, indicated by a 'W' suffix to the opcode.", + "source_file": "src/rv64.adoc", + "section": "Preamble > RV64I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 15, + 20 + ] + }, + { + "chunk_id": "chunk_6b73e97b", + "text": "ADDIW is an RV64I instruction that adds the sign-extended 12-bit immediate to register rs1 and produces the proper sign extension of a 32-bit result in rd.", + "source_file": "src/rv64.adoc", + "section": "Preamble > RV64I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Immediate Instructions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 31, + 36 + ] + }, + { + "chunk_id": "chunk_3168746c", + "text": "Shifts by a constant are encoded as a specialization of the I-type format using the same instruction opcode as RV32I.", + "source_file": "src/rv64.adoc", + "section": "Preamble > RV64I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Immediate Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 42, + 53 + ] + }, + { + "chunk_id": "chunk_8f71ba9f", + "text": "The operand to be shifted is in rs1, and the shift amount is encoded in the lower 6 bits of the I-immediate field for RV64I.", + "source_file": "src/rv64.adoc", + "section": "Preamble > RV64I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Immediate Instructions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 42, + 53 + ] + }, + { + "chunk_id": "chunk_404f8bd5", + "text": "The right-shift type is encoded in bit 30. SLLI is a logical left shift (zeros are shifted into the lower bits); SRLI is a logical right shift (zeros are shifted into the upper bits); and SRAI is an arithmetic right shift (the original sign bit is copied into the vacated upper bits).", + "source_file": "src/rv64.adoc", + "section": "Preamble > RV64I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Immediate Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 42, + 53 + ] + }, + { + "chunk_id": "chunk_dbcbdead", + "text": "LUI (load upper immediate) uses the same opcode as RV32I. LUI places the 32-bit U-immediate into register rd, filling in the lowest 12 bits with zeros.", + "source_file": "src/rv64.adoc", + "section": "Preamble > RV64I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Immediate Instructions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 67, + 71 + ] + }, + { + "chunk_id": "chunk_744d2c07", + "text": "The 32-bit result is sign-extended to 64 bits.", + "source_file": "src/rv64.adoc", + "section": "Preamble > RV64I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Immediate Instructions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 67, + 71 + ] + }, + { + "chunk_id": "chunk_f6f4fcf3", + "text": "AUIPC (add upper immediate to `pc`) uses the same opcode as RV32I. AUIPC is used to build `pc`-relative addresses and uses the U-type format. AUIPC forms a 32-bit offset from the U-immediate, filling in the lowest 12 bits with zeros, sign-extends the result to 64 bits, adds it to the address of the AUIPC instruction, then places the result in register rd.", + "source_file": "src/rv64.adoc", + "section": "Preamble > RV64I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Immediate Instructions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 73, + 77 + ] + }, + { + "chunk_id": "chunk_1d4e289c", + "text": "ADDW and SUBW are RV64I-only instructions that are defined analogously to ADD and SUB but operate on 32-bit values and produce signed 32-bit results.", + "source_file": "src/rv64.adoc", + "section": "Preamble > RV64I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Register Operations", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 86, + 91 + ] + }, + { + "chunk_id": "chunk_fcd1d6d8", + "text": "SLL, SRL, and SRA perform logical left, logical right, and arithmetic right shifts on the value in register rs1 by the shift amount held in register rs2.", + "source_file": "src/rv64.adoc", + "section": "Preamble > RV64I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Register Operations", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 93, + 96 + ] + }, + { + "chunk_id": "chunk_257157c9", + "text": "In RV64I, only the low 6 bits of rs2 are considered for the shift amount.", + "source_file": "src/rv64.adoc", + "section": "Preamble > RV64I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Register Operations", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 93, + 96 + ] + }, + { + "chunk_id": "chunk_345ea0be", + "text": "SLLW, SRLW, and SRAW are RV64I-only instructions that are analogously defined but operate on 32-bit values and sign-extend their 32-bit results to 64 bits.", + "source_file": "src/rv64.adoc", + "section": "Preamble > RV64I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Register Operations", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 98, + 103 + ] + }, + { + "chunk_id": "chunk_e51f954c", + "text": "The shift amount is given by rs2[4:0].", + "source_file": "src/rv64.adoc", + "section": "Preamble > RV64I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Register Operations", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 98, + 103 + ] + }, + { + "chunk_id": "chunk_e9dca960", + "text": "RV64I extends the address space to 64 bits.", + "source_file": "src/rv64.adoc", + "section": "Preamble > RV64I Base Integer Instruction Set, Version 2.1 > Load and Store Instructions", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 107, + 108 + ] + }, + { + "chunk_id": "chunk_078852ca", + "text": "The LD instruction loads a 64-bit value from memory into register rd for RV64I.", + "source_file": "src/rv64.adoc", + "section": "Preamble > RV64I Base Integer Instruction Set, Version 2.1 > Load and Store Instructions", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 114, + 116 + ] + }, + { + "chunk_id": "chunk_f9ee47d5", + "text": "The LW instruction loads a 32-bit value from memory and sign-extends this to 64 bits before storing it in register rd for RV64I.", + "source_file": "src/rv64.adoc", + "section": "Preamble > RV64I Base Integer Instruction Set, Version 2.1 > Load and Store Instructions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 118, + 124 + ] + }, + { + "chunk_id": "chunk_aa3d0f8f", + "text": "The LWU instruction, on the other hand, zero-extends the 32-bit value from memory for RV64I. LH and LHU are defined analogously for 16-bit values, as are LB and LBU for 8-bit values.", + "source_file": "src/rv64.adoc", + "section": "Preamble > RV64I Base Integer Instruction Set, Version 2.1 > Load and Store Instructions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 118, + 124 + ] + }, + { + "chunk_id": "chunk_6fb41617", + "text": "The SD, SW, SH, and SB instructions store 64-bit, 32-bit, 16-bit, and 8-bit values from the low bits of register rs2 to memory respectively.", + "source_file": "src/rv64.adoc", + "section": "Preamble > RV64I Base Integer Instruction Set, Version 2.1 > Load and Store Instructions", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 118, + 124 + ] + } + ] + }, + { + "file": "src/scalar-crypto.adoc", + "chunks": [ + { + "chunk_id": "chunk_835623bc", + "text": "Where possible, we have written this specification to be understandable by all, though we recognise that the motivations and references to algorithms or other specifications and standards may be unfamiliar to those who are not domain experts.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Introduction > Intended Audience", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 25, + 30 + ] + }, + { + "chunk_id": "chunk_715aa5be", + "text": "We hope this aids people's understanding of which aspects of the specification are particularly relevant to them, and which they may (safely!) ignore or pass to a colleague.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Introduction > Intended Audience", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 32, + 39 + ] + }, + { + "chunk_id": "chunk_cf9fe0f9", + "text": "They should understand fairly obviously the motivations for the instructions we include, and be familiar with most of the algorithms and outside standards to which we refer.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Introduction > Intended Audience", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 41, + 51 + ] + }, + { + "chunk_id": "chunk_bb3f5c91", + "text": "In particular, they should be aware of the literature around efficiently implementing AES and SM4 SBoxes in hardware.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Introduction > Intended Audience", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 60, + 67 + ] + }, + { + "chunk_id": "chunk_1b532d9a", + "text": "It is anticipated that the NIST Lightweight Cryptography contest and the NIST Post-Quantum Cryptography contest may be dealt with this way, depending on timescales.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Introduction > Policies", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 134, + 143 + ] + }, + { + "chunk_id": "chunk_1dad1470", + "text": "The standard will not try to anticipate new useful low-level operations which may be useful as building blocks for future cryptographic constructs.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Introduction > Policies", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 145, + 151 + ] + }, + { + "chunk_id": "chunk_9b188cc8", + "text": "Regarding side-channel countermeasures: Where relevant, proposed instructions must aim to remove the possibility of any timing side-channels.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Introduction > Policies", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 153, + 160 + ] + }, + { + "chunk_id": "chunk_f50080cd", + "text": "The entropy source extension defines the `seed` CSR at address `0x015`.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Extensions Overview > `Zkr` - Entropy Source Extension", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 331, + 334 + ] + }, + { + "chunk_id": "chunk_68a2f271", + "text": "A core which implements `Zkn` must implement all of the above extensions.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Extensions Overview > `Zkn` - NIST Algorithm Suite", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 358, + 359 + ] + }, + { + "chunk_id": "chunk_c2899614", + "text": "A core which implements `Zks` must implement all of the above extensions.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Extensions Overview > `Zks` - ShangMi Algorithm Suite", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 378, + 379 + ] + }, + { + "chunk_id": "chunk_b9e43f9d", + "text": "A core which implements `Zk` must implement all of the above extensions.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Extensions Overview > `Zk` - Standard scalar cryptography extension", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 396, + 397 + ] + }, + { + "chunk_id": "chunk_92071d43", + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated on.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes32dsi", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 437, + 442 + ] + }, + { + "chunk_id": "chunk_80254b05", + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated on.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes32dsmi", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 501, + 506 + ] + }, + { + "chunk_id": "chunk_05b04f05", + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated on.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes32esi", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 566, + 571 + ] + }, + { + "chunk_id": "chunk_b055d155", + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated on.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes32esmi", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 630, + 635 + ] + }, + { + "chunk_id": "chunk_d19e8377", + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated on.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64ds", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 695, + 700 + ] + }, + { + "chunk_id": "chunk_71a82971", + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated on.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64dsm", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 771, + 776 + ] + }, + { + "chunk_id": "chunk_5e278710", + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated on.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64es", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 848, + 853 + ] + }, + { + "chunk_id": "chunk_56d7c71d", + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated on.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64esm", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 924, + 929 + ] + }, + { + "chunk_id": "chunk_28f0a134", + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated on.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64im", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1002, + 1010 + ] + }, + { + "chunk_id": "chunk_a1b9c042", + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated on.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64ks1i", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1070, + 1076 + ] + }, + { + "chunk_id": "chunk_9647158e", + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated on.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64ks2", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1145, + 1149 + ] + }, + { + "chunk_id": "chunk_076b266c", + "text": "foreach (i from 0 to (xlen - 1) by 1) { output = if ((rs2val >> i) & 1) then output ^ (rs1val << i); else output; }", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > clmul", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1315, + 1319 + ] + }, + { + "chunk_id": "chunk_022f233d", + "text": "foreach (i from 1 to xlen by 1) { output = if ((rs2val >> i) & 1) then output ^ (rs1val >> (xlen - i)); else output; }", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > clmulh", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1374, + 1378 + ] + }, + { + "chunk_id": "chunk_d8cd33b2", + "text": "Operation:: [source,sail] -- let shamt = if xlen 32 then X(rs2)[4..0] else X(rs2)[5..0]; let result = (X(rs1) (xlen - shamt));", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > rol", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1707, + 1713 + ] + }, + { + "chunk_id": "chunk_d74b96a4", + "text": "The resulting word value is sign-extended by copying bit 31 to all of the more-significant bits.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > rolw", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 1758, + 1760 + ] + }, + { + "chunk_id": "chunk_7e7a5bc3", + "text": "Operation:: [source,sail] -- let shamt = if xlen 32 then X(rs2)[4..0] else X(rs2)[5..0]; let result = (X(rs1) >> shamt) | (X(rs1) << (xlen - shamt));", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > ror", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1814, + 1820 + ] + }, + { + "chunk_id": "chunk_c3b2cbc9", + "text": "Operation:: [source,sail] -- let shamt = if xlen 32 then shamt[4..0] else shamt[5..0]; let result = (X(rs1) >> shamt) | (X(rs1) << (xlen - shamt));", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > rori", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1882, + 1888 + ] + }, + { + "chunk_id": "chunk_e615fbc6", + "text": "The resulting word value is sign-extended by copying bit 31 to all of the more-significant bits.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > roriw", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 1933, + 1938 + ] + }, + { + "chunk_id": "chunk_ccf07a80", + "text": "The resultant word is sign-extended by copying bit 31 to all of the more-significant bits.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > rorw", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 1989, + 1991 + ] + }, + { + "chunk_id": "chunk_355a7b7f", + "text": "For RV64, the low `32` bits of the source register are operated on, and the result sign extended to `XLEN` bits.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha256sig0", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2045, + 2054 + ] + }, + { + "chunk_id": "chunk_4df9c70a", + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated on.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha256sig0", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 2045, + 2054 + ] + }, + { + "chunk_id": "chunk_1e1e5800", + "text": "For RV64, the low `32` bits of the source register are operated on, and the result sign extended to `XLEN` bits.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha256sig1", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2113, + 2122 + ] + }, + { + "chunk_id": "chunk_d38aa277", + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated on.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha256sig1", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 2113, + 2122 + ] + }, + { + "chunk_id": "chunk_959d20f8", + "text": "For RV64, the low `32` bits of the source register are operated on, and the result sign extended to `XLEN` bits.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha256sum0", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2181, + 2190 + ] + }, + { + "chunk_id": "chunk_d131292a", + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated on.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha256sum0", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 2181, + 2190 + ] + }, + { + "chunk_id": "chunk_0dcd8f3d", + "text": "For RV64, the low `32` bits of the source register are operated on, and the result sign extended to `XLEN` bits.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha256sum1", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2249, + 2258 + ] + }, + { + "chunk_id": "chunk_a106de6a", + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated on.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha256sum1", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 2249, + 2258 + ] + }, + { + "chunk_id": "chunk_d2accadf", + "text": "The transform is a 64-bit to 64-bit function, so the input and output are each represented by two 32-bit registers.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig0h", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 2317, + 2324 + ] + }, + { + "chunk_id": "chunk_6239e14b", + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated on.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig0h", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 2317, + 2324 + ] + }, + { + "chunk_id": "chunk_0847b8dc", + "text": "[NOTE] .Note to software developers The entire Sigma0 transform for SHA2-512 may be computed on RV32 using the following instruction sequence:", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig0h", + "confidence": "medium", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 2326, + 2330 + ] + }, + { + "chunk_id": "chunk_909aad4b", + "text": "The transform is a 64-bit to 64-bit function, so the input and output are each represented by two 32-bit registers.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig0l", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 2393, + 2400 + ] + }, + { + "chunk_id": "chunk_2fa66283", + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated on.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig0l", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 2393, + 2400 + ] + }, + { + "chunk_id": "chunk_5d2dfd93", + "text": "[NOTE] .Note to software developers The entire Sigma0 transform for SHA2-512 may be computed on RV32 using the following instruction sequence:", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig0l", + "confidence": "medium", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 2402, + 2406 + ] + }, + { + "chunk_id": "chunk_38f6c313", + "text": "The transform is a 64-bit to 64-bit function, so the input and output are each represented by two 32-bit registers.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig1h", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 2469, + 2476 + ] + }, + { + "chunk_id": "chunk_cd32f903", + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated on.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig1h", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 2469, + 2476 + ] + }, + { + "chunk_id": "chunk_51a6b367", + "text": "[NOTE] .Note to software developers The entire Sigma1 transform for SHA2-512 may be computed on RV32 using the following instruction sequence:", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig1h", + "confidence": "medium", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 2478, + 2482 + ] + }, + { + "chunk_id": "chunk_1343e810", + "text": "The transform is a 64-bit to 64-bit function, so the input and output are each represented by two 32-bit registers.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig1l", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 2545, + 2552 + ] + }, + { + "chunk_id": "chunk_35a1679a", + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated on.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig1l", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 2545, + 2552 + ] + }, + { + "chunk_id": "chunk_fa494a2e", + "text": "[NOTE] .Note to software developers The entire Sigma1 transform for SHA2-512 may be computed on RV32 using the following instruction sequence:", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig1l", + "confidence": "medium", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 2554, + 2558 + ] + }, + { + "chunk_id": "chunk_8428bd12", + "text": "The transform is a 64-bit to 64-bit function, so the input and output is represented by two 32-bit registers.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sum0r", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 2621, + 2627 + ] + }, + { + "chunk_id": "chunk_8697ed66", + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated on.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sum0r", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 2621, + 2627 + ] + }, + { + "chunk_id": "chunk_1507bd07", + "text": "[NOTE] .Note to software developers The entire Sum0 transform for SHA2-512 may be computed on RV32 using the following instruction sequence:", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sum0r", + "confidence": "medium", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 2629, + 2633 + ] + }, + { + "chunk_id": "chunk_b755681f", + "text": "The transform is a 64-bit to 64-bit function, so the input and output is represented by two 32-bit registers.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sum1r", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 2697, + 2703 + ] + }, + { + "chunk_id": "chunk_211b5593", + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated on.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sum1r", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 2697, + 2703 + ] + }, + { + "chunk_id": "chunk_23f24493", + "text": "[NOTE] .Note to software developers The entire Sum1 transform for SHA2-512 may be computed on RV32 using the following instruction sequence:", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sum1r", + "confidence": "medium", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 2705, + 2709 + ] + }, + { + "chunk_id": "chunk_f92dace2", + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated on.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig0", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 2773, + 2778 + ] + }, + { + "chunk_id": "chunk_c5115b0d", + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated on.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig1", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 2835, + 2840 + ] + }, + { + "chunk_id": "chunk_2c264432", + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated on.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sum0", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 2897, + 2902 + ] + }, + { + "chunk_id": "chunk_8b569b24", + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated on.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sum1", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 2959, + 2964 + ] + }, + { + "chunk_id": "chunk_35100e6d", + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated on.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sm3p0", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 3021, + 3025 + ] + }, + { + "chunk_id": "chunk_82228d2d", + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated on.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sm3p1", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 3082, + 3086 + ] + }, + { + "chunk_id": "chunk_6f672564", + "text": "On RV64, the 32-bit result is sign extended to XLEN bits.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sm4ed", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 3143, + 3152 + ] + }, + { + "chunk_id": "chunk_0d17d254", + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated on.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sm4ed", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 3143, + 3152 + ] + }, + { + "chunk_id": "chunk_4bad67d6", + "text": "On RV64, the 32-bit result is sign extended to XLEN bits.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sm4ks", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 3214, + 3223 + ] + }, + { + "chunk_id": "chunk_d3755de8", + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated on.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sm4ks", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 3214, + 3223 + ] + }, + { + "chunk_id": "chunk_218c2c93", + "text": "The rs1 register contains a vector of XLEN/8 8-bit elements.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > xperm8", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 3392, + 3397 + ] + }, + { + "chunk_id": "chunk_84db91b7", + "text": "The rs2 register contains a vector of XLEN/8 8-bit indexes.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > xperm8", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 3392, + 3397 + ] + }, + { + "chunk_id": "chunk_f66271b1", + "text": "The rs1 register contains a vector of XLEN/4 4-bit elements.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > xperm4", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 3454, + 3459 + ] + }, + { + "chunk_id": "chunk_d8a64be2", + "text": "The rs2 register contains a vector of XLEN/4 4-bit indexes.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > xperm4", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 3454, + 3459 + ] + }, + { + "chunk_id": "chunk_71134e7d", + "text": "The `seed` CSR provides an interface to a NIST SP 800-90B cite:[TuBaKe:18] or BSI AIS-31 cite:[KiSc11] compliant physical Entropy Source (ES).", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 3558, + 3559 + ] + }, + { + "chunk_id": "chunk_2b864b44", + "text": "`seed` is an unprivileged CSR located at address `0x015`.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 3576, + 3577 + ] + }, + { + "chunk_id": "chunk_255cd5cc", + "text": "The 32-bit contents of `seed` are as follows:", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 3576, + 3577 + ] + }, + { + "chunk_id": "chunk_0d0b4d16", + "text": "|`31:30` |`OPST` |Status: `BIST` (00), `WAIT` (01), `ES16` (10), `DEAD` (11).", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 3583, + 3584 + ] + }, + { + "chunk_id": "chunk_04eb520f", + "text": "|`29:24` |reserved |For future use by the RISC-V specification.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 3586, + 3586 + ] + }, + { + "chunk_id": "chunk_1f09fd42", + "text": "|`23:16` |custom |Designated for custom and experimental use.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 3588, + 3588 + ] + }, + { + "chunk_id": "chunk_381c5b55", + "text": "|`15: 0` |`entropy` |16 bits of randomness, only when `OPST=ES16`. |", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 3590, + 3591 + ] + }, + { + "chunk_id": "chunk_58410c01", + "text": "Attempts to access the `seed` CSR using a read-only CSR-access instruction (`CSRRS`/`CSRRC` with rs1=`x0` or `CSRRSI`/`CSRRCI` with uimm=0) raise an illegal-instruction exception; any other CSR-access instruction may be used to access `seed`.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 3593, + 3598 + ] + }, + { + "chunk_id": "chunk_a9cc350a", + "text": "The write value (in `rs1` or `uimm`) must be ignored by implementations.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 3593, + 3598 + ] + }, + { + "chunk_id": "chunk_ddceffaf", + "text": "The purpose of the write is to signal polling and flushing.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 3593, + 3598 + ] + }, + { + "chunk_id": "chunk_d7c8c3d1", + "text": "Software normally uses the instruction `csrrw rd, seed, x0` to read the `seed` CSR.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 3600, + 3601 + ] + }, + { + "chunk_id": "chunk_aa84b942", + "text": "The `seed` CSR is also access controlled by execution mode, and attempted read or write access will raise an illegal-instruction exception outside M mode unless access is explicitly granted.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 3615, + 3618 + ] + }, + { + "chunk_id": "chunk_46defd3e", + "text": "The status bits `seed[31:30]` = `OPST` may be `ES16` (10), indicating successful polling, or one of three entropy polling failure statuses `BIST` (00), `WAIT` (01), or `DEAD` (11), discussed below.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 3620, + 3622 + ] + }, + { + "chunk_id": "chunk_518a5702", + "text": "Each returned `seed[15:0]` = `entropy` value represents unique randomness when `OPST`=`ES16` (`seed[31:30]` = `10`), even if its numerical value is the same as that of a previously polled `entropy` value.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 3624, + 3629 + ] + }, + { + "chunk_id": "chunk_cf0d0c43", + "text": "The implementation requirements of `entropy` bits are defined in .", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 3624, + 3629 + ] + }, + { + "chunk_id": "chunk_80484094", + "text": "When `OPST` is not `ES16`, `entropy` must be set to 0.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 3624, + 3629 + ] + }, + { + "chunk_id": "chunk_1c68bfee", + "text": "An implementation may safely set reserved and custom bits to zeros.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 3624, + 3629 + ] + }, + { + "chunk_id": "chunk_0276a697", + "text": "For security reasons, the interface guarantees that secret `entropy` words are not made available multiple times.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 3631, + 3636 + ] + }, + { + "chunk_id": "chunk_8c53a16b", + "text": "Hence polling (reading) must also have the side effect of clearing (wipe-on-read) the `entropy` contents and changing the state to `WAIT` (unless there is `entropy` immediately available for `ES16`).", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 3631, + 3636 + ] + }, + { + "chunk_id": "chunk_0d904830", + "text": "Other states (`BIST`, `WAIT`, and `DEAD`) may be unaffected by polling.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 3631, + 3636 + ] + }, + { + "chunk_id": "chunk_07f285f6", + "text": "`00` - `BIST` indicates that Built-In Self-Test \"on-demand\" (BIST) testing is being performed.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 3640, + 3646 + ] + }, + { + "chunk_id": "chunk_570967d3", + "text": "If `OPST` returns temporarily to `BIST` from any other state, this signals a non-fatal self-test alarm, which is non-actionable, apart from being logged.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 3640, + 3646 + ] + }, + { + "chunk_id": "chunk_ee9f77b9", + "text": "Such a `BIST` alarm must be latched until polled at least once to enable software to record its occurrence.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR", + "confidence": "very_high", + "parameter_class": "SW_rule", + "parameter_type": "range", + "line_range": [ + 3640, + 3646 + ] + }, + { + "chunk_id": "chunk_48b386c6", + "text": "`01` - `WAIT` means that a sufficient amount of entropy is not yet available.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 3648, + 3651 + ] + }, + { + "chunk_id": "chunk_dd30c8e8", + "text": "This is not an error condition and may (in fact) be more frequent than ES16 since physical entropy sources often have low bandwidth.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 3648, + 3651 + ] + }, + { + "chunk_id": "chunk_b9b15a68", + "text": "`11` - `DEAD` is an unrecoverable self-test error.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 3658, + 3663 + ] + }, + { + "chunk_id": "chunk_bbe877cf", + "text": "This may indicate a hardware fault, a security issue, or (extremely rarely) a type-1 statistical false positive in the continuous testing procedures.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 3658, + 3663 + ] + }, + { + "chunk_id": "chunk_5da81d74", + "text": "In case of a fatal failure, an immediate lockdown may also be an appropriate response in dedicated security devices.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 3658, + 3663 + ] + }, + { + "chunk_id": "chunk_e4b6b488", + "text": "The main requirement is that 2-to-1 cryptographic post-processing in 256-bit input blocks will yield 128-bit \"full entropy\" output blocks.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 3682, + 3689 + ] + }, + { + "chunk_id": "chunk_77f3c373", + "text": "Entropy source users may make this conservative assumption but are not prohibited from using more than twice the number of seed bits relative to the desired resulting entropy.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 3682, + 3689 + ] + }, + { + "chunk_id": "chunk_e19bb927", + "text": "An implementation of the entropy source should meet at least one of the following requirements sets in order to be considered a secure and safe design:", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 3691, + 3693 + ] + }, + { + "chunk_id": "chunk_31436a65", + "text": "The source must also meet the NIST 800-90B min-entropy rate 192/256 = 0.75.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 3699, + 3702 + ] + }, + { + "chunk_id": "chunk_e100a35e", + "text": "It must have at least a 256-bit (Post-Quantum Category 5) internal security level.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 3704, + 3706 + ] + }, + { + "chunk_id": "chunk_9b8e2426", + "text": "All implementations must signal initialization, test mode, and health alarms as required by respective standards.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 3708, + 3711 + ] + }, + { + "chunk_id": "chunk_6e36a6a2", + "text": "This may require the implementer to add non-standard (custom) test interfaces in a secure and safe manner, an example of which is described in", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 3708, + 3711 + ] + }, + { + "chunk_id": "chunk_d3cf7c26", + "text": "All NIST SP 800-90B cite:[TuBaKe:18] required components and health test mechanisms must be implemented.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements > NIST SP 800-90B / FIPS 140-3 Requirements", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 3717, + 3718 + ] + }, + { + "chunk_id": "chunk_cd11cdb1", + "text": "Instead, the implication is that every 256-bit sequence should have min-entropy of at least 128+64 = 192 bits, as discussed in SP 800-90C cite:[BaKeMc:25]; the likelihood of successfully \"guessing\" an individual 256-bit output sequence should not be higher than 2^-192^ even with (almost) unconstrained amount of entropy source data and computational power.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements > NIST SP 800-90B / FIPS 140-3 Requirements", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 3727, + 3733 + ] + }, + { + "chunk_id": "chunk_52c7ef06", + "text": "Rather than attempting to define all the mathematical and architectural properties that the entropy source must satisfy, we define that the physical entropy source be strong and robust enough to pass the equivalent of NIST SP 800-90 evaluation and certification for full entropy when conditioned cryptographically in ratio 2:1 with 128-bit output blocks.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements > NIST SP 800-90B / FIPS 140-3 Requirements", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 3735, + 3739 + ] + }, + { + "chunk_id": "chunk_b931694f", + "text": "Even though the requirement is defined in terms of 128-bit full entropy blocks, we recommend 256-bit security.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements > NIST SP 800-90B / FIPS 140-3 Requirements", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 3741, + 3743 + ] + }, + { + "chunk_id": "chunk_aed9c8c6", + "text": "This can be accomplished by using at least 512 `entropy` bits to initialize a DRBG that has 256-bit security.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements > NIST SP 800-90B / FIPS 140-3 Requirements", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 3741, + 3743 + ] + }, + { + "chunk_id": "chunk_83e6df61", + "text": "For alternative Common Criteria certification (or self-certification), AIS 31 PTG.2 class cite:[KiSc11] (Sect. 4.3.) required hardware components and mechanisms must be implemented.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements > BSI AIS-31 PTG.2 / Common Criteria Requirements", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 3748, + 3755 + ] + }, + { + "chunk_id": "chunk_564cc192", + "text": "These two metrics should not be equated or confused with each other.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements > BSI AIS-31 PTG.2 / Common Criteria Requirements", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 3748, + 3755 + ] + }, + { + "chunk_id": "chunk_d75b4f88", + "text": "It is defined for the benefit of the RISC-V security ecosystem so that virtual systems may have a consistent level of security.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements > Virtual Sources: Security Requirement", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 3761, + 3763 + ] + }, + { + "chunk_id": "chunk_3586d4be", + "text": "Despite limited trust, implementers should try to guarantee that even such environments have sufficient entropy available for secure cryptographic operations.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements > Virtual Sources: Security Requirement", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 3765, + 3770 + ] + }, + { + "chunk_id": "chunk_6a31d449", + "text": "A virtual source traps access to the `seed` CSR, emulates it, or otherwise implements it, possibly without direct access to a physical entropy source.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements > Virtual Sources: Security Requirement", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 3772, + 3777 + ] + }, + { + "chunk_id": "chunk_16a0bf00", + "text": "The output can be cryptographically secure pseudorandomness instead of real entropy, but must have at least 256-bit security, as defined below. A virtual source is intended especially for guest operating systems, sandboxes, emulators, and similar use cases.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements > Virtual Sources: Security Requirement", + "confidence": "very_high", + "parameter_class": "SW_rule", + "parameter_type": "range", + "line_range": [ + 3772, + 3777 + ] + }, + { + "chunk_id": "chunk_c18d934f", + "text": "Any implementation of the `seed` CSR that limits the security strength shall not reduce it to less than 256 bits.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements > Virtual Sources: Security Requirement", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 3787, + 3789 + ] + }, + { + "chunk_id": "chunk_61b3ff74", + "text": "If the security level is under 256 bits, then the interface must not be available.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements > Virtual Sources: Security Requirement", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 3787, + 3789 + ] + }, + { + "chunk_id": "chunk_bf037a77", + "text": "It should fail (`DEAD`) if the host DRBG or entropy source fails and there is insufficient seeding material for the host DRBG.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements > Virtual Sources: Security Requirement", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 3791, + 3793 + ] + }, + { + "chunk_id": "chunk_974c56f2", + "text": "The Zkr extension adds the `SSEED` and `USEED` fields to the `mseccfg` CSR to control access to the `seed` CSR from U, S, or HS modes (see Privileged ISA specification).", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Access Control to `seed`", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 3799, + 3801 + ] + }, + { + "chunk_id": "chunk_a36b6293", + "text": "Systems should implement carefully considered access control policies from lower privilege modes to physical entropy sources.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Access Control to `seed`", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 3803, + 3811 + ] + }, + { + "chunk_id": "chunk_9eec2530", + "text": "The system can trap attempted access to `seed` and feed a less privileged client virtual entropy source data () instead of invoking an SP 800-90B () or PTG.2 () physical entropy source.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Access Control to `seed`", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 3803, + 3811 + ] + }, + { + "chunk_id": "chunk_80d4b3d5", + "text": "Implementations may implement `mseccfg` such that `[s,u]seed` is a read-only constant value `0`.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Access Control to `seed`", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 3813, + 3816 + ] + }, + { + "chunk_id": "chunk_60a541a2", + "text": "Software may discover if access to the `seed` CSR can be enabled in U and S mode by writing a `1` to `[s,u]seed` and reading back the result.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Access Control to `seed`", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 3813, + 3816 + ] + }, + { + "chunk_id": "chunk_ee488e55", + "text": "This property is commonly called \"constant-time\" although should not be taken with that literal meaning.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 3822, + 3824 + ] + }, + { + "chunk_id": "chunk_0fa5bd64", + "text": "Zkt does not define a set of instructions available in the core; it just restricts the behaviour of certain instructions if those are implemented.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt > Scope and Goal", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 3841, + 3846 + ] + }, + { + "chunk_id": "chunk_13f08413", + "text": "The stated goal is that OpenSSL, BoringSSL (Android), the Linux Kernel, and similar trusted software will not have directly observable timing side channels when compiled and running on a Zkt-enabled RISC-V target.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt > Scope and Goal", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "binary", + "line_range": [ + 3858, + 3862 + ] + }, + { + "chunk_id": "chunk_64e66675", + "text": "Vendors do not have to implement all of the list's instructions to be Zkt compliant; however, if they claim to have Zkt and implement any of the listed instructions, it must have data-independent latency.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt > Scope and Goal", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 3864, + 3865 + ] + }, + { + "chunk_id": "chunk_32e5bed5", + "text": "The guiding principle should be that no information about the data being operated on should be leaked based on the execution latency.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt > Scope and Goal", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 3875, + 3879 + ] + }, + { + "chunk_id": "chunk_de86ad76", + "text": "Timing attacks are much more powerful than was realised before the 2010s, which has led to a significant mitigation effort in current cryptographic code-bases. * Cryptography developers use static and dynamic security testing tools to trace the handling of secret information and detect occasions where it influences a branch or is used for a table lookup. * Architectural testing for Zkt can be pragmatic and semi-formal; security by design against basic timing attacks can usually be achieved via conscious implementation (of relevant iterative multi-cycle instructions or instructions composed of micro-ops) in way that avoids data-dependent latency. * Laboratory testing may utilize statistical timing attack leakage analysis techniques such as those described in ISO/IEC 17825 cite:[IS16]. * Binary executables should not contain secrets in the instruction encodings (Kerckhoffs's principle), so instruction timing may leak information about immediates, ordering of input registers, etc.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt > Background", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 3897, + 3924 + ] + }, + { + "chunk_id": "chunk_76e8a993", + "text": "There may be an exception to this in systems where a binary loader modifies the executable for purposes of relocation -- and it is desirable to keep the execution location (PC) secret.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt > Background", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 3897, + 3924 + ] + }, + { + "chunk_id": "chunk_6282c8e8", + "text": "If a secret ends up in address calculation affecting a load or store, that is a violation.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt > Background", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 3897, + 3924 + ] + }, + { + "chunk_id": "chunk_97125d05", + "text": "If a secret affects a branch's condition, that is also a violation. A secret variable location or register becomes a non-secret via specific zeroization/sanitisation or by being declared ciphertext (or otherwise no-longer-secret information).", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt > Background", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 3897, + 3924 + ] + }, + { + "chunk_id": "chunk_d814d69a", + "text": "Rather, every one of these instructions that the core does implement must adhere to the requirements of `Zkt`.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt > Zkt listings", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 3967, + 3973 + ] + }, + { + "chunk_id": "chunk_02d01f83", + "text": "Additionally, `seed` CSR latency should be independent of `ES16` state output `entropy` bits, as that is a sensitive security parameter.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt > Zkt listings > RVK (Scalar Cryptography)", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 4097, + 4100 + ] + }, + { + "chunk_id": "chunk_37b2c135", + "text": "The 32-bit instructions were derived from work in cite:[MJS:LWAES:20] and contributed to the RISC-V cryptography extension.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instruction Rationale > AES Instructions", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 4184, + 4187 + ] + }, + { + "chunk_id": "chunk_ab2da50e", + "text": "The 64-bit instructions were developed collaboratively by task group members on our mailing list.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instruction Rationale > AES Instructions", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 4184, + 4187 + ] + }, + { + "chunk_id": "chunk_e07e3e32", + "text": "Algorithms making use of 32-bit rotations: SHA256, AES (Shift Rows), ChaCha20, SM3. * Algorithms making use of 64-bit rotations: SHA512, SHA3.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instruction Rationale > Bitmanip Instructions for Cryptography > Rotations", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 4256, + 4260 + ] + }, + { + "chunk_id": "chunk_7c2c6b17", + "text": "The `xperm4` instruction operates on nibbles. `GPR[rs1]` contains a vector of `XLEN/4` 4-bit elements. `GPR[rs2]` contains a vector of `XLEN/4` 4-bit indexes.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instruction Rationale > Bitmanip Instructions for Cryptography > Crossbar Permutation Instructions", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 4380, + 4384 + ] + }, + { + "chunk_id": "chunk_e7c90dc8", + "text": "The `xperm8` instruction operates on bytes. `GPR[rs1]` contains a vector of `XLEN/8` 8-bit elements. `GPR[rs2]` contains a vector of `XLEN/8` 8-bit indexes.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instruction Rationale > Bitmanip Instructions for Cryptography > Crossbar Permutation Instructions", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 4386, + 4390 + ] + }, + { + "chunk_id": "chunk_5d139d38", + "text": "Lightweight block ciphers using 4-bit SBoxes include: PRESENT cite:[block:present], Rectangle cite:[block:rectangle], GIFT cite:[block:gift], Twine cite:[block:twine], Skinny, MANTIS cite:[block:skinny], Midori cite:[block:midori].", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instruction Rationale > Bitmanip Instructions for Cryptography > Crossbar Permutation Instructions", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 4401, + 4407 + ] + }, + { + "chunk_id": "chunk_4b3cb13e", + "text": "National ciphers using 8-bit SBoxes include: Camellia cite:[block:camellia] (Japan), Aria cite:[block:aria] (Korea), AES cite:[nist:fips:197] (USA, Belgium), SM4 cite:[gbt:sm4] (China) Kuznyechik (Russia).", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instruction Rationale > Bitmanip Instructions for Cryptography > Crossbar Permutation Instructions", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 4409, + 4414 + ] + }, + { + "chunk_id": "chunk_7de735cf", + "text": "Hence we also discuss non-ISA system features that may be needed for cryptographic standards compliance and security testing.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 4427, + 4430 + ] + }, + { + "chunk_id": "chunk_9d9af863", + "text": "The scope of RISC-V ISA architectural tests are those behaviors that are independent of the physical entropy source details. A smoke test ES module may be helpful in design phase. * *Technical justification for entropy.* This may take the form of a stochastic model or a heuristic argument that explains why the noise source output is from a random, rather than pseudorandom (deterministic) process, and is not easily predictable or externally observable. A complete physical model is not necessary; research literature can be cited.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Checklists for Design and Self-Certification", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 4444, + 4482 + ] + }, + { + "chunk_id": "chunk_f378e173", + "text": "For example, one can show that a good ring oscillator noise derives an amount of physical entropy from local, spontaneously occurring Johnson-Nyquist thermal noise cite:[Sa21], and is therefore not merely \"random-looking\". * *Entropy Source Design Review.* An entropy source is more than a noise source, and must have features such as health tests (), a conditioner (), and a security boundary with clearly defined interfaces.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Checklists for Design and Self-Certification", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 4444, + 4482 + ] + }, + { + "chunk_id": "chunk_dbadf7a4", + "text": "One may tabulate the SHALL statements of SP 800-90B cite:[TuBaKe:18], FIPS 140-3 Implementation Guidance cite:[NICC21], AIS-31 cite:[KiSc11] or other standards being used.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Checklists for Design and Self-Certification", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 4444, + 4482 + ] + }, + { + "chunk_id": "chunk_d9996046", + "text": "Official and non-official checklist tables are available: https://github.com/usnistgov/90B-Shall-Statements * *Experimental Tests.* The raw noise source is subjected to entropy estimation as defined in NIST 800-90B, Section 3 cite:[TuBaKe:18].", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Checklists for Design and Self-Certification", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 4444, + 4482 + ] + }, + { + "chunk_id": "chunk_5e778158", + "text": "For SP 800-90B, NIST has made a min-entropy estimation package freely available: https://github.com/usnistgov/SP800-90BEntropyAssessment * **Resilience.** Above physical engineering steps should consider the operational environment of the device, which may be unexpected or hostile (actively attempting to exploit vulnerabilities in the design).", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Checklists for Design and Self-Certification", + "confidence": "medium", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 4444, + 4482 + ] + }, + { + "chunk_id": "chunk_e30406a5", + "text": "Compared to older (FIPS 140-2) RNG and DRBG modules, an entropy source module may have a relatively small area (just a few thousand NAND2 gate equivalent). CMVP is introducing an \"Entropy Source Validation Scope\" which potentially allows 90B validations to be reused for different (FIPS 140-3) modules.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Checklists for Design and Self-Certification", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 4487, + 4493 + ] + }, + { + "chunk_id": "chunk_b7fc22f7", + "text": "These standards set many of the technical requirements for the RISC-V entropy source design, and we use their terminology if possible.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Standards and Terminology", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 4506, + 4507 + ] + }, + { + "chunk_id": "chunk_a3384916", + "text": "image::esdataflow.svg[align=\"center\",scaledwidth=50%] The `seed` CSR provides an Entropy Source (ES) interface, not a stateful random number generator.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Standards and Terminology", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 4509, + 4517 + ] + }, + { + "chunk_id": "chunk_e9af56e2", + "text": "Since these are directly based on natural phenomena and are subject to environmental conditions (which may be adversarial), they require features that monitor the \"health\" and quality of those sources.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Standards and Terminology > Entropy Source (ES)", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 4523, + 4528 + ] + }, + { + "chunk_id": "chunk_d11701bf", + "text": "Non-cryptographic conditioners and extractors such as von Neumann's \"debiased coin tossing\" cite:[Ne51] are easier to implement efficiently but may reduce entropy content (in individual bits removed) more than cryptographic hashes, which mix the input entropy very efficiently.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Standards and Terminology > Conditioning: Cryptographic and Non-Cryptographic", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 4549, + 4556 + ] + }, + { + "chunk_id": "chunk_a8630b22", + "text": "Non-cryptographic PRNGs, such as LFSRs and the linear-congruential generators found in many programming libraries, may generate statistically satisfactory random numbers but must never be used for cryptographic keying.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Standards and Terminology > Pseudorandom Number Generator (PRNG)", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 4566, + 4573 + ] + }, + { + "chunk_id": "chunk_89978e21", + "text": "The DRBG should still be frequently refreshed (reseeded) for forward and backward security.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Standards and Terminology > Deterministic Random Bit Generator (DRBG)", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 4578, + 4587 + ] + }, + { + "chunk_id": "chunk_afb4ff93", + "text": "An entropy source does not require a high-bandwidth interface; a single DRBG source initialization only requires 512 bits (256 bits of entropy), and DRBG output can be shared by any number of callers.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > The `seed` CSR", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 4600, + 4604 + ] + }, + { + "chunk_id": "chunk_0aea1c13", + "text": "Once initiated, a DRBG requires new entropy only to mitigate the risk of state compromise.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > The `seed` CSR", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 4600, + 4604 + ] + }, + { + "chunk_id": "chunk_bc5205da", + "text": "From a security perspective, it is essential that the side effect of flushing the secret entropy bits occurs upon reading.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > The `seed` CSR", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 4606, + 4608 + ] + }, + { + "chunk_id": "chunk_fc8f92ca", + "text": "Hence we mandate a write operation on this particular CSR.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > The `seed` CSR", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 4606, + 4608 + ] + }, + { + "chunk_id": "chunk_0c6bdf30", + "text": "A blocking instruction may have been easier to use, but most users should be querying a (D)RBG instead of an entropy source.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > The `seed` CSR", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 4610, + 4615 + ] + }, + { + "chunk_id": "chunk_0c584d48", + "text": "Without a polling-style mechanism, the entropy source could hang for thousands of cycles under some circumstances. A `wfi` or `pause` mechanism (at least potentially) allows energy-saving sleep on MCUs and context switching on higher-end CPUs.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > The `seed` CSR", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "range", + "line_range": [ + 4610, + 4615 + ] + }, + { + "chunk_id": "chunk_b1f58541", + "text": "The reason for the particular `OPST = seed[31:0]` two-bit mechanism is to provide redundancy.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > The `seed` CSR", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 4617, + 4620 + ] + }, + { + "chunk_id": "chunk_819b73e0", + "text": "The \"fault\" bit combinations `11` (`DEAD`) and `00` (`BIST`) are more likely for electrical reasons if feature discovery fails and the entropy source is actually not available.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > The `seed` CSR", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 4617, + 4620 + ] + }, + { + "chunk_id": "chunk_917fae76", + "text": "The 16-bit bandwidth was a compromise motivated by the desire to provide redundancy in the return value, some protection against potential Power/EM leakage (further alleviated by the 2:1 cryptographic conditioning discussed in ), and the desire to have all of the bits \"in the same place\" on both RV32 and RV64 architectures for programming convenience.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > The `seed` CSR", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 4622, + 4627 + ] + }, + { + "chunk_id": "chunk_6d42042e", + "text": "Hence NIST SP 800-90B cite:[TuBaKe:18] min-entropy assessment must guarantee at least 128 + 64 = 192 bits input entropy per 256-bit block (cite:[BaKeMc:25], Sections 4.1. and 4.3.2).", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > NIST SP 800-90B", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 4633, + 4643 + ] + }, + { + "chunk_id": "chunk_fadc1b89", + "text": "Only then a hashing of 16 * 16 = 256 bits from the entropy source will produce the desired 128 bits of full entropy.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > NIST SP 800-90B", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 4633, + 4643 + ] + }, + { + "chunk_id": "chunk_3f4742f2", + "text": "If NIST SP 800-90B certification is chosen, the entropy source should implement at least the health tests defined in Section 4.4 of cite:[TuBaKe:18]: the repetition count test and adaptive proportion test, or show that the same flaws will be detected by vendor-defined tests.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > NIST SP 800-90B", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 4656, + 4660 + ] + }, + { + "chunk_id": "chunk_df4fd91e", + "text": "For validation purposes, the PTG.2 requirements may be mapped to security controls T1-3 () and the interface as follows:", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > BSI AIS-31", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 4671, + 4673 + ] + }, + { + "chunk_id": "chunk_d4faae6d", + "text": "P1 *[PTG.2.1]* Start-up tests map to T1 and reset-triggered (on-demand) `BIST` tests. * P2 *[PTG.2.2]* Continuous testing total failure maps to T2 and the `DEAD` state. * P3 *[PTG.2.3]* Online tests are continuous tests of T2 \u2013 entropy output is prevented in the `BIST` state. * P4 *[PTG.2.4]* Is related to the design of effective entropy source health tests, which we encourage. * P5 *[PTG.2.5]* Raw random sequence may be checked via the GetNoise interface (). * P6 *[PTG.2.6]* Test Procedure A cite:[KiSc11] (Sect 2.4.4.1) is a part of the evaluation process, and we suggest self-evaluation using these tests even if AIS-31 certification is not sought. * P7 *[PTG.2.7]* Average Shannon entropy of \"internal random bits\" exceeds 0.997.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > BSI AIS-31", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 4675, + 4689 + ] + }, + { + "chunk_id": "chunk_543b1060", + "text": "The entropy source must be able to support current and future security standards and applications.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > Virtual Sources", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 4706, + 4712 + ] + }, + { + "chunk_id": "chunk_d087e925", + "text": "The 256-bit requirement maps to \"Category 5\" of NIST Post-Quantum Cryptography (4.A.5 \"Security Strength Categories\" in cite:[NI16]) and TOP SECRET schemes in Suite B and the newer U.S.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > Virtual Sources", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 4706, + 4712 + ] + }, + { + "chunk_id": "chunk_9aa89725", + "text": "The ISA implementation and system design must try to ensure that the hardware-software interface minimizes avenues for adversarial information flow even if not explicitly forbidden in the specification.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > Security Considerations for Direct Hardware Access", + "confidence": "very_high", + "parameter_class": "SW_rule", + "parameter_type": "binary", + "line_range": [ + 4719, + 4721 + ] + }, + { + "chunk_id": "chunk_7b59297f", + "text": "It is recommended if a single physical entropy source is shared between multiple different virtual machines or if the guest OS is untrusted. A virtual entropy source is significantly more resistant to depletion attacks and also lessens the risk from covert channels.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > Security Considerations for Direct Hardware Access", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 4723, + 4727 + ] + }, + { + "chunk_id": "chunk_c8ba5855", + "text": "The direct `mseccfg.[s,u]seed` option allows one to draw a security boundary around a component in relation to Sensitive Security Parameter (SSP) flows, even if that component is not in M mode.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > Security Considerations for Direct Hardware Access", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 4729, + 4735 + ] + }, + { + "chunk_id": "chunk_c25c8bcb", + "text": "This is helpful when implementing trusted enclaves.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > Security Considerations for Direct Hardware Access", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 4729, + 4735 + ] + }, + { + "chunk_id": "chunk_81486d45", + "text": "All information flows and interaction mechanisms must be considered from an adversarial viewpoint: the fewer the better.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > Security Considerations for Direct Hardware Access", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 4763, + 4767 + ] + }, + { + "chunk_id": "chunk_b495a948", + "text": "If it does, additional countermeasures are necessary.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > Security Considerations for Direct Hardware Access", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 4769, + 4776 + ] + }, + { + "chunk_id": "chunk_2066a0c8", + "text": "In almost all cases, a hardware entropy source must implement appropriate security controls to guarantee unpredictability, prevent leakage, detect attacks, and deny adversarial control over the entropy output or ts generation mechanism.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests", + "confidence": "very_high", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 4781, + 4786 + ] + }, + { + "chunk_id": "chunk_379d8339", + "text": "Hence the default action in case of a failure should be aimed at damage control: Limiting further output and preventing weak crypto keys from being generated.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 4797, + 4800 + ] + }, + { + "chunk_id": "chunk_e7a1e83e", + "text": "The implementation will simply return `BIST` during the initial start-up self-test period; in any case, the driver must wait for them to finish before starting cryptographic operations.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests > T1: On-demand testing", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 4808, + 4813 + ] + }, + { + "chunk_id": "chunk_67999daa", + "text": "If an error is detected in continuous tests or environmental sensors, the entropy source will enter a no-output state.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests > T2: Continuous checks", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 4824, + 4831 + ] + }, + { + "chunk_id": "chunk_33d6149d", + "text": "We define that a non-critical alarm is signaled if the entropy source returns to `BIST` state from live (`WAIT` or `ES16`) states.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests > T2: Continuous checks", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 4824, + 4831 + ] + }, + { + "chunk_id": "chunk_27503b07", + "text": "Critical failures will result in `DEAD` state immediately. A hardware-based continuous testing mechanism must not make statistical information externally available, and it must be zeroized periodically or upon demand via reset, power-up, or similar signal.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests > T2: Continuous checks", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 4824, + 4831 + ] + }, + { + "chunk_id": "chunk_474b7d61", + "text": "The design should avoid guiding such active attacks by revealing detailed status information.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests > T2: Continuous checks", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 4833, + 4838 + ] + }, + { + "chunk_id": "chunk_8d37cdad", + "text": "Upon detection of an attack, the default action should be aimed at damage control -- to prevent weak crypto keys from being generated.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests > T2: Continuous checks", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 4833, + 4838 + ] + }, + { + "chunk_id": "chunk_eb9afb91", + "text": "There may also be requirements for signaling of non-fatal alarms; AIS 31 specifies \"noise alarms\" that can go off with non-negligible probability even if the device is functioning correctly; these can be signaled with `BIST`.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests > T2: Continuous checks", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 4840, + 4846 + ] + }, + { + "chunk_id": "chunk_cefa4f3e", + "text": "There rarely is anything that can or should be done about a non-fatal alarm condition in an operator-free, autonomous system.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests > T2: Continuous checks", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 4840, + 4846 + ] + }, + { + "chunk_id": "chunk_1948121a", + "text": "Since the security of most cryptographic operations depends on the entropy source, a system-wide \"default deny\" security policy approach is appropriate for most entropy source failures. A hardware test failure should at least result in the `DEAD` state and possibly reset/halt.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests > T3: Fatal error states", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 4854, + 4860 + ] + }, + { + "chunk_id": "chunk_9fd34c6f", + "text": "It\u2019s a show stopper: The entropy source (or its cryptographic client application) must not be allowed to run if its secure operation can\u2019t be guaranteed.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests > T3: Fatal error states", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 4854, + 4860 + ] + }, + { + "chunk_id": "chunk_5135b5ea", + "text": "However, even such \"innocent\" failure modes may indicate a fault attack cite:[KaScVe13] and therefore should be addressed as a system integrity failure rather than as a diagnostic issue.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests > T3: Fatal error states", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 4866, + 4870 + ] + }, + { + "chunk_id": "chunk_4b36f457", + "text": "Security architects will understand to use permanent or hard-to-recover \"security-fuse\" lockdowns only if the threshold of a test is such that the probability of false-positive is negligible over the entire device lifetime.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests > T3: Fatal error states", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 4872, + 4875 + ] + }, + { + "chunk_id": "chunk_eccca728", + "text": "For the same reasons, only complete and fully processed random words shall be made available via `entropy` (ES16 status of `seed`).", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests > Information Flows", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 4885, + 4890 + ] + }, + { + "chunk_id": "chunk_d5ba3935", + "text": "Importantly the test interface and the main interface should not be operational at the same time.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests > Information Flows", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 4892, + 4895 + ] + }, + { + "chunk_id": "chunk_709927df", + "text": "[quote, NIST SP 800-90B, Noise Source Requirements] The noise source state shall be protected from adversarial knowledge or influence to the greatest extent possible.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests > Information Flows", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 4897, + 4902 + ] + }, + { + "chunk_id": "chunk_4a3dd97e", + "text": "The methods used for this shall be documented, including a description of the (conceptual) security boundary's role in protecting the noise source from adversarial observation or influence.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests > Information Flows", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 4897, + 4902 + ] + }, + { + "chunk_id": "chunk_82df096a", + "text": "When considering implementation options and trade-offs, one must look at the entire information flow.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 4920, + 4921 + ] + }, + { + "chunk_id": "chunk_b131ce4a", + "text": "This raw data also needs to be protected by the design. . *Continuous health tests* ensure that the noise source and its environment meet their operational parameters. . *Non-cryptographic conditioners* remove much of the bias and correlation in input noise. . *Cryptographic conditioners* produce full entropy output, completely indistinguishable from ideal random. . *DRBG* takes in `>=256` bits of seed entropy as keying material and uses a \"one way\" cryptographic process to rapidly generate bits on demand (without revealing the seed/state).", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 4923, + 4935 + ] + }, + { + "chunk_id": "chunk_e6b5f0fa", + "text": "Steps 1-4 (possibly 5) are considered to be part of the Entropy Source (ES) and provided by the `seed` CSR.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 4937, + 4940 + ] + }, + { + "chunk_id": "chunk_9c194382", + "text": "The sampled bit sequence may be expected to be relatively uncorrelated (close to IID) if the sample rate is suitably low cite:[KiSc11].", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Ring Oscillators", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 4948, + 4954 + ] + }, + { + "chunk_id": "chunk_b728bc1b", + "text": "Their output is sometimes highly dependent on temperature, which must be taken into account in testing and modeling.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Ring Oscillators", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 4973, + 4983 + ] + }, + { + "chunk_id": "chunk_250bceb3", + "text": "Countermeasures are related to circuit design; environmental sensors, electrical filters, and usage of a differential oscillator may help.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Ring Oscillators", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 4973, + 4983 + ] + }, + { + "chunk_id": "chunk_e1e67d7c", + "text": "It may be possible to certify more exotic noise sources and designs, although their stochastic model needs to be equally well understood, and their CPU interfaces must be secure.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Other types of noise", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 4999, + 5003 + ] + }, + { + "chunk_id": "chunk_4e9f12e6", + "text": "The tests should be designed in a way that a specific number of samples guarantees a state flush (no hung states).", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Continuous Health Tests", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 5008, + 5013 + ] + }, + { + "chunk_id": "chunk_71af6c13", + "text": "Repetition count is reset every time the output sample value changes; if the count reaches a certain cutoff limit, a noise alarm (`BIST`) or failure (`DEAD`) is signaled.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Continuous Health Tests", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 5015, + 5025 + ] + }, + { + "chunk_id": "chunk_2b1ad5e8", + "text": "We see that the structure of the mandatory tests is such that, if well implemented, no information is carried beyond a limit of `W` samples.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Continuous Health Tests", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 5015, + 5025 + ] + }, + { + "chunk_id": "chunk_4c4143f0", + "text": "Especially if a non-cryptographic conditioner is used in hardware, it is possible that the AIS 31 cite:[KiSc11] online tests are implemented by driver software.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Continuous Health Tests", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 5033, + 5040 + ] + }, + { + "chunk_id": "chunk_7c5d7029", + "text": "For some security profiles, AIS 31 mandates that their tolerances are set in a way that the probability of an alarm is at least 10^-6^ yearly under \"normal usage.\" Such requirements are problematic in modern applications since their probability is too high for critical systems.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Continuous Health Tests", + "confidence": "medium", + "parameter_class": "SW_rule", + "parameter_type": "range", + "line_range": [ + 5033, + 5040 + ] + }, + { + "chunk_id": "chunk_3527cd09", + "text": "There rarely is anything that can or should be done about a non-fatal alarm condition in an operator-free, autonomous system.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Continuous Health Tests", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 5042, + 5050 + ] + }, + { + "chunk_id": "chunk_94a3ce45", + "text": "However, AIS 31 allows the DRBG component to keep running despite a failure in its Entropy Source, so we suggest re-entering a temporary `BIST` state () to signal a non-fatal statistical error if such (non-actionable) signaling is necessary.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Continuous Health Tests", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 5042, + 5050 + ] + }, + { + "chunk_id": "chunk_110f0933", + "text": "Drivers and applications can react to this appropriately (or simply log it), but it will not directly affect the availability of the TRNG. A permanent error condition should result in `DEAD` state.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Continuous Health Tests", + "confidence": "medium", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 5042, + 5050 + ] + }, + { + "chunk_id": "chunk_08fdad7f", + "text": "One may take a set of bits from a noise source and XOR them together to produce a less biased (and more independent) bit.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Non-cryptographic Conditioners", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 5065, + 5079 + ] + }, + { + "chunk_id": "chunk_3184ba57", + "text": "However, such an XOR may introduce \"pseudorandomness\" and make the output difficult to analyze. * The von Neumann extractor cite:[Ne51] looks at consecutive pairs of bits, rejects 00 and 11, and outputs 0 or 1 for 01 and 10, respectively.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Non-cryptographic Conditioners", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 5065, + 5079 + ] + }, + { + "chunk_id": "chunk_788ef845", + "text": "If its assumptions hold, it also removes dependencies, creating an independent and identically distributed (IID) source. * Other linear and non-linear correctors such as those discussed by Dichtl and Lacharme cite:[La08].", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Non-cryptographic Conditioners", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 5065, + 5079 + ] + }, + { + "chunk_id": "chunk_a46bac67", + "text": "If well designed, they can be evaluated in conjunction with a stochastic model of the noise source itself.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Non-cryptographic Conditioners", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 5085, + 5090 + ] + }, + { + "chunk_id": "chunk_a3cdec66", + "text": "They may also be implemented on the hardware side if necessary.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Cryptographic Conditioners", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 5095, + 5099 + ] + }, + { + "chunk_id": "chunk_4b09bc92", + "text": "In any case, the `entropy` ES16 output must always be compressed 2:1 (or more) before being used as keying material or considered \"full entropy.\"", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Cryptographic Conditioners", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 5095, + 5099 + ] + }, + { + "chunk_id": "chunk_b32cff0f", + "text": "On the other hand, simpler non-cryptographic conditioners may be too wasteful on input entropy if high-quality random output is required -- (ARM TrustZone TRBG cite:[AR17] outputs only 10Kbit/sec at 200 MHz.) Hence a resource-saving compromise is made between hardware and software generation.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Cryptographic Conditioners", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 5110, + 5118 + ] + }, + { + "chunk_id": "chunk_767c5dd1", + "text": "All random bits reaching end users and applications must come from a cryptographic DRBG.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > The Final Random: DRBGs", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 5123, + 5127 + ] + }, + { + "chunk_id": "chunk_b90d64a0", + "text": "The RISC-V AES and SHA instruction set extensions should be used if available since they offer additional security features such as timing attack resistance.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > The Final Random: DRBGs", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 5123, + 5127 + ] + }, + { + "chunk_id": "chunk_d80165d5", + "text": "These are significantly easier to implement in software than in hardware.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > The Final Random: DRBGs", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 5129, + 5136 + ] + }, + { + "chunk_id": "chunk_cc6918ae", + "text": "This security model means that many of the available QRNG devices do not use cryptographic conditioning and may fail cryptographic statistical requirements cite:[HuHe20].", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Quantum vs. Classical Random", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 5168, + 5171 + ] + }, + { + "chunk_id": "chunk_8f76eda7", + "text": "Many implementers may consider them to be entropy sources instead.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Quantum vs. Classical Random", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 5168, + 5171 + ] + }, + { + "chunk_id": "chunk_f1e13901", + "text": "Of course, one must avoid DRBGs that are based on problems that are easily solvable with quantum computers, such as factoring cite:[Sh94] in the case of the Blum-Blum-Shub generator cite:[BlBlSh86].", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Post-Quantum Cryptography", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 5194, + 5198 + ] + }, + { + "chunk_id": "chunk_a25f96f8", + "text": "While even \"64-bit\" quantum security is extremely difficult to break, many applications specify a higher security requirement. NIST cite:[NI16] defines AES-128 to be \"Category 1\" equivalent post-quantum security, while AES-256 is \"Category 5\" (highest).", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Post-Quantum Cryptography", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 5200, + 5209 + ] + }, + { + "chunk_id": "chunk_ea4b9ac0", + "text": "Since this type of interface is both necessary for security testing and also constitutes a potential backdoor to the cryptographic key generation process, we define a safety behavior that compliant implementations can have for temporarily disabling the entropy source `seed` CSR interface during test.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Suggested GetNoise Test Interface", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 5219, + 5223 + ] + }, + { + "chunk_id": "chunk_14e3315f", + "text": "In order for shared RISC-V self-certification scripts (and drivers) to accommodate the test interface in a secure fashion, we suggest that it is implemented as a custom, M-mode only CSR, denoted here as `mnoise`.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Suggested GetNoise Test Interface", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 5225, + 5227 + ] + }, + { + "chunk_id": "chunk_434131ac", + "text": "We define the semantics for single bit for this interface, `mnoise[31]`, which is named `NOISETEST`, which will affect the behavior of `seed` if implemented.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Suggested GetNoise Test Interface", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 5229, + 5233 + ] + }, + { + "chunk_id": "chunk_8a163af0", + "text": "When `NOISETEST = 1` in `mnoise`, the `seed` CSR must not return anything via `ES16`; it should be in `BIST` state unless the source is `DEAD`.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Suggested GetNoise Test Interface", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 5235, + 5239 + ] + }, + { + "chunk_id": "chunk_6ae842cc", + "text": "When `NOISETEST` is again disabled, the entropy source shall return from `BIST` via an appropriate zeroization and self-test mechanism.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Suggested GetNoise Test Interface", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 5235, + 5239 + ] + }, + { + "chunk_id": "chunk_93b2f655", + "text": "The behavior of other input and output bits is largely left to the vendor (as they depend on the technical details of the physical entropy source), as is the address of the custom `mnoise` CSR.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Suggested GetNoise Test Interface", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 5241, + 5245 + ] + }, + { + "chunk_id": "chunk_2763a284", + "text": "Other contents and behavior of the CSR only can be interpreted in the context of `mvendorid`, `marchid`, and `mimpid` CSR identifiers.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Suggested GetNoise Test Interface", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 5241, + 5245 + ] + }, + { + "chunk_id": "chunk_ad7f258b", + "text": "Implementation of test interfaces that directly affect ES16 entropy output from the `seed` CSR interface is discouraged.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Suggested GetNoise Test Interface", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 5252, + 5264 + ] + }, + { + "chunk_id": "chunk_a34eb39b", + "text": "Hence even a temporary lapse in `entropy` security may have serious security implications.", + "source_file": "src/scalar-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Suggested GetNoise Test Interface", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 5252, + 5264 + ] + } + ] + }, + { + "file": "src/unpriv/bitmanip-examples.adoc", + "chunks": [ + { + "chunk_id": "chunk_d800fa01", + "text": "the result of *orc.b* on a chunk that does not contain any *NUL* bytes will be all-ones, and * after a bitwise-negation of the result of *orc.b*, the number of data bytes before the first *NUL* byte (if any) can be detected by *ctz*/*clz* (depending on the endianness of data).", + "source_file": "src/unpriv/bitmanip-examples.adoc", + "section": "Preamble > Bit Manipulation Extensions Assembly Code Examples > strlen", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 9, + 10 + ] + }, + { + "chunk_id": "chunk_e6028ff0", + "text": "Get bytes in big-endian order and compare. if BYTEORDER ORDERLITTLEENDIAN rev8 a2, a2 rev8 a3, a3 endif Synthesize (a2 >= a3) ? 1 : -1 in a branchless sequence. sltu a0, a2, a3 neg a0, a0 ori a0, a0, 1 ret", + "source_file": "src/unpriv/bitmanip-examples.adoc", + "section": "Preamble > Bit Manipulation Extensions Assembly Code Examples > strlen > strcmp", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 109, + 119 + ] + }, + { + "chunk_id": "chunk_a5a4afaf", + "text": "If words don't match, fall back to simple loop. bne a2, a3, .Lsimpleloop", + "source_file": "src/unpriv/bitmanip-examples.adoc", + "section": "Preamble > Bit Manipulation Extensions Assembly Code Examples > strlen > strcmp", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 121, + 124 + ] + } + ] + }, + { + "file": "src/unpriv/c-st-ext.adoc", + "chunks": [ + { + "chunk_id": "chunk_d5c591df", + "text": "If XLEN=32 and the F extension is present, the ext:c[] extension additionally depends upon the extlink:zcf[] extension.", + "source_file": "src/unpriv/c-st-ext.adoc", + "section": "Preamble > ext:c[] Extension for Compressed Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 13, + 14 + ] + }, + { + "chunk_id": "chunk_76dbbf83", + "text": "If the D extension is present, the ext:c[] extension additionally depends upon the extlink:zcd[] extension.", + "source_file": "src/unpriv/c-st-ext.adoc", + "section": "Preamble > ext:c[] Extension for Compressed Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 16, + 17 + ] + } + ] + }, + { + "file": "src/unpriv/cfi.adoc", + "chunks": [ + { + "chunk_id": "chunk_a5541f68", + "text": "Conditional branches encode an offset in the immediate field of the instruction and are thus direct branches that are not susceptible to control-flow subversion.", + "source_file": "src/unpriv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 13, + 20 + ] + }, + { + "chunk_id": "chunk_ff57a87c", + "text": "Unconditional indirect jumps using the `JALR` obtain their branch target by adding the sign extended 12-bit immediate encoded in the instruction to the `rs1` register.", + "source_file": "src/unpriv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI)", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 13, + 20 + ] + }, + { + "chunk_id": "chunk_c616789b", + "text": "The RV32I/RV64I does not have a dedicated instruction for calling a procedure or returning from a procedure. A `JAL` or `JALR` may be used to perform a procedure call and `JALR` to return from a procedure.", + "source_file": "src/unpriv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI)", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 22, + 29 + ] + }, + { + "chunk_id": "chunk_c639dd6a", + "text": "The `C.J` and `C.JAL` instructions encode an offset in the immediate field of the instruction and thus are not susceptible to control-flow subversion.", + "source_file": "src/unpriv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 31, + 39 + ] + }, + { + "chunk_id": "chunk_dd1685e2", + "text": "The `LPAD` instruction must be placed at the program locations that are valid targets of indirect jumps or calls.", + "source_file": "src/unpriv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp)", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 70, + 74 + ] + }, + { + "chunk_id": "chunk_fdc515eb", + "text": "When the Zicfilp is active, the hart tracks an expected landing pad (`ELP`) state that is updated by an indirectcall or indirectjump to require a landing pad instruction at the target of the branch.", + "source_file": "src/unpriv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 81, + 87 + ] + }, + { + "chunk_id": "chunk_0d038889", + "text": "If the instruction at the target is not a landing pad, then a software-check exception is raised.", + "source_file": "src/unpriv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp)", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 81, + 87 + ] + }, + { + "chunk_id": "chunk_c07a1444", + "text": "A landing pad may be optionally associated with a 20-bit label.", + "source_file": "src/unpriv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp)", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 89, + 96 + ] + }, + { + "chunk_id": "chunk_78cbda99", + "text": "When labeling of landing pads is used, indirect call or indirect jump site can specify the expected label of the landing pad and thereby constrain the set of landing pads that may be reached from each indirect call or indirect jump site in the program.", + "source_file": "src/unpriv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp)", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 89, + 96 + ] + }, + { + "chunk_id": "chunk_05841818", + "text": "By constraining gadgets to be preceded by a landing pad instruction that marks the start of indirect callable functions, the program can significantly reduce the available gadget space. A second form of label generation may generate a signature, such as a MAC, using the prototype of the function.", + "source_file": "src/unpriv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp)", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 98, + 125 + ] + }, + { + "chunk_id": "chunk_0b1a2a8f", + "text": "Such programs may further use multiple labels per function, which means that if a function is called from two or more call sites, the functions can be labeled as being reachable from each of the call sites.", + "source_file": "src/unpriv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp)", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 98, + 125 + ] + }, + { + "chunk_id": "chunk_f5a7f46a", + "text": "However, if function Y was assigned two labels - one corresponding to call site A and the other to call site B, then Y can be invoked by both call sites, but X can only be invoked by call site A and Z can only be invoked by call site B.", + "source_file": "src/unpriv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 98, + 125 + ] + }, + { + "chunk_id": "chunk_d99afebb", + "text": "This would allow the function to be labeled with multiple labels, each corresponding to a specific call site. A portion of the label space may be dedicated to labeled landing pads that are only valid targets of an indirect jump (and not an indirect call).", + "source_file": "src/unpriv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp)", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 98, + 125 + ] + }, + { + "chunk_id": "chunk_f5842660", + "text": "When Zicfilp is not active at a privilege level or when the extension is not implemented, the landing pad instruction executes as a no-op. A program that is built with `LPAD` instructions can thus continue to operate correctly, but without forward-edge control-flow integrity, on processors that do not support the Zicfilp extension or if the Zicfilp extension is not active.", + "source_file": "src/unpriv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 127, + 132 + ] + }, + { + "chunk_id": "chunk_f507952e", + "text": "Compilers and linkers should provide an attribute flag to indicate if the program has been compiled with the Zicfilp extension and use that to determine if the Zicfilp extension should be activated.", + "source_file": "src/unpriv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp)", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 134, + 139 + ] + }, + { + "chunk_id": "chunk_fecd75f8", + "text": "The dynamic loader should activate the use of Zicfilp extension for an application only if all executables (the application and the dependent dynamically linked libraries) used by that application use the Zicfilp extension.", + "source_file": "src/unpriv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp)", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 134, + 139 + ] + }, + { + "chunk_id": "chunk_40e9212b", + "text": "When Zicfilp extension is not active or not implemented, the hart does not require landing pad instructions at the targets of indirect calls/jumps, and the landing instructions revert to being no-ops.", + "source_file": "src/unpriv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 141, + 145 + ] + }, + { + "chunk_id": "chunk_410b183a", + "text": "The Zicfilp extensions may be activated for use individually and independently for each privilege mode.", + "source_file": "src/unpriv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp)", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 147, + 148 + ] + }, + { + "chunk_id": "chunk_b2ac7cce", + "text": "The Zicfilp extension depends on the Zicsr extension.", + "source_file": "src/unpriv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp)", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 150, + 150 + ] + }, + { + "chunk_id": "chunk_871c41a4", + "text": "To enforce that the target of an indirect call or indirect jump must be a valid landing pad instruction, the hart maintains an expected landing pad (`ELP`) state to determine if a landing pad instruction is required at the target of an indirect call or an indirect jump.", + "source_file": "src/unpriv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing Pad Enforcement", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 154, + 157 + ] + }, + { + "chunk_id": "chunk_6e14207f", + "text": "The Zicfilp extension, when enabled, determines if an indirect call or an indirect jump must land on a landing pad, as specified in .", + "source_file": "src/unpriv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing Pad Enforcement", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 164, + 167 + ] + }, + { + "chunk_id": "chunk_0f5d631f", + "text": "If `islpexpected` is 1, then the hart updates the `ELP` to `LPEXPECTED`.", + "source_file": "src/unpriv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing Pad Enforcement", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 164, + 167 + ] + }, + { + "chunk_id": "chunk_1816d7b0", + "text": "The landing pad may be labeled.", + "source_file": "src/unpriv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing Pad Enforcement", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 183, + 191 + ] + }, + { + "chunk_id": "chunk_c1df2e5a", + "text": "The `LPAD` instruction is encoded with a 20-bit immediate value called the landing-pad-label (`LPL`) that is matched to the expected landing pad label.", + "source_file": "src/unpriv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing Pad Enforcement", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 183, + 191 + ] + }, + { + "chunk_id": "chunk_e5f11012", + "text": "When `LPL` is encoded as zero, the `LPAD` instruction does not perform the label check and in programs built with this single label mode of operation the indirect call/jump sites do not need to establish an expected landing pad label value in `x7`.", + "source_file": "src/unpriv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing Pad Enforcement", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 183, + 191 + ] + }, + { + "chunk_id": "chunk_efa1a38f", + "text": "When `ELP` is set to `LPEXPECTED`, if the next instruction in the instruction stream is not 4-byte aligned, or is not `LPAD`, or if the landing pad label encoded in `LPAD` is not zero and does not match the expected landing pad label in bits 31:12 of the `x7` register, then a software-check exception (cause=18) with `xtval` set to \"landing pad fault (code=2)\" is raised else the `ELP` is updated to `NOLPEXPECTED`.", + "source_file": "src/unpriv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing Pad Enforcement", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "range", + "line_range": [ + 193, + 199 + ] + }, + { + "chunk_id": "chunk_0c5f0d86", + "text": "When Zicfilp is enabled, `LPAD` is the only instruction allowed to execute when the `ELP` state is `LPEXPECTED`.", + "source_file": "src/unpriv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing Pad Enforcement > Landing Pad Instruction", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 206, + 210 + ] + }, + { + "chunk_id": "chunk_e73ff3d6", + "text": "If Zicfilp is not enabled then the instruction is a no-op.", + "source_file": "src/unpriv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing Pad Enforcement > Landing Pad Instruction", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 206, + 210 + ] + }, + { + "chunk_id": "chunk_5b363bc7", + "text": "If Zicfilp is enabled, the `LPAD` instruction causes a software-check exception with `xtval` set to \"landing pad fault (code=2)\" if any of the following conditions are true:", + "source_file": "src/unpriv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing Pad Enforcement > Landing Pad Instruction", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "binary", + "line_range": [ + 206, + 210 + ] + }, + { + "chunk_id": "chunk_75394296", + "text": "The `pc` is not 4-byte aligned and `ELP` is `LPEXPECTED`. * The `ELP` is `LPEXPECTED` and the `LPL` is not zero and the `LPL` does not match the expected landing pad label in bits 31:12 of the `x7` register.", + "source_file": "src/unpriv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing Pad Enforcement > Landing Pad Instruction", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 212, + 213 + ] + }, + { + "chunk_id": "chunk_f439a0f0", + "text": "If a software-check exception is not caused then the `ELP` is updated to `NOLPEXPECTED`.", + "source_file": "src/unpriv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing Pad Enforcement > Landing Pad Instruction", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 215, + 217 + ] + }, + { + "chunk_id": "chunk_a4e42b97", + "text": "If PC not 4-byte aligned then software-check exception if pc[1:0] != 0 raise software-check exception //", + "source_file": "src/unpriv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing Pad Enforcement > Landing Pad Instruction", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "range", + "line_range": [ + 230, + 247 + ] + }, + { + "chunk_id": "chunk_37d3e12d", + "text": "If landing pad label not matched -> software-check exception else if (inst.LPL != x7[31:12] && inst.LPL != 0) raise software-check exception else ELP = NOLPEXPECTED else no-op endif ---- <<<", + "source_file": "src/unpriv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing Pad Enforcement > Landing Pad Instruction", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 230, + 247 + ] + }, + { + "chunk_id": "chunk_f099cf05", + "text": "The Zicfiss extension introduces a shadow stack to enforce backward-edge control-flow integrity. A shadow stack is a second stack used to store a shadow copy of the return address in the link register if it needs to be spilled.", + "source_file": "src/unpriv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 252, + 255 + ] + }, + { + "chunk_id": "chunk_a858386a", + "text": "The shadow stack is used to spill the link register, if required, by non-leaf functions.", + "source_file": "src/unpriv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 262, + 266 + ] + }, + { + "chunk_id": "chunk_4e4bdadc", + "text": "When such a function returns (the epilogue), the function loads the link register from the regular stack and the shadow copy of the link register from the shadow stack.", + "source_file": "src/unpriv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 282, + 291 + ] + }, + { + "chunk_id": "chunk_77fcb688", + "text": "Then, the link register value from the regular stack and the shadow link register value from the shadow stack are compared. A mismatch of the two values is indicative of a subversion of the return address control variable and causes a software-check exception.", + "source_file": "src/unpriv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss)", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 282, + 291 + ] + }, + { + "chunk_id": "chunk_a2b1a9d1", + "text": "The Zicfiss instructions, except `SSAMOSWAP.W/D`, are encoded using a subset of May-Be-Operation instructions defined by the Zimop and Zcmop extensions.", + "source_file": "src/unpriv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 293, + 301 + ] + }, + { + "chunk_id": "chunk_309ec18a", + "text": "This subset of instructions revert to their Zimop/Zcmop defined behavior when the Zicfiss extension is not implemented or if the extension has not been activated. A program that is built with Zicfiss instructions can thus continue to operate correctly, but without backward-edge control-flow integrity, on processors that do not support the Zicfiss extension or if the Zicfiss extension is not active.", + "source_file": "src/unpriv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 293, + 301 + ] + }, + { + "chunk_id": "chunk_88341973", + "text": "The Zicfiss extension may be activated for use individually and independently for each privilege mode.", + "source_file": "src/unpriv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss)", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 293, + 301 + ] + }, + { + "chunk_id": "chunk_fe0e295b", + "text": "The dynamic loader should activate the use of Zicfiss extension for an application only if all executables (the application and the dependent dynamically-linked libraries) used by that application use the Zicfiss extension.", + "source_file": "src/unpriv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss)", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 310, + 313 + ] + }, + { + "chunk_id": "chunk_ffe57f52", + "text": "The Zicfiss extension depends on the Zicsr, Zimop and Zaamo extensions.", + "source_file": "src/unpriv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss)", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 325, + 328 + ] + }, + { + "chunk_id": "chunk_5d7c1318", + "text": "Furthermore, if the Zcmop extension is implemented, the Zicfiss extension also provides the `C.SSPUSH` and `C.SSPOPCHK` instructions.", + "source_file": "src/unpriv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 325, + 328 + ] + }, + { + "chunk_id": "chunk_27aaf883", + "text": "When a `MOP.RR.7` or `MOP.R.28` encoding is not used by the Zicfiss extension, the corresponding instruction adheres to its Zimop-defined behavior, unless redefined by another extension.", + "source_file": "src/unpriv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Zicfiss Instructions Summary", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 348, + 351 + ] + }, + { + "chunk_id": "chunk_9942154e", + "text": "The `ssp` CSR is an unprivileged read-write (URW) CSR that reads and writes `XLEN` low order bits of the shadow stack pointer (`ssp`).", + "source_file": "src/unpriv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Pointer (`ssp`)", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 355, + 359 + ] + }, + { + "chunk_id": "chunk_84e9d6dd", + "text": "There is no high CSR defined as the `ssp` is always as wide as the `XLEN` of the current privilege mode.", + "source_file": "src/unpriv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Pointer (`ssp`)", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 355, + 359 + ] + }, + { + "chunk_id": "chunk_32a94b69", + "text": "The bits 1:0 of `ssp` are read-only zero.", + "source_file": "src/unpriv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Pointer (`ssp`)", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 355, + 359 + ] + }, + { + "chunk_id": "chunk_c3016c27", + "text": "If the UXLEN or SXLEN may never be 32, then the bit 2 is also read-only zero.", + "source_file": "src/unpriv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Pointer (`ssp`)", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 355, + 359 + ] + }, + { + "chunk_id": "chunk_fe86b5d0", + "text": "Zicfiss provides a 16-bit version of the `SSPUSH x1` instruction using the Zcmop defined `C.MOP.1` encoding.", + "source_file": "src/unpriv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Push to the Shadow Stack", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 398, + 400 + ] + }, + { + "chunk_id": "chunk_7f13ff0f", + "text": "Zicfiss provides a 16-bit version of the `SSPOPCHK x5` using the Zcmop defined `C.MOP.5` encoding.", + "source_file": "src/unpriv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Pop from the Shadow Stack", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 455, + 457 + ] + }, + { + "chunk_id": "chunk_e3093bf4", + "text": "When returning from these non-leaf functions, such programs pop the link register from the regular stack and pop a shadow copy of the link register from the shadow stack.", + "source_file": "src/unpriv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Pop from the Shadow Stack", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 459, + 464 + ] + }, + { + "chunk_id": "chunk_6d3fded7", + "text": "If the values do not match, it is indicative of a corruption of the return address variable on the regular stack.", + "source_file": "src/unpriv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Pop from the Shadow Stack", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 459, + 464 + ] + }, + { + "chunk_id": "chunk_6b0fdd34", + "text": "While any register may be used as link register, conventionally the `x1` or `x5` registers are used.", + "source_file": "src/unpriv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Pop from the Shadow Stack", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 472, + 474 + ] + }, + { + "chunk_id": "chunk_172d1c6a", + "text": "Only x1 and x5 may be used as src raise software-check exception else ssp = ssp + (XLEN/8) increment ssp by XLEN/8. endif endif ----", + "source_file": "src/unpriv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Pop from the Shadow Stack", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 485, + 499 + ] + }, + { + "chunk_id": "chunk_fb3e3fe3", + "text": "If the value loaded from the address in `ssp` does not match the value in `rs1`, a software-check exception (cause=18) is raised with `xtval` set to \"shadow stack fault (code=3)\".", + "source_file": "src/unpriv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Pop from the Shadow Stack", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 501, + 505 + ] + }, + { + "chunk_id": "chunk_87bc98ef", + "text": "The software-check exception caused by `SSPOPCHK`/ `C.SSPOPCHK` is lower in priority than a load/store/AMO access-fault exception.", + "source_file": "src/unpriv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Pop from the Shadow Stack", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 501, + 505 + ] + }, + { + "chunk_id": "chunk_f46b0060", + "text": "The `ssp` is incremented by `SSPOPCHK` and `C.SSPOPCHK` only if the load from the shadow stack completes successfully and no software-check exception is raised.", + "source_file": "src/unpriv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Pop from the Shadow Stack", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 507, + 510 + ] + }, + { + "chunk_id": "chunk_28b2d36b", + "text": "The `SSRDP` instruction is provided to move the contents of `ssp` to a destination register.", + "source_file": "src/unpriv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Read `ssp` into a Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 518, + 520 + ] + }, + { + "chunk_id": "chunk_3e1e7a49", + "text": "Encoding rd as `x0` is not supported for `SSRDP`.", + "source_file": "src/unpriv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Read `ssp` into a Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 533, + 533 + ] + }, + { + "chunk_id": "chunk_dea0297e", + "text": "The operation of the `SSRDP` instructions is as follows:", + "source_file": "src/unpriv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Read `ssp` into a Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 535, + 535 + ] + }, + { + "chunk_id": "chunk_f1a02f36", + "text": "For RV32, `SSAMOSWAP.W` atomically loads a 32-bit data value from address of a shadow stack location in `rs1`, puts the loaded value into register `rd`, and stores the 32-bit value held in `rs2` to the original address in `rs1`. `SSAMOSWAP.D` (RV64 only) is similar to `SSAMOSWAP.W` but operates on 64-bit data values.", + "source_file": "src/unpriv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Atomic Swap from a Shadow Stack Location", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 568, + 573 + ] + }, + { + "chunk_id": "chunk_d75f186b", + "text": "For RV64, `SSAMOSWAP.W` atomically loads a 32-bit data value from address of a shadow stack location in `rs1`, sign-extends the loaded value and puts it in `rd`, and stores the lower 32 bits of the value held in `rs2` to the original address in `rs1`.", + "source_file": "src/unpriv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Atomic Swap from a Shadow Stack Location", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 594, + 598 + ] + }, + { + "chunk_id": "chunk_8ff591c2", + "text": "The same exception options apply if the address is not naturally aligned.", + "source_file": "src/unpriv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Atomic Swap from a Shadow Stack Location", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 620, + 624 + ] + }, + { + "chunk_id": "chunk_f04d142b", + "text": "An `SSAMOSWAP.W/D` operation has acquire semantics if `aq=1` and release semantics if `rl=1`.", + "source_file": "src/unpriv/cfi.adoc", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Atomic Swap from a Shadow Stack Location", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 626, + 629 + ] + } + ] + }, + { + "file": "src/unpriv/cmo.adoc", + "chunks": [ + { + "chunk_id": "chunk_70b9e13d", + "text": "A management instruction manipulates cached copies of data with respect to a set of agents that can access the data * A zero instruction zeros out a range of memory locations, potentially allocating cached copies of data in one or more caches * A prefetch instruction indicates to hardware that data at a given memory location may be accessed in the near future, potentially allocating cached copies of data in one or more caches", + "source_file": "src/unpriv/cmo.adoc", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Introduction", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 17, + 23 + ] + }, + { + "chunk_id": "chunk_0f8f6d33", + "text": "The execution behavior of the above instructions is also modified by CSR state added by this specification.", + "source_file": "src/unpriv/cmo.adoc", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Introduction", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 37, + 38 + ] + }, + { + "chunk_id": "chunk_4d246f59", + "text": "Any number of caches may be interspersed between an agent and a memory location, and load and store operations from an agent may be satisfied by a cache instead of the memory location.", + "source_file": "src/unpriv/cmo.adoc", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Background > Memory and Caches", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 62, + 65 + ] + }, + { + "chunk_id": "chunk_fef45040", + "text": "In the initial set of CMO extensions, the size of a cache block shall be uniform throughout the system.", + "source_file": "src/unpriv/cmo.adoc", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Background > Memory and Caches", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 67, + 74 + ] + }, + { + "chunk_id": "chunk_c5a53ad0", + "text": "Implementation techniques such as speculative execution or hardware prefetching may cause a given cache to allocate or deallocate a copy of a cache block at any time, provided the corresponding physical addresses are accessible according to the supported access type PMA and are cacheable according to the cacheability PMA.", + "source_file": "src/unpriv/cmo.adoc", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Background > Memory and Caches", + "confidence": "medium", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 76, + 84 + ] + }, + { + "chunk_id": "chunk_25dd6779", + "text": "Allocating a copy of a cache block results in a read transfer from another cache or from memory, while deallocating a copy of a cache block may result in a write transfer to another cache or to memory depending on whether the data in the copy were modified by a store operation.", + "source_file": "src/unpriv/cmo.adoc", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Background > Memory and Caches", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 76, + 84 + ] + }, + { + "chunk_id": "chunk_f30d8b44", + "text": "A clean operation performs a write transfer to another cache or to memory if the data in the copy of the cache block have been modified by a store operation", + "source_file": "src/unpriv/cmo.adoc", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Background > Cache-Block Operations", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 98, + 100 + ] + }, + { + "chunk_id": "chunk_c6d70ed4", + "text": "Unless specified otherwise, the store operations generated by a cache-block zero instruction have the same general properties and behaviors that other store instructions in the architecture have.", + "source_file": "src/unpriv/cmo.adoc", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Background > Cache-Block Operations", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 108, + 114 + ] + }, + { + "chunk_id": "chunk_ad671992", + "text": "An implementation may or may not update the entire set of bytes atomically with a single store operation.", + "source_file": "src/unpriv/cmo.adoc", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Background > Cache-Block Operations", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 108, + 114 + ] + }, + { + "chunk_id": "chunk_a013b8fe", + "text": "The coherent agents within such a set shall access a given memory location with the same physical address and the same physical memory attributes; however, if the coherence PMA for a given agent indicates a given memory location is not coherent, that agent shall not be a member of a set of coherent agents with any other agent for that memory location and shall be the sole member of a set of coherent agents consisting of itself.", + "source_file": "src/unpriv/cmo.adoc", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 133, + 138 + ] + }, + { + "chunk_id": "chunk_75f4f251", + "text": "Caches introduce the possibility that multiple copies of a given cache block may be present in a system at the same time.", + "source_file": "src/unpriv/cmo.adoc", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 145, + 151 + ] + }, + { + "chunk_id": "chunk_4abb473e", + "text": "Additionally, if a coherent agent in the set executes a CBO instruction that specifies the cache block, the resulting operation shall apply to any and all of the copies in the caches that can be accessed by the load and store operations from the coherent agents.", + "source_file": "src/unpriv/cmo.adoc", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 145, + 151 + ] + }, + { + "chunk_id": "chunk_216bd557", + "text": "A coherent cache is permitted to perform a write transfer to memory provided that a store operation has modified the data in the cache block since the most recent invalidate, clean, or flush operation on the cache block", + "source_file": "src/unpriv/cmo.adoc", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 160, + 162 + ] + }, + { + "chunk_id": "chunk_d491fb56", + "text": "A coherent cache is required to perform a write transfer to memory if a store operation has modified the data in the cache block since the most recent invalidate, clean, or flush operation on the cache block and if the next clean or flush operation requires a write transfer to memory", + "source_file": "src/unpriv/cmo.adoc", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 170, + 173 + ] + }, + { + "chunk_id": "chunk_d93d1724", + "text": "A non-coherent agent may initiate a cache-block operation that operates on the set of coherent caches accessed by a set of coherent agents.", + "source_file": "src/unpriv/cmo.adoc", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 175, + 177 + ] + }, + { + "chunk_id": "chunk_ff1e4842", + "text": "Specifically, if a precedes b in program order, then a will precede b in the global memory order if:", + "source_file": "src/unpriv/cmo.adoc", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Memory Ordering > Preserved Program Order", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 187, + 190 + ] + }, + { + "chunk_id": "chunk_9157077d", + "text": "An invalidate operation may change the set of values that can be returned by a load.", + "source_file": "src/unpriv/cmo.adoc", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Memory Ordering > Load Values", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 210, + 211 + ] + }, + { + "chunk_id": "chunk_9abaea11", + "text": "If an invalidate operation i precedes a load r and operates on a byte x returned by r, and no store to x appears between i and r in program order or in the global memory order, then r returns any of the following values for x:", + "source_file": "src/unpriv/cmo.adoc", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Memory Ordering > Load Values", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 213, + 216 + ] + }, + { + "chunk_id": "chunk_1f9748b3", + "text": "If no clean or flush operations on x precede i in the global memory order, either the initial value of x or the value of any store to x that precedes i", + "source_file": "src/unpriv/cmo.adoc", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Memory Ordering > Load Values", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 218, + 220 + ] + }, + { + "chunk_id": "chunk_905ce2ff", + "text": "If no store to x precedes a clean or flush operation on x in the global memory order and if the clean or flush operation on x precedes i in the global memory order, either the initial value of x or the value of any store to x that precedes i", + "source_file": "src/unpriv/cmo.adoc", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Memory Ordering > Load Values", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 222, + 225 + ] + }, + { + "chunk_id": "chunk_4edfbf82", + "text": "If a store to x precedes a clean or flush operation on x in the global memory order and if the clean or flush operation on x precedes i in the global memory order, either the value of the latest store to x that precedes the latest clean or flush operation on x or the value of any store to x that both precedes i and succeeds the latest clean or flush operation on x that precedes i", + "source_file": "src/unpriv/cmo.adoc", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Memory Ordering > Load Values", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 227, + 232 + ] + }, + { + "chunk_id": "chunk_8c4588d9", + "text": "The value of any store to x by a non-coherent agent regardless of the above conditions", + "source_file": "src/unpriv/cmo.adoc", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Memory Ordering > Load Values", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 234, + 235 + ] + }, + { + "chunk_id": "chunk_17c5d1b2", + "text": "Execution of certain CMO instructions may result in traps due to CSR state, described in the section, or due to the address translation and protection mechanisms.", + "source_file": "src/unpriv/cmo.adoc", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Traps", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 239, + 242 + ] + }, + { + "chunk_id": "chunk_2047f520", + "text": "The trapping behavior of CMO instructions is described in the following sections.", + "source_file": "src/unpriv/cmo.adoc", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Traps", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 239, + 242 + ] + }, + { + "chunk_id": "chunk_135b9f22", + "text": "Cache-block management instructions and cache-block zero instructions may raise illegal-instruction exceptions or virtual-instruction exceptions depending on the current privilege mode and the state of the CMO control registers described in the section.", + "source_file": "src/unpriv/cmo.adoc", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Traps > Illegal-Instruction and Virtual-Instruction Exceptions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 246, + 249 + ] + }, + { + "chunk_id": "chunk_91674397", + "text": "Cache-block prefetch instructions raise neither illegal-instruction exceptions nor virtual-instruction exceptions.", + "source_file": "src/unpriv/cmo.adoc", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Traps > Illegal-Instruction and Virtual-Instruction Exceptions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 251, + 252 + ] + }, + { + "chunk_id": "chunk_ba012004", + "text": "The PMP access control bits shall be the same for all physical addresses in the cache block, and if write permission is granted by the PMP access control bits, read permission shall also be granted", + "source_file": "src/unpriv/cmo.adoc", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Traps > Page-Fault, Guest-Page-Fault, and Access-Fault Exceptions", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 262, + 264 + ] + }, + { + "chunk_id": "chunk_0ba97f21", + "text": "The PMAs shall be the same for all physical addresses in the cache block, and if write permission is granted by the supported access type PMAs, read permission shall also be granted", + "source_file": "src/unpriv/cmo.adoc", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Traps > Page-Fault, Guest-Page-Fault, and Access-Fault Exceptions", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 266, + 268 + ] + }, + { + "chunk_id": "chunk_bdba7395", + "text": "If the above constraints are not met, the behavior of a CBO instruction is UNSPECIFIED.", + "source_file": "src/unpriv/cmo.adoc", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Traps > Page-Fault, Guest-Page-Fault, and Access-Fault Exceptions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 270, + 271 + ] + }, + { + "chunk_id": "chunk_3aa7bb28", + "text": "Main memory regions are required to support accesses by cache-block zero instructions; however, I/O regions may specify whether accesses by cache-block zero instructions are supported.", + "source_file": "src/unpriv/cmo.adoc", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Traps > Page-Fault, Guest-Page-Fault, and Access-Fault Exceptions", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 273, + 276 + ] + }, + { + "chunk_id": "chunk_bc844375", + "text": "If neither a load instruction nor store instruction is permitted to access the physical addresses, but an instruction fetch is permitted to access the physical addresses, whether a cache-block management instruction is permitted to access the cache block is UNSPECIFIED.", + "source_file": "src/unpriv/cmo.adoc", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Traps > Page-Fault, Guest-Page-Fault, and Access-Fault Exceptions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 278, + 288 + ] + }, + { + "chunk_id": "chunk_e9b47295", + "text": "If access to the cache block is not permitted, a cache-block management instruction raises a store page-fault or store guest-page-fault exception if address translation does not permit any access or raises a store access-fault exception otherwise.", + "source_file": "src/unpriv/cmo.adoc", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Traps > Page-Fault, Guest-Page-Fault, and Access-Fault Exceptions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 278, + 288 + ] + }, + { + "chunk_id": "chunk_15e20446", + "text": "During address translation, the instruction also checks the accessed bit and may either raise an exception or set the bit as required.", + "source_file": "src/unpriv/cmo.adoc", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Traps > Page-Fault, Guest-Page-Fault, and Access-Fault Exceptions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 278, + 288 + ] + }, + { + "chunk_id": "chunk_7ddf3070", + "text": "A cache-block zero instruction is permitted to access the specified cache block whenever a store instruction is permitted to access the corresponding physical addresses and when the PMAs indicate that cache-block zero instructions are a supported access type.", + "source_file": "src/unpriv/cmo.adoc", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Traps > Page-Fault, Guest-Page-Fault, and Access-Fault Exceptions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 290, + 298 + ] + }, + { + "chunk_id": "chunk_4661739b", + "text": "If access to the cache block is not permitted, a cache-block zero instruction raises a store page-fault or store guest-page-fault exception if address translation does not permit write access or raises a store access-fault exception otherwise.", + "source_file": "src/unpriv/cmo.adoc", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Traps > Page-Fault, Guest-Page-Fault, and Access-Fault Exceptions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 290, + 298 + ] + }, + { + "chunk_id": "chunk_cd91ad39", + "text": "During address translation, the instruction also checks the accessed and dirty bits and may either raise an exception or set the bits as required.", + "source_file": "src/unpriv/cmo.adoc", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Traps > Page-Fault, Guest-Page-Fault, and Access-Fault Exceptions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 290, + 298 + ] + }, + { + "chunk_id": "chunk_18de9b48", + "text": "If access to the cache block is not permitted, a cache-block prefetch instruction does not raise any exceptions and shall not access any caches or memory.", + "source_file": "src/unpriv/cmo.adoc", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Traps > Page-Fault, Guest-Page-Fault, and Access-Fault Exceptions", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 300, + 306 + ] + }, + { + "chunk_id": "chunk_afcc32a5", + "text": "During address translation, the instruction does not check the accessed and dirty bits and neither raises an exception nor sets the bits.", + "source_file": "src/unpriv/cmo.adoc", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Traps > Page-Fault, Guest-Page-Fault, and Access-Fault Exceptions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 300, + 306 + ] + }, + { + "chunk_id": "chunk_28d4d64b", + "text": "CMO instructions do not generate address-misaligned exceptions.", + "source_file": "src/unpriv/cmo.adoc", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Traps > Address-Misaligned Exceptions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 314, + 315 + ] + }, + { + "chunk_id": "chunk_2543dec1", + "text": "Unless otherwise defined by the debug architecture specification, the behavior of trigger modules with respect to CMO instructions is UNSPECIFIED.", + "source_file": "src/unpriv/cmo.adoc", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Traps > Breakpoint Exceptions and Debug Mode Entry", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 319, + 320 + ] + }, + { + "chunk_id": "chunk_767b8f61", + "text": "For the purposes of writing the `mtinst` or `htinst` register on a trap, the following standard transformation is defined for cache-block management instructions and cache-block zero instructions:", + "source_file": "src/unpriv/cmo.adoc", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Traps > Hypervisor Extension", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 324, + 327 + ] + }, + { + "chunk_id": "chunk_9981bf2a", + "text": "The `operation` field corresponds to the 12 most significant bits of the trapping instruction.", + "source_file": "src/unpriv/cmo.adoc", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Traps > Hypervisor Extension", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 340, + 341 + ] + }, + { + "chunk_id": "chunk_34f5dcaf", + "text": "Other general cache characteristics may also be specified in the discovery mechanism.", + "source_file": "src/unpriv/cmo.adoc", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Software Discovery", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 361, + 362 + ] + }, + { + "chunk_id": "chunk_f9fbcf96", + "text": "The x{csrname} registers control CBO instruction execution based on the current privilege mode and the state of the appropriate CSRs, as detailed below.", + "source_file": "src/unpriv/cmo.adoc", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > CSR controls for CMO instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 367, + 368 + ] + }, + { + "chunk_id": "chunk_97ffe78d", + "text": "A `CBO.INVAL` instruction executes or raises either an illegal-instruction exception or a virtual-instruction exception based on the state of the `x{csrname}.CBIE` fields:", + "source_file": "src/unpriv/cmo.adoc", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > CSR controls for CMO instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 370, + 373 + ] + }, + { + "chunk_id": "chunk_0e5171b7", + "text": "A `CBO.CLEAN` or `CBO.FLUSH` instruction executes or raises an illegal-instruction or virtual-instruction exception based on the state of the `x{csrname}.CBCFE` bits:", + "source_file": "src/unpriv/cmo.adoc", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > CSR controls for CMO instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 408, + 411 + ] + }, + { + "chunk_id": "chunk_895a12b5", + "text": "Finally, a `CBO.ZERO` instruction executes or raises an illegal-instruction or virtual-instruction exception based on the state of the `x{csrname}.CBZE` bits:", + "source_file": "src/unpriv/cmo.adoc", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > CSR controls for CMO instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 436, + 438 + ] + }, + { + "chunk_id": "chunk_4ede1bb0", + "text": "The CBIE/CBCFE/CBZE fields in each `x{csrname}` register do not affect the read and write behavior of the same fields in the other `x{csrname}` registers.", + "source_file": "src/unpriv/cmo.adoc", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > CSR controls for CMO instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 463, + 465 + ] + }, + { + "chunk_id": "chunk_d81e9d78", + "text": "Each `x{csrname}` register is WARL; however, software should determine the legal values from the execution environment discovery mechanism.", + "source_file": "src/unpriv/cmo.adoc", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > CSR controls for CMO instructions", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 467, + 468 + ] + }, + { + "chunk_id": "chunk_00a69760", + "text": "An implementation may update the bytes in any order and with any granularity and atomicity, including individual bytes.", + "source_file": "src/unpriv/cmo.adoc", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Extensions > Cache-Block Zero Instructions", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 541, + 543 + ] + }, + { + "chunk_id": "chunk_693f42c3", + "text": "These instructions operate on the cache block whose effective address is the sum of the base address specified in rs1 and the sign-extended offset encoded in imm[11:0], where imm[4:0] shall equal `0b00000`.", + "source_file": "src/unpriv/cmo.adoc", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Extensions > Cache-Block Prefetch Instructions", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 574, + 578 + ] + }, + { + "chunk_id": "chunk_ec901148", + "text": "The offset operand may be omitted; otherwise, any expression that computes the offset shall evaluate to zero.", + "source_file": "src/unpriv/cmo.adoc", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > cbo.clean", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 632, + 636 + ] + }, + { + "chunk_id": "chunk_8e913bcc", + "text": "On faults, the faulting virtual address is considered to be the value in rs1, rather than the base address of the cache block.", + "source_file": "src/unpriv/cmo.adoc", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > cbo.flush", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 661, + 666 + ] + }, + { + "chunk_id": "chunk_71e6f59d", + "text": "The assembly offset operand may be omitted.", + "source_file": "src/unpriv/cmo.adoc", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > cbo.flush", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 668, + 669 + ] + }, + { + "chunk_id": "chunk_457bb6ed", + "text": "If it isn't then any expression that computes the offset shall evaluate to zero.", + "source_file": "src/unpriv/cmo.adoc", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > cbo.flush", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 668, + 669 + ] + }, + { + "chunk_id": "chunk_18780dda", + "text": "On faults, the faulting virtual address is considered to be the value in rs1, rather than the base address of the cache block.", + "source_file": "src/unpriv/cmo.adoc", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > cbo.inval", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 694, + 699 + ] + }, + { + "chunk_id": "chunk_21893a48", + "text": "Depending on CSR programming, the instruction may perform a flush operation instead of an invalidate operation.", + "source_file": "src/unpriv/cmo.adoc", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > cbo.inval", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 701, + 702 + ] + }, + { + "chunk_id": "chunk_21d81d84", + "text": "The assembly offset operand may be omitted.", + "source_file": "src/unpriv/cmo.adoc", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > cbo.inval", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 704, + 705 + ] + }, + { + "chunk_id": "chunk_501d0fd9", + "text": "If it isn't then any expression that computes the offset shall evaluate to zero.", + "source_file": "src/unpriv/cmo.adoc", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > cbo.inval", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 704, + 705 + ] + }, + { + "chunk_id": "chunk_225a2730", + "text": "On faults, the faulting virtual address is considered to be the value in rs1, rather than the base address of the cache block.", + "source_file": "src/unpriv/cmo.adoc", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > cbo.zero", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 730, + 735 + ] + }, + { + "chunk_id": "chunk_3a72bf01", + "text": "An implementation may or may not update the entire set of bytes atomically.", + "source_file": "src/unpriv/cmo.adoc", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > cbo.zero", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 730, + 735 + ] + }, + { + "chunk_id": "chunk_da05c2dc", + "text": "The assembly offset operand may be omitted.", + "source_file": "src/unpriv/cmo.adoc", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > cbo.zero", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 737, + 739 + ] + }, + { + "chunk_id": "chunk_1b10ed25", + "text": "If it isn't then any expression that computes the offset shall evaluate to zero.", + "source_file": "src/unpriv/cmo.adoc", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > cbo.zero", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 737, + 739 + ] + }, + { + "chunk_id": "chunk_34be1a43", + "text": "A *prefetch.i* instruction indicates to hardware that the cache block whose effective address is the sum of the base address specified in rs1 and the sign-extended offset encoded in imm[11:0], where imm[4:0] equals `0b00000`, is likely to be accessed by an instruction fetch in the near future.", + "source_file": "src/unpriv/cmo.adoc", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > prefetch.i", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 766, + 770 + ] + } + ] + }, + { + "file": "src/unpriv/d-st-ext.adoc", + "chunks": [ + { + "chunk_id": "chunk_6aea78ce", + "text": "The D extension widens the 32 floating-point registers, `f0-f31`, to 64 bits (FLEN=64 in ).", + "source_file": "src/unpriv/d-st-ext.adoc", + "section": "Preamble > \"D\" Extension for Double-Precision Floating-Point, Version 2.2 > D Register State", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 12, + 15 + ] + }, + { + "chunk_id": "chunk_fdcb2901", + "text": "The `f` registers can now hold either 32-bit or 64-bit floating-point values as described below in .", + "source_file": "src/unpriv/d-st-ext.adoc", + "section": "Preamble > \"D\" Extension for Double-Precision Floating-Point, Version 2.2 > D Register State", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 12, + 15 + ] + }, + { + "chunk_id": "chunk_31603a1b", + "text": "When multiple floating-point precisions are supported, then valid values of narrower n-bit types, n \"D\" Extension for Double-Precision Floating-Point, Version 2.2 > D Register State > NaN Boxing of Narrower Values", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 22, + 27 + ] + }, + { + "chunk_id": "chunk_6ecde738", + "text": "The upper bits of a valid NaN-boxed value must be all 1s.", + "source_file": "src/unpriv/d-st-ext.adoc", + "section": "Preamble > \"D\" Extension for Double-Precision Floating-Point, Version 2.2 > D Register State > NaN Boxing of Narrower Values", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 22, + 27 + ] + }, + { + "chunk_id": "chunk_556104c7", + "text": "Valid NaN-boxed n-bit values therefore appear as negative quiet NaNs (qNaNs) when viewed as any wider m-bit value, n < m {le} FLEN.", + "source_file": "src/unpriv/d-st-ext.adoc", + "section": "Preamble > \"D\" Extension for Double-Precision Floating-Point, Version 2.2 > D Register State > NaN Boxing of Narrower Values", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 22, + 27 + ] + }, + { + "chunk_id": "chunk_4614bfa3", + "text": "Any operation that writes a narrower result to an 'f' register must write all 1s to the uppermost FLEN-n bits to yield a legal NaN-boxedvalue.", + "source_file": "src/unpriv/d-st-ext.adoc", + "section": "Preamble > \"D\" Extension for Double-Precision Floating-Point, Version 2.2 > D Register State > NaN Boxing of Narrower Values", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 22, + 27 + ] + }, + { + "chunk_id": "chunk_2c0ef9fa", + "text": "Floating-point n-bit transfer operations move external values held in the IEEE 754-2008 formats into and out of the `f` registers, and comprise floating-point loads and stores (FLn/FSn) and floating-point move instructions (FMV.n.X/FMV.X.n). A narrower n-bit transfer, n \"D\" Extension for Double-Precision Floating-Point, Version 2.2 > D Register State > NaN Boxing of Narrower Values", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 29, + 38 + ] + }, + { + "chunk_id": "chunk_c75d483f", + "text": "If so, the n least-significant bits of the input are used as the input value, otherwise the input value is treated as an n-bit canonical NaN.", + "source_file": "src/unpriv/d-st-ext.adoc", + "section": "Preamble > \"D\" Extension for Double-Precision Floating-Point, Version 2.2 > D Register State > NaN Boxing of Narrower Values", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 40, + 47 + ] + }, + { + "chunk_id": "chunk_dc48bb74", + "text": "The FLD instruction loads a double-precision floating-point value from memory into floating-point register rd. FSD stores a double-precision value from the floating-point registers to memory.", + "source_file": "src/unpriv/d-st-ext.adoc", + "section": "Preamble > \"D\" Extension for Double-Precision Floating-Point, Version 2.2 > D Register State > Double-Precision Load and Store Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 51, + 54 + ] + }, + { + "chunk_id": "chunk_95a9506d", + "text": "FLD and FSD are only guaranteed to execute atomically if the effective address is naturally aligned and XLEN{ge}64.", + "source_file": "src/unpriv/d-st-ext.adoc", + "section": "Preamble > \"D\" Extension for Double-Precision Floating-Point, Version 2.2 > D Register State > Double-Precision Load and Store Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 60, + 62 + ] + }, + { + "chunk_id": "chunk_5653d8f5", + "text": "FLD and FSD do not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved.", + "source_file": "src/unpriv/d-st-ext.adoc", + "section": "Preamble > \"D\" Extension for Double-Precision Floating-Point, Version 2.2 > D Register State > Double-Precision Load and Store Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 64, + 66 + ] + }, + { + "chunk_id": "chunk_0bc742e7", + "text": "The double-precision floating-point computational instructions are defined analogously to their single-precision counterparts, but operate on double-precision operands and produce double-precision results.", + "source_file": "src/unpriv/d-st-ext.adoc", + "section": "Preamble > \"D\" Extension for Double-Precision Floating-Point, Version 2.2 > D Register State > Double-Precision Floating-Point Computational Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 70, + 73 + ] + }, + { + "chunk_id": "chunk_0931643d", + "text": "Floating-point-to-integer and integer-to-floating-point conversion instructions are encoded in the OP-FP major opcode space. FCVT.W.D or FCVT.L.D converts a double-precision floating-point number in floating-point register rs1 to a signed 32-bit or 64-bit integer, respectively, in integer register rd. FCVT.D.W or FCVT.D.L converts a 32-bit or 64-bit signed integer, respectively, in integer register rs1 into a double-precision floating-point number in floating-point register rd. FCVT.WU.D, FCVT.LU.D, FCVT.D.WU, and FCVT.D.LU variants convert to or from unsigned integer values.", + "source_file": "src/unpriv/d-st-ext.adoc", + "section": "Preamble > \"D\" Extension for Double-Precision Floating-Point, Version 2.2 > D Register State > Double-Precision Floating-Point Conversion and Move Instructions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 81, + 93 + ] + }, + { + "chunk_id": "chunk_5c3d0e09", + "text": "For RV64, FCVT.W[U].D sign-extends the 32-bit result. FCVT.L[U].D and FCVT.D.L[U] are RV64-only instructions.", + "source_file": "src/unpriv/d-st-ext.adoc", + "section": "Preamble > \"D\" Extension for Double-Precision Floating-Point, Version 2.2 > D Register State > Double-Precision Floating-Point Conversion and Move Instructions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 81, + 93 + ] + }, + { + "chunk_id": "chunk_6818df56", + "text": "The range of valid inputs for FCVT.int.D and the behavior for invalid inputs are the same as for FCVT.int.S.", + "source_file": "src/unpriv/d-st-ext.adoc", + "section": "Preamble > \"D\" Extension for Double-Precision Floating-Point, Version 2.2 > D Register State > Double-Precision Floating-Point Conversion and Move Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 81, + 93 + ] + }, + { + "chunk_id": "chunk_2330def6", + "text": "All floating-point to integer and integer to floating-point conversion instructions round according to the rm field.", + "source_file": "src/unpriv/d-st-ext.adoc", + "section": "Preamble > \"D\" Extension for Double-Precision Floating-Point, Version 2.2 > D Register State > Double-Precision Floating-Point Conversion and Move Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 95, + 97 + ] + }, + { + "chunk_id": "chunk_1878cf7c", + "text": "The double-precision to single-precision and single-precision to double-precision conversion instructions, FCVT.S.D and FCVT.D.S, are encoded in the OP-FP major opcode space and both the source and destination are floating-point registers.", + "source_file": "src/unpriv/d-st-ext.adoc", + "section": "Preamble > \"D\" Extension for Double-Precision Floating-Point, Version 2.2 > D Register State > Double-Precision Floating-Point Conversion and Move Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 103, + 111 + ] + }, + { + "chunk_id": "chunk_6a39c27f", + "text": "The rs2 field encodes the datatype of the source, and the fmt field encodes the datatype of the destination. FCVT.S.D rounds according to the RM field; FCVT.D.S will never round.", + "source_file": "src/unpriv/d-st-ext.adoc", + "section": "Preamble > \"D\" Extension for Double-Precision Floating-Point, Version 2.2 > D Register State > Double-Precision Floating-Point Conversion and Move Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 103, + 111 + ] + }, + { + "chunk_id": "chunk_eb9f8dfe", + "text": "Floating-point to floating-point sign-injection instructions, FSGNJ.D, FSGNJN.D, and FSGNJX.D are defined analogously to the single-precision sign-injection instruction. //FSGNJ.D, FSGNJN.D, and FSGNJX.D", + "source_file": "src/unpriv/d-st-ext.adoc", + "section": "Preamble > \"D\" Extension for Double-Precision Floating-Point, Version 2.2 > D Register State > Double-Precision Floating-Point Conversion and Move Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 117, + 121 + ] + }, + { + "chunk_id": "chunk_f5028b11", + "text": "For XLEN{ge}64 only, instructions are provided to move bit patterns between the floating-point and integer registers. FMV.X.D moves the double-precision value in floating-point register rs1 to a representation in the IEEE 754-2008 encoding in integer register rd. FMV.D.X moves the double-precision value encoded in the IEEE 754-2008 encoding from the integer register rs1 to the floating-point register rd.", + "source_file": "src/unpriv/d-st-ext.adoc", + "section": "Preamble > \"D\" Extension for Double-Precision Floating-Point, Version 2.2 > D Register State > Double-Precision Floating-Point Conversion and Move Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 126, + 132 + ] + }, + { + "chunk_id": "chunk_c85c11f0", + "text": "FMV.X.D and FMV.D.X do not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved.", + "source_file": "src/unpriv/d-st-ext.adoc", + "section": "Preamble > \"D\" Extension for Double-Precision Floating-Point, Version 2.2 > D Register State > Double-Precision Floating-Point Conversion and Move Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 134, + 136 + ] + }, + { + "chunk_id": "chunk_c8703113", + "text": "The double-precision floating-point classify instruction, FCLASS.D, is defined analogously to its single-precision counterpart, but operates on double-precision operands.", + "source_file": "src/unpriv/d-st-ext.adoc", + "section": "Preamble > \"D\" Extension for Double-Precision Floating-Point, Version 2.2 > D Register State > Double-Precision Floating-Point Classify Instruction", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 156, + 160 + ] + } + ] + }, + { + "file": "src/unpriv/f-st-ext.adoc", + "chunks": [ + { + "chunk_id": "chunk_1991a1a4", + "text": "The F extension depends on the \"Zicsr\" extension for control and status register access.", + "source_file": "src/unpriv/f-st-ext.adoc", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 3, + 7 + ] + }, + { + "chunk_id": "chunk_b615d00e", + "text": "The F extension adds 32 floating-point registers, `f0-f31`, each 32 bits wide, and a floating-point control and status register `fcsr`, which contains the operating mode and exception status of the floating-point unit.", + "source_file": "src/unpriv/f-st-ext.adoc", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 11, + 20 + ] + }, + { + "chunk_id": "chunk_72d74173", + "text": "This additional state is shown in .", + "source_file": "src/unpriv/f-st-ext.adoc", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 11, + 20 + ] + }, + { + "chunk_id": "chunk_2e164b71", + "text": "We use the term FLEN to describe the width of the floating-point registers in the RISC-V ISA, and FLEN=32 for the F single-precision floating-point extension.", + "source_file": "src/unpriv/f-st-ext.adoc", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 11, + 20 + ] + }, + { + "chunk_id": "chunk_f67b35ab", + "text": "Most floating-point instructions operate on values in the floating-point register file.", + "source_file": "src/unpriv/f-st-ext.adoc", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 11, + 20 + ] + }, + { + "chunk_id": "chunk_b1d800b5", + "text": "Floating-point load and store instructions transfer floating-point values between registers and memory.", + "source_file": "src/unpriv/f-st-ext.adoc", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 11, + 20 + ] + }, + { + "chunk_id": "chunk_95bd5a0f", + "text": "Instructions to transfer values to and from the integer register file are also provided.", + "source_file": "src/unpriv/f-st-ext.adoc", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 11, + 20 + ] + }, + { + "chunk_id": "chunk_0cc999d8", + "text": "The floating-point control and status register, `fcsr`, is a RISC-V control and status register (CSR).", + "source_file": "src/unpriv/f-st-ext.adoc", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Floating-Point Control and Status Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 67, + 71 + ] + }, + { + "chunk_id": "chunk_b53db82e", + "text": "It is a 32-bit read/write register that selects the dynamic rounding mode for floating-point arithmetic operations and holds the accrued exception flags, as shown in .", + "source_file": "src/unpriv/f-st-ext.adoc", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Floating-Point Control and Status Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 67, + 71 + ] + }, + { + "chunk_id": "chunk_79ad7d38", + "text": "The `fcsr` register can be read and written with the FRCSR and FSCSR instructions, which are assembler pseudoinstructions built on the underlying CSR access instructions. FRCSR reads `fcsr` by copying it into integer register rd. FSCSR swaps the value in `fcsr` by copying the original value into integer register rd, and then writing a new value obtained from integer register rs1 into `fcsr`.", + "source_file": "src/unpriv/f-st-ext.adoc", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Floating-Point Control and Status Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 77, + 82 + ] + }, + { + "chunk_id": "chunk_e3f82d9d", + "text": "The fields within the `fcsr` can also be accessed individually through different CSR addresses, and separate assembler pseudoinstructions are defined for these accesses.", + "source_file": "src/unpriv/f-st-ext.adoc", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Floating-Point Control and Status Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 84, + 93 + ] + }, + { + "chunk_id": "chunk_868eec54", + "text": "The FRRM instruction reads the Rounding Mode field `frm` (`fcsr` bits 7--5) and copies it into the least-significant three bits of integer register rd, with zero in all other bits. FSRM swaps the value in `frm` by copying the original value into integer register rd, and then writing a new value obtained from the three least-significant bits of integer register rs1 into `frm`. FRFLAGS and FSFLAGS are defined analogously for the Accrued Exception Flags field `fflags` (`fcsr` bits 4--0).", + "source_file": "src/unpriv/f-st-ext.adoc", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Floating-Point Control and Status Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 84, + 93 + ] + }, + { + "chunk_id": "chunk_444044d0", + "text": "Bits 31--8 of the `fcsr` are reserved for other standard extensions.", + "source_file": "src/unpriv/f-st-ext.adoc", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Floating-Point Control and Status Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 95, + 99 + ] + }, + { + "chunk_id": "chunk_bb9e1a1c", + "text": "If these extensions are not present, implementations shall ignore writes to these bits and supply a zero value when read.", + "source_file": "src/unpriv/f-st-ext.adoc", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Floating-Point Control and Status Register", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 95, + 99 + ] + }, + { + "chunk_id": "chunk_9140a189", + "text": "Standard software should preserve the contents of these bits.", + "source_file": "src/unpriv/f-st-ext.adoc", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Floating-Point Control and Status Register", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 95, + 99 + ] + }, + { + "chunk_id": "chunk_494a48e8", + "text": "Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in `frm`.", + "source_file": "src/unpriv/f-st-ext.adoc", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Floating-Point Control and Status Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 101, + 108 + ] + }, + { + "chunk_id": "chunk_a9563045", + "text": "Rounding modes are encoded as shown in . A value of 111 in the instruction's rm field selects the dynamic rounding mode held in `frm`.", + "source_file": "src/unpriv/f-st-ext.adoc", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Floating-Point Control and Status Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 101, + 108 + ] + }, + { + "chunk_id": "chunk_16d46055", + "text": "The behavior of floating-point instructions that depend on rounding mode when executed with a reserved rounding mode is reserved, including both static reserved rounding modes (101-110) and dynamic reserved rounding modes (101-111).", + "source_file": "src/unpriv/f-st-ext.adoc", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Floating-Point Control and Status Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 101, + 108 + ] + }, + { + "chunk_id": "chunk_d255edd5", + "text": "Some instructions, including widening conversions, have the rm field but are nevertheless mathematically unaffected by the rounding mode; software should set their rm field to RNE (000) but implementations must treat the rm field as usual (in particular, with regard to decoding legal vs. reserved encodings).", + "source_file": "src/unpriv/f-st-ext.adoc", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Floating-Point Control and Status Register", + "confidence": "very_high", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 101, + 108 + ] + }, + { + "chunk_id": "chunk_2e4cd33b", + "text": "The accrued exception flags indicate the exception conditions that have arisen on any floating-point arithmetic instruction since the field was last reset by software, as shown in .", + "source_file": "src/unpriv/f-st-ext.adoc", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Floating-Point Control and Status Register", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 125, + 130 + ] + }, + { + "chunk_id": "chunk_a4c47ee2", + "text": "The base RISC-V ISA does not support generating a trap on the setting of a floating-point exception flag.", + "source_file": "src/unpriv/f-st-ext.adoc", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Floating-Point Control and Status Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 125, + 130 + ] + }, + { + "chunk_id": "chunk_3a461859", + "text": "Except when otherwise stated, if the result of a floating-point operation is NaN, it is the canonical NaN.", + "source_file": "src/unpriv/f-st-ext.adoc", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > NaN Generation and Propagation", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 147, + 153 + ] + }, + { + "chunk_id": "chunk_06458eda", + "text": "The canonical NaN has a positive sign and all significand bits clear except the MSB, a.k.a. the quiet bit.", + "source_file": "src/unpriv/f-st-ext.adoc", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > NaN Generation and Propagation", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 147, + 153 + ] + }, + { + "chunk_id": "chunk_f938b6e7", + "text": "For single-precision floating-point, this corresponds to the pattern `0x7fc00000`.", + "source_file": "src/unpriv/f-st-ext.adoc", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > NaN Generation and Propagation", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 147, + 153 + ] + }, + { + "chunk_id": "chunk_a4b85a69", + "text": "Operations on subnormal numbers are handled in accordance with IEEE 754-2008.", + "source_file": "src/unpriv/f-st-ext.adoc", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Subnormal Arithmetic", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 159, + 162 + ] + }, + { + "chunk_id": "chunk_17d82abe", + "text": "In the parlance of IEEE 754-2008, tininess is detected after rounding.", + "source_file": "src/unpriv/f-st-ext.adoc", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Subnormal Arithmetic", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 164, + 166 + ] + }, + { + "chunk_id": "chunk_71f88c81", + "text": "The FLW instruction loads a single-precision floating-point value from memory into floating-point register rd. FSW stores a single-precision value from floating-point register rs2 to memory.", + "source_file": "src/unpriv/f-st-ext.adoc", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Load and Store Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 170, + 171 + ] + }, + { + "chunk_id": "chunk_c2ab8c6b", + "text": "FLW and FSW are only guaranteed to execute atomically if the effective address is naturally aligned.", + "source_file": "src/unpriv/f-st-ext.adoc", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Load and Store Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 177, + 179 + ] + }, + { + "chunk_id": "chunk_cd3fb6b8", + "text": "FLW and FSW do not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved.", + "source_file": "src/unpriv/f-st-ext.adoc", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Load and Store Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 181, + 182 + ] + }, + { + "chunk_id": "chunk_5e5094c2", + "text": "As described in , the execution environment defines whether misaligned floating-point loads and stores are handled invisibly or raise a contained or fatal trap.", + "source_file": "src/unpriv/f-st-ext.adoc", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Load and Store Instructions", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 184, + 185 + ] + }, + { + "chunk_id": "chunk_326f8d50", + "text": "Floating-point arithmetic instructions with one or two source operands use the R-type format with the OP-FP major opcode. FADD.S and FMUL.S perform single-precision floating-point addition and multiplication respectively, between rs1 and rs2. FSUB.S performs the single-precision floating-point subtraction of rs2 from rs1. FDIV.S performs the single-precision floating-point division of rs1 by rs2. FSQRT.S computes the square root of rs1.", + "source_file": "src/unpriv/f-st-ext.adoc", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Computational Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 190, + 194 + ] + }, + { + "chunk_id": "chunk_ce8cdf68", + "text": "The 2-bit floating-point format field fmt is encoded as shown in .", + "source_file": "src/unpriv/f-st-ext.adoc", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Computational Instructions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 196, + 198 + ] + }, + { + "chunk_id": "chunk_a84ac5e3", + "text": "It is set to S (00) for all instructions in the F extension.", + "source_file": "src/unpriv/f-st-ext.adoc", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Computational Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 196, + 198 + ] + }, + { + "chunk_id": "chunk_ff1dc099", + "text": "All floating-point operations that perform rounding can select the rounding mode using the rm field with the encoding shown in .", + "source_file": "src/unpriv/f-st-ext.adoc", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Computational Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 211, + 214 + ] + }, + { + "chunk_id": "chunk_0d0ae83c", + "text": "Floating-point minimum-number and maximum-number instructions FMIN.S and FMAX.S write, respectively, the smaller or larger of rs1 and rs2 to rd.", + "source_file": "src/unpriv/f-st-ext.adoc", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Computational Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "range", + "line_range": [ + 216, + 220 + ] + }, + { + "chunk_id": "chunk_43317650", + "text": "For the purposes of these instructions only, the value \u22120.0 is considered to be less than the value +0.0.", + "source_file": "src/unpriv/f-st-ext.adoc", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Computational Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "range", + "line_range": [ + 216, + 220 + ] + }, + { + "chunk_id": "chunk_d32b33b7", + "text": "Floating-point fused multiply-add instructions require a new standard instruction format. R4-type instructions specify three source registers (rs1, rs2, and rs3) and a destination register (rd).", + "source_file": "src/unpriv/f-st-ext.adoc", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Computational Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 227, + 229 + ] + }, + { + "chunk_id": "chunk_3ba124e7", + "text": "This format is only used by the floating-point fused multiply-add instructions.", + "source_file": "src/unpriv/f-st-ext.adoc", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Computational Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 227, + 229 + ] + }, + { + "chunk_id": "chunk_5d1cc062", + "text": "FMADD.S multiplies the values in rs1 and rs2, adds the value in rs3, and writes the final result to rd. FMADD.S computes (rs1\u00d7rs2)+rs3.", + "source_file": "src/unpriv/f-st-ext.adoc", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Computational Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 231, + 234 + ] + }, + { + "chunk_id": "chunk_7d1ddcab", + "text": "FMSUB.S multiplies the values in rs1 and rs2, subtracts the value in rs3, and writes the final result to rd. FMSUB.S computes (rs1\u00d7rs2)\u2212rs3.", + "source_file": "src/unpriv/f-st-ext.adoc", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Computational Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 236, + 238 + ] + }, + { + "chunk_id": "chunk_2af17f24", + "text": "FNMSUB.S multiplies the values in rs1 and rs2, negates the product, adds the value in rs3, and writes the final result to rd. FNMSUB.S computes \u2212(rs1\u00d7rs2)+rs3.", + "source_file": "src/unpriv/f-st-ext.adoc", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Computational Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 240, + 241 + ] + }, + { + "chunk_id": "chunk_f2d14872", + "text": "FNMADD.S multiplies the values in rs1 and rs2, negates the product, subtracts the value in rs3, and writes the final result to rd. FNMADD.S computes \u2212(rs1\u00d7rs2)\u2212rs3.", + "source_file": "src/unpriv/f-st-ext.adoc", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Computational Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 243, + 244 + ] + }, + { + "chunk_id": "chunk_757afb3e", + "text": "The fused multiply-add instructions must set the invalid operation exception flag when the multiplicands are {inf} and zero, even when the addend is a quiet NaN.", + "source_file": "src/unpriv/f-st-ext.adoc", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Computational Instructions", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 250, + 252 + ] + }, + { + "chunk_id": "chunk_bad21167", + "text": "Floating-point-to-integer and integer-to-floating-point conversion instructions are encoded in the OP-FP major opcode space. FCVT.W.S or FCVT.L.S converts a floating-point number in floating-point register rs1 to a signed 32-bit or 64-bit integer, respectively, in integer register rd. FCVT.S.W or FCVT.S.L converts a 32-bit or 64-bit signed integer, respectively, in integer register rs1 into a floating-point number in floating-point register rd. FCVT.WU.S, FCVT.LU.S, FCVT.S.WU, and FCVT.S.LU variants convert to or from unsigned integer values.", + "source_file": "src/unpriv/f-st-ext.adoc", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Conversion and Move Instructions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 256, + 270 + ] + }, + { + "chunk_id": "chunk_b7d1643a", + "text": "For XLEN>32, FCVT.W[U].S sign-extends the 32-bit result to the destination register width. FCVT.L[U].S and FCVT.S.L[U] are RV64-only instructions.", + "source_file": "src/unpriv/f-st-ext.adoc", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Conversion and Move Instructions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 256, + 270 + ] + }, + { + "chunk_id": "chunk_d13667ad", + "text": "If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set. gives the range of valid inputs for FCVT.int.S and the behavior for invalid inputs.", + "source_file": "src/unpriv/f-st-ext.adoc", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Conversion and Move Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 256, + 270 + ] + }, + { + "chunk_id": "chunk_72f7ad4c", + "text": "All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, `x0`, which will never set any exception flags.", + "source_file": "src/unpriv/f-st-ext.adoc", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Conversion and Move Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 272, + 276 + ] + }, + { + "chunk_id": "chunk_70285fd6", + "text": "|Maximum valid input (after rounding) |2^31^\u22121 |2^32^\u22121 |2^63^\u22121 |2^64^\u22121", + "source_file": "src/unpriv/f-st-ext.adoc", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Conversion and Move Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "range", + "line_range": [ + 286, + 287 + ] + }, + { + "chunk_id": "chunk_81f8baf0", + "text": "|Output for out-of-range negative input |\u22122^31^ |0 |\u22122^63^ |0", + "source_file": "src/unpriv/f-st-ext.adoc", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Conversion and Move Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 289, + 290 + ] + }, + { + "chunk_id": "chunk_b943541a", + "text": "|Output for -{inf} |\u22122^31^ |0 |\u22122^63^ |0", + "source_file": "src/unpriv/f-st-ext.adoc", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Conversion and Move Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 292, + 293 + ] + }, + { + "chunk_id": "chunk_75c9707b", + "text": "|Output for out-of-range positive input |2^31^\u22121 |2^32^\u22121 |2^63^\u22121 |2^64^\u22121", + "source_file": "src/unpriv/f-st-ext.adoc", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Conversion and Move Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 295, + 296 + ] + }, + { + "chunk_id": "chunk_0b976431", + "text": "|Output for +{inf} or NaN |2^31^\u22121 |2^32^\u22121 |2^63^\u22121 |2^64^\u22121 |", + "source_file": "src/unpriv/f-st-ext.adoc", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Conversion and Move Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 298, + 300 + ] + }, + { + "chunk_id": "chunk_6e497bf8", + "text": "All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set.", + "source_file": "src/unpriv/f-st-ext.adoc", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Conversion and Move Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 302, + 305 + ] + }, + { + "chunk_id": "chunk_d4a1c607", + "text": "Floating-point to floating-point sign-injection instructions, FSGNJ.S, FSGNJN.S, and FSGNJX.S, produce a result that takes all bits except the sign bit from rs1.", + "source_file": "src/unpriv/f-st-ext.adoc", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Conversion and Move Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 311, + 321 + ] + }, + { + "chunk_id": "chunk_681d4ebc", + "text": "For FSGNJ, the result's sign bit is rs2's sign bit; for FSGNJN, the result's sign bit is the opposite of rs2's sign bit; and for FSGNJX, the sign bit is the XOR of the sign bits of rs1 and rs2.", + "source_file": "src/unpriv/f-st-ext.adoc", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Conversion and Move Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 311, + 321 + ] + }, + { + "chunk_id": "chunk_9f3245bb", + "text": "Sign-injection instructions do not set floating-point exception flags, nor do they canonicalize NaNs.", + "source_file": "src/unpriv/f-st-ext.adoc", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Conversion and Move Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 311, + 321 + ] + }, + { + "chunk_id": "chunk_92952ae5", + "text": "Instructions are provided to move bit patterns between the floating-point and integer registers. FMV.X.W moves the single-precision value in floating-point register rs1 represented in the IEEE 754-2008 encoding to the lower 32 bits of integer register rd.", + "source_file": "src/unpriv/f-st-ext.adoc", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Conversion and Move Instructions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 326, + 333 + ] + }, + { + "chunk_id": "chunk_11c338ae", + "text": "The bits are not modified in the transfer, and in particular, the payloads of non-canonical NaNs are preserved.", + "source_file": "src/unpriv/f-st-ext.adoc", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Conversion and Move Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 326, + 333 + ] + }, + { + "chunk_id": "chunk_785a50a5", + "text": "For RV64, the higher 32 bits of the destination register are filled with copies of the floating-point number's sign bit.", + "source_file": "src/unpriv/f-st-ext.adoc", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Conversion and Move Instructions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 326, + 333 + ] + }, + { + "chunk_id": "chunk_810b099e", + "text": "FMV.W.X moves the single-precision value encoded in the IEEE 754-2008 encoding from the lower 32 bits of integer register rs1 to the floating-point register rd.", + "source_file": "src/unpriv/f-st-ext.adoc", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Conversion and Move Instructions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 335, + 339 + ] + }, + { + "chunk_id": "chunk_f2d4eb2b", + "text": "The bits are not modified in the transfer, and in particular, the payloads of non-canonical NaNs are preserved.", + "source_file": "src/unpriv/f-st-ext.adoc", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Conversion and Move Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 335, + 339 + ] + }, + { + "chunk_id": "chunk_80a974f2", + "text": "FLT.S and FLE.S perform what IEEE 754-2008 refers to as signaling comparisons: that is, they set the invalid operation exception flag if either input is NaN. FEQ.S performs a quiet comparison: it only sets the invalid operation exception flag if either input is a signaling NaN.", + "source_file": "src/unpriv/f-st-ext.adoc", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Compare Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 354, + 360 + ] + }, + { + "chunk_id": "chunk_f2689ca4", + "text": "The FCLASS.S instruction examines the value in floating-point register rs1 and writes to integer register rd a 10-bit mask that indicates the class of the floating-point number.", + "source_file": "src/unpriv/f-st-ext.adoc", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Classify Instruction", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 367, + 375 + ] + }, + { + "chunk_id": "chunk_1dac62c1", + "text": "The format of the mask is described in .", + "source_file": "src/unpriv/f-st-ext.adoc", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Classify Instruction", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 367, + 375 + ] + }, + { + "chunk_id": "chunk_42a5c06a", + "text": "The corresponding bit in rd will be set if the property is true and clear otherwise.", + "source_file": "src/unpriv/f-st-ext.adoc", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Classify Instruction", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 367, + 375 + ] + }, + { + "chunk_id": "chunk_f826b56f", + "text": "All other bits in rd are cleared.", + "source_file": "src/unpriv/f-st-ext.adoc", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Classify Instruction", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 367, + 375 + ] + } + ] + }, + { + "file": "src/unpriv/m-st-ext.adoc", + "chunks": [ + { + "chunk_id": "chunk_29703e4e", + "text": "MUL performs an XLEN-bit\u00d7XLEN-bit multiplication of `rs1` by `rs2` and places the lower XLEN bits in the destination register. MULH, MULHU, and MULHSU perform the same multiplication but return the upper XLEN bits of the full 2\u00d7XLEN-bit product, for signed\u00d7signed, unsigned\u00d7unsigned, and `rs1`\u00d7unsigned `rs2` multiplication.", + "source_file": "src/unpriv/m-st-ext.adoc", + "section": "Preamble > \"M\" Extension for Integer Multiplication and Division, Version 2.0 > Multiplication Operations", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "range", + "line_range": [ + 17, + 23 + ] + }, + { + "chunk_id": "chunk_3835b90b", + "text": "If both the high and low bits of the same product are required, then the recommended code sequence is: `MULH[[S]U] rdh, rs1, rs2; MUL rdl, rs1, rs2` (source register specifiers must be in same order and `rdh` cannot be the same as `rs1` or `rs2`).", + "source_file": "src/unpriv/m-st-ext.adoc", + "section": "Preamble > \"M\" Extension for Integer Multiplication and Division, Version 2.0 > Multiplication Operations", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 17, + 23 + ] + }, + { + "chunk_id": "chunk_4e75dc79", + "text": "MULW is an RV64 instruction that multiplies the lower 32 bits of the source registers, placing the sign extension of the lower 32 bits of the result into the destination register.", + "source_file": "src/unpriv/m-st-ext.adoc", + "section": "Preamble > \"M\" Extension for Integer Multiplication and Division, Version 2.0 > Multiplication Operations", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 25, + 27 + ] + }, + { + "chunk_id": "chunk_e59c8ef2", + "text": "DIV and DIVU perform an XLEN bits by XLEN bits signed and unsigned integer division of `rs1` by `rs2`, rounding towards zero. REM and REMU provide the remainder of the corresponding division operation.", + "source_file": "src/unpriv/m-st-ext.adoc", + "section": "Preamble > \"M\" Extension for Integer Multiplication and Division, Version 2.0 > Multiplication Operations > Division Operations", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "range", + "line_range": [ + 37, + 40 + ] + }, + { + "chunk_id": "chunk_c6dabebb", + "text": "If both the quotient and remainder are required from the same division, the recommended code sequence is: `DIV[U] rdq, rs1, rs2; REM[U] rdr,` `rs1, rs2` (`rdq` cannot be the same as `rs1` or `rs2`).", + "source_file": "src/unpriv/m-st-ext.adoc", + "section": "Preamble > \"M\" Extension for Integer Multiplication and Division, Version 2.0 > Multiplication Operations > Division Operations", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 42, + 46 + ] + }, + { + "chunk_id": "chunk_553e68a0", + "text": "DIVW and DIVUW are RV64 instructions that divide the lower 32 bits of `rs1` by the lower 32 bits of `rs2`, treating them as signed and unsigned integers, placing the 32-bit quotient in `rd`, sign-extended to 64 bits. REMW and REMUW are RV64 instructions that provide the corresponding signed and unsigned remainder operations.", + "source_file": "src/unpriv/m-st-ext.adoc", + "section": "Preamble > \"M\" Extension for Integer Multiplication and Division, Version 2.0 > Multiplication Operations > Division Operations", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 48, + 55 + ] + }, + { + "chunk_id": "chunk_aaba239b", + "text": "Both REMW and REMUW always sign-extend the 32-bit result to 64 bits, including on a divide by zero.", + "source_file": "src/unpriv/m-st-ext.adoc", + "section": "Preamble > \"M\" Extension for Integer Multiplication and Division, Version 2.0 > Multiplication Operations > Division Operations", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 48, + 55 + ] + }, + { + "chunk_id": "chunk_d863e630", + "text": "The quotient of division by zero has all bits set, and the remainder of division by zero equals the dividend.", + "source_file": "src/unpriv/m-st-ext.adoc", + "section": "Preamble > \"M\" Extension for Integer Multiplication and Division, Version 2.0 > Multiplication Operations > Division Operations", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 57, + 63 + ] + }, + { + "chunk_id": "chunk_6d42e327", + "text": "Signed division overflow occurs only when the most-negative integer is divided by \u22121.", + "source_file": "src/unpriv/m-st-ext.adoc", + "section": "Preamble > \"M\" Extension for Integer Multiplication and Division, Version 2.0 > Multiplication Operations > Division Operations", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 57, + 63 + ] + } + ] + }, + { + "file": "src/unpriv/mm-explanatory.adoc", + "chunks": [ + { + "chunk_id": "chunk_fe45fafe", + "text": "This appendix should be treated as commentary; all normative material is provided in and in the rest of the main body of the ISA specification.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 3, + 11 + ] + }, + { + "chunk_id": "chunk_3d7fb806", + "text": "To facilitate the porting of code from other architectures, some hardware implementations may choose to implement the Ztso extension, which provides stricter RVTSO ordering semantics by default.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO?", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 36, + 45 + ] + }, + { + "chunk_id": "chunk_c9d8eaf3", + "text": "Each implementation must therefore choose whether to prioritize compatibility with RVTSO code (e.g., to facilitate porting from x86) or whether to instead prioritize compatibility with other RISC-V cores implementing RVWMO.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO?", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 36, + 45 + ] + }, + { + "chunk_id": "chunk_57e8e6f4", + "text": "However, these fences must remain present in the code if compatibility with non-Ztso implementations is desired.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO?", + "confidence": "very_high", + "parameter_class": "SW_rule", + "parameter_type": "binary", + "line_range": [ + 47, + 52 + ] + }, + { + "chunk_id": "chunk_266ffadd", + "text": "As a convention for this figure and for all figures that follow in this chapter, we assume that `s0-s2` are pre-set to the same value in all harts and that `s0` holds the address labeled `x`, `s1` holds `y`, and `s2` holds `z`, where `x`, `y`, and `z` are disjoint memory locations aligned to 8 byte boundaries.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Litmus Tests", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 57, + 66 + ] + }, + { + "chunk_id": "chunk_15fcb8c9", + "text": "However, in this example, the final value of `a0` in Hart 0 will never be 1 or 3; intuitively, the value 1 will no longer be visible at the time the load executes, and the value 3 will not yet be visible by the time the load executes.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Litmus Tests", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 97, + 105 + ] + }, + { + "chunk_id": "chunk_398406bc", + "text": "Preserved program order represents the subset of program order that must be respected within the global memory order.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Preserved Program Order and Global Memory Order", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 171, + 177 + ] + }, + { + "chunk_id": "chunk_e5c3042b", + "text": "Conceptually, events from the same hart that are ordered by preserved program order must appear in that order from the perspective of other harts and/or observers.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Preserved Program Order and Global Memory Order", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 171, + 177 + ] + }, + { + "chunk_id": "chunk_08477fb4", + "text": "Events from the same hart that are not ordered by preserved program order, on the other hand, may appear reordered from the perspective of other harts and/or observers.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Preserved Program Order and Global Memory Order", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 171, + 177 + ] + }, + { + "chunk_id": "chunk_b646fb5e", + "text": "Informally, the global memory order represents the order in which loads and stores perform.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Preserved Program Order and Global Memory Order", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 179, + 189 + ] + }, + { + "chunk_id": "chunk_837804ad", + "text": "In this sense, the global memory order also represents the contribution of the coherence protocol and/or the rest of the memory system to interleave the (possibly reordered) memory accesses being issued by each hart into a single total order agreed upon by all harts.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Preserved Program Order and Global Memory Order", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 179, + 189 + ] + }, + { + "chunk_id": "chunk_200fa231", + "text": "The order in which loads perform does not always directly correspond to the relative age of the values those two loads return.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Preserved Program Order and Global Memory Order", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 191, + 205 + ] + }, + { + "chunk_id": "chunk_0de93172", + "text": "This discrepancy captures (among other things) the reordering effects of buffering placed between the core and memory.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Preserved Program Order and Global Memory Order", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 191, + 205 + ] + }, + { + "chunk_id": "chunk_91d9bcf7", + "text": "To account for this, at the time each load performs, the value it returns is determined by the load value axiom, not just strictly by determining the most recent store to the same address in the global memory order, as described below.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Preserved Program Order and Global Memory Order", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 191, + 205 + ] + }, + { + "chunk_id": "chunk_bffe76cd", + "text": "Preserved program order is not required to respect the ordering of a store followed by a load to an overlapping address.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Load value axiom", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 221, + 228 + ] + }, + { + "chunk_id": "chunk_47e30fde", + "text": "Informally, the load may perform (return a value) by forwarding from the store while the store is still in the store buffer, and hence before the store itself performs (writes back to globally visible memory).", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Load value axiom", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 221, + 228 + ] + }, + { + "chunk_id": "chunk_8474558f", + "text": "When running this program on an implementation with store buffers, it is possible to arrive at the final outcome `a0=1, a1=0, a2=1, a3=0` as follows:", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Load value axiom", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 230, + 231 + ] + }, + { + "chunk_id": "chunk_7609f830", + "text": "Therefore, the memory model must be able to account for this behavior.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Load value axiom", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 270, + 270 + ] + }, + { + "chunk_id": "chunk_7ae2cdf8", + "text": "To put it another way, suppose the definition of preserved program order did include the following hypothetical rule: memory access a precedes memory access b in preserved program order (and hence also in the global memory order) if a precedes b in program order and a and b are accesses to the same memory location, a is a write, and b is a read.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Load value axiom", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 272, + 279 + ] + }, + { + "chunk_id": "chunk_81544ef3", + "text": "Otherwise, if (e) preceded (d), then (d) would be required to return the value 1. (This is a perfectly legal execution; it's just not the one in question) * (e) precedes (f): by rule X * (f) precedes (h): by rule * (h) precedes (a): by the load value axiom, as above.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Load value axiom", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 281, + 288 + ] + }, + { + "chunk_id": "chunk_6b9da712", + "text": "The global memory order must be a total order and cannot be cyclic, because a cycle would imply that every event in the cycle happens before itself, which is impossible.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Load value axiom", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 290, + 295 + ] + }, + { + "chunk_id": "chunk_f63968df", + "text": "Nevertheless, even if (b) precedes (a) and/or (f) precedes (e) in the global memory order, the only sensible possibility in this example is for (b) to return the value written by (a), and likewise for (f) and (e).", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Load value axiom", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 297, + 306 + ] + }, + { + "chunk_id": "chunk_257d9110", + "text": "If r and w are paired load and store operations generated by aligned LR and SC instructions in a hart h, s is a store to byte x, and r returns a value written by s, then s must precede w in the global memory order, and there can be no store from a hart other than h to byte x following s and preceding w in the global memory order.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Atomicity axiom", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 361, + 369 + ] + }, + { + "chunk_id": "chunk_a1876c4c", + "text": "Unlike architectures such as TSO, RISC-V atomics under RVWMO do not impose any ordering requirements by default.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Atomicity axiom", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 371, + 374 + ] + }, + { + "chunk_id": "chunk_2521ad7a", + "text": "These conceptually behave differently, in the following way. LR/SC behave as if the old value is brought up to the core, modified, and written back to memory, all while a reservation is held on that memory location. AMOs on the other hand conceptually behave as if they are performed directly in memory. AMOs are therefore inherently atomic, while LR/SC pairs are atomic in the slightly different sense that the memory location in question will not be modified by another hart during the time the original hart holds the reservation.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Atomicity axiom", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 376, + 384 + ] + }, + { + "chunk_id": "chunk_87d77c1b", + "text": "Likewise, scenarios in which stores from the same hart between an LR/SC pair actually overlap the memory location(s) referenced by the LR or SC are expected to be rare compared to scenarios where the intervening store may simply fall onto the same cache line.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Atomicity axiom", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 418, + 424 + ] + }, + { + "chunk_id": "chunk_37f42644", + "text": "[IMPORTANT] : No memory operation may be preceded in the global memory order by an infinite sequence of other memory operations.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Progress axiom", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 429, + 433 + ] + }, + { + "chunk_id": "chunk_ae0b1a68", + "text": "Implementations with non-coherent caches may have to provide some other mechanism to ensure the eventual visibility of all stores (or successors thereof) to all harts.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Progress axiom", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 448, + 452 + ] + }, + { + "chunk_id": "chunk_228e1b1a", + "text": "Same-address orderings where the latter is a store are straightforward: a load or store can never be reordered with a later store to an overlapping memory location.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 457, + 467 + ] + }, + { + "chunk_id": "chunk_d31b3468", + "text": "From a microarchitecture perspective, generally speaking, it is difficult or impossible to undo a speculatively reordered store if the speculation turns out to be invalid, so such behavior is simply disallowed by the model.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 457, + 467 + ] + }, + { + "chunk_id": "chunk_da5feae2", + "text": "Same-address orderings from a store to a later load, on the other hand, do not need to be enforced.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 457, + 467 + ] + }, + { + "chunk_id": "chunk_e79a418f", + "text": "As discussed in , this reflects the observable behavior of implementations that forward values from buffered stores to later loads.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 457, + 467 + ] + }, + { + "chunk_id": "chunk_800783f0", + "text": "Same-address load-load ordering requirements are far more subtle.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 469, + 481 + ] + }, + { + "chunk_id": "chunk_22c11ce5", + "text": "The basic requirement is that a younger load must not return a value that is older than a value returned by an older load in the same hart to the same address.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 469, + 481 + ] + }, + { + "chunk_id": "chunk_3d208768", + "text": "This is often known as \"CoRR\" (Coherence for Read-Read pairs), or as part of a broader \"coherence\" or \"sequential consistency per location\" requirement.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 469, + 481 + ] + }, + { + "chunk_id": "chunk_77dc127d", + "text": "Some architectures in the past have relaxed same-address load-load ordering, but in hindsight this is generally considered to complicate the programming model too much, and so RVWMO requires CoRR ordering to be enforced.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 469, + 481 + ] + }, + { + "chunk_id": "chunk_f748fd84", + "text": "[float=\"center\",align=\"center\",cols=\".^1a,.^1a\",frame=\"none\",grid=\"none\",options=\"noheader\"] .Litmus test MP+fence.w.w+fre-rfi-addr (outcome permitted) | | ! 2+!Hart 0 2+^!Hart 1 !!li t1, 1 !!li t2, 2 >!(a) !sw t1,0(s0) >!(d) !lw a0,0(s1) >!(b) !fence w, w >!(e) !sw t2,0(s1) >!(c) !sw t1,0(s1) >!(f) !lw a1,0(s1) ! ! >!(g) !xor t3,a1,a1 ! ! >!(h) !add s0,s0,t3 ! ! >!(i) !lw a2,0(s0) 4+^!Outcome: `a0=1`, `a1=2`, `a2=0` ! | ! //a! graphviz::images/graphviz/litmusmpfencewwfrirfiaddr.txt[] a! image::graphviz/litmusmpfencewwfrirfiaddr.png[] ! | Consider the litmus test of , which is one particular instance of the more general \"fri-rfi\" pattern.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)", + "confidence": "medium", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 486, + 512 + ] + }, + { + "chunk_id": "chunk_8c9f8eab", + "text": "From a microarchitectural perspective, outcome `a0=1`, `a1=2`, `a2=0` is legal (as are various other less subtle outcomes).", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 514, + 516 + ] + }, + { + "chunk_id": "chunk_cced40b8", + "text": "Intuitively, the following would produce the outcome in question:", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 514, + 516 + ] + }, + { + "chunk_id": "chunk_2a826d86", + "text": "(d) stalls (for whatever reason; perhaps it's stalled waiting for some other preceding instruction) * (e) executes and enters the store buffer (but does not yet drain to memory) * (f) executes and forwards from (e) in the store buffer * (g), (h), and (i) execute * (a) executes and drains to memory, (b) executes, and (c) executes and drains to memory * (d) unstalls and executes * (e) drains from the store buffer to memory", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 518, + 527 + ] + }, + { + "chunk_id": "chunk_4cbc9dc8", + "text": "This corresponds to a global memory order of (f), (i), (a), (c), (d), (e).", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 529, + 532 + ] + }, + { + "chunk_id": "chunk_a2489796", + "text": "Therefore, this execution is legal and does not violate the CoRR requirements.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 529, + 532 + ] + }, + { + "chunk_id": "chunk_b7c1e039", + "text": "Likewise, if two back-to-back loads return the values written by the same store, then they may also appear out-of-order in the global memory order without violating CoRR.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 534, + 538 + ] + }, + { + "chunk_id": "chunk_8ca57382", + "text": "Consider the litmus test of .", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 566, + 576 + ] + }, + { + "chunk_id": "chunk_3a31cbf7", + "text": "The outcome `a0=1`, `a1=v`, `a2=v`, `a3=0` (where v is some value written by another hart) can be observed by allowing (g) and (h) to be reordered.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 566, + 576 + ] + }, + { + "chunk_id": "chunk_1a1ff413", + "text": "The global memory order corresponding to this execution would be (h),(k),(a),(c),(d),(g).", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 566, + 576 + ] + }, + { + "chunk_id": "chunk_32d525f8", + "text": "Executions of the test in in which `a1` does not equal `a2` do in fact require that (g) appears before (h) in the global memory order.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "range", + "line_range": [ + 578, + 587 + ] + }, + { + "chunk_id": "chunk_0dae7f9f", + "text": "Therefore, forbids this CoRR violation from occurring.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 578, + 587 + ] + }, + { + "chunk_id": "chunk_ad8310f1", + "text": "As such, strikes a careful balance between enforcing CoRR in all cases while simultaneously being weak enough to permit \"RSW\" and \"fri-rfi\" patterns that commonly appear in real microarchitectures.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 578, + 587 + ] + }, + { + "chunk_id": "chunk_716cfd0d", + "text": "There is one more overlapping-address rule: simply states that a value cannot be returned from an AMO or SC to a subsequent load until the AMO or SC has (in the case of the SC, successfully) performed globally.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 589, + 601 + ] + }, + { + "chunk_id": "chunk_0c374289", + "text": "This follows somewhat naturally from the conceptual view that both AMOs and SC instructions are meant to be performed atomically in memory.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 589, + 601 + ] + }, + { + "chunk_id": "chunk_683d9840", + "text": "However, notably, states that hardware may not even non-speculatively forward the value being stored by an AMOSWAP to a subsequent load, even though for AMOSWAP that store value is not actually semantically dependent on the previous value in memory, as is the case for the other AMOs.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 589, + 601 + ] + }, + { + "chunk_id": "chunk_93fa0c09", + "text": "The same holds true even when forwarding from SC store values that are not semantically dependent on the value returned by the paired LR.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 589, + 601 + ] + }, + { + "chunk_id": "chunk_22622c1d", + "text": "The three PPO rules above also apply when the memory accesses in question only overlap partially.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 603, + 609 + ] + }, + { + "chunk_id": "chunk_9ce06704", + "text": "When misaligned memory accesses are being used, the overlapping-address PPO rules apply to each of the component memory accesses independently.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 603, + 609 + ] + }, + { + "chunk_id": "chunk_f5cfc595", + "text": "[IMPORTANT] Rule : There is a FENCE instruction that orders a before b", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Fences (<>)", + "confidence": "medium", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 614, + 617 + ] + }, + { + "chunk_id": "chunk_8b91df59", + "text": "By default, the FENCE instruction ensures that all memory accesses from instructions preceding the fence in program order (the \"predecessor set\") appear earlier in the global memory order than memory accesses from instructions appearing after the fence in program order (the \"successor set\").", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Fences (<>)", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 619, + 629 + ] + }, + { + "chunk_id": "chunk_5a85c353", + "text": "However, fences can optionally further restrict the predecessor set and/or the successor set to a smaller set of memory accesses in order to provide some speedup.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Fences (<>)", + "confidence": "medium", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 619, + 629 + ] + }, + { + "chunk_id": "chunk_7feda3a7", + "text": "The FENCE encoding currently has nine non-trivial combinations of the four bits PR, PW, SR, and SW, plus one extra encoding FENCE.TSO which facilitates mapping of \"acquire+release\" or RVTSO semantics.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Fences (<>)", + "confidence": "medium", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 631, + 636 + ] + }, + { + "chunk_id": "chunk_b07961e7", + "text": "The remaining seven combinations have empty predecessor and/or successor sets and hence are no-ops.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Fences (<>)", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 631, + 636 + ] + }, + { + "chunk_id": "chunk_26eea979", + "text": "FENCE instructions using other combinations of PR, PW, SR, and SW are not normally used in the Linux or C++ memory models but are otherwise well defined.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Fences (<>)", + "confidence": "medium", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 645, + 647 + ] + }, + { + "chunk_id": "chunk_3325b338", + "text": "Fences in RISC-V are not cumulative, as they are in some non-multi-copy-atomic memory models.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Fences (<>)", + "confidence": "medium", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 649, + 652 + ] + }, + { + "chunk_id": "chunk_e8541e2a", + "text": "[IMPORTANT] : a has an acquire annotation", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Explicit Synchronization (<>)", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 657, + 659 + ] + }, + { + "chunk_id": "chunk_2e91cc08", + "text": "An acquire operation, as would be used at the start of a critical section, requires all memory operations following the acquire in program order to also follow the acquire in the global memory order.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Explicit Synchronization (<>)", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 668, + 676 + ] + }, + { + "chunk_id": "chunk_e7e47582", + "text": "Acquire ordering can be enforced in one of two ways: with an acquire annotation, which enforces ordering with respect to just the synchronization variable itself, or with a FENCE R,RW, which enforces ordering with respect to all previous loads.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Explicit Synchronization (<>)", + "confidence": "medium", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 668, + 676 + ] + }, + { + "chunk_id": "chunk_7c3dd790", + "text": "However, assuming `a0`, `a1`, and `a2` point to different memory locations, the loads and stores in the critical section may or may not appear after the \"Arbitrary unrelated load\" at the beginning of the example in the global memory order.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Explicit Synchronization (<>)", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 696, + 702 + ] + }, + { + "chunk_id": "chunk_8bf019e7", + "text": "Now, consider the alternative in .", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Explicit Synchronization (<>)", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 724, + 735 + ] + }, + { + "chunk_id": "chunk_46c704d1", + "text": "In this case, even though the AMOSWAP does not enforce ordering with an aq bit, the fence nevertheless enforces that the acquire AMOSWAP appears earlier in the global memory order than all loads and stores in the critical section.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Explicit Synchronization (<>)", + "confidence": "medium", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 724, + 735 + ] + }, + { + "chunk_id": "chunk_cd4a3926", + "text": "Release orderings work exactly the same as acquire orderings, just in the opposite direction.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Explicit Synchronization (<>)", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 737, + 748 + ] + }, + { + "chunk_id": "chunk_e4e24863", + "text": "Release semantics require all loads and stores preceding the release operation in program order to also precede the release operation in the global memory order.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Explicit Synchronization (<>)", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 737, + 748 + ] + }, + { + "chunk_id": "chunk_3199643c", + "text": "Just as for acquire semantics, release semantics can be enforced using release annotations or with a FENCE RW,W operation.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Explicit Synchronization (<>)", + "confidence": "medium", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 737, + 748 + ] + }, + { + "chunk_id": "chunk_42af797c", + "text": "Using the same examples, the ordering between the loads and stores in the critical section and the \"Arbitrary unrelated store\" at the end of the code snippet is enforced only by the FENCE RW,W in , not by the rl in .", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Explicit Synchronization (<>)", + "confidence": "medium", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 737, + 748 + ] + }, + { + "chunk_id": "chunk_f5f2f575", + "text": "With RCpc annotations alone, store-release-to-load-acquire ordering is not enforced.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Explicit Synchronization (<>)", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 750, + 757 + ] + }, + { + "chunk_id": "chunk_20df72ac", + "text": "This facilitates the porting of code written under the TSO and/or RCpc memory models.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Explicit Synchronization (<>)", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 750, + 757 + ] + }, + { + "chunk_id": "chunk_278d847d", + "text": "To enforce store-release-to-load-acquire ordering, the code must use store-release-RCsc and load-acquire-RCsc operations so that PPO rule 7 applies. RCpc alone is sufficient for many use cases in C/C\\++ but is insufficient for many other use cases in C/C++, Java, and Linux, to name just a few examples; see for details.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Explicit Synchronization (<>)", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 750, + 757 + ] + }, + { + "chunk_id": "chunk_2ddf8df0", + "text": "PPO rule 8 indicates that an SC must appear after its paired LR in the global memory order.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Explicit Synchronization (<>)", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 759, + 764 + ] + }, + { + "chunk_id": "chunk_2d970656", + "text": "This will follow naturally from the common use of LR/SC to perform an atomic read-modify-write operation due to the inherent data dependency.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Explicit Synchronization (<>)", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 759, + 764 + ] + }, + { + "chunk_id": "chunk_784281ac", + "text": "However, PPO rule 8 also applies even when the value being stored does not syntactically depend on the value returned by the paired LR.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Explicit Synchronization (<>)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 759, + 764 + ] + }, + { + "chunk_id": "chunk_88c2cdc4", + "text": "[IMPORTANT] : b has a syntactic address dependency on a", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 772, + 775 + ] + }, + { + "chunk_id": "chunk_775577a1", + "text": ": b is a store, and b has a syntactic control dependency on a", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 779, + 780 + ] + }, + { + "chunk_id": "chunk_5cae2326", + "text": "Dependencies from a load to a later memory operation in the same hart are respected by the RVWMO memory model.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 782, + 789 + ] + }, + { + "chunk_id": "chunk_a92bd0dd", + "text": "The Alpha memory model was notable for choosing not to enforce the ordering of such dependencies, but most modern hardware and software memory models consider allowing dependent instructions to be reordered too confusing and counterintuitive.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)", + "confidence": "medium", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 782, + 789 + ] + }, + { + "chunk_id": "chunk_1bd015c1", + "text": "Furthermore, modern code sometimes intentionally uses such dependencies as a particularly lightweight ordering enforcement mechanism.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 782, + 789 + ] + }, + { + "chunk_id": "chunk_b66d9a31", + "text": "Instructions are said to carry dependencies from their source register(s) to their destination register(s) whenever the value written into each destination register is a function of the source register(s).", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 791, + 805 + ] + }, + { + "chunk_id": "chunk_46b5fa49", + "text": "For most instructions, this means that the destination register(s) carry a dependency from all source register(s).", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 791, + 805 + ] + }, + { + "chunk_id": "chunk_0fa48a47", + "text": "In the case of memory instructions, the value written into the destination register ultimately comes from the memory system rather than from the source register(s) directly, and so this breaks the chain of dependencies carried from the source register(s).", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 791, + 805 + ] + }, + { + "chunk_id": "chunk_81c0005f", + "text": "In the case of unconditional jumps, the value written into the destination register comes from the current `pc` (which is never considered a source register by the memory model), and so likewise, JALR (the only jump with a source register) does not carry a dependency from rs1 to rd.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 791, + 805 + ] + }, + { + "chunk_id": "chunk_b9271c44", + "text": "Like other modern memory models, the RVWMO memory model uses syntactic rather than semantic dependencies.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 822, + 829 + ] + }, + { + "chunk_id": "chunk_1740af5c", + "text": "In other words, this definition depends on the identities of the registers being accessed by different instructions, not the actual contents of those registers.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 822, + 829 + ] + }, + { + "chunk_id": "chunk_bcadfec1", + "text": "This means that an address, control, or data dependency must be enforced even if the calculation could seemingly be `optimized away`.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 822, + 829 + ] + }, + { + "chunk_id": "chunk_94e5d203", + "text": "This choice ensures that RVWMO remains compatible with code that uses these false syntactic dependencies as a lightweight ordering mechanism.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 822, + 829 + ] + }, + { + "chunk_id": "chunk_f35d4f33", + "text": "The benefit of using dependencies as a lightweight synchronization mechanism is that the ordering enforcement requirement is limited only to the specific two instructions in question.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 848, + 856 + ] + }, + { + "chunk_id": "chunk_ec01a702", + "text": "Other non-dependent instructions may be freely reordered by aggressive implementations.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 848, + 856 + ] + }, + { + "chunk_id": "chunk_49c76ffe", + "text": "One alternative would be to use a load-acquire, but this would enforce ordering for the first load with respect to all subsequent instructions.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 848, + 856 + ] + }, + { + "chunk_id": "chunk_2a63edc0", + "text": "Control dependencies behave differently from address and data dependencies in the sense that a control dependency always extends to all instructions following the original target in program order.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 868, + 874 + ] + }, + { + "chunk_id": "chunk_37c9b3a6", + "text": "Consider the instruction at `next` will always execute, but the memory operation generated by that last instruction nevertheless still has a control dependency from the memory operation generated by the first instruction.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 868, + 874 + ] + }, + { + "chunk_id": "chunk_e48cf20c", + "text": "Even though both branch outcomes have the same target, there is still a control dependency from the memory operation generated by the first instruction in this snippet to the memory operation generated by the last instruction.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 885, + 892 + ] + }, + { + "chunk_id": "chunk_c16fc9f0", + "text": "However, since control, address, and data dependencies are defined over memory operations, and since an unsuccessful SC does not generate a memory operation, no order is enforced between unsuccessful SC and its dependent instructions.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 894, + 909 + ] + }, + { + "chunk_id": "chunk_6bc31ff4", + "text": "Moreover, since SC is defined to carry dependencies from its source registers to rd only when the SC is successful, an unsuccessful SC has no effect on the global memory order.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 894, + 909 + ] + }, + { + "chunk_id": "chunk_2fec39d2", + "text": "In addition, the choice to respect dependencies originating at store-conditional instructions ensures that certain out-of-thin-air-like behaviors will be prevented.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 934, + 946 + ] + }, + { + "chunk_id": "chunk_5f5212cd", + "text": "Suppose a hypothetical implementation could occasionally make some early guarantee that a store-conditional operation will succeed.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 934, + 946 + ] + }, + { + "chunk_id": "chunk_9632fb82", + "text": "In this case, (c) could return 0 to `a2` early (before actually executing), allowing the sequence (d), (e), (f), (a), and then (b) to execute, and then (c) might execute (successfully) only at that point.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 934, + 946 + ] + }, + { + "chunk_id": "chunk_49f49f22", + "text": "For example: a syntactic dependency between two `F` instructions via one of the `accumulating CSRs` in does not imply that the two `F` instructions must be executed in order.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 948, + 956 + ] + }, + { + "chunk_id": "chunk_13bc7288", + "text": "Such a dependency would only serve to ultimately set up later a dependency from both `F` instructions to a later CSR instruction accessing the CSR flag in question.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 948, + 956 + ] + }, + { + "chunk_id": "chunk_d60de3c4", + "text": "[IMPORTANT] : b is a load, and there exists some store m between a and b in program order such that m has an address or data dependency on a, and b returns a value written by m", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Pipeline Dependencies (<>)", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 962, + 967 + ] + }, + { + "chunk_id": "chunk_56dabc33", + "text": ": b is a store, and there exists some instruction m between a and b in program order such that m has an address dependency on a", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Pipeline Dependencies (<>)", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 969, + 971 + ] + }, + { + "chunk_id": "chunk_c1d0bdd7", + "text": "PPO rules and reflect behaviors of almost all real processor pipeline implementations.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Pipeline Dependencies (<>)", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 996, + 1004 + ] + }, + { + "chunk_id": "chunk_9e54dbae", + "text": "Rule states that a load cannot forward from a store until the address and data for that store are known.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Pipeline Dependencies (<>)", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 996, + 1004 + ] + }, + { + "chunk_id": "chunk_3196163e", + "text": "Consider (f) cannot be executed until the data for (e) has been resolved, because (f) must return the value written by (e) (or by something even later in the global memory order), and the old value must not be clobbered by the write-back of (e) before (d) has had a chance to perform.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Pipeline Dependencies (<>)", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 996, + 1004 + ] + }, + { + "chunk_id": "chunk_cd4dd644", + "text": "Therefore, (f) will never perform before (d) has performed.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Pipeline Dependencies (<>)", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 996, + 1004 + ] + }, + { + "chunk_id": "chunk_3b45583f", + "text": "[float=\"center\",align=\"center\",cols=\".^1a,.^1a\",frame=\"none\",grid=\"none\",options=\"noheader\"] | | ! 2+!Hart 0 2+!Hart 1 2+!li t1, 1 2+^!li t1, 1 !(a) !sw t1,0(s0) !(d) !lw a0, 0(s1) !(b) !fence w, w !(e) !sw a0, 0(s2) !(c) !sw t1,0(s1) !(f) !sw t1, 0(s2) ! ! !(g) !lw a1, 0(s2) ! ! ! !xor a2,a1,a1 ! ! ! !add s0,s0,a2 ! ! !(h) !lw a3,0(s0) 4+!Outcome: `a0=1`, `a3=0` ! | ! //a! graphviz::images/graphviz/litmusdatacoirfi.txt[] a! image::graphviz/litmusdatacoirfi.png[] ! |", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Pipeline Dependencies (<>)", + "confidence": "medium", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 1008, + 1029 + ] + }, + { + "chunk_id": "chunk_4841da90", + "text": "Rule makes a similar observation to the previous rule: a store cannot be performed at memory until all previous loads that might access the same address have themselves been performed.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Pipeline Dependencies (<>)", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1037, + 1046 + ] + }, + { + "chunk_id": "chunk_9fb64c76", + "text": "Such a load must appear to execute before the store, but it cannot do so if the store were to overwrite the value in memory before the load had a chance to read the old value.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Pipeline Dependencies (<>)", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 1037, + 1046 + ] + }, + { + "chunk_id": "chunk_29b31706", + "text": "Likewise, a store generally cannot be performed until it is known that preceding instructions will not cause an exception due to failed address resolution, and in this sense, rule 13 can be seen as somewhat of a special case of rule .", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Pipeline Dependencies (<>)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1037, + 1046 + ] + }, + { + "chunk_id": "chunk_266e9c70", + "text": "Therefore, (f) cannot be sent to memory before (d) has executed and confirmed whether the addresses do indeed overlap.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Pipeline Dependencies (<>)", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1069, + 1073 + ] + }, + { + "chunk_id": "chunk_fc160f8d", + "text": "The RISC-V Privileged ISA defines Physical Memory Attributes (PMAs) which specify, among other things, whether portions of the address space are coherent and/or cacheable.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > Coherence and Cacheability", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1088, + 1092 + ] + }, + { + "chunk_id": "chunk_8828b3dc", + "text": "See the RISC-V Privileged ISA Specification for the complete details.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > Coherence and Cacheability", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1088, + 1092 + ] + }, + { + "chunk_id": "chunk_8e7a7a9f", + "text": "Here, we simply discuss how the various details in each PMA relate to the memory model:", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > Coherence and Cacheability", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1088, + 1092 + ] + }, + { + "chunk_id": "chunk_281cf3db", + "text": "Non-cacheable regions may have more restrictive behavior than cacheable regions, but the set of allowed behaviors does not change regardless.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > Coherence and Cacheability", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1094, + 1116 + ] + }, + { + "chunk_id": "chunk_def092c8", + "text": "However, some platform-specific and/or device-specific cacheability settings may differ. * Coherence PMAs: The memory consistency model for memory regions marked as non-coherent in PMAs is currently platform-specific and/or device-specific: the load-value axiom, the atomicity axiom, and the progress axiom all may be violated with non-coherent memory.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > Coherence and Cacheability", + "confidence": "medium", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 1094, + 1116 + ] + }, + { + "chunk_id": "chunk_91242b40", + "text": "This distinction does not affect the memory model.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > Coherence and Cacheability", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1094, + 1116 + ] + }, + { + "chunk_id": "chunk_85a15741", + "text": "Nevertheless, the following preserved program order rules still generally apply for accesses to I/O memory: memory access a precedes memory access b in global memory order if a precedes b in program order and one or more of the following holds:", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > I/O Ordering", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1120, + 1127 + ] + }, + { + "chunk_id": "chunk_b06fc445", + "text": "To enforce ordering between I/O operations and main memory operations, code must use a FENCE with PI, PO, SI, and/or SO, plus PR, PW, SR, and/or SW.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > I/O Ordering", + "confidence": "very_high", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 1145, + 1158 + ] + }, + { + "chunk_id": "chunk_33c74417", + "text": "When a fence is in fact used, implementations must assume that the device may attempt to access memory immediately after receiving the MMIO signal, and subsequent memory accesses from that device to memory must observe the effects of all accesses ordered prior to that MMIO operation.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > I/O Ordering", + "confidence": "very_high", + "parameter_class": "SW_rule", + "parameter_type": "binary", + "line_range": [ + 1160, + 1176 + ] + }, + { + "chunk_id": "chunk_1b270c5b", + "text": "In other words, in , suppose `0(a0)` is in main memory and `0(a1)` is the address of a device register in I/O memory.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > I/O Ordering", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1160, + 1176 + ] + }, + { + "chunk_id": "chunk_a14543c5", + "text": "If the device accesses `0(a0)` upon receiving the MMIO write, then that load must conceptually appear after the first store to `0(a0)` according to the rules of the RVWMO memory model.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > I/O Ordering", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 1160, + 1176 + ] + }, + { + "chunk_id": "chunk_c48c1f22", + "text": "Other implementations may find ways to be more aggressive, while others still may not need to do anything different at all for I/O and main memory accesses.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > I/O Ordering", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1160, + 1176 + ] + }, + { + "chunk_id": "chunk_2d7c04cd", + "text": "Nevertheless, the RVWMO memory model does not distinguish between these options; it simply provides an implementation-agnostic mechanism to specify the orderings that must be enforced.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > I/O Ordering", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1160, + 1176 + ] + }, + { + "chunk_id": "chunk_64f8ae35", + "text": "Many architectures include separate notions of \"ordering\" and \"completion\" fences, especially as it relates to I/O (as opposed to regular main memory).", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > I/O Ordering", + "confidence": "medium", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 1178, + 1185 + ] + }, + { + "chunk_id": "chunk_30e09741", + "text": "Ordering fences simply ensure that memory operations stay in order, while completion fences ensure that predecessor accesses have all completed before any successors are made visible. RISC-V does not explicitly distinguish between ordering and completion fences.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > I/O Ordering", + "confidence": "medium", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 1178, + 1185 + ] + }, + { + "chunk_id": "chunk_4060cee4", + "text": "Instead, this distinction is simply inferred from different uses of the FENCE bits.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > I/O Ordering", + "confidence": "medium", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 1178, + 1185 + ] + }, + { + "chunk_id": "chunk_a9259dc5", + "text": "For implementations that conform to the RISC-V Unix Platform Specification, I/O devices and DMA operations are required to access memory coherently and via strongly ordered I/O channels.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > I/O Ordering", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1187, + 1195 + ] + }, + { + "chunk_id": "chunk_534db460", + "text": "Therefore, accesses to regular main memory regions that are concurrently accessed by external devices can also use the standard synchronization mechanisms.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > I/O Ordering", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1187, + 1195 + ] + }, + { + "chunk_id": "chunk_d5302fbc", + "text": "Implementations that do not conform to the Unix Platform Specification and/or in which devices do not access memory coherently will need to use mechanisms (which are currently platform-specific or device-specific) to enforce coherency.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > I/O Ordering", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1187, + 1195 + ] + }, + { + "chunk_id": "chunk_f427ee08", + "text": "I/O regions in the address space should be considered non-cacheable regions in the PMAs for those regions.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > I/O Ordering", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1197, + 1199 + ] + }, + { + "chunk_id": "chunk_14737dc4", + "text": "Such regions can be considered coherent by the PMA if they are not cached by any agent.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > I/O Ordering", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1197, + 1199 + ] + }, + { + "chunk_id": "chunk_68f3b50c", + "text": "The ordering guarantees in this section may not apply beyond a platform-specific boundary between the RISC-V cores and the device.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > I/O Ordering", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1201, + 1206 + ] + }, + { + "chunk_id": "chunk_848aa8fc", + "text": "Ordering must be enforced in such situations according to the platform-specific rules of those external devices and buses.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > I/O Ordering", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1201, + 1206 + ] + }, + { + "chunk_id": "chunk_b86b06d8", + "text": "Normal x86 loads and stores are all inherently acquire-RCpc and release-RCpc operations: TSO enforces all load-load, load-store, and store-store ordering by default.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 1223, + 1235 + ] + }, + { + "chunk_id": "chunk_68f4d020", + "text": "Therefore, under RVWMO, all TSO loads must be mapped onto a load followed by FENCE R,RW, and all TSO stores must be mapped onto FENCE RW,W followed by a store. TSO atomic read-modify-writes and x86 instructions using the LOCK prefix are fully ordered and can be implemented either via an AMO with both aq and rl set, or via an LR with aq set, the arithmetic operation in question, an SC with both aq and rl set, and a conditional branch checking the success condition.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "confidence": "very_high", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 1223, + 1235 + ] + }, + { + "chunk_id": "chunk_29398847", + "text": "However, since RVWMO PPO Rule forbids forwarding of values from AMOs to subsequent loads, the use of AMOSWAP for stores may negatively affect performance. A TSO load can be mapped using LR with aq set: all such LR instructions will be unpaired, but that fact in and of itself does not preclude the use of LR for loads.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1237, + 1245 + ] + }, + { + "chunk_id": "chunk_24509e60", + "text": "However, again, this mapping may also negatively affect performance if it puts more pressure on the reservation mechanism than was originally intended.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1237, + 1245 + ] + }, + { + "chunk_id": "chunk_8e821c28", + "text": "Since RISC-V does not currently have plain load and store opcodes with aq or rl annotations, ARM load-acquire and store-release operations should be mapped using fences instead.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "confidence": "medium", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 1286, + 1298 + ] + }, + { + "chunk_id": "chunk_3ee19ac0", + "text": "Furthermore, in order to enforce store-release-to-load-acquire ordering, there must be a FENCE RW,RW between the store-release and load-acquire; enforces this by always placing the fence in front of each acquire operation. ARM load-exclusive and store-exclusive instructions can likewise map onto their RISC-V LR and SC equivalents, but instead of placing a FENCE RW,RW in front of an LR with aq set, we simply also set rl instead. ARM ISB maps on RISC-V to FENCE.I followed by FENCE R,R similarly to how ISYNC maps for Power.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "confidence": "very_high", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 1286, + 1298 + ] + }, + { + "chunk_id": "chunk_ac91305b", + "text": "With regards to , other constructs (such as spinlocks) should follow accordingly.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1350, + 1354 + ] + }, + { + "chunk_id": "chunk_9c582431", + "text": "Platforms or devices with non-coherent DMA may need additional synchronization (such as cache flush or invalidate mechanisms); currently any such extra synchronization will be device-specific.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1350, + 1354 + ] + }, + { + "chunk_id": "chunk_7352d7b8", + "text": "Platforms with non-coherent DMA may also require a mechanism by which cache lines can be flushed and/or invalidated.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1356, + 1364 + ] + }, + { + "chunk_id": "chunk_daf05007", + "text": "The Linux mappings for release operations may seem stronger than necessary, but these mappings are needed to cover some cases in which Linux requires stronger orderings than the more intuitive mappings would provide.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1366, + 1376 + ] + }, + { + "chunk_id": "chunk_8d6ec7ea", + "text": "If load and store opcodes with aq and rl modifiers are introduced, then the mappings in will suffice.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1425, + 1436 + ] + }, + { + "chunk_id": "chunk_2ed1e9ec", + "text": "Even more importantly, a sequentially consistent store, followed by a sequentially consistent load can be reordered unless the mapping of stores is strengthened by either adding a second fence or mapping the store to `amoswap.rl` instead.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 1425, + 1436 + ] + }, + { + "chunk_id": "chunk_3697bf9d", + "text": "2+!^*^ must be `lr.{w|d}.aqrl` in order to interoperate with code mapped per |", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1559, + 1560 + ] + }, + { + "chunk_id": "chunk_8e0d01b3", + "text": "Any AMO can be emulated by an LR/SC pair, but care must be taken to ensure that any PPO orderings that originate from the LR are also made to originate from the SC, and that any PPO orderings that terminate at the SC are also made to terminate at the LR.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1562, + 1572 + ] + }, + { + "chunk_id": "chunk_66011a49", + "text": "For example, the LR must also be made to respect any data dependencies that the AMO has, given that load operations do not otherwise have any notion of a data dependency.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1562, + 1572 + ] + }, + { + "chunk_id": "chunk_0aec14f4", + "text": "Likewise, the effect a FENCE R,R elsewhere in the same hart must also be made to apply to the SC, which would not otherwise respect that fence.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "confidence": "very_high", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 1562, + 1572 + ] + }, + { + "chunk_id": "chunk_91a03d69", + "text": "That said, to help people understand the actual implementations of the memory model, in this section we provide some guidelines on how architects and programmers should interpret the models' rules.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Implementation Guidelines", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1588, + 1600 + ] + }, + { + "chunk_id": "chunk_1c08c596", + "text": "Both RVWMO and RVTSO are multi-copy atomic (or other-multi-copy-atomic): any store value that is visible to a hart other than the one that originally issued it must also be conceptually visible to all other harts in the system.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Implementation Guidelines", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1602, + 1611 + ] + }, + { + "chunk_id": "chunk_5bc24164", + "text": "In other words, harts may forward from their own previous stores before those stores have become globally visible to all harts, but no early inter-hart forwarding is permitted.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Implementation Guidelines", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1602, + 1611 + ] + }, + { + "chunk_id": "chunk_d62be608", + "text": "Multi-copy atomicity may be enforced in a number of ways.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Implementation Guidelines", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1602, + 1611 + ] + }, + { + "chunk_id": "chunk_399dd0f2", + "text": "It might hold inherently due to the physical design of the caches and store buffers, it may be enforced via a single-writer/multiple-reader cache coherence protocol, or it might hold due to some other mechanism.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Implementation Guidelines", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1602, + 1611 + ] + }, + { + "chunk_id": "chunk_35da5759", + "text": "Nor may a cache coherence protocol forward a value from one hart to another until the coherence protocol has invalidated all older copies from other caches.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Implementation Guidelines", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1613, + 1624 + ] + }, + { + "chunk_id": "chunk_0cf2a857", + "text": "Of course, microarchitectures may (and high-performance implementations likely will) violate these rules under the covers through speculation or other optimizations, as long as any non-compliant behaviors are not exposed to the programmer.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Implementation Guidelines", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1613, + 1624 + ] + }, + { + "chunk_id": "chunk_5a4c1660", + "text": "programmers will use PPO rules and regularly and actively. * expert programmers will use PPO rules to speed up critical paths of important data structures. * even expert programmers will rarely if ever use PPO rules and directly.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Implementation Guidelines", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1629, + 1639 + ] + }, + { + "chunk_id": "chunk_c6cdfa9b", + "text": "PPO rules and reflect well-understood rules that should pose few surprises to architects. * PPO rule reflects a natural and common hardware optimization, but one that is very subtle and hence is worth double checking carefully. * PPO rule may not be immediately obvious to architects, but it is a standard memory model requirement * The load value axiom, the atomicity axiom, and PPO rules reflect rules that most hardware implementations will enforce naturally, unless they contain extreme optimizations.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Implementation Guidelines", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 1643, + 1655 + ] + }, + { + "chunk_id": "chunk_784480d3", + "text": "Of course, implementations should make sure to double check these rules nevertheless.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Implementation Guidelines", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1643, + 1655 + ] + }, + { + "chunk_id": "chunk_75711236", + "text": "Hardware must also ensure that syntactic dependencies are not `optimized away`.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Implementation Guidelines", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1643, + 1655 + ] + }, + { + "chunk_id": "chunk_7b8892e2", + "text": "Ignore all fences that do not have both PW and SR (unless the fence also orders I/O) * Ignore all PPO rules except for rules through , since the rest are redundant with other PPO rules under RVTSO assumptions", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Implementation Guidelines", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 1681, + 1684 + ] + }, + { + "chunk_id": "chunk_59970993", + "text": "Microarchitectures that attempt to implement silent stores must take care to ensure that the memory model is still obeyed, particularly in cases such as RSW which tend to be incompatible with silent stores. * Writes may be merged (i.e., two consecutive writes to the same address may be merged) or subsumed (i.e., the earlier of two back-to-back writes to the same address may be elided) as long as the resulting behavior does not otherwise violate the memory model semantics.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Implementation Guidelines", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1688, + 1700 + ] + }, + { + "chunk_id": "chunk_3ad4c20e", + "text": "As written, if the load (d) reads value 1, then (a) must precede (f) in the global memory order:", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Implementation Guidelines", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 1725, + 1726 + ] + }, + { + "chunk_id": "chunk_7ee8c80f", + "text": "In other words the final value of the memory location whose address is in `s0` must be 2 (the value written by the store (f)) and cannot be 3 (the value written by the store (a)).", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Implementation Guidelines", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1734, + 1736 + ] + }, + { + "chunk_id": "chunk_5ff37e32", + "text": "To address this, we may choose to add something like the following new PPO rule: Memory operation a precedes memory operation b in preserved program order (and hence also in the global memory order) if a precedes b in program order, a and b both access regular main memory (rather than I/O regions), a is a load, b is a store, there is a load m between a and b, there is a byte x that both a and m read, there is no store between a and m that writes to x, and m precedes b in PPO.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Known Issues > Mixed-size RSW", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1808, + 1827 + ] + }, + { + "chunk_id": "chunk_b2861666", + "text": "In other words, in herd syntax, we may choose to add `(po-loc & rsw);ppo;[W]` to PPO.", + "source_file": "src/unpriv/mm-explanatory.adoc", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Known Issues > Mixed-size RSW", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1808, + 1827 + ] + } + ] + }, + { + "file": "src/unpriv/mm-formal.adoc", + "chunks": [ + { + "chunk_id": "chunk_0071b77a", + "text": "This appendix should be treated as commentary; all normative material is provided in and in the rest of the main body of the ISA specification.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 8, + 12 + ] + }, + { + "chunk_id": "chunk_ea4128dc", + "text": "We present a formal specification of the RVWMO memory model in Alloy (http://alloy.mit.edu).", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 17, + 19 + ] + }, + { + "chunk_id": "chunk_7aba8faa", + "text": "This model is available online at https://github.com/daniellustig/riscv-memory-model.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 17, + 19 + ] + }, + { + "chunk_id": "chunk_f6da777a", + "text": "sig Hart { // hardware thread start : one Event } sig Address {} abstract sig Event { po: lone Event // program order }", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 94, + 100 + ] + }, + { + "chunk_id": "chunk_4b37c4bc", + "text": "abstract sig MemoryEvent extends Event { address: one Address, acquireRCpc: lone MemoryEvent, acquireRCsc: lone MemoryEvent, releaseRCpc: lone MemoryEvent, releaseRCsc: lone MemoryEvent, addrdep: set MemoryEvent, ctrldep: set Event, datadep: set MemoryEvent, gmo: set MemoryEvent, // global memory order rf: set MemoryEvent } sig LoadNormal extends MemoryEvent {} // l{b|h|w|d} sig LoadReserve extends MemoryEvent { // lr pair: lone StoreConditional } sig StoreNormal extends MemoryEvent {} // s{b|h|w|d} // all StoreConditionals in the model are assumed to be successful sig StoreConditional extends MemoryEvent {} // sc sig AMO extends MemoryEvent {} // amo sig NOP extends Event {}", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 102, + 122 + ] + }, + { + "chunk_id": "chunk_a831b369", + "text": "fun Load : Event { LoadNormal + LoadReserve + AMO } fun Store : Event { StoreNormal + StoreConditional + AMO }", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 124, + 125 + ] + }, + { + "chunk_id": "chunk_5f3b8157", + "text": "sig Fence extends Event { pr: lone Fence, // opcode bit pw: lone Fence, // opcode bit sr: lone Fence, // opcode bit sw: lone Fence // opcode bit } sig FenceTSO extends Fence {}", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy", + "confidence": "medium", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 127, + 133 + ] + }, + { + "chunk_id": "chunk_ba82bf2c", + "text": "pred restricttocurrentencodings { no (LoadNormal + StoreNormal) & (Acquire + Release) }", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 235, + 237 + ] + }, + { + "chunk_id": "chunk_97468130", + "text": "The tool [.sans-serif]herd takes a memory model and a litmus test as input and simulates the execution of the test on top of the memory model.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > Formal Axiomatic Specification in Herd", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 251, + 259 + ] + }, + { + "chunk_id": "chunk_70c79372", + "text": "Memory models are written in the domain specific language Cat.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > Formal Axiomatic Specification in Herd", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 251, + 259 + ] + }, + { + "chunk_id": "chunk_de8a0591", + "text": "This section provides two Cat memory model of RVWMO.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > Formal Axiomatic Specification in Herd", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 251, + 259 + ] + }, + { + "chunk_id": "chunk_3ae362c7", + "text": "The first model, , follows the global memory order, , definition of RVWMO, as much as is possible for a Cat model.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > Formal Axiomatic Specification in Herd", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 251, + 259 + ] + }, + { + "chunk_id": "chunk_5d81e359", + "text": "The second model, , is an equivalent, more efficient, partial order based RVWMO model.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > Formal Axiomatic Specification in Herd", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 251, + 259 + ] + }, + { + "chunk_id": "chunk_10ba83fe", + "text": "The simulator `herd` is part of the `diy` tool suite \u2014 see http://diy.inria.fr for software and documentation.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > Formal Axiomatic Specification in Herd", + "confidence": "medium", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 261, + 270 + ] + }, + { + "chunk_id": "chunk_a547799e", + "text": "(* Same address, no W to the same address in-between *) let po-loc-no-w = po-loc \\ (po-loc?;[W];po-loc) (* Read same write *) let rsw = rf^-1;rf (* Acquire, or stronger *) let AQ = Acq|AcqRel (* Release or stronger *) and RL = RelAcqRel (* All RCsc *) let RCsc = Acq|Rel|AcqRel (* Amo events are both R and W, relation rmw relates paired lr/sc *) let AMO = R & W let StCond = range(rmw)", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > Formal Axiomatic Specification in Herd", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 292, + 304 + ] + }, + { + "chunk_id": "chunk_8b24712b", + "text": "(* Overlapping-Address Orderings *) let r1 = [M];po-loc;[W] and r2 = ([R];po-loc-no-w;[R]) \\ rsw and r3 = [AMO|StCond];rfi;[R] (* Explicit Synchronization *) and r4 = fence and r5 = [AQ];po;[M] and r6 = [M];po;[RL] and r7 = [RCsc];po;[RCsc] and r8 = rmw (* Syntactic Dependencies *) and r9 = [M];addr;[M] and r10 = [M];data;[W] and r11 = [M];ctrl;[W] (* Pipeline Dependencies *) and r12 = [R];(addr|data);[W];rfi;[R] and r13 = [R];addr;[M];po;[W]", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > Formal Axiomatic Specification in Herd", + "confidence": "medium", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 310, + 326 + ] + }, + { + "chunk_id": "chunk_751b821a", + "text": "(* Notice that herd has defined its own rf relation *)", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > Formal Axiomatic Specification in Herd", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 336, + 336 + ] + }, + { + "chunk_id": "chunk_cf70252d", + "text": "(********************************) (* Generate global memory order *) (********************************)", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > Formal Axiomatic Specification in Herd", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 341, + 343 + ] + }, + { + "chunk_id": "chunk_93533f52", + "text": "let gmo0 = (* precursor: ie build gmo as an total order that include gmo0 *) loc & (W\\FW) * FW | Final write after any write to the same location ppo | ppo compatible rfe includes herd external rf (optimization)", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > Formal Axiomatic Specification in Herd", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 345, + 348 + ] + }, + { + "chunk_id": "chunk_337f2737", + "text": "(* Walk over all linear extensions of gmo0 *) with gmo from linearizations(M\\IW,gmo0)", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > Formal Axiomatic Specification in Herd", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 350, + 351 + ] + }, + { + "chunk_id": "chunk_3b85cab6", + "text": "(* Add initial writes upfront -- convenient for computing rfGMO *) let gmo = gmo | loc & IW * (M\\IW)", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > Formal Axiomatic Specification in Herd", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 353, + 354 + ] + }, + { + "chunk_id": "chunk_30e7ddcd", + "text": "(* Compute rf according to the load value axiom, aka rfGMO *) let WR = loc & ([W];(gmo|po);[R]) let rfGMO = WR \\ (loc&([W];gmo);WR)", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > Formal Axiomatic Specification in Herd", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 360, + 362 + ] + }, + { + "chunk_id": "chunk_8014b1f4", + "text": "(* Check equality of herd rf and of rfGMO *) empty (rf\\rfGMO)|(rfGMO\\rf) as RfCons", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > Formal Axiomatic Specification in Herd", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 364, + 365 + ] + }, + { + "chunk_id": "chunk_62dff2b5", + "text": "(* Compute coherence relation *) include \"cos-opt.cat\"", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > Formal Axiomatic Specification in Herd", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 386, + 387 + ] + }, + { + "chunk_id": "chunk_aa316717", + "text": "(* Sc per location *) acyclic co|rf|fr|po-loc as Coherence", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > Formal Axiomatic Specification in Herd", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 393, + 394 + ] + }, + { + "chunk_id": "chunk_e725010e", + "text": "(* Main model axiom *) acyclic co|rfe|fr|ppo as Model", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > Formal Axiomatic Specification in Herd", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 396, + 397 + ] + }, + { + "chunk_id": "chunk_1e4ea52c", + "text": "This is an alternative presentation of the RVWMO memory model in operational style.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 406, + 409 + ] + }, + { + "chunk_id": "chunk_97e7f3cc", + "text": "It aims to admit exactly the same extensional behavior as the axiomatic presentation: for any given program, admitting an execution if and only if the axiomatic presentation allows it.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 406, + 409 + ] + }, + { + "chunk_id": "chunk_e3e448ba", + "text": "The axiomatic presentation is defined as a predicate on complete candidate executions.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 411, + 422 + ] + }, + { + "chunk_id": "chunk_31870c17", + "text": "In contrast, this operational presentation has an abstract microarchitectural flavor: it is expressed as a state machine, with states that are an abstract representation of hardware machine states, and with explicit out-of-order and speculative execution (but abstracting from more implementation-specific microarchitectural details such as register renaming, store buffers, cache hierarchies, cache protocols, etc.).", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 411, + 422 + ] + }, + { + "chunk_id": "chunk_83ba8998", + "text": "It can also construct executions incrementally, making it possible to interactively and randomly explore the behavior of larger examples, while the axiomatic model requires complete candidate executions over which the axioms can be checked.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 411, + 422 + ] + }, + { + "chunk_id": "chunk_ee15c13c", + "text": "The operational presentation covers mixed-size execution, with potentially overlapping memory accesses of different power-of-two byte sizes.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 424, + 426 + ] + }, + { + "chunk_id": "chunk_c7b5237b", + "text": "In `rmem`, the ISA semantics is expressed explicitly in Sail (see https://github.com/rems-project/sail for the Sail language, and https://github.com/rems-project/sail-riscv for the RISC-V ISA model), and the concurrency semantics is expressed in Lem (see https://github.com/rems-project/lem for the Lem language).", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 428, + 437 + ] + }, + { + "chunk_id": "chunk_6d9c1010", + "text": "`rmem` has a command-line interface and a web-interface.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 439, + 443 + ] + }, + { + "chunk_id": "chunk_3f350b56", + "text": "The web-interface runs entirely on the client side, and is provided online together with a library of litmus tests: http://www.cl.cam.ac.uk/.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 439, + 443 + ] + }, + { + "chunk_id": "chunk_299d0526", + "text": "The command-line interface is faster than the web-interface, specially in exhaustive mode.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 439, + 443 + ] + }, + { + "chunk_id": "chunk_e9dd54ab", + "text": "Terminology: In contrast to the axiomatic presentation, here every memory operation is either a load or a store.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 448, + 456 + ] + }, + { + "chunk_id": "chunk_3dd82b5d", + "text": "Hence, AMOs give rise to two distinct memory operations, a load and a store.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 448, + 456 + ] + }, + { + "chunk_id": "chunk_1207ee15", + "text": "When used in conjunction with `instruction`, the terms `load` and `store` refer to instructions that give rise to such memory operations.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 448, + 456 + ] + }, + { + "chunk_id": "chunk_c95fe718", + "text": "The term `acquire` refers to an instruction (or its memory operation) with the acquire-RCpc or acquire-RCsc annotation.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 448, + 456 + ] + }, + { + "chunk_id": "chunk_efba5840", + "text": "The term `release` refers to an instruction (or its memory operation) with the release-RCpc or release-RCsc annotation.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 448, + 456 + ] + }, + { + "chunk_id": "chunk_0e8184c4", + "text": "Model states: A model state consists of a shared memory and a tuple of hart states.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 460, + 460 + ] + }, + { + "chunk_id": "chunk_add0eaa5", + "text": "The shared memory state records all the memory store operations that have propagated so far, in the order they propagated (this can be made more efficient, but for simplicity of the presentation we keep it this way).", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 473, + 476 + ] + }, + { + "chunk_id": "chunk_ee5c4c91", + "text": "Each hart state consists principally of a tree of instruction instances, some of which have been finished, and some of which have not.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 478, + 482 + ] + }, + { + "chunk_id": "chunk_9a8c1fcd", + "text": "Conditional branch and indirect jump instructions may have multiple successors in the instruction tree.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 484, + 486 + ] + }, + { + "chunk_id": "chunk_c797fa78", + "text": "Each instruction instance in the instruction tree has a state that includes an execution state of the intra-instruction semantics (the ISA pseudocode for this instruction).", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 488, + 496 + ] + }, + { + "chunk_id": "chunk_f31fa55d", + "text": "One can think of the execution state of an instruction as a representation of the pseudocode control state, pseudocode call stack, and local variable values.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 488, + 496 + ] + }, + { + "chunk_id": "chunk_4f882a65", + "text": "An instruction instance state also includes information about the instance's memory and register footprints, its register reads and writes, its memory operations, whether it is finished, etc.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 488, + 496 + ] + }, + { + "chunk_id": "chunk_3d06102d", + "text": "The model defines, for any model state, the set of allowed transitions, each of which is a single atomic step to a new abstract machine state.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 500, + 510 + ] + }, + { + "chunk_id": "chunk_753cffb7", + "text": "Each transition arises from a single instruction instance; it will change the state of that instance, and it may depend on or change the rest of its hart state and the shared memory state, but it does not depend on other hart states, and it will not change them.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 500, + 510 + ] + }, + { + "chunk_id": "chunk_62ffd597", + "text": "The transitions are introduced below and defined in , with a precondition and a construction of the post-transition model state for each.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 500, + 510 + ] + }, + { + "chunk_id": "chunk_18b0b77d", + "text": ": This transition represents a fetch and decode of a new instruction instance, as a program order successor of a previously fetched instruction instance (or the initial fetch address).", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 514, + 515 + ] + }, + { + "chunk_id": "chunk_32a42b42", + "text": "The model assumes the instruction memory is fixed; it does not describe the behavior of self-modifying code.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 517, + 521 + ] + }, + { + "chunk_id": "chunk_5151a39a", + "text": "In particular, the transition does not generate memory load operations, and the shared memory is not involved in the transition.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 517, + 521 + ] + }, + { + "chunk_id": "chunk_38f9490c", + "text": "Instead, the model depends on an external oracle that provides an opcode when given a memory location.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 517, + 521 + ] + }, + { + "chunk_id": "chunk_076d0a30", + "text": ": This is a read of a register value from the most recent program-order-predecessor instruction instance that writes to that register.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 526, + 528 + ] + }, + { + "chunk_id": "chunk_27354d72", + "text": ": This covers pseudocode internal computation: arithmetic, function calls, etc.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 530, + 531 + ] + }, + { + "chunk_id": "chunk_f6d7bf96", + "text": ": At this point the instruction pseudocode is done, the instruction cannot be restarted, memory accesses cannot be discarded, and all memory effects have taken place.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 533, + 538 + ] + }, + { + "chunk_id": "chunk_4ab04611", + "text": "For conditional branch and indirect jump instructions, any program order successors that were fetched from an address that is not the one that was written to the pc register are discarded, together with the sub-tree of instruction instances below them.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 533, + 538 + ] + }, + { + "chunk_id": "chunk_c76f56b4", + "text": "[circle] * : At this point the memory footprint of the load instruction is provisionally known (it could change if earlier instructions are restarted) and its individual memory load operations can start being satisfied.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 542, + 546 + ] + }, + { + "chunk_id": "chunk_5e99cd00", + "text": "[disc] * : This partially or entirely satisfies a single memory load operation by forwarding, from program-order-previous memory store operations.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 548, + 549 + ] + }, + { + "chunk_id": "chunk_1049a7fe", + "text": ": This entirely satisfies the outstanding slices of a single memory load operation, from memory.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 551, + 552 + ] + }, + { + "chunk_id": "chunk_7e774973", + "text": "[circle] * : At this point all the memory load operations of the instruction have been entirely satisfied and the instruction pseudocode can continue executing. A load instruction can be subject to being restarted until the transition.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 554, + 559 + ] + }, + { + "chunk_id": "chunk_b3118161", + "text": "[circle] * : At this point the memory footprint of the store is provisionally known.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 563, + 565 + ] + }, + { + "chunk_id": "chunk_d946f40f", + "text": ": At this point the memory store operations have their values and program-order-successor memory load operations can be satisfied by forwarding from them.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 567, + 569 + ] + }, + { + "chunk_id": "chunk_011742cf", + "text": ": At this point the store operations are guaranteed to happen (the instruction can no longer be restarted or discarded), and they can start being propagated to memory.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 571, + 573 + ] + }, + { + "chunk_id": "chunk_fc1f3677", + "text": "[disc] * : This propagates a single memory store operation to memory.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 575, + 576 + ] + }, + { + "chunk_id": "chunk_f25ddaad", + "text": "[circle] * : At this point all the memory store operations of the instruction have been propagated to memory, and the instruction pseudocode can continue executing.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 578, + 581 + ] + }, + { + "chunk_id": "chunk_ac10304f", + "text": ": This is an atomic execution of the transitions and , it is enabled only if the stores from which the `lr` read from have not been overwritten.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 591, + 593 + ] + }, + { + "chunk_id": "chunk_b54865e7", + "text": "[disc] * : This is an atomic execution of all the transitions needed to satisfy the load operation, do the required arithmetic, and propagate the store operation.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 600, + 603 + ] + }, + { + "chunk_id": "chunk_5e952d45", + "text": "The transitions labeled {circ} can always be taken eagerly, as soon as their precondition is satisfied, without excluding other behavior; the {bullet} cannot.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 610, + 614 + ] + }, + { + "chunk_id": "chunk_d1d4b77e", + "text": "This concludes the informal description of the operational model.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 632, + 633 + ] + }, + { + "chunk_id": "chunk_1e9175c1", + "text": "The following sections describe the formal operational model.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 632, + 633 + ] + }, + { + "chunk_id": "chunk_8c11ee5b", + "text": "The intra-instruction semantics for each instruction instance is expressed as a state machine, essentially running the instruction pseudocode.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Intra-instruction Pseudocode Execution", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 639, + 644 + ] + }, + { + "chunk_id": "chunk_93db2f5b", + "text": "Given a pseudocode execution state, it computes the next state.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Intra-instruction Pseudocode Execution", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 639, + 644 + ] + }, + { + "chunk_id": "chunk_e0195a75", + "text": "Most states identify a pending memory or register operation, requested by the pseudocode, which the memory model has to do.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Intra-instruction Pseudocode Execution", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 639, + 644 + ] + }, + { + "chunk_id": "chunk_69cf75a1", + "text": "[cols=\"<,<\",grid=\"none\"] | |Loadmem(kind, address, size, loadcontinuation) |- memory load operation", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Intra-instruction Pseudocode Execution", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 646, + 649 + ] + }, + { + "chunk_id": "chunk_cbea74c6", + "text": "|Earlyscfail(rescontinuation) |- allow `sc` to fail early", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Intra-instruction Pseudocode Execution", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 651, + 651 + ] + }, + { + "chunk_id": "chunk_c64732ea", + "text": "|Storeea(kind, address, size, nextstate) |- memory store effective address", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Intra-instruction Pseudocode Execution", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 653, + 654 + ] + }, + { + "chunk_id": "chunk_446591f2", + "text": "for load/store, kind identifies whether it is `lr/sc`, acquire-RCpc/release-RCpc, acquire-RCsc/release-RCsc, acquire-release-RCsc; * for fence, kind identifies whether it is a normal or TSO, and (for normal fences) the predecessor and successor ordering bits; * regname identifies a register and a slice thereof (start and end bit indices); and the continuations describe how the instruction instance will continue for each value that might be provided by the surrounding memory model (the loadcontinuation and readcontinuation take the value loaded from memory and read from the previous register write, the storecontinuation takes false for an `sc` that failed and true in all other cases, and rescontinuation takes false if the `sc` fails and true otherwise).", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Intra-instruction Pseudocode Execution", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 674, + 695 + ] + }, + { + "chunk_id": "chunk_047a7a8f", + "text": "Notice that writing to memory is split into two steps, Storeea and Storememv: the first one makes the memory footprint of the store provisionally known, and the second one adds the value to be stored.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Intra-instruction Pseudocode Execution", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 674, + 695 + ] + }, + { + "chunk_id": "chunk_f41140ee", + "text": "We ensure these are paired in the pseudocode (Storeea followed by Storememv), but there may be other steps between them.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Intra-instruction Pseudocode Execution", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 674, + 695 + ] + }, + { + "chunk_id": "chunk_0e838eb5", + "text": "The pseudocode of each instruction performs at most one store or one load, except for AMOs that perform exactly one load and one store.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Intra-instruction Pseudocode Execution", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "range", + "line_range": [ + 674, + 695 + ] + }, + { + "chunk_id": "chunk_8ddfb9bb", + "text": "Those memory accesses are then split apart into the architecturally atomic units by the hart semantics (see and below).", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Intra-instruction Pseudocode Execution", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 674, + 695 + ] + }, + { + "chunk_id": "chunk_f03700c5", + "text": "Informally, each bit of a register read should be satisfied from a register write by the most recent (in program order) instruction instance that can write that bit (or from the hart\u2019s initial register state if there is no such write).", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Intra-instruction Pseudocode Execution", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 697, + 705 + ] + }, + { + "chunk_id": "chunk_2a03b49b", + "text": "We ensure in the pseudocode that each instruction does at most one register write to each register bit, and also that it does not try to read a register value it just wrote.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Intra-instruction Pseudocode Execution", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "range", + "line_range": [ + 697, + 705 + ] + }, + { + "chunk_id": "chunk_b408e4e1", + "text": "Data-flow dependencies (address and data) in the model emerge from the fact that each register read has to wait for the appropriate register write to be executed (as described above).", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Intra-instruction Pseudocode Execution", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 707, + 709 + ] + }, + { + "chunk_id": "chunk_71f6a960", + "text": "Each instruction instance i has a state comprising:", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Instruction Instance State", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 714, + 714 + ] + }, + { + "chunk_id": "chunk_83766a01", + "text": "[cols=\"<,<\",grid=\"none\"] | |Plain(isastate) |- ready to make a pseudocode transition", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Instruction Instance State", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 730, + 732 + ] + }, + { + "chunk_id": "chunk_d96dbb62", + "text": "|Pendingmemstores(storecontinuation) |- requesting memory store operation(s) | * regreads, the register reads the instance has performed, including, for each one, the register write slices it read from; * regwrites, the register writes the instance has performed; * memloads, a set of memory load operations, and for each one the as-yet-unsatisfied slices (the byte indices that have not been satisfied yet), and, for the satisfied slices, the store slices (each consisting of a memory store operation and subset of its byte indices) that satisfied it. * memstores, a set of memory store operations, and for each one a flag that indicates whether it has been propagated (passed to the shared memory) or not. * information recording whether the instance is committed, finished, etc.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Instruction Instance State", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 737, + 752 + ] + }, + { + "chunk_id": "chunk_e8d569da", + "text": "Each memory load operation includes a memory footprint (address and size).", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Instruction Instance State", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 754, + 756 + ] + }, + { + "chunk_id": "chunk_c018fe6e", + "text": "Each memory store operations includes a memory footprint, and, when available, a value.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Instruction Instance State", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 754, + 756 + ] + }, + { + "chunk_id": "chunk_1824b40a", + "text": "Similarly, it is said to have a fully determined memory footprint if the load (and `sc`) instructions feeding its memory operation address register are finished.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Instruction Instance State", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 762, + 770 + ] + }, + { + "chunk_id": "chunk_d62eaaa3", + "text": "Formally, we first define the notion of fully determined register write: a register write w from regwrites of instruction instance i is said to be fully determined if one of the following conditions hold:", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Instruction Instance State", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 762, + 770 + ] + }, + { + "chunk_id": "chunk_e4f85dda", + "text": "Now, an instruction instance i is said to have fully determined data if for every register read r from regreads, the register writes that r reads from are fully determined.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Instruction Instance State", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 780, + 787 + ] + }, + { + "chunk_id": "chunk_5a61afcf", + "text": "An instruction instance i is said to have a fully determined memory footprint if for every register read r from regreads that feeds into i\u2019s memory operation address, the register writes that r reads from are fully determined.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Instruction Instance State", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 780, + 787 + ] + }, + { + "chunk_id": "chunk_d02118f6", + "text": "The model state of a single hart comprises:", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Hart State", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 791, + 791 + ] + }, + { + "chunk_id": "chunk_5fd12c29", + "text": "hartid, a unique identifier of the hart; * initialregisterstate, the initial register value for each register; * initialfetchaddress, the initial instruction fetch address; * instructiontree, a tree of the instruction instances that have been fetched (and not discarded), in program order.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Hart State", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 793, + 798 + ] + }, + { + "chunk_id": "chunk_72a4793b", + "text": "The model state of the shared memory comprises a list of memory store operations, in the order they propagated to the shared memory.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Shared Memory State", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 802, + 803 + ] + }, + { + "chunk_id": "chunk_6381b3fc", + "text": "When a store operation is propagated to the shared memory it is simply added to the end of the list.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Shared Memory State", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 805, + 809 + ] + }, + { + "chunk_id": "chunk_cc1ecbd0", + "text": "When a load operation is satisfied from memory, for each byte of the load operation, the most recent corresponding store slice is returned.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Shared Memory State", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 805, + 809 + ] + }, + { + "chunk_id": "chunk_5b25d999", + "text": "The description starts with a condition over the current system state.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 812, + 817 + ] + }, + { + "chunk_id": "chunk_5b534fb3", + "text": "The transition can be taken in the current state only if the condition is satisfied.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 812, + 817 + ] + }, + { + "chunk_id": "chunk_8103ecdf", + "text": "The condition is followed by an action that is applied to that state when the transition is taken, in order to generate the new system state.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 812, + 817 + ] + }, + { + "chunk_id": "chunk_f0a909ba", + "text": "A possible program-order-successor of instruction instance i can be fetched from address loc if:", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Fetch instruction", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 822, + 823 + ] + }, + { + "chunk_id": "chunk_b0536a89", + "text": "Action: construct a freshly initialized instruction instance i' for the instruction in the program memory at loc, with state Plain(isastate), computed from the instruction pseudocode, including the static information available from the pseudocode such as its instructionkind, srcregs, and dstregs, and add i' to the hart\u2019s instructiontree as a successor of i.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Fetch instruction", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 836, + 842 + ] + }, + { + "chunk_id": "chunk_667b7744", + "text": "For most instructions these addresses are easily obtained from the instruction pseudocode.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Fetch instruction", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 844, + 862 + ] + }, + { + "chunk_id": "chunk_28b84575", + "text": "In principle the mathematical model should allow speculation to arbitrary addresses here.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Fetch instruction", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 844, + 862 + ] + }, + { + "chunk_id": "chunk_53266906", + "text": "The exhaustive search in the `rmem` tool handles this by running the exhaustive search multiple times with a growing set of possible next fetch addresses for each indirect jump.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Fetch instruction", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 844, + 862 + ] + }, + { + "chunk_id": "chunk_1e522679", + "text": "The initial search uses empty sets, hence there is no fetch after indirect jump instruction until the pseudocode of the instruction writes to pc, and then we use that value for fetching the next instruction.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Fetch instruction", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 844, + 862 + ] + }, + { + "chunk_id": "chunk_1e9e1f74", + "text": "Before starting the next iteration of exhaustive search, we collect for each indirect jump (grouped by code location) the set of values it wrote to pc in all the executions in the previous search iteration, and use that as possible next fetch addresses of the instruction.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Fetch instruction", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 844, + 862 + ] + }, + { + "chunk_id": "chunk_ecaeafb1", + "text": "An instruction instance i in state Plain(Loadmem(kind, address, size, loadcontinuation)) can always initiate the corresponding memory load operations.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Initiate memory load operations", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 867, + 869 + ] + }, + { + "chunk_id": "chunk_05ee3e6b", + "text": "For a non-AMO load instruction instance i in state Pendingmemloads(loadcontinuation), and a memory load operation mlo in i.memloads that has unsatisfied slices, the memory load operation can be partially or entirely satisfied by forwarding from unpropagated memory store operations by store instruction instances that are program-order-before i if:", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Satisfy memory load operation by forwarding from unpropagated stores", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 883, + 889 + ] + }, + { + "chunk_id": "chunk_a640bb59", + "text": "Let msoss be the set of all unpropagated memory store operation slices from non-`sc` store instruction instances that are program-order-before i and have already calculated the value to be stored, that overlap with the unsatisfied slices of mlo, and which are not superseded by intervening store operations or store operations that are read from by an intervening load.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Satisfy memory load operation by forwarding from unpropagated stores", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 909, + 917 + ] + }, + { + "chunk_id": "chunk_cee88834", + "text": "The last condition requires, for each memory store operation slice msos in msoss from instruction i':", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Satisfy memory load operation by forwarding from unpropagated stores", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 909, + 917 + ] + }, + { + "chunk_id": "chunk_6bb184c2", + "text": "that there is no store instruction program-order-between i and i' with a memory store operation overlapping msos; and * that there is no load instruction program-order-between i and i' that was satisfied from an overlapping memory store operation slice from a different hart.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Satisfy memory load operation by forwarding from unpropagated stores", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 919, + 924 + ] + }, + { + "chunk_id": "chunk_4ec499fc", + "text": "program-order-successors of j that have data-flow dependency on a register write of j; * program-order-successors of j that have a memory load operation that reads from a memory store operation of j (by forwarding); * if j is a load-acquire, all the program-order-successors of j; * if j is a load, for every `fence`, f, with `.sr` and `.pr` set, and `.pw` not set, that is a program-order-successor of j, all the load instructions that are program-order-successors of f; * if j is a load, for every `fence.tso`, f, that is a program-order-successor of j, all the load instructions that are program-order-successors of f; and * (recursively) all the restart-dependents of all the instruction instances above.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Satisfy memory load operation by forwarding from unpropagated stores", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 943, + 959 + ] + }, + { + "chunk_id": "chunk_2faf5104", + "text": "For an instruction instance i of a non-AMO load instruction or an AMO instruction in the context of the transition, any memory load operation mlo in i.memloads that has unsatisfied slices, can be satisfied from memory if all the conditions of > are satisfied.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Satisfy memory load operation from memory", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 962, + 970 + ] + }, + { + "chunk_id": "chunk_7fd6a2e4", + "text": "Action: let msoss be the memory store operation slices from memory covering the unsatisfied slices of mlo, and apply the action of .", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Satisfy memory load operation from memory", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 962, + 970 + ] + }, + { + "chunk_id": "chunk_c26ac4d3", + "text": "Action: update the state of i to Plain(loadcontinuation(memvalue)), where memvalue is assembled from all the memory store operation slices that satisfied i.memloads.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Complete load operations", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 973, + 980 + ] + }, + { + "chunk_id": "chunk_972a4716", + "text": "An `sc` instruction instance i in state Plain(Earlyscfail(rescontinuation)) can always be made to fail.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Early `sc` fail", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 985, + 988 + ] + }, + { + "chunk_id": "chunk_22ac1409", + "text": "Action: update the state of i to Plain(rescontinuation(false)).", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Early `sc` fail", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 985, + 988 + ] + }, + { + "chunk_id": "chunk_5f7b5313", + "text": "An `sc` instruction instance i in state Plain(Earlyscfail(rescontinuation)) can continue its (potentially successful) execution if i is paired with an `lr`.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Paired `sc`", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 993, + 996 + ] + }, + { + "chunk_id": "chunk_3a4c5e9e", + "text": "Action: update the state of i to Plain(rescontinuation(true)).", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Paired `sc`", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 993, + 996 + ] + }, + { + "chunk_id": "chunk_5c9d9b55", + "text": "An instruction instance i in state Plain(Storeea(kind, address, size, nextstate)) can always announce its pending memory store operation footprint.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Initiate memory store operation footprints", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1001, + 1003 + ] + }, + { + "chunk_id": "chunk_6c12220b", + "text": "An instruction instance i in state Plain(Storememv(memvalue, storecontinuation)) can always instantiate the values of the memory store operations i.memstores.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Instantiate memory store operation values", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1017, + 1020 + ] + }, + { + "chunk_id": "chunk_6abdc165", + "text": "An uncommitted instruction instance i of a non-`sc` store instruction or an `sc` instruction in the context of the transition, in state Pendingmemstores(storecontinuation), can be committed (not to be confused with propagated) if:", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Commit store instruction", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1030, + 1033 + ] + }, + { + "chunk_id": "chunk_e4ab3146", + "text": "Action: record that i is committed.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Commit store instruction", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1053, + 1054 + ] + }, + { + "chunk_id": "chunk_28deb88b", + "text": "For a committed instruction instance i in state Pendingmemstores(storecontinuation), and an unpropagated memory store operation mso in i.memstores, mso can be propagated if:", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Propagate store operation", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1057, + 1061 + ] + }, + { + "chunk_id": "chunk_b968b1a1", + "text": "An uncommitted `sc` instruction instance i, from hart h, in state Pendingmemstores(storecontinuation), with a paired `lr` i' that has been satisfied by some store slices msoss, can be committed and propagated at the same time if:", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Commit and propagate store operation of an `sc`", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1105, + 1109 + ] + }, + { + "chunk_id": "chunk_8fa66658", + "text": "An `sc` instruction instance i in state Pendingmemstores(storecontinuation), that has not propagated its memory store operation, can always be made to fail.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Late `sc` fail", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1130, + 1132 + ] + }, + { + "chunk_id": "chunk_782f03af", + "text": "A store instruction instance i in state Pendingmemstores(storecontinuation), for which all the memory store operations in i.memstores have been propagated, can always be completed (not to be confused with finished).", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Complete store operations", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1140, + 1145 + ] + }, + { + "chunk_id": "chunk_fe8e0253", + "text": "Action: update the state of i to Plain(storecontinuation(true)).", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Complete store operations", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1140, + 1145 + ] + }, + { + "chunk_id": "chunk_8d6cae47", + "text": "An AMO instruction instance i in state Pendingmemloads(loadcontinuation) can perform its memory access if it is possible to perform the following sequence of transitions with no intervening transitions:", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Satisfy, commit and propagate operations of an AMO", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1150, + 1153 + ] + }, + { + "chunk_id": "chunk_f580db65", + "text": "and in addition, the condition of , with the exception of not requiring i to be in state Plain(Done), holds after those transitions.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Satisfy, commit and propagate operations of an AMO", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1163, + 1168 + ] + }, + { + "chunk_id": "chunk_87ba038a", + "text": "Action: perform the above sequence of transitions (this does not include ), one after the other, with no intervening transitions.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Satisfy, commit and propagate operations of an AMO", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1163, + 1168 + ] + }, + { + "chunk_id": "chunk_a29af968", + "text": "A fence instruction instance i in state Plain(Fence(kind, nextstate)) can be committed if:", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Commit fence", + "confidence": "medium", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 1171, + 1172 + ] + }, + { + "chunk_id": "chunk_474d9742", + "text": "An instruction instance i in state Plain(Readreg(regname, readcont)) can do a register read of regname if every instruction instance that it needs to read from has already performed the expected regname register write.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Register read", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1189, + 1192 + ] + }, + { + "chunk_id": "chunk_df044385", + "text": "Let readsources include, for each bit of regname, the write to that bit by the most recent (in program order) instruction instance that can write to that bit, if any.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Register read", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1194, + 1198 + ] + }, + { + "chunk_id": "chunk_38aa5961", + "text": "If there is no such instruction, the source is the initial register value from initialregisterstate.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Register read", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1194, + 1198 + ] + }, + { + "chunk_id": "chunk_8c84d2cb", + "text": "Let regvalue be the value assembled from readsources.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Register read", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1194, + 1198 + ] + }, + { + "chunk_id": "chunk_5ce7ef6c", + "text": "where deps is a pair of the set of all readsources from i.regreads, and a flag that is true iff i is a load instruction instance that has already been entirely satisfied.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Register write", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1215, + 1218 + ] + }, + { + "chunk_id": "chunk_1504e0ec", + "text": "An instruction instance i in state Plain(Internal(nextstate)) can always do that pseudocode-internal step.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Pseudocode internal step", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1223, + 1226 + ] + }, + { + "chunk_id": "chunk_f8e98720", + "text": "The model covers user-level RV64I and RV64A.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Limitations", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1280, + 1293 + ] + }, + { + "chunk_id": "chunk_d90dd08c", + "text": "In particular, it does not support the misaligned atomicity granule PMA or the total store ordering extension \"Ztso\".", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Limitations", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1280, + 1293 + ] + }, + { + "chunk_id": "chunk_e5a0ab97", + "text": "This will involve, mostly, writing Sail code for the instructions, with minimal, if any, changes to the concurrency model. * The model covers only normal memory accesses (it does not handle I/O accesses). * The model does not cover TLB-related effects. * The model assumes the instruction memory is fixed.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Limitations", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1280, + 1293 + ] + }, + { + "chunk_id": "chunk_780250bc", + "text": "In particular, the transition does not generate memory load operations, and the shared memory is not involved in the transition.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Limitations", + "confidence": "medium", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1280, + 1293 + ] + }, + { + "chunk_id": "chunk_a8823504", + "text": "Instead, the model depends on an external oracle that provides an opcode when given a memory location. * The model does not cover exceptions, traps and interrupts.", + "source_file": "src/unpriv/mm-formal.adoc", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Limitations", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 1280, + 1293 + ] + } + ] + }, + { + "file": "src/unpriv/preface.adoc", + "chunks": [ + { + "chunk_id": "chunk_0a569f46", + "text": "However, it remains the only standard instruction-fetch coherence mechanism. * Removed prohibitions on using RV32E with other extensions. * Removed platform-specific mandates that certain encodings produce illegal-instruction exceptions in RV32E and RV64I chapters. * Counter/timer instructions are now not considered part of the mandatory base ISA, and so CSR instructions were moved into separate chapter and marked as version 2.0, with the unprivileged counters moved into another separate chapter.", + "source_file": "src/unpriv/preface.adoc", + "section": "Preamble > Preface", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 443, + 503 + ] + }, + { + "chunk_id": "chunk_604e7a05", + "text": "The counters are not ready for ratification as there are outstanding issues, including counter inaccuracies. * A CSR-access ordering model has been added. * Explicitly defined the 16-bit half-precision floating-point format for floating-point instructions in the 2-bit fmt field. * Defined the signed-zero behavior of FMIN.fmt and FMAX.fmt, and changed their behavior on signaling-NaN inputs to conform to the `minimumNumber` and `maximumNumber` operations in the proposed IEEE 754-201x specification. * The memory consistency model, RVWMO, has been defined. * The \"Zam\" extension, which permits misaligned AMOs and specifies their semantics, has been defined. * The \"Ztso\" extension, which enforces a stricter memory consistency model than RVWMO, has been defined. * Improvements to the description and commentary. * Defined the term `IALIGN` as shorthand to describe the instruction-address alignment constraint. * Removed text of `P` extension chapter as now superseded by active task group documents. * Removed text of `V` extension chapter as now superseded by separate vector extension draft document.", + "source_file": "src/unpriv/preface.adoc", + "section": "Preamble > Preface", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 443, + 503 + ] + }, + { + "chunk_id": "chunk_e5172c01", + "text": "Numerous additions and improvements to the commentary sections. * Separate version numbers for each chapter. * Modification to long instruction encodings >64 bits to avoid moving the rd specifier in very long instruction formats. * CSR instructions are now described in the base integer format where the counter registers are introduced, as opposed to only being introduced later in the floating-point section (and the companion privileged architecture manual). * The SCALL and SBREAK instructions have been renamed to `ECALL` and `EBREAK`, respectively.", + "source_file": "src/unpriv/preface.adoc", + "section": "Preamble > Preface", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 580, + 601 + ] + }, + { + "chunk_id": "chunk_6f88d834", + "text": "The ISA has been divided into an integer base with several standard extensions. * The instruction formats have been rearranged to make immediate encoding more efficient. * The base ISA has been defined to have a little-endian memory system, with big-endian or bi-endian as non-standard variants. * Load-Reserved/Store-Conditional (`LR/SC`) instructions have been added in the atomic instruction extension. * `AMOs` and `LR/SC` can support the release consistency model. * The `FENCE` instruction provides finer-grain memory and I/O orderings. * An `AMO` for fetch-and-`XOR` (`AMOXOR`) has been added, and the encoding for `AMOSWAP` has been changed to make room. * The `AUIPC` instruction, which adds a 20-bit upper immediate to the `PC`, replaces the `RDNPC` instruction, which only read the current `PC` value.", + "source_file": "src/unpriv/preface.adoc", + "section": "Preamble > Preface", + "confidence": "medium", + "parameter_class": "SW_rule", + "parameter_type": "range", + "line_range": [ + 610, + 658 + ] + }, + { + "chunk_id": "chunk_1864b5b7", + "text": "This change simplifies datapath design. * `FCLASS.S` and `FCLASS.D` floating-point classify instructions have been added. * A simpler NaN generation and propagation scheme has been adopted. * For `RV32I`, the system performance counters have been extended to 64-bits wide, with separate read access to the upper and lower 32 bits. * Canonical `NOP` and `MV` encodings have been defined. * Standard instruction-length encodings have been defined for 48-bit, 64-bit, and >64-bit instructions. * Description of a 128-bit address space variant, `RV128`, has been added. * Major opcodes in the 32-bit base instruction format have been allocated for user-defined custom extensions. * A typographical error that suggested that stores source their data from rd has been corrected to refer to rs2.", + "source_file": "src/unpriv/preface.adoc", + "section": "Preamble > Preface", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 610, + 658 + ] + } + ] + }, + { + "file": "src/unpriv/q-st-ext.adoc", + "chunks": [ + { + "chunk_id": "chunk_5519f459", + "text": "New 128-bit variants of LOAD-FP and STORE-FP instructions are added, encoded with a new value for the funct3 width field.", + "source_file": "src/unpriv/q-st-ext.adoc", + "section": "Preamble > \"Q\" Extension for Quad-Precision Floating-Point, Version 2.2 > Quad-Precision Load and Store Instructions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 16, + 18 + ] + }, + { + "chunk_id": "chunk_e86a31c5", + "text": "FLQ and FSQ are only guaranteed to execute atomically if the effective address is naturally aligned and XLEN=128.", + "source_file": "src/unpriv/q-st-ext.adoc", + "section": "Preamble > \"Q\" Extension for Quad-Precision Floating-Point, Version 2.2 > Quad-Precision Load and Store Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 24, + 26 + ] + }, + { + "chunk_id": "chunk_ada16a4c", + "text": "A new supported format is added to the format field of most instructions, as shown in", + "source_file": "src/unpriv/q-st-ext.adoc", + "section": "Preamble > \"Q\" Extension for Quad-Precision Floating-Point, Version 2.2 > Quad-Precision Load and Store Instructions > Quad-Precision Computational Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 34, + 35 + ] + }, + { + "chunk_id": "chunk_fbe9ffb6", + "text": "These instructions are defined analogously to the double-precision-to-integer and integer-to-double-precision conversion instructions. FCVT.W.Q or FCVT.L.Q converts a quad-precision floating-point number to a signed 32-bit or 64-bit integer, respectively. FCVT.Q.W or FCVT.Q.L converts a 32-bit or 64-bit signed integer, respectively, into a quad-precision floating-point number. FCVT.WU.Q, FCVT.LU.Q, FCVT.Q.WU, and FCVT.Q.LU variants convert to or from unsigned integer values. FCVT.L[U].Q and FCVT.Q.L[U] are RV64-only instructions.", + "source_file": "src/unpriv/q-st-ext.adoc", + "section": "Preamble > \"Q\" Extension for Quad-Precision Floating-Point, Version 2.2 > Quad-Precision Load and Store Instructions > Quad-Precision Convert and Move Instructions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 59, + 68 + ] + }, + { + "chunk_id": "chunk_01b06710", + "text": "FMV.X.Q and FMV.Q.X instructions are not provided in RV32 or RV64, so quad-precision bit patterns must be moved to the integer registers via memory.", + "source_file": "src/unpriv/q-st-ext.adoc", + "section": "Preamble > \"Q\" Extension for Quad-Precision Floating-Point, Version 2.2 > Quad-Precision Load and Store Instructions > Quad-Precision Convert and Move Instructions", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 95, + 97 + ] + } + ] + }, + { + "file": "src/unpriv/rationale.adoc", + "chunks": [ + { + "chunk_id": "chunk_78b10a24", + "text": "The PAUSE instruction hints to a hart that it should temporarily reduce its rate of execution.", + "source_file": "src/unpriv/rationale.adoc", + "section": "Preamble > Historical Rationale for Extensions > \"Zihintpause\" Extension for Pause Hint", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 16, + 19 + ] + }, + { + "chunk_id": "chunk_836d2946", + "text": "Much of the debate surrounding this extension centered on whether a facility similar to x86's MONITOR/MWAIT should instead be provided.", + "source_file": "src/unpriv/rationale.adoc", + "section": "Preamble > Historical Rationale for Extensions > \"Zihintpause\" Extension for Pause Hint", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 21, + 29 + ] + }, + { + "chunk_id": "chunk_b08329c6", + "text": "Two conditional-zero instructions are included: one that writes zero if the comparand is zero, and one that does so if the comparand is nonzero.", + "source_file": "src/unpriv/rationale.adoc", + "section": "Preamble > Historical Rationale for Extensions > \"Zicond\" Extension for Integer Conditional Operations", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 58, + 61 + ] + }, + { + "chunk_id": "chunk_235ff1dc", + "text": "While compare-and-swap for XLEN wide data may be accomplished using LR/SC, the CAS atomic instructions scale better to highly parallel systems than LR/SC.", + "source_file": "src/unpriv/rationale.adoc", + "section": "Preamble > Historical Rationale for Extensions > \"Zacas\" Extension for Atomic Compare-and-Swap (CAS) Instructions", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 65, + 74 + ] + }, + { + "chunk_id": "chunk_44100064", + "text": "Many lock-free algorithms, such as a lock-free queue, require manipulation of pointer variables. A simple CAS operation may not be sufficient to guard against what is commonly referred to as the ABA problem in such algorithms that manipulate pointer variables.", + "source_file": "src/unpriv/rationale.adoc", + "section": "Preamble > Historical Rationale for Extensions > \"Zacas\" Extension for Atomic Compare-and-Swap (CAS) Instructions", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 65, + 74 + ] + }, + { + "chunk_id": "chunk_13377cb9", + "text": "Emulation of narrower AMOs through wider AMO* instructions on non-idempotent IO memory regions may result in unintended side effects.", + "source_file": "src/unpriv/rationale.adoc", + "section": "Preamble > Historical Rationale for Extensions > \"Zabha\" Extension for Byte and Halfword Atomic Memory Operations, Version 1.0", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 94, + 95 + ] + }, + { + "chunk_id": "chunk_c314bd1f", + "text": "When FP16 (officially called binary16) was first introduced by IEEE 754-2008, it was just an interchange format.", + "source_file": "src/unpriv/rationale.adoc", + "section": "Preamble > Historical Rationale for Extensions > \"Zfbfmin\" Extension for Scalar BFloat16 Operations", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 114, + 117 + ] + }, + { + "chunk_id": "chunk_5195fae5", + "text": "However, they also found that intermediate values were much better when accumulated into a higher precision.", + "source_file": "src/unpriv/rationale.adoc", + "section": "Preamble > Historical Rationale for Extensions > \"Zfbfmin\" Extension for Scalar BFloat16 Operations", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 132, + 144 + ] + }, + { + "chunk_id": "chunk_0ea19875", + "text": "There was the added benefit that smaller multiplication blocks could be created for the FP16's smaller number of significant bits.", + "source_file": "src/unpriv/rationale.adoc", + "section": "Preamble > Historical Rationale for Extensions > \"Zfbfmin\" Extension for Scalar BFloat16 Operations", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 132, + 144 + ] + }, + { + "chunk_id": "chunk_4f394264", + "text": "Also, more complicated dot product instructions started to show up including those that packed two FP16 numbers in a 32-bit register, multiplied these by another pair of FP16 numbers in another register, added these two products to an FP32 accumulate value in a 3rd register and returned an FP32 result.", + "source_file": "src/unpriv/rationale.adoc", + "section": "Preamble > Historical Rationale for Extensions > \"Zfbfmin\" Extension for Scalar BFloat16 Operations", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 132, + 144 + ] + }, + { + "chunk_id": "chunk_2fe988cf", + "text": "Experts working in machine learning at Google who continued to work with FP32 values noted that the least significant 16 bits of their mantissas were not always needed for good results, even in training.", + "source_file": "src/unpriv/rationale.adoc", + "section": "Preamble > Historical Rationale for Extensions > \"Zfbfmin\" Extension for Scalar BFloat16 Operations", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 146, + 158 + ] + }, + { + "chunk_id": "chunk_27f3ac82", + "text": "They proposed a truncated version of FP32, which was the 16 most significant bits of the FP32 encoding.", + "source_file": "src/unpriv/rationale.adoc", + "section": "Preamble > Historical Rationale for Extensions > \"Zfbfmin\" Extension for Scalar BFloat16 Operations", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 146, + 158 + ] + }, + { + "chunk_id": "chunk_8c52a393", + "text": "Not only did they find that the number of significant bits in BF16 tended to be sufficient for their work (despite being fewer than in FP16), but it was very easy for them to reuse their existing data; FP32 numbers could be readily rounded to BF16 with a minimal amount of work.", + "source_file": "src/unpriv/rationale.adoc", + "section": "Preamble > Historical Rationale for Extensions > \"Zfbfmin\" Extension for Scalar BFloat16 Operations", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 146, + 158 + ] + }, + { + "chunk_id": "chunk_cf9d7b18", + "text": "Furthermore, the even smaller number of the BF16 significant bits enabled even smaller multiplication blocks to be built.", + "source_file": "src/unpriv/rationale.adoc", + "section": "Preamble > Historical Rationale for Extensions > \"Zfbfmin\" Extension for Scalar BFloat16 Operations", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 146, + 158 + ] + } + ] + }, + { + "file": "src/unpriv/rv-32-64g.adoc", + "chunks": [ + { + "chunk_id": "chunk_857b01d9", + "text": "For this purpose, we define a combination of a base ISA (RV32I or RV64I) plus selected standard extensions (IMAFD, Zicsr, Zifencei) as a \"general-purpose\" ISA, and we use the abbreviation G for the IMAFDZicsrZifencei combination of instruction-set extensions.", + "source_file": "src/unpriv/rv-32-64g.adoc", + "section": "Preamble > RV32/64G Instruction Set Listings", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 4, + 10 + ] + }, + { + "chunk_id": "chunk_b8fd51b4", + "text": "Opcodes marked as reserved should be avoided for custom instruction-set extensions as they might be used by future standard extensions.", + "source_file": "src/unpriv/rv-32-64g.adoc", + "section": "Preamble > RV32/64G Instruction Set Listings", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 24, + 30 + ] + }, + { + "chunk_id": "chunk_bef23743", + "text": "Major opcodes marked as custom-0 through custom-3 will be avoided by future standard extensions and are recommended for use by custom instruction-set extensions within the base 32-bit instruction format.", + "source_file": "src/unpriv/rv-32-64g.adoc", + "section": "Preamble > RV32/64G Instruction Set Listings", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 24, + 30 + ] + }, + { + "chunk_id": "chunk_710bb04f", + "text": "| 15+^|*RV32/RV64 Zicsr Standard Extension* 6+^|csr 2+^|rs1 2+^|001 2+^|rd 2+^|1110011 <|CSRRW 6+^|csr 2+^|rs1 2+^|010 2+^|rd 2+^|1110011 <|CSRRS 6+^|csr 2+^|rs1 2+^|011 2+^|rd 2+^|1110011 <|CSRRC 6+^|csr 2+^|uimm 2+^|101 2+^|rd 2+^|1110011 <|CSRRWI 6+^|csr 2+^|uimm 2+^|110 2+^|rd 2+^|1110011 <|CSRRSI 6+^|csr 2+^|uimm 2+^|111 2+^|rd 2+^|1110011 <|CSRRCI |", + "source_file": "src/unpriv/rv-32-64g.adoc", + "section": "Preamble > RV32/64G Instruction Set Listings", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 141, + 150 + ] + }, + { + "chunk_id": "chunk_2ab5c1f5", + "text": "lists the CSRs that have currently been allocated CSR addresses.", + "source_file": "src/unpriv/rv-32-64g.adoc", + "section": "Preamble > RV32/64G Instruction Set Listings", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 440, + 442 + ] + }, + { + "chunk_id": "chunk_ff91fe55", + "text": "The timers, counters, and floating-point CSRs are the only CSRs defined in this specification.", + "source_file": "src/unpriv/rv-32-64g.adoc", + "section": "Preamble > RV32/64G Instruction Set Listings", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 440, + 442 + ] + } + ] + }, + { + "file": "src/unpriv/rvwmo.adoc", + "chunks": [ + { + "chunk_id": "chunk_e1e9daab", + "text": "Under RVWMO, code running on a single hart appears to execute in order from the perspective of other memory instructions in the same hart, but memory instructions from another hart may observe the memory instructions from the first hart being executed in a different order.", + "source_file": "src/unpriv/rvwmo.adoc", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 12, + 20 + ] + }, + { + "chunk_id": "chunk_6f3f6606", + "text": "Therefore, multithreaded code may require explicit synchronization to guarantee ordering between memory instructions from different harts.", + "source_file": "src/unpriv/rvwmo.adoc", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 12, + 20 + ] + }, + { + "chunk_id": "chunk_5dc56f14", + "text": "Each aligned memory instruction that accesses XLEN or fewer bits gives rise to exactly one memory operation, unless specified otherwise.", + "source_file": "src/unpriv/rvwmo.adoc", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 61, + 64 + ] + }, + { + "chunk_id": "chunk_784a1731", + "text": "A misaligned load or store instruction may be decomposed into a set of component memory operations of any granularity. A floating-point load or store of more than XLEN bits may also be decomposed into a set of component memory operations of any granularity.", + "source_file": "src/unpriv/rvwmo.adoc", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 66, + 80 + ] + }, + { + "chunk_id": "chunk_fdd7c4e4", + "text": "However, if misaligned atomics are supported via the misaligned atomicity granule PMA, then AMOs within an atomicity granule are not decomposed, nor are loads and stores defined in the base ISAs, nor are loads and stores of no more than XLEN bits defined in the F, D, and Q extensions.", + "source_file": "src/unpriv/rvwmo.adoc", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "range", + "line_range": [ + 66, + 80 + ] + }, + { + "chunk_id": "chunk_b31d964e", + "text": "An LR instruction and an SC instruction are said to be paired if the LR precedes the SC in program order and if there are no other LR or SC instructions in between; the corresponding memory operations are said to be paired as well (except in case of a failed SC, where no store operation is generated).", + "source_file": "src/unpriv/rvwmo.adoc", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 82, + 88 + ] + }, + { + "chunk_id": "chunk_b7d10a09", + "text": "The complete list of conditions determining whether an SC must succeed, may succeed, or must fail is defined in .", + "source_file": "src/unpriv/rvwmo.adoc", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 82, + 88 + ] + }, + { + "chunk_id": "chunk_b2c41f08", + "text": "Load and store operations may also carry one or more ordering annotations from the following set: \"acquire-RCpc\", \"acquire-RCsc\", \"release-RCpc\", and \"release-RCsc\".", + "source_file": "src/unpriv/rvwmo.adoc", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 90, + 96 + ] + }, + { + "chunk_id": "chunk_d93d82e0", + "text": "In the context of defining dependencies, a register refers either to an entire general-purpose register, some portion of a CSR, or an entire CSR.", + "source_file": "src/unpriv/rvwmo.adoc", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives > Syntactic Dependencies", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 112, + 116 + ] + }, + { + "chunk_id": "chunk_f15b72fa", + "text": "The granularity at which dependencies are tracked through CSRs is specific to each CSR and is defined in .", + "source_file": "src/unpriv/rvwmo.adoc", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives > Syntactic Dependencies", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 112, + 116 + ] + }, + { + "chunk_id": "chunk_1ada0fd0", + "text": "In the opcode of i, rs1, rs2, or rs3 is set to r * i is a CSR instruction, and in the opcode of i, csr is set to r, unless i is CSRRW or CSRRWI and rd is set to `x0` * r is a CSR and an implicit source register for i, as defined in * r is a CSR that aliases with another source register for i", + "source_file": "src/unpriv/rvwmo.adoc", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives > Syntactic Dependencies", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 129, + 137 + ] + }, + { + "chunk_id": "chunk_16373aa0", + "text": "In the opcode of i, rd is set to r * i is a CSR instruction, and in the opcode of i, csr is set to r, unless i is CSRRS or CSRRC and rs1 is set to `x0` or i is CSRRSI or CSRRCI and uimm[4:0] is set to zero. * r is a CSR and an implicit destination register for i, as defined in * r is a CSR that aliases with another destination register for i", + "source_file": "src/unpriv/rvwmo.adoc", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives > Syntactic Dependencies", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 146, + 154 + ] + }, + { + "chunk_id": "chunk_be1f6a58", + "text": "Instruction j has a syntactic dependency on instruction i via destination register s of i and source register r of j if either of the following hold:", + "source_file": "src/unpriv/rvwmo.adoc", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives > Syntactic Dependencies", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 160, + 163 + ] + }, + { + "chunk_id": "chunk_db9ecc3c", + "text": "b has a syntactic address dependency on a if r is an address source register for j and j has a syntactic dependency on i via source register r", + "source_file": "src/unpriv/rvwmo.adoc", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives > Syntactic Dependencies", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 182, + 185 + ] + }, + { + "chunk_id": "chunk_cf6fb098", + "text": "b has a syntactic data dependency on a if b is a store operation, r is a data source register for j, and j has a syntactic dependency on i via source register r", + "source_file": "src/unpriv/rvwmo.adoc", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives > Syntactic Dependencies", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 187, + 190 + ] + }, + { + "chunk_id": "chunk_6a261dea", + "text": "b has a syntactic control dependency on a if there is an instruction m program-ordered between i and j such that m is a branch or indirect jump and m has a syntactic dependency on i.", + "source_file": "src/unpriv/rvwmo.adoc", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives > Syntactic Dependencies", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 192, + 196 + ] + }, + { + "chunk_id": "chunk_3162a1b3", + "text": "The subset of program order that must be respected by the global memory order is known as preserved program order.", + "source_file": "src/unpriv/rvwmo.adoc", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives > Preserved Program Order", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 200, + 204 + ] + }, + { + "chunk_id": "chunk_532077c9", + "text": "An execution of a RISC-V program obeys the RVWMO memory consistency model only if there exists a global memory order conforming to preserved program order and satisfying the load value axiom, the atomicity axiom, and the progress axiom.", + "source_file": "src/unpriv/rvwmo.adoc", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives > Memory Model Axioms", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 244, + 248 + ] + }, + { + "chunk_id": "chunk_a0e2af4f", + "text": "If r and w are paired load and store operations generated by aligned LR and SC instructions in a hart h, s is a store to byte x, and r returns a value written by s, then s must precede w in the global memory order, and there can be no store from a hart other than h to byte x following s and preceding w in the global memory order.", + "source_file": "src/unpriv/rvwmo.adoc", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives > Memory Model Axioms > Atomicity Axiom", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 267, + 276 + ] + }, + { + "chunk_id": "chunk_64452d3c", + "text": "No memory operation may be preceded in the global memory order by an infinite sequence of other memory operations.", + "source_file": "src/unpriv/rvwmo.adoc", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives > Memory Model Axioms > Progress Axiom", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 279, + 281 + ] + }, + { + "chunk_id": "chunk_3a68286d", + "text": "This section provides a concrete listing of the source and destination registers for each instruction.", + "source_file": "src/unpriv/rvwmo.adoc", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 301, + 304 + ] + }, + { + "chunk_id": "chunk_02a1679a", + "text": "These listings are used in the definition of syntactic dependencies in .", + "source_file": "src/unpriv/rvwmo.adoc", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 301, + 304 + ] + }, + { + "chunk_id": "chunk_bd985468", + "text": "The term \"accumulating CSR\" is used to describe a CSR that is both a source and a destination register, but which carries a dependency only from itself to itself.", + "source_file": "src/unpriv/rvwmo.adoc", + "section": "Preamble > RVWMO Memory Consistency Model, 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"chunk_eb508f38", + "text": "\u2020 The instruction does not carry a dependency from any source register to any destination register", + "source_file": "src/unpriv/rvwmo.adoc", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 323, + 324 + ] + }, + { + "chunk_id": "chunk_09e4ddfb", + "text": "\u2021 The instruction carries dependencies from source register(s) to destination register(s) as specified", + "source_file": "src/unpriv/rvwmo.adoc", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 326, + 327 + ] + }, + { + "chunk_id": "chunk_0c1f40f9", + "text": "|SB |rs1 ^A^, rs2 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+ 719 + ] + } + ] + }, + { + "file": "src/unpriv/vector-examples.adoc", + "chunks": [ + { + "chunk_id": "chunk_cea6364f", + "text": "---- Code using one width for predicate and different width for masked compute. int8t a[]; int32t b[], c[]; for (i=0; i Vector Assembly Code Examples > Vector-vector add example > Example with mixed-width mask and compute.", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 13, + 24 + ] + }, + { + "chunk_id": "chunk_3d957d2d", + "text": "vsetvli x0, a0, e32, m4, ta, mu Vector of 32-bit values. sub a0, a0, a4 Decrement count vmv.v.i v4, 1 Splat immediate to destination vle32.v v4, (a3), v0.t Load requested elements of C, others undisturbed sll t1, a4, 2 add a3, a3, t1 Bump pointer. vse32.v v4, (a2) Store b[i]. add a2, a2, t1 Bump pointer. bnez a0, loop Any more? ----", + "source_file": "src/unpriv/vector-examples.adoc", + "section": "Preamble > Vector Assembly Code Examples > Vector-vector add example > Example with mixed-width mask and compute.", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 26, + 35 + ] + }, + { + "chunk_id": "chunk_aa783c15", + "text": "loop: vsetvli t0, a0, e8, m1, ta, ma Use 8b elements. vle8.v v0, (a1) Get x[i] sub a0, a0, t0 Decrement element count add a1, a1, t0 x[i] Bump pointer vmslt.vi v0, v0, 5 Set mask in v0 vsetvli x0, x0, e16, m2, ta, mu Use 16b elements. slli t0, t0, 1 Multiply by 2 bytes vle16.v v2, (a2), v0.t z[i] = a[i] case vmnot.m v0, v0 Invert v0 add a2, a2, t0 a[i] bump pointer vle16.v v2, (a3), v0.t z[i] = b[i] case add a3, a3, t0 b[i] bump pointer vse16.v v2, (a4) Store z add a4, a4, t0 z[i] bump pointer bnez a0, loop ----", + "source_file": "src/unpriv/vector-examples.adoc", + "section": "Preamble > Vector Assembly Code Examples > Vector-vector add example > Conditional example", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 49, + 65 + ] + }, + { + "chunk_id": "chunk_745c57da", + "text": "---- v1 = v1 / v2 to almost 23 bits of precision.", + "source_file": "src/unpriv/vector-examples.adoc", + "section": "Preamble > Vector Assembly Code Examples > Vector-vector add example > Division approximation example", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 80, + 81 + ] + }, + { + "chunk_id": "chunk_8a9760cd", + "text": "---- v1 = sqrt(v1) to more than 23 bits of precision.", + "source_file": "src/unpriv/vector-examples.adoc", + "section": "Preamble > Vector Assembly Code Examples > Vector-vector add example > Square root approximation example", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 96, + 97 + ] + }, + { + "chunk_id": "chunk_9bece716", + "text": "fmv.w.x ft0, x0 Mask off zero inputs vmfne.vf v0, v1, ft0 to avoid DZ exception vfrsqrt7.v v2, v1, v0.t Estimate r ~= 1/sqrt(v1) vmfne.vf v0, v2, ft0, v0.t Mask off +inf to avoid NV li t0, 0x3f800000 fli.s ft0, 0.5 vmv.v.x v5, t0 Splat 1.0 vfmul.vv v3, v1, v2, v0.t t = v1 r vfmul.vf v4, v2, ft0, v0.t 0.5 r vfmsub.vv v3, v2, v5, v0.t t r - 1 vfnmsac.vv v2, v3, v4, v0.t r - (0.5 r) (t r - 1) Better estimate of 1/sqrt(v1) vfmul.vv v1, v1, v2, v0.t t = v1 r vfmsub.vv v2, v1, v5, v0.t t r - 1 vfmul.vf v3, v1, ft0, v0.t 0.5 t vfnmsac.vv v1, v2, v3, v0.t t - (0.5 t) (t r - 1) ~ sqrt(v1) to about 23.3 bits ----", + "source_file": "src/unpriv/vector-examples.adoc", + "section": "Preamble > Vector Assembly Code Examples > Vector-vector add example > Square root approximation example", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 99, + 116 + ] + }, + { + "chunk_id": "chunk_1847da71", + "text": "The compiler realizes there are two datatypes within the loop: an 8-bit 'char' and a 64-bit 'long *'.", + "source_file": "src/unpriv/vector-examples.adoc", + "section": "Preamble > Vector Assembly Code Examples > Vector-vector add example > Fractional LMUL example", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 152, + 160 + ] + }, + { + "chunk_id": "chunk_4a871b13", + "text": "Without fractional LMUL, the compiler would be forced to use LMUL=1 for the 8-bit computation and LMUL=8 for the 64-bit computation(s), to have equal number of elements on all computations within the same loop iteration.", + "source_file": "src/unpriv/vector-examples.adoc", + "section": "Preamble > Vector Assembly Code Examples > Vector-vector add example > Fractional LMUL example", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 152, + 160 + ] + }, + { + "chunk_id": "chunk_a4519941", + "text": "Given the large number of 64-bit variables and temporaries required in this loop, the compiler ends up generating a lot of spill code.", + "source_file": "src/unpriv/vector-examples.adoc", + "section": "Preamble > Vector Assembly Code Examples > Vector-vector add example > Fractional LMUL example", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 152, + 160 + ] + }, + { + "chunk_id": "chunk_fabb674b", + "text": "---- .LBB04: %vector.body =>This Inner Loop Header: Depth=1 add s9, a2, s6 vsetvli s1, zero, e8,m1,ta,mu vle8.v v25, (s9) add s1, a3, s6 vle8.v v26, (s1) vadd.vv v25, v26, v25 add s1, a1, s6 vse8.v v25, (s1) add s9, a5, s10 vsetvli s1, zero, e64,m8,ta,mu vle64.v v8, (s9) add s1, a6, s10 vle64.v v16, (s1) add s1, a7, s10 vle64.v v24, (s1) add s1, s3, s10 vle64.v v0, (s1) sd a0, -112(s0) ld a0, -128(s0) vs8r.v v0, (a0) Spill LMUL=8 add s9, t6, s10 add s11, t5, s10 add ra, t2, s10 add s1, t3, s10 vle64.v v0, (s9) ld s9, -136(s0) vs8r.v v0, (s9) Spill LMUL=8 vle64.v v0, (s11) ld s9, -144(s0) vs8r.v v0, (s9) Spill LMUL=8 vle64.v v0, (ra) ld s9, -160(s0) vs8r.v v0, (s9) Spill LMUL=8 vle64.v v0, (s1) ld s1, -152(s0) vs8r.v v0, (s1) Spill LMUL=8 vadd.vv v16, v16, v8 ld s1, -128(s0) vl8r.v v8, (s1) Reload LMUL=8 vadd.vv v8, v8, v24 ld s1, -136(s0) vl8r.v v24, (s1) Reload LMUL=8 ld s1, -144(s0) vl8r.v v0, (s1) Reload LMUL=8 vadd.vv v24, v0, v24 ld s1, -128(s0) vs8r.v v24, (s1) Spill LMUL=8 ld s1, -152(s0) vl8r.v v0, (s1) Reload LMUL=8 ld s1, -160(s0) vl8r.v v24, (s1) Reload LMUL=8 vadd.vv v0, v0, v24 add s1, a4, s10 vse64.v v16, (s1) add s1, s2, s10 vse64.v v8, (s1) vadd.vv v8, v8, v16 add s1, t4, s10 ld s9, -128(s0) vl8r.v v16, (s9) Reload LMUL=8 vse64.v v16, (s1) add s9, t0, s10 vadd.vv v8, v8, v16 vle64.v v16, (s9) add s1, t1, s10 vse64.v v0, (s1) vadd.vv v8, v8, v0 vsll.vi v16, v16, 1 vadd.vv v8, v8, v16 vse64.v v8, (s9) add s6, s6, s7 add s10, s10, s8 bne s6, s4, .LBB04 ----", + "source_file": "src/unpriv/vector-examples.adoc", + "section": "Preamble > Vector Assembly Code Examples > Vector-vector add example > Fractional LMUL example", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 162, + 238 + ] + }, + { + "chunk_id": "chunk_39ed75db", + "text": "---- .LBB04: %vector.body =>This Inner Loop Header: Depth=1 add s9, a2, s6 vsetvli s1, zero, e8,mf2,ta,mu // LMUL=1/2 ! vle8.v v25, (s9) add s1, a3, s6 vle8.v v26, (s1) vadd.vv v25, v26, v25 add s1, a1, s6 vse8.v v25, (s1) add s9, a5, s10 vsetvli s1, zero, e64,m4,ta,mu // LMUL=4 vle64.v v28, (s9) add s1, a6, s10 vle64.v v8, (s1) vadd.vv v28, v8, v28 add s1, a7, s10 vle64.v v8, (s1) add s1, s3, s10 vle64.v v12, (s1) add s1, t6, s10 vle64.v v16, (s1) add s1, t5, s10 vle64.v v20, (s1) add s1, a4, s10 vse64.v v28, (s1) vadd.vv v8, v12, v8 vadd.vv v12, v20, v16 add s1, t2, s10 vle64.v v16, (s1) add s1, t3, s10 vle64.v v20, (s1) add s1, s2, s10 vse64.v v8, (s1) add s9, t4, s10 vadd.vv v16, v20, v16 add s11, t0, s10 vle64.v v20, (s11) vse64.v v12, (s9) add s1, t1, s10 vse64.v v16, (s1) vsll.vi v20, v20, 1 vadd.vv v28, v8, v28 vadd.vv v28, v28, v12 vadd.vv v28, v28, v16 vadd.vv v28, v28, v20 vse64.v v28, (s11) add s6, s6, s7 add s10, s10, s8 bne s6, s4, .LBB04 ----", + "source_file": "src/unpriv/vector-examples.adoc", + "section": "Preamble > Vector Assembly Code Examples > Vector-vector add example > Fractional LMUL example", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 247, + 298 + ] + } + ] + }, + { + "file": "src/unpriv/za.adoc", + "chunks": [ + { + "chunk_id": "chunk_c6ab809e", + "text": "No ordering constraint is implied to accesses to the other domain, and a FENCE instruction should be used to order across both domains.", + "source_file": "src/unpriv/za.adoc", + "section": "Preamble > Atomic Instructions > Specifying Ordering of Atomic Instructions", + "confidence": "medium", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 28, + 34 + ] + }, + { + "chunk_id": "chunk_82d7022b", + "text": "If both bits are clear, no additional ordering constraints are imposed on the atomic memory operation.", + "source_file": "src/unpriv/za.adoc", + "section": "Preamble > Atomic Instructions > Specifying Ordering of Atomic Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 36, + 47 + ] + }, + { + "chunk_id": "chunk_13a4f9a4", + "text": "If both the aq and rl bits are set, the atomic memory operation is sequentially consistent and cannot be observed to happen before any earlier memory operations or after any later memory operations in the same RISC-V hart and to the same address domain.", + "source_file": "src/unpriv/za.adoc", + "section": "Preamble > Atomic Instructions > Specifying Ordering of Atomic Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 36, + 47 + ] + } + ] + }, + { + "file": "src/unpriv/zaamo.adoc", + "chunks": [ + { + "chunk_id": "chunk_3119cc81", + "text": "The atomic memory operation (AMO) instructions perform read-modify-write operations for multiprocessor synchronization and are encoded with an R-type instruction format.", + "source_file": "src/unpriv/zaamo.adoc", + "section": "Preamble > \"Zaamo\" Extension for Atomic Memory Operations", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 5, + 13 + ] + }, + { + "chunk_id": "chunk_ae2d334e", + "text": "For RV64, 32-bit AMOs always sign-extend the value placed in rd, and ignore the upper 32 bits of the original value of rs2.", + "source_file": "src/unpriv/zaamo.adoc", + "section": "Preamble > \"Zaamo\" Extension for Atomic Memory Operations", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 5, + 13 + ] + }, + { + "chunk_id": "chunk_b7f66826", + "text": "If the address is not naturally aligned, an address-misaligned exception or an access-fault exception will be generated.", + "source_file": "src/unpriv/zaamo.adoc", + "section": "Preamble > \"Zaamo\" Extension for Atomic Memory Operations", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 15, + 22 + ] + }, + { + "chunk_id": "chunk_79c3920a", + "text": "The access-fault exception can be generated for a memory access that would otherwise be able to complete except for the misalignment, if the misaligned access should not be emulated.", + "source_file": "src/unpriv/zaamo.adoc", + "section": "Preamble > \"Zaamo\" Extension for Atomic Memory Operations", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 15, + 22 + ] + }, + { + "chunk_id": "chunk_cd713f83", + "text": "If present, the misaligned atomicity granule PMA specifies the size of a misaligned atomicity granule, a power-of-two number of bytes.", + "source_file": "src/unpriv/zaamo.adoc", + "section": "Preamble > \"Zaamo\" Extension for Atomic Memory Operations", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 24, + 34 + ] + }, + { + "chunk_id": "chunk_313d65cf", + "text": "The operations supported are swap, integer add, bitwise AND, bitwise OR, bitwise XOR, and signed and unsigned integer maximum and minimum.", + "source_file": "src/unpriv/zaamo.adoc", + "section": "Preamble > \"Zaamo\" Extension for Atomic Memory Operations", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "range", + "line_range": [ + 36, + 40 + ] + }, + { + "chunk_id": "chunk_585bd9cb", + "text": "If the aq bit is set, then no later memory operations in this RISC-V hart can be observed to take place before the AMO.", + "source_file": "src/unpriv/zaamo.adoc", + "section": "Preamble > \"Zaamo\" Extension for Atomic Memory Operations", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 42, + 50 + ] + }, + { + "chunk_id": "chunk_f76d65e9", + "text": "Conversely, if the rl bit is set, then other RISC-V harts will not observe the AMO before memory accesses preceding the AMO in this RISC-V hart.", + "source_file": "src/unpriv/zaamo.adoc", + "section": "Preamble > \"Zaamo\" Extension for Atomic Memory Operations", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 42, + 50 + ] + } + ] + }, + { + "file": "src/unpriv/zabha.adoc", + "chunks": [ + { + "chunk_id": "chunk_fd5b5a05", + "text": "Emulation of narrower AMOs through wider AMO* instructions on non-idempotent IO memory regions may result in unintended side effects.", + "source_file": "src/unpriv/zabha.adoc", + "section": "Preamble > \"Zabha\" Extension for Byte and Halfword Atomic Memory Operations, Version 1.0", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 16, + 17 + ] + }, + { + "chunk_id": "chunk_22ee40f0", + "text": "If Zacas extension is also implemented, Zabha further provides the `AMOCAS.[B|H]` instructions.", + "source_file": "src/unpriv/zabha.adoc", + "section": "Preamble > \"Zabha\" Extension for Byte and Halfword Atomic Memory Operations, Version 1.0 > Byte and Halfword Atomic Memory Operation Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 33, + 35 + ] + }, + { + "chunk_id": "chunk_c8dcd629", + "text": "Similar to the AMOs specified in the A extension, the Zabha extension mandates that the address contained in the `rs1` register must be naturally aligned to the size of the operand.", + "source_file": "src/unpriv/zabha.adoc", + "section": "Preamble > \"Zabha\" Extension for Byte and Halfword Atomic Memory Operations, Version 1.0 > Byte and Halfword Atomic Memory Operation Instructions", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 56, + 59 + ] + }, + { + "chunk_id": "chunk_33521a87", + "text": "The same exception options as specified in the A extension are applicable in cases where the address is not naturally aligned.", + "source_file": "src/unpriv/zabha.adoc", + "section": "Preamble > \"Zabha\" Extension for Byte and Halfword Atomic Memory Operations, Version 1.0 > Byte and Halfword Atomic Memory Operation Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 56, + 59 + ] + } + ] + }, + { + "file": "src/unpriv/zacas.adoc", + "chunks": [ + { + "chunk_id": "chunk_03c75dd7", + "text": "This extension defines CAS instructions to operate on 32-bit, 64-bit, and 128-bit (RV64 only) data values.", + "source_file": "src/unpriv/zacas.adoc", + "section": "Preamble > \"Zacas\" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 3, + 7 + ] + }, + { + "chunk_id": "chunk_26dbebc1", + "text": "For RV32, `AMOCAS.W` atomically loads a 32-bit data value from address in `rs1`, compares the loaded value to the 32-bit value held in `rd`, and if the comparison is bitwise equal, then stores the 32-bit value held in `rs2` to the original address in `rs1`.", + "source_file": "src/unpriv/zacas.adoc", + "section": "Preamble > \"Zacas\" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 > Word/Doubleword/Quadword CAS (AMOCAS.W/D/Q) Instructions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 25, + 29 + ] + }, + { + "chunk_id": "chunk_8ed7eeeb", + "text": "[listing] ---- temp = mem[X(rs1)] if ( temp X(rd) ) mem[X(rs1)] = X(rs2) X(rd) = temp ----", + "source_file": "src/unpriv/zacas.adoc", + "section": "Preamble > \"Zacas\" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 > Word/Doubleword/Quadword CAS (AMOCAS.W/D/Q) Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 31, + 37 + ] + }, + { + "chunk_id": "chunk_7526b198", + "text": "`AMOCAS.D` is similar to `AMOCAS.W` but operates on 64-bit data values.", + "source_file": "src/unpriv/zacas.adoc", + "section": "Preamble > \"Zacas\" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 > Word/Doubleword/Quadword CAS (AMOCAS.W/D/Q) Instructions", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 39, + 39 + ] + }, + { + "chunk_id": "chunk_8281b82c", + "text": "When the first register of a source register pair is `x0`, then both halves of the pair read as zero.", + "source_file": "src/unpriv/zacas.adoc", + "section": "Preamble > \"Zacas\" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 > Word/Doubleword/Quadword CAS (AMOCAS.W/D/Q) Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 41, + 52 + ] + }, + { + "chunk_id": "chunk_433d4ab0", + "text": "When the first register of a destination register pair is `x0`, then the entire register result is discarded and neither destination register is written.", + "source_file": "src/unpriv/zacas.adoc", + "section": "Preamble > \"Zacas\" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 > Word/Doubleword/Quadword CAS (AMOCAS.W/D/Q) Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 41, + 52 + ] + }, + { + "chunk_id": "chunk_5aa38207", + "text": "[listing] temp0 = mem[X(rs1)+0] temp1 = mem[X(rs1)+4] comp0 = (rd x0) ? 0 : X(rd) comp1 = (rd x0) ? 0 : X(rd+1) swap0 = (rs2 x0) ? 0 : X(rs2) swap1 = (rs2 x0) ? 0 : X(rs2+1) if ( temp0 comp0 ) && ( temp1 comp1 ) mem[X(rs1)+0] = swap0 mem[X(rs1)+4] = swap1 endif if ( rd != x0 ) X(rd) = temp0 X(rd+1) = temp1 endif", + "source_file": "src/unpriv/zacas.adoc", + "section": "Preamble > \"Zacas\" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 > Word/Doubleword/Quadword CAS (AMOCAS.W/D/Q) Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 56, + 70 + ] + }, + { + "chunk_id": "chunk_32959945", + "text": "For RV64, `AMOCAS.W` atomically loads a 32-bit data value from address in `rs1`, compares the loaded value to the lower 32 bits of the value held in `rd`, and if the comparison is bitwise equal, then stores the lower 32 bits of the value held in `rs2` to the original address in `rs1`.", + "source_file": "src/unpriv/zacas.adoc", + "section": "Preamble > \"Zacas\" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 > Word/Doubleword/Quadword CAS (AMOCAS.W/D/Q) Instructions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 72, + 77 + ] + }, + { + "chunk_id": "chunk_c538c32b", + "text": "The 32-bit value loaded from memory is sign-extended and is placed into register `rd`.", + "source_file": "src/unpriv/zacas.adoc", + "section": "Preamble > \"Zacas\" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 > Word/Doubleword/Quadword CAS (AMOCAS.W/D/Q) Instructions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 72, + 77 + ] + }, + { + "chunk_id": "chunk_bc2892e6", + "text": "[listing] temp[31:0] = mem[X(rs1)] if ( temp[31:0] X(rd)[31:0] ) mem[X(rs1)] = X(rs2)[31:0] X(rd) = SignExtend(temp[31:0])", + "source_file": "src/unpriv/zacas.adoc", + "section": "Preamble > \"Zacas\" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 > Word/Doubleword/Quadword CAS (AMOCAS.W/D/Q) Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 79, + 83 + ] + }, + { + "chunk_id": "chunk_2e5194bc", + "text": "For RV64, `AMOCAS.D` atomically loads 64-bits of a data value from address in `rs1`, compares the loaded value to a 64-bit value held in `rd`, and if the comparison is bitwise equal, then stores the 64-bit value held in `rs2` to the original address in `rs1`.", + "source_file": "src/unpriv/zacas.adoc", + "section": "Preamble > \"Zacas\" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 > Word/Doubleword/Quadword CAS (AMOCAS.W/D/Q) Instructions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 85, + 94 + ] + }, + { + "chunk_id": "chunk_8cfea027", + "text": "The operation performed by `AMOCAS.D` for RV64 is as follows: [listing] temp = mem[X(rs1)] if ( temp X(rd) ) mem[X(rs1)] = X(rs2) X(rd) = temp", + "source_file": "src/unpriv/zacas.adoc", + "section": "Preamble > \"Zacas\" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 > Word/Doubleword/Quadword CAS (AMOCAS.W/D/Q) Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 85, + 94 + ] + }, + { + "chunk_id": "chunk_c1f0e826", + "text": "When the first register of a source register pair is `x0`, then both halves of the pair read as zero.", + "source_file": "src/unpriv/zacas.adoc", + "section": "Preamble > \"Zacas\" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 > Word/Doubleword/Quadword CAS (AMOCAS.W/D/Q) Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 96, + 107 + ] + }, + { + "chunk_id": "chunk_bf618e59", + "text": "When the first register of a destination register pair is `x0`, then the entire register result is discarded and neither destination register is written.", + "source_file": "src/unpriv/zacas.adoc", + "section": "Preamble > \"Zacas\" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 > Word/Doubleword/Quadword CAS (AMOCAS.W/D/Q) Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 96, + 107 + ] + }, + { + "chunk_id": "chunk_6d473f6f", + "text": "[listing] temp0 = mem[X(rs1)+0] temp1 = mem[X(rs1)+8] comp0 = (rd x0) ? 0 : X(rd) comp1 = (rd x0) ? 0 : X(rd+1) swap0 = (rs2 x0) ? 0 : X(rs2) swap1 = (rs2 x0) ? 0 : X(rs2+1) if ( temp0 comp0 ) && ( temp1 comp1 ) mem[X(rs1)+0] = swap0 mem[X(rs1)+8] = swap1 endif if ( rd != x0 ) X(rd) = temp0 X(rd+1) = temp1 endif", + "source_file": "src/unpriv/zacas.adoc", + "section": "Preamble > \"Zacas\" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 > Word/Doubleword/Quadword CAS (AMOCAS.W/D/Q) Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 111, + 125 + ] + }, + { + "chunk_id": "chunk_4fb09933", + "text": "And the same exception options apply if the address is not naturally aligned.", + "source_file": "src/unpriv/zacas.adoc", + "section": "Preamble > \"Zacas\" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 > Word/Doubleword/Quadword CAS (AMOCAS.W/D/Q) Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 127, + 131 + ] + }, + { + "chunk_id": "chunk_8fcaf242", + "text": "The memory operation performed by an `AMOCAS.W/D/Q`, when successful, has acquire semantics if `aq` bit is 1 and has release semantics if `rl` bit is 1.", + "source_file": "src/unpriv/zacas.adoc", + "section": "Preamble > \"Zacas\" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 > Word/Doubleword/Quadword CAS (AMOCAS.W/D/Q) Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 133, + 139 + ] + }, + { + "chunk_id": "chunk_116f9aba", + "text": "The memory operation performed by an `AMOCAS.W/D/Q`, when not successful, has acquire semantics if `aq` bit is 1 but does not have release semantics, regardless of `rl`.", + "source_file": "src/unpriv/zacas.adoc", + "section": "Preamble > \"Zacas\" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 > Word/Doubleword/Quadword CAS (AMOCAS.W/D/Q) Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 133, + 139 + ] + }, + { + "chunk_id": "chunk_334c5c8b", + "text": "A FENCE instruction may be used to order the memory read access and, if produced, the memory write access by an `AMOCAS.W/D/Q` instruction.", + "source_file": "src/unpriv/zacas.adoc", + "section": "Preamble > \"Zacas\" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 > Word/Doubleword/Quadword CAS (AMOCAS.W/D/Q) Instructions", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 141, + 142 + ] + } + ] + }, + { + "file": "src/unpriv/zalasr.adoc", + "chunks": [ + { + "chunk_id": "chunk_0ec3bc4e", + "text": "The Zalasr instructions always sign-extend the value placed in rd and ignore the upper bits of the value of rs2.", + "source_file": "src/unpriv/zalasr.adoc", + "section": "Preamble > \"Zalasr\" Atomic Load-Acquire and Store-Release Instructions, Version 1.0 > Load-Acquire and Store-Release Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 20, + 23 + ] + }, + { + "chunk_id": "chunk_b948c696", + "text": "If the address is not naturally aligned, an address-misaligned exception or an access-fault exception will be generated.", + "source_file": "src/unpriv/zalasr.adoc", + "section": "Preamble > \"Zalasr\" Atomic Load-Acquire and Store-Release Instructions, Version 1.0 > Load-Acquire and Store-Release Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 20, + 23 + ] + }, + { + "chunk_id": "chunk_c1db1c03", + "text": "The access-fault exception can be generated for a memory access that would otherwise be able to complete except for the misalignment, if the misaligned access should not be emulated.", + "source_file": "src/unpriv/zalasr.adoc", + "section": "Preamble > \"Zalasr\" Atomic Load-Acquire and Store-Release Instructions, Version 1.0 > Load-Acquire and Store-Release Instructions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 20, + 23 + ] + }, + { + "chunk_id": "chunk_be48df91", + "text": "This load must have the ordering annotation aq and may have ordering annotation rl encoded in the instruction.", + "source_file": "src/unpriv/zalasr.adoc", + "section": "Preamble > \"Zalasr\" Atomic Load-Acquire and Store-Release Instructions, Version 1.0 > Load-Acquire and Store-Release Instructions > Load Acquire", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 64, + 70 + ] + }, + { + "chunk_id": "chunk_811aa6cb", + "text": "The instruction always has an \"acquire-RCsc\" annotation, and if the bit rl is set the instruction has a \"release-RCsc\" annotation. + The versions without the aq bit set are RESERVED. LD.{AQ, AQRL} is RV64-only.", + "source_file": "src/unpriv/zalasr.adoc", + "section": "Preamble > \"Zalasr\" Atomic Load-Acquire and Store-Release Instructions, Version 1.0 > Load-Acquire and Store-Release Instructions > Load Acquire", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 64, + 70 + ] + }, + { + "chunk_id": "chunk_17b7aee1", + "text": "This store must have ordering annotation rl and may have ordering annotation aq encoded in the instruction.", + "source_file": "src/unpriv/zalasr.adoc", + "section": "Preamble > \"Zalasr\" Atomic Load-Acquire and Store-Release Instructions, Version 1.0 > Load-Acquire and Store-Release Instructions > Store Release", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 110, + 115 + ] + }, + { + "chunk_id": "chunk_cef22543", + "text": "The instruction always has an \"release-RCsc\" annotation, and if the bit aq is set the instruction has a \"acquire-RCsc\" annotation. + The versions without the rl bit set are RESERVED. SD.{RL, AQRL} is RV64-only.", + "source_file": "src/unpriv/zalasr.adoc", + "section": "Preamble > \"Zalasr\" Atomic Load-Acquire and Store-Release Instructions, Version 1.0 > Load-Acquire and Store-Release Instructions > Store Release", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 110, + 115 + ] + } + ] + }, + { + "file": "src/unpriv/zalrsc.adoc", + "chunks": [ + { + "chunk_id": "chunk_0867a8c1", + "text": "Complex atomic memory operations on a single memory word or doubleword are performed with the load-reserved (LR) and store-conditional (SC) instructions. LR.W loads a word from the address in rs1, places the sign-extended value in rd, and registers a reservation set\u2014a set of bytes that subsumes the bytes in the addressed word. SC.W conditionally writes a word in rs2 to the address in rs1: the SC.W succeeds only if the reservation is still valid and the reservation set contains the bytes being written.", + "source_file": "src/unpriv/zalrsc.adoc", + "section": "Preamble > \"Zalrsc\" Extension for Load-Reserved/Store-Conditional Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 5, + 25 + ] + }, + { + "chunk_id": "chunk_fdca9cc1", + "text": "If the SC.W succeeds, the instruction writes the word in rs2 to memory, and it writes zero to rd.", + "source_file": "src/unpriv/zalrsc.adoc", + "section": "Preamble > \"Zalrsc\" Extension for Load-Reserved/Store-Conditional Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 5, + 25 + ] + }, + { + "chunk_id": "chunk_2b6efded", + "text": "If the SC.W fails, the instruction does not write to memory, and it writes a nonzero value to rd.", + "source_file": "src/unpriv/zalrsc.adoc", + "section": "Preamble > \"Zalrsc\" Extension for Load-Reserved/Store-Conditional Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 5, + 25 + ] + }, + { + "chunk_id": "chunk_4481135b", + "text": "No SC.W instruction shall retire unless it passes memory permission checks, but it is UNSPECIFIED whether any side effects of implicit address translation and protection memory accesses (such as setting a page-table entry D bit) occur on a failed SC.W.", + "source_file": "src/unpriv/zalrsc.adoc", + "section": "Preamble > \"Zalrsc\" Extension for Load-Reserved/Store-Conditional Instructions", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 5, + 25 + ] + }, + { + "chunk_id": "chunk_441cd4d5", + "text": "For the purposes of memory protection, a failed SC.W may be treated like a store.", + "source_file": "src/unpriv/zalrsc.adoc", + "section": "Preamble > \"Zalrsc\" Extension for Load-Reserved/Store-Conditional Instructions", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 5, + 25 + ] + }, + { + "chunk_id": "chunk_1434282b", + "text": "Portable software should only assume the failure code will be non-zero.", + "source_file": "src/unpriv/zalrsc.adoc", + "section": "Preamble > \"Zalrsc\" Extension for Load-Reserved/Store-Conditional Instructions", + "confidence": "medium", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 27, + 29 + ] + }, + { + "chunk_id": "chunk_0b8622dd", + "text": "If the address is not naturally aligned, an address-misaligned exception or an access-fault exception will be generated.", + "source_file": "src/unpriv/zalrsc.adoc", + "section": "Preamble > \"Zalrsc\" Extension for Load-Reserved/Store-Conditional Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 31, + 49 + ] + }, + { + "chunk_id": "chunk_63fb69e8", + "text": "The access-fault exception can be generated for a memory access that would otherwise be able to complete except for the misalignment, if the misaligned access should not be emulated.", + "source_file": "src/unpriv/zalrsc.adoc", + "section": "Preamble > \"Zalrsc\" Extension for Load-Reserved/Store-Conditional Instructions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 31, + 49 + ] + }, + { + "chunk_id": "chunk_2bfa263e", + "text": "An SC may succeed only if no store from another hart to the reservation set can be observed to have occurred between the LR and the SC, and if there is no other SC between the LR and itself in program order.", + "source_file": "src/unpriv/zalrsc.adoc", + "section": "Preamble > \"Zalrsc\" Extension for Load-Reserved/Store-Conditional Instructions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 31, + 49 + ] + }, + { + "chunk_id": "chunk_540c678d", + "text": "An SC may succeed only if no write from a device other than a hart to the bytes accessed by the LR instruction can be observed to have occurred between the LR and SC.", + "source_file": "src/unpriv/zalrsc.adoc", + "section": "Preamble > \"Zalrsc\" Extension for Load-Reserved/Store-Conditional Instructions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 31, + 49 + ] + }, + { + "chunk_id": "chunk_f5eaf65f", + "text": "The SC must fail if the address is not within the reservation set of the most recent LR in program order.", + "source_file": "src/unpriv/zalrsc.adoc", + "section": "Preamble > \"Zalrsc\" Extension for Load-Reserved/Store-Conditional Instructions", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 51, + 61 + ] + }, + { + "chunk_id": "chunk_f5e22b0e", + "text": "The SC must fail if a store to the reservation set from another hart can be observed to occur between the LR and SC.", + "source_file": "src/unpriv/zalrsc.adoc", + "section": "Preamble > \"Zalrsc\" Extension for Load-Reserved/Store-Conditional Instructions", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 51, + 61 + ] + }, + { + "chunk_id": "chunk_9d0b2a89", + "text": "The SC must fail if a write from some other device to the bytes accessed by the LR can be observed to occur between the LR and SC. (", + "source_file": "src/unpriv/zalrsc.adoc", + "section": "Preamble > \"Zalrsc\" Extension for Load-Reserved/Store-Conditional Instructions", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 51, + 61 + ] + }, + { + "chunk_id": "chunk_63eb6051", + "text": "If such a device writes the reservation set but does not write the bytes accessed by the LR, the SC may or may not fail.) An SC must fail if there is another SC (to any address) between the LR and the SC in program order.", + "source_file": "src/unpriv/zalrsc.adoc", + "section": "Preamble > \"Zalrsc\" Extension for Load-Reserved/Store-Conditional Instructions", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 51, + 61 + ] + }, + { + "chunk_id": "chunk_8bc79d34", + "text": "Software should not set the rl bit on an LR instruction unless the aq bit is also set, nor should software set the aq bit on an SC instruction unless the rl bit is also set. LR.rl and SC.aq instructions are not guaranteed to provide any stronger ordering than those with both bits clear, but may result in lower performance.", + "source_file": "src/unpriv/zalrsc.adoc", + "section": "Preamble > \"Zalrsc\" Extension for Load-Reserved/Store-Conditional Instructions", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 66, + 70 + ] + }, + { + "chunk_id": "chunk_61d2b5da", + "text": "The loop comprises only an LR/SC sequence and code to retry the sequence in the case of failure, and must comprise at most 16 instructions placed sequentially in memory. * An LR/SC sequence begins with an LR instruction and ends with an SC instruction.", + "source_file": "src/unpriv/zalrsc.adoc", + "section": "Preamble > \"Zalrsc\" Extension for Load-Reserved/Store-Conditional Instructions > Eventual Success of Store-Conditional Instructions", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 78, + 95 + ] + }, + { + "chunk_id": "chunk_c74d91c7", + "text": "Compressed forms of the aforementioned ''I'' instructions in the C (hence Zca) and Zcb extensions are also permitted. * The code to retry a failing LR/SC sequence can contain backwards jumps and/or branches to repeat the LR/SC sequence, but otherwise has the same constraint as the code between the LR and SC. * The LR and SC addresses must lie within a memory region with the LR/SC eventuality property.", + "source_file": "src/unpriv/zalrsc.adoc", + "section": "Preamble > \"Zalrsc\" Extension for Load-Reserved/Store-Conditional Instructions > Eventual Success of Store-Conditional Instructions", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 78, + 95 + ] + }, + { + "chunk_id": "chunk_80abc89b", + "text": "The execution environment is responsible for communicating which regions have this property. * The SC must be to the same effective address and of the same data size as the latest LR executed by the same hart.", + "source_file": "src/unpriv/zalrsc.adoc", + "section": "Preamble > \"Zalrsc\" Extension for Load-Reserved/Store-Conditional Instructions > Eventual Success of Store-Conditional Instructions", + "confidence": "very_high", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 78, + 95 + ] + }, + { + "chunk_id": "chunk_297259b9", + "text": "If a hart H enters a constrained LR/SC loop, the execution environment must guarantee that one of the following events eventually occurs:", + "source_file": "src/unpriv/zalrsc.adoc", + "section": "Preamble > \"Zalrsc\" Extension for Load-Reserved/Store-Conditional Instructions > Eventual Success of Store-Conditional Instructions", + "confidence": "very_high", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 102, + 103 + ] + }, + { + "chunk_id": "chunk_616fff44", + "text": "H or some other hart executes a successful SC to the reservation set of the LR instruction in H's constrained LR/SC loops. * Some other hart executes an unconditional store or AMO instruction to the reservation set of the LR instruction in H's constrained LR/SC loop, or some other device in the system writes to that reservation set. * H executes a branch or jump that exits the constrained LR/SC loop. * H traps.", + "source_file": "src/unpriv/zalrsc.adoc", + "section": "Preamble > \"Zalrsc\" Extension for Load-Reserved/Store-Conditional Instructions > Eventual Success of Store-Conditional Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 105, + 111 + ] + } + ] + }, + { + "file": "src/unpriv/zama.adoc", + "chunks": [ + { + "chunk_id": "chunk_6bd45ee2", + "text": "If the Zama16b extension is implemented, then the in main memory regions with both the cacheability and coherence PMAs is 16 bytes.", + "source_file": "src/unpriv/zama.adoc", + "section": "Preamble > Zama16b Extension for 16-byte Misaligned Atomicity, Version 1.0", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "range", + "line_range": [ + 3, + 8 + ] + }, + { + "chunk_id": "chunk_3ee34466", + "text": "Misaligned loads, stores, and AMOs to main memory regions that do not cross a naturally aligned 16-byte boundary are atomic.", + "source_file": "src/unpriv/zama.adoc", + "section": "Preamble > Zama16b Extension for 16-byte Misaligned Atomicity, Version 1.0", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 3, + 8 + ] + } + ] + }, + { + "file": "src/unpriv/zars.adoc", + "chunks": [ + { + "chunk_id": "chunk_2d18870e", + "text": "The Za128rs extension requires that the reservation sets used by the instructions in the Zalrsc extension be contiguous, naturally aligned, and at most 128 bytes in size.", + "source_file": "src/unpriv/zars.adoc", + "section": "Preamble > Za128rs Extension for Reservation-Set Size, Version 1.0", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 3, + 5 + ] + }, + { + "chunk_id": "chunk_36b588c9", + "text": "The Za64rs extension requires that the reservation sets used by the instructions in the Zalrsc extension be contiguous, naturally aligned, and at most 64 bytes in size.", + "source_file": "src/unpriv/zars.adoc", + "section": "Preamble > Za128rs Extension for Reservation-Set Size, Version 1.0 > Za64rs Extension for Reservation-Set Size, Version 1.0", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 10, + 12 + ] + } + ] + }, + { + "file": "src/unpriv/zawrs.adoc", + "chunks": [ + { + "chunk_id": "chunk_10ba508f", + "text": "The producer may be code executing on a RISC-V hart, an accelerator device, an external I/O agent.", + "source_file": "src/unpriv/zawrs.adoc", + "section": "Preamble > \"Zawrs\" Extension for Wait-on-Reservation-Set instructions, Version 1.01", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 10, + 12 + ] + }, + { + "chunk_id": "chunk_37177c9c", + "text": "Then a subsequent `WRS.NTO` instruction would cause the hart to temporarily stall execution in a low-power state until a store occurs to the reservation set or an interrupt is observed.", + "source_file": "src/unpriv/zawrs.adoc", + "section": "Preamble > \"Zawrs\" Extension for Wait-on-Reservation-Set instructions, Version 1.01", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 19, + 26 + ] + }, + { + "chunk_id": "chunk_a9c6a859", + "text": "Sometimes the program waiting on a memory update may also need to carry out a task at a future time or otherwise place an upper bound on the wait.", + "source_file": "src/unpriv/zawrs.adoc", + "section": "Preamble > \"Zawrs\" Extension for Wait-on-Reservation-Set instructions, Version 1.01", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 28, + 35 + ] + }, + { + "chunk_id": "chunk_c0e90a23", + "text": "To support such use cases a second instruction `WRS.STO` (WRS-with-short-timeout) is provided that works like `WRS.NTO` but bounds the stall duration to an implementation-define short timeout such that the stall is terminated on the timeout if no other conditions have occurred to terminate the stall.", + "source_file": "src/unpriv/zawrs.adoc", + "section": "Preamble > \"Zawrs\" Extension for Wait-on-Reservation-Set instructions, Version 1.01", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 28, + 35 + ] + }, + { + "chunk_id": "chunk_ba3a3671", + "text": "The program using this instruction may then determine if its deadline has been reached.", + "source_file": "src/unpriv/zawrs.adoc", + "section": "Preamble > \"Zawrs\" Extension for Wait-on-Reservation-Set instructions, Version 1.01", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 28, + 35 + ] + }, + { + "chunk_id": "chunk_64af53f2", + "text": "The `WRS.NTO` and `WRS.STO` instructions cause the hart to temporarily stall execution in a low-power state as long as the reservation set is valid and no pending interrupts, even if disabled, are observed.", + "source_file": "src/unpriv/zawrs.adoc", + "section": "Preamble > \"Zawrs\" Extension for Wait-on-Reservation-Set instructions, Version 1.01 > Wait-on-Reservation-Set Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 40, + 44 + ] + }, + { + "chunk_id": "chunk_a934267f", + "text": "Hart execution may be stalled while the following conditions are all satisfied: [loweralpha] .", + "source_file": "src/unpriv/zawrs.adoc", + "section": "Preamble > \"Zawrs\" Extension for Wait-on-Reservation-Set instructions, Version 1.01 > Wait-on-Reservation-Set Instructions", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 59, + 63 + ] + }, + { + "chunk_id": "chunk_c07c51b9", + "text": "If `WRS.STO`, a \"short\" duration since start of stall has not elapsed .", + "source_file": "src/unpriv/zawrs.adoc", + "section": "Preamble > \"Zawrs\" Extension for Wait-on-Reservation-Set instructions, Version 1.01 > Wait-on-Reservation-Set Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 59, + 63 + ] + }, + { + "chunk_id": "chunk_fd414941", + "text": "No pending interrupt is observed (see the rules below)", + "source_file": "src/unpriv/zawrs.adoc", + "section": "Preamble > \"Zawrs\" Extension for Wait-on-Reservation-Set instructions, Version 1.01 > Wait-on-Reservation-Set Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 59, + 63 + ] + }, + { + "chunk_id": "chunk_4d5a2864", + "text": "`WRS.NTO` and `WRS.STO` instructions follow the rules of the `WFI` instruction for resuming execution on a pending interrupt.", + "source_file": "src/unpriv/zawrs.adoc", + "section": "Preamble > \"Zawrs\" Extension for Wait-on-Reservation-Set instructions, Version 1.01 > Wait-on-Reservation-Set Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 68, + 69 + ] + }, + { + "chunk_id": "chunk_7c2258e6", + "text": "When the `TW` (Timeout Wait) bit in `mstatus` is set and `WRS.NTO` is executed in any privilege mode other than M mode, and it does not complete within an implementation-specific bounded time limit, the `WRS.NTO` instruction will cause an illegal-instruction exception.", + "source_file": "src/unpriv/zawrs.adoc", + "section": "Preamble > \"Zawrs\" Extension for Wait-on-Reservation-Set instructions, Version 1.01 > Wait-on-Reservation-Set Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 71, + 74 + ] + }, + { + "chunk_id": "chunk_ffe620a3", + "text": "When executing in VS or VU mode, if the `VTW` bit is set in `hstatus`, the `TW` bit in `mstatus` is clear, and the `WRS.NTO` does not complete within an implementation-specific bounded time limit, the `WRS.NTO` instruction will cause a virtual-instruction exception.", + "source_file": "src/unpriv/zawrs.adoc", + "section": "Preamble > \"Zawrs\" Extension for Wait-on-Reservation-Set instructions, Version 1.01 > Wait-on-Reservation-Set Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 76, + 79 + ] + } + ] + }, + { + "file": "src/unpriv/zc.adoc", + "chunks": [ + { + "chunk_id": "chunk_4848b96d", + "text": "This chapter describes the RISC-V compressed instruction-set extensions, which reduce static and dynamic code size by adding short 16-bit instruction encodings for common operations.", + "source_file": "src/unpriv/zc.adoc", + "section": "Preamble > Compressed Instructions", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 3, + 7 + ] + }, + { + "chunk_id": "chunk_58ea6b72", + "text": "The extlink:c[] extension combines ext:zca[], ext:zcf[] if XLEN=32 and the F extension is present, and ext:zcd[] if the D extension is present.", + "source_file": "src/unpriv/zc.adoc", + "section": "Preamble > Compressed Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 9, + 18 + ] + } + ] + }, + { + "file": "src/unpriv/zca.adoc", + "chunks": [ + { + "chunk_id": "chunk_b175a898", + "text": "The compressed extensions use a simple compression scheme that offers shorter 16-bit versions of common 32-bit RISC-V instructions when:", + "source_file": "src/unpriv/zca.adoc", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 3, + 4 + ] + }, + { + "chunk_id": "chunk_01312075", + "text": "With the addition of the ext:zca[] extension, no instructions can raise instruction-address-misaligned exceptions.", + "source_file": "src/unpriv/zca.adoc", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 12, + 17 + ] + }, + { + "chunk_id": "chunk_ca9336cf", + "text": "If the C extension is implemented, the appropriate compressed floating-point load and store instructions must be provided whenever the relevant standard floating-point extension (F and/or D) is also implemented.", + "source_file": "src/unpriv/zca.adoc", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 19, + 32 + ] + }, + { + "chunk_id": "chunk_bf632ac0", + "text": "ext:zca[] was designed under the constraint that each ext:zca[] instruction expands into a single 32-bit instruction in the base ISA.", + "source_file": "src/unpriv/zca.adoc", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 34, + 36 + ] + }, + { + "chunk_id": "chunk_a2a75af3", + "text": "When the full 5-bit destination register specifier is present, it is in the same place as in the 32-bit RISC-V encoding.", + "source_file": "src/unpriv/zca.adoc", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 64, + 77 + ] + }, + { + "chunk_id": "chunk_38253dfb", + "text": "Where immediates are sign-extended, the sign extension is always from bit 12.", + "source_file": "src/unpriv/zca.adoc", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 64, + 77 + ] + }, + { + "chunk_id": "chunk_7a256ba7", + "text": "Immediate fields have been scrambled, as in the base specification, to reduce the number of immediate multiplexers required.", + "source_file": "src/unpriv/zca.adoc", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 64, + 77 + ] + }, + { + "chunk_id": "chunk_7643332e", + "text": "For many ext:zca[] instructions, zero-valued immediates are disallowed and `x0` is not a valid 5-bit register specifier.", + "source_file": "src/unpriv/zca.adoc", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 64, + 77 + ] + }, + { + "chunk_id": "chunk_9c7a2d59", + "text": "To increase the reach of 16-bit instructions, data-transfer instructions use zero-extended immediates that are scaled by the size of the data in bytes: \u00d74 for words, \u00d78 for doublewords, and \u00d716 for quadwords.", + "source_file": "src/unpriv/zca.adoc", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Load and Store Instructions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 138, + 140 + ] + }, + { + "chunk_id": "chunk_1083dca1", + "text": "C.LWSP loads a 32-bit value from memory into register rd.", + "source_file": "src/unpriv/zca.adoc", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Load and Store Instructions > Stack-Pointer-Based Loads and Stores", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 155, + 159 + ] + }, + { + "chunk_id": "chunk_a57e7c35", + "text": "It computes an effective address by adding the zero-extended offset, scaled by 4, to the stack pointer, `x2`.", + "source_file": "src/unpriv/zca.adoc", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Load and Store Instructions > Stack-Pointer-Based Loads and Stores", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 155, + 159 + ] + }, + { + "chunk_id": "chunk_82114342", + "text": "C.LDSP is an XLEN=64-only instruction that loads a 64-bit value from memory into register rd.", + "source_file": "src/unpriv/zca.adoc", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Load and Store Instructions > Stack-Pointer-Based Loads and Stores", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 161, + 167 + ] + }, + { + "chunk_id": "chunk_ccef4248", + "text": "It computes its effective address by adding the zero-extended offset, scaled by 8, to the stack pointer, `x2`.", + "source_file": "src/unpriv/zca.adoc", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Load and Store Instructions > Stack-Pointer-Based Loads and Stores", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 161, + 167 + ] + }, + { + "chunk_id": "chunk_cacc9a62", + "text": "C.SWSP stores a 32-bit value in register rs2 to memory.", + "source_file": "src/unpriv/zca.adoc", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Load and Store Instructions > Stack-Pointer-Based Loads and Stores", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 175, + 177 + ] + }, + { + "chunk_id": "chunk_098481d1", + "text": "It computes an effective address by adding the zero-extended offset, scaled by 4, to the stack pointer, `x2`.", + "source_file": "src/unpriv/zca.adoc", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Load and Store Instructions > Stack-Pointer-Based Loads and Stores", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 175, + 177 + ] + }, + { + "chunk_id": "chunk_2819f935", + "text": "C.SDSP is an XLEN=64-only instruction that stores a 64-bit value in register rs2 to memory.", + "source_file": "src/unpriv/zca.adoc", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Load and Store Instructions > Stack-Pointer-Based Loads and Stores", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 179, + 182 + ] + }, + { + "chunk_id": "chunk_f3922a4e", + "text": "It computes an effective address by adding the zero-extended offset, scaled by 8, to the stack pointer, `x2`.", + "source_file": "src/unpriv/zca.adoc", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Load and Store Instructions > Stack-Pointer-Based Loads and Stores", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 179, + 182 + ] + }, + { + "chunk_id": "chunk_f38fe9f7", + "text": "These instructions use the CL format.", + "source_file": "src/unpriv/zca.adoc", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Load and Store Instructions > Register-Based Loads and Stores", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 186, + 190 + ] + }, + { + "chunk_id": "chunk_a6381f09", + "text": "C.LW loads a 32-bit value from memory into register `rd\u2032`.", + "source_file": "src/unpriv/zca.adoc", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Load and Store Instructions > Register-Based Loads and Stores", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 192, + 195 + ] + }, + { + "chunk_id": "chunk_9ce59e41", + "text": "It computes an effective address by adding the zero-extended offset, scaled by 4, to the base address in register `rs1\u2032`.", + "source_file": "src/unpriv/zca.adoc", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Load and Store Instructions > Register-Based Loads and Stores", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 192, + 195 + ] + }, + { + "chunk_id": "chunk_64b9baaf", + "text": "C.LD is an XLEN=64-only instruction that loads a 64-bit value from memory into register `rd\u2032`.", + "source_file": "src/unpriv/zca.adoc", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Load and Store Instructions > Register-Based Loads and Stores", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 197, + 201 + ] + }, + { + "chunk_id": "chunk_ac6e9320", + "text": "It computes an effective address by adding the zero-extended offset, scaled by 8, to the base address in register `rs1\u2032`.", + "source_file": "src/unpriv/zca.adoc", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Load and Store Instructions > Register-Based Loads and Stores", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 197, + 201 + ] + }, + { + "chunk_id": "chunk_787b99b9", + "text": "These instructions use the CS format.", + "source_file": "src/unpriv/zca.adoc", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Load and Store Instructions > Register-Based Loads and Stores", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 208, + 208 + ] + }, + { + "chunk_id": "chunk_3ad5982e", + "text": "C.SW stores a 32-bit value in register `rs2\u2032` to memory.", + "source_file": "src/unpriv/zca.adoc", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Load and Store Instructions > Register-Based Loads and Stores", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 210, + 213 + ] + }, + { + "chunk_id": "chunk_69f9e371", + "text": "It computes an effective address by adding the zero-extended offset, scaled by 4, to the base address in register `rs1\u2032`.", + "source_file": "src/unpriv/zca.adoc", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Load and Store Instructions > Register-Based Loads and Stores", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 210, + 213 + ] + }, + { + "chunk_id": "chunk_28ae0e02", + "text": "C.SD is an XLEN=64-only instruction that stores a 64-bit value in register `rs2\u2032` to memory.", + "source_file": "src/unpriv/zca.adoc", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Load and Store Instructions > Register-Based Loads and Stores", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 215, + 219 + ] + }, + { + "chunk_id": "chunk_98780eb9", + "text": "It computes an effective address by adding the zero-extended offset, scaled by 8, to the base address in register `rs1\u2032`.", + "source_file": "src/unpriv/zca.adoc", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Load and Store Instructions > Register-Based Loads and Stores", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 215, + 219 + ] + }, + { + "chunk_id": "chunk_0224cf39", + "text": "As with base RVI instructions, the offsets of all ext:zca[] control transfer instructions are in multiples of 2 bytes.", + "source_file": "src/unpriv/zca.adoc", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Control Transfer Instructions", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 223, + 225 + ] + }, + { + "chunk_id": "chunk_cb6ee97d", + "text": "The offset is sign-extended and added to the `pc` to form the branch target address.", + "source_file": "src/unpriv/zca.adoc", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Control Transfer Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 273, + 277 + ] + }, + { + "chunk_id": "chunk_976fc7ba", + "text": "It can therefore target a {pm}256 B range. C.BEQZ takes the branch if the value in register rs1\u2032 is zero.", + "source_file": "src/unpriv/zca.adoc", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Control Transfer Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 273, + 277 + ] + }, + { + "chunk_id": "chunk_9aad6ca1", + "text": "C.BNEZ is defined analogously, but it takes the branch if rs1\u2032 contains a nonzero value.", + "source_file": "src/unpriv/zca.adoc", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Control Transfer Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 279, + 281 + ] + }, + { + "chunk_id": "chunk_ba5a195b", + "text": "C.LI loads the sign-extended 6-bit immediate, imm, into register rd. C.LI expands into `addi rd, x0, imm`.", + "source_file": "src/unpriv/zca.adoc", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Constant-Generation Instructions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 298, + 300 + ] + }, + { + "chunk_id": "chunk_10509d59", + "text": "C.LUI loads the non-zero 6-bit immediate field into bits 17\u201312 of the destination register, clears the bottom 12 bits, and sign-extends bit 17 into all higher bits of the destination. C.LUI expands into `lui rd, imm`. C.LUI is valid only when rd!=`x2`, and when the immediate is not equal to zero.", + "source_file": "src/unpriv/zca.adoc", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Constant-Generation Instructions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 302, + 312 + ] + }, + { + "chunk_id": "chunk_c81364d0", + "text": "These integer register-immediate operations are encoded in the CI format and perform operations on an integer register and a 6-bit immediate.", + "source_file": "src/unpriv/zca.adoc", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Immediate Operations", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 317, + 318 + ] + }, + { + "chunk_id": "chunk_c12004bc", + "text": "C.ADDI adds the non-zero sign-extended 6-bit immediate to the value in register rd then writes the result to rd. C.ADDI expands into `addi rd, rd, imm`.", + "source_file": "src/unpriv/zca.adoc", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Immediate Operations", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 325, + 330 + ] + }, + { + "chunk_id": "chunk_e69f637e", + "text": "The code points with rd!=0 and imm=0 are HINTs.", + "source_file": "src/unpriv/zca.adoc", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Immediate Operations", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 325, + 330 + ] + }, + { + "chunk_id": "chunk_d62bca7f", + "text": "The code points with rd=`x0` encode the C.NOP instruction, of which the code points with imm!=0 are HINTs.", + "source_file": "src/unpriv/zca.adoc", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Immediate Operations", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 325, + 330 + ] + }, + { + "chunk_id": "chunk_f7d8810b", + "text": "C.ADDIW is an XLEN=64-only instruction that performs the same computation but produces a 32-bit result, then sign-extends result to 64 bits. C.ADDIW expands into `addiw rd, rd, imm`.", + "source_file": "src/unpriv/zca.adoc", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Immediate Operations", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 332, + 338 + ] + }, + { + "chunk_id": "chunk_689af43a", + "text": "The immediate can be zero for C.ADDIW, where this corresponds to `sext.w rd`. C.ADDIW is valid only when rd!=`x0`; the code points with rd=`x0` are reserved.", + "source_file": "src/unpriv/zca.adoc", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Immediate Operations", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 332, + 338 + ] + }, + { + "chunk_id": "chunk_25315327", + "text": "C.ADDI16SP (add immediate to stack pointer) shares the opcode with C.LUI, but has a destination field of `x2`. C.ADDI16SP adds the non-zero sign-extended 6-bit immediate to the value in the stack pointer (`sp=x2`), where the immediate is scaled to represent multiples of 16 in the range [-512, 496]. C.ADDI16SP is used to adjust the stack pointer in procedure prologues and epilogues.", + "source_file": "src/unpriv/zca.adoc", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Immediate Operations", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 340, + 348 + ] + }, + { + "chunk_id": "chunk_4afe7147", + "text": "It expands into `addi x2, x2, nzimm[9:4]`. C.ADDI16SP is valid only when nzimm!=0; the code point with nzimm=0 is reserved.", + "source_file": "src/unpriv/zca.adoc", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Immediate Operations", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 340, + 348 + ] + }, + { + "chunk_id": "chunk_c7e35661", + "text": "C.SLLI is a CI-format instruction that performs a logical left shift of the value in register rd then writes the result to rd.", + "source_file": "src/unpriv/zca.adoc", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Immediate Operations", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 369, + 372 + ] + }, + { + "chunk_id": "chunk_03bc4049", + "text": "The shift amount is encoded in the shamt field. C.SLLI expands into `slli rd, rd, shamt[5:0]`.", + "source_file": "src/unpriv/zca.adoc", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Immediate Operations", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 369, + 372 + ] + }, + { + "chunk_id": "chunk_80b6a509", + "text": "The C.SLLI code points with shamt=0 or with rd=`x0` are HINTs.", + "source_file": "src/unpriv/zca.adoc", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Immediate Operations", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 374, + 374 + ] + }, + { + "chunk_id": "chunk_9d4d17cb", + "text": "For XLEN=32, shamt[5] must be zero; the code points with shamt[5]=1 are designated for custom extensions.", + "source_file": "src/unpriv/zca.adoc", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Immediate Operations", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 376, + 377 + ] + }, + { + "chunk_id": "chunk_477b7141", + "text": "C.SRLI is a CB-format instruction that performs a logical right shift of the value in register rd\u2032 then writes the result to rd\u2032.", + "source_file": "src/unpriv/zca.adoc", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Immediate Operations", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 385, + 388 + ] + }, + { + "chunk_id": "chunk_fca60568", + "text": "The shift amount is encoded in the shamt field. C.SRLI expands into `srli rd\u2032, rd\u2032, shamt`.", + "source_file": "src/unpriv/zca.adoc", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Immediate Operations", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 385, + 388 + ] + }, + { + "chunk_id": "chunk_00a520b6", + "text": "The C.SRLI code points with shamt=0 are HINTs.", + "source_file": "src/unpriv/zca.adoc", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Immediate Operations", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 390, + 390 + ] + }, + { + "chunk_id": "chunk_f987c107", + "text": "For XLEN=32, shamt[5] must be zero; the code points with shamt[5]=1 are designated for custom extensions.", + "source_file": "src/unpriv/zca.adoc", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Immediate Operations", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 392, + 393 + ] + }, + { + "chunk_id": "chunk_2a841775", + "text": "C.MV copies the value in register rs2 into register rd. C.MV expands into `add rd, x0, rs2`. C.MV is valid only when rs2!=`x0`; the code points with rs2=`x0` correspond to the C.JR instruction.", + "source_file": "src/unpriv/zca.adoc", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Register Operations", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 418, + 422 + ] + }, + { + "chunk_id": "chunk_dc485e6e", + "text": "The code points with rs2!=`x0` and rd=`x0` are HINTs.", + "source_file": "src/unpriv/zca.adoc", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Register Operations", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 418, + 422 + ] + }, + { + "chunk_id": "chunk_7e484ec7", + "text": "C.ADD adds the values in registers rd and rs2 and writes the result to register rd. C.ADD expands into `add rd, rd, rs2`. C.ADD is only valid when rs2!=`x0`; the code points with rs2=`x0` correspond to the C.JALR and C.EBREAK instructions.", + "source_file": "src/unpriv/zca.adoc", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Register Operations", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 424, + 429 + ] + }, + { + "chunk_id": "chunk_ce062bb0", + "text": "The code points with rs2!=`x0` and rd=`x0` are HINTs.", + "source_file": "src/unpriv/zca.adoc", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Register Operations", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 424, + 429 + ] + }, + { + "chunk_id": "chunk_3ea09b36", + "text": "These instructions use the CA format.", + "source_file": "src/unpriv/zca.adoc", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Register Operations", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 436, + 436 + ] + }, + { + "chunk_id": "chunk_f68161c9", + "text": "`C.AND` computes the bitwise `AND` of the values in registers rd\u2032 and rs2\u2032, then writes the result to register rd\u2032. `C.AND` expands into `and rd\u2032, rd\u2032, rs2\u2032`.", + "source_file": "src/unpriv/zca.adoc", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Register Operations", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 438, + 441 + ] + }, + { + "chunk_id": "chunk_01747956", + "text": "`C.OR` computes the bitwise `OR` of the values in registers rd\u2032 and rs2\u2032, then writes the result to register rd\u2032. `C.OR` expands into `or rd\u2032, rd\u2032, rs2\u2032`.", + "source_file": "src/unpriv/zca.adoc", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Register Operations", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 443, + 446 + ] + }, + { + "chunk_id": "chunk_aa2086f2", + "text": "`C.XOR` computes the bitwise `XOR` of the values in registers rd\u2032 and rs2\u2032, then writes the result to register rd\u2032. `C.XOR` expands into `xor rd\u2032, rd\u2032, rs2\u2032`.", + "source_file": "src/unpriv/zca.adoc", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Register Operations", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 448, + 451 + ] + }, + { + "chunk_id": "chunk_87cafca2", + "text": "`C.SUB` subtracts the value in register rs2\u2032 from the value in register rd\u2032, then writes the result to register rd\u2032. `C.SUB` expands into `sub rd\u2032, rd\u2032, rs2\u2032`.", + "source_file": "src/unpriv/zca.adoc", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Register Operations", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 453, + 456 + ] + }, + { + "chunk_id": "chunk_a3324971", + "text": "`C.ADDW` is an XLEN=64-only instruction that adds the values in registers rd\u2032 and rs2\u2032, then sign-extends the lower 32 bits of the sum before writing the result to register rd\u2032. `C.ADDW` expands into `addw rd\u2032, rd\u2032, rs2\u2032`.", + "source_file": "src/unpriv/zca.adoc", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Register Operations", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 458, + 462 + ] + }, + { + "chunk_id": "chunk_ef4e9811", + "text": "`C.SUBW` is an XLEN=64-only instruction that subtracts the value in register rs2\u2032 from the value in register rd\u2032, then sign-extends the lower 32 bits of the difference before writing the result to register rd\u2032. `C.SUBW` expands into `subw rd\u2032, rd\u2032, rs2\u2032`.", + "source_file": "src/unpriv/zca.adoc", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Register Operations", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 464, + 468 + ] + }, + { + "chunk_id": "chunk_993070b0", + "text": "A 16-bit instruction with all bits zero is permanently reserved as an illegal instruction.", + "source_file": "src/unpriv/zca.adoc", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Defined Illegal Instruction", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 476, + 477 + ] + }, + { + "chunk_id": "chunk_7e44809f", + "text": "The last quadrant, which has the two least-significant bits set, corresponds to instructions wider than 16 bits, including those in the base ISAs.", + "source_file": "src/unpriv/zca.adoc", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > ext:zca[] Instruction Set Listings", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 561, + 570 + ] + }, + { + "chunk_id": "chunk_ec2339ed", + "text": "Several instructions are only valid for certain operands; when invalid, they are marked either RES to indicate that the opcode is reserved for future standard extensions;", + "source_file": "src/unpriv/zca.adoc", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > ext:zca[] Instruction Set Listings", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 561, + 570 + ] + } + ] + }, + { + "file": "src/unpriv/zcb.adoc", + "chunks": [ + { + "chunk_id": "chunk_5263eecb", + "text": "The ext:zcb[] extension adds several compressed instructions which, like those in the extlink:zca[] extension, expand into a single 32-bit instruction.", + "source_file": "src/unpriv/zcb.adoc", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 3, + 5 + ] + }, + { + "chunk_id": "chunk_adeec0bd", + "text": "The resulting byte is zero extended to XLEN bits and is written to rd'.", + "source_file": "src/unpriv/zcb.adoc", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "range", + "line_range": [ + 118, + 118 + ] + }, + { + "chunk_id": "chunk_cfb059c1", + "text": "The resulting halfword is zero extended to XLEN bits and is written to rd'.", + "source_file": "src/unpriv/zcb.adoc", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.lhu", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "range", + "line_range": [ + 173, + 173 + ] + }, + { + "chunk_id": "chunk_f137fe17", + "text": "The resulting halfword is sign extended to XLEN bits and is written to rd'.", + "source_file": "src/unpriv/zcb.adoc", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.lh", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "range", + "line_range": [ + 229, + 229 + ] + }, + { + "chunk_id": "chunk_0289468d", + "text": "This instruction stores the least significant byte of rs2' to the memory address formed by adding rs1' to the zero extended immediate uimm.", + "source_file": "src/unpriv/zcb.adoc", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.sb", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 284, + 284 + ] + }, + { + "chunk_id": "chunk_0f5d4f3d", + "text": "This instruction stores the least significant halfword of rs2' to the memory address formed by adding rs1' to the zero extended immediate uimm.", + "source_file": "src/unpriv/zcb.adoc", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.sh", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 341, + 341 + ] + }, + { + "chunk_id": "chunk_d91c998f", + "text": "It zero-extends the least-significant byte of the operand to XLEN bits by inserting zeros into all of the bits more significant than 7.", + "source_file": "src/unpriv/zcb.adoc", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.zext.b", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "range", + "line_range": [ + 387, + 389 + ] + }, + { + "chunk_id": "chunk_e19a2bf7", + "text": "Zbb is also required. // //32-bit equivalent: // // from Zbb", + "source_file": "src/unpriv/zcb.adoc", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.sext.b", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 443, + 447 + ] + }, + { + "chunk_id": "chunk_0c8b7ec9", + "text": "It zero-extends the least-significant halfword of the operand to XLEN bits by inserting zeros into all of the bits more significant than 15.", + "source_file": "src/unpriv/zcb.adoc", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.zext.h", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "range", + "line_range": [ + 488, + 490 + ] + }, + { + "chunk_id": "chunk_503b5bcd", + "text": "Zbb is also required. // //32-bit equivalent: // // from Zbb", + "source_file": "src/unpriv/zcb.adoc", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.zext.h", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 494, + 498 + ] + }, + { + "chunk_id": "chunk_620596b7", + "text": "Zbb is also required. // //32-bit equivalent: // // from Zbb", + "source_file": "src/unpriv/zcb.adoc", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.sext.h", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 541, + 545 + ] + }, + { + "chunk_id": "chunk_76d7d6d5", + "text": "It zero-extends the least-significant word of the operand to XLEN bits by inserting zeros into all of the bits more significant than 31.", + "source_file": "src/unpriv/zcb.adoc", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.zext.w", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "range", + "line_range": [ + 582, + 584 + ] + }, + { + "chunk_id": "chunk_10648681", + "text": "M or Zmmul must be configured. // //32-bit equivalent: // //", + "source_file": "src/unpriv/zcb.adoc", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.mul", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 684, + 688 + ] + } + ] + }, + { + "file": "src/unpriv/zcd.adoc", + "chunks": [ + { + "chunk_id": "chunk_3bc84a13", + "text": "It computes its effective address by adding the zero-extended offset, scaled by 8, to the stack pointer, `x2`.", + "source_file": "src/unpriv/zcd.adoc", + "section": "Preamble > ext:zcd[] Double-Precision Floating-Point Compressed Instructions Extension > Stack-Pointer-Based Loads and Stores", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 8, + 12 + ] + }, + { + "chunk_id": "chunk_17b32b64", + "text": "It computes an effective address by adding the zero-extended offset, scaled by 8, to the stack pointer, `x2`.", + "source_file": "src/unpriv/zcd.adoc", + "section": "Preamble > ext:zcd[] Double-Precision Floating-Point Compressed Instructions Extension > Stack-Pointer-Based Loads and Stores", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 14, + 18 + ] + }, + { + "chunk_id": "chunk_4785730c", + "text": "These instructions encode their data source or destination as described in .", + "source_file": "src/unpriv/zcd.adoc", + "section": "Preamble > ext:zcd[] Double-Precision Floating-Point Compressed Instructions Extension > Stack-Pointer-Based Loads and Stores > Register-Based Loads and Stores", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 22, + 23 + ] + }, + { + "chunk_id": "chunk_32d3a092", + "text": "C.FLD is an RV32DC/RV64DC-only instruction that loads a double-precision floating-point value from memory into floating-point register `rd\u2032`.", + "source_file": "src/unpriv/zcd.adoc", + "section": "Preamble > ext:zcd[] Double-Precision Floating-Point Compressed Instructions Extension > Stack-Pointer-Based Loads and Stores > Register-Based Loads and Stores", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 25, + 30 + ] + }, + { + "chunk_id": "chunk_d45f296c", + "text": "It computes an effective address by adding the zero-extended offset, scaled by 8, to the base address in register `rs1\u2032`.", + "source_file": "src/unpriv/zcd.adoc", + "section": "Preamble > ext:zcd[] Double-Precision Floating-Point Compressed Instructions Extension > Stack-Pointer-Based Loads and Stores > Register-Based Loads and Stores", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 25, + 30 + ] + }, + { + "chunk_id": "chunk_882384cf", + "text": "C.FSD is an RV32DC/RV64DC-only instruction that stores a double-precision floating-point value in floating-point register `rs2\u2032` to memory.", + "source_file": "src/unpriv/zcd.adoc", + "section": "Preamble > ext:zcd[] Double-Precision Floating-Point Compressed Instructions Extension > Stack-Pointer-Based Loads and Stores > Register-Based Loads and Stores", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 32, + 37 + ] + }, + { + "chunk_id": "chunk_b48956e2", + "text": "It computes an effective address by adding the zero-extended offset, scaled by 8, to the base address in register `rs1\u2032`.", + "source_file": "src/unpriv/zcd.adoc", + "section": "Preamble > ext:zcd[] Double-Precision Floating-Point Compressed Instructions Extension > Stack-Pointer-Based Loads and Stores > Register-Based Loads and Stores", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 32, + 37 + ] + } + ] + }, + { + "file": "src/unpriv/zce.adoc", + "chunks": [ + { + "chunk_id": "chunk_bd54237f", + "text": "If XLEN=32 and the F extension is present, the ext:zce[] extension additionally depends upon the extlink:zcf[] extension.", + "source_file": "src/unpriv/zce.adoc", + "section": "Preamble > ext:zce[] Extension for Enhanced Instruction Compression", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 11, + 12 + ] + } + ] + }, + { + "file": "src/unpriv/zcf.adoc", + "chunks": [ + { + "chunk_id": "chunk_4b2bbfed", + "text": "It computes its effective address by adding the zero-extended offset, scaled by 4, to the stack pointer, `x2`.", + "source_file": "src/unpriv/zcf.adoc", + "section": "Preamble > ext:zcf[] Single-Precision Floating-Point Compressed Instructions Extension > Stack-Pointer-Based Loads and Stores", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 9, + 14 + ] + }, + { + "chunk_id": "chunk_f54a3799", + "text": "It computes an effective address by adding the zero-extended offset, scaled by 4, to the stack pointer, `x2`.", + "source_file": "src/unpriv/zcf.adoc", + "section": "Preamble > ext:zcf[] Single-Precision Floating-Point Compressed Instructions Extension > Stack-Pointer-Based Loads and Stores", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 16, + 20 + ] + }, + { + "chunk_id": "chunk_cccfef8f", + "text": "These instructions encode their data source or destination as described in the following table.", + "source_file": "src/unpriv/zcf.adoc", + "section": "Preamble > ext:zcf[] Single-Precision Floating-Point Compressed Instructions Extension > Stack-Pointer-Based Loads and Stores > Register-Based Loads and Stores", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 24, + 25 + ] + }, + { + "chunk_id": "chunk_8e028dcf", + "text": "! !`000` !`001` !`010` !`011` !`100` !`101` !`110` !`111` !`f8` !`f9` !`f10` !`f11` !`f12` !`f13`!`f14` !`f15` !`fs0` !`fs1` !`fa0` !`fa1` !`fa2`!`fa3` !`fa4` !`fa5` ! |", + "source_file": "src/unpriv/zcf.adoc", + "section": "Preamble > ext:zcf[] Single-Precision Floating-Point Compressed Instructions Extension > Stack-Pointer-Based Loads and Stores > Register-Based Loads and Stores", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 41, + 47 + ] + }, + { + "chunk_id": "chunk_8e5f6bb3", + "text": "C.FLW is an RV32FC-only instruction that loads a single-precision floating-point value from memory into floating-point register `rd\u2032`.", + "source_file": "src/unpriv/zcf.adoc", + "section": "Preamble > ext:zcf[] Single-Precision Floating-Point Compressed Instructions Extension > Stack-Pointer-Based Loads and Stores > Register-Based Loads and Stores", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 49, + 54 + ] + }, + { + "chunk_id": "chunk_c846447d", + "text": "It computes an effective address by adding the zero-extended offset, scaled by 4, to the base address in register `rs1\u2032`.", + "source_file": "src/unpriv/zcf.adoc", + "section": "Preamble > ext:zcf[] Single-Precision Floating-Point Compressed Instructions Extension > Stack-Pointer-Based Loads and Stores > Register-Based Loads and Stores", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 49, + 54 + ] + }, + { + "chunk_id": "chunk_8931f154", + "text": "C.FSW is an RV32FC-only instruction that stores a single-precision floating-point value in floating-point register `rs2\u2032` to memory.", + "source_file": "src/unpriv/zcf.adoc", + "section": "Preamble > ext:zcf[] Single-Precision Floating-Point Compressed Instructions Extension > Stack-Pointer-Based Loads and Stores > Register-Based Loads and Stores", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 56, + 61 + ] + }, + { + "chunk_id": "chunk_9e99f103", + "text": "It computes an effective address by adding the zero-extended offset, scaled by 4, to the base address in register `rs1\u2032`.", + "source_file": "src/unpriv/zcf.adoc", + "section": "Preamble > ext:zcf[] Single-Precision Floating-Point Compressed Instructions Extension > Stack-Pointer-Based Loads and Stores > Register-Based Loads and Stores", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 56, + 61 + ] + } + ] + }, + { + "file": "src/unpriv/zclsd.adoc", + "chunks": [ + { + "chunk_id": "chunk_5be97811", + "text": "For the purposes of RVWMO and exception handling, C.LD[SP] and C.SD[SP] instructions are considered to be misaligned loads and stores, with one additional constraint: a C.LD[SP] or C.SD[SP] instruction whose effective address is a multiple of 4 gives rise to two 4-byte memory operations.", + "source_file": "src/unpriv/zclsd.adoc", + "section": "Preamble > ext:zclsd[] Extension for Compressed Load/Store Pair Instructions > Use of `x0` as operand > Exception Handling", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 18, + 21 + ] + }, + { + "chunk_id": "chunk_3d8c64db", + "text": "[insns-cldsp,reftext=\"Stack-pointer based load doubleword to register pair, 16-bit encoding\"]", + "source_file": "src/unpriv/zclsd.adoc", + "section": "Preamble > ext:zclsd[] Extension for Compressed Load/Store Pair Instructions > Use of `x0` as operand > Exception Handling", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 56, + 56 + ] + }, + { + "chunk_id": "chunk_89080859", + "text": "It computes its effective address by adding the zero-extended offset, scaled by 8, to the stack pointer, `x2`.", + "source_file": "src/unpriv/zclsd.adoc", + "section": "Preamble > ext:zclsd[] Extension for Compressed Load/Store Pair Instructions > Use of `x0` as operand > Exception Handling > c.ldsp", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 77, + 79 + ] + }, + { + "chunk_id": "chunk_7abbc5ea", + "text": "[insns-csdsp,reftext=\"Stack-pointer based store doubleword from register pair, 16-bit encoding\"]", + "source_file": "src/unpriv/zclsd.adoc", + "section": "Preamble > ext:zclsd[] Extension for Compressed Load/Store Pair Instructions > Use of `x0` as operand > Exception Handling > c.ldsp", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 85, + 85 + ] + }, + { + "chunk_id": "chunk_148711ae", + "text": "It computes an effective address by adding the zero-extended offset, scaled by 8, to the stack pointer, `x2`.", + "source_file": "src/unpriv/zclsd.adoc", + "section": "Preamble > ext:zclsd[] Extension for Compressed Load/Store Pair Instructions > Use of `x0` as operand > Exception Handling > c.sdsp", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 105, + 107 + ] + }, + { + "chunk_id": "chunk_fa65403f", + "text": "[insns-cld,reftext=\"Load doubleword to register pair, 16-bit encoding\"]", + "source_file": "src/unpriv/zclsd.adoc", + "section": "Preamble > ext:zclsd[] Extension for Compressed Load/Store Pair Instructions > Use of `x0` as operand > Exception Handling > c.sdsp", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 113, + 113 + ] + }, + { + "chunk_id": "chunk_35041d65", + "text": "It computes an effective address by adding the zero-extended offset, scaled by 8, to the base address in register rs1'.", + "source_file": "src/unpriv/zclsd.adoc", + "section": "Preamble > ext:zclsd[] Extension for Compressed Load/Store Pair Instructions > Use of `x0` as operand > Exception Handling > c.ld", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 135, + 138 + ] + }, + { + "chunk_id": "chunk_f822abb1", + "text": "[insns-csd,reftext=\"Store doubleword from register pair, 16-bit encoding\"]", + "source_file": "src/unpriv/zclsd.adoc", + "section": "Preamble > ext:zclsd[] Extension for Compressed Load/Store Pair Instructions > Use of `x0` as operand > Exception Handling > c.ld", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 144, + 144 + ] + }, + { + "chunk_id": "chunk_54a1dde2", + "text": "It computes an effective address by adding the zero-extended offset, scaled by 8, to the base address in register rs1'.", + "source_file": "src/unpriv/zclsd.adoc", + "section": "Preamble > ext:zclsd[] Extension for Compressed Load/Store Pair Instructions > Use of `x0` as operand > Exception Handling > c.sd", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 166, + 170 + ] + } + ] + }, + { + "file": "src/unpriv/zcmop.adoc", + "chunks": [ + { + "chunk_id": "chunk_9b06a903", + "text": "This section defines the ext:zcmop[] extension, which defines eight 16-bit MOP instructions named C.MOP.n, where n is an odd integer between 1 and 15, inclusive. C.MOP.n is encoded in the reserved encoding space corresponding to C.LUI xn, 0, as shown in .", + "source_file": "src/unpriv/zcmop.adoc", + "section": "Preamble > ext:zcmop[] Compressed May-Be-Operations Extension", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 3, + 10 + ] + } + ] + }, + { + "file": "src/unpriv/zcmp.adoc", + "chunks": [ + { + "chunk_id": "chunk_bda13cc3", + "text": "As well as reducing the code-size PUSH and POPRET eliminate the branches from calling the millicode save/restore routines and so may also perform better.", + "source_file": "src/unpriv/zcmp.adoc", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Example usage", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 109, + 112 + ] + }, + { + "chunk_id": "chunk_2e331ed9", + "text": "Additionally the spimm field in the encoding allows the stack pointer to be adjusted in additional increments of 16-bytes.", + "source_file": "src/unpriv/zcmp.adoc", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Example usage > Stack pointer adjustment handling", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 118, + 120 + ] + }, + { + "chunk_id": "chunk_883f34a4", + "text": "There is no support for the \\{ra, s0-s10} register list without also adding s11.", + "source_file": "src/unpriv/zcmp.adoc", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Example usage > Register list handling", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 124, + 124 + ] + }, + { + "chunk_id": "chunk_8eaa350b", + "text": "Therefore the \\{ra, s0-s11} register list must be used in this case.", + "source_file": "src/unpriv/zcmp.adoc", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Example usage > Register list handling", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 124, + 124 + ] + }, + { + "chunk_id": "chunk_b8cdaabd", + "text": "Correct execution requires that sp refers to idempotent memory (also see ), because the core must be able to handle traps detected during the sequence.", + "source_file": "src/unpriv/zcmp.adoc", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > PUSH/POP Fault handling", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 129, + 132 + ] + }, + { + "chunk_id": "chunk_8a42edb9", + "text": "The entire PUSH/POP sequence is re-executed after returning from the trap handler, and multiple traps are possible during the sequence.", + "source_file": "src/unpriv/zcmp.adoc", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > PUSH/POP Fault handling", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 129, + 132 + ] + }, + { + "chunk_id": "chunk_bf90f828", + "text": "If a trap occurs during the sequence then xEPC is updated with the PC of the instruction, xTVAL (if not read-only-zero) updated with the bad address if it was an access fault and xCAUSE updated with the type of trap.", + "source_file": "src/unpriv/zcmp.adoc", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > PUSH/POP Fault handling", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 134, + 134 + ] + }, + { + "chunk_id": "chunk_22a94933", + "text": "A sequence of stores writing the bytes required by the pseudocode ** The bytes may be written in any order. ** The bytes may be grouped into larger accesses. ** Any of the bytes may be written multiple times. * A stack pointer adjustment", + "source_file": "src/unpriv/zcmp.adoc", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Software view of execution > Software view of the PUSH sequence", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 146, + 150 + ] + }, + { + "chunk_id": "chunk_5b2dd590", + "text": "The stack pointer adjustment must only be committed only when it is certain that the entire PUSH instruction will commit.", + "source_file": "src/unpriv/zcmp.adoc", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Software view of execution > Software view of the PUSH sequence", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 152, + 152 + ] + }, + { + "chunk_id": "chunk_244a5921", + "text": "Stores may also return imprecise faults from the bus.", + "source_file": "src/unpriv/zcmp.adoc", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Software view of execution > Software view of the PUSH sequence", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 154, + 157 + ] + }, + { + "chunk_id": "chunk_dfe1aa70", + "text": "[source,asm] ---- any bytes from sp-1 to sp-28 may be written multiple times before the instruction completes therefore these updates may be visible in the interrupt/exception handler below the stack pointer sw s5, -4(sp) sw s4, -8(sp) sw s3,-12(sp) sw s2,-16(sp) sw s1,-20(sp) sw s0,-24(sp) sw ra,-28(sp)", + "source_file": "src/unpriv/zcmp.adoc", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Software view of execution > Software view of the PUSH sequence", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 170, + 181 + ] + }, + { + "chunk_id": "chunk_bcda8ac5", + "text": "this must only execute once, and will only execute after all stores completed without any precise faults, therefore this update is only visible in the interrupt/exception handler if cm.push has completed addi sp, sp, -64 ----", + "source_file": "src/unpriv/zcmp.adoc", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Software view of execution > Software view of the PUSH sequence", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 183, + 187 + ] + }, + { + "chunk_id": "chunk_7696c9eb", + "text": "A sequence of loads reading the bytes required by the pseudocode. ** The bytes may be loaded in any order. ** The bytes may be grouped into larger accesses. ** Any of the bytes may be loaded multiple times. * A stack pointer adjustment * An optional `li a0, 0` * An optional `ret`", + "source_file": "src/unpriv/zcmp.adoc", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Software view of execution > Software view of the POP/POPRET sequence", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 193, + 199 + ] + }, + { + "chunk_id": "chunk_13f1a7d5", + "text": "If a trap occurs during the sequence, then any loads which were executed before the trap may update architectural state.", + "source_file": "src/unpriv/zcmp.adoc", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Software view of execution > Software view of the POP/POPRET sequence", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 201, + 203 + ] + }, + { + "chunk_id": "chunk_0ae836bd", + "text": "The loads will be re-executed once the trap handler completes, so the values will be overwritten.", + "source_file": "src/unpriv/zcmp.adoc", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Software view of execution > Software view of the POP/POPRET sequence", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 201, + 203 + ] + }, + { + "chunk_id": "chunk_a89de1bd", + "text": "Therefore it is permitted for an implementation to update some of the destination registers before taking a fault.", + "source_file": "src/unpriv/zcmp.adoc", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Software view of execution > Software view of the POP/POPRET sequence", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 201, + 203 + ] + }, + { + "chunk_id": "chunk_c0b97b01", + "text": "The optional `li a0, 0`, stack pointer adjustment and optional `ret` must only be committed only when it is certain that the entire POP/POPRET instruction will commit.", + "source_file": "src/unpriv/zcmp.adoc", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Software view of execution > Software view of the POP/POPRET sequence", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 205, + 205 + ] + }, + { + "chunk_id": "chunk_4e1f005e", + "text": "For POPRET once the stack pointer adjustment has been committed the `ret` must execute.", + "source_file": "src/unpriv/zcmp.adoc", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Software view of execution > Software view of the POP/POPRET sequence", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 207, + 207 + ] + }, + { + "chunk_id": "chunk_a15a4c11", + "text": "[source,asm] ---- any or all of these load instructions may execute multiple times therefore these updates may be visible in the interrupt/exception handler lw s3, 28(sp) lw s2, 24(sp) lw s1, 20(sp) lw s0, 16(sp) lw ra, 12(sp)", + "source_file": "src/unpriv/zcmp.adoc", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Software view of execution > Software view of the POP/POPRET sequence", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 219, + 227 + ] + }, + { + "chunk_id": "chunk_0941a2fa", + "text": "these must only execute once, will only execute after all loads complete successfully all instructions must execute atomically therefore these updates are not visible in the interrupt/exception handler li a0, 0 addi sp, sp, 32 ret ----", + "source_file": "src/unpriv/zcmp.adoc", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Software view of execution > Software view of the POP/POPRET sequence", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 229, + 235 + ] + }, + { + "chunk_id": "chunk_f214c8f2", + "text": "An implementation may have a requirement to issue a PUSH/POP instruction to non-idempotent memory.", + "source_file": "src/unpriv/zcmp.adoc", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Non-idempotent memory handling", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 240, + 240 + ] + }, + { + "chunk_id": "chunk_7b1c311f", + "text": "If the core implementation does not support PUSH/POP to non-idempotent memories, the core may use an idempotency PMA to detect it and take a load (POP/POPRET) or store (PUSH) access-fault exception in order to avoid unpredictable results.", + "source_file": "src/unpriv/zcmp.adoc", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Non-idempotent memory handling", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 242, + 243 + ] + }, + { + "chunk_id": "chunk_4830fc54", + "text": "Software should only use these instructions on non-idempotent memory regions when software can tolerate the required memory accesses being issued repeatedly in the case that they cause exceptions.", + "source_file": "src/unpriv/zcmp.adoc", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Non-idempotent memory handling", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 245, + 246 + ] + }, + { + "chunk_id": "chunk_39381afb", + "text": "switch (rlist){ case 4: \\{reglist=\"ra\"; xreglist=\"x1\";} case 5: \\{reglist=\"ra, s0\"; xreglist=\"x1, x8\";} case 6: \\{reglist=\"ra, s0-s1\"; xreglist=\"x1, x8-x9\";} default: reserved(); } stackadj = stackadjbase + spimm * 16; ----", + "source_file": "src/unpriv/zcmp.adoc", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.push", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 381, + 388 + ] + }, + { + "chunk_id": "chunk_dfc47a5a", + "text": "[source,sail] ---- RV32I, RV64: switch (rlist){ case 4: \\{reglist=\"ra\"; xreglist=\"x1\";} case 5: \\{reglist=\"ra, s0\"; xreglist=\"x1, x8\";} case 6: \\{reglist=\"ra, s0-s1\"; xreglist=\"x1, x8-x9\";} case 7: \\{reglist=\"ra, s0-s2\"; xreglist=\"x1, x8-x9, x18\";} case 8: \\{reglist=\"ra, s0-s3\"; xreglist=\"x1, x8-x9, x18-x19\";} case 9: \\{reglist=\"ra, s0-s4\"; xreglist=\"x1, x8-x9, x18-x20\";} case 10: \\{reglist=\"ra, s0-s5\"; xreglist=\"x1, x8-x9, x18-x21\";} case 11: \\{reglist=\"ra, s0-s6\"; xreglist=\"x1, x8-x9, x18-x22\";} case 12: \\{reglist=\"ra, s0-s7\"; xreglist=\"x1, x8-x9, x18-x23\";} case 13: \\{reglist=\"ra, s0-s8\"; xreglist=\"x1, x8-x9, x18-x24\";} case 14: \\{reglist=\"ra, s0-s9\"; xreglist=\"x1, x8-x9, x18-x25\";} //note - to include s10, s11 must also be included case 15: \\{reglist=\"ra, s0-s11\"; xreglist=\"x1, x8-x9, x18-x27\";} default: reserved(); } stackadj = stackadjbase + spimm * 16; ----", + "source_file": "src/unpriv/zcmp.adoc", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.push", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 390, + 410 + ] + }, + { + "chunk_id": "chunk_938f399a", + "text": "This instruction pushes (stores) the registers in reglist to the memory below the stack pointer, and then creates the stack frame by decrementing the stack pointer by stackadj, including any additional stack space requested by the value of spimm.", + "source_file": "src/unpriv/zcmp.adoc", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.push", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 470, + 472 + ] + }, + { + "chunk_id": "chunk_59adbc22", + "text": "stackadjbase is the minimum number of bytes, in multiples of 16-byte address increments, required to cover the registers in the list.", + "source_file": "src/unpriv/zcmp.adoc", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.push", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 478, + 478 + ] + }, + { + "chunk_id": "chunk_f1ef55ea", + "text": "spimm is the number of additional 16-byte address increments allocated for the stack frame.", + "source_file": "src/unpriv/zcmp.adoc", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.push", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 480, + 480 + ] + }, + { + "chunk_id": "chunk_1239efe6", + "text": "The first section of pseudocode may be executed multiple times before the instruction successfully completes.", + "source_file": "src/unpriv/zcmp.adoc", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.push", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 495, + 495 + ] + }, + { + "chunk_id": "chunk_e8834e78", + "text": "addr=sp-bytes; for(i in 27,26,25,24,23,22,21,20,19,18,9,8,1) { //if register i is in xreglist if (xreglist[i]) { switch(bytes) { 4: asm(\"sw x[i], 0(addr)\"); 8: asm(\"sd x[i], 0(addr)\"); } addr-=bytes; } } ----", + "source_file": "src/unpriv/zcmp.adoc", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.push", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 503, + 514 + ] + }, + { + "chunk_id": "chunk_c3233798", + "text": "The final section of pseudocode executes atomically, and only executes if the section above completes without any exceptions or interrupts.", + "source_file": "src/unpriv/zcmp.adoc", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.push", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 516, + 516 + ] + }, + { + "chunk_id": "chunk_8068740c", + "text": "[source,sail] ---- RV32E: switch (rlist){ case 4: \\{reglist=\"ra\"; xreglist=\"x1\";} case 5: \\{reglist=\"ra, s0\"; xreglist=\"x1, x8\";} case 6: \\{reglist=\"ra, s0-s1\"; xreglist=\"x1, x8-x9\";} default: reserved(); } stackadj = stackadjbase + spimm * 16; ----", + "source_file": "src/unpriv/zcmp.adoc", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.pop", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 561, + 571 + ] + }, + { + "chunk_id": "chunk_3622230c", + "text": "[source,sail] ---- RV32I, RV64: switch (rlist){ case 4: \\{reglist=\"ra\"; xreglist=\"x1\";} case 5: \\{reglist=\"ra, s0\"; xreglist=\"x1, x8\";} case 6: \\{reglist=\"ra, s0-s1\"; xreglist=\"x1, x8-x9\";} case 7: \\{reglist=\"ra, s0-s2\"; xreglist=\"x1, x8-x9, x18\";} case 8: \\{reglist=\"ra, s0-s3\"; xreglist=\"x1, x8-x9, x18-x19\";} case 9: \\{reglist=\"ra, s0-s4\"; xreglist=\"x1, x8-x9, x18-x20\";} case 10: \\{reglist=\"ra, s0-s5\"; xreglist=\"x1, x8-x9, x18-x21\";} case 11: \\{reglist=\"ra, s0-s6\"; xreglist=\"x1, x8-x9, x18-x22\";} case 12: \\{reglist=\"ra, s0-s7\"; xreglist=\"x1, x8-x9, x18-x23\";} case 13: \\{reglist=\"ra, s0-s8\"; xreglist=\"x1, x8-x9, x18-x24\";} case 14: \\{reglist=\"ra, s0-s9\"; xreglist=\"x1, x8-x9, x18-x25\";} //note - to include s10, s11 must also be included case 15: \\{reglist=\"ra, s0-s11\"; xreglist=\"x1, x8-x9, x18-x27\";} default: reserved(); } stackadj = stackadjbase + spimm * 16; ----", + "source_file": "src/unpriv/zcmp.adoc", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.pop", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 573, + 593 + ] + }, + { + "chunk_id": "chunk_6757022f", + "text": "stackadjbase is the minimum number of bytes, in multiples of 16-byte address increments, required to cover the registers in the list.", + "source_file": "src/unpriv/zcmp.adoc", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.pop", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 661, + 661 + ] + }, + { + "chunk_id": "chunk_475ffe07", + "text": "spimm is the number of additional 16-byte address increments allocated for the stack frame.", + "source_file": "src/unpriv/zcmp.adoc", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.pop", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 663, + 663 + ] + }, + { + "chunk_id": "chunk_e6a70a49", + "text": "The first section of pseudocode may be executed multiple times before the instruction successfully completes.", + "source_file": "src/unpriv/zcmp.adoc", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.pop", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 678, + 678 + ] + }, + { + "chunk_id": "chunk_0badcf9b", + "text": "The final section of pseudocode executes atomically, and only executes if the section above completes without any exceptions or interrupts.", + "source_file": "src/unpriv/zcmp.adoc", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.pop", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 699, + 699 + ] + }, + { + "chunk_id": "chunk_dae7b925", + "text": "[source,sail] ---- RV32E: switch (rlist){ case 4: \\{reglist=\"ra\"; xreglist=\"x1\";} case 5: \\{reglist=\"ra, s0\"; xreglist=\"x1, x8\";} case 6: \\{reglist=\"ra, s0-s1\"; xreglist=\"x1, x8-x9\";} default: reserved(); } stackadj = stackadjbase + spimm * 16; ----", + "source_file": "src/unpriv/zcmp.adoc", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popretz", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 741, + 751 + ] + }, + { + "chunk_id": "chunk_2367d297", + "text": "switch (rlist){ case 4: \\{reglist=\"ra\"; xreglist=\"x1\";} case 5: \\{reglist=\"ra, s0\"; xreglist=\"x1, x8\";} case 6: \\{reglist=\"ra, s0-s1\"; xreglist=\"x1, x8-x9\";} case 7: \\{reglist=\"ra, s0-s2\"; xreglist=\"x1, x8-x9, x18\";} case 8: \\{reglist=\"ra, s0-s3\"; xreglist=\"x1, x8-x9, x18-x19\";} case 9: \\{reglist=\"ra, s0-s4\"; xreglist=\"x1, x8-x9, x18-x20\";} case 10: \\{reglist=\"ra, s0-s5\"; xreglist=\"x1, x8-x9, x18-x21\";} case 11: \\{reglist=\"ra, s0-s6\"; xreglist=\"x1, x8-x9, x18-x22\";} case 12: \\{reglist=\"ra, s0-s7\"; xreglist=\"x1, x8-x9, x18-x23\";} case 13: \\{reglist=\"ra, s0-s8\"; xreglist=\"x1, x8-x9, x18-x24\";} case 14: \\{reglist=\"ra, s0-s9\"; xreglist=\"x1, x8-x9, x18-x25\";} //note - to include s10, s11 must also be included case 15: \\{reglist=\"ra, s0-s11\"; xreglist=\"x1, x8-x9, x18-x27\";} default: reserved(); } stackadj = stackadjbase + spimm * 16; ----", + "source_file": "src/unpriv/zcmp.adoc", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popretz", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 757, + 774 + ] + }, + { + "chunk_id": "chunk_7d323770", + "text": "stackadjbase is the minimum number of bytes, in multiples of 16-byte address increments, required to cover the registers in the list.", + "source_file": "src/unpriv/zcmp.adoc", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popretz", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 841, + 841 + ] + }, + { + "chunk_id": "chunk_38118f2c", + "text": "spimm is the number of additional 16-byte address increments allocated for the stack frame.", + "source_file": "src/unpriv/zcmp.adoc", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popretz", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 843, + 843 + ] + }, + { + "chunk_id": "chunk_cc3decbc", + "text": "The first section of pseudocode may be executed multiple times before the instruction successfully completes.", + "source_file": "src/unpriv/zcmp.adoc", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popretz", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 857, + 857 + ] + }, + { + "chunk_id": "chunk_8f043a94", + "text": "The final section of pseudocode executes atomically, and only executes if the section above completes without any exceptions or interrupts.", + "source_file": "src/unpriv/zcmp.adoc", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popretz", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 878, + 878 + ] + }, + { + "chunk_id": "chunk_7b0a8f3d", + "text": "switch (rlist){ case 4: \\{reglist=\"ra\"; xreglist=\"x1\";} case 5: \\{reglist=\"ra, s0\"; xreglist=\"x1, x8\";} case 6: \\{reglist=\"ra, s0-s1\"; xreglist=\"x1, x8-x9\";} default: reserved(); } stackadj = stackadjbase + spimm * 16; ----", + "source_file": "src/unpriv/zcmp.adoc", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popret", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 929, + 936 + ] + }, + { + "chunk_id": "chunk_a23d07f7", + "text": "switch (rlist){ case 4: \\{reglist=\"ra\"; xreglist=\"x1\";} case 5: \\{reglist=\"ra, s0\"; xreglist=\"x1, x8\";} case 6: \\{reglist=\"ra, s0-s1\"; xreglist=\"x1, x8-x9\";} case 7: \\{reglist=\"ra, s0-s2\"; xreglist=\"x1, x8-x9, x18\";} case 8: \\{reglist=\"ra, s0-s3\"; xreglist=\"x1, x8-x9, x18-x19\";} case 9: \\{reglist=\"ra, s0-s4\"; xreglist=\"x1, x8-x9, x18-x20\";} case 10: \\{reglist=\"ra, s0-s5\"; xreglist=\"x1, x8-x9, x18-x21\";} case 11: \\{reglist=\"ra, s0-s6\"; xreglist=\"x1, x8-x9, x18-x22\";} case 12: \\{reglist=\"ra, s0-s7\"; xreglist=\"x1, x8-x9, x18-x23\";} case 13: \\{reglist=\"ra, s0-s8\"; xreglist=\"x1, x8-x9, x18-x24\";} case 14: \\{reglist=\"ra, s0-s9\"; xreglist=\"x1, x8-x9, x18-x25\";} //note - to include s10, s11 must also be included case 15: \\{reglist=\"ra, s0-s11\"; xreglist=\"x1, x8-x9, x18-x27\";} default: reserved(); } stackadj = stackadjbase + spimm * 16; ----", + "source_file": "src/unpriv/zcmp.adoc", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popret", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 942, + 959 + ] + }, + { + "chunk_id": "chunk_c00f1f05", + "text": "stackadjbase is the minimum number of bytes, in multiples of 16-byte address increments, required to cover the registers in the list.", + "source_file": "src/unpriv/zcmp.adoc", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popret", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 1026, + 1026 + ] + }, + { + "chunk_id": "chunk_94439e00", + "text": "spimm is the number of additional 16-byte address increments allocated for the stack frame.", + "source_file": "src/unpriv/zcmp.adoc", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popret", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 1028, + 1028 + ] + }, + { + "chunk_id": "chunk_68eb1534", + "text": "The first section of pseudocode may be executed multiple times before the instruction successfully completes.", + "source_file": "src/unpriv/zcmp.adoc", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popret", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1042, + 1042 + ] + }, + { + "chunk_id": "chunk_03028360", + "text": "The final section of pseudocode executes atomically, and only executes if the section above completes without any exceptions or interrupts.", + "source_file": "src/unpriv/zcmp.adoc", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popret", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1063, + 1063 + ] + }, + { + "chunk_id": "chunk_b46a388d", + "text": "The SAIL hasn't been written yet. if (RV32E && (r1sc>1 || r2sc>1)) { reserved(); } xreg1 = {r1sc[2:1]>0,r1sc[2:1]0,r1sc[2:0]}; xreg2 = {r2sc[2:1]>0,r2sc[2:1]0,r2sc[2:0]}; X[xreg1] = X[10]; X[xreg2] = X[11]; ----", + "source_file": "src/unpriv/zcmp.adoc", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.mvsa01", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1124, + 1134 + ] + }, + { + "chunk_id": "chunk_4649270e", + "text": "The SAIL hasn't been written yet. if (RV32E && (r1sc>1 || r2sc>1)) { reserved(); } xreg1 = {r1sc[2:1]>0,r1sc[2:1]0,r1sc[2:0]}; xreg2 = {r2sc[2:1]>0,r2sc[2:1]0,r2sc[2:0]}; X[10] = X[xreg1]; X[11] = X[xreg2]; ----", + "source_file": "src/unpriv/zcmp.adoc", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.mva01s", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1187, + 1197 + ] + } + ] + }, + { + "file": "src/unpriv/zcmt.adoc", + "chunks": [ + { + "chunk_id": "chunk_6735a2ba", + "text": "The ext:zcmt[] extension adds table-jump instructions, which improve code density when procedures have many call sites.", + "source_file": "src/unpriv/zcmt.adoc", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 3, + 7 + ] + }, + { + "chunk_id": "chunk_9aed215a", + "text": "It also adds the csr:jvt[] CSR.", + "source_file": "src/unpriv/zcmt.adoc", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 3, + 7 + ] + }, + { + "chunk_id": "chunk_106f0851", + "text": "The csr:jvt[] CSR requires a state enable if Smstateen is implemented.", + "source_file": "src/unpriv/zcmt.adoc", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 3, + 7 + ] + }, + { + "chunk_id": "chunk_499c4a72", + "text": "The ext:zcmt[] extension depends on the extlink:zca[] and extlink:zicsr[] extensions.", + "source_file": "src/unpriv/zcmt.adoc", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 14, + 14 + ] + }, + { + "chunk_id": "chunk_f1809f62", + "text": "The table must be a minimum of 64-byte aligned.", + "source_file": "src/unpriv/zcmt.adoc", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 40, + 41 + ] + }, + { + "chunk_id": "chunk_cfc49892", + "text": "If a return address stack is implemented, then as cm.jalt is equivalent to jal ra, it pushes to the stack.", + "source_file": "src/unpriv/zcmt.adoc", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 57, + 57 + ] + }, + { + "chunk_id": "chunk_096c9552", + "text": "If the same function is called with and without linking then it must have two entries in the table.", + "source_file": "src/unpriv/zcmt.adoc", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > jvt", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 63, + 64 + ] + }, + { + "chunk_id": "chunk_6bf5c16d", + "text": "Multiple contexts may have different jump vector tables. JVT may be switched between them without an instruction barrier if the tables have not been updated in memory since the last fence.i.", + "source_file": "src/unpriv/zcmt.adoc", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > Table Jump Fault handling", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 76, + 77 + ] + }, + { + "chunk_id": "chunk_2bcf64e2", + "text": "If an exception occurs on either instruction fetch, xEPC is set to the PC of the table jump instruction, xCAUSE is set as expected for the type of fault and xTVAL (if not set to zero) contains the fetch address which caused the fault.", + "source_file": "src/unpriv/zcmt.adoc", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > Table Jump Fault handling", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 79, + 79 + ] + }, + { + "chunk_id": "chunk_bb9adf0d", + "text": "<<< [csrs-jvt,reftext=\"jvt CSR, table jump base vector and control register\"]", + "source_file": "src/unpriv/zcmt.adoc", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > Table Jump Fault handling", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 81, + 82 + ] + }, + { + "chunk_id": "chunk_e28fd435", + "text": "Table jump base vector and control register", + "source_file": "src/unpriv/zcmt.adoc", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > jvt CSR", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 87, + 87 + ] + }, + { + "chunk_id": "chunk_fb019f48", + "text": "The jvt register is an XLEN-bit *WARL* read/write register that holds the jump table configuration, consisting of the jump table base address (BASE) and the jump table mode (MODE).", + "source_file": "src/unpriv/zcmt.adoc", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > jvt CSR", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 119, + 119 + ] + }, + { + "chunk_id": "chunk_cda16098", + "text": "If ext:zcmt[] is implemented then jvt must also be implemented, but can contain a read-only value.", + "source_file": "src/unpriv/zcmt.adoc", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > jvt CSR", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 121, + 122 + ] + }, + { + "chunk_id": "chunk_2f351e84", + "text": "If jvt is writable, the set of values the register may hold can vary by implementation.", + "source_file": "src/unpriv/zcmt.adoc", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > jvt CSR", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 121, + 122 + ] + }, + { + "chunk_id": "chunk_6b510430", + "text": "The value in the BASE field must always be aligned on a 64-byte boundary.", + "source_file": "src/unpriv/zcmt.adoc", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > jvt CSR", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 121, + 122 + ] + }, + { + "chunk_id": "chunk_9c947ab6", + "text": "When computing jump-table accesses, the lower six bits of base are filled with zeroes to obtain an XLEN-bit jump-table base address jvt.base that is always aligned on a 64-byte boundary.", + "source_file": "src/unpriv/zcmt.adoc", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > jvt CSR", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 121, + 122 + ] + }, + { + "chunk_id": "chunk_1bd419cf", + "text": "jvt.base is a virtual address, whenever virtual memory is enabled.", + "source_file": "src/unpriv/zcmt.adoc", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > jvt CSR", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 124, + 124 + ] + }, + { + "chunk_id": "chunk_290c2b3d", + "text": "The memory pointed to by jvt.base is treated as instruction memory for the purpose of executing table jump instructions, implying execute access permission.", + "source_file": "src/unpriv/zcmt.adoc", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > jvt CSR", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 126, + 126 + ] + }, + { + "chunk_id": "chunk_28456f50", + "text": "[JVT-config-table] .jvt.mode definition [width=\"60%\",options=header] | | jvt.mode | Comment | 000000 | Jump table mode | others | *reserved for future standard use* |", + "source_file": "src/unpriv/zcmt.adoc", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > jvt CSR", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 128, + 135 + ] + }, + { + "chunk_id": "chunk_e24417c7", + "text": "jvt.mode is a *WARL* field, so can only be programmed to modes which are implemented.", + "source_file": "src/unpriv/zcmt.adoc", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > jvt CSR", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 137, + 138 + ] + }, + { + "chunk_id": "chunk_dcf77a12", + "text": "Therefore the discovery mechanism is to attempt to program different modes and read back the values to see which are available.", + "source_file": "src/unpriv/zcmt.adoc", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > jvt CSR", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 137, + 138 + ] + }, + { + "chunk_id": "chunk_e466a733", + "text": "Jump table mode must be implemented.", + "source_file": "src/unpriv/zcmt.adoc", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > jvt CSR", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 137, + 138 + ] + }, + { + "chunk_id": "chunk_75f4f4e9", + "text": "jvt CSR adds architectural state to the system software context (such as an OS process), therefore must be saved/restored on context switches. <<< [insns-cmjt,reftext=\"Jump via table\"]", + "source_file": "src/unpriv/zcmt.adoc", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > jvt CSR", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 142, + 144 + ] + } + ] + }, + { + "file": "src/unpriv/zfa.adoc", + "chunks": [ + { + "chunk_id": "chunk_189c8c9e", + "text": "The FLI.S instruction loads one of 32 single-precision floating-point constants, encoded in the rs1 field, into floating-point register rd.", + "source_file": "src/unpriv/zfa.adoc", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 14, + 19 + ] + }, + { + "chunk_id": "chunk_32869777", + "text": "The correspondence of rs1 field values and single-precision floating-point values is shown in . FLI.S is encoded like FMV.W.X, but with rs2=1.", + "source_file": "src/unpriv/zfa.adoc", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 14, + 19 + ] + }, + { + "chunk_id": "chunk_d5ccbd86", + "text": "If the D extension is implemented, FLI.D performs the analogous operation, but loads a double-precision value into floating-point register rd.", + "source_file": "src/unpriv/zfa.adoc", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 60, + 66 + ] + }, + { + "chunk_id": "chunk_b30cd70a", + "text": "If the Q extension is implemented, FLI.Q performs the analogous operation, but loads a quad-precision value into floating-point register rd.", + "source_file": "src/unpriv/zfa.adoc", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 68, + 73 + ] + }, + { + "chunk_id": "chunk_3d9edbd1", + "text": "If the Zfh or Zvfh extension is implemented, FLI.H performs the analogous operation, but loads a half-precision floating-point value into register rd.", + "source_file": "src/unpriv/zfa.adoc", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 75, + 84 + ] + }, + { + "chunk_id": "chunk_47f24a88", + "text": "The FLI.fmt instructions never set any floating-point exception flags.", + "source_file": "src/unpriv/zfa.adoc", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 75, + 84 + ] + }, + { + "chunk_id": "chunk_6a907d49", + "text": "If the D extension is implemented, FMINM.D and FMAXM.D instructions are analogously defined to operate on double-precision numbers.", + "source_file": "src/unpriv/zfa.adoc", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Minimum and Maximum Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 93, + 95 + ] + }, + { + "chunk_id": "chunk_0415e4c0", + "text": "If the Zfh extension is implemented, FMINM.H and FMAXM.H instructions are analogously defined to operate on half-precision numbers.", + "source_file": "src/unpriv/zfa.adoc", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Minimum and Maximum Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 97, + 99 + ] + }, + { + "chunk_id": "chunk_ba239815", + "text": "If the Q extension is implemented, FMINM.Q and FMAXM.Q instructions are analogously defined to operate on quad-precision numbers.", + "source_file": "src/unpriv/zfa.adoc", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Minimum and Maximum Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 101, + 103 + ] + }, + { + "chunk_id": "chunk_77a5c549", + "text": "These instructions are encoded like their FMIN and FMAX counterparts, but with instruction bit 13 set to 1.", + "source_file": "src/unpriv/zfa.adoc", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Minimum and Maximum Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 105, + 106 + ] + }, + { + "chunk_id": "chunk_a99ed609", + "text": "The FROUND.S instruction rounds the single-precision floating-point number in floating-point register rs1 to an integer, according to the rounding mode specified in the instruction's rm field.", + "source_file": "src/unpriv/zfa.adoc", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Round-to-Integer Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 109, + 116 + ] + }, + { + "chunk_id": "chunk_b86fedb4", + "text": "Signaling NaN inputs cause the invalid operation exception flag to be set; no other exception flags are set. FROUND.S is encoded like FCVT.S.D, but with rs2=4.", + "source_file": "src/unpriv/zfa.adoc", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Round-to-Integer Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 109, + 116 + ] + }, + { + "chunk_id": "chunk_70da0eb0", + "text": "The FROUNDNX.S instruction is defined similarly, but it also sets the inexact exception flag if the input differs from the rounded result and is not NaN. FROUNDNX.S is encoded like FCVT.S.D, but with rs2=5.", + "source_file": "src/unpriv/zfa.adoc", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Round-to-Integer Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 118, + 121 + ] + }, + { + "chunk_id": "chunk_4a20b922", + "text": "If the D extension is implemented, FROUND.D and FROUNDNX.D instructions are analogously defined to operate on double-precision numbers.", + "source_file": "src/unpriv/zfa.adoc", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Round-to-Integer Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 123, + 126 + ] + }, + { + "chunk_id": "chunk_9d67c274", + "text": "They are encoded like FCVT.D.S, but with rs2=4 and 5, respectively,", + "source_file": "src/unpriv/zfa.adoc", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Round-to-Integer Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 123, + 126 + ] + }, + { + "chunk_id": "chunk_1a226253", + "text": "If the Zfh extension is implemented, FROUND.H and FROUNDNX.H instructions are analogously defined to operate on half-precision numbers.", + "source_file": "src/unpriv/zfa.adoc", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Round-to-Integer Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 128, + 132 + ] + }, + { + "chunk_id": "chunk_0820a252", + "text": "They are encoded like FCVT.H.S, but with rs2=4 and 5, respectively,", + "source_file": "src/unpriv/zfa.adoc", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Round-to-Integer Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 128, + 132 + ] + }, + { + "chunk_id": "chunk_9c917bad", + "text": "If the Q extension is implemented, FROUND.Q and FROUNDNX.Q instructions are analogously defined to operate on quad-precision numbers.", + "source_file": "src/unpriv/zfa.adoc", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Round-to-Integer Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 134, + 137 + ] + }, + { + "chunk_id": "chunk_96c215b1", + "text": "They are encoded like FCVT.Q.S, but with rs2=4 and 5, respectively,", + "source_file": "src/unpriv/zfa.adoc", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Round-to-Integer Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 134, + 137 + ] + }, + { + "chunk_id": "chunk_5d83c8af", + "text": "Bits 31:0 are taken from the rounded, unbounded two's complement result, then sign-extended to XLEN bits and written to integer register rd. \u00b1{inf} and NaN are converted to zero.", + "source_file": "src/unpriv/zfa.adoc", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Modular Convert-to-Integer Instruction", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "range", + "line_range": [ + 140, + 146 + ] + }, + { + "chunk_id": "chunk_789e6ece", + "text": "Floating-point exception flags are raised the same as they would be for FCVT.W.D with the same input operand.", + "source_file": "src/unpriv/zfa.adoc", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Modular Convert-to-Integer Instruction", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 148, + 150 + ] + }, + { + "chunk_id": "chunk_cc9e723a", + "text": "This instruction is only provided if the D extension is implemented.", + "source_file": "src/unpriv/zfa.adoc", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Modular Convert-to-Integer Instruction", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 152, + 154 + ] + }, + { + "chunk_id": "chunk_4c21b2d1", + "text": "It is encoded like FCVT.W.D, but with the rs2 field set to 8 and the rm field set to 1 (RTZ).", + "source_file": "src/unpriv/zfa.adoc", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Modular Convert-to-Integer Instruction", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 152, + 154 + ] + }, + { + "chunk_id": "chunk_bd063bf2", + "text": "For RV32 only, if the D extension is implemented, the FMVH.X.D instruction moves bits 63:32 of floating-point register rs1 into integer register rd.", + "source_file": "src/unpriv/zfa.adoc", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Move Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 157, + 168 + ] + }, + { + "chunk_id": "chunk_7da7a4fa", + "text": "It is encoded in the OP-FP major opcode with funct3=0, rs2=1, and funct7=1110001.", + "source_file": "src/unpriv/zfa.adoc", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Move Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 157, + 168 + ] + }, + { + "chunk_id": "chunk_4ab9ea14", + "text": "For RV32 only, if the D extension is implemented, the FMVP.D.X instruction moves a double-precision number from a pair of integer registers into a floating-point register.", + "source_file": "src/unpriv/zfa.adoc", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Move Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 157, + 168 + ] + }, + { + "chunk_id": "chunk_280451f6", + "text": "For RV64 only, if the Q extension is implemented, the FMVH.X.Q instruction moves bits 127:64 of floating-point register rs1 into integer register rd.", + "source_file": "src/unpriv/zfa.adoc", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Move Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 170, + 181 + ] + }, + { + "chunk_id": "chunk_4e4549a2", + "text": "It is encoded in the OP-FP major opcode with funct3=0, rs2=1, and funct7=1110011.", + "source_file": "src/unpriv/zfa.adoc", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Move Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 170, + 181 + ] + }, + { + "chunk_id": "chunk_a1bf2a22", + "text": "For RV64 only, if the Q extension is implemented, the FMVP.Q.X instruction moves a double-precision number from a pair of integer registers into a floating-point register.", + "source_file": "src/unpriv/zfa.adoc", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Move Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 170, + 181 + ] + }, + { + "chunk_id": "chunk_33b26964", + "text": "The FLEQ.S and FLTQ.S instructions are defined like the FLE.S and FLT.S instructions, except that quiet NaN inputs do not cause the invalid operation exception flag to be set.", + "source_file": "src/unpriv/zfa.adoc", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Comparison Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 185, + 188 + ] + }, + { + "chunk_id": "chunk_69d6a512", + "text": "If the D extension is implemented, FLEQ.D and FLTQ.D instructions are analogously defined to operate on double-precision numbers.", + "source_file": "src/unpriv/zfa.adoc", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Comparison Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 190, + 192 + ] + }, + { + "chunk_id": "chunk_5ebd38b0", + "text": "If the Zfh extension is implemented, FLEQ.H and FLTQ.H instructions are analogously defined to operate on half-precision numbers.", + "source_file": "src/unpriv/zfa.adoc", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Comparison Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 194, + 196 + ] + }, + { + "chunk_id": "chunk_6dd6158a", + "text": "If the Q extension is implemented, FLEQ.Q and FLTQ.Q instructions are analogously defined to operate on quad-precision numbers.", + "source_file": "src/unpriv/zfa.adoc", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Comparison Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 198, + 200 + ] + }, + { + "chunk_id": "chunk_311b4175", + "text": "These instructions are encoded like their FLE and FLT counterparts, but with instruction bit 14 set to 1.", + "source_file": "src/unpriv/zfa.adoc", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Comparison Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "binary", + "line_range": [ + 202, + 203 + ] + } + ] + }, + { + "file": "src/unpriv/zfbfmin.adoc", + "chunks": [ + { + "chunk_id": "chunk_465554a9", + "text": "BF16 computational instructions defined in this chapter support all IEEE 754-2008 features, including all rounding modes, subnormal inputs and outputs, overflow and underflow, and default exception handling.", + "source_file": "src/unpriv/zfbfmin.adoc", + "section": "Preamble > `Zfbfmin` Extension for Scalar BFloat16 Conversions > BF16 Number Format", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 30, + 34 + ] + }, + { + "chunk_id": "chunk_cb2c536c", + "text": "BF16 values are NaN-boxed when held in `f` registers, as described in .", + "source_file": "src/unpriv/zfbfmin.adoc", + "section": "Preamble > `Zfbfmin` Extension for Scalar BFloat16 Conversions > BF16 Number Format", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 38, + 38 + ] + }, + { + "chunk_id": "chunk_2eb3bd2e", + "text": "Round according to the RM field.", + "source_file": "src/unpriv/zfbfmin.adoc", + "section": "Preamble > `Zfbfmin` Extension for Scalar BFloat16 Conversions > BF16 Number Format > fcvt.bf16.s", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 62, + 64 + ] + } + ] + }, + { + "file": "src/unpriv/zfh.adoc", + "chunks": [ + { + "chunk_id": "chunk_e619a18c", + "text": "The NaN-boxing scheme described in is extended to allow a half-precision value to be NaN-boxed inside a single-precision value (which may be recursively NaN-boxed inside a double- or quad-precision value when the D or Q extension is present).", + "source_file": "src/unpriv/zfh.adoc", + "section": "Preamble > `Zfh` Extension for Half-Precision Floating-Point", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 3, + 9 + ] + }, + { + "chunk_id": "chunk_226b1613", + "text": "New 16-bit variants of LOAD-FP and STORE-FP instructions are added, encoded with a new value for the funct3 width field.", + "source_file": "src/unpriv/zfh.adoc", + "section": "Preamble > `Zfh` Extension for Half-Precision Floating-Point > Half-Precision Load and Store Instructions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 13, + 15 + ] + }, + { + "chunk_id": "chunk_e98cc70a", + "text": "FLH and FSH are only guaranteed to execute atomically if the effective address is naturally aligned.", + "source_file": "src/unpriv/zfh.adoc", + "section": "Preamble > `Zfh` Extension for Half-Precision Floating-Point > Half-Precision Load and Store Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 21, + 23 + ] + }, + { + "chunk_id": "chunk_5fc0d0c2", + "text": "FLH and FSH do not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved. FLH NaN-boxes the result written to rd, whereas FSH ignores all but the lower 16 bits in rs2.", + "source_file": "src/unpriv/zfh.adoc", + "section": "Preamble > `Zfh` Extension for Half-Precision Floating-Point > Half-Precision Load and Store Instructions", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 25, + 28 + ] + }, + { + "chunk_id": "chunk_fc637e5d", + "text": "A new supported format is added to the format field of most instructions, as shown in .", + "source_file": "src/unpriv/zfh.adoc", + "section": "Preamble > `Zfh` Extension for Half-Precision Floating-Point > Half-Precision Load and Store Instructions > Half-Precision Computational Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 32, + 33 + ] + }, + { + "chunk_id": "chunk_02f65601", + "text": "These instructions are defined analogously to the single-precision-to-integer and integer-to-single-precision conversion instructions. FCVT.W.H or FCVT.L.H converts a half-precision floating-point number to a signed 32-bit or 64-bit integer, respectively. FCVT.H.W or FCVT.H.L converts a 32-bit or 64-bit signed integer, respectively, into a half-precision floating-point number. FCVT.WU.H, FCVT.LU.H, FCVT.H.WU, and FCVT.H.LU variants convert to or from unsigned integer values. FCVT.L[U].H and FCVT.H.L[U] are RV64-only instructions.", + "source_file": "src/unpriv/zfh.adoc", + "section": "Preamble > `Zfh` Extension for Half-Precision Floating-Point > Half-Precision Load and Store Instructions > Half-Precision Conversion and Move Instructions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 57, + 66 + ] + }, + { + "chunk_id": "chunk_f4b30396", + "text": "If the D extension is present, FCVT.D.H or FCVT.H.D converts a half-precision floating-point number to a double-precision floating-point number, or vice-versa, respectively.", + "source_file": "src/unpriv/zfh.adoc", + "section": "Preamble > `Zfh` Extension for Half-Precision Floating-Point > Half-Precision Load and Store Instructions > Half-Precision Conversion and Move Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 71, + 81 + ] + }, + { + "chunk_id": "chunk_3526cc83", + "text": "If the Q extension is present, FCVT.Q.H or FCVT.H.Q converts a half-precision floating-point number to a quad-precision floating-point number, or vice-versa, respectively.", + "source_file": "src/unpriv/zfh.adoc", + "section": "Preamble > `Zfh` Extension for Half-Precision Floating-Point > Half-Precision Load and Store Instructions > Half-Precision Conversion and Move Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 71, + 81 + ] + }, + { + "chunk_id": "chunk_0511159c", + "text": "Instructions are provided to move bit patterns between the floating-point and integer registers. FMV.X.H moves the half-precision value in floating-point register rs1 to a representation in the IEEE 754-2008 encoding in integer register rd, filling the upper XLEN-16 bits with copies of the floating-point number's sign bit.", + "source_file": "src/unpriv/zfh.adoc", + "section": "Preamble > `Zfh` Extension for Half-Precision Floating-Point > Half-Precision Load and Store Instructions > Half-Precision Conversion and Move Instructions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 94, + 99 + ] + }, + { + "chunk_id": "chunk_ee726b52", + "text": "FMV.H.X moves the half-precision value encoded in the IEEE 754-2008 encoding from the lower 16 bits of integer register rs1 to the floating-point register rd, NaN-boxing the result.", + "source_file": "src/unpriv/zfh.adoc", + "section": "Preamble > `Zfh` Extension for Half-Precision Floating-Point > Half-Precision Load and Store Instructions > Half-Precision Conversion and Move Instructions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 101, + 104 + ] + } + ] + }, + { + "file": "src/unpriv/zfhmin.adoc", + "chunks": [ + { + "chunk_id": "chunk_132f54af", + "text": "This section describes the Zfhmin standard extension, which provides minimal support for 16-bit half-precision binary floating-point instructions.", + "source_file": "src/unpriv/zfhmin.adoc", + "section": "Preamble > ext:zfhmin[] Extension for Minimal Half-Precision Floating-Point", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 3, + 10 + ] + }, + { + "chunk_id": "chunk_b89ce9f3", + "text": "If the D extension is present, the FCVT.D.H and FCVT.H.D instructions are also included.", + "source_file": "src/unpriv/zfhmin.adoc", + "section": "Preamble > ext:zfhmin[] Extension for Minimal Half-Precision Floating-Point", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 12, + 17 + ] + }, + { + "chunk_id": "chunk_4eacfc81", + "text": "If the Q extension is present, the FCVT.Q.H and FCVT.H.Q instructions are additionally included.", + "source_file": "src/unpriv/zfhmin.adoc", + "section": "Preamble > ext:zfhmin[] Extension for Minimal Half-Precision Floating-Point", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 12, + 17 + ] + } + ] + }, + { + "file": "src/unpriv/zfinx.adoc", + "chunks": [ + { + "chunk_id": "chunk_09884646", + "text": "This chapter defines the \"Zfinx\" extension (pronounced \"z-f-in-x\") that provides instructions similar to those in the standard floating-point F extension for single-precision floating-point instructions but which operate on the `x` registers instead of the `f` registers.", + "source_file": "src/unpriv/zfinx.adoc", + "section": "Preamble > \"Zfinx\", \"Zdinx\", \"Zhinx\", \"Zhinxmin\" Extensions for Floating-Point in Integer Registers, Version 1.0", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 3, + 9 + ] + }, + { + "chunk_id": "chunk_49710c2f", + "text": "This chapter also defines the \"Zdinx\", \"Zhinx\", and \"Zhinxmin\" extensions that provide similar instructions for other floating-point precisions.", + "source_file": "src/unpriv/zfinx.adoc", + "section": "Preamble > \"Zfinx\", \"Zdinx\", \"Zhinx\", \"Zhinxmin\" Extensions for Floating-Point in Integer Registers, Version 1.0", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 3, + 9 + ] + }, + { + "chunk_id": "chunk_9bda02a6", + "text": "The Zfinx extension adds all of the instructions that the F extension adds, except for the transfer instructions FLW, FSW, FMV.W.X, FMV.X.W, C.FLW[SP], and C.FSW[SP].", + "source_file": "src/unpriv/zfinx.adoc", + "section": "Preamble > \"Zfinx\", \"Zdinx\", \"Zhinx\", \"Zhinxmin\" Extensions for Floating-Point in Integer Registers, Version 1.0", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 11, + 14 + ] + }, + { + "chunk_id": "chunk_9be62281", + "text": "The Zfinx variants of these F-extension instructions have the same semantics, except that whenever such an instruction would have accessed an `f` register, it instead accesses the `x` register with the same number.", + "source_file": "src/unpriv/zfinx.adoc", + "section": "Preamble > \"Zfinx\", \"Zdinx\", \"Zhinx\", \"Zhinxmin\" Extensions for Floating-Point in Integer Registers, Version 1.0", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 16, + 20 + ] + }, + { + "chunk_id": "chunk_3c7e9006", + "text": "The Zfinx extension depends on the \"Zicsr\" extension for control and status register access.", + "source_file": "src/unpriv/zfinx.adoc", + "section": "Preamble > \"Zfinx\", \"Zdinx\", \"Zhinx\", \"Zhinxmin\" Extensions for Floating-Point in Integer Registers, Version 1.0", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 22, + 22 + ] + }, + { + "chunk_id": "chunk_23088c1f", + "text": "Floating-point operands of width w < XLEN bits occupy bits w-1:0 of an `x` register.", + "source_file": "src/unpriv/zfinx.adoc", + "section": "Preamble > \"Zfinx\", \"Zdinx\", \"Zhinx\", \"Zhinxmin\" Extensions for Floating-Point in Integer Registers, Version 1.0 > Processing of Narrower Values", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "range", + "line_range": [ + 26, + 29 + ] + }, + { + "chunk_id": "chunk_23e363e3", + "text": "Floating-point operations on w-bit operands ignore operand bits XLEN-1: w.", + "source_file": "src/unpriv/zfinx.adoc", + "section": "Preamble > \"Zfinx\", \"Zdinx\", \"Zhinx\", \"Zhinxmin\" Extensions for Floating-Point in Integer Registers, Version 1.0 > Processing of Narrower Values", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 26, + 29 + ] + }, + { + "chunk_id": "chunk_f61810ad", + "text": "Floating-point operations that produce w < XLEN-bit results fill bits XLEN-1: w with copies of bit w-1 (the sign bit).", + "source_file": "src/unpriv/zfinx.adoc", + "section": "Preamble > \"Zfinx\", \"Zdinx\", \"Zhinx\", \"Zhinxmin\" Extensions for Floating-Point in Integer Registers, Version 1.0 > Processing of Narrower Values", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "range", + "line_range": [ + 31, + 33 + ] + }, + { + "chunk_id": "chunk_ceba460d", + "text": "The Zdinx extension provides analogous double-precision floating-point instructions.", + "source_file": "src/unpriv/zfinx.adoc", + "section": "Preamble > \"Zfinx\", \"Zdinx\", \"Zhinx\", \"Zhinxmin\" Extensions for Floating-Point in Integer Registers, Version 1.0 > Processing of Narrower Values > Zdinx", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 37, + 38 + ] + }, + { + "chunk_id": "chunk_a0040fcd", + "text": "The Zdinx extension depends upon the Zfinx extension.", + "source_file": "src/unpriv/zfinx.adoc", + "section": "Preamble > \"Zfinx\", \"Zdinx\", \"Zhinx\", \"Zhinxmin\" Extensions for Floating-Point in Integer Registers, Version 1.0 > Processing of Narrower Values > Zdinx", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 37, + 38 + ] + }, + { + "chunk_id": "chunk_68d1455c", + "text": "The Zdinx extension adds all of the instructions that the D extension adds, except for the transfer instructions FLD, FSD, FMV.D.X, FMV.X.D, C.FLD[SP], and C.FSD[SP].", + "source_file": "src/unpriv/zfinx.adoc", + "section": "Preamble > \"Zfinx\", \"Zdinx\", \"Zhinx\", \"Zhinxmin\" Extensions for Floating-Point in Integer Registers, Version 1.0 > Processing of Narrower Values > Zdinx", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 40, + 43 + ] + }, + { + "chunk_id": "chunk_1b7e1fd7", + "text": "The Zdinx variants of these D-extension instructions have the same semantics, except that whenever such an instruction would have accessed an `f` register, it instead accesses the `x` register with the same number.", + "source_file": "src/unpriv/zfinx.adoc", + "section": "Preamble > \"Zfinx\", \"Zdinx\", \"Zhinx\", \"Zhinxmin\" Extensions for Floating-Point in Integer Registers, Version 1.0 > Processing of Narrower Values > Zdinx", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 45, + 49 + ] + }, + { + "chunk_id": "chunk_93feb562", + "text": "Double-precision operands in RV32Zdinx are held in aligned `x`-register pairs, i.e., register numbers must be even.", + "source_file": "src/unpriv/zfinx.adoc", + "section": "Preamble > \"Zfinx\", \"Zdinx\", \"Zhinx\", \"Zhinxmin\" Extensions for Floating-Point in Integer Registers, Version 1.0 > Processing of Narrower Values > Processing of Wider Values", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 53, + 57 + ] + }, + { + "chunk_id": "chunk_4dca5e84", + "text": "Use of misaligned (odd-numbered) registers for double-width floating-point operands is reserved.", + "source_file": "src/unpriv/zfinx.adoc", + "section": "Preamble > \"Zfinx\", \"Zdinx\", \"Zhinx\", \"Zhinxmin\" Extensions for Floating-Point in Integer Registers, Version 1.0 > Processing of Narrower Values > Processing of Wider Values", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 53, + 57 + ] + }, + { + "chunk_id": "chunk_0f200b97", + "text": "The Zhinx extension provides analogous half-precision floating-point instructions.", + "source_file": "src/unpriv/zfinx.adoc", + "section": "Preamble > \"Zfinx\", \"Zdinx\", \"Zhinx\", \"Zhinxmin\" Extensions for Floating-Point in Integer Registers, Version 1.0 > Processing of Narrower Values > Zhinx", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 77, + 78 + ] + }, + { + "chunk_id": "chunk_eac83960", + "text": "The Zhinx extension depends upon the Zfinx extension.", + "source_file": "src/unpriv/zfinx.adoc", + "section": "Preamble > \"Zfinx\", \"Zdinx\", \"Zhinx\", \"Zhinxmin\" Extensions for Floating-Point in Integer Registers, Version 1.0 > Processing of Narrower Values > Zhinx", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 77, + 78 + ] + }, + { + "chunk_id": "chunk_6df97b08", + "text": "The Zhinx extension adds all of the instructions that the Zfh extension adds, except for the transfer instructions FLH, FSH, FMV.H.X, and FMV.X.H.", + "source_file": "src/unpriv/zfinx.adoc", + "section": "Preamble > \"Zfinx\", \"Zdinx\", \"Zhinx\", \"Zhinxmin\" Extensions for Floating-Point in Integer Registers, Version 1.0 > Processing of Narrower Values > Zhinx", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 80, + 83 + ] + }, + { + "chunk_id": "chunk_4dd6daf3", + "text": "The Zhinx variants of these Zfh-extension instructions have the same semantics, except that whenever such an instruction would have accessed an `f` register, it instead accesses the `x` register with the same number.", + "source_file": "src/unpriv/zfinx.adoc", + "section": "Preamble > \"Zfinx\", \"Zdinx\", \"Zhinx\", \"Zhinxmin\" Extensions for Floating-Point in Integer Registers, Version 1.0 > Processing of Narrower Values > Zhinx", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 85, + 89 + ] + }, + { + "chunk_id": "chunk_582f03d4", + "text": "The Zhinxmin extension provides minimal support for 16-bit half-precision floating-point instructions that operate on the `x` registers.", + "source_file": "src/unpriv/zfinx.adoc", + "section": "Preamble > \"Zfinx\", \"Zdinx\", \"Zhinx\", \"Zhinxmin\" Extensions for Floating-Point in Integer Registers, Version 1.0 > Processing of Narrower Values > Zhinxmin", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 93, + 95 + ] + }, + { + "chunk_id": "chunk_4e6d87b6", + "text": "The Zhinxmin extension depends upon the Zfinx extension.", + "source_file": "src/unpriv/zfinx.adoc", + "section": "Preamble > \"Zfinx\", \"Zdinx\", \"Zhinx\", \"Zhinxmin\" Extensions for Floating-Point in Integer Registers, Version 1.0 > Processing of Narrower Values > Zhinxmin", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 93, + 95 + ] + }, + { + "chunk_id": "chunk_4823d6b3", + "text": "The Zhinxmin extension includes the following instructions from the Zhinx extension: FCVT.S.H and FCVT.H.S.", + "source_file": "src/unpriv/zfinx.adoc", + "section": "Preamble > \"Zfinx\", \"Zdinx\", \"Zhinx\", \"Zhinxmin\" Extensions for Floating-Point in Integer Registers, Version 1.0 > Processing of Narrower Values > Zhinxmin", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 97, + 100 + ] + }, + { + "chunk_id": "chunk_fe0759c9", + "text": "If the Zdinx extension is present, the FCVT.D.H and FCVT.H.D instructions are also included.", + "source_file": "src/unpriv/zfinx.adoc", + "section": "Preamble > \"Zfinx\", \"Zdinx\", \"Zhinx\", \"Zhinxmin\" Extensions for Floating-Point in Integer Registers, Version 1.0 > Processing of Narrower Values > Zhinxmin", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 97, + 100 + ] + }, + { + "chunk_id": "chunk_7323e61e", + "text": "As described in , the `mstatus` field FS is hardwired to 0 if the Zfinx extension is implemented, and FS no longer affects the trapping behavior of floating-point instructions or `fcsr` accesses.", + "source_file": "src/unpriv/zfinx.adoc", + "section": "Preamble > \"Zfinx\", \"Zdinx\", \"Zhinx\", \"Zhinxmin\" Extensions for Floating-Point in Integer Registers, Version 1.0 > Processing of Narrower Values > Privileged Architecture Implications", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 103, + 107 + ] + }, + { + "chunk_id": "chunk_2f2a0fc2", + "text": "The `misa` bits F, D, and Q are hardwired to 0 when the Zfinx extension is implemented.", + "source_file": "src/unpriv/zfinx.adoc", + "section": "Preamble > \"Zfinx\", \"Zdinx\", \"Zhinx\", \"Zhinxmin\" Extensions for Floating-Point in Integer Registers, Version 1.0 > Processing of Narrower Values > Privileged Architecture Implications", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 109, + 111 + ] + } + ] + }, + { + "file": "src/unpriv/zi.adoc", + "chunks": [ + { + "chunk_id": "chunk_2350c40d", + "text": "Most of these extensions are accordingly named with the prefix \"Zi\", with the exception of the integer multiplication and division extensions, which are named \"M\" or prefixed with \"Zm\".", + "source_file": "src/unpriv/zi.adoc", + "section": "Preamble > Scalar Integer Extensions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 6, + 9 + ] + } + ] + }, + { + "file": "src/unpriv/zic64b.adoc", + "chunks": [ + { + "chunk_id": "chunk_844e38f9", + "text": "If the Zic64b extension is implemented, then cache blocks must be 64 bytes in size, naturally aligned in the address space.", + "source_file": "src/unpriv/zic64b.adoc", + "section": "Preamble > Zic64b Extension for 64-byte Cache Blocks, Version 1.0", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 3, + 4 + ] + } + ] + }, + { + "file": "src/unpriv/ziccamoa.adoc", + "chunks": [ + { + "chunk_id": "chunk_873e17a8", + "text": "If the Ziccamoa extension is implemented, then main memory regions with both the cacheability and coherence PMAs must support all atomics in the Zaamo extension.", + "source_file": "src/unpriv/ziccamoa.adoc", + "section": "Preamble > Ziccamoa Extension for Main Memory Atomics, Version 1.0", + "confidence": "very_high", + "parameter_class": "SW_rule", + "parameter_type": "binary", + "line_range": [ + 3, + 5 + ] + } + ] + }, + { + "file": "src/unpriv/ziccamoc.adoc", + "chunks": [ + { + "chunk_id": "chunk_a1df76c9", + "text": "If the Ziccamoc extension is implemented, then main memory regions with both the cacheability and coherence PMAs must provide ``AMOCASQ``-level PMA support.", + "source_file": "src/unpriv/ziccamoc.adoc", + "section": "Preamble > Ziccamoc Extension for Main Memory Compare-and-Swap, Version 1.0", + "confidence": "very_high", + "parameter_class": "SW_rule", + "parameter_type": "binary", + "line_range": [ + 3, + 5 + ] + } + ] + }, + { + "file": "src/unpriv/ziccif.adoc", + "chunks": [ + { + "chunk_id": "chunk_fac5a4e4", + "text": "If the Ziccif extension is implemented, main memory regions with both the cacheability and coherence PMAs must support instruction fetch, and any instruction fetches of naturally aligned power-of-2 sizes of at most `min(ILEN,XLEN)` bits are atomic.", + "source_file": "src/unpriv/ziccif.adoc", + "section": "Preamble > Ziccif Extension for Instruction-Fetch Atomicity, Version 1.0", + "confidence": "very_high", + "parameter_class": "SW_rule", + "parameter_type": "range", + "line_range": [ + 7, + 10 + ] + }, + { + "chunk_id": "chunk_bdeb387b", + "text": "An implementation with the Ziccif extension fetches instructions in a manner equivalent to the following state machine.", + "source_file": "src/unpriv/ziccif.adoc", + "section": "Preamble > Ziccif Extension for Instruction-Fetch Atomicity, Version 1.0", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 12, + 13 + ] + }, + { + "chunk_id": "chunk_89eaef06", + "text": "If the `T` bytes fetched begin with a complete instruction of length `L` {le} `T`, then execute that instruction, discard the remaining `T` - `L` bytes fetched, and go back to step 1, using the updated `pc`.", + "source_file": "src/unpriv/ziccif.adoc", + "section": "Preamble > Ziccif Extension for Instruction-Fetch Atomicity, Version 1.0", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 20, + 24 + ] + } + ] + }, + { + "file": "src/unpriv/zicclsm.adoc", + "chunks": [ + { + "chunk_id": "chunk_79748322", + "text": "If the Zicclsm extension is implemented, then misaligned loads and stores to main memory regions with both the cacheability and coherence PMAs must be supported.", + "source_file": "src/unpriv/zicclsm.adoc", + "section": "Preamble > Zicclsm Extension for Main Memory Misaligned Accesses, Version 1.0", + "confidence": "very_high", + "parameter_class": "SW_rule", + "parameter_type": "binary", + "line_range": [ + 3, + 5 + ] + }, + { + "chunk_id": "chunk_463acae0", + "text": "Standard software distributions should assume their existence only for correctness, not for performance.", + "source_file": "src/unpriv/zicclsm.adoc", + "section": "Preamble > Zicclsm Extension for Main Memory Misaligned Accesses, Version 1.0", + "confidence": "medium", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 10, + 13 + ] + } + ] + }, + { + "file": "src/unpriv/ziccrse.adoc", + "chunks": [ + { + "chunk_id": "chunk_a63db0e0", + "text": "If the Ziccrse extension is implemented, then main memory regions with both the cacheability and coherence PMAs must support the RsrvEventual PMA.", + "source_file": "src/unpriv/ziccrse.adoc", + "section": "Preamble > Ziccrse Extension for Main Memory Reservability, Version 1.0", + "confidence": "very_high", + "parameter_class": "SW_rule", + "parameter_type": "binary", + "line_range": [ + 3, + 4 + ] + } + ] + }, + { + "file": "src/unpriv/zicntr.adoc", + "chunks": [ + { + "chunk_id": "chunk_479e1cd1", + "text": "RISC-V ISAs provide a set of up to thirty-two 64-bit performance counters and timers that are accessible via unprivileged XLEN-bit read-only CSR registers `0xC00`\u2013`0xC1F` (when XLEN=32, the upper 32 bits are accessed via CSR registers `0xC80`\u2013`0xC9F`).", + "source_file": "src/unpriv/zicntr.adoc", + "section": "Preamble > \"Zicntr\" Extension for Base Counters and Timers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 3, + 7 + ] + }, + { + "chunk_id": "chunk_c408604e", + "text": "The Zicntr extension depends on the Zicsr extension.", + "source_file": "src/unpriv/zicntr.adoc", + "section": "Preamble > \"Zicntr\" Extension for Base Counters and Timers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 9, + 12 + ] + }, + { + "chunk_id": "chunk_288606bf", + "text": "For base ISAs with XLEN{ge}64, CSR instructions can access the full 64-bit CSRs directly.", + "source_file": "src/unpriv/zicntr.adoc", + "section": "Preamble > \"Zicntr\" Extension for Base Counters and Timers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 16, + 19 + ] + }, + { + "chunk_id": "chunk_73778658", + "text": "In particular, the RDCYCLE, RDTIME, and RDINSTRET pseudoinstructions read the full 64 bits of the `cycle`, `time`, and `instret` counters.", + "source_file": "src/unpriv/zicntr.adoc", + "section": "Preamble > \"Zicntr\" Extension for Base Counters and Timers", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 16, + 19 + ] + }, + { + "chunk_id": "chunk_ea4b7db1", + "text": "For base ISAs with XLEN=32, the Zicntr extension enables the three 64-bit read-only counters to be accessed in 32-bit pieces.", + "source_file": "src/unpriv/zicntr.adoc", + "section": "Preamble > \"Zicntr\" Extension for Base Counters and Timers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 21, + 57 + ] + }, + { + "chunk_id": "chunk_fb251695", + "text": "The RDCYCLE, RDTIME, and RDINSTRET pseudoinstructions provide the lower 32 bits, and the RDCYCLEH, RDTIMEH, and RDINSTRETH pseudoinstructions provide the upper 32 bits of the respective counters.", + "source_file": "src/unpriv/zicntr.adoc", + "section": "Preamble > \"Zicntr\" Extension for Base Counters and Timers", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 21, + 57 + ] + }, + { + "chunk_id": "chunk_9db69357", + "text": "The RDCYCLE pseudoinstruction reads the low XLEN bits of the `cycle` CSR which holds a count of the number of clock cycles executed by the processor core on which the hart is running from an arbitrary start time in the past. RDCYCLEH is only present when XLEN=32 and reads bits 63-32 of the same cycle counter.", + "source_file": "src/unpriv/zicntr.adoc", + "section": "Preamble > \"Zicntr\" Extension for Base Counters and Timers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 21, + 57 + ] + }, + { + "chunk_id": "chunk_a477e9fd", + "text": "The execution environment should provide a means to determine the current rate (cycles/second) at which the cycle counter is incrementing.", + "source_file": "src/unpriv/zicntr.adoc", + "section": "Preamble > \"Zicntr\" Extension for Base Counters and Timers", + "confidence": "medium", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 21, + 57 + ] + }, + { + "chunk_id": "chunk_93dcfd5e", + "text": "The RDTIME pseudoinstruction reads the low XLEN bits of the \"time\" CSR, which counts wall-clock real time that has passed from an arbitrary start time in the past. RDTIMEH is only present when XLEN=32 and reads bits 63-32 of the same real-time counter.", + "source_file": "src/unpriv/zicntr.adoc", + "section": "Preamble > \"Zicntr\" Extension for Base Counters and Timers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 21, + 57 + ] + }, + { + "chunk_id": "chunk_7e76bafb", + "text": "The execution environment should provide a means of determining the period of a counter tick (seconds/tick).", + "source_file": "src/unpriv/zicntr.adoc", + "section": "Preamble > \"Zicntr\" Extension for Base Counters and Timers", + "confidence": "medium", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 21, + 57 + ] + }, + { + "chunk_id": "chunk_6c022daa", + "text": "The period should be constant within a small error bound.", + "source_file": "src/unpriv/zicntr.adoc", + "section": "Preamble > \"Zicntr\" Extension for Base Counters and Timers", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 21, + 57 + ] + }, + { + "chunk_id": "chunk_d078367c", + "text": "The real-time clocks of all harts must be synchronized to within one tick of the real-time clock.", + "source_file": "src/unpriv/zicntr.adoc", + "section": "Preamble > \"Zicntr\" Extension for Base Counters and Timers", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 21, + 57 + ] + }, + { + "chunk_id": "chunk_dd32d15f", + "text": "The RDINSTRET pseudoinstruction reads the low XLEN bits of the `instret` CSR, which counts the number of instructions retired by this hart from some arbitrary start point in the past. RDINSTRETH is only present when XLEN=32 and reads bits 63-32 of the same instruction counter.", + "source_file": "src/unpriv/zicntr.adoc", + "section": "Preamble > \"Zicntr\" Extension for Base Counters and Timers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 21, + 57 + ] + }, + { + "chunk_id": "chunk_68f2c698", + "text": "The following code sequence will read a valid 64-bit cycle counter value into `x3:x2`, even if the counter overflows its lower half between reading its upper and lower halves.", + "source_file": "src/unpriv/zicntr.adoc", + "section": "Preamble > \"Zicntr\" Extension for Base Counters and Timers", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 21, + 57 + ] + }, + { + "chunk_id": "chunk_12ddb6a0", + "text": "[source,asm.] .Sample code for reading the 64-bit cycle counter when XLEN=32. again: rdcycleh x3 rdcycle x2 rdcycleh x4 bne x3, x4, again", + "source_file": "src/unpriv/zicntr.adoc", + "section": "Preamble > \"Zicntr\" Extension for Base Counters and Timers", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 59, + 65 + ] + } + ] + }, + { + "file": "src/unpriv/zicond.adoc", + "chunks": [ + { + "chunk_id": "chunk_a1214c6d", + "text": "[insns-czero-eqz,reftext=\"Conditional zero, if condition is equal to zero\"]", + "source_file": "src/unpriv/zicond.adoc", + "section": "Preamble > \"Zicond\" Extension for Integer Conditional Operations, Version 1.0.0 > Instructions (in alphabetical order)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "range", + "line_range": [ + 27, + 27 + ] + }, + { + "chunk_id": "chunk_86864e34", + "text": "If rs2 contains the value zero, this instruction writes the value zero to rd.", + "source_file": "src/unpriv/zicond.adoc", + "section": "Preamble > \"Zicond\" Extension for Integer Conditional Operations, Version 1.0.0 > Instructions (in alphabetical order) > czero.eqz", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 49, + 51 + ] + }, + { + "chunk_id": "chunk_05762067", + "text": "Furthermore, if the Zkt extension is implemented, this instruction's timing is independent of the data values in rs1 and rs2.", + "source_file": "src/unpriv/zicond.adoc", + "section": "Preamble > \"Zicond\" Extension for Integer Conditional Operations, Version 1.0.0 > Instructions (in alphabetical order) > czero.eqz", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 53, + 55 + ] + }, + { + "chunk_id": "chunk_52ed35c9", + "text": "If rs2 contains a nonzero value, this instruction writes the value zero to rd.", + "source_file": "src/unpriv/zicond.adoc", + "section": "Preamble > \"Zicond\" Extension for Integer Conditional Operations, Version 1.0.0 > Instructions (in alphabetical order) > czero.eqz > czero.nez", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 90, + 92 + ] + }, + { + "chunk_id": "chunk_b666cd86", + "text": "Furthermore, if the Zkt extension is implemented, this instruction's timing is independent of the data values in rs1 and rs2.", + "source_file": "src/unpriv/zicond.adoc", + "section": "Preamble > \"Zicond\" Extension for Integer Conditional Operations, Version 1.0.0 > Instructions (in alphabetical order) > czero.eqz > czero.nez", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 94, + 96 + ] + }, + { + "chunk_id": "chunk_1331da3c", + "text": "|*Conditional add, if zero* + `rd = (rc 0) ? (rs1 + rs2) : rs1` |czero.nez rd, rs2, rc add rd, rs1, rd .8+.^|2 insns", + "source_file": "src/unpriv/zicond.adoc", + "section": "Preamble > \"Zicond\" Extension for Integer Conditional Operations, Version 1.0.0 > Instructions (in alphabetical order) > Usage examples > Instruction sequences", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 119, + 123 + ] + }, + { + "chunk_id": "chunk_3f9ac21d", + "text": "|*Conditional add, if non-zero* + `rd = (rc != 0) ? (rs1 + rs2) : rs1` |czero.eqz rd, rs2, rc add rd, rs1, rd", + "source_file": "src/unpriv/zicond.adoc", + "section": "Preamble > \"Zicond\" Extension for Integer Conditional Operations, Version 1.0.0 > Instructions (in alphabetical order) > Usage examples > Instruction sequences", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 125, + 128 + ] + }, + { + "chunk_id": "chunk_f0cc4d6d", + "text": "|*Conditional subtract, if zero* + `rd = (rc 0) ? (rs1 - rs2) : rs1` |czero.nez rd, rs2, rc sub rd, rs1, rd", + "source_file": "src/unpriv/zicond.adoc", + "section": "Preamble > \"Zicond\" Extension for Integer Conditional Operations, Version 1.0.0 > Instructions (in alphabetical order) > Usage examples > Instruction sequences", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 130, + 133 + ] + }, + { + "chunk_id": "chunk_0d764e52", + "text": "|*Conditional subtract, if non-zero* + `rd = (rc != 0) ? (rs1 - rs2) : rs1` |czero.eqz rd, rs2, rc sub rd, rs1, rd", + "source_file": "src/unpriv/zicond.adoc", + "section": "Preamble > \"Zicond\" Extension for Integer Conditional Operations, Version 1.0.0 > Instructions (in alphabetical order) > Usage examples > Instruction sequences", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 135, + 138 + ] + }, + { + "chunk_id": "chunk_03c75558", + "text": "|*Conditional bitwise-or, if zero* + `rd = (rc 0) ? (rs1 \\| rs2) : rs1` |czero.nez rd, rs2, rc or rd, rs1, rd", + "source_file": "src/unpriv/zicond.adoc", + "section": "Preamble > \"Zicond\" Extension for Integer Conditional Operations, Version 1.0.0 > Instructions (in alphabetical order) > Usage examples > Instruction sequences", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 140, + 143 + ] + }, + { + "chunk_id": "chunk_10c1a422", + "text": "|*Conditional bitwise-or, if non-zero* + `rd = (rc != 0) ? (rs1 \\| rs2) : rs1` |czero.eqz rd, rs2, rc or rd, rs1, rd", + "source_file": "src/unpriv/zicond.adoc", + "section": "Preamble > \"Zicond\" Extension for Integer Conditional Operations, Version 1.0.0 > Instructions (in alphabetical order) > Usage examples > Instruction sequences", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 145, + 148 + ] + }, + { + "chunk_id": "chunk_f5f24e63", + "text": "|*Conditional bitwise-xor, if zero* + `rd = (rc 0) ? (rs1 ^ rs2) : rs1` |czero.nez rd, rs2, rc xor rd, rs1, rd", + "source_file": "src/unpriv/zicond.adoc", + "section": "Preamble > \"Zicond\" Extension for Integer Conditional Operations, Version 1.0.0 > Instructions (in alphabetical order) > Usage examples > Instruction sequences", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 150, + 153 + ] + }, + { + "chunk_id": "chunk_a97d94a3", + "text": "|*Conditional bitwise-xor, if non-zero* + `rd = (rc != 0) ? (rs1 ^ rs2) : rs1` |czero.eqz rd, rs2, rc xor rd, rs1, rd", + "source_file": "src/unpriv/zicond.adoc", + "section": "Preamble > \"Zicond\" Extension for Integer Conditional Operations, Version 1.0.0 > Instructions (in alphabetical order) > Usage examples > Instruction sequences", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 155, + 158 + ] + }, + { + "chunk_id": "chunk_79abb737", + "text": "|*Conditional bitwise-and, if zero* + `rd = (rc 0) ? (rs1 & rs2) : rs1` |and rd, rs1, rs2 czero.eqz rtmp, rs1, rc or rd, rd, rtmp .4+.^|3 insns + (requires 1 temporary)", + "source_file": "src/unpriv/zicond.adoc", + "section": "Preamble > \"Zicond\" Extension for Integer Conditional Operations, Version 1.0.0 > Instructions (in alphabetical order) > Usage examples > Instruction sequences", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 160, + 166 + ] + }, + { + "chunk_id": "chunk_ea489e42", + "text": "|*Conditional bitwise-and, if non-zero* + `rd = (rc != 0) ? (rs1 & rs2) : rs1` |and rd, rs1, rs2 czero.nez rtmp, rs1, rc or rd, rd, rtmp", + "source_file": "src/unpriv/zicond.adoc", + "section": "Preamble > \"Zicond\" Extension for Integer Conditional Operations, Version 1.0.0 > Instructions (in alphabetical order) > Usage examples > Instruction sequences", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 168, + 172 + ] + }, + { + "chunk_id": "chunk_967ee658", + "text": "|*Conditional select, if zero* + `rd = (rc 0) ? rs1 : rs2` |czero.nez rd, rs1, rc czero.eqz rtmp, rs2, rc add rd, rd, rtmp", + "source_file": "src/unpriv/zicond.adoc", + "section": "Preamble > \"Zicond\" Extension for Integer Conditional Operations, Version 1.0.0 > Instructions (in alphabetical order) > Usage examples > Instruction sequences", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 174, + 178 + ] + }, + { + "chunk_id": "chunk_b4b0da7d", + "text": "|*Conditional select, if non-zero* + `rd = (rc != 0) ? rs1 : rs2` |czero.eqz rd, rs1, rc czero.nez rtmp, rs2, rc add rd, rd, rtmp", + "source_file": "src/unpriv/zicond.adoc", + "section": "Preamble > \"Zicond\" Extension for Integer Conditional Operations, Version 1.0.0 > Instructions (in alphabetical order) > Usage examples > Instruction sequences", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 180, + 184 + ] + } + ] + }, + { + "file": "src/unpriv/zicsr.adoc", + "chunks": [ + { + "chunk_id": "chunk_e287c5a3", + "text": "RISC-V defines a separate address space of 4096 Control and Status registers associated with each hart.", + "source_file": "src/unpriv/zicsr.adoc", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 3, + 5 + ] + }, + { + "chunk_id": "chunk_1c9fc825", + "text": "This chapter defines the full set of CSR instructions that operate on these CSRs.", + "source_file": "src/unpriv/zicsr.adoc", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 3, + 5 + ] + }, + { + "chunk_id": "chunk_431e8b3d", + "text": "All CSR instructions atomically read-modify-write a single CSR, whose CSR specifier is encoded in the 12-bit csr field of the instruction held in bits 31-20.", + "source_file": "src/unpriv/zicsr.adoc", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 9, + 12 + ] + }, + { + "chunk_id": "chunk_8ecdb3f5", + "text": "The immediate forms use a 5-bit zero-extended immediate encoded in the rs1 field.", + "source_file": "src/unpriv/zicsr.adoc", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 9, + 12 + ] + }, + { + "chunk_id": "chunk_3910d2e2", + "text": "The CSRRW (Atomic Read/Write CSR) instruction atomically swaps values in the CSRs and integer registers. CSRRW reads the old value of the CSR, zero-extends the value to XLEN bits, then writes it to integer register rd.", + "source_file": "src/unpriv/zicsr.adoc", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 16, + 22 + ] + }, + { + "chunk_id": "chunk_4b27f85d", + "text": "The initial value in rs1 is written to the CSR.", + "source_file": "src/unpriv/zicsr.adoc", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 16, + 22 + ] + }, + { + "chunk_id": "chunk_5e969665", + "text": "If rd=`x0`, then the instruction shall not read the CSR and shall not cause any of the side effects that might occur on a CSR read.", + "source_file": "src/unpriv/zicsr.adoc", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 16, + 22 + ] + }, + { + "chunk_id": "chunk_ba728b9c", + "text": "The CSRRS (Atomic Read and Set Bits in CSR) instruction reads the value of the CSR, zero-extends the value to XLEN bits, and writes it to integer register rd.", + "source_file": "src/unpriv/zicsr.adoc", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 24, + 30 + ] + }, + { + "chunk_id": "chunk_fa62ab4c", + "text": "The initial value in integer register rs1 is treated as a bit mask that specifies bit positions to be set in the CSR.", + "source_file": "src/unpriv/zicsr.adoc", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 24, + 30 + ] + }, + { + "chunk_id": "chunk_c1b61849", + "text": "Any bit that is high in rs1 will cause the corresponding bit to be set in the CSR, if that CSR bit is writable.", + "source_file": "src/unpriv/zicsr.adoc", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 24, + 30 + ] + }, + { + "chunk_id": "chunk_03fe1b1e", + "text": "The CSRRC (Atomic Read and Clear Bits in CSR) instruction reads the value of the CSR, zero-extends the value to XLEN bits, and writes it to integer register rd.", + "source_file": "src/unpriv/zicsr.adoc", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 32, + 38 + ] + }, + { + "chunk_id": "chunk_b3c0c19b", + "text": "The initial value in integer register rs1 is treated as a bit mask that specifies bit positions to be cleared in the CSR.", + "source_file": "src/unpriv/zicsr.adoc", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 32, + 38 + ] + }, + { + "chunk_id": "chunk_bd9a4a8f", + "text": "Any bit that is high in rs1 will cause the corresponding bit to be cleared in the CSR, if that CSR bit is writable.", + "source_file": "src/unpriv/zicsr.adoc", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 32, + 38 + ] + }, + { + "chunk_id": "chunk_96304ce4", + "text": "For both CSRRS and CSRRC, if rs1=`x0`, then the instruction will not write to the CSR at all, and so shall not cause any of the side effects that might otherwise occur on a CSR write, nor raise illegal-instruction exceptions on accesses to read-only CSRs.", + "source_file": "src/unpriv/zicsr.adoc", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 40, + 50 + ] + }, + { + "chunk_id": "chunk_d10c0607", + "text": "Both CSRRS and CSRRC always read the addressed CSR and cause any read side effects regardless of rs1 and rd fields.", + "source_file": "src/unpriv/zicsr.adoc", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 40, + 50 + ] + }, + { + "chunk_id": "chunk_7fb7d76c", + "text": "A CSRRW with rs1=`x0` will attempt to write zero to the destination CSR.", + "source_file": "src/unpriv/zicsr.adoc", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 52, + 53 + ] + }, + { + "chunk_id": "chunk_9db88041", + "text": "The CSRRWI, CSRRSI, and CSRRCI variants are similar to CSRRW, CSRRS, and CSRRC respectively, except they update the CSR using an XLEN-bit value obtained by zero-extending a 5-bit unsigned immediate (uimm[4:0]) field encoded in the rs1 field instead of a value from an integer register.", + "source_file": "src/unpriv/zicsr.adoc", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 55, + 67 + ] + }, + { + "chunk_id": "chunk_a1a3ca17", + "text": "For CSRRSI and CSRRCI, if the uimm[4:0] field is zero, then these instructions will not write to the CSR, and shall not cause any of the side effects that might otherwise occur on a CSR write, nor raise illegal-instruction exceptions on accesses to read-only CSRs.", + "source_file": "src/unpriv/zicsr.adoc", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 55, + 67 + ] + }, + { + "chunk_id": "chunk_135e68b2", + "text": "For CSRRWI, if rd=`x0`, then the instruction shall not read the CSR and shall not cause any of the side effects that might occur on a CSR read.", + "source_file": "src/unpriv/zicsr.adoc", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 55, + 67 + ] + }, + { + "chunk_id": "chunk_f3ce8ea7", + "text": "Both CSRRSI and CSRRCI will always read the CSR and cause any read side effects regardless of rd and rs1 fields.", + "source_file": "src/unpriv/zicsr.adoc", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 55, + 67 + ] + }, + { + "chunk_id": "chunk_d06ade09", + "text": "|Instruction |rd is `x0` |uimm=0 |Reads CSR |Writes CSR", + "source_file": "src/unpriv/zicsr.adoc", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 86, + 87 + ] + }, + { + "chunk_id": "chunk_fc511527", + "text": "summarizes the behavior of the CSR instructions with respect to whether they read and/or write the CSR.", + "source_file": "src/unpriv/zicsr.adoc", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 98, + 100 + ] + }, + { + "chunk_id": "chunk_f195af57", + "text": "In addition to side effects that occur as a consequence of reading or writing a CSR, individual fields within a CSR might have side effects when written.", + "source_file": "src/unpriv/zicsr.adoc", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 102, + 120 + ] + }, + { + "chunk_id": "chunk_64046f4d", + "text": "The CSRRW[I] instructions action side effects for all such fields within the written CSR.", + "source_file": "src/unpriv/zicsr.adoc", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 102, + 120 + ] + }, + { + "chunk_id": "chunk_4de2104c", + "text": "The CSRRS[I] and CSRRC[I] instructions only action side effects for fields for which the rs1 or uimm argument has at least one bit set corresponding to that field.", + "source_file": "src/unpriv/zicsr.adoc", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 102, + 120 + ] + }, + { + "chunk_id": "chunk_eaef22cc", + "text": "For any event or consequence that occurs due to a CSR having a particular value, if a write to the CSR gives it that value, the resulting event or consequence is said to be an indirect effect of the write.", + "source_file": "src/unpriv/zicsr.adoc", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 102, + 120 + ] + }, + { + "chunk_id": "chunk_98b81793", + "text": "Indirect effects of a CSR write are not considered by the RISC-V ISA to be side effects of that write.", + "source_file": "src/unpriv/zicsr.adoc", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 102, + 120 + ] + }, + { + "chunk_id": "chunk_27c169ed", + "text": "Some CSRs, such as the instructions-retired counter, `instret`, may be modified as side effects of instruction execution.", + "source_file": "src/unpriv/zicsr.adoc", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 102, + 120 + ] + }, + { + "chunk_id": "chunk_f75a76ad", + "text": "In these cases, if a CSR access instruction reads a CSR, it reads the value prior to the execution of the instruction.", + "source_file": "src/unpriv/zicsr.adoc", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 102, + 120 + ] + }, + { + "chunk_id": "chunk_9c3e461a", + "text": "If a CSR access instruction writes such a CSR, the explicit write is done instead of the update from the side effect.", + "source_file": "src/unpriv/zicsr.adoc", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 102, + 120 + ] + }, + { + "chunk_id": "chunk_11629f63", + "text": "In particular, a value written to `instret` by one instruction will be the value read by the following instruction.", + "source_file": "src/unpriv/zicsr.adoc", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 102, + 120 + ] + }, + { + "chunk_id": "chunk_d4bd6e00", + "text": "The assembler pseudoinstruction to read a CSR, CSRR rd, csr, is encoded as CSRRS rd, csr, x0.", + "source_file": "src/unpriv/zicsr.adoc", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 122, + 125 + ] + }, + { + "chunk_id": "chunk_8185f9c5", + "text": "The assembler pseudoinstruction to write a CSR, CSRW csr, rs1, is encoded as CSRRW x0, csr, rs1, while CSRWI csr, uimm, is encoded as CSRRWI x0, csr, uimm.", + "source_file": "src/unpriv/zicsr.adoc", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 122, + 125 + ] + }, + { + "chunk_id": "chunk_cb7068f8", + "text": "Further assembler pseudoinstructions are defined to set and clear bits in the CSR when the old value is not required: CSRS/CSRC csr, rs1; CSRSI/CSRCI csr, uimm.", + "source_file": "src/unpriv/zicsr.adoc", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 127, + 129 + ] + }, + { + "chunk_id": "chunk_ae0b8d38", + "text": "Each RISC-V hart normally observes its own CSR accesses, including its implicit CSR accesses, as performed in program order.", + "source_file": "src/unpriv/zicsr.adoc", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions > CSR Access Ordering", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 133, + 142 + ] + }, + { + "chunk_id": "chunk_dd4964c0", + "text": "Furthermore, an explicit CSR read returns the CSR state before the execution of the instruction, while an explicit CSR write suppresses and overrides any implicit writes or modifications to the same CSR by the same instruction.", + "source_file": "src/unpriv/zicsr.adoc", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions > CSR Access Ordering", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 133, + 142 + ] + }, + { + "chunk_id": "chunk_26c36073", + "text": "Likewise, any side effects from an explicit CSR access are normally observed to occur synchronously in program order.", + "source_file": "src/unpriv/zicsr.adoc", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions > CSR Access Ordering", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 144, + 149 + ] + }, + { + "chunk_id": "chunk_4272daf5", + "text": "Unless specified otherwise, the full consequences of any such side effects are observable by the very next instruction, and no consequences may be observed out-of-order by preceding instructions. (Note the distinction made earlier between side effects and indirect effects of CSR writes.)", + "source_file": "src/unpriv/zicsr.adoc", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions > CSR Access Ordering", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 144, + 149 + ] + }, + { + "chunk_id": "chunk_21bad2c7", + "text": "For the RVWMO memory consistency model (), CSR accesses are weakly ordered by default, so other harts or devices may observe CSR accesses in an order different from program order.", + "source_file": "src/unpriv/zicsr.adoc", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions > CSR Access Ordering", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 151, + 168 + ] + }, + { + "chunk_id": "chunk_f1e14775", + "text": "In addition, CSR accesses are not ordered with respect to explicit memory accesses, unless a CSR access modifies the execution behavior of the instruction that performs the explicit memory access or unless a CSR access and an explicit memory access are ordered by either the syntactic dependencies defined by the memory model or the ordering requirements defined in .", + "source_file": "src/unpriv/zicsr.adoc", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions > CSR Access Ordering", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 151, + 168 + ] + }, + { + "chunk_id": "chunk_85b3dc5c", + "text": "To enforce ordering in all other cases, software should execute a FENCE instruction between the relevant accesses.", + "source_file": "src/unpriv/zicsr.adoc", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions > CSR Access Ordering", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 151, + 168 + ] + }, + { + "chunk_id": "chunk_ebd4feaa", + "text": "For the purposes of the FENCE instruction, CSR read accesses are classified as device input (I), and CSR write accesses are classified as device output (O).", + "source_file": "src/unpriv/zicsr.adoc", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions > CSR Access Ordering", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 151, + 168 + ] + }, + { + "chunk_id": "chunk_6769351e", + "text": "The hardware platform may define that accesses to certain CSRs are strongly ordered, Accesses to strongly ordered CSRs have stronger ordering constraints with respect to accesses to both weakly ordered CSRs and accesses to memory-mapped I/O regions.", + "source_file": "src/unpriv/zicsr.adoc", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions > CSR Access Ordering", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 151, + 168 + ] + } + ] + }, + { + "file": "src/unpriv/zifencei.adoc", + "chunks": [ + { + "chunk_id": "chunk_e8f13d4d", + "text": "The unused fields in the FENCE.I instruction, funct12, rs1, and rd, are reserved for finer-grain fences in future extensions.", + "source_file": "src/unpriv/zifencei.adoc", + "section": "Preamble > \"Zifencei\" Extension for Instruction-Fetch Fence, Version 2.0", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 37, + 43 + ] + }, + { + "chunk_id": "chunk_c4d46b13", + "text": "For forward compatibility, base implementations shall ignore these fields, and standard software shall zero these fields.", + "source_file": "src/unpriv/zifencei.adoc", + "section": "Preamble > \"Zifencei\" Extension for Instruction-Fetch Fence, Version 2.0", + "confidence": "very_high", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 37, + 43 + ] + } + ] + }, + { + "file": "src/unpriv/zihintntl.adoc", + "chunks": [ + { + "chunk_id": "chunk_dba267ff", + "text": "The NTL.P1 instruction indicates that the target instruction does not exhibit temporal locality within the capacity of the innermost level of private cache in the memory hierarchy. NTL.P1 is encoded as ADD x0, x0, x2.", + "source_file": "src/unpriv/zihintntl.adoc", + "section": "Preamble > \"Zihintntl\" Extension for Non-Temporal Locality Hints, Version 1.0", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 10, + 13 + ] + }, + { + "chunk_id": "chunk_bac7f0dd", + "text": "The NTL.PALL instruction indicates that the target instruction does not exhibit temporal locality within the capacity of any level of private cache in the memory hierarchy. NTL.PALL is encoded as ADD x0, x0, x3.", + "source_file": "src/unpriv/zihintntl.adoc", + "section": "Preamble > \"Zihintntl\" Extension for Non-Temporal Locality Hints, Version 1.0", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 15, + 17 + ] + }, + { + "chunk_id": "chunk_841c2ff4", + "text": "The NTL.S1 instruction indicates that the target instruction does not exhibit temporal locality within the capacity of the innermost level of shared cache in the memory hierarchy. NTL.S1 is encoded as ADD x0, x0, x4.", + "source_file": "src/unpriv/zihintntl.adoc", + "section": "Preamble > \"Zihintntl\" Extension for Non-Temporal Locality Hints, Version 1.0", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 19, + 22 + ] + }, + { + "chunk_id": "chunk_14e12045", + "text": "The NTL.ALL instruction indicates that the target instruction does not exhibit temporal locality within the capacity of any level of cache in the memory hierarchy. NTL.ALL is encoded as ADD x0, x0, x5.", + "source_file": "src/unpriv/zihintntl.adoc", + "section": "Preamble > \"Zihintntl\" Extension for Non-Temporal Locality Hints, Version 1.0", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 24, + 26 + ] + }, + { + "chunk_id": "chunk_47069481", + "text": "The table also recommends which NTL variant that implementation-tuned software should use to avoid allocating in a particular cache level.", + "source_file": "src/unpriv/zihintntl.adoc", + "section": "Preamble > \"Zihintntl\" Extension for Non-Temporal Locality Hints, Version 1.0", + "confidence": "medium", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 42, + 52 + ] + }, + { + "chunk_id": "chunk_51184e82", + "text": "Furthermore, software tuned for such a system should use NTL.P1 to indicate a lack of temporal locality exploitable by the L1, or should use NTL.ALL indicate a lack of temporal locality exploitable by the L2.", + "source_file": "src/unpriv/zihintntl.adoc", + "section": "Preamble > \"Zihintntl\" Extension for Non-Temporal Locality Hints, Version 1.0", + "confidence": "medium", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 42, + 52 + ] + }, + { + "chunk_id": "chunk_ad9a22b3", + "text": "If the C or Zca extension is provided, compressed variants of these HINTs are also provided: C.NTL.P1 is encoded as C.ADD x0, x2; C.NTL.PALL is encoded as C.ADD x0, x3; C.NTL.S1 is encoded as C.ADD x0, x4; and C.NTL.ALL is encoded as C.ADD x0, x5.", + "source_file": "src/unpriv/zihintntl.adoc", + "section": "Preamble > \"Zihintntl\" Extension for Non-Temporal Locality Hints, Version 1.0", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 54, + 57 + ] + }, + { + "chunk_id": "chunk_8e3b2dc2", + "text": "When an NTL instruction is applied to a prefetch hint in the Zicbop extension, it indicates that a cache line should be prefetched into a cache that is outer from the level specified by the NTL.", + "source_file": "src/unpriv/zihintntl.adoc", + "section": "Preamble > \"Zihintntl\" Extension for Non-Temporal Locality Hints, Version 1.0", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 89, + 91 + ] + }, + { + "chunk_id": "chunk_6cc183d2", + "text": "In the event that a trap is taken on the target instruction, implementations are discouraged from applying the NTL to the first instruction in the trap handler.", + "source_file": "src/unpriv/zihintntl.adoc", + "section": "Preamble > \"Zihintntl\" Extension for Non-Temporal Locality Hints, Version 1.0", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 98, + 101 + ] + } + ] + }, + { + "file": "src/unpriv/zihintpause.adoc", + "chunks": [ + { + "chunk_id": "chunk_a96dd875", + "text": "The PAUSE instruction is a HINT that indicates the current hart's rate of instruction retirement should be temporarily reduced or paused.", + "source_file": "src/unpriv/zihintpause.adoc", + "section": "Preamble > \"Zihintpause\" Extension for Pause Hint, Version 2.0", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 3, + 7 + ] + }, + { + "chunk_id": "chunk_0de4ca53", + "text": "The duration of its effect must be bounded and may be zero.", + "source_file": "src/unpriv/zihintpause.adoc", + "section": "Preamble > \"Zihintpause\" Extension for Pause Hint, Version 2.0", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 3, + 7 + ] + }, + { + "chunk_id": "chunk_6a6a0b8c", + "text": "PAUSE is encoded as a FENCE instruction with pred=`W`, succ=`0`, fm=`0`, rd=`x0`, and rs1=`x0`.", + "source_file": "src/unpriv/zihintpause.adoc", + "section": "Preamble > \"Zihintpause\" Extension for Pause Hint, Version 2.0", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 9, + 10 + ] + } + ] + }, + { + "file": "src/unpriv/zihpm.adoc", + "chunks": [ + { + "chunk_id": "chunk_6abf98ab", + "text": "The Zihpm extension comprises up to 29 additional unprivileged 64-bit hardware performance counters, `hpmcounter3-hpmcounter31`.", + "source_file": "src/unpriv/zihpm.adoc", + "section": "Preamble > \"Zihpm\" Extension for Hardware Performance Counters", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 3, + 13 + ] + }, + { + "chunk_id": "chunk_a67989e0", + "text": "When XLEN=32, the upper 32 bits of these performance counters are accessible via additional CSRs `hpmcounter3h- hpmcounter31h`.", + "source_file": "src/unpriv/zihpm.adoc", + "section": "Preamble > \"Zihpm\" Extension for Hardware Performance Counters", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 3, + 13 + ] + }, + { + "chunk_id": "chunk_df54db05", + "text": "The Zihpm extension depends on the Zicsr extension.", + "source_file": "src/unpriv/zihpm.adoc", + "section": "Preamble > \"Zihpm\" Extension for Hardware Performance Counters", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 3, + 13 + ] + }, + { + "chunk_id": "chunk_dc32f4bd", + "text": "Accessing an unimplemented counter may cause an illegal-instruction exception or may return a constant value.", + "source_file": "src/unpriv/zihpm.adoc", + "section": "Preamble > \"Zihpm\" Extension for Hardware Performance Counters", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 3, + 13 + ] + }, + { + "chunk_id": "chunk_67e109b9", + "text": "If the configuration used to select the events counted by a counter is misconfigured, the counter may return a constant value.", + "source_file": "src/unpriv/zihpm.adoc", + "section": "Preamble > \"Zihpm\" Extension for Hardware Performance Counters", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 3, + 13 + ] + }, + { + "chunk_id": "chunk_7e664c43", + "text": "The execution environment should provide a means to determine the number and width of the implemented counters, and an interface to configure the events to be counted by each counter.", + "source_file": "src/unpriv/zihpm.adoc", + "section": "Preamble > \"Zihpm\" Extension for Hardware Performance Counters", + "confidence": "medium", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 15, + 17 + ] + } + ] + }, + { + "file": "src/unpriv/zilsd.adoc", + "chunks": [ + { + "chunk_id": "chunk_c54d4c93", + "text": "Operands containing `src` for store instructions and `dest` for load instructions are held in aligned `x`-register pairs, i.e., register numbers must be even.", + "source_file": "src/unpriv/zilsd.adoc", + "section": "Preamble > ext:zilsd[] Extension for Load/Store Pair Instructions", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 5, + 5 + ] + }, + { + "chunk_id": "chunk_4f66a74a", + "text": "As the access size is 64-bit, accesses are only considered naturally aligned for effective addresses that are a multiple of 8.", + "source_file": "src/unpriv/zilsd.adoc", + "section": "Preamble > ext:zilsd[] Extension for Load/Store Pair Instructions", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 32, + 34 + ] + }, + { + "chunk_id": "chunk_5c555bb3", + "text": "In this case, these instructions are guaranteed to not raise an address-misaligned exception.", + "source_file": "src/unpriv/zilsd.adoc", + "section": "Preamble > ext:zilsd[] Extension for Load/Store Pair Instructions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 32, + 34 + ] + }, + { + "chunk_id": "chunk_a0448686", + "text": "Even if naturally aligned, the memory access might not be performed atomically.", + "source_file": "src/unpriv/zilsd.adoc", + "section": "Preamble > ext:zilsd[] Extension for Load/Store Pair Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 32, + 34 + ] + }, + { + "chunk_id": "chunk_16355b0a", + "text": "If the effective address is a multiple of 4, then each word access is required to be performed atomically.", + "source_file": "src/unpriv/zilsd.adoc", + "section": "Preamble > ext:zilsd[] Extension for Load/Store Pair Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 36, + 36 + ] + }, + { + "chunk_id": "chunk_a5483d4e", + "text": "| |Alignment |Word accesses guaranteed atomic? |Can cause misaligned trap? |8{nbsp}B |yes |no |4{nbsp}B not 8{nbsp}B |yes |yes |else |no | yes |", + "source_file": "src/unpriv/zilsd.adoc", + "section": "Preamble > ext:zilsd[] Extension for Load/Store Pair Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 40, + 46 + ] + }, + { + "chunk_id": "chunk_eaecca12", + "text": "To ensure resumable trap handling is possible for the load instructions, the base register must have its original value if a trap is taken.", + "source_file": "src/unpriv/zilsd.adoc", + "section": "Preamble > ext:zilsd[] Extension for Load/Store Pair Instructions", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 48, + 50 + ] + }, + { + "chunk_id": "chunk_bc6a0930", + "text": "For the purposes of RVWMO and exception handling, LD and SD instructions are considered to be misaligned loads and stores, with one additional constraint: an LD or SD instruction whose effective address is a multiple of 4 gives rise to two 4-byte memory operations.", + "source_file": "src/unpriv/zilsd.adoc", + "section": "Preamble > ext:zilsd[] Extension for Load/Store Pair Instructions > Use of x0 as operand > Exception Handling", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 62, + 65 + ] + }, + { + "chunk_id": "chunk_6ec83172", + "text": "If instructions with 4-byte-aligned effective address are decomposed into two 32b operations, there is no constraint on the order in which the operations are performed and each operation is guaranteed to be atomic.", + "source_file": "src/unpriv/zilsd.adoc", + "section": "Preamble > ext:zilsd[] Extension for Load/Store Pair Instructions > Use of x0 as operand > Exception Handling", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 67, + 74 + ] + }, + { + "chunk_id": "chunk_9323d676", + "text": "These decomposed sequences are interruptible.", + "source_file": "src/unpriv/zilsd.adoc", + "section": "Preamble > ext:zilsd[] Extension for Load/Store Pair Instructions > Use of x0 as operand > Exception Handling", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 67, + 74 + ] + }, + { + "chunk_id": "chunk_5f6a3ba5", + "text": "Exceptions might occur on subsequent operations, making the effects of previous operations within the same instruction visible.", + "source_file": "src/unpriv/zilsd.adoc", + "section": "Preamble > ext:zilsd[] Extension for Load/Store Pair Instructions > Use of x0 as operand > Exception Handling", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 67, + 74 + ] + }, + { + "chunk_id": "chunk_2f70ffe3", + "text": "[insns-ld,reftext=\"Load doubleword to register pair, 32-bit encoding\"]", + "source_file": "src/unpriv/zilsd.adoc", + "section": "Preamble > ext:zilsd[] Extension for Load/Store Pair Instructions > Use of x0 as operand > Instructions", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 86, + 86 + ] + }, + { + "chunk_id": "chunk_e399cd38", + "text": "The effective address is obtained by adding register rs1 to the sign-extended 12-bit offset.", + "source_file": "src/unpriv/zilsd.adoc", + "section": "Preamble > ext:zilsd[] Extension for Load/Store Pair Instructions > Use of x0 as operand > Instructions > ld", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 106, + 110 + ] + }, + { + "chunk_id": "chunk_c6ec822a", + "text": "[insns-sd,reftext=\"Store doubleword from register pair, 32-bit encoding\"]", + "source_file": "src/unpriv/zilsd.adoc", + "section": "Preamble > ext:zilsd[] Extension for Load/Store Pair Instructions > Use of x0 as operand > Instructions > ld", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 116, + 116 + ] + }, + { + "chunk_id": "chunk_00d22761", + "text": "The effective address is obtained by adding register rs1 to the sign-extended 12-bit offset.", + "source_file": "src/unpriv/zilsd.adoc", + "section": "Preamble > ext:zilsd[] Extension for Load/Store Pair Instructions > Use of x0 as operand > Instructions > sd", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 138, + 142 + ] + } + ] + }, + { + "file": "src/unpriv/zimop.adoc", + "chunks": [ + { + "chunk_id": "chunk_22eb57ca", + "text": "Unless redefined by another extension, these instructions simply write 0 to `x[rd]`.", + "source_file": "src/unpriv/zimop.adoc", + "section": "Preamble > ext:zimop[] Extension for May-Be-Operations", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 9, + 13 + ] + }, + { + "chunk_id": "chunk_53a21fab", + "text": "Unless redefined by another extension, these instructions simply write 0 to `x[rd]`.", + "source_file": "src/unpriv/zimop.adoc", + "section": "Preamble > ext:zimop[] Extension for May-Be-Operations", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 19, + 23 + ] + }, + { + "chunk_id": "chunk_36ad14da", + "text": "The extension that redefines a MOP may define an alternate assembly mnemonic.", + "source_file": "src/unpriv/zimop.adoc", + "section": "Preamble > ext:zimop[] Extension for May-Be-Operations", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 29, + 32 + ] + }, + { + "chunk_id": "chunk_a2981048", + "text": "The MOPs defined in the ext:zimop[] extension do not carry a syntactic dependency from `x[rs1]` or `x[rs2]` to `x[rd]`, though an extension that redefines the MOP may impose such a requirement.", + "source_file": "src/unpriv/zimop.adoc", + "section": "Preamble > ext:zimop[] Extension for May-Be-Operations", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 41, + 43 + ] + } + ] + }, + { + "file": "src/unpriv/ztso.adoc", + "chunks": [ + { + "chunk_id": "chunk_c49a56c7", + "text": "All load operations behave as if they have an acquire-RCpc annotation * All store operations behave as if they have a release-RCpc annotation. * All AMOs behave as if they have both acquire-RCsc and release-RCsc annotations.", + "source_file": "src/unpriv/ztso.adoc", + "section": "Preamble > \"Ztso\" Extension for Total Store Ordering, Version 1.0", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 9, + 12 + ] + }, + { + "chunk_id": "chunk_56ece718", + "text": "Additionally, if the Ztso extension is implemented, then vector memory instructions in the V extension and Zve family of extensions follow RVTSO at the instruction level.", + "source_file": "src/unpriv/ztso.adoc", + "section": "Preamble > \"Ztso\" Extension for Total Store Ordering, Version 1.0", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 14, + 18 + ] + }, + { + "chunk_id": "chunk_55f6fbc1", + "text": "Binaries compiled to run only under Ztso should indicate as such via a flag in the binary, so that platforms which do not implement Ztso can simply refuse to run them.", + "source_file": "src/unpriv/ztso.adoc", + "section": "Preamble > \"Ztso\" Extension for Total Store Ordering, Version 1.0", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 20, + 24 + ] + } + ] + }, + { + "file": "src/unpriv/zvfbfmin.adoc", + "chunks": [ + { + "chunk_id": "chunk_a779dcd6", + "text": "Round according to the frm register.", + "source_file": "src/unpriv/zvfbfmin.adoc", + "section": "Preamble > `Zvfbfmin` Extension for Vector BF16 Conversions > vfncvtbf16.f.f.w", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 49, + 51 + ] + } + ] + }, + { + "file": "src/unpriv/zvfbfwma.adoc", + "chunks": [ + { + "chunk_id": "chunk_d8280420", + "text": "The sum is rounded according to the frm register.", + "source_file": "src/unpriv/zvfbfwma.adoc", + "section": "Preamble > `Zvfbfwma` Extension for Vector BF16 Widening Multiply-Accumulation > vfwmaccbf16", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 66, + 70 + ] + } + ] + }, + { + "file": "src/v-st-ext.adoc", + "chunks": [ + { + "chunk_id": "chunk_56023d0e", + "text": "The maximum size in bits of a vector element that any operation can produce or consume, ELEN {ge} 8, which must be a power of 2. .", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Implementation-defined Constant Parameters", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 13, + 15 + ] + }, + { + "chunk_id": "chunk_66980178", + "text": "The number of bits in a single vector register, VLEN {ge} ELEN, which must be a power of 2, and must be no greater than 2^16^.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Implementation-defined Constant Parameters", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 13, + 15 + ] + }, + { + "chunk_id": "chunk_78fba37e", + "text": "Standard vector extensions () and architecture profiles may set further constraints on ELEN and VLEN.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Implementation-defined Constant Parameters", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 17, + 18 + ] + }, + { + "chunk_id": "chunk_32671622", + "text": "The vector extension supports writing binary code that under certain constraints will execute portably on harts with different values for the VLEN parameter, provided the harts support the required element types and instructions.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Implementation-defined Constant Parameters", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 31, + 34 + ] + }, + { + "chunk_id": "chunk_b2098700", + "text": "The vector extension adds 32 vector registers, and seven unprivileged CSRs (`vstart`, `vxsat`, `vxrm`, `vcsr`, `vtype`, `vl`, `vlenb`) to a base scalar RISC-V ISA.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 45, + 47 + ] + }, + { + "chunk_id": "chunk_c8ebffe9", + "text": "| 0x008 | URW | vstart | Vector start element index | 0x009 | URW | vxsat | Fixed-Point Saturate Flag | 0x00A | URW | vxrm | Fixed-Point Rounding Mode | 0x00F | URW | vcsr | Vector control and status register | 0xC20 | URO | vl | Vector length | 0xC21 | URO | vtype | Vector data type register | 0xC22 | URO | vlenb | VLEN/8 (vector register length in bytes) |", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 55, + 62 + ] + }, + { + "chunk_id": "chunk_3855def4", + "text": "The vector extension adds 32 architectural vector registers, `v0`-`v31` to the base scalar RISC-V ISA.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Registers", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 69, + 71 + ] + }, + { + "chunk_id": "chunk_9cf236cc", + "text": "Each vector register has a fixed VLEN bits of state.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Registers", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 73, + 73 + ] + }, + { + "chunk_id": "chunk_7d1c368f", + "text": "A vector context status field, `VS`, is added to `mstatus[10:9]` and shadowed in `sstatus[10:9]`.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Context Status in `mstatus`", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 77, + 80 + ] + }, + { + "chunk_id": "chunk_fc6d2e32", + "text": "It is defined analogously to the floating-point context status field, `FS`.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Context Status in `mstatus`", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 77, + 80 + ] + }, + { + "chunk_id": "chunk_c0c0139f", + "text": "Attempts to execute any vector instruction, or to access the vector CSRs, raise an illegal-instruction exception when `mstatus.VS` is set to Off.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Context Status in `mstatus`", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 82, + 85 + ] + }, + { + "chunk_id": "chunk_fccdaa45", + "text": "When `mstatus.VS` is set to Initial or Clean, executing any instruction that changes vector state, including the vector CSRs, will change `mstatus.VS` to Dirty.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Context Status in `mstatus`", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 87, + 92 + ] + }, + { + "chunk_id": "chunk_19a758db", + "text": "Implementations may also change `mstatus.VS` from Initial or Clean to Dirty at any time, even when there is no change in vector state.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Context Status in `mstatus`", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 87, + 92 + ] + }, + { + "chunk_id": "chunk_c68436d4", + "text": "If `mstatus.VS` is Dirty, `mstatus.SD` is 1; otherwise, `mstatus.SD` is set in accordance with existing specifications.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Context Status in `mstatus`", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 97, + 99 + ] + }, + { + "chunk_id": "chunk_b544d7cd", + "text": "Implementations may have a writable `misa.V` field.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Context Status in `mstatus`", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 101, + 103 + ] + }, + { + "chunk_id": "chunk_9a0af34c", + "text": "Analogous to the way in which the floating-point unit is handled, the `mstatus.VS` field may exist even if `misa.V` is clear.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Context Status in `mstatus`", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 101, + 103 + ] + }, + { + "chunk_id": "chunk_016445ef", + "text": "When the hypervisor extension is present, a vector context status field, `VS`, is added to `vsstatus[10:9]`.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Context Status in `vsstatus`", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 111, + 114 + ] + }, + { + "chunk_id": "chunk_4f9b96af", + "text": "It is defined analogously to the floating-point context status field, `FS`.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Context Status in `vsstatus`", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 111, + 114 + ] + }, + { + "chunk_id": "chunk_c7a05af6", + "text": "When V=1, both `vsstatus.VS` and `mstatus.VS` are in effect: attempts to execute any vector instruction, or to access the vector CSRs, raise an illegal-instruction exception when either field is set to Off.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Context Status in `vsstatus`", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 116, + 119 + ] + }, + { + "chunk_id": "chunk_4f912182", + "text": "When V=1 and neither `vsstatus.VS` nor `mstatus.VS` is set to Off, executing any instruction that changes vector state, including the vector CSRs, will change both `mstatus.VS` and `vsstatus.VS` to Dirty.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Context Status in `vsstatus`", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 121, + 125 + ] + }, + { + "chunk_id": "chunk_1e6d5f75", + "text": "Implementations may also change `mstatus.VS` or `vsstatus.VS` from Initial or Clean to Dirty at any time, even when there is no change in vector state.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Context Status in `vsstatus`", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 121, + 125 + ] + }, + { + "chunk_id": "chunk_19745b2d", + "text": "If `vsstatus.VS` is Dirty, `vsstatus.SD` is 1; otherwise, `vsstatus.SD` is set in accordance with existing specifications.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Context Status in `vsstatus`", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 127, + 129 + ] + }, + { + "chunk_id": "chunk_5dcf34fc", + "text": "If `mstatus.VS` is Dirty, `mstatus.SD` is 1; otherwise, `mstatus.SD` is set in accordance with existing specifications.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Context Status in `vsstatus`", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 131, + 133 + ] + }, + { + "chunk_id": "chunk_5e7facac", + "text": "For implementations with a writable `misa.V` field, the `vsstatus.VS` field may exist even if `misa.V` is clear.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Context Status in `vsstatus`", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 135, + 137 + ] + }, + { + "chunk_id": "chunk_f5c34059", + "text": "The read-only XLEN-wide vector type CSR, `vtype` provides the default type used to interpret the contents of the vector register file, and can only be updated by `vset{i}vl{i}` instructions.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 141, + 147 + ] + }, + { + "chunk_id": "chunk_13a1efbf", + "text": "The vector type determines the organization of elements in each vector register, and how multiple vector registers are grouped.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 141, + 147 + ] + }, + { + "chunk_id": "chunk_b75676f5", + "text": "The `vtype` register also indicates how masked-off elements and elements past the current vector length in a vector result are handled.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 141, + 147 + ] + }, + { + "chunk_id": "chunk_14951828", + "text": "The `vtype` register has five fields, `vill`, `vma`, `vta`, `vsew[2:0]`, and `vlmul[2:0]`.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 152, + 155 + ] + }, + { + "chunk_id": "chunk_2bb9a0dd", + "text": "Bits `vtype[XLEN-2:8]` should be written with zero, and non-zero values in this field are reserved.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 152, + 155 + ] + }, + { + "chunk_id": "chunk_c35b9616", + "text": "The illegal value represented by `vill` can be internally encoded using the illegal 64-bit combination in `vsew[1:0]` without requiring an additional storage bit to hold `vill`.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 159, + 160 + ] + }, + { + "chunk_id": "chunk_be0ffe7c", + "text": "In many cases, the `vl` and `vtype` values can be reused across multiple instructions, reducing the static and dynamic instruction overhead from the `vset{i}vl{i}` instructions.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 165, + 175 + ] + }, + { + "chunk_id": "chunk_f6b6c9b2", + "text": "It is anticipated that a future extended 64-bit instruction encoding would allow these fields to be specified statically in the instruction encoding.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 165, + 175 + ] + }, + { + "chunk_id": "chunk_92e7b5fb", + "text": "The value in `vsew` sets the dynamic selected element width (SEW).", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Selected Element Width (`vsew[2:0]`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 180, + 183 + ] + }, + { + "chunk_id": "chunk_ab5aa1c4", + "text": "By default, a vector register is viewed as being divided into VLEN/SEW elements.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Selected Element Width (`vsew[2:0]`)", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 180, + 183 + ] + }, + { + "chunk_id": "chunk_159d2358", + "text": "| 0 | 0 | 0 | 8 | 0 | 0 | 1 | 16 | 0 | 1 | 0 | 32 | 0 | 1 | 1 | 64 | 1 | X | X | Reserved |", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Selected Element Width (`vsew[2:0]`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 191, + 196 + ] + }, + { + "chunk_id": "chunk_9ba76760", + "text": "| 64 | 2 | 32 | 4 | 16 | 8 | 8 | 16 |", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Selected Element Width (`vsew[2:0]`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 208, + 212 + ] + }, + { + "chunk_id": "chunk_1a98b1dd", + "text": "The supported element width may vary with LMUL.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Selected Element Width (`vsew[2:0]`)", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 214, + 214 + ] + }, + { + "chunk_id": "chunk_5054779e", + "text": "Some future extensions may support larger SEWs only when bits from multiple vector registers are combined using LMUL.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Selected Element Width (`vsew[2:0]`)", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 216, + 225 + ] + }, + { + "chunk_id": "chunk_4bcb757d", + "text": "In this case, software that relies on large SEW should attempt to use the largest LMUL, and hence the fewest vector register groups, to increase the number of implementations on which the code will run.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Selected Element Width (`vsew[2:0]`)", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 216, + 225 + ] + }, + { + "chunk_id": "chunk_2525e083", + "text": "The `vill` bit in `vtype` should be checked after setting `vtype` to see if the configuration is supported, and an alternate code path should be provided if it is not.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Selected Element Width (`vsew[2:0]`)", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 216, + 225 + ] + }, + { + "chunk_id": "chunk_22b8bce5", + "text": "Alternatively, a profile can mandate the minimum SEW at each LMUL setting.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Selected Element Width (`vsew[2:0]`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "range", + "line_range": [ + 216, + 225 + ] + }, + { + "chunk_id": "chunk_0c2bdd51", + "text": "Multiple vector registers can be grouped together, so that a single vector instruction can operate on multiple vector registers.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 229, + 240 + ] + }, + { + "chunk_id": "chunk_5a59f768", + "text": "The term vector register group is used herein to refer to one or more vector registers used as a single operand to a vector instruction.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 229, + 240 + ] + }, + { + "chunk_id": "chunk_d568baa3", + "text": "The vector length multiplier, LMUL, when greater than 1, represents the default number of vector registers that are combined to form a vector register group.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "range", + "line_range": [ + 229, + 240 + ] + }, + { + "chunk_id": "chunk_8ab701ed", + "text": "Implementations must support LMUL integer values of 1, 2, 4, and 8.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 229, + 240 + ] + }, + { + "chunk_id": "chunk_6e0b521b", + "text": "The effective LMUL (EMUL) of each vector operand is determined by the number of registers required to hold the elements.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 242, + 248 + ] + }, + { + "chunk_id": "chunk_336dbdb3", + "text": "LMUL can also be a fractional value, reducing the number of bits used in a single vector register.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 250, + 253 + ] + }, + { + "chunk_id": "chunk_dccc5503", + "text": "Fractional LMUL is used to increase the number of effective usable vector register groups when operating on mixed-width values.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 250, + 253 + ] + }, + { + "chunk_id": "chunk_69d66bf2", + "text": "This can limit the number of vector register groups available.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 255, + 267 + ] + }, + { + "chunk_id": "chunk_49f4fd38", + "text": "With fractional LMUL, the widest values need occupy only a single vector register while narrower values can occupy a fraction of a single vector register, allowing all 32 architectural vector register names to be used for different values in a vector loop even when handling mixed-width values.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 255, + 267 + ] + }, + { + "chunk_id": "chunk_c2993deb", + "text": "Fractional LMUL implies portions of vector registers are unused, but in some cases, having more shorter register-resident vectors improves efficiency relative to fewer longer register-resident vectors.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 255, + 267 + ] + }, + { + "chunk_id": "chunk_f82746f4", + "text": "Implementations must provide fractional LMUL settings that allow the narrowest supported type to occupy a fraction of a vector register corresponding to the ratio of the narrowest supported type's width to that of the largest supported type's width.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 269, + 279 + ] + }, + { + "chunk_id": "chunk_85c7cba7", + "text": "In the standard extensions, SEW~MIN~=8.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 269, + 279 + ] + }, + { + "chunk_id": "chunk_13e8418d", + "text": "For standard vector extensions with ELEN=32, fractional LMULs of 1/2 and 1/4 must be supported.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 269, + 279 + ] + }, + { + "chunk_id": "chunk_52ccf9d2", + "text": "For standard vector extensions with ELEN=64, fractional LMULs of 1/2, 1/4, and 1/8 must be supported.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 269, + 279 + ] + }, + { + "chunk_id": "chunk_e7f18d7c", + "text": "When LMUL < SEW~MIN~/ELEN, there is no guarantee an implementation would have enough bits in the fractional vector register to store at least one element, as VLEN=ELEN is a valid implementation choice.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 281, + 286 + ] + }, + { + "chunk_id": "chunk_50421d62", + "text": "For a given supported fractional LMUL setting, implementations must support SEW settings between SEW~MIN~ and LMUL * ELEN, inclusive.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 288, + 290 + ] + }, + { + "chunk_id": "chunk_abf96fb1", + "text": "The use of `vtype` encodings with LMUL < SEW~MIN~/ELEN is reserved, but implementations can set `vill` if they do not support these configurations.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 292, + 295 + ] + }, + { + "chunk_id": "chunk_2c7941b0", + "text": "The derived value VLMAX = LMUL*VLEN/SEW represents the maximum number of elements that can be operated on with a single vector instruction given the current SEW and LMUL settings as shown in the table below.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 309, + 312 + ] + }, + { + "chunk_id": "chunk_2e07878e", + "text": "Instructions specifying an LMUL=2 vector register group with an odd-numbered vector register are reserved.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 329, + 332 + ] + }, + { + "chunk_id": "chunk_059a9151", + "text": "When LMUL=4, the vector register group contains four vector registers, and instructions specifying an LMUL=4 vector register group using vector register numbers that are not multiples of four are reserved.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 334, + 336 + ] + }, + { + "chunk_id": "chunk_cab34478", + "text": "When LMUL=8, the vector register group contains eight vector registers, and instructions specifying an LMUL=8 vector register group using register numbers that are not multiples of eight are reserved.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 338, + 340 + ] + }, + { + "chunk_id": "chunk_e478d910", + "text": "Mask registers are always contained in a single vector register, regardless of LMUL.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 342, + 344 + ] + }, + { + "chunk_id": "chunk_4bd30b70", + "text": "These two bits modify the behavior of destination tail elements and destination inactive masked-off elements respectively during the execution of vector instructions.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma`", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 350, + 355 + ] + }, + { + "chunk_id": "chunk_52063155", + "text": "The tail and inactive sets contain element positions that are not receiving new results during a vector operation,", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma`", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 350, + 355 + ] + }, + { + "chunk_id": "chunk_62203d67", + "text": "All systems must support all four options:", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma`", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 357, + 358 + ] + }, + { + "chunk_id": "chunk_cf2d4fda", + "text": "[cols=\"1,1,3,3\"] | | `vta` | `vma` | Tail Elements | Inactive Elements", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma`", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 360, + 363 + ] + }, + { + "chunk_id": "chunk_9d5641cd", + "text": "| 0 | 0 | undisturbed | undisturbed | 0 | 1 | undisturbed | agnostic | 1 | 0 | agnostic | undisturbed | 1 | 1 | agnostic | agnostic |", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma`", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 365, + 369 + ] + }, + { + "chunk_id": "chunk_6e40ff6c", + "text": "Mask destination tail elements are always treated as tail-agnostic, regardless of the setting of `vta`.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma`", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 371, + 373 + ] + }, + { + "chunk_id": "chunk_e647f308", + "text": "When a set is marked undisturbed, the corresponding set of destination elements in a vector register group retain the value they previously held.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma`", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 375, + 378 + ] + }, + { + "chunk_id": "chunk_c676cdc4", + "text": "When a set is marked agnostic, the corresponding set of destination elements in any vector destination operand can either retain the value they previously held, or are overwritten with 1s.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma`", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 380, + 387 + ] + }, + { + "chunk_id": "chunk_a901278d", + "text": "Within a single vector instruction, each destination element can be either left undisturbed or overwritten with 1s, in any combination, and the pattern of undisturbed or overwritten with 1s is not required to be deterministic when the instruction is executed with the same inputs.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma`", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 380, + 387 + ] + }, + { + "chunk_id": "chunk_d4bc9d75", + "text": "With an undisturbed policy, all elements would have to be read from the old physical destination vector register to be copied into the new physical destination vector register.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma`", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 389, + 394 + ] + }, + { + "chunk_id": "chunk_f7248ab1", + "text": "This causes an inefficiency when these inactive or tail values are not required for subsequent calculations.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma`", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 389, + 394 + ] + }, + { + "chunk_id": "chunk_6d0aa5ef", + "text": "The `vta` and `vma` state bits must still be provided in `vtype` for compatibility and to support thread migration.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma`", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 400, + 403 + ] + }, + { + "chunk_id": "chunk_382f7cbc", + "text": "As it might be necessary to restart in the middle, we allow arbitrary mixing of agnostic policies within a single vector instruction.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma`", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 409, + 419 + ] + }, + { + "chunk_id": "chunk_0f653bae", + "text": "In addition, except for mask load instructions, any element in the tail of a mask result can also be written with the value the mask-producing operation would have calculated with `vl`=VLMAX.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma`", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 421, + 429 + ] + }, + { + "chunk_id": "chunk_e201e0d2", + "text": "There appears to be little software need to support tail-undisturbed for mask register values.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma`", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 431, + 438 + ] + }, + { + "chunk_id": "chunk_0c7925a1", + "text": "Allowing mask-generating instructions to write back the result of the instruction avoids the need for logic to mask out the tail, except mask loads cannot write memory values to destination mask tails as this would imply accessing memory past software intent.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma`", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 431, + 438 + ] + }, + { + "chunk_id": "chunk_ab050261", + "text": "The assembly syntax adds two mandatory flags to the `vsetvli` instruction:", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma`", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 440, + 440 + ] + }, + { + "chunk_id": "chunk_fe22b9c1", + "text": "---- ta Tail agnostic tu Tail undisturbed ma Mask agnostic mu Mask undisturbed", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma`", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 442, + 446 + ] + }, + { + "chunk_id": "chunk_3294b759", + "text": "vsetvli t0, a0, e32, m4, ta, ma Tail agnostic, mask agnostic vsetvli t0, a0, e32, m4, tu, ma Tail undisturbed, mask agnostic vsetvli t0, a0, e32, m4, ta, mu Tail agnostic, mask undisturbed vsetvli t0, a0, e32, m4, tu, mu Tail undisturbed, mask undisturbed ----", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma`", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 448, + 452 + ] + }, + { + "chunk_id": "chunk_380b9eb2", + "text": "The use of `vsetvli` without these flags is deprecated, however, and specifying a flag setting is now mandatory.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma`", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 454, + 461 + ] + }, + { + "chunk_id": "chunk_ca56a477", + "text": "The default should perhaps be tail-agnostic/mask-agnostic, so software has to specify when it cares about the non-participating elements, but given the historical meaning of the instruction prior to introduction of these flags, it was decided to always require them in future assembly code.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma`", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 454, + 461 + ] + }, + { + "chunk_id": "chunk_e2f6f4fa", + "text": "The `vill` bit is used to encode that a previous `vset{i}vl{i}` instruction attempted to write an unsupported value to `vtype`.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Type Illegal (`vill`)", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 465, + 466 + ] + }, + { + "chunk_id": "chunk_3f095a40", + "text": "If the `vill` bit is set, then any attempt to execute a vector instruction that depends upon `vtype` will raise an illegal-instruction exception.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Type Illegal (`vill`)", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 471, + 473 + ] + }, + { + "chunk_id": "chunk_e8852c78", + "text": "When the `vill` bit is set, the other XLEN-1 bits in `vtype` shall be zero.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Type Illegal (`vill`)", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 478, + 479 + ] + }, + { + "chunk_id": "chunk_ed4676a7", + "text": "The XLEN-bit-wide read-only `vl` CSR can only be updated by the `vset{i}vl{i}` instructions, and the fault-only-first vector load instruction variants.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Length (`vl`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 483, + 486 + ] + }, + { + "chunk_id": "chunk_80d9c7fe", + "text": "The `vl` register holds an unsigned integer specifying the number of elements to be updated with results from a vector instruction, as further detailed in .", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Length (`vl`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 488, + 491 + ] + }, + { + "chunk_id": "chunk_0830e388", + "text": "The smallest vector implementation with VLEN=32 and supporting SEW=8 would need at least six bits in `vl` to hold the values 0-32 (VLEN=32, with LMUL=8 and SEW=8, yields VLMAX=32).", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Length (`vl`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 493, + 497 + ] + }, + { + "chunk_id": "chunk_96b18efb", + "text": "The XLEN-bit-wide read-write `vstart` CSR specifies the index of the first element to be executed by a vector instruction, as described in .", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Start Index (`vstart`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 514, + 517 + ] + }, + { + "chunk_id": "chunk_49e0d509", + "text": "Normally, `vstart` is only written by hardware on a trap on a vector instruction, with the `vstart` value representing the element on which the trap was taken (either a synchronous exception or an asynchronous interrupt), and at which execution should resume after a resumable trap is handled.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Start Index (`vstart`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 519, + 523 + ] + }, + { + "chunk_id": "chunk_874ef282", + "text": "All vector instructions are defined to begin execution with the element number given in the `vstart` CSR, leaving earlier elements in the destination vector undisturbed, and to reset the `vstart` CSR to zero at the end of execution.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Start Index (`vstart`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 525, + 528 + ] + }, + { + "chunk_id": "chunk_11535194", + "text": "`vstart` is not modified by vector instructions that raise illegal-instruction exceptions.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Start Index (`vstart`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 533, + 535 + ] + }, + { + "chunk_id": "chunk_f186a2d8", + "text": "The `vstart` CSR is defined to have only enough writable bits to hold the largest element index (one less than the maximum VLMAX).", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Start Index (`vstart`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 537, + 539 + ] + }, + { + "chunk_id": "chunk_6c161904", + "text": "The use of `vstart` values greater than the largest element index for the current `vtype` setting is reserved.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Start Index (`vstart`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 545, + 547 + ] + }, + { + "chunk_id": "chunk_fd9b2c24", + "text": "It is not required to trap, as a possible future use of upper `vstart` bits is to store imprecise trap information.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Start Index (`vstart`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 549, + 551 + ] + }, + { + "chunk_id": "chunk_e6535f14", + "text": "The `vstart` CSR is writable by unprivileged code, but non-zero `vstart` values may cause vector instructions to run substantially slower on some implementations, so `vstart` should not be used by application programmers. A few vector instructions cannot be executed with a non-zero `vstart` value and will raise an illegal-instruction exception as defined below.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Start Index (`vstart`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 553, + 558 + ] + }, + { + "chunk_id": "chunk_54ca22af", + "text": "Implementations are permitted to raise illegal-instruction exceptions when attempting to execute a vector instruction with a value of `vstart` that the implementation can never produce when executing that same instruction with the same `vtype` setting.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Start Index (`vstart`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 563, + 567 + ] + }, + { + "chunk_id": "chunk_b7bfd38e", + "text": "Such implementations are permitted to raise an illegal-instruction exception when attempting to execute a vector arithmetic instruction when `vstart` is nonzero.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Start Index (`vstart`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 569, + 573 + ] + }, + { + "chunk_id": "chunk_46f5cca6", + "text": "When migrating a software thread between two harts with different microarchitectures, the `vstart` value might not be supported by the new hart microarchitecture.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Start Index (`vstart`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 575, + 581 + ] + }, + { + "chunk_id": "chunk_e612aca8", + "text": "The runtime on the receiving hart might then have to emulate instruction execution up to the next supported `vstart` element position.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Start Index (`vstart`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 575, + 581 + ] + }, + { + "chunk_id": "chunk_40a29758", + "text": "Alternatively, migration events can be constrained to only occur at mutually supported `vstart` locations.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Start Index (`vstart`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 575, + 581 + ] + }, + { + "chunk_id": "chunk_20f1c61e", + "text": "The upper bits, `vxrm[XLEN-1:2]`, should be written as zeros.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Fixed-Point Rounding Mode (`vxrm`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 584, + 588 + ] + }, + { + "chunk_id": "chunk_61649f19", + "text": "The vector fixed-point rounding-mode is given a separate CSR address to allow independent access, but is also reflected as a field in `vcsr`.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Fixed-Point Rounding Mode (`vxrm`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 590, + 593 + ] + }, + { + "chunk_id": "chunk_f4447951", + "text": "The fixed-point rounding algorithm is specified as follows.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Fixed-Point Rounding Mode (`vxrm`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 598, + 603 + ] + }, + { + "chunk_id": "chunk_9d18a174", + "text": "Suppose the pre-rounding result is `v`, and `d` bits of that result are to be rounded off.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Fixed-Point Rounding Mode (`vxrm`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 598, + 603 + ] + }, + { + "chunk_id": "chunk_d08a2eeb", + "text": "Then the rounded result is `(v >> d) + r`, where `r` depends on the rounding mode as specified in the following table.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Fixed-Point Rounding Mode (`vxrm`) Register", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 598, + 603 + ] + }, + { + "chunk_id": "chunk_387d4e3e", + "text": "The rounding functions: ---- roundoffunsigned(v, d) = (unsigned(v) >> d) + r roundoffsigned(v, d) = (signed(v) >> d) + r ---- are used to represent this operation in the instruction descriptions below.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Fixed-Point Rounding Mode (`vxrm`) Register", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 617, + 622 + ] + }, + { + "chunk_id": "chunk_48bae0cc", + "text": "The `vxsat` CSR has a single read-write least-significant bit (`vxsat[0]`) that indicates if a fixed-point instruction has had to saturate an output value to fit into a destination format.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Fixed-Point Saturation Flag (`vxsat`)", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 626, + 630 + ] + }, + { + "chunk_id": "chunk_2ae89361", + "text": "Bits `vxsat[XLEN-1:1]` should be written as zeros.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Fixed-Point Saturation Flag (`vxsat`)", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 626, + 630 + ] + }, + { + "chunk_id": "chunk_c5769816", + "text": "The `vxsat` bit is mirrored in `vcsr`.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Fixed-Point Saturation Flag (`vxsat`)", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 632, + 633 + ] + }, + { + "chunk_id": "chunk_e05c2c3e", + "text": "The `vxrm` and `vxsat` separate CSRs can also be accessed via fields in the XLEN-bit-wide vector control and status CSR, `vcsr`.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Control and Status (`vcsr`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 637, + 639 + ] + }, + { + "chunk_id": "chunk_b3802007", + "text": "| XLEN-1:3 | | Reserved | 2:1 | vxrm[1:0] | Fixed-point rounding mode | 0 | vxsat | Fixed-point accrued saturation flag |", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Control and Status (`vcsr`) Register", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 647, + 650 + ] + }, + { + "chunk_id": "chunk_5af03e29", + "text": "The vector extension must have a consistent state at reset.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > State of Vector Extension at Reset", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 654, + 656 + ] + }, + { + "chunk_id": "chunk_73e87195", + "text": "In particular, `vtype` and `vl` must have values that can be read and then restored with a single `vsetvl` instruction.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > State of Vector Extension at Reset", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 654, + 656 + ] + }, + { + "chunk_id": "chunk_8d61799d", + "text": "The `vstart`, `vxrm`, `vxsat` CSRs can have arbitrary values at reset.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > State of Vector Extension at Reset", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 661, + 661 + ] + }, + { + "chunk_id": "chunk_36882137", + "text": "The `vxrm` and `vxsat` fields should be reset explicitly in software before use.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > State of Vector Extension at Reset", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 663, + 665 + ] + }, + { + "chunk_id": "chunk_e481ceb3", + "text": "The following diagrams illustrate how different width elements are packed into the bytes of a vector register depending on the current SEW and LMUL settings, as well as implementation VLEN.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 671, + 675 + ] + }, + { + "chunk_id": "chunk_1aa12ceb", + "text": "Elements are packed into each vector register with the least-significant byte in the lowest-numbered bits.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 671, + 675 + ] + }, + { + "chunk_id": "chunk_3cdaaf87", + "text": "The mapping was chosen to provide the simplest and most portable model for software, but might appear to incur large wiring cost for wider vector datapaths on certain operations.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "unknown", + "line_range": [ + 677, + 682 + ] + }, + { + "chunk_id": "chunk_da3cbc85", + "text": "When LMUL=1, elements are simply packed in order from the least-significant to most-significant bits of the vector register.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping for LMUL = 1", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 691, + 693 + ] + }, + { + "chunk_id": "chunk_54d91bfc", + "text": "Bits within an element are numbered in a little-endian format with increasing bit index from right to left corresponding to increasing magnitude.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping for LMUL = 1", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 695, + 699 + ] + }, + { + "chunk_id": "chunk_b40e4e1f", + "text": "The element index is given in hexadecimal and is shown placed at the least-significant byte of the stored element.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping for LMUL = 1", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 704, + 705 + ] + }, + { + "chunk_id": "chunk_2489fc21", + "text": "SEW=8b 3 2 1 0 SEW=16b 1 0 SEW=32b 0", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping for LMUL = 1", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 711, + 713 + ] + }, + { + "chunk_id": "chunk_5d1900d8", + "text": "SEW=8b 7 6 5 4 3 2 1 0 SEW=16b 3 2 1 0 SEW=32b 1 0 SEW=64b 0", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping for LMUL = 1", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 719, + 722 + ] + }, + { + "chunk_id": "chunk_d19d0ab7", + "text": "Byte F E D C B A 9 8 7 6 5 4 3 2 1 0", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping for LMUL = 1", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 726, + 726 + ] + }, + { + "chunk_id": "chunk_8e5330ce", + "text": "SEW=8b F E D C B A 9 8 7 6 5 4 3 2 1 0 SEW=16b 7 6 5 4 3 2 1 0 SEW=32b 3 2 1 0 SEW=64b 1 0", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector 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"parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 746, + 749 + ] + }, + { + "chunk_id": "chunk_2d95f4d5", + "text": "Byte F E D C B A 9 8 7 6 5 4 3 2 1 0", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping for LMUL < 1", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 754, + 754 + ] + }, + { + "chunk_id": "chunk_26be5177", + "text": "SEW=8b - - - - - - - - - - - - 3 2 1 0 SEW=16b - - - - - - 1 0 SEW=32b - - - 0 ----", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping for LMUL < 1", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 756, + 759 + ] + }, + { + "chunk_id": "chunk_642d8cf4", + "text": "When vector registers are grouped, the elements of the vector register group are packed contiguously in element order beginning with the lowest-numbered vector register and moving to the next-highest-numbered vector register in the group once each vector register is filled.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping for LMUL > 1", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 763, + 768 + ] + }, + { + "chunk_id": "chunk_bc5eba89", + "text": "Byte 3 2 1 0 v2*n 3 2 1 0 v2*n+1 7 6 5 4", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping for LMUL > 1", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + 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"confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 809, + 813 + ] + }, + { + "chunk_id": "chunk_75a6490e", + "text": "Byte F E D C B A 9 8 7 6 5 4 3 2 1 0 v2*n 3 2 1 0 v2*n+1 7 6 5 4", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping for LMUL > 1", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 817, + 819 + ] + }, + { + "chunk_id": "chunk_6eb0e4a2", + "text": "Byte F E D C B A 9 8 7 6 5 4 3 2 1 0 v4*n 3 2 1 0 v4*n+1 7 6 5 4 v4*n+2 B A 9 8 v4*n+3 F E D C ----", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping for LMUL > 1", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 823, + 828 + ] + }, + { + "chunk_id": "chunk_4bd6f882", + "text": "The recommended software strategy when operating on multiple vectors with different precision values is to modify `vtype` dynamically to keep SEW/LMUL constant (and hence VLMAX constant).", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping across Mixed-Width Operations", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 833, + 837 + ] + }, + { + "chunk_id": "chunk_4273fab1", + "text": "The following example shows four different packed element widths (8b, 16b, 32b, 64b) in a VLEN=128b implementation.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping across Mixed-Width Operations", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 839, + 843 + ] + }, + { + "chunk_id": "chunk_2706a7b4", + "text": "The vector register grouping factor (LMUL) is increased by the relative element size such that each group can hold the same number of vector elements (VLMAX=8 in this example) to simplify strip-mining code.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping across Mixed-Width Operations", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 839, + 843 + ] + }, + { + "chunk_id": "chunk_23cd3004", + "text": "Byte F E D C B A 9 8 7 6 5 4 3 2 1 0 vn - - - - - - - - 7 6 5 4 3 2 1 0 SEW=8b, LMUL=1/2", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping across Mixed-Width Operations", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 848, + 849 + ] + }, + { + "chunk_id": "chunk_b13bf5c4", + "text": "vn 7 6 5 4 3 2 1 0 SEW=16b, LMUL=1", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping across Mixed-Width Operations", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 851, + 851 + ] + }, + { + "chunk_id": "chunk_4a696ffa", + "text": "v2*n 3 2 1 0 SEW=32b, LMUL=2 v2*n+1 7 6 5 4", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping across Mixed-Width Operations", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 853, + 854 + ] + }, + { + "chunk_id": "chunk_d242e6af", + "text": "v4*n 1 0 SEW=64b, LMUL=4 v4*n+1 3 2 v4*n+2 5 4 v4*n+3 7 6 ----", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping across Mixed-Width Operations", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 856, + 860 + ] + }, + { + "chunk_id": "chunk_62236b15", + "text": "The following table shows each possible constant SEW/LMUL operating point for loops with mixed-width operations.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping across Mixed-Width Operations", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 862, + 868 + ] + }, + { + "chunk_id": "chunk_0949b082", + "text": "Each column represents a constant SEW/LMUL operating point.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping across Mixed-Width Operations", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 862, + 868 + ] + }, + { + "chunk_id": "chunk_7b712bae", + "text": "Entries in table are the LMUL values that yield that column's SEW/LMUL value for the data width on that row.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping across Mixed-Width Operations", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 862, + 868 + ] + }, + { + "chunk_id": "chunk_85d2a9b7", + "text": "In each column, an LMUL setting for a data width indicates that it can be aligned with the other data widths in the same column that also have an LMUL setting, such that all have the same VLMAX.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping across Mixed-Width Operations", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 862, + 868 + ] + }, + { + "chunk_id": "chunk_6aae7a5b", + "text": "| | 7+^| SEW/LMUL | | 1 | 2 | 4 | 8 | 16 | 32 | 64", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping across Mixed-Width Operations", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 870, + 872 + ] + }, + { + "chunk_id": "chunk_3e044c94", + "text": "| SEW= 8 | 8 | 4 | 2 | 1 | 1/2 | 1/4 | 1/8 | SEW= 16 | | 8 | 4 | 2 | 1 | 1/2 | 1/4 | SEW= 32 | | | 8 | 4 | 2 | 1 | 1/2 | SEW= 64 | | | | 8 | 4 | 2 | 1 |", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping across Mixed-Width Operations", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 874, + 878 + ] + }, + { + "chunk_id": "chunk_8f5f8d0b", + "text": "Larger LMUL settings can also used to simply increase vector length to reduce instruction fetch and dispatch overheads in cases where fewer vector register groups are needed.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping across Mixed-Width Operations", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 880, + 882 + ] + }, + { + "chunk_id": "chunk_1dbb37f1", + "text": "A vector mask occupies only one vector register regardless of SEW and LMUL.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mask Register Layout", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 887, + 889 + ] + }, + { + "chunk_id": "chunk_1bc4d072", + "text": "Each element is allocated a single mask bit in a mask vector register.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mask Register Layout", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 891, + 894 + ] + }, + { + "chunk_id": "chunk_800e13ed", + "text": "The mask bit for element i is located in bit i of the mask register, independent of SEW or LMUL.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mask Register Layout", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 891, + 894 + ] + }, + { + "chunk_id": "chunk_1c47f08c", + "text": "Vector loads and stores are encoded within the scalar floating-point load and store major opcodes (LOAD-FP/STORE-FP).", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 901, + 906 + ] + }, + { + "chunk_id": "chunk_4e824fcd", + "text": "By default, for most operands of most instructions, EEW=SEW and EMUL=LMUL.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Vector Operands", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 948, + 953 + ] + }, + { + "chunk_id": "chunk_838f92a2", + "text": "Vector operands or results may occupy one or more vector registers depending on EMUL, but are always specified using the lowest-numbered vector register in the group.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Vector Operands", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 963, + 967 + ] + }, + { + "chunk_id": "chunk_5bb645c0", + "text": "An encoding that would result in the same vector register being read with two or more different EEWs, including when the vector register appears at different positions within two or more vector register groups, is reserved.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Vector Operands", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 969, + 976 + ] + }, + { + "chunk_id": "chunk_e9a44fbe", + "text": "A destination vector register group can overlap a source vector register group only if one of the following holds:", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Vector Operands", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 983, + 985 + ] + }, + { + "chunk_id": "chunk_ffeacabb", + "text": "When source and destination registers overlap and have different EEW, the instruction is mask- and tail-agnostic, regardless of the setting of the `vta` and `vma` bits in `vtype`.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Vector Operands", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1010, + 1013 + ] + }, + { + "chunk_id": "chunk_81aa6583", + "text": "Element operations that are masked off (inactive) never generate exceptions.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Vector Masking", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1030, + 1035 + ] + }, + { + "chunk_id": "chunk_74460c10", + "text": "The destination vector register elements corresponding to masked-off elements are handled with either a mask-undisturbed or mask-agnostic policy depending on the setting of the `vma` bit in `vtype` ().", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Vector Masking", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1030, + 1035 + ] + }, + { + "chunk_id": "chunk_bcb4bbe5", + "text": "Where available, masking is encoded in a single-bit `vm` field in the instruction (`inst[25]`).", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Vector Masking > Mask Encoding", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 1066, + 1068 + ] + }, + { + "chunk_id": "chunk_616a0657", + "text": "Vector masking is represented in assembler code as another vector operand, with `.t` indicating that the operation occurs when `v0.mask[i]` is `1` (`t` for \"true\").", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Vector Masking > Mask Encoding", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1078, + 1081 + ] + }, + { + "chunk_id": "chunk_c36221d3", + "text": "If no masking operand is specified, unmasked vector execution (`vm=1`) is assumed.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Vector Masking > Mask Encoding", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1078, + 1081 + ] + }, + { + "chunk_id": "chunk_2fbc3961", + "text": "The prestart elements are those whose element index is less than the initial value in the `vstart` register.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Prestart, Active, Inactive, Body, and Tail Element Definitions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 1105, + 1106 + ] + }, + { + "chunk_id": "chunk_8157fc43", + "text": "The prestart elements do not raise exceptions and do not update the destination vector register.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Prestart, Active, Inactive, Body, and Tail Element Definitions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 1105, + 1106 + ] + }, + { + "chunk_id": "chunk_db16c30e", + "text": "The body elements are those whose element index is greater than or equal to the initial value in the `vstart` register, and less than the current vector length setting in `vl`.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Prestart, Active, Inactive, Body, and Tail Element Definitions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 1108, + 1110 + ] + }, + { + "chunk_id": "chunk_03604f63", + "text": "The active elements can raise exceptions and update the destination vector register group.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Prestart, Active, Inactive, Body, and Tail Element Definitions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 1112, + 1114 + ] + }, + { + "chunk_id": "chunk_e12a5ef7", + "text": "The inactive elements do not raise exceptions and do not update any destination vector register group unless masked agnostic is specified (`vtype.vma`=1), in which case inactive elements may be overwritten with 1s.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Prestart, Active, Inactive, Body, and Tail Element Definitions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1116, + 1118 + ] + }, + { + "chunk_id": "chunk_8d8fc413", + "text": "The tail elements during a vector instruction's execution are the elements past the current vector length setting specified in `vl`.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Prestart, Active, Inactive, Body, and Tail Element Definitions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1120, + 1122 + ] + }, + { + "chunk_id": "chunk_38e1c0ce", + "text": "The tail elements do not raise exceptions, and do not update any destination vector register group unless tail agnostic is specified (`vtype.vta`=1), in which case tail elements may be overwritten with 1s, or with the result of the instruction in the case of mask-producing instructions except for mask loads.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Prestart, Active, Inactive, Body, and Tail Element Definitions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1120, + 1122 + ] + }, + { + "chunk_id": "chunk_7a8c3b86", + "text": "When LMUL < 1, the tail includes the elements past VLMAX that are held in the same vector register.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Prestart, Active, Inactive, Body, and Tail Element Definitions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1120, + 1122 + ] + }, + { + "chunk_id": "chunk_cb85a7a1", + "text": "---- for element index x prestart(x) = (0 <= x < vstart) body(x) = (vstart <= x < vl) tail(x) = (vl <= x < max(VLMAX,VLEN/SEW)) mask(x) = unmasked || v0.mask[x] 1 active(x) = body(x) && mask(x) inactive(x) = body(x) && !mask(x) ----", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Prestart, Active, Inactive, Body, and Tail Element Definitions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1124, + 1132 + ] + }, + { + "chunk_id": "chunk_7abd1fbf", + "text": "When `vstart` {ge} `vl`, there are no body elements, and no elements are updated in any destination vector register group, including that no tail elements are updated with agnostic values.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Prestart, Active, Inactive, Body, and Tail Element Definitions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1134, + 1137 + ] + }, + { + "chunk_id": "chunk_0646c622", + "text": "Instructions that write an `x` register or `f` register do so even when `vstart` {ge} `vl`, including when `vl`=0.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Prestart, Active, Inactive, Body, and Tail Element Definitions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1143, + 1145 + ] + }, + { + "chunk_id": "chunk_6e31e5d5", + "text": "The general policy is to return the value 0 when the index is greater than VLMAX in the source vector register group.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Prestart, Active, Inactive, Body, and Tail Element Definitions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 1147, + 1150 + ] + }, + { + "chunk_id": "chunk_a2daceee", + "text": "The application specifies the total number of elements to be processed (the application vector length or AVL) as a candidate value for `vl`, and the hardware responds via a general-purpose register with the (frequently smaller) number of elements that the hardware will handle per iteration (stored in `vl`), based on the microarchitectural implementation and the `vtype` setting. A straightforward loop structure, shown in , depicts the ease with which the code keeps track of the remaining number of elements and the amount per iteration handled by hardware.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`)", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1155, + 1166 + ] + }, + { + "chunk_id": "chunk_983fab24", + "text": "A set of instructions is provided to allow rapid configuration of the values in `vl` and `vtype` to match application needs.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`)", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1168, + 1171 + ] + }, + { + "chunk_id": "chunk_6b11e34b", + "text": "The `vset{i}vl{i}` instructions set the `vtype` and `vl` CSRs based on their arguments, and write the new value of `vl` into `rd`.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`)", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1168, + 1171 + ] + }, + { + "chunk_id": "chunk_d08063ef", + "text": "---- vsetvli rd, rs1, vtypei rd = new vl, rs1 = AVL, vtypei = new vtype setting vsetivli rd, uimm, vtypei rd = new vl, uimm = AVL, vtypei = new vtype setting vsetvl rd, rs1, rs2 rd = new vl, rs1 = AVL, rs2 = new vtype value ----", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`)", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1173, + 1177 + ] + }, + { + "chunk_id": "chunk_cccadccc", + "text": "The new `vtype` value is encoded in the immediate fields of `vsetvli` and `vsetivli`, and in the `rs2` register for `vsetvl`.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > `vtype` encoding", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1185, + 1187 + ] + }, + { + "chunk_id": "chunk_f9421ee1", + "text": "---- Suggested assembler names used for vset{i}vli vtypei immediate", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > `vtype` encoding", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1189, + 1190 + ] + }, + { + "chunk_id": "chunk_de3c6ab2", + "text": "Examples: vsetvli t0, a0, e8, m1, ta, ma SEW= 8, LMUL=1 vsetvli t0, a0, e8, m2, ta, ma SEW= 8, LMUL=2 vsetvli t0, a0, e32, mf2, ta, ma SEW=32, LMUL=1/2 ----", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > `vtype` encoding", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1205, + 1209 + ] + }, + { + "chunk_id": "chunk_7a158acb", + "text": "The `vsetvl` variant operates similarly to `vsetvli` except that it takes a `vtype` value from `rs2` and can be used for context restore.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > `vtype` encoding", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1211, + 1212 + ] + }, + { + "chunk_id": "chunk_2153b69c", + "text": "If the `vtype` value is not supported by the implementation, then the `vill` bit is set in `vtype`, the remaining bits in `vtype` are set to zero, and the `vl` register is also set to zero.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > `vtype` encoding > Unsupported `vtype` Values", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 1216, + 1218 + ] + }, + { + "chunk_id": "chunk_da8f6255", + "text": "However, this would have added the first data-dependent trap on a CSR write to the ISA.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > `vtype` encoding > Unsupported `vtype` Values", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1220, + 1227 + ] + }, + { + "chunk_id": "chunk_4f481530", + "text": "Implementations could choose to trap when illegal values are written to `vtype` instead of setting `vill`, to allow emulation to support new configurations for forward-compatibility.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > `vtype` encoding > Unsupported `vtype` Values", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1220, + 1227 + ] + }, + { + "chunk_id": "chunk_a123b49a", + "text": "The current scheme supports light-weight runtime interrogation of the supported vector unit configurations by checking if `vill` is clear for a given setting.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > `vtype` encoding > Unsupported `vtype` Values", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1220, + 1227 + ] + }, + { + "chunk_id": "chunk_d5e40453", + "text": "A `vtype` value with `vill` set is treated as an unsupported configuration.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > `vtype` encoding > Unsupported `vtype` Values", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1229, + 1231 + ] + }, + { + "chunk_id": "chunk_a20bbe5a", + "text": "Implementations must consider all bits of the `vtype` value to determine if the configuration is supported.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > `vtype` encoding > Unsupported `vtype` Values", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1233, + 1236 + ] + }, + { + "chunk_id": "chunk_4dd0c839", + "text": "An unsupported value in any location within the `vtype` value must result in `vill` being set.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > `vtype` encoding > Unsupported `vtype` Values", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1233, + 1236 + ] + }, + { + "chunk_id": "chunk_9c10de18", + "text": "Implementations cannot ignore fields they do not implement.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > `vtype` encoding > Unsupported `vtype` Values", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 1238, + 1242 + ] + }, + { + "chunk_id": "chunk_8efcbd73", + "text": "All bits must be checked to ensure that new code assuming unsupported vector features in `vtype` traps instead of executing incorrectly on an older implementation.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > `vtype` encoding > Unsupported `vtype` Values", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1238, + 1242 + ] + }, + { + "chunk_id": "chunk_5bdb9f2f", + "text": "The new vector length setting is based on AVL, which for `vsetvli` and `vsetvl` is encoded in the `rs1` and `rd` fields as follows:", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > AVL encoding", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1246, + 1248 + ] + }, + { + "chunk_id": "chunk_55fae626", + "text": "When rs1 is not `x0`, the AVL is an unsigned integer held in the `x` register specified by rs1, and the new `vl` value is also written to the `x` register specified by rd.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > AVL encoding", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1260, + 1263 + ] + }, + { + "chunk_id": "chunk_4e93bbbd", + "text": "When rs1=`x0` but rd!=`x0`, the maximum unsigned integer value (`~0`) is used as the AVL, and the resulting VLMAX is written to `vl` and also to the `x` register specified by `rd`.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > AVL encoding", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 1265, + 1268 + ] + }, + { + "chunk_id": "chunk_fa0458ed", + "text": "When rs1=`x0` and rd=`x0`, the instructions operate as if the current vector length in `vl` is used as the AVL, and the resulting value is written to `vl`, but not to a destination register.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > AVL encoding", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1270, + 1270 + ] + }, + { + "chunk_id": "chunk_efce93a0", + "text": "This form can only be used when VLMAX and hence `vl` is not actually changed by the new SEW/LMUL ratio.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > AVL encoding", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1270, + 1270 + ] + }, + { + "chunk_id": "chunk_55ecc5ba", + "text": "Use of the instructions with a new SEW/LMUL ratio that would result in a change of VLMAX is reserved.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > AVL encoding", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1270, + 1270 + ] + }, + { + "chunk_id": "chunk_77c3e146", + "text": "Use of the instructions is also reserved if `vill` was 1 beforehand.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > AVL encoding", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1270, + 1270 + ] + }, + { + "chunk_id": "chunk_7b4d904f", + "text": "Implementations may set `vill` in either case.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > AVL encoding", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1270, + 1270 + ] + }, + { + "chunk_id": "chunk_39f219b2", + "text": "This design was chosen to ensure `vl` would always hold a legal value for current `vtype` setting.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > AVL encoding", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1272, + 1280 + ] + }, + { + "chunk_id": "chunk_67f004f2", + "text": "The current `vl` value can be read from the `vl` CSR.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > AVL encoding", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1272, + 1280 + ] + }, + { + "chunk_id": "chunk_621489a4", + "text": "The `vl` value could be reduced by these instructions if the new SEW/LMUL ratio causes VLMAX to shrink, and so this case has been reserved as it is not clear this is a generally useful operation, and implementations can otherwise assume `vl` is not changed by these instructions to optimize their microarchitecture.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > AVL encoding", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1272, + 1280 + ] + }, + { + "chunk_id": "chunk_4ae85374", + "text": "For the `vsetivli` instruction, the AVL is encoded as a 5-bit zero-extended immediate (0--31) in the `rs1` field.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > AVL encoding", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 1282, + 1284 + ] + }, + { + "chunk_id": "chunk_c9912437", + "text": "The `vset{i}vl{i}` instructions first set VLMAX according to their `vtype` argument, then set `vl` obeying the following constraints:", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > Constraints on Setting `vl`", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1296, + 1298 + ] + }, + { + "chunk_id": "chunk_3004082d", + "text": "Deterministic on any given implementation for same input AVL and VLMAX values .", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > Constraints on Setting `vl`", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1300, + 1311 + ] + }, + { + "chunk_id": "chunk_402dab50", + "text": "These specific properties follow from the prior rules: .. `vl = 0` if `AVL = 0` .. `vl > 0` if `AVL > 0` .. `vl {le} VLMAX` .. `vl {le} AVL` .. a value read from `vl` when used as the AVL argument to `vset{i}vl{i}` results in the same value in `vl`, provided the resultant VLMAX equals the value of VLMAX at the time that `vl` was read", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > Constraints on Setting `vl`", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1300, + 1311 + ] + }, + { + "chunk_id": "chunk_aa2ac48b", + "text": "Requirement 2 ensures that the first strip-mine iteration of reduction loops uses the largest vector length of all iterations, even in the case of `AVL < 2*VLMAX`.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > Constraints on Setting `vl`", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1320, + 1329 + ] + }, + { + "chunk_id": "chunk_2180ca08", + "text": "Requirement 2 also allows an implementation to set vl to VLMAX for `VLMAX < AVL < 2*VLMAX` --", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > Constraints on Setting `vl`", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1320, + 1329 + ] + }, + { + "chunk_id": "chunk_f59c03df", + "text": "The SEW and LMUL settings can be changed dynamically to provide high throughput on mixed-width operations in a single loop. ---- Example: Load 16-bit values, widen multiply to 32b, shift 32b result right by 3, store 32b values.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > Example of strip mining and changes to SEW", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 1334, + 1342 + ] + }, + { + "chunk_id": "chunk_08b7e239", + "text": "vsetvli x0, x0, e32, m8, ta, ma Operate on 32b values vsrl.vi v8, v8, 3 vse32.v v8, (a2) Store vector of 32b elements slli t1, a3, 2 Multiply elements this iteration by 4 bytes/destination element add a2, a2, t1 Bump pointer sub a0, a0, a3 Decrement count by vl bnez a0, loop Any more? ----", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > Example of strip mining and changes to SEW", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 1352, + 1359 + ] + }, + { + "chunk_id": "chunk_7410d06d", + "text": "Vector loads and stores can be masked, and they only access memory or raise exceptions for active elements.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 1364, + 1372 + ] + }, + { + "chunk_id": "chunk_d7acb521", + "text": "Masked vector loads do not update inactive elements in the destination vector register group, unless masked agnostic is specified (`vtype.vma`=1).", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1364, + 1372 + ] + }, + { + "chunk_id": "chunk_153d329d", + "text": "All vector loads and stores may generate and accept a non-zero `vstart` value.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1364, + 1372 + ] + }, + { + "chunk_id": "chunk_4d0b3fae", + "text": "Vector loads and stores are encoded within the scalar floating-point load and store major opcodes (LOAD-FP/STORE-FP).", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Instruction Encoding", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 1376, + 1381 + ] + }, + { + "chunk_id": "chunk_eedf5d77", + "text": "See | mop[1:0] | specifies memory addressing mode | nf[2:0] | specifies the number of fields in each segment, for segment load/stores | lumop[4:0]/sumop[4:0] | are additional fields encoding variants of unit-stride instructions |", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Instruction Encoding", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 1389, + 1400 + ] + }, + { + "chunk_id": "chunk_30622221", + "text": "Vector memory unit-stride and constant-stride operations directly encode EEW of the data to be transferred statically in the instruction to reduce the number of `vtype` changes when accessing memory in a mixed-width routine.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Instruction Encoding", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1402, + 1402 + ] + }, + { + "chunk_id": "chunk_793aeb7a", + "text": "The data vector register group has EEW=SEW, EMUL=LMUL, while the offset vector register group has EEW encoded in the instruction and EMUL=(EEW/SEW)*LMUL.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Addressing Modes", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 1424, + 1430 + ] + }, + { + "chunk_id": "chunk_5bb0d930", + "text": "If the vector offset elements are narrower than XLEN, they are zero-extended to XLEN before adding to the base effective address.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Addressing Modes", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 1443, + 1450 + ] + }, + { + "chunk_id": "chunk_d2da2701", + "text": "If the vector offset elements are wider than XLEN, the least-significant XLEN bits are used in the address calculation.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Addressing Modes", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "range", + "line_range": [ + 1443, + 1450 + ] + }, + { + "chunk_id": "chunk_000cf0e1", + "text": "If the implementation does not support the EEW of the offset elements, the instruction is reserved.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Addressing Modes", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1443, + 1450 + ] + }, + { + "chunk_id": "chunk_8c1cbf96", + "text": "The vector addressing modes are encoded using the 2-bit `mop[1:0]` field.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Addressing Modes", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 1455, + 1456 + ] + }, + { + "chunk_id": "chunk_fac8ce9f", + "text": "If the accesses are to a strongly ordered IO region, the element accesses can be initiated in any order.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Addressing Modes", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1487, + 1490 + ] + }, + { + "chunk_id": "chunk_9e116f85", + "text": "For implementations with precise vector traps, exceptions on indexed-unordered stores must also be precise.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Addressing Modes", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "line_range": [ + 1495, + 1497 + ] + }, + { + "chunk_id": "chunk_9be7667f", + "text": "Additional unit-stride vector addressing modes are encoded using the 5-bit `lumop` and `sumop` fields in the unit-stride load and store instruction encodings respectively.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Addressing Modes", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 1499, + 1501 + ] + }, + { + "chunk_id": "chunk_003dc0bf", + "text": "| 0 | 0 | 0 | 0 | 0 | unit-stride load | 0 | 1 | 0 | 0 | 0 | unit-stride, whole register load | 0 | 1 | 0 | 1 | 1 | unit-stride, mask load, EEW=8 | 1 | 0 | 0 | 0 | 0 | unit-stride fault-only-first | x | x | x | x | x | other encodings reserved |", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Addressing Modes", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 1508, + 1513 + ] + }, + { + "chunk_id": "chunk_2f486243", + "text": "The `nf[2:0]` field encodes the number of fields in each segment.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Addressing Modes", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 1526, + 1532 + ] + }, + { + "chunk_id": "chunk_d6d1e392", + "text": "Larger values in the `nf` field are used to access multiple contiguous fields within a segment as described below in .", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Addressing Modes", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 1526, + 1532 + ] + }, + { + "chunk_id": "chunk_6fb69d97", + "text": "The `nf[2:0]` field also encodes the number of whole vector registers to transfer for the whole vector register load/store instructions.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Addressing Modes", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 1534, + 1536 + ] + }, + { + "chunk_id": "chunk_9bd72c15", + "text": "Vector loads and stores have an EEW encoded directly in the instruction.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Width Encoding", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 1541, + 1546 + ] + }, + { + "chunk_id": "chunk_bbdba0c6", + "text": "If the EMUL would be out of range (EMUL>8 or EMUL<1/8), the instruction encoding is reserved.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Width Encoding", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 1541, + 1546 + ] + }, + { + "chunk_id": "chunk_7a47c928", + "text": "The vector register groups must have legal register specifiers for the selected EMUL, otherwise the instruction encoding is reserved.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Width Encoding", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1541, + 1546 + ] + }, + { + "chunk_id": "chunk_ad86c660", + "text": "Vector unit-stride and constant-stride use the EEW/EMUL encoded in the instruction for the data values, while vector indexed loads and stores use the EEW/EMUL encoded in the instruction for the index values and the SEW/LMUL encoded in `vtype` for the data values.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Width Encoding", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1548, + 1552 + ] + }, + { + "chunk_id": "chunk_ad14d11d", + "text": "Vector loads and stores are encoded using width values that are not claimed by the standard scalar floating-point loads and stores.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Width Encoding", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 1554, + 1555 + ] + }, + { + "chunk_id": "chunk_19264dca", + "text": "Implementations must provide vector loads and stores with EEWs corresponding to all supported SEW settings.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Width Encoding", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1557, + 1557 + ] + }, + { + "chunk_id": "chunk_0c6aee9a", + "text": "| Standard scalar FP | x | 0 | 0 | 1 | 16| FLEN | - | FLH/FSH | Standard scalar FP | x | 0 | 1 | 0 | 32| FLEN | - | FLW/FSW | Standard scalar FP | x | 0 | 1 | 1 | 64| FLEN | - | FLD/FSD | Standard scalar FP | x | 1 | 0 | 0 | 128| FLEN | - | FLQ/FSQ | Vector 8b element | 0 | 0 | 0 | 0 | 8| 8 | - | VLxE8/VSxE8 | Vector 16b element | 0 | 1 | 0 | 1 | 16| 16 | - | VLxE16/VSxE16 | Vector 32b element | 0 | 1 | 1 | 0 | 32| 32 | - | VLxE32/VSxE32 | Vector 64b element | 0 | 1 | 1 | 1 | 64| 64 | - | VLxE64/VSxE64 | Vector 8b index | 0 | 0 | 0 | 0 | SEW | SEW | 8 | VLxEI8/VSxEI8 | Vector 16b index | 0 | 1 | 0 | 1 | SEW | SEW | 16 | VLxEI16/VSxEI16 | Vector 32b index | 0 | 1 | 1 | 0 | SEW | SEW | 32 | VLxEI32/VSxEI32 | Vector 64b index | 0 | 1 | 1 | 1 | SEW | SEW | 64 | VLxEI64/VSxEI64 | Reserved | 1 | X | X | X | - | - | - | |", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Width Encoding", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1564, + 1577 + ] + }, + { + "chunk_id": "chunk_06e83c95", + "text": "---- Vector unit-stride mask load vlm.v vd, (rs1) Load byte vector of length ceil(vl/8)", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Unit-Stride Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1616, + 1618 + ] + }, + { + "chunk_id": "chunk_8f80ad27", + "text": "Vector unit-stride mask store vsm.v vs3, (rs1) Store byte vector of length ceil(vl/8) ----", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Unit-Stride Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1620, + 1622 + ] + }, + { + "chunk_id": "chunk_9e77658f", + "text": "`vlm.v` and `vsm.v` are encoded with the same `width[2:0]`=0 encoding as `vle8.v` and `vse8.v`, but are distinguished by different `lumop` and `sumop` encodings.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Unit-Stride Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1624, + 1627 + ] + }, + { + "chunk_id": "chunk_21bf3e84", + "text": "Since `vlm.v` and `vsm.v` operate as byte loads and stores, `vstart` is in units of bytes for these instructions.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Unit-Stride Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1624, + 1627 + ] + }, + { + "chunk_id": "chunk_060180a5", + "text": "However, these instructions also provide a convenient mechanism to use packed bit vectors in memory as mask values, and also reduce the cost of mask spill/fill by reducing need to change `vl`.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Unit-Stride Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1637, + 1642 + ] + }, + { + "chunk_id": "chunk_c579ff8a", + "text": "vd destination, rs1 base address, rs2 byte constant-stride vlse8.v vd, (rs1), rs2, vm 8-bit constant-stride load vlse16.v vd, (rs1), rs2, vm 16-bit constant-stride load vlse32.v vd, (rs1), rs2, vm 32-bit constant-stride load vlse64.v vd, (rs1), rs2, vm 64-bit constant-stride load", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Constant-Stride Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 1649, + 1653 + ] + }, + { + "chunk_id": "chunk_30eaf178", + "text": "vs3 store data, rs1 base address, rs2 byte constant-stride vsse8.v vs3, (rs1), rs2, vm 8-bit constant-stride store vsse16.v vs3, (rs1), rs2, vm 16-bit constant-stride store vsse32.v vs3, (rs1), rs2, vm 32-bit constant-stride store vsse64.v vs3, (rs1), rs2, vm 64-bit constant-stride store ----", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Constant-Stride Instructions", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 1655, + 1660 + ] + }, + { + "chunk_id": "chunk_9ca3cffa", + "text": "When `rs2`=`x0`, then an implementation is allowed, but not required, to perform fewer memory operations than the number of active elements, and may perform different numbers of memory operations across different dynamic executions of the same static instruction.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Constant-Stride Instructions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1669, + 1673 + ] + }, + { + "chunk_id": "chunk_480de010", + "text": "When `rs2!=x0` and the value of `x[rs2]=0`, the implementation must perform one memory access for each active element (but these accesses will not be ordered).", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Constant-Stride Instructions", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1679, + 1681 + ] + }, + { + "chunk_id": "chunk_92dc0b09", + "text": "When repeating ordered vector accesses to the same memory address are required, then an ordered indexed operation can be used.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Constant-Stride Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1690, + 1691 + ] + }, + { + "chunk_id": "chunk_b3afcbd5", + "text": "Vector indexed-unordered load instructions vd destination, rs1 base address, vs2 byte offsets vluxei8.v vd, (rs1), vs2, vm unordered 8-bit indexed load of SEW data vluxei16.v vd, (rs1), vs2, vm unordered 16-bit indexed load of SEW data vluxei32.v vd, (rs1), vs2, vm unordered 32-bit indexed load of SEW data vluxei64.v vd, (rs1), vs2, vm unordered 64-bit indexed load of SEW data", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Indexed Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 1698, + 1703 + ] + }, + { + "chunk_id": "chunk_434969dd", + "text": "Vector indexed-ordered load instructions vd destination, rs1 base address, vs2 byte offsets vloxei8.v vd, (rs1), vs2, vm ordered 8-bit indexed load of SEW data vloxei16.v vd, (rs1), vs2, vm ordered 16-bit indexed load of SEW data vloxei32.v vd, (rs1), vs2, vm ordered 32-bit indexed load of SEW data vloxei64.v vd, (rs1), vs2, vm ordered 64-bit indexed load of SEW data", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Indexed Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 1705, + 1710 + ] + }, + { + "chunk_id": "chunk_5823302e", + "text": "Vector indexed-unordered store instructions vs3 store data, rs1 base address, vs2 byte offsets vsuxei8.v vs3, (rs1), vs2, vm unordered 8-bit indexed store of SEW data vsuxei16.v vs3, (rs1), vs2, vm unordered 16-bit indexed store of SEW data vsuxei32.v vs3, (rs1), vs2, vm unordered 32-bit indexed store of SEW data vsuxei64.v vs3, (rs1), vs2, vm unordered 64-bit indexed store of SEW data", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Indexed Instructions", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 1712, + 1717 + ] + }, + { + "chunk_id": "chunk_48b72283", + "text": "Vector indexed-ordered store instructions vs3 store data, rs1 base address, vs2 byte offsets vsoxei8.v vs3, (rs1), vs2, vm ordered 8-bit indexed store of SEW data vsoxei16.v vs3, (rs1), vs2, vm ordered 16-bit indexed store of SEW data vsoxei32.v vs3, (rs1), vs2, vm ordered 32-bit indexed store of SEW data vsoxei64.v vs3, (rs1), vs2, vm ordered 64-bit indexed store of SEW data ----", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Indexed Instructions", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 1719, + 1725 + ] + }, + { + "chunk_id": "chunk_a2007328", + "text": "The unit-stride fault-only-first load instructions are used to vectorize loops with data-dependent exit conditions (\"while\" loops).", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Unit-stride Fault-Only-First Loads", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1740, + 1743 + ] + }, + { + "chunk_id": "chunk_1429c5af", + "text": "These instructions execute as a regular load except that they will only take a trap caused by a synchronous exception on element 0.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Unit-stride Fault-Only-First Loads", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1740, + 1743 + ] + }, + { + "chunk_id": "chunk_ec1a1765", + "text": "If element 0 raises an exception, `vl` is not modified, and the trap is taken.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Unit-stride Fault-Only-First Loads", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1740, + 1743 + ] + }, + { + "chunk_id": "chunk_6ce0ce7d", + "text": "If an element > 0 raises an exception, the corresponding trap is not taken, and the vector length `vl` is reduced to the index of the element that would have raised an exception.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Unit-stride Fault-Only-First Loads", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1740, + 1743 + ] + }, + { + "chunk_id": "chunk_726d5217", + "text": "Load instructions may overwrite active destination vector register group elements past the element index at which the trap is reported.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Unit-stride Fault-Only-First Loads", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1745, + 1747 + ] + }, + { + "chunk_id": "chunk_12d536d4", + "text": "Similarly, fault-only-first load instructions may update active destination elements past the element that causes trimming of the vector length (but not past the original vector length).", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Unit-stride Fault-Only-First Loads", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1745, + 1747 + ] + }, + { + "chunk_id": "chunk_09971494", + "text": "Non-idempotent memory locations can only be accessed when it is known the corresponding element load operation will not be restarted due to a trap or vector-length trimming.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Unit-stride Fault-Only-First Loads", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1745, + 1747 + ] + }, + { + "chunk_id": "chunk_c29d5fa7", + "text": "---- strlen example using unit-stride fault-only-first instruction", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Unit-stride Fault-Only-First Loads", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1759, + 1760 + ] + }, + { + "chunk_id": "chunk_8bcbd080", + "text": "The unit-stride versions only allow probing a region immediately contiguous to a known region, and so reduce the security impact when used in unprivileged code.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Unit-stride Fault-Only-First Loads", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1765, + 1776 + ] + }, + { + "chunk_id": "chunk_664faa8a", + "text": "Constant-stride and scatter/gather fault-only-first instructions are not provided due to lack of encoding space, but they can also represent a larger security hole, allowing even unprivileged software to easily check multiple random pages for accessibility without experiencing a trap.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Unit-stride Fault-Only-First Loads", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "enum", + "line_range": [ + 1765, + 1776 + ] + }, + { + "chunk_id": "chunk_c479a877", + "text": "This standard does not address possible security mitigations for fault-only-first instructions.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Unit-stride Fault-Only-First Loads", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1765, + 1776 + ] + }, + { + "chunk_id": "chunk_b40b80b0", + "text": "Even when an exception is not raised, implementations are permitted to process fewer than `vl` elements and reduce `vl` accordingly, but if `vstart`=0 and `vl`>0, then at least one element must be processed.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Unit-stride Fault-Only-First Loads", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 1778, + 1781 + ] + }, + { + "chunk_id": "chunk_42cf6152", + "text": "When the fault-only-first instruction takes a trap due to an interrupt, implementations should not reduce `vl` and should instead set a `vstart` value.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Unit-stride Fault-Only-First Loads", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1783, + 1786 + ] + }, + { + "chunk_id": "chunk_666c4ff3", + "text": "When the fault-only-first instruction would trigger a debug data-watchpoint trap on an element after the first, implementations should not reduce `vl` but instead should trigger the debug trap as otherwise the event might be lost.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Unit-stride Fault-Only-First Loads", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1788, + 1791 + ] + }, + { + "chunk_id": "chunk_a03e8e70", + "text": "The vector load/store segment instructions move multiple contiguous fields in memory to and from consecutively numbered vector registers.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 1796, + 1797 + ] + }, + { + "chunk_id": "chunk_af1d1b2e", + "text": "The three-bit `nf` field in the vector instruction encoding is an unsigned integer that contains one less than the number of fields per segment, NFIELDS.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "range", + "line_range": [ + 1805, + 1808 + ] + }, + { + "chunk_id": "chunk_a66def17", + "text": "The EMUL setting must be such that EMUL * NFIELDS {le} 8, otherwise the instruction encoding is reserved.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1826, + 1828 + ] + }, + { + "chunk_id": "chunk_1c6aa97a", + "text": "Each field will be held in successively numbered vector register groups.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 1836, + 1843 + ] + }, + { + "chunk_id": "chunk_4ce717ba", + "text": "When EMUL>1, each field will occupy a vector register group held in multiple successively numbered vector registers, and the vector register group for each field must follow the usual vector register alignment constraints (e.g., when EMUL=2 and NFIELDS=4, each field's vector register group must start at an even vector register, but does not have to start at a multiple of 8 vector register number).", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1836, + 1843 + ] + }, + { + "chunk_id": "chunk_f418ea7f", + "text": "If the vector register numbers accessed by the segment load or store would increment past 31, then the instruction encoding is reserved.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 1845, + 1847 + ] + }, + { + "chunk_id": "chunk_17a94e21", + "text": "The `vl` register gives the number of segments to move, which is equal to the number of elements transferred to each vector register group.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 1853, + 1856 + ] + }, + { + "chunk_id": "chunk_fd2bb749", + "text": "For segment loads and stores, the individual memory accesses used to access fields within each segment are unordered with respect to each other even for ordered indexed segment loads and stores.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 1858, + 1861 + ] + }, + { + "chunk_id": "chunk_5855aeff", + "text": "The `vstart` value is in units of whole segments.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1863, + 1865 + ] + }, + { + "chunk_id": "chunk_c9b92996", + "text": "If a trap occurs during access to a segment, it is implementation-defined whether a subset of the faulting segment's accesses are performed before the trap is taken.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 1863, + 1865 + ] + }, + { + "chunk_id": "chunk_b062fbc5", + "text": "The assembler prefixes `vlseg`/`vsseg` are used for unit-stride segment loads and stores respectively.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions > Vector Unit-Stride Segment Loads and Stores", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1878, + 1879 + ] + }, + { + "chunk_id": "chunk_35e54fdb", + "text": "Examples vlseg8e8.v vd, (rs1), vm Load eight vector registers with eight byte fields.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions > Vector Unit-Stride Segment Loads and Stores", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1887, + 1888 + ] + }, + { + "chunk_id": "chunk_f4be0851", + "text": "vsseg3e32.v vs3, (rs1), vm Store packed vector of 3*4-byte segments from vs3,vs3+1,vs3+2 to memory ----", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions > Vector Unit-Stride Segment Loads and Stores", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 1890, + 1891 + ] + }, + { + "chunk_id": "chunk_b0889704", + "text": "For loads, the `vd` register will hold the first field loaded from the segment.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions > Vector Unit-Stride Segment Loads and Stores", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 1893, + 1896 + ] + }, + { + "chunk_id": "chunk_0a89af58", + "text": "For stores, the `vs3` register is read to provide the first field to be stored to each segment.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions > Vector Unit-Stride Segment Loads and Stores", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 1893, + 1896 + ] + }, + { + "chunk_id": "chunk_f32d7842", + "text": "---- Example 1 Memory structure holds packed RGB pixels (24-bit data structure, 8bpp) vsetvli a1, t0, e8, m1, ta, ma vlseg3e8.v v8, (a0), vm v8 holds the red pixels v9 holds the green pixels v10 holds the blue pixels", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions > Vector Unit-Stride Segment Loads and Stores", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 1898, + 1905 + ] + }, + { + "chunk_id": "chunk_1afd0b53", + "text": "Example 2 Memory structure holds complex values, 32b for real and 32b for imaginary vsetvli a1, t0, e32, m1, ta, ma vlseg2e32.v v8, (a0), vm v8 holds real v9 holds imaginary ----", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions > Vector Unit-Stride Segment Loads and Stores", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1907, + 1913 + ] + }, + { + "chunk_id": "chunk_ed674a64", + "text": "There are also fault-only-first versions of the unit-stride instructions.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions > Vector Unit-Stride Segment Loads and Stores", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1915, + 1915 + ] + }, + { + "chunk_id": "chunk_57081eb7", + "text": "For fault-only-first segment loads, if an exception is detected partway through accessing the zeroth segment, the trap is taken.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions > Vector Unit-Stride Segment Loads and Stores", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1922, + 1929 + ] + }, + { + "chunk_id": "chunk_2df8a29a", + "text": "If an exception is detected partway through accessing a subsequent segment, `vl` is reduced to the index of that segment.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions > Vector Unit-Stride Segment Loads and Stores", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1922, + 1929 + ] + }, + { + "chunk_id": "chunk_b8a1275a", + "text": "These instructions may overwrite destination vector register group elements past the point at which a trap is reported or past the point at which vector length is trimmed.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions > Vector Unit-Stride Segment Loads and Stores", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1931, + 1934 + ] + }, + { + "chunk_id": "chunk_96b7541f", + "text": "Examples vsetvli a1, t0, e8, m1, ta, ma vlsseg3e8.v v4, (x5), x6 Load bytes at addresses x5+i*x6 into v4[i], and bytes at addresses x5+i*x6+1 into v5[i], and bytes at addresses x5+i*x6+2 into v6[i].", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions > Vector Constant-Stride Segment Loads and Stores", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1950, + 1954 + ] + }, + { + "chunk_id": "chunk_c220a78e", + "text": "Examples vsetvli a1, t0, e32, m1, ta, ma vssseg2e32.v v2, (x5), x6 Store words from v2[i] to address x5+i*x6 and words from v3[i] to address x5+i*x6+4 ----", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions > Vector Constant-Stride Segment Loads and Stores", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1956, + 1960 + ] + }, + { + "chunk_id": "chunk_d09e6f06", + "text": "Accesses to the fields within each segment can occur in any order, including the case where the byte stride is such that segments overlap in memory.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions > Vector Constant-Stride Segment Loads and Stores", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 1962, + 1965 + ] + }, + { + "chunk_id": "chunk_8b2ee621", + "text": "Vector indexed segment loads and stores move contiguous segments where each segment is located at an address given by adding the scalar base address in the `rs1` field to byte offsets in vector register `vs2`.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions > Vector Indexed Segment Loads and Stores", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 1969, + 1969 + ] + }, + { + "chunk_id": "chunk_a20753e3", + "text": "However, even for the ordered form, accesses to the fields within an individual segment are not ordered with respect to each other.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions > Vector Indexed Segment Loads and Stores", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 1969, + 1969 + ] + }, + { + "chunk_id": "chunk_e47e99bf", + "text": "The data vector register group has EEW=SEW, EMUL=LMUL, while the index vector register group has EEW encoded in the instruction with EMUL=(EEW/SEW)*LMUL.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions > Vector Indexed Segment Loads and Stores", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 1971, + 1976 + ] + }, + { + "chunk_id": "chunk_f2d896a8", + "text": "The EMUL * NFIELDS {le} 8 constraint applies to the data vector register group.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions > Vector Indexed Segment Loads and Stores", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 1971, + 1976 + ] + }, + { + "chunk_id": "chunk_911fa1e4", + "text": "Examples vsetvli a1, t0, e8, m1, ta, ma vluxseg3ei8.v v4, (x5), v3 Load bytes at addresses x5+v3[i] into v4[i], and bytes at addresses x5+v3[i]+1 into v5[i], and bytes at addresses x5+v3[i]+2 into v6[i].", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions > Vector Indexed Segment Loads and Stores", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1985, + 1989 + ] + }, + { + "chunk_id": "chunk_c069fe59", + "text": "Examples vsetvli a1, t0, e32, m1, ta, ma vsuxseg2ei32.v v2, (x5), v5 Store words from v2[i] to address x5+v5[i] and words from v3[i] to address x5+v5[i]+4 ----", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions > Vector Indexed Segment Loads and Stores", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1991, + 1995 + ] + }, + { + "chunk_id": "chunk_b2152f5d", + "text": "Format for Vector Load Whole Register Instructions under LOAD-FP major opcode", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2007, + 2007 + ] + }, + { + "chunk_id": "chunk_6c3cf57a", + "text": "Format for Vector Store Whole Register Instructions under STORE-FP major opcode", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2029, + 2029 + ] + }, + { + "chunk_id": "chunk_56aa9e41", + "text": "These instructions load and store whole vector register groups.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2051, + 2051 + ] + }, + { + "chunk_id": "chunk_6e6fc620", + "text": "Examples include compiler register spills, vector function calls where values are passed in vector registers, interrupt handlers, and OS context switches.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2053, + 2059 + ] + }, + { + "chunk_id": "chunk_cc5fddea", + "text": "Software can determine the number of bytes transferred by reading the `vlenb` register.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 2053, + 2059 + ] + }, + { + "chunk_id": "chunk_92a8fcae", + "text": "The load instructions have an EEW encoded in the `mew` and `width` fields following the pattern of regular unit-stride loads.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 2061, + 2063 + ] + }, + { + "chunk_id": "chunk_7275e9f5", + "text": "Hence, it would have sufficed to provide only EEW=8 variants.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2065, + 2071 + ] + }, + { + "chunk_id": "chunk_f9ab3ac5", + "text": "The full set of EEW variants is provided so that the encoded EEW can be used as a hint to indicate the destination register group will next be accessed with this EEW, which aids implementations that rearrange data internally.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 2065, + 2071 + ] + }, + { + "chunk_id": "chunk_37ef2fdd", + "text": "The vector whole register store instructions are encoded similar to unmasked unit-stride store of elements with EEW=8.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 2073, + 2074 + ] + }, + { + "chunk_id": "chunk_5fa18b40", + "text": "The `nf` field encodes how many vector registers to load and store using the NFIELDS encoding (Figure ).", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 2076, + 2085 + ] + }, + { + "chunk_id": "chunk_9543dc6e", + "text": "The encoded number of registers must be a power of 2 and the vector register numbers must be aligned as with a vector register group, otherwise the instruction encoding is reserved. NFIELDS indicates the number of vector registers to transfer, numbered successively after the base.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 2076, + 2085 + ] + }, + { + "chunk_id": "chunk_e143bcf6", + "text": "Only NFIELDS values of 1, 2, 4, 8 are supported, with other values reserved.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 2076, + 2085 + ] + }, + { + "chunk_id": "chunk_2dfc05c6", + "text": "When multiple registers are transferred, the lowest-numbered vector register is held in the lowest-numbered memory addresses and successive vector register numbers are placed contiguously in memory.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2076, + 2085 + ] + }, + { + "chunk_id": "chunk_b62cb4c2", + "text": "The instructions operate with an effective vector length, `evl`=NFIELDS*VLEN/EEW, regardless of current settings in `vtype` and `vl`.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 2087, + 2095 + ] + }, + { + "chunk_id": "chunk_1cd9fe2d", + "text": "The usual property that no elements are written if `vstart` {ge} `vl` does not apply to these instructions.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 2087, + 2095 + ] + }, + { + "chunk_id": "chunk_b71f8243", + "text": "Similarly, the property that the instructions are reserved if `vstart` exceeds the largest element index for the current `vtype` setting does not apply.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 2087, + 2095 + ] + }, + { + "chunk_id": "chunk_04b6214f", + "text": "Instead, the instructions are reserved if `vstart` {ge} `evl`.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 2087, + 2095 + ] + }, + { + "chunk_id": "chunk_230a10ee", + "text": "The instructions operate similarly to unmasked unit-stride load and store instructions, with the base address passed in the scalar `x` register specified by `rs1`.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2097, + 2099 + ] + }, + { + "chunk_id": "chunk_09018e24", + "text": "Implementations are allowed to raise a misaligned address exception on whole register loads and stores if the base address is not naturally aligned to the larger of the size of the encoded EEW in bytes (EEW/8) or the implementation's smallest supported SEW size in bytes (SEW~MIN~/8).", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 2101, + 2106 + ] + }, + { + "chunk_id": "chunk_eee684ac", + "text": "Some subset implementations might not support smaller SEW widths, so are allowed to report misaligned exceptions for the smallest supported SEW even if larger than encoded EEW.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 2108, + 2115 + ] + }, + { + "chunk_id": "chunk_e7bd38ad", + "text": "Software environments can mandate the minimum alignment requirements to support an ABI.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "confidence": "high", + "parameter_class": "SW_rule", + "parameter_type": "range", + "line_range": [ + 2108, + 2115 + ] + }, + { + "chunk_id": "chunk_440ed0bc", + "text": "---- Format of whole register load and store instructions. vl1r.v v3, (a0) Pseudoinstruction equal to vl1re8.v", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 2117, + 2119 + ] + }, + { + "chunk_id": "chunk_b7106e30", + "text": "vl1re8.v v3, (a0) Load v3 with VLEN/8 bytes held at address in a0 vl1re16.v v3, (a0) Load v3 with VLEN/16 halfwords held at address in a0 vl1re32.v v3, (a0) Load v3 with VLEN/32 words held at address in a0 vl1re64.v v3, (a0) Load v3 with VLEN/64 doublewords held at address in a0", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 2121, + 2124 + ] + }, + { + "chunk_id": "chunk_d81d3b25", + "text": "vl2r.v v2, (a0) Pseudoinstruction equal to vl2re8.v", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 2126, + 2126 + ] + }, + { + "chunk_id": "chunk_3cc8ce31", + "text": "vl2re8.v v2, (a0) Load v2-v3 with 2*VLEN/8 bytes from address in a0 vl2re16.v v2, (a0) Load v2-v3 with 2*VLEN/16 halfwords held at address in a0 vl2re32.v v2, (a0) Load v2-v3 with 2*VLEN/32 words held at address in a0 vl2re64.v v2, (a0) Load v2-v3 with 2*VLEN/64 doublewords held at address in a0", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 2128, + 2131 + ] + }, + { + "chunk_id": "chunk_29f2b99d", + "text": "vl4r.v v4, (a0) Pseudoinstruction equal to vl4re8.v", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 2133, + 2133 + ] + }, + { + "chunk_id": "chunk_c7103d4e", + "text": "vl4re8.v v4, (a0) Load v4-v7 with 4*VLEN/8 bytes from address in a0 vl4re16.v v4, (a0) vl4re32.v v4, (a0) vl4re64.v v4, (a0)", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 2135, + 2138 + ] + }, + { + "chunk_id": "chunk_03a079dd", + "text": "vl8r.v v8, (a0) Pseudoinstruction equal to vl8re8.v", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 2140, + 2140 + ] + }, + { + "chunk_id": "chunk_50580c08", + "text": "vl8re8.v v8, (a0) Load v8-v15 with 8*VLEN/8 bytes from address in a0 vl8re16.v v8, (a0) vl8re32.v v8, (a0) vl8re64.v v8, (a0)", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 2142, + 2145 + ] + }, + { + "chunk_id": "chunk_f22ab8a6", + "text": "vs1r.v v3, (a1) Store v3 to address in a1 vs2r.v v2, (a1) Store v2-v3 to address in a1 vs4r.v v4, (a1) Store v4-v7 to address in a1 vs8r.v v8, (a1) Store v8-v15 to address in a1 ----", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2147, + 2151 + ] + }, + { + "chunk_id": "chunk_bcca5b18", + "text": "The primary purpose would be to inform the microarchitecture that the data will be used as a mask.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2153, + 2168 + ] + }, + { + "chunk_id": "chunk_b8d988a3", + "text": "The same effect can be achieved with the following code sequence, whose cost is at most four instructions.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "range", + "line_range": [ + 2153, + 2168 + ] + }, + { + "chunk_id": "chunk_74df8f5e", + "text": "Of these, the first could likely be removed as `vl` is often already in a scalar register, and the last might already be present if the following vector instruction needs a new SEW/LMUL.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 2153, + 2168 + ] + }, + { + "chunk_id": "chunk_0e13627a", + "text": "If an element accessed by a vector memory instruction is not naturally aligned to the size of the element, either the element is transferred successfully or an address-misaligned exception is raised on that element.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Memory Alignment Constraints", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 2173, + 2177 + ] + }, + { + "chunk_id": "chunk_275416b5", + "text": "If the Ztso extension is implemented, vector memory instructions additionally follow RVTSO at the instruction level.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Memory Consistency Model", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2198, + 2199 + ] + }, + { + "chunk_id": "chunk_f9a58a58", + "text": "Instructions affected by the vector length register `vl` have a control dependency on `vl`, rather than a data dependency.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Memory Consistency Model", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 2215, + 2220 + ] + }, + { + "chunk_id": "chunk_15feb995", + "text": "The three-bit `funct3` field is used to define sub-categories of vector instructions.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 2231, + 2233 + ] + }, + { + "chunk_id": "chunk_a8f0b3e0", + "text": "The `funct3` field encodes the operand type and source locations.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Vector Arithmetic Instruction encoding", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 2240, + 2240 + ] + }, + { + "chunk_id": "chunk_72d7eddd", + "text": "All vector floating-point operations use the dynamic rounding mode in the `frm` register.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Vector Arithmetic Instruction encoding", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 2263, + 2267 + ] + }, + { + "chunk_id": "chunk_6ea15001", + "text": "Use of the `frm` field when it contains an invalid rounding mode by any vector floating-point instruction--even those that do not depend on the rounding mode, or when `vl`=0, or when `vstart` {ge} `vl`--is reserved.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Vector Arithmetic Instruction encoding", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 2263, + 2267 + ] + }, + { + "chunk_id": "chunk_2da14e29", + "text": "Implementations can make all vector FP instructions report exceptions when the rounding mode is invalid to simplify control logic.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Vector Arithmetic Instruction encoding", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2269, + 2272 + ] + }, + { + "chunk_id": "chunk_e9115c3b", + "text": "For integer operations, the scalar can be a 5-bit immediate, `imm[4:0]`, encoded in the `rs1` field.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Vector Arithmetic Instruction encoding", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 2282, + 2283 + ] + }, + { + "chunk_id": "chunk_c80e0890", + "text": "The value is sign-extended to SEW bits, unless otherwise specified.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Vector Arithmetic Instruction encoding", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 2282, + 2283 + ] + }, + { + "chunk_id": "chunk_f048017a", + "text": "If XLEN>SEW, the least-significant SEW bits of the `x` register are used, unless otherwise specified.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Vector Arithmetic Instruction encoding", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2285, + 2287 + ] + }, + { + "chunk_id": "chunk_e1765f80", + "text": "If XLEN \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Vector Arithmetic Instruction encoding", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 2285, + 2287 + ] + }, + { + "chunk_id": "chunk_7f474328", + "text": "If FLEN > SEW, the value in the `f` registers is checked for a valid NaN-boxed value, in which case the least-significant SEW bits of the `f` register are used, else the canonical NaN value is used.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Vector Arithmetic Instruction encoding", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2289, + 2295 + ] + }, + { + "chunk_id": "chunk_47551ea0", + "text": "Vector instructions where any floating-point vector operand's EEW is not a supported floating-point type width (which includes when FLEN < SEW) are reserved.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Vector Arithmetic Instruction encoding", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2289, + 2295 + ] + }, + { + "chunk_id": "chunk_05ffec25", + "text": "When adding a vector extension to the Zfinx/Zdinx/Zhinx extensions, floating-point scalar arguments are taken from the `x` registers.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Vector Arithmetic Instruction encoding", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2300, + 2304 + ] + }, + { + "chunk_id": "chunk_827ca6eb", + "text": "Vector arithmetic instructions are masked under control of the `vm` field.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Vector Arithmetic Instruction encoding", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 2306, + 2307 + ] + }, + { + "chunk_id": "chunk_269534aa", + "text": "This arrangement retains the existing encoding conventions that instructions that read only one scalar register, read it from `rs1`, and that 5-bit immediates are sourced from the `rs1` field.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Vector Arithmetic Instruction encoding", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 2321, + 2325 + ] + }, + { + "chunk_id": "chunk_022ea3a4", + "text": "Widening instruction encodings must follow the constraints in .", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Widening Vector Arithmetic Instructions", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 2384, + 2385 + ] + }, + { + "chunk_id": "chunk_ae8bb168", + "text": "The choice here is motivated by the belief the chosen approach will require fewer `vtype` changes.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Narrowing Vector Arithmetic Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 2397, + 2400 + ] + }, + { + "chunk_id": "chunk_1ccea559", + "text": "Narrowing instruction encodings must follow the constraints in .", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Narrowing Vector Arithmetic Instructions", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 2419, + 2420 + ] + }, + { + "chunk_id": "chunk_13267868", + "text": "Unless otherwise stated, integer operations wrap around on overflow.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2425, + 2426 + ] + }, + { + "chunk_id": "chunk_627da66f", + "text": "The widening add/subtract instructions are provided in both signed and unsigned variants, depending on whether the narrower source operands are first sign- or zero-extended before forming the double-width sum.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Widening Integer Add/Subtract", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 2454, + 2456 + ] + }, + { + "chunk_id": "chunk_dfd0c833", + "text": "If the source EEW is not a supported width, or source EMUL would be below the minimum legal LMUL, the instruction encoding is reserved.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Extension", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "range", + "line_range": [ + 2506, + 2507 + ] + }, + { + "chunk_id": "chunk_93216de6", + "text": "To avoid having to provide the cross-product of the number of vector load instructions by the number of data types (byte, word, halfword, and also signed/unsigned variants), we instead add explicit extension instructions that can be used if an appropriate widening arithmetic instruction is not available.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Extension", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2509, + 2517 + ] + }, + { + "chunk_id": "chunk_ae262851", + "text": "For each operation (add or subtract), two instructions are provided: one to provide the result (SEW width), and the second to generate the carry output (single bit encoded as a mask boolean).", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 2521, + 2525 + ] + }, + { + "chunk_id": "chunk_827a9f43", + "text": "Due to encoding constraints, the carry input must come from the implicit `v0` register, but carry outputs can be written to any vector register that respects the source/destination overlap restrictions.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 2527, + 2531 + ] + }, + { + "chunk_id": "chunk_ece761f2", + "text": "These instructions are encoded as masked instructions (`vm=0`), but they operate on and write back all body elements.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 2533, + 2537 + ] + }, + { + "chunk_id": "chunk_1b1e3f78", + "text": "`vmadc` and `vmsbc` add or subtract the source operands, optionally add the carry-in or subtract the borrow-in if masked (`vm=0`), and write the resulting carry-out or borrow-out back to mask register `vd`.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2539, + 2545 + ] + }, + { + "chunk_id": "chunk_895a0ebc", + "text": "If unmasked (`vm=1`), there is no carry-in or borrow-in.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2539, + 2545 + ] + }, + { + "chunk_id": "chunk_25b97861", + "text": "These instructions operate on and write back all body elements, even if masked.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2539, + 2545 + ] + }, + { + "chunk_id": "chunk_fed93517", + "text": "For `vadc` and `vsbc`, the instruction encoding is reserved if the destination vector register is `v0`.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 2622, + 2623 + ] + }, + { + "chunk_id": "chunk_4a30edc6", + "text": "The data to be shifted is in the vector register group specified by `vs2` and the shift amount value can come from a vector register group `vs1`, a scalar integer register `rs1`, or a zero-extended 5-bit immediate.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Single-Width Shift Instructions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 2652, + 2659 + ] + }, + { + "chunk_id": "chunk_a58b5b81", + "text": "The narrowing right shifts extract a smaller field from a wider operand and have both zero-extending (`srl`) and sign-extending (`sra`) forms.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Narrowing Integer Right Shift Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 2678, + 2684 + ] + }, + { + "chunk_id": "chunk_f4b1ca64", + "text": "The shift amount can come from a vector register group, or a scalar `x` register, or a zero-extended 5-bit immediate.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Narrowing Integer Right Shift Instructions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 2678, + 2684 + ] + }, + { + "chunk_id": "chunk_17dbd262", + "text": "The destination mask vector register may be the same as the source vector mask register (`v0`).", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Compare Instructions", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 2707, + 2712 + ] + }, + { + "chunk_id": "chunk_49c7bae8", + "text": "---- Set if equal vmseq.vv vd, vs2, vs1, vm Vector-vector vmseq.vx vd, vs2, rs1, vm vector-scalar vmseq.vi vd, vs2, imm, vm vector-immediate", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Compare Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2714, + 2718 + ] + }, + { + "chunk_id": "chunk_a7f730f8", + "text": "Set if not equal vmsne.vv vd, vs2, vs1, vm Vector-vector vmsne.vx vd, vs2, rs1, vm vector-scalar vmsne.vi vd, vs2, imm, vm vector-immediate", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Compare Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "range", + "line_range": [ + 2720, + 2723 + ] + }, + { + "chunk_id": "chunk_aa36e0e1", + "text": "Set if less than, unsigned vmsltu.vv vd, vs2, vs1, vm Vector-vector vmsltu.vx vd, vs2, rs1, vm Vector-scalar", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Compare Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "range", + "line_range": [ + 2725, + 2727 + ] + }, + { + "chunk_id": "chunk_7dbbb399", + "text": "Set if less than, signed vmslt.vv vd, vs2, vs1, vm Vector-vector vmslt.vx vd, vs2, rs1, vm vector-scalar", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Compare Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "range", + "line_range": [ + 2729, + 2731 + ] + }, + { + "chunk_id": "chunk_6d44b7bc", + "text": "Set if less than or equal, unsigned vmsleu.vv vd, vs2, vs1, vm Vector-vector vmsleu.vx vd, vs2, rs1, vm vector-scalar vmsleu.vi vd, vs2, imm, vm Vector-immediate", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Compare Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "range", + "line_range": [ + 2733, + 2736 + ] + }, + { + "chunk_id": "chunk_fac29bdd", + "text": "Set if less than or equal, signed vmsle.vv vd, vs2, vs1, vm Vector-vector vmsle.vx vd, vs2, rs1, vm vector-scalar vmsle.vi vd, vs2, imm, vm vector-immediate", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Compare Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "range", + "line_range": [ + 2738, + 2741 + ] + }, + { + "chunk_id": "chunk_b5e1e886", + "text": "Set if greater than, unsigned vmsgtu.vx vd, vs2, rs1, vm Vector-scalar vmsgtu.vi vd, vs2, imm, vm Vector-immediate", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Compare Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "range", + "line_range": [ + 2743, + 2745 + ] + }, + { + "chunk_id": "chunk_c12a8c02", + "text": "Set if greater than, signed vmsgt.vx vd, vs2, rs1, vm Vector-scalar vmsgt.vi vd, vs2, imm, vm Vector-immediate", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Compare Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "range", + "line_range": [ + 2747, + 2749 + ] + }, + { + "chunk_id": "chunk_79dce25b", + "text": "Following two instructions are not provided directly Set if greater than or equal, unsigned vmsgeu.vx vd, vs2, rs1, vm Vector-scalar Set if greater than or equal, signed vmsge.vx vd, vs2, rs1, vm Vector-scalar ----", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Compare Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "range", + "line_range": [ + 2751, + 2756 + ] + }, + { + "chunk_id": "chunk_f4690bd1", + "text": "The `vmsge{u}.vx` operation can be synthesized by reducing the value of `x` by 1 and using the `vmsgt{u}.vx` instruction, when it is known that this will not underflow the representation in `x`.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Compare Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 2823, + 2825 + ] + }, + { + "chunk_id": "chunk_be344f25", + "text": "The vt argument to the pseudoinstruction must name a temporary vector register that is not same as vd and which will be clobbered by the pseudoinstruction ----", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Compare Instructions", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 2860, + 2862 + ] + }, + { + "chunk_id": "chunk_191a80cd", + "text": "---- (a < b) && (b < c) in two instructions when mask-undisturbed vmslt.vv v0, va, vb All body elements written vmslt.vv v0, vb, vc, v0.t Only update at set mask ----", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Compare Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2866, + 2870 + ] + }, + { + "chunk_id": "chunk_a4b05703", + "text": "---- Signed multiply, returning low bits of product vmul.vv vd, vs2, vs1, vm Vector-vector vmul.vx vd, vs2, rs1, vm vector-scalar", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Single-Width Integer Multiply Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2907, + 2910 + ] + }, + { + "chunk_id": "chunk_1a1364b0", + "text": "Signed multiply, returning high bits of product vmulh.vv vd, vs2, vs1, vm Vector-vector vmulh.vx vd, vs2, rs1, vm vector-scalar", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Single-Width Integer Multiply Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2912, + 2914 + ] + }, + { + "chunk_id": "chunk_2c5d6465", + "text": "Unsigned multiply, returning high bits of product vmulhu.vv vd, vs2, vs1, vm Vector-vector vmulhu.vx vd, vs2, rs1, vm vector-scalar", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Single-Width Integer Multiply Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2916, + 2918 + ] + }, + { + "chunk_id": "chunk_96e754ef", + "text": "Signed(vs2)-Unsigned multiply, returning high bits of product vmulhsu.vv vd, vs2, vs1, vm Vector-vector vmulhsu.vx vd, vs2, rs1, vm vector-scalar ----", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Single-Width Integer Multiply Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2920, + 2923 + ] + }, + { + "chunk_id": "chunk_7e7bed85", + "text": "The `vmerge` instructions are encoded as masked instructions (`vm=0`).", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Merge Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 3051, + 3059 + ] + }, + { + "chunk_id": "chunk_c65f6dea", + "text": "The second operand is a vector register group specified by `vs1` or a scalar `x` register specified by `rs1` or a 5-bit sign-extended immediate.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Merge Instructions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 3051, + 3059 + ] + }, + { + "chunk_id": "chunk_46b5e528", + "text": "These instructions are encoded as unmasked instructions (`vm=1`).", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Move Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 3069, + 3076 + ] + }, + { + "chunk_id": "chunk_fe2a2de3", + "text": "The first operand specifier (`vs2`) must contain `v0`, and any other vector register number in `vs2` is reserved.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Move Instructions", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 3069, + 3076 + ] + }, + { + "chunk_id": "chunk_b46cf7d2", + "text": "Implementations that do not internally reorganize data can dynamically elide this instruction (aside from resetting `vstart` to 0).", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Move Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 3094, + 3097 + ] + }, + { + "chunk_id": "chunk_2c810be6", + "text": "The averaging add and subtract instructions right shift the result by one bit and round off the result according to the setting in `vxrm`.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions > Vector Single-Width Averaging Add and Subtract", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 3151, + 3156 + ] + }, + { + "chunk_id": "chunk_eadefd5b", + "text": "The signed fractional multiply instruction produces a 2*SEW product of the two SEW inputs, then shifts the result right by SEW-1 bits, rounding these bits according to `vxrm`, then saturates the result to fit into SEW bits.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions > Vector Single-Width Fractional Multiply with Rounding and Saturation", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 3185, + 3189 + ] + }, + { + "chunk_id": "chunk_4527fab3", + "text": "If the result causes saturation, the `vxsat` bit is set.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions > Vector Single-Width Fractional Multiply with Rounding and Saturation", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 3185, + 3189 + ] + }, + { + "chunk_id": "chunk_4b449aad", + "text": "---- Signed saturating and rounding fractional multiply See vxrm description for rounding calculation vsmul.vv vd, vs2, vs1, vm vd[i] = clip(roundoffsigned(vs2[i]*vs1[i], SEW-1)) vsmul.vx vd, vs2, rs1, vm vd[i] = clip(roundoffsigned(vs2[i]*x[rs1], SEW-1)) ----", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions > Vector Single-Width Fractional Multiply with Rounding and Saturation", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 3191, + 3196 + ] + }, + { + "chunk_id": "chunk_1e388db4", + "text": "When multiplying two N-bit signed numbers, the largest magnitude is obtained for -2^N-1^ * -2^N-1^ producing a result +2^2N-2^, which has a single (zero) sign bit when held in 2N bits.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions > Vector Single-Width Fractional Multiply with Rounding and Saturation", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 3198, + 3204 + ] + }, + { + "chunk_id": "chunk_15296079", + "text": "All other products have two sign bits in 2N bits.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions > Vector Single-Width Fractional Multiply with Rounding and Saturation", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 3198, + 3204 + ] + }, + { + "chunk_id": "chunk_e03e1964", + "text": "These instructions shift the input value right, and round off the shifted out bits according to `vxrm`.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions > Vector Single-Width Scaling Shift Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 3214, + 3220 + ] + }, + { + "chunk_id": "chunk_94960edf", + "text": "The data to be shifted is in the vector register group specified by `vs2` and the shift amount value can come from a vector register group `vs1`, a scalar integer register `rs1`, or a zero-extended 5-bit immediate.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions > Vector Single-Width Scaling Shift Instructions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 3214, + 3220 + ] + }, + { + "chunk_id": "chunk_aac2a72a", + "text": "The scaling shift amount value can come from a vector register group `vs1`, a scalar integer register `rs1`, or a zero-extended 5-bit immediate.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions > Vector Narrowing Fixed-Point Clip Instructions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 3236, + 3250 + ] + }, + { + "chunk_id": "chunk_b3467f3c", + "text": "For `vnclipu`/`vnclip`, the rounding mode is specified in the `vxrm` CSR.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions > Vector Narrowing Fixed-Point Clip Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 3258, + 3260 + ] + }, + { + "chunk_id": "chunk_e0a0cf16", + "text": "Rounding occurs around the least-significant bit of the destination and before saturation.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions > Vector Narrowing Fixed-Point Clip Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 3258, + 3260 + ] + }, + { + "chunk_id": "chunk_05595617", + "text": "For `vnclipu`, the shifted rounded source value is treated as an unsigned integer and saturates if the result would overflow the destination viewed as an unsigned integer.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions > Vector Narrowing Fixed-Point Clip Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 3262, + 3264 + ] + }, + { + "chunk_id": "chunk_df860a3b", + "text": "For `vnclip`, the shifted rounded source value is treated as a signed integer and saturates if the result would overflow the destination viewed as a signed integer.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions > Vector Narrowing Fixed-Point Clip Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 3274, + 3276 + ] + }, + { + "chunk_id": "chunk_e3f52391", + "text": "If any destination element is saturated, the `vxsat` bit is set in the `vxsat` register.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions > Vector Narrowing Fixed-Point Clip Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 3278, + 3279 + ] + }, + { + "chunk_id": "chunk_769d3963", + "text": "If the EEW of a vector floating-point operand does not correspond to a supported IEEE floating-point type, the instruction encoding is reserved.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 3284, + 3287 + ] + }, + { + "chunk_id": "chunk_24ac14f4", + "text": "The current set of extensions include support for 32-bit and 64-bit floating-point values.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 3289, + 3294 + ] + }, + { + "chunk_id": "chunk_1f6d1e65", + "text": "When 16-bit and 128-bit element widths are added, they will be also be treated as IEEE 754-2008-compatible values.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 3289, + 3294 + ] + }, + { + "chunk_id": "chunk_eb55f3bc", + "text": "Other floating-point formats may be supported in future extensions.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 3289, + 3294 + ] + }, + { + "chunk_id": "chunk_61306eba", + "text": "If the floating-point unit status field `mstatus.FS` is `Off` then any attempt to execute a vector floating-point instruction will raise an illegal-instruction exception.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 3304, + 3308 + ] + }, + { + "chunk_id": "chunk_6d3a5562", + "text": "Any vector floating-point instruction that modifies any floating-point extension state (i.e., floating-point CSRs or `f` registers) must set `mstatus.FS` to `Dirty`.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 3304, + 3308 + ] + }, + { + "chunk_id": "chunk_905348a0", + "text": "If the hypervisor extension is implemented and V=1, the `vsstatus.FS` field is additionally in effect for vector floating-point instructions.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 3310, + 3316 + ] + }, + { + "chunk_id": "chunk_f4a00fe3", + "text": "If `vsstatus.FS` or `mstatus.FS` is `Off` then any attempt to execute a vector floating-point instruction will raise an illegal-instruction exception.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 3310, + 3316 + ] + }, + { + "chunk_id": "chunk_e6fa493c", + "text": "Any vector floating-point instruction that modifies any floating-point extension state (i.e., floating-point CSRs or `f` registers) must set both `mstatus.FS` and `vsstatus.FS` to `Dirty`.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 3310, + 3316 + ] + }, + { + "chunk_id": "chunk_d924facc", + "text": "A vector floating-point exception at any active floating-point element sets the standard FP exception flags in the `fflags` register.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Exception Flags", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 3326, + 3328 + ] + }, + { + "chunk_id": "chunk_643ef9ef", + "text": "Inactive elements do not set FP exception flags.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Exception Flags", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 3326, + 3328 + ] + }, + { + "chunk_id": "chunk_9d7fc124", + "text": "---- Floating-point reciprocal square-root estimate to 7 bits. vfrsqrt7.v vd, vs2, vm ----", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Square-Root Estimate Instruction", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 3466, + 3469 + ] + }, + { + "chunk_id": "chunk_79d007c2", + "text": "This is a unary vector-vector instruction that returns an estimate of 1/sqrt(x) accurate to 7 bits.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Square-Root Estimate Instruction", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 3471, + 3472 + ] + }, + { + "chunk_id": "chunk_0aac6040", + "text": "[cols=\"1,1,1\"] | | Input | Output | Exceptions raised", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Square-Root Estimate Instruction", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 3482, + 3485 + ] + }, + { + "chunk_id": "chunk_8d4dc33a", + "text": "For the non-exceptional cases, the low bit of the exponent and the six high bits of significand (after the leading one) are concatenated and used to address the following table.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Square-Root Estimate Instruction", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 3500, + 3508 + ] + }, + { + "chunk_id": "chunk_553ab545", + "text": "The output of the table becomes the seven high bits of the result significand (after the leading one); the remainder of the result significand is zero.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Square-Root Estimate Instruction", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 3500, + 3508 + ] + }, + { + "chunk_id": "chunk_afbaa4d7", + "text": "Let the normalized input exponent be equal to the input exponent if the input is normal, or 0 minus the number of leading zeros in the significand otherwise.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Square-Root Estimate Instruction", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "range", + "line_range": [ + 3510, + 3518 + ] + }, + { + "chunk_id": "chunk_83cba425", + "text": "If the input is subnormal, the normalized input significand is given by shifting the input significand left by 1 minus the normalized input exponent, discarding the leading 1 bit.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Square-Root Estimate Instruction", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 3510, + 3518 + ] + }, + { + "chunk_id": "chunk_108509ab", + "text": "The following table gives the seven MSBs of the output significand as a function of the LSB of the normalized input exponent and the six MSBs of the normalized input significand; the other bits of the output significand are zero.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Square-Root Estimate Instruction", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 3520, + 3522 + ] + }, + { + "chunk_id": "chunk_24af5065", + "text": "---- Floating-point reciprocal estimate to 7 bits. vfrec7.v vd, vs2, vm ----", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Estimate Instruction", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 3535, + 3538 + ] + }, + { + "chunk_id": "chunk_a4e86fdb", + "text": "This is a unary vector-vector instruction that returns an estimate of 1/x accurate to 7 bits.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Estimate Instruction", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 3545, + 3546 + ] + }, + { + "chunk_id": "chunk_de9bbbb6", + "text": "[cols=\"1,1,1,1\"] | | Input (x) | Rounding Mode | Output (y {approx} 1/x) | Exceptions raised", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Estimate Instruction", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 3551, + 3554 + ] + }, + { + "chunk_id": "chunk_a0541d24", + "text": "Normal inputs with magnitude at least 2^B-1^ produce subnormal outputs; other normal inputs produce normal outputs.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Estimate Instruction", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 3578, + 3581 + ] + }, + { + "chunk_id": "chunk_d159b4fa", + "text": "For the non-exceptional cases, the seven high bits of significand (after the leading one) are used to address the following table.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Estimate Instruction", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 3586, + 3593 + ] + }, + { + "chunk_id": "chunk_3c51b7e9", + "text": "The output of the table becomes the seven high bits of the result significand (after the leading one); the remainder of the result significand is zero.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Estimate Instruction", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 3586, + 3593 + ] + }, + { + "chunk_id": "chunk_a96ef144", + "text": "Let the normalized input exponent be equal to the input exponent if the input is normal, or 0 minus the number of leading zeros in the significand otherwise.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Estimate Instruction", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "range", + "line_range": [ + 3595, + 3601 + ] + }, + { + "chunk_id": "chunk_02fa3d4e", + "text": "If the normalized output exponent is outside the range [-1, 2*B], the result corresponds to one of the exceptional cases in the table above.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Estimate Instruction", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 3595, + 3601 + ] + }, + { + "chunk_id": "chunk_e40d65c6", + "text": "If the input is subnormal, the normalized input significand is given by shifting the input significand left by 1 minus the normalized input exponent, discarding the leading 1 bit.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Estimate Instruction", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 3603, + 3609 + ] + }, + { + "chunk_id": "chunk_a55098cb", + "text": "The following table gives the seven MSBs of the normalized output significand as a function of the seven MSBs of the normalized input significand; the other bits of the normalized output significand are zero.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Estimate Instruction", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 3603, + 3609 + ] + }, + { + "chunk_id": "chunk_4ec5b218", + "text": "The result takes all bits except the sign bit from the vector `vs2` operands.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Sign-Injection Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 3647, + 3648 + ] + }, + { + "chunk_id": "chunk_b174182e", + "text": "The destination mask vector register may be the same as the source vector mask register (`v0`).", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Compare Instructions", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 3672, + 3678 + ] + }, + { + "chunk_id": "chunk_04926b9a", + "text": "When the comparand is a non-NaN constant, the middle two instructions can be omitted.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Compare Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 3733, + 3736 + ] + }, + { + "chunk_id": "chunk_1e049c6e", + "text": "The 10-bit mask produced by this instruction is placed in the least-significant bits of the result elements.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Classify Instruction", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 3761, + 3765 + ] + }, + { + "chunk_id": "chunk_a71846e9", + "text": "The upper (SEW-10) bits of the result are filled with zeros.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Classify Instruction", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 3761, + 3765 + ] + }, + { + "chunk_id": "chunk_4b20124c", + "text": "A vector-scalar floating-point merge instruction is provided, which operates on all body elements from `vstart` up to the current vector length in `vl` regardless of mask value.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Merge Instruction", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 3769, + 3771 + ] + }, + { + "chunk_id": "chunk_9bf11c90", + "text": "The `vfmerge.vfm` instruction is encoded as a masked instruction (`vm=0`).", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Merge Instruction", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 3773, + 3776 + ] + }, + { + "chunk_id": "chunk_5c64c8e1", + "text": "This instruction is encoded as an unmasked instruction (`vm=1`).", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Move Instruction", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 3784, + 3789 + ] + }, + { + "chunk_id": "chunk_cd9b11dc", + "text": "The instruction must have the `vs2` field set to `v0`, with all other values for `vs2` reserved.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Move Instruction", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 3784, + 3789 + ] + }, + { + "chunk_id": "chunk_53a65f29", + "text": "The conversions follow the same rules on exceptional conditions as the scalar conversion instructions.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Single-Width Floating-Point/Integer Type-Convert Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 3815, + 3818 + ] + }, + { + "chunk_id": "chunk_2ba5461c", + "text": "The conversions use the dynamic rounding mode in `frm`, except for the `rtz` variants, which round towards zero.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Single-Width Floating-Point/Integer Type-Convert Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 3815, + 3818 + ] + }, + { + "chunk_id": "chunk_70059d11", + "text": "Results are equivalently rounded and the same exception flags are raised if all but the last halving step use round-towards-odd (`vfncvt.rod.f.f.w`).", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Narrowing Floating-Point/Integer Type-Convert Instructions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 3879, + 3884 + ] + }, + { + "chunk_id": "chunk_7a7e77f3", + "text": "Only the final step should use the desired rounding mode.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Narrowing Floating-Point/Integer Type-Convert Instructions", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 3879, + 3884 + ] + }, + { + "chunk_id": "chunk_cb9088b2", + "text": "The other elements in the destination vector register ( 0 < index < VLEN/SEW) are considered the tail and are managed with the current tail agnostic/undisturbed policy.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 3912, + 3914 + ] + }, + { + "chunk_id": "chunk_691bc124", + "text": "For the uncommon case that the source and destination scalar operand are in different vector registers, this instruction will not copy the source into the destination when `vl`=0.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 3919, + 3930 + ] + }, + { + "chunk_id": "chunk_77bae2f3", + "text": "However, it is expected that in most of these cases it will be statically known that `vl` is not zero.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 3919, + 3930 + ] + }, + { + "chunk_id": "chunk_29701136", + "text": "Traps on vector reduction instructions are always reported with a `vstart` of 0.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 3932, + 3934 + ] + }, + { + "chunk_id": "chunk_22050f67", + "text": "Vector reduction operations raise an illegal-instruction exception if `vstart` is non-zero.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 3932, + 3934 + ] + }, + { + "chunk_id": "chunk_290197fb", + "text": "The `vfredosum` instruction must sum the floating-point values in element order, starting with the scalar in `vs1[0]`--that is, it performs the computation:", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations > Vector Single-Width Floating-Point Reduction Instructions > Vector Ordered Single-Width Floating-Point Sum Reduction", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 3994, + 3996 + ] + }, + { + "chunk_id": "chunk_07299328", + "text": "When the operation is masked (`vm=0`), the masked-off elements do not affect the result or the exception flags.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations > Vector Single-Width Floating-Point Reduction Instructions > Vector Ordered Single-Width Floating-Point Sum Reduction", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 4008, + 4009 + ] + }, + { + "chunk_id": "chunk_1cd74e7b", + "text": "If no elements are active, no additions are performed, so the scalar in `vs1[0]` is simply copied to the destination register, without canonicalizing NaN values and without setting any exception flags.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations > Vector Single-Width Floating-Point Reduction Instructions > Vector Ordered Single-Width Floating-Point Sum Reduction", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 4011, + 4015 + ] + }, + { + "chunk_id": "chunk_741ba3ad", + "text": "This behavior preserves the handling of NaNs, exceptions, and rounding when auto-vectorizing a scalar summation loop.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations > Vector Single-Width Floating-Point Reduction Instructions > Vector Ordered Single-Width Floating-Point Sum Reduction", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 4011, + 4015 + ] + }, + { + "chunk_id": "chunk_e42f3fa3", + "text": "The implementation must produce a result equivalent to a reduction tree composed of binary operator nodes, with the inputs being elements from the source vector register group (`vs2`) and the source scalar value (`vs1[0]`).", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations > Vector Single-Width Floating-Point Reduction Instructions > Vector Unordered Single-Width Floating-Point Sum Reduction", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 4022, + 4042 + ] + }, + { + "chunk_id": "chunk_81a246ff", + "text": "Each operator first computes an exact sum as a RISC-V scalar floating-point addition with infinite exponent range and precision, then converts this exact sum to a floating-point format with range and precision each at least as great as the element floating-point format indicated by SEW, rounding using the currently active floating-point dynamic rounding mode and raising exception flags as necessary. A different floating-point range and precision may be chosen for the result of each operator. A node where one input is derived only from elements masked-off or beyond the active vector length may either treat that input as the additive identity of the appropriate EEW or simply copy the other input to its output.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations > Vector Single-Width Floating-Point Reduction Instructions > Vector Unordered Single-Width Floating-Point Sum Reduction", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 4022, + 4042 + ] + }, + { + "chunk_id": "chunk_f71b5fc5", + "text": "The additive identity is +0.0 when rounding down (towards -{inf}) or -0.0 for all other rounding modes.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations > Vector Single-Width Floating-Point Reduction Instructions > Vector Unordered Single-Width Floating-Point Sum Reduction", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 4044, + 4045 + ] + }, + { + "chunk_id": "chunk_84b5f542", + "text": "The reduction tree structure must be deterministic for a given value in `vtype` and `vl`.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations > Vector Single-Width Floating-Point Reduction Instructions > Vector Unordered Single-Width Floating-Point Sum Reduction", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 4047, + 4048 + ] + }, + { + "chunk_id": "chunk_b30184dc", + "text": "In particular, if no elements are active and the scalar input is NaN, implementations are permitted to canonicalize the NaN and, if the NaN is signaling, set the invalid exception flag.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations > Vector Single-Width Floating-Point Reduction Instructions > Vector Unordered Single-Width Floating-Point Sum Reduction", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 4050, + 4056 + ] + }, + { + "chunk_id": "chunk_ce0d4f21", + "text": "Implementations are alternatively permitted to pass through the original NaN and set no exception flags, as with `vfredosum`.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations > Vector Single-Width Floating-Point Reduction Instructions > Vector Unordered Single-Width Floating-Point Sum Reduction", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 4050, + 4056 + ] + }, + { + "chunk_id": "chunk_0d378927", + "text": "If no elements are active, the scalar in `vs1[0]` is simply copied to the destination register, without canonicalizing NaN values and without setting any exception flags.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations > Vector Single-Width Floating-Point Reduction Instructions > Vector Single-Width Floating-Point Max and Min Reductions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 4071, + 4073 + ] + }, + { + "chunk_id": "chunk_a14b951e", + "text": "Widening forms of the sum reductions are provided that read and write a double-width reduction result.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations > Vector Widening Floating-Point Reduction Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 4078, + 4079 + ] + }, + { + "chunk_id": "chunk_7b272c87", + "text": "Vector mask-register logical operations operate on mask registers.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Mask-Register Logical Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 4105, + 4110 + ] + }, + { + "chunk_id": "chunk_9694aaed", + "text": "Each element in a mask register is a single bit, so these instructions all operate on single vector registers regardless of the setting of the `vlmul` field in `vtype`.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Mask-Register Logical Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 4105, + 4110 + ] + }, + { + "chunk_id": "chunk_6bddb64b", + "text": "They do not change the value of `vlmul`.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Mask-Register Logical Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 4105, + 4110 + ] + }, + { + "chunk_id": "chunk_2b1c792e", + "text": "The destination vector register may be the same as either source vector register.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Mask-Register Logical Instructions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 4105, + 4110 + ] + }, + { + "chunk_id": "chunk_17e270ca", + "text": "As with other vector instructions, the elements with indices less than `vstart` are unchanged, and `vstart` is reset to zero after execution.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Mask-Register Logical Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 4112, + 4117 + ] + }, + { + "chunk_id": "chunk_22f53182", + "text": "Vector mask logical instructions are always unmasked, so there are no inactive elements, and the encodings with `vm=0` are reserved.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Mask-Register Logical Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 4112, + 4117 + ] + }, + { + "chunk_id": "chunk_182130d3", + "text": "Mask elements past `vl`, the tail elements, are always updated with a tail-agnostic policy.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Mask-Register Logical Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 4112, + 4117 + ] + }, + { + "chunk_id": "chunk_da4b8205", + "text": "---- vmand.mm vd, vs2, vs1 vd.mask[i] = vs2.mask[i] && vs1.mask[i] vmnand.mm vd, vs2, vs1 vd.mask[i] = !(vs2.mask[i] && vs1.mask[i]) vmandn.mm vd, vs2, vs1 vd.mask[i] = vs2.mask[i] && !vs1.mask[i] vmxor.mm vd, vs2, vs1 vd.mask[i] = vs2.mask[i] ^^ vs1.mask[i] vmor.mm vd, vs2, vs1 vd.mask[i] = vs2.mask[i] || vs1.mask[i] vmnor.mm vd, vs2, vs1 vd.mask[i] = !(vs2.mask[i] || vs1.mask[i]) vmorn.mm vd, vs2, vs1 vd.mask[i] = vs2.mask[i] || !vs1.mask[i] vmxnor.mm vd, vs2, vs1 vd.mask[i] = !(vs2.mask[i] ^^ vs1.mask[i]) ----", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Mask-Register Logical Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 4119, + 4129 + ] + }, + { + "chunk_id": "chunk_c4f5a9ef", + "text": "The old `vmandnot` and `vmornot` mnemonics can be retained as assembler aliases for compatibility.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Mask-Register Logical Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 4131, + 4134 + ] + }, + { + "chunk_id": "chunk_72e72db8", + "text": "Several assembler pseudoinstructions are defined as shorthand for common uses of mask logical operations: ---- vmmv.m vd, vs => vmand.mm vd, vs, vs Copy mask register vmclr.m vd => vmxor.mm vd, vd, vd Clear mask register vmset.m vd => vmxnor.mm vd, vd, vd Set mask register vmnot.m vd, vs => vmnand.mm vd, vs, vs Invert bits ----", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Mask-Register Logical Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 4136, + 4143 + ] + }, + { + "chunk_id": "chunk_43432ade", + "text": "The `vmcpy.m` assembler pseudoinstruction can be retained for compatibility.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Mask-Register Logical Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 4145, + 4151 + ] + }, + { + "chunk_id": "chunk_7111b863", + "text": "For implementations that internally rearrange bits according to EEW, a `vmmv.m` instruction with same source and destination can be used as idiom to force an internal reformat into a mask vector.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Mask-Register Logical Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 4145, + 4151 + ] + }, + { + "chunk_id": "chunk_fc5f2a7f", + "text": "The set of eight mask logical instructions can generate any of the 16 possibly binary logical functions of the two input masks:", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Mask-Register Logical Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 4153, + 4154 + ] + }, + { + "chunk_id": "chunk_b1bcac2f", + "text": "| 0 | 0 | 1 | 1 | src1 | 0 | 1 | 0 | 1 | src2 |", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Mask-Register Logical Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 4160, + 4162 + ] + }, + { + "chunk_id": "chunk_141503eb", + "text": "[cols=\"1,1,1,1,6,6\"] | 4+| output | instruction | pseudoinstruction", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Mask-Register Logical Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 4164, + 4166 + ] + }, + { + "chunk_id": "chunk_b33c25b1", + "text": "| 0 | 0 | 0 | 0 | vmxor.mm vd, vd, vd | vmclr.m vd | 1 | 0 | 0 | 0 | vmnor.mm vd, src1, src2 | | 0 | 1 | 0 | 0 | vmandn.mm vd, src2, src1 | | 1 | 1 | 0 | 0 | vmnand.mm vd, src1, src1 | vmnot.m vd, src1 | 0 | 0 | 1 | 0 | vmandn.mm vd, src1, src2 | | 1 | 0 | 1 | 0 | vmnand.mm vd, src2, src2 | vmnot.m vd, src2 | 0 | 1 | 1 | 0 | vmxor.mm vd, src1, src2 | | 1 | 1 | 1 | 0 | vmnand.mm vd, src1, src2 | | 0 | 0 | 0 | 1 | vmand.mm vd, src1, src2 | | 1 | 0 | 0 | 1 | vmxnor.mm vd, src1, src2 | | 0 | 1 | 0 | 1 | vmand.mm vd, src2, src2 | vmmv.m vd, src2 | 1 | 1 | 0 | 1 | vmorn.mm vd, src2, src1 | | 0 | 0 | 1 | 1 | vmand.mm vd, src1, src1 | vmmv.m vd, src1 | 1 | 0 | 1 | 1 | vmorn.mm vd, src1, src2 | | 0 | 1 | 1 | 1 | vmor.mm vd, src1, src2 | | 1 | 1 | 1 | 1 | vmxnor.mm vd, vd, vd | vmset.m vd |", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Mask-Register Logical Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 4168, + 4184 + ] + }, + { + "chunk_id": "chunk_588bb847", + "text": "The `vcpop.m` instruction writes `x[rd]` even if `vl`=0 (with the value 0, since no mask elements are active).", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector count population in mask `vcpop.m`", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 4217, + 4218 + ] + }, + { + "chunk_id": "chunk_ee999c5d", + "text": "Traps on `vcpop.m` are always reported with a `vstart` of 0.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector count population in mask `vcpop.m`", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 4220, + 4222 + ] + }, + { + "chunk_id": "chunk_1cd9d0f2", + "text": "The `vcpop.m` instruction will raise an illegal-instruction exception if `vstart` is non-zero.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector count population in mask `vcpop.m`", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 4220, + 4222 + ] + }, + { + "chunk_id": "chunk_6977a624", + "text": "If no active element has the value 1, -1 is written to the GPR.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > `vfirst` find-first-set mask bit", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 4230, + 4233 + ] + }, + { + "chunk_id": "chunk_48003e61", + "text": "The `vfirst.m` instruction writes `x[rd]` even if `vl`=0 (with the value -1, since no mask elements are active).", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > `vfirst` find-first-set mask bit", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 4239, + 4240 + ] + }, + { + "chunk_id": "chunk_abab55e1", + "text": "Traps on `vfirst` are always reported with a `vstart` of 0.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > `vfirst` find-first-set mask bit", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 4242, + 4244 + ] + }, + { + "chunk_id": "chunk_b1d916b3", + "text": "The `vfirst` instruction will raise an illegal-instruction exception if `vstart` is non-zero.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > `vfirst` find-first-set mask bit", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 4242, + 4244 + ] + }, + { + "chunk_id": "chunk_e4d11974", + "text": "If there is no set bit in the active elements of the source vector, then all active elements in the destination are written with a 1.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > `vmsbf.m` set-before-first mask bit", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 4273, + 4278 + ] + }, + { + "chunk_id": "chunk_5370701a", + "text": "Traps on `vmsbf.m` are always reported with a `vstart` of 0.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > `vmsbf.m` set-before-first mask bit", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 4283, + 4285 + ] + }, + { + "chunk_id": "chunk_62ba7498", + "text": "The `vmsbf` instruction will raise an illegal-instruction exception if `vstart` is non-zero.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > `vmsbf.m` set-before-first mask bit", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 4283, + 4285 + ] + }, + { + "chunk_id": "chunk_523dacea", + "text": "The destination register cannot overlap the source register and, if masked, cannot overlap the mask register (`v0`).", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > `vmsbf.m` set-before-first mask bit", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 4287, + 4288 + ] + }, + { + "chunk_id": "chunk_e871eff9", + "text": "Traps on `vmsif.m` are always reported with a `vstart` of 0.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > `vmsif.m` set-including-first mask bit", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 4319, + 4321 + ] + }, + { + "chunk_id": "chunk_e61d2738", + "text": "The `vmsif` instruction will raise an illegal-instruction exception if `vstart` is non-zero.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > `vmsif.m` set-including-first mask bit", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 4319, + 4321 + ] + }, + { + "chunk_id": "chunk_33ae605e", + "text": "The destination register cannot overlap the source register and, if masked, cannot overlap the mask register (`v0`).", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > `vmsif.m` set-including-first mask bit", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 4323, + 4324 + ] + }, + { + "chunk_id": "chunk_75fcb78c", + "text": "The vector mask set-only-first instruction is similar to set-before-first, except it only sets the first element with a bit set, if any.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > `vmsof.m` set-only-first mask bit", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 4328, + 4330 + ] + }, + { + "chunk_id": "chunk_d7a8c05b", + "text": "Traps on `vmsof.m` are always reported with a `vstart` of 0.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > `vmsof.m` set-only-first mask bit", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 4356, + 4358 + ] + }, + { + "chunk_id": "chunk_5b9c39f1", + "text": "The `vmsof` instruction will raise an illegal-instruction exception if `vstart` is non-zero.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > `vmsof.m` set-only-first mask bit", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 4356, + 4358 + ] + }, + { + "chunk_id": "chunk_7774827c", + "text": "The destination register cannot overlap the source register and, if masked, cannot overlap the mask register (`v0`).", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > `vmsof.m` set-only-first mask bit", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 4360, + 4361 + ] + }, + { + "chunk_id": "chunk_e97a5ac2", + "text": "1 1 1 0 1 0 1 1 v0 contents 1 0 0 1 0 0 0 1 v2 contents 2 3 4 5 6 7 8 9 v4 contents viota.m v4, v2, v0.t Masked, vtype.vma=0 1 1 1 5 1 7 1 0 v4 results ----", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Iota Instruction", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 4396, + 4401 + ] + }, + { + "chunk_id": "chunk_db760b2f", + "text": "The result value is zero-extended to fill the destination element if SEW is wider than the result.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Iota Instruction", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 4403, + 4405 + ] + }, + { + "chunk_id": "chunk_22e45d2c", + "text": "If the result value would overflow the destination SEW, the least-significant SEW bits are retained.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Iota Instruction", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 4403, + 4405 + ] + }, + { + "chunk_id": "chunk_7baafd20", + "text": "Traps on `viota.m` are always reported with a `vstart` of 0, and execution is always restarted from the beginning when resuming after a trap handler.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Iota Instruction", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 4407, + 4410 + ] + }, + { + "chunk_id": "chunk_7ff4a988", + "text": "An illegal-instruction exception is raised if `vstart` is non-zero.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Iota Instruction", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 4407, + 4410 + ] + }, + { + "chunk_id": "chunk_a35efd59", + "text": "The destination register group cannot overlap the source register and, if masked, cannot overlap the mask register (`v0`).", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Iota Instruction", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 4412, + 4413 + ] + }, + { + "chunk_id": "chunk_9eeeccdd", + "text": "---- Compact non-zero elements from input memory array to output memory array sizet compactnonzero(sizet n, const int* in, int* out) { sizet i; int *p = out; for (i=0; i \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Iota Instruction", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 4418, + 4438 + ] + }, + { + "chunk_id": "chunk_3e158839", + "text": "compactnonzero: li a6, 0 Clear count of non-zero elements loop: vsetvli a5, a0, e32, m8, ta, ma 32-bit integers vle32.v v8, (a1) Load input vector sub a0, a0, a5 Decrement number done slli a5, a5, 2 Multiply by four bytes vmsne.vi v0, v8, 0 Locate non-zero values add a1, a1, a5 Bump input pointer vcpop.m a5, v0 Count number of elements set in v0 viota.m v16, v0 Get destination offsets of active elements add a6, a6, a5 Accumulate number of elements vsll.vi v16, v16, 2, v0.t Multiply offsets by four bytes slli a5, a5, 2 Multiply number of non-zero elements by four bytes vsuxei32.v v8, (a2), v16, v0.t Scatter using scaled viota results under mask add a2, a2, a5 Bump output pointer bnez a0, loop Any more?", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Iota Instruction", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 4440, + 4456 + ] + }, + { + "chunk_id": "chunk_ca8888e5", + "text": "The `vid.v` instruction writes each element's index to the destination vector register group, from 0 to `vl`-1.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Element Index Instruction", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 4464, + 4465 + ] + }, + { + "chunk_id": "chunk_a9e9a162", + "text": "The `vs2` field of the instruction must be set to `v0`, otherwise the encoding is reserved.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Element Index Instruction", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 4474, + 4475 + ] + }, + { + "chunk_id": "chunk_75931988", + "text": "The result value is zero-extended to fill the destination element if SEW is wider than the result.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Element Index Instruction", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 4477, + 4479 + ] + }, + { + "chunk_id": "chunk_ef2ed3f4", + "text": "If the result value would overflow the destination SEW, the least-significant SEW bits are retained.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Element Index Instruction", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 4477, + 4479 + ] + }, + { + "chunk_id": "chunk_a2870437", + "text": "The integer scalar read/write instructions transfer a single value between a scalar `x` register and element 0 of a vector register.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Integer Scalar Move Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 4492, + 4494 + ] + }, + { + "chunk_id": "chunk_1b11c757", + "text": "If SEW > XLEN, the least-significant XLEN bits are transferred and the upper SEW-XLEN bits are ignored.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Integer Scalar Move Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "range", + "line_range": [ + 4501, + 4504 + ] + }, + { + "chunk_id": "chunk_d4fac149", + "text": "If SEW < XLEN, the value is sign-extended to XLEN bits.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Integer Scalar Move Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "range", + "line_range": [ + 4501, + 4504 + ] + }, + { + "chunk_id": "chunk_1eff46e3", + "text": "If SEW < XLEN, the least-significant bits are copied and the upper XLEN-SEW bits are ignored.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Integer Scalar Move Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 4508, + 4513 + ] + }, + { + "chunk_id": "chunk_9d52996d", + "text": "If SEW > XLEN, the value is sign-extended to SEW bits.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Integer Scalar Move Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 4508, + 4513 + ] + }, + { + "chunk_id": "chunk_36ecfd75", + "text": "The other elements in the destination vector register ( 0 < index < VLEN/SEW) are treated as tail elements using the current tail agnostic/undisturbed policy.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Integer Scalar Move Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 4508, + 4513 + ] + }, + { + "chunk_id": "chunk_a5832245", + "text": "The floating-point scalar read/write instructions transfer a single value between a scalar `f` register and element 0 of a vector register.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Floating-Point Scalar Move Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 4524, + 4526 + ] + }, + { + "chunk_id": "chunk_7c96b96a", + "text": "The other elements in the destination vector register ( 0 < index < VLEN/SEW) are treated as tail elements using the current tail agnostic/undisturbed policy.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Floating-Point Scalar Move Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 4539, + 4544 + ] + }, + { + "chunk_id": "chunk_58fb62d7", + "text": "Implementations may optimize certain OFFSET values for `vslideup` and `vslidedown`.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 4557, + 4561 + ] + }, + { + "chunk_id": "chunk_e788e6ec", + "text": "In particular, power-of-2 offsets may operate substantially faster than other offsets.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 4557, + 4561 + ] + }, + { + "chunk_id": "chunk_a06ce344", + "text": "For all of the `vslideup`, `vslidedown`, `v[f]slide1up`, and `v[f]slide1down` instructions, if `vstart` {ge} `vl`, the instruction performs no operation and leaves the destination vector register unchanged.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 4563, + 4565 + ] + }, + { + "chunk_id": "chunk_01230961", + "text": "The slide instructions may be masked, with mask element i controlling whether destination element i is written.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 4572, + 4574 + ] + }, + { + "chunk_id": "chunk_f3d0d241", + "text": "For `vslideup`, the value in `vl` specifies the maximum number of destination elements that are written.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-up Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 4583, + 4589 + ] + }, + { + "chunk_id": "chunk_fc2831b4", + "text": "The start index (OFFSET) for the destination can be either specified using an unsigned integer in the `x` register specified by `rs1`, or a 5-bit immediate, zero-extended to XLEN bits.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-up Instructions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 4583, + 4589 + ] + }, + { + "chunk_id": "chunk_fa60b433", + "text": "If XLEN > SEW, OFFSET is not truncated to SEW bits.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-up Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 4583, + 4589 + ] + }, + { + "chunk_id": "chunk_70f32fc3", + "text": "Destination elements OFFSET through `vl`-1 are written if unmasked and if OFFSET < `vl`.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-up Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 4583, + 4589 + ] + }, + { + "chunk_id": "chunk_7b61bfd5", + "text": "---- vslideup behavior for destination elements (vstart < vl)", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-up Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 4591, + 4592 + ] + }, + { + "chunk_id": "chunk_73ca926d", + "text": "OFFSET is amount to slideup, either from x register or a 5-bit immediate", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-up Instructions", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 4594, + 4594 + ] + }, + { + "chunk_id": "chunk_4a8f21f9", + "text": "0 <= i < min(vl, max(vstart, OFFSET)) Unchanged max(vstart, OFFSET) <= i < vl vd[i] = vs2[i-OFFSET] if v0.mask[i] enabled vl <= i < VLMAX Follow tail policy ----", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-up Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 4596, + 4599 + ] + }, + { + "chunk_id": "chunk_cc004563", + "text": "For `vslidedown`, the value in `vl` specifies the maximum number of destination elements that are written.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-down Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 4616, + 4619 + ] + }, + { + "chunk_id": "chunk_569cbb2b", + "text": "The remaining elements past `vl` are handled according to the current tail policy ().", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-down Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 4616, + 4619 + ] + }, + { + "chunk_id": "chunk_3b680b09", + "text": "The start index (OFFSET) for the source can be either specified using an unsigned integer in the `x` register specified by `rs1`, or a 5-bit immediate, zero-extended to XLEN bits.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-down Instructions", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 4621, + 4624 + ] + }, + { + "chunk_id": "chunk_c1a17417", + "text": "If XLEN > SEW, OFFSET is not truncated to SEW bits.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-down Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 4621, + 4624 + ] + }, + { + "chunk_id": "chunk_a0b329d0", + "text": "---- vslidedown behavior for source elements for element i in slide (vstart < vl) 0 <= i+OFFSET < VLMAX src[i] = vs2[i+OFFSET] VLMAX <= i+OFFSET src[i] = 0", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-down Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 4626, + 4629 + ] + }, + { + "chunk_id": "chunk_c2bd2a4e", + "text": "vslidedown behavior for destination element i in slide (vstart < vl) 0 <= i < vstart Unchanged vstart <= i < vl vd[i] = src[i] if v0.mask[i] enabled vl <= i < VLMAX Follow tail policy ----", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-down Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 4631, + 4635 + ] + }, + { + "chunk_id": "chunk_fd2a667f", + "text": "Variants of slide are provided that only move by one element but which also allow a scalar integer value to be inserted at the vacated element position.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-1-up", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 4639, + 4641 + ] + }, + { + "chunk_id": "chunk_97842578", + "text": "The `vslide1up` instruction places the `x` register argument at location 0 of the destination vector register group, provided that element 0 is active, otherwise the destination element update follows the current mask agnostic/undisturbed policy.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-1-up", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 4647, + 4652 + ] + }, + { + "chunk_id": "chunk_0812bdd1", + "text": "If XLEN < SEW, the value is sign-extended to SEW bits.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-1-up", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 4647, + 4652 + ] + }, + { + "chunk_id": "chunk_0732b9c3", + "text": "If XLEN > SEW, the least-significant bits are copied over and the high XLEN-SEW bits are ignored.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-1-up", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 4647, + 4652 + ] + }, + { + "chunk_id": "chunk_6aefd1ad", + "text": "The `vl` register specifies the maximum number of destination vector register elements updated with source values, and remaining elements past `vl` are handled according to the current tail policy ().", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-1-up", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 4658, + 4661 + ] + }, + { + "chunk_id": "chunk_2fd0b917", + "text": "---- vslide1up behavior when vl > 0", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-1-up", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 4663, + 4664 + ] + }, + { + "chunk_id": "chunk_12b3fc04", + "text": "i < vstart unchanged 0 = i = vstart vd[i] = x[rs1] if v0.mask[i] enabled max(vstart, 1) <= i < vl vd[i] = vs2[i-1] if v0.mask[i] enabled vl <= i < VLMAX Follow tail policy ----", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-1-up", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 4666, + 4670 + ] + }, + { + "chunk_id": "chunk_a4b9b4ae", + "text": "The `vl` register specifies the maximum number of destination vector register elements written with source values, and remaining elements past `vl` are handled according to the current tail policy ().", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-1-down Instruction", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 4693, + 4696 + ] + }, + { + "chunk_id": "chunk_2c7c4241", + "text": "---- vslide1down.vx vd, vs2, rs1, vm vd[i] = vs2[i+1], vd[vl-1]=x[rs1] ----", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-1-down Instruction", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 4698, + 4700 + ] + }, + { + "chunk_id": "chunk_54edfb97", + "text": "The `vslide1down` instruction places the `x` register argument at location `vl`-1 in the destination vector register, provided that element `vl-1` is active, otherwise the destination element update follows the current mask agnostic/undisturbed policy.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-1-down Instruction", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 4702, + 4708 + ] + }, + { + "chunk_id": "chunk_3ac62189", + "text": "If XLEN < SEW, the value is sign-extended to SEW bits.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-1-down Instruction", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 4702, + 4708 + ] + }, + { + "chunk_id": "chunk_54b32d67", + "text": "If XLEN > SEW, the least-significant bits are copied over and the high SEW-XLEN bits are ignored.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-1-down Instruction", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "range", + "line_range": [ + 4702, + 4708 + ] + }, + { + "chunk_id": "chunk_7b415b1d", + "text": "i < vstart unchanged vstart <= i < vl-1 vd[i] = vs2[i+1] if v0.mask[i] enabled vstart <= i = vl-1 vd[vl-1] = x[rs1] if v0.mask[i] enabled vl <= i < VLMAX Follow tail policy ----", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-1-down Instruction", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "binary", + "line_range": [ + 4713, + 4717 + ] + }, + { + "chunk_id": "chunk_1473405c", + "text": "---- vfslide1down.vf vd, vs2, rs1, vm vd[i] = vs2[i+1], vd[vl-1]=f[rs1] ----", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Floating-Point Slide-1-down Instruction", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 4728, + 4730 + ] + }, + { + "chunk_id": "chunk_0b5ab9c5", + "text": "The vector register gather instructions read elements from a first source vector register group at locations given by a second source vector register group.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Register Gather Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 4737, + 4745 + ] + }, + { + "chunk_id": "chunk_2ca45b80", + "text": "The index values in the second vector are treated as unsigned integers.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Register Gather Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 4737, + 4745 + ] + }, + { + "chunk_id": "chunk_cda645c7", + "text": "The source vector can be read at any index < VLMAX regardless of `vl`.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Register Gather Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 4737, + 4745 + ] + }, + { + "chunk_id": "chunk_7b373d05", + "text": "The maximum number of elements to write to the destination register is given by `vl`, and the remaining elements past `vl` are handled according to the current tail policy ().", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Register Gather Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 4737, + 4745 + ] + }, + { + "chunk_id": "chunk_bf7e8005", + "text": "The operation can be masked, and the mask undisturbed/agnostic policy is followed for inactive elements.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Register Gather Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 4737, + 4745 + ] + }, + { + "chunk_id": "chunk_39b3a901", + "text": "---- vrgather.vv vd, vs2, vs1, vm vd[i] = (vs1[i] >= VLMAX) ? 0 : vs2[vs1[i]]; vrgatherei16.vv vd, vs2, vs1, vm vd[i] = (vs1[i] >= VLMAX) ? 0 : vs2[vs1[i]]; ----", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Register Gather Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 4747, + 4751 + ] + }, + { + "chunk_id": "chunk_63535f93", + "text": "The `vrgather.vv` form uses SEW/LMUL for both the data and indices.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Register Gather Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 4753, + 4755 + ] + }, + { + "chunk_id": "chunk_38b48a5f", + "text": "The `vrgatherei16.vv` form uses SEW/LMUL for the data in `vs2` but EEW=16 and EMUL = (16/SEW)*LMUL for the indices in `vs1`.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Register Gather Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 4753, + 4755 + ] + }, + { + "chunk_id": "chunk_ee540469", + "text": "When SEW=8, `vrgather.vv` can only reference vector elements 0-255.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Register Gather Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 4757, + 4760 + ] + }, + { + "chunk_id": "chunk_611b9e0c", + "text": "The `vrgatherei16` form can index 64K elements, and can also be used to reduce the register capacity needed to hold indices when SEW > 16.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Register Gather Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 4757, + 4760 + ] + }, + { + "chunk_id": "chunk_8f637b17", + "text": "If an element index is out of range ( `vs1[i]` {ge} VLMAX ) then zero is returned for the element value.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Register Gather Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 4762, + 4763 + ] + }, + { + "chunk_id": "chunk_5e09101b", + "text": "Vector-scalar and vector-immediate forms of the register gather are also provided.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Register Gather Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 4765, + 4771 + ] + }, + { + "chunk_id": "chunk_aae7d88d", + "text": "These read one element from the source vector at the given index, and write this value to the active elements of the destination vector register.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Register Gather Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 4765, + 4771 + ] + }, + { + "chunk_id": "chunk_07040439", + "text": "The index value in the scalar register and the immediate, zero-extended to XLEN bits, are treated as unsigned integers.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Register Gather Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "range", + "line_range": [ + 4765, + 4771 + ] + }, + { + "chunk_id": "chunk_7fd5cb29", + "text": "If XLEN > SEW, the index value is not truncated to SEW bits.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Register Gather Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 4765, + 4771 + ] + }, + { + "chunk_id": "chunk_7536e6bc", + "text": "---- vrgather.vx vd, vs2, rs1, vm vd[i] = (x[rs1] >= VLMAX) ? 0 : vs2[x[rs1]] vrgather.vi vd, vs2, uimm, vm vd[i] = (uimm >= VLMAX) ? 0 : vs2[uimm] ----", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Register Gather Instructions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 4775, + 4778 + ] + }, + { + "chunk_id": "chunk_cddfc96e", + "text": "For any `vrgather` instruction, the destination vector register group cannot overlap with the source vector register groups, otherwise the instruction encoding is reserved.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Register Gather Instructions", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 4780, + 4782 + ] + }, + { + "chunk_id": "chunk_30e5151c", + "text": "The vector mask register specified by `vs1` indicates which of the first `vl` elements of vector register group `vs2` should be extracted and packed into contiguous elements at the beginning of vector register `vd`.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Compress Instruction", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 4795, + 4800 + ] + }, + { + "chunk_id": "chunk_79bd8b48", + "text": "1 1 0 1 0 0 1 0 1 v0 8 7 6 5 4 3 2 1 0 v1 1 2 3 4 5 6 7 8 9 v2 vsetivli t0, 9, e8, m1, tu, ma vcompress.vm v2, v1, v0 1 2 3 4 8 7 5 2 0 v2 ----", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Compress Instruction", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 4807, + 4813 + ] + }, + { + "chunk_id": "chunk_6170a268", + "text": "T`vcompress` is encoded as an unmasked instruction (`vm=1`).", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Compress Instruction", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 4815, + 4816 + ] + }, + { + "chunk_id": "chunk_eabb5799", + "text": "A trap on a `vcompress` instruction is always reported with a `vstart` of 0.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Compress Instruction", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 4822, + 4824 + ] + }, + { + "chunk_id": "chunk_c2a73b4b", + "text": "Executing a `vcompress` instruction with a non-zero `vstart` raises an illegal-instruction exception.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Compress Instruction", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 4822, + 4824 + ] + }, + { + "chunk_id": "chunk_60c2eecb", + "text": "This does mean elements in destination register after `vstart` will already have been updated.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Compress Instruction", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 4826, + 4830 + ] + }, + { + "chunk_id": "chunk_17c36ae1", + "text": "The `nr` value in the opcode is the number of individual vector registers, NREG, to copy.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Whole Vector Register Move", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 4866, + 4870 + ] + }, + { + "chunk_id": "chunk_86d405e4", + "text": "The instructions operate as if EEW=SEW, EMUL = NREG, effective length `evl`= EMUL * VLEN/SEW.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Whole Vector Register Move", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 4866, + 4870 + ] + }, + { + "chunk_id": "chunk_9a383ad3", + "text": "The usual property that no elements are written if `vstart` {ge} `vl` does not apply to these instructions.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Whole Vector Register Move", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 4875, + 4880 + ] + }, + { + "chunk_id": "chunk_5867c880", + "text": "Similarly, the property that the instructions are reserved if `vstart` exceeds the largest element index for the current `vtype` setting does not apply.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Whole Vector Register Move", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 4875, + 4880 + ] + }, + { + "chunk_id": "chunk_c360baeb", + "text": "Instead, the instructions are reserved if `vstart` {ge} `evl`.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Whole Vector Register Move", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 4875, + 4880 + ] + }, + { + "chunk_id": "chunk_7e5462d8", + "text": "If `vd` is equal to `vs2`, the instruction does not change any vector register state.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Whole Vector Register Move", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "range", + "line_range": [ + 4882, + 4886 + ] + }, + { + "chunk_id": "chunk_4a963a93", + "text": "Implementations that rearrange data internally can treat this instruction as a hint that the register group will next be accessed with an EEW equal to SEW.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Whole Vector Register Move", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "range", + "line_range": [ + 4882, + 4886 + ] + }, + { + "chunk_id": "chunk_9e2df6bd", + "text": "The instruction is encoded as an OPIVI instruction.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Whole Vector Register Move", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 4888, + 4891 + ] + }, + { + "chunk_id": "chunk_f6668414", + "text": "The value of NREG must be 1, 2, 4, or 8, and values of `simm[4:0]` other than 0, 1, 3, and 7 are reserved.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Whole Vector Register Move", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 4893, + 4894 + ] + }, + { + "chunk_id": "chunk_6f08d54b", + "text": "This encoding is chosen as it is close to the related `vmerge` encoding, and it is unlikely the `vsmul` instruction would benefit from an immediate form.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Whole Vector Register Move", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 4898, + 4902 + ] + }, + { + "chunk_id": "chunk_71960078", + "text": "The source and destination vector register numbers must be aligned appropriately for the vector register group size, and encodings with other vector register numbers are reserved.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Whole Vector Register Move", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 4913, + 4915 + ] + }, + { + "chunk_id": "chunk_cc28174e", + "text": "On a trap during a vector instruction (caused by either a synchronous exception or an asynchronous interrupt), the existing `*epc` CSR is written with a pointer to the trapping vector instruction, while the `vstart` CSR contains the element index on which the trap was taken.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Exception Handling", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 4922, + 4926 + ] + }, + { + "chunk_id": "chunk_e04db574", + "text": "To ensure forward progress without the `vstart` CSR, implementations would have to guarantee an entire vector instruction can always complete atomically without generating a trap.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Exception Handling", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 4928, + 4936 + ] + }, + { + "chunk_id": "chunk_1841408f", + "text": "We relax the last requirement to allow elements following `vstart` to have been updated at the time the trap is reported, provided that re-executing the instruction from the given `vstart` will correctly overwrite those elements.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Exception Handling > Precise vector traps", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 4950, + 4953 + ] + }, + { + "chunk_id": "chunk_407f951b", + "text": "In idempotent memory regions, vector store instructions may have updated elements in memory past the element causing a synchronous trap.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Exception Handling > Precise vector traps", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 4955, + 4959 + ] + }, + { + "chunk_id": "chunk_a7889603", + "text": "Non-idempotent memory regions must not have been updated for indices equal to or greater than the element that caused a synchronous trap during a vector store instruction.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Exception Handling > Precise vector traps", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 4955, + 4959 + ] + }, + { + "chunk_id": "chunk_b8441f87", + "text": "Except where noted above, vector instructions are allowed to overwrite their inputs, and so in most cases, the vector instruction restart must be from the `vstart` element index.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Exception Handling > Precise vector traps", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 4961, + 4966 + ] + }, + { + "chunk_id": "chunk_bd0d0892", + "text": "Implementations must ensure forward progress can be eventually guaranteed for the element or segment reported by `vstart`.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Exception Handling > Precise vector traps", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 4968, + 4969 + ] + }, + { + "chunk_id": "chunk_cf29ffa9", + "text": "Imprecise vector traps are traps that are not precise.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Exception Handling > Imprecise vector traps", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 4973, + 4978 + ] + }, + { + "chunk_id": "chunk_dab23b82", + "text": "In particular, instructions newer than `*epc` may have committed results, and instructions older than `*epc` may have not completed execution.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Exception Handling > Imprecise vector traps", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 4973, + 4978 + ] + }, + { + "chunk_id": "chunk_6ca58132", + "text": "We assume many embedded implementations will generate only imprecise traps for vector instructions on fatal errors, as they will not require resumable traps.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Exception Handling > Imprecise vector traps", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 4980, + 4983 + ] + }, + { + "chunk_id": "chunk_a73dcb9d", + "text": "Imprecise traps shall report the faulting element in `vstart` for traps caused by synchronous vector exceptions.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Exception Handling > Imprecise vector traps", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 4985, + 4986 + ] + }, + { + "chunk_id": "chunk_6d387ad0", + "text": "There is no support for imprecise traps in the current standard extensions.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Exception Handling > Imprecise vector traps", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 4988, + 4988 + ] + }, + { + "chunk_id": "chunk_2bd29a03", + "text": "Some profiles may choose to provide a privileged mode bit to select between precise and imprecise vector traps.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Exception Handling > Selectable precise/imprecise traps", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 4992, + 4997 + ] + }, + { + "chunk_id": "chunk_ef08a509", + "text": "Another trap mode can support swappable state in the vector unit, where on a trap, special instructions can save and restore the vector unit microarchitectural state, to allow execution to continue correctly around imprecise traps.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Exception Handling > Swappable traps", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 5003, + 5006 + ] + }, + { + "chunk_id": "chunk_d1027985", + "text": "All standard vector extensions have a minimum required VLEN as described below. A set of vector length extensions are provided to increase the minimum vector length of a vector extension.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > Zvl*: Minimum Vector Length Extensions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 5030, + 5032 + ] + }, + { + "chunk_id": "chunk_d21b8b44", + "text": "| Zvl32b | 32 | Zvl64b | 64 | Zvl128b | 128 | Zvl256b | 256 | Zvl512b | 512 | Zvl1024b | 1024 |", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > Zvl*: Minimum Vector Length Extensions", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 5044, + 5050 + ] + }, + { + "chunk_id": "chunk_ecee0605", + "text": "The table lists the minimum VLEN and supported EEWs for each extension as well as what floating-point types are supported.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > Zve*: Vector Extensions for Embedded Processors", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 5064, + 5069 + ] + }, + { + "chunk_id": "chunk_a9633243", + "text": "All Zve* extensions have precise traps.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > Zve*: Vector Extensions for Embedded Processors", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 5088, + 5088 + ] + }, + { + "chunk_id": "chunk_f4c175c4", + "text": "All Zve* extensions support all vector load and store instructions (), except Zve64* extensions do not support EEW=64 for index values when XLEN=32.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > Zve*: Vector Extensions for Embedded Processors", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 5099, + 5101 + ] + }, + { + "chunk_id": "chunk_d358b70b", + "text": "The Zve32x extension depends on the Zicsr extension.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > Zve*: Vector Extensions for Embedded Processors", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 5131, + 5136 + ] + }, + { + "chunk_id": "chunk_e8c152c0", + "text": "The V vector extension has precise traps.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > V: Vector Extension for Application Processors", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 5155, + 5155 + ] + }, + { + "chunk_id": "chunk_e33c1a69", + "text": "The V vector extension depends upon the Zvl128b and Zve64d extensions.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > V: Vector Extension for Application Processors", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 5157, + 5157 + ] + }, + { + "chunk_id": "chunk_fb4daf3a", + "text": "Providing a larger VLEN allows strip-mining code to be elided in some cases for short vectors, but also increases the size of the minimum implementation.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > V: Vector Extension for Application Processors", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 5159, + 5166 + ] + }, + { + "chunk_id": "chunk_c3744897", + "text": "The V extension supports all vector load and store instructions (), except the V extension does not support EEW=64 for index values when XLEN=32.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > V: Vector Extension for Application Processors", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 5173, + 5175 + ] + }, + { + "chunk_id": "chunk_9d1e0c1c", + "text": "When the Zvfhmin extension is implemented, the `vfwcvt.f.f.v` and `vfncvt.f.f.w` instructions become defined when SEW=16.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > Zvfhmin: Vector Extension for Minimal Half-Precision Floating-Point", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 5204, + 5209 + ] + }, + { + "chunk_id": "chunk_b84dc252", + "text": "When the Zvfh extension is implemented, all instructions in , , , , , and become defined when SEW=16.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > Zvfh: Vector Extension for Half-Precision Floating-Point", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 5216, + 5224 + ] + }, + { + "chunk_id": "chunk_748bada1", + "text": "Additionally, conversions between 8-bit integers and binary16 values are provided.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > Zvfh: Vector Extension for Half-Precision Floating-Point", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 5226, + 5229 + ] + }, + { + "chunk_id": "chunk_b806deb9", + "text": "The floating-point-to-integer narrowing conversions (`vfncvt[.rtz].x[u].f.w`) and integer-to-floating-point widening conversions (`vfwcvt.f.x[u].v`) become defined when SEW=8.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > Zvfh: Vector Extension for Half-Precision Floating-Point", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 5226, + 5229 + ] + }, + { + "chunk_id": "chunk_968b68c9", + "text": "As another example, the SHA-256 cryptographic instructions in the Zvknha extension operate on 128-bit values represented as a 4-element group of 32-bit elements.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Element Groups", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 5242, + 5248 + ] + }, + { + "chunk_id": "chunk_8eecc1f7", + "text": "The element group size (EGS) is the number of elements in one group, and must be a power-of-two (POT).", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Element Groups > Element Group Size", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 5256, + 5257 + ] + }, + { + "chunk_id": "chunk_989808cd", + "text": "Error checking for `vl` is a little more difficult.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Element Groups > Element Group Size", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 5259, + 5266 + ] + }, + { + "chunk_id": "chunk_6674c7ed", + "text": "Non-POT EGS can also cause large increases in the lowest-common-multiple of element group sizes, which adds constraints to `vl` setting in order to avoid splitting an element group across strip-mine iterations in vector-length-agnostic code.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Element Groups > Element Group Size", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 5259, + 5266 + ] + }, + { + "chunk_id": "chunk_201b2057", + "text": "The element group size is statically encoded in the instruction, often implicitly as part of the opcode.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Element Groups > Element Group Size", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 5268, + 5269 + ] + }, + { + "chunk_id": "chunk_ba9b0b66", + "text": "Vector instructions with EGS > VLMAX are reserved.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Element Groups > Element Group Size", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 5271, + 5271 + ] + }, + { + "chunk_id": "chunk_34252ccb", + "text": "When an operand is a vector of element groups, the `vl` setting must correspond to an integer multiple of the element group size, with other values of `vl` reserved.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Element Groups > Setting `vl`", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 5283, + 5287 + ] + }, + { + "chunk_id": "chunk_c5e85f62", + "text": "When element group instructions are present, an additional constraint is placed on the setting of `vl` based on an AVL value (augmenting ). EGSMAX is the largest EGS supported by the implementation.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Element Groups > Setting `vl`", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 5292, + 5297 + ] + }, + { + "chunk_id": "chunk_01343bc4", + "text": "When AVL > VLMAX, the value of `vl` must be set to either VLMAX or a positive integer multiple of EGSMAX.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Element Groups > Setting `vl`", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 5292, + 5297 + ] + }, + { + "chunk_id": "chunk_4a6faa2e", + "text": "If EEW is encoded statically in the instruction, or if an instruction has multiple operands containing vectors of element groups with different EEW, an appropriate SEW must be chosen for `vsetvl` instructions.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Element Groups > Setting `vl`", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 5307, + 5310 + ] + }, + { + "chunk_id": "chunk_3b50ed53", + "text": "Alternatively, the opcode might encode EEW of all operands statically and ignore the value of SEW when the operation only makes sense for a single size on each operand.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Element Groups > Determining EEW", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 5323, + 5325 + ] + }, + { + "chunk_id": "chunk_a883f232", + "text": "Each source and destination operand to a vector instruction may have a different element group size, different EMUL, and/or different EEW.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Element Groups > Determining EMUL", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 5346, + 5347 + ] + }, + { + "chunk_id": "chunk_3556f2e3", + "text": "It is possible to use LMUL to concatenate multiple vector registers together to support larger EGW>VLEN.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Element Groups > Element Group Width", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 5351, + 5356 + ] + }, + { + "chunk_id": "chunk_db3172a7", + "text": "Profiles can set minimum VLEN requirements to inform authors of such software.", + "source_file": "src/v-st-ext.adoc", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Element Groups > Element Group Width", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 5358, + 5362 + ] + } + ] + }, + { + "file": "src/vector-crypto.adoc", + "chunks": [ + { + "chunk_id": "chunk_dcf68539", + "text": "Where possible, we have written this specification to be understandable by all, though we recognize that the motivations and references to algorithms or other specifications and standards may be unfamiliar to those who are not domain experts.", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Intended Audience", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 19, + 24 + ] + }, + { + "chunk_id": "chunk_325872c6", + "text": "We hope this aids people's understanding of which aspects of the specification are particularly relevant to them, and which they may (safely!) ignore or pass to a colleague.", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Intended Audience", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 26, + 33 + ] + }, + { + "chunk_id": "chunk_c5eae6f5", + "text": "They should understand the motivations for the instructions we include, and be familiar with most of the algorithms and outside standards to which we refer.", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Intended Audience", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 35, + 40 + ] + }, + { + "chunk_id": "chunk_370f9e33", + "text": "In particular, they should be aware of the literature around efficiently implementing AES and SM4 SBoxes in hardware.", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Intended Audience", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 49, + 56 + ] + }, + { + "chunk_id": "chunk_1eaa4ab0", + "text": "The standard will not try to anticipate new useful low-level operations which may be useful as building blocks for future cryptographic constructs.", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Policies", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 140, + 146 + ] + }, + { + "chunk_id": "chunk_7adc298c", + "text": "Regarding side-channel countermeasures: Where relevant, proposed instructions must aim to remove the possibility of any timing side-channels.", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Policies", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 148, + 152 + ] + }, + { + "chunk_id": "chunk_c5ef14fa", + "text": "All instructions shall be implemented with data-independent timing.", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Policies", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 148, + 152 + ] + }, + { + "chunk_id": "chunk_853aecc6", + "text": "That is, the latency of the execution of these instructions shall not vary with different input values.", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Policies", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 148, + 152 + ] + }, + { + "chunk_id": "chunk_5d06aa19", + "text": "Many vector crypto instructions operate on operands that are wider than elements (which are currently limited to 64 bits wide).", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Element Groups", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 157, + 162 + ] + }, + { + "chunk_id": "chunk_b66ad81b", + "text": "As with all vector instructions, the number of elements processed is specified by the vector length `vl`.", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Element Groups", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 195, + 199 + ] + }, + { + "chunk_id": "chunk_de8729ff", + "text": "The number of element groups operated upon is then `vl`/`EGS`.", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Element Groups", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 195, + 199 + ] + }, + { + "chunk_id": "chunk_d2bd3ffd", + "text": "Likewise the starting element group is `vstart`/`EGS`.", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Element Groups", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 195, + 199 + ] + }, + { + "chunk_id": "chunk_cd2c84cc", + "text": "See for limitations on `vl` and `vstart` for vector crypto instructions.", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Element Groups", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 195, + 199 + ] + }, + { + "chunk_id": "chunk_6fc87476", + "text": "Instructions that violate the `vl` or `vstart` requirements are reserved.", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Instruction Constraints", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 219, + 219 + ] + }, + { + "chunk_id": "chunk_a8c17d39", + "text": "LMUL constraints:: For element-group instructions, `LMUL`*`VLEN` must always be at least as large as `EGW`, otherwise an illegal-instruction exception is raised, even if `vl`=0.", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Instruction Constraints", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 235, + 237 + ] + }, + { + "chunk_id": "chunk_356861ac", + "text": "The *Scalar Element Group* operand has `EMUL = ceil(EGW / VLEN)`.", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Instruction Constraints", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 275, + 276 + ] + }, + { + "chunk_id": "chunk_ed9fc12d", + "text": "In the case of the `.vs` instructions defined in this specification, `vs2` holds a 128-bit scalar element group.", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Instruction Constraints", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 278, + 283 + ] + }, + { + "chunk_id": "chunk_72f4ea11", + "text": "For implementations with `VLEN` \u2265 128, `vs2` refers to a single register.", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Instruction Constraints", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 278, + 283 + ] + }, + { + "chunk_id": "chunk_5b9da8d8", + "text": "Thus, the `vd` register group must not overlap the `vs2` register.", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Instruction Constraints", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 278, + 283 + ] + }, + { + "chunk_id": "chunk_1ab1961e", + "text": "However, in implementations where `VLEN` < 128, `vs2` refers to a register group comprised of the number of registers needed to hold the 128-bit scalar element group.", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Instruction Constraints", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 278, + 283 + ] + }, + { + "chunk_id": "chunk_6b9467f4", + "text": "In this case, the `vd` register group must not overlap this `vs2` register group.", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Instruction Constraints", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 278, + 283 + ] + }, + { + "chunk_id": "chunk_eb8c5660", + "text": "The following contains some guidelines that enable the portability of vector-crypto-based code to implementations with different values for `VLEN`", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Software Portability", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 348, + 349 + ] + }, + { + "chunk_id": "chunk_e447ceef", + "text": "Application Processors:: Application processors are expected to follow the V-extension and will therefore have `VLEN` {ge} 128.", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Software Portability", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 351, + 352 + ] + }, + { + "chunk_id": "chunk_bae02ff2", + "text": "Implementations with `VLEN` = 128, require that `LMUL` is doubled for these instructions in order to create 256-bit elements across a pair of registers.", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Software Portability", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 359, + 364 + ] + }, + { + "chunk_id": "chunk_dd6c9a77", + "text": "Therefore, we recommend that libraries that implement SHA-512 and SM3 employ this doubling of `LMUL` to ensure that the software can run on all implementation with `VLEN` {ge} 128.", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Software Portability", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 359, + 364 + ] + }, + { + "chunk_id": "chunk_5aa7c4e2", + "text": "While the doubling of `LMUL` for these instructions is safe for implementations with `VLEN` {ge} 256, it may be less optimal as it will result in unnecessary register pressure and might exact a performance penalty in some microarchitectures.", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Software Portability", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 366, + 370 + ] + }, + { + "chunk_id": "chunk_ff2c9b2a", + "text": "Therefore, we suggest that in addition to providing portable code for SHA-512 and SM3, libraries should also include more optimal code for these instructions when `VLEN` {ge} 256. //", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Software Portability", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 366, + 370 + ] + }, + { + "chunk_id": "chunk_ffca5398", + "text": "| | Algorithm | Instructions | VLEN | LMUL", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Software Portability", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 372, + 378 + ] + }, + { + "chunk_id": "chunk_c35595a7", + "text": "| SHA-512 | vsha2* | 64 | vl/2 | SM3 | vsm3* | 32 | vl/4 |", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Software Portability", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 380, + 382 + ] + }, + { + "chunk_id": "chunk_f7e14b9d", + "text": "On implementations with `VLEN` < 128, these scalar element groups will necessarily be formed across registers.", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Software Portability", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 396, + 398 + ] + }, + { + "chunk_id": "chunk_684726a3", + "text": "If `Zve32x` is supported then `Zvkb` or `Zvbb` provide support for EEW of 8, 16, and 32.", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 422, + 422 + ] + }, + { + "chunk_id": "chunk_75a26ddf", + "text": "If `Zve64x` is supported then `Zvkb` or `Zvbb` also add support for EEW 64.", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 422, + 422 + ] + }, + { + "chunk_id": "chunk_bb27d2de", + "text": "All cryptography-specific instructions defined in this Vector Crypto specification (i.e., those in , , , and but not ,, or ) shall be executed with data-independent execution latency as defined in the .", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 427, + 432 + ] + }, + { + "chunk_id": "chunk_fe57b73f", + "text": "This specification includes a extension that, when implemented, requires certain vector instructions (including , , and ) to be executed with data-independent execution latency.", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "line_range": [ + 434, + 435 + ] + }, + { + "chunk_id": "chunk_ccc37ee9", + "text": "All of these instructions work on 128-bit element groups comprised of four 32-bit elements.", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvkg` - Vector GCM/GMAC", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 521, + 521 + ] + }, + { + "chunk_id": "chunk_c1e1f6a7", + "text": "GHASH~H~ is defined in the // link:https://csrc.nist.gov/publications/detail/sp/800-38d/final[NIST Special Publication 800-38D] \"Recommendation for Block Cipher Modes of Operation: Galois/Counter Mode (GCM) and GMAC\" cite:[nist:gcm] (NIST Specification).", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvkg` - Vector GCM/GMAC", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 523, + 527 + ] + }, + { + "chunk_id": "chunk_d533d724", + "text": "To help avoid side-channel timing attacks, these instructions shall be implemented with data-independent timing.", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvkg` - Vector GCM/GMAC", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 529, + 529 + ] + }, + { + "chunk_id": "chunk_27440d37", + "text": "The number of element groups to be processed is `vl`/`EGS`. `vl` must be set to the number of `SEW=32` elements to be processed and therefore must be a multiple of `EGS=4`. + Likewise, `vstart` must be a multiple of `EGS=4`.", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvkg` - Vector GCM/GMAC", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 531, + 534 + ] + }, + { + "chunk_id": "chunk_a241af1e", + "text": "All of these instructions work on 128-bit element groups comprised of four 32-bit elements.", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvkned` - NIST Suite: Vector AES Block Cipher", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 560, + 561 + ] + }, + { + "chunk_id": "chunk_b910ad34", + "text": "On systems with `VLEN`<128, element groups may be formed by concatenating 32-bit elements from two or four registers by using an LMUL =2 and LMUL=4 respectively.", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvkned` - NIST Suite: Vector AES Block Cipher", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "range", + "line_range": [ + 563, + 565 + ] + }, + { + "chunk_id": "chunk_c4c3216d", + "text": "To help avoid side-channel timing attacks, these instructions shall be implemented with data-independent timing.", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvkned` - NIST Suite: Vector AES Block Cipher", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 571, + 571 + ] + }, + { + "chunk_id": "chunk_391c8fd1", + "text": "The number of element groups to be processed is `vl`/`EGS`. `vl` must be set to the number of `SEW=32` elements to be processed and therefore must be a multiple of `EGS=4`. + Likewise, `vstart` must be a multiple of `EGS=4`.", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvkned` - NIST Suite: Vector AES Block Cipher", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 573, + 576 + ] + }, + { + "chunk_id": "chunk_767310fa", + "text": "SHA-256: these instructions work on 128-bit element groups comprised of four 32-bit elements. - SHA-512: these instructions work on 256-bit element groups comprised of four 64-bit elements.", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvknh[ab]` - NIST Suite: Vector SHA-2 Secure Hash", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 605, + 606 + ] + }, + { + "chunk_id": "chunk_516c21f1", + "text": "To help avoid side-channel timing attacks, these instructions shall be implemented with data-independent timing.", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvknh[ab]` - NIST Suite: Vector SHA-2 Secure Hash", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 640, + 640 + ] + }, + { + "chunk_id": "chunk_e32644aa", + "text": "The number of element groups to be processed is `vl`/`EGS`. `vl` must be set to the number of `SEW` elements to be processed and therefore must be a multiple of `EGS=4`. + Likewise, `vstart` must be a multiple of `EGS=4`.", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvknh[ab]` - NIST Suite: Vector SHA-2 Secure Hash", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 650, + 653 + ] + }, + { + "chunk_id": "chunk_fa1dcc0b", + "text": "All of these instructions work on 128-bit element groups comprised of four 32-bit elements.", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvksed` - ShangMi Suite: SM4 Block Cipher", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 687, + 688 + ] + }, + { + "chunk_id": "chunk_441c4256", + "text": "To help avoid side-channel timing attacks, these instructions shall be implemented with data-independent timing.", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvksed` - ShangMi Suite: SM4 Block Cipher", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 694, + 694 + ] + }, + { + "chunk_id": "chunk_1d39c544", + "text": "The number of element groups to be processed is `vl`/`EGS`. `vl` must be set to the number of `SEW=32` elements to be processed and therefore must be a multiple of `EGS=4`. + Likewise, `vstart` must be a multiple of `EGS=4`.", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvksed` - ShangMi Suite: SM4 Block Cipher", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 696, + 699 + ] + }, + { + "chunk_id": "chunk_f8ef407b", + "text": "All of these instructions work on 256-bit element groups comprised of eight 32-bit elements.", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvksh` - ShangMi Suite: SM3 Secure Hash", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 731, + 732 + ] + }, + { + "chunk_id": "chunk_81fcf466", + "text": "To help avoid side-channel timing attacks, these instructions shall be implemented with data-independent timing.", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvksh` - ShangMi Suite: SM3 Secure Hash", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 746, + 746 + ] + }, + { + "chunk_id": "chunk_2715a8e8", + "text": "The number of element groups to be processed is `vl`/`EGS`. `vl` must be set to the number of `SEW=32` elements to be processed and therefore must be a multiple of `EGS=8`. + Likewise, `vstart` must be a multiple of `EGS=8`.", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvksh` - ShangMi Suite: SM3 Secure Hash", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 748, + 751 + ] + }, + { + "chunk_id": "chunk_ccd0d1b5", + "text": "However, DIEL does not apply to other values such as vl, vtype, and the mask (when used to control execution of a masked vector instruction).", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvkt` - Vector Data-Independent Execution Latency", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 890, + 897 + ] + }, + { + "chunk_id": "chunk_b1e1d28d", + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated upon.", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesdf.[vv,vs]", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1067, + 1068 + ] + }, + { + "chunk_id": "chunk_54cab962", + "text": "Operation:: [source,sail] -- function clause execute (VAESDF(vs2, vd, suffix)) = { if(LMUL*VLEN < EGW) then { handleillegal(); // illegal-instruction exception RETIREFAIL } else {", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesdf.[vv,vs]", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1072, + 1079 + ] + }, + { + "chunk_id": "chunk_77c26fc3", + "text": "foreach (i from egstart to eglen-1) { let keyelem = if suffix \"vv\" then i else 0; let state : bits(128) = getvelem(vd, EGW=128, i); let rkey : bits(128) = getvelem(vs2, EGW=128, keyelem); let sr : bits(128) = aesshiftrowsinv(state); let sb : bits(128) = aessubbytesinv(sr); let ark : bits(128) = sb ^ rkey; setvelem(vd, EGW=128, i, ark); } RETIRESUCCESS } } --", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesdf.[vv,vs]", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1084, + 1096 + ] + }, + { + "chunk_id": "chunk_b0bd5069", + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated upon. // // The number of element groups to be processed is `vl`/`EGS`. // `vl` must be set to the number of `SEW=32` elements to be processed and // therefore must be a multiple of `EGS=4`. + // Likewise, `vstart` must be a multiple of `EGS=4`.", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesdm.[vv,vs]", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1169, + 1175 + ] + }, + { + "chunk_id": "chunk_c0f4cdd4", + "text": "Operation:: [source,sail] -- function clause execute (VAESDM(vs2, vd, suffix)) = { if(LMUL*VLEN < EGW) then { handleillegal(); // illegal-instruction exception RETIREFAIL } else {", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesdm.[vv,vs]", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1177, + 1184 + ] + }, + { + "chunk_id": "chunk_e2fbb825", + "text": "foreach (i from egstart to eglen-1) { let keyelem = if suffix \"vv\" then i else 0; let state : bits(128) = getvelem(vd, EGW=128, i); let rkey : bits(128) = getvelem(vs2, EGW=128, keyelem); let sr : bits(128) = aesshiftrowsinv(state); let sb : bits(128) = aessubbytesinv(sr); let ark : bits(128) = sb ^ rkey; let mix : bits(128) = aesmixcolumnsinv(ark); setvelem(vd, EGW=128, i, mix); } RETIRESUCCESS } } --", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesdm.[vv,vs]", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1189, + 1202 + ] + }, + { + "chunk_id": "chunk_698591a0", + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated upon. // // The number of element groups to be processed is `vl`/`EGS`. // `vl` must be set to the number of `SEW=32` elements to be processed and // therefore must be a multiple of `EGS=4`. + // Likewise, `vstart` must be a multiple of `EGS=4`.", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesef.[vv,vs]", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1274, + 1280 + ] + }, + { + "chunk_id": "chunk_07a088e2", + "text": "Operation:: [source,sail] -- function clause execute (VAESEF(vs2, vd, suffix) = { if(LMUL*VLEN < EGW) then { handleillegal(); // illegal-instruction exception RETIREFAIL } else {", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesef.[vv,vs]", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1282, + 1289 + ] + }, + { + "chunk_id": "chunk_d8eba26e", + "text": "foreach (i from egstart to eglen-1) { let keyelem = if suffix \"vv\" then i else 0; let state : bits(128) = getvelem(vd, EGW=128, i); let rkey : bits(128) = getvelem(vs2, EGW=128, keyelem); let sb : bits(128) = aessubbytesfwd(state); let sr : bits(128) = aesshiftrowsfwd(sb); let ark : bits(128) = sr ^ rkey; setvelem(vd, EGW=128, i, ark); } RETIRESUCCESS } } --", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesef.[vv,vs]", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1294, + 1306 + ] + }, + { + "chunk_id": "chunk_2fc0ff0c", + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated upon. // // The number of element groups to be processed is `vl`/`EGS`. // `vl` must be set to the number of `SEW=32` elements to be processed and // therefore must be a multiple of `EGS=4`. + // Likewise, `vstart` must be a multiple of `EGS=4`.", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesem.[vv,vs]", + "confidence": "very_high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1379, + 1385 + ] + }, + { + "chunk_id": "chunk_242ff693", + "text": "Operation:: [source,sail] -- function clause execute (VAESEM(vs2, vd, suffix)) = { if(LMUL*VLEN < EGW) then { handleillegal(); // illegal-instruction exception RETIREFAIL } else {", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesem.[vv,vs]", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1387, + 1394 + ] + }, + { + "chunk_id": "chunk_d5b261d1", + "text": "foreach (i from egstart to eglen-1) { let keyelem = if suffix \"vv\" then i else 0; let state : bits(128) = getvelem(vd, EGW=128, i); let rkey : bits(128) = getvelem(vs2, EGW=128, keyelem); let sb : bits(128) = aessubbytesfwd(state); let sr : bits(128) = aesshiftrowsfwd(sb); let mix : bits(128) = aesmixcolumnsfwd(sr); let ark : bits(128) = mix ^ rkey; setvelem(vd, EGW=128, i, ark); } RETIRESUCCESS } } --", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesem.[vv,vs]", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 1399, + 1412 + ] + }, + { + "chunk_id": "chunk_f5ec64b6", + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated upon.", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaeskf1.vi", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1479, + 1480 + ] + }, + { + "chunk_id": "chunk_3778f1de", + "text": "Operation:: [source,Sail] -- function clause execute (VAESKF1(rnd, vd, vs2)) = { if(LMUL*VLEN < EGW) then { handleillegal(); // illegal-instruction exception RETIREFAIL } else {", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaeskf1.vi", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1491, + 1498 + ] + }, + { + "chunk_id": "chunk_d4bb108c", + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated upon.", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaeskf2.vi", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1589, + 1590 + ] + }, + { + "chunk_id": "chunk_fbc5a5e2", + "text": "Operation:: [source,Sail] -- function clause execute (VAESKF2(rnd, vd, vs2)) = { if(LMUL*VLEN < EGW) then { handleillegal(); // illegal-instruction exception RETIREFAIL } else {", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaeskf2.vi", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1599, + 1606 + ] + }, + { + "chunk_id": "chunk_81b48b9a", + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated upon.", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesz.vs", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 1690, + 1691 + ] + }, + { + "chunk_id": "chunk_639eb033", + "text": "Operation:: [source,sail] -- function clause execute (VAESZ(vs2, vd) = { if(((vstart%EGS)<>0) | (LMUL*VLEN < EGW)) then { handleillegal(); // illegal-instruction exception RETIREFAIL } else {", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesz.vs", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1699, + 1706 + ] + }, + { + "chunk_id": "chunk_3b7e5c6a", + "text": "In the vector-scalar version, `Op1` is the sign-extended or truncated value in scalar register `rs1`.", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vandn.[vv,vx]", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 1796, + 1799 + ] + }, + { + "chunk_id": "chunk_ea6fad60", + "text": "Operation:: [source,sail] -- function clause execute (VANDN(vs2, vs1, vd, suffix)) = { foreach (i from vstart to vl-1) { let op1 = match suffix { \"vv\" => getvelem(vs1, SEW, i), \"vx\" => sextortruncatetosew(X(vs1)) }; let op2 = getvelem(vs2, SEW, i); setvelem(vd, EEW=SEW, i, ~op1 & op2); } RETIRESUCCESS }", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vandn.[vv,vx]", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 1812, + 1825 + ] + }, + { + "chunk_id": "chunk_858684d8", + "text": "Each 64-bit element in the `vs2` vector register is carry-less multiplied by either each 64-bit element in `vs1` (vector-vector), or the 64-bit value from integer register `rs1` (vector-scalar).", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vclmul.[vv,vx]", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 2016, + 2019 + ] + }, + { + "chunk_id": "chunk_f11d9371", + "text": "foreach (i from vstart to vl-1) { let op1 : bits (64) = if suffix \"vv\" then getvelem(vs1,i) else zextortruncatetosew(X(vs1)); let op2 : bits (64) = getvelem(vs2,i); let product : bits (64) = clmul(op1,op2,SEW); setvelem(vd, i, product); } RETIRESUCCESS }", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vclmul.[vv,vx]", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 2027, + 2035 + ] + }, + { + "chunk_id": "chunk_2d8ad53a", + "text": "Each 64-bit element in the `vs2` vector register is carry-less multiplied by either each 64-bit element in `vs1` (vector-vector), or the 64-bit value from integer register `rs1` (vector-scalar).", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vclmulh.[vv,vx]", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 2109, + 2112 + ] + }, + { + "chunk_id": "chunk_58fedcc1", + "text": "foreach (i from vstart to vl-1) { let op1 : bits (64) = if suffix \"vv\" then getvelem(vs1,i) else zextortruncatetosew(X(vs1)); let op2 : bits (64) = getvelem(vs2, i); let product : bits (64) = clmulh(op1, op2, SEW); setvelem(vd, i, product); } RETIRESUCCESS }", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vclmulh.[vv,vx]", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 2122, + 2130 + ] + }, + { + "chunk_id": "chunk_0d45ecd1", + "text": "| Vs2 | input | Input elements | Vd | output | Count of leading zero bits |", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vclz.v", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2179, + 2181 + ] + }, + { + "chunk_id": "chunk_932db4e6", + "text": "foreach (i from vstart to vl-1) { let input = getvelem(vs2, SEW, i); for (j = (SEW - 1); j >= 0; j--) if [input[j]] 0b1 then break; setvelem(vd, SEW, i, SEW - 1 - j) } RETIRESUCCESS } --", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vclz.v", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 2193, + 2201 + ] + }, + { + "chunk_id": "chunk_c998a2a3", + "text": "| Vs2 | input | Input elements | Vd | output | Count of trailing zero bits |", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vctz.v", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2296, + 2298 + ] + }, + { + "chunk_id": "chunk_28ae0776", + "text": "foreach (i from vstart to vl-1) { let input = getvelem(vs2, SEW, i); for (j = 0; j < SEW; j++) if [input[j]] 0b1 then break; setvelem(vd, SEW, i, j) } RETIRESUCCESS } --", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vctz.v", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 2310, + 2318 + ] + }, + { + "chunk_id": "chunk_822e0943", + "text": "This instruction treats all of the inputs and outputs as 128-bit polynomials and performs operations over GF[2].", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vghsh.vv", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 2371, + 2375 + ] + }, + { + "chunk_id": "chunk_06125fe7", + "text": "The multiplication over GF(2^128^) is a carry-less multiply of two 128-bit polynomials modulo GHASH's irreducible polynomial (x^128^ + x^7^ + x^2^ + x + 1).", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vghsh.vv", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 2377, + 2378 + ] + }, + { + "chunk_id": "chunk_3ca24c25", + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated upon.", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vghsh.vv", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 2391, + 2392 + ] + }, + { + "chunk_id": "chunk_4ed2f790", + "text": "for (int bit = 0; bit < 128; bit++) { if bittobool(S[bit]) Z ^= H", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vghsh.vv", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2416, + 2418 + ] + }, + { + "chunk_id": "chunk_9de0270b", + "text": "bool reduce = bittobool(H[127]); H = H << 1; // left shift H by 1 if (reduce) H ^= 0x87; // Reduce using x^7 + x^2 + x^1 + 1 polynomial }", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vghsh.vv", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2420, + 2424 + ] + }, + { + "chunk_id": "chunk_9dc6eb59", + "text": "This instruction treats all of the inputs and outputs as 128-bit polynomials and performs operations over GF[2].", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vgmul.vv", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 2484, + 2486 + ] + }, + { + "chunk_id": "chunk_a0947dcb", + "text": "It produces the product over GF(2^128^) of the two 128-bit inputs.", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vgmul.vv", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 2484, + 2486 + ] + }, + { + "chunk_id": "chunk_4b8602f0", + "text": "The multiplication over GF(2^128^) is a carry-less multiply of two 128-bit polynomials modulo GHASH's irreducible polynomial (x^128^ + x^7^ + x^2^ + x + 1).", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vgmul.vv", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 2488, + 2489 + ] + }, + { + "chunk_id": "chunk_ff885a1c", + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated upon.", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vgmul.vv", + "confidence": "very_high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "line_range": [ + 2498, + 2499 + ] + }, + { + "chunk_id": "chunk_3782b992", + "text": "for (int bit = 0; bit < 128; bit++) { if bittobool(Y[bit]) Z ^= H", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vgmul.vv", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2519, + 2521 + ] + }, + { + "chunk_id": "chunk_82803ec7", + "text": "bool reduce = bittobool(H[127]); H = H << 1; // left shift H by 1 if (reduce) H ^= 0x87; // Reduce using x^7 + x^2 + x^1 + 1 polynomial }", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vgmul.vv", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 2523, + 2527 + ] + }, + { + "chunk_id": "chunk_2a537f4c", + "text": "Operation:: [source,sail] -- function clause execute (VREV8(vs2)) = { foreach (i from vstart to vl-1) { input = getvelem(vs2, SEW, i); let output : SEW = 0; let j = SEW - 1; foreach (k from 0 to (SEW - 8) by 8) { output[k..(k + 7)] = input[(j - 7)..j]; j = j - 8; setvelem(vd, SEW, i, output) } RETIRESUCCESS } --", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vrev8.v", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 2585, + 2600 + ] + }, + { + "chunk_id": "chunk_4c28def4", + "text": "Operation:: [source,sail] -- function clause execute (VROLVV(vs2, vs1, vd)) = { foreach (i from vstart to vl - 1) { setvelem(vd, EEW=SEW, i, getvelem(vs2, i) <<< (getvelem(vs1, i) & (SEW-1)) ) } RETIRESUCCESS }", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vrol.[vv,vx]", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 2686, + 2696 + ] + }, + { + "chunk_id": "chunk_1a7d2a0d", + "text": "function clause execute (VROLVX(vs2, rs1, vd)) = { foreach (i from vstart to vl - 1) { setvelem(vd, EEW=SEW, i, getvelem(vs2, i) <<< (X(rs1) & (SEW-1)) ) } RETIRESUCCESS }", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vrol.[vv,vx]", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 2698, + 2705 + ] + }, + { + "chunk_id": "chunk_f5f6efb4", + "text": "Operation:: [source,sail] -- function clause execute (VRORVV(vs2, vs1, vd)) = { foreach (i from vstart to vl - 1) { setvelem(vd, EEW=SEW, i, getvelem(vs2, i) >>> (getvelem(vs1, i) & (SEW-1)) ) } RETIRESUCCESS }", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vror.[vv,vx,vi]", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 2809, + 2819 + ] + }, + { + "chunk_id": "chunk_52fd3c99", + "text": "function clause execute (VRORVX(vs2, rs1, vd)) = { foreach (i from vstart to vl - 1) { setvelem(vd, EEW=SEW, i, getvelem(vs2, i) >>> (X(rs1) & (SEW-1)) ) } RETIRESUCCESS }", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vror.[vv,vx,vi]", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 2821, + 2828 + ] + }, + { + "chunk_id": "chunk_e59bc2cf", + "text": "function clause execute (VRORVI(vs2, uimm[5:0], vd)) = { foreach (i from vstart to vl - 1) { setvelem(vd, EEW=SEW, i, getvelem(vs2, i) >>> (uimm[5:0] & (SEW-1)) ) } RETIRESUCCESS } --", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vror.[vv,vx,vi]", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 2830, + 2838 + ] + }, + { + "chunk_id": "chunk_3a7f24b8", + "text": "Two words of `vs1` are processed with the 8 words of current state held in `vd` and `vs2` to perform two rounds of hash computation producing four words of the next state.", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsha2c[hl].vv", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 2911, + 2914 + ] + }, + { + "chunk_id": "chunk_8a14d441", + "text": "Operation:: [source,sail] -- function clause execute (VSHA2c(vs2, vs1, vd)) = { if(LMUL*VLEN < EGW) then { handleillegal(); // illegal-instruction exception RETIREFAIL } else {", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsha2c[hl].vv", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 2965, + 2972 + ] + }, + { + "chunk_id": "chunk_d8a05b31", + "text": "Operation:: [source,sail] -- function clause execute (VSHA2ms(vs2, vs1, vd)) = { // SEW32 = SHA-256 // SEW64 = SHA-512 if(LMUL*VLEN < EGW) then { handleillegal(); // illegal-instruction exception RETIREFAIL } else {", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsha2ms.vv", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 3165, + 3174 + ] + }, + { + "chunk_id": "chunk_fb584b00", + "text": "The current state of eight 32-bit words is read in as an element group from `vd`.", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm3c.vi", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 3266, + 3273 + ] + }, + { + "chunk_id": "chunk_13a309c8", + "text": "Eight 32-bit message words are read in as an element group from `vs2`, although only four of them are used.", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm3c.vi", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 3266, + 3273 + ] + }, + { + "chunk_id": "chunk_ad5dc774", + "text": "All of the 32-bit input words are byte-swapped from big endian to little endian.", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm3c.vi", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 3266, + 3273 + ] + }, + { + "chunk_id": "chunk_e96e140e", + "text": "These inputs are processed somewhat differently based on the round group (as specified in rnds), and the next state is generated as an element group of eight 32-bit words.", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm3c.vi", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 3266, + 3273 + ] + }, + { + "chunk_id": "chunk_d06fa038", + "text": "The next state of eight 32-bit words are generated, swapped from little endian to big endian, and are returned in an eight-element group.", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm3c.vi", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 3266, + 3273 + ] + }, + { + "chunk_id": "chunk_46e1371f", + "text": "The round number is provided by the 5-bit `rnds` unsigned immediate.", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm3c.vi", + "confidence": "high", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 3275, + 3277 + ] + }, + { + "chunk_id": "chunk_21e22715", + "text": "Operation:: [source,sail] -- function clause execute (VSM3C(rnds, vs2, vd)) = { if(LMUL*VLEN < EGW) then { handleillegal(); // illegal-instruction exception RETIREFAIL } else {", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm3c.vi", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 3297, + 3304 + ] + }, + { + "chunk_id": "chunk_9d1208b0", + "text": "The sixteen most recent 32-bit message words are read in as two eight-element groups from `vs1` and `vs2`.", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm3me.vv", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 3439, + 3444 + ] + }, + { + "chunk_id": "chunk_d0a40012", + "text": "The next eight 32-bit message words are generated, swapped from little endian to big endian, and are returned in an eight-element group.", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm3me.vv", + "confidence": "medium", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "line_range": [ + 3439, + 3444 + ] + }, + { + "chunk_id": "chunk_14b808ca", + "text": "Operation:: [source,sail] -- function clause execute (VSM3ME(vs2, vs1)) = { if(LMUL*VLEN < EGW) then { handleillegal(); // illegal-instruction exception RETIREFAIL } else {", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm3me.vv", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 3458, + 3465 + ] + }, + { + "chunk_id": "chunk_6a9ee2b1", + "text": "function clause execute (vsm4k(uimm, vs2)) = { if(LMUL*VLEN < EGW) then { handleillegal(); // illegal-instruction exception RETIREFAIL } else {", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm4k.vi", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 3661, + 3665 + ] + }, + { + "chunk_id": "chunk_be5fae05", + "text": "Operation:: [source,pseudocode] -- function clause execute (VSM4R(vd, vs2)) = { if(LMUL*VLEN < EGW) then { handleillegal(); // illegal-instruction exception RETIREFAIL } else {", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm4r.[vv,vs]", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 3807, + 3814 + ] + }, + { + "chunk_id": "chunk_f7f97d23", + "text": "foreach (i from egstart to eglen-1) { keyelem = if suffix \"vv\" then i else 0; {rk3 @ rk2 @ rk1 @ rk0} : bits(128) = getvelem(vs2, EGW=128, keyelem); {x3 @ x2 @ x1 @ x0} : bits(128) = getvelem(vd, EGW=128, i);", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm4r.[vv,vs]", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "unknown", + "line_range": [ + 3836, + 3839 + ] + }, + { + "chunk_id": "chunk_e4b62a77", + "text": "The elements in `vs2` are zero-extended to 2*`SEW` bits, then shifted left by the shift amount specified by either the corresponding elements of `vs1` (vector-vector), integer register `rs1` (vector-scalar), or an immediate value (vector-immediate).", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vwsll.[vv,vx,vi]", + "confidence": "high", + "parameter_class": "unknown", + "parameter_type": "enum", + "line_range": [ + 3960, + 3965 + ] + }, + { + "chunk_id": "chunk_4611802a", + "text": "Operation:: [source,sail] -- function clause execute (VWSLLVV(vs2, vs1, vd)) = { foreach (i from vstart to vl - 1) { setvelem(vd, EEW=2*SEW, i, getvelem(vs2, i) << (getvelem(vs1, i) & ((2*SEW)-1)) ) } RETIRESUCCESS }", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vwsll.[vv,vx,vi]", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 3967, + 3977 + ] + }, + { + "chunk_id": "chunk_074c75bf", + "text": "function clause execute (VWSLLVX(vs2, rs1, vd)) = { foreach (i from vstart to vl - 1) { setvelem(vd, EEW=2*SEW, i, getvelem(vs2, i) << (X(rs1) & ((2*SEW)-1)) ) } RETIRESUCCESS }", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vwsll.[vv,vx,vi]", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 3979, + 3986 + ] + }, + { + "chunk_id": "chunk_2ec7e2d8", + "text": "function clause execute (VWSLLVI(vs2, uimm[4:0], vd)) = { foreach (i from vstart to vl - 1) { setvelem(vd, EEW=2*SEW, i, getvelem(vs2, i) << (uimm[4:0] & ((2*SEW)-1)) ) } RETIRESUCCESS } --", + "source_file": "src/vector-crypto.adoc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vwsll.[vv,vx,vi]", + "confidence": "high", + "parameter_class": "CSR_controlled", + "parameter_type": "enum", + "line_range": [ + 3988, + 3996 + ] + } + ] + } +] \ No newline at end of file diff --git a/tools/llm-extraction/data/output/parameter_dataset.csv b/tools/llm-extraction/data/output/parameter_dataset.csv new file mode 100644 index 0000000000..0e965d688f --- /dev/null +++ b/tools/llm-extraction/data/output/parameter_dataset.csv @@ -0,0 +1,4312 @@ +chunk_id,file,line,section,text,parameter_class,parameter_type,confidence,reviewed,notes +chunk_72400c97,src/b-st-ext.adoc,7,Preamble > Bit Manipulation Extensions,"Thus, when implementing extensions with overlapping instructions, there is no redundancy in logic or encoding.",unknown,enum,high,False, +chunk_72f0e68d,src/b-st-ext.adoc,13,Preamble > Bit Manipulation Extensions,"The bitmanip extension follows the convention in RV64 that w-suffixed instructions (without a dot before the w) ignore the upper 32 bits of their inputs, operate on the least-significant 32 bits as signed values, and produce a 32-bit signed result that is sign-extended to XLEN.",non_CSR_parameter,range,high,False, +chunk_6f482888,src/b-st-ext.adoc,15,Preamble > Bit Manipulation Extensions,Bitmanip instructions with the suffix .uw have one operand that is an unsigned 32-bit value that is extracted from the least-significant 32 bits of the specified register.,non_CSR_parameter,range,high,False, +chunk_6cde1763,src/b-st-ext.adoc,17,Preamble > Bit Manipulation Extensions,"Bitmanip instructions with the suffixes .b, .h, and .w only look at the least-significant 8 bits, 16 bits, and 32 bits of the input (respectively) and produce an XLEN-wide result that is sign-extended or zero-extended, based on the specific instruction.",non_CSR_parameter,range,high,False, +chunk_8ae4c463,src/b-st-ext.adoc,102,"Preamble > Bit Manipulation Extensions > Zba: Extension for Address generation, Version 1.0.0",The slli.uw -- added in this extension -- can be used when the index is to be interpreted as an unsigned word.,unknown,unknown,high,False, +chunk_3bc70eec,src/b-st-ext.adoc,278,"Preamble > Bit Manipulation Extensions > ext:zbb[] Extension for Basic bit-manipulation, Version 1.0.0 > Sign extension and zero extension",These instructions perform the sign extension or zero extension of the least-significant 8 bits or 16 bits of the source register.,non_CSR_parameter,range,high,False, +chunk_ade33c39,src/b-st-ext.adoc,307,"Preamble > Bit Manipulation Extensions > ext:zbb[] Extension for Basic bit-manipulation, Version 1.0.0 > Bitwise rotation","However, where the shift-logical instructions shift in zeros, the rotate instructions shift in the bits that were shifted out of the other side of the value.",unknown,unknown,high,False, +chunk_b800648f,src/b-st-ext.adoc,362,"Preamble > Bit Manipulation Extensions > ext:zbb[] Extension for Basic bit-manipulation, Version 1.0.0 > OR Combine","One use-case is string-processing functions, such as *strlen* and *strcpy*, which can use *orc.b* to test for the terminating zero byte by counting the set bits in leading non-zero bytes in a word.",unknown,unknown,high,False, +chunk_2d7318b2,src/b-st-ext.adoc,593,"Preamble > Bit Manipulation Extensions > Zbkx: Extension for Crossbar permutations, Version 1.0.0","These instructions implement a ""lookup table"" for 4 and 8 bit elements inside the general purpose registers. rs1 is used as a vector of N-bit words, and rs2 as a vector of N-bit indices into rs1.",non_CSR_parameter,range,medium,False, +chunk_07a81f9e,src/b-st-ext.adoc,593,"Preamble > Bit Manipulation Extensions > Zbkx: Extension for Crossbar permutations, Version 1.0.0","Elements in rs1 are replaced by the indexed element in rs2, or zero if the index into rs2 is out of bounds.",unknown,unknown,high,False, +chunk_6f7ecc59,src/b-st-ext.adoc,1213,Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > clmul,foreach (i from 0 to (xlen - 1) by 1) { output = if ((rs2val >> i) & 1) then output ^ (rs1val << i); else output; },unknown,unknown,high,False, +chunk_9119292b,src/b-st-ext.adoc,1273,Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > clmulh,foreach (i from 1 to xlen by 1) { output = if ((rs2val >> i) & 1) then output ^ (rs1val >> (xlen - i)); else output; },unknown,unknown,high,False, +chunk_9f291ed8,src/b-st-ext.adoc,1335,Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > clmulr,foreach (i from 0 to (xlen - 1) by 1) { output = if ((rs2val >> i) & 1) then output ^ (rs1val >> (xlen - i - 1)); else output; },unknown,unknown,high,False, +chunk_c467946b,src/b-st-ext.adoc,1389,Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > clz,"Accordingly, if the input is 0, the output is XLEN, and if the most-significant bit of the input is a 1, the output is 0.",unknown,unknown,high,False, +chunk_c6b7c07b,src/b-st-ext.adoc,1398,Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > clz,function HighestSetBit x = { foreach (i from (xlen - 1) to 0 by 1 in dec) if [x[i]] 0b1 then return(i) else (); return -1; },unknown,unknown,high,False, +chunk_39d5e5ae,src/b-st-ext.adoc,1454,Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > clzw,function HighestSetBit32 x = { foreach (i from 31 to 0 by 1 in dec) if [x[i]] 0b1 then return(i) else (); return -1; },unknown,unknown,high,False, +chunk_3448113b,src/b-st-ext.adoc,1509,Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > cpop,foreach (i from 0 to (xlen - 1) in inc) if rs[i] 0b1 then bitcount = bitcount + 1 else ();,unknown,unknown,high,False, +chunk_0c22b02e,src/b-st-ext.adoc,1569,Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > cpopw,foreach (i from 0 to 31 in inc) if val[i] 0b1 then bitcount = bitcount + 1 else ();,unknown,unknown,high,False, +chunk_3abf2f8d,src/b-st-ext.adoc,1611,Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > ctz,"Accordingly, if the input is 0, the output is XLEN, and if the least-significant bit of the input is a 1, the output is 0.",unknown,unknown,high,False, +chunk_4586d663,src/b-st-ext.adoc,1621,Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > ctz,function LowestSetBit x = { foreach (i from 0 to (xlen - 1) by 1 in dec) if [x[i]] 0b1 then return(i) else (); return xlen; },unknown,unknown,high,False, +chunk_3e8b7f15,src/b-st-ext.adoc,1667,Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > ctzw,"Accordingly, if the least-significant word is 0, the output is 32, and if the least-significant bit of the input is a 1, the output is 0.",unknown,unknown,high,False, +chunk_7ac216f1,src/b-st-ext.adoc,1676,Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > ctzw,function LowestSetBit32 x = { foreach (i from 0 to 31 by 1 in dec) if [x[i]] 0b1 then return(i) else (); return 32; },unknown,unknown,high,False, +chunk_8547b17a,src/b-st-ext.adoc,1732,Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > max,let result = if rs1val Bit Manipulation Extensions > Instructions (in alphabetical order) > maxu,let result = if rs1val Bit Manipulation Extensions > Instructions (in alphabetical order) > min,let result = if rs1val Bit Manipulation Extensions > Instructions (in alphabetical order) > minu,let result = if rs1val Bit Manipulation Extensions > Instructions (in alphabetical order) > orc.b,"This sets the bits of each byte in the result rd to all zeros if no bit within the respective byte of rs is set, or to all ones if any bit within the respective byte of rs is set.",unknown,unknown,high,False, +chunk_8367c35b,src/b-st-ext.adoc,1954,Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > orc.b,foreach (i from 0 to (xlen - 8) by 8) { output[(i + 7)..i] = if input[(i + 7)..i] 0 then 0b00000000 else 0b11111111; },unknown,unknown,high,False, +chunk_a13aaf9e,src/b-st-ext.adoc,2074,Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > pack,"Hence, for RV32, any extension that contains the `pack` instruction also contains the `zext.h` instruction (but not necessarily the `c.zext.h` instruction, which is only guaranteed to exist if both the Zcb and Zbb extensions are implemented).",unknown,unknown,high,False, +chunk_9d078cff,src/b-st-ext.adoc,2182,Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > packw,"Hence, for RV64, any extension that contains the `packw` instruction also contains the `zext.h` instruction (but not necessarily the `c.zext.h` instruction, which is only guaranteed to exist if both the Zcb and Zbb extensions are implemented).",unknown,unknown,high,False, +chunk_3fa701c7,src/b-st-ext.adoc,2351,Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > rol,"Operation:: [source,sail] -- let shamt = if xlen 32 then X(rs2)[4..0] else X(rs2)[5..0]; let result = (X(rs1) (xlen - shamt));",unknown,unknown,high,False, +chunk_5d1d4830,src/b-st-ext.adoc,2403,Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > rolw,The resulting word value is sign-extended by copying bit 31 to all of the more-significant bits.,unknown,enum,high,False, +chunk_94adf6c4,src/b-st-ext.adoc,2460,Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > ror,"Operation:: [source,sail] -- let shamt = if xlen 32 then X(rs2)[4..0] else X(rs2)[5..0]; let result = (X(rs1) >> shamt) | (X(rs1) << (xlen - shamt));",unknown,unknown,high,False, +chunk_724c674f,src/b-st-ext.adoc,2530,Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > rori,"Operation:: [source,sail] -- let shamt = if xlen 32 then shamt[4..0] else shamt[5..0]; let result = (X(rs1) >> shamt) | (X(rs1) << (xlen - shamt));",unknown,unknown,high,False, +chunk_6c1bc4c4,src/b-st-ext.adoc,2582,Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > roriw,The resulting word value is sign-extended by copying bit 31 to all of the more-significant bits.,unknown,enum,high,False, +chunk_3c467591,src/b-st-ext.adoc,2639,Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > rorw,The resultant word is sign-extended by copying bit 31 to all of the more-significant bits.,unknown,enum,high,False, +chunk_d381403f,src/b-st-ext.adoc,3241,Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > xperm8,The rs1 register contains a vector of XLEN/8 8-bit elements.,non_CSR_parameter,range,medium,False, +chunk_e09be124,src/b-st-ext.adoc,3241,Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > xperm8,The rs2 register contains a vector of XLEN/8 8-bit indexes.,non_CSR_parameter,range,medium,False, +chunk_0c7247ac,src/b-st-ext.adoc,3303,Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > xperm4,The rs1 register contains a vector of XLEN/4 4-bit elements.,non_CSR_parameter,range,medium,False, +chunk_e09dbd4b,src/b-st-ext.adoc,3303,Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > xperm4,The rs2 register contains a vector of XLEN/4 4-bit indexes.,non_CSR_parameter,range,medium,False, +chunk_a7b3ed7d,src/intro.adoc,146,Preamble > Introduction > RISC-V ISA Overview,"A RISC-V ISA is defined as a base integer ISA, which must be present in any implementation, plus optional extensions to the base ISA.",non_CSR_parameter,enum,very_high,False, +chunk_934647e2,src/intro.adoc,172,Preamble > Introduction > RISC-V ISA Overview,"For this purpose, we divide each RISC-V instruction-set encoding space (and related encoding spaces such as the CSRs) into three disjoint categories: standard, reserved, and custom.",CSR_controlled,enum,high,False, +chunk_6db06846,src/intro.adoc,172,Preamble > Introduction > RISC-V ISA Overview,Custom encodings shall never be used for standard extensions and are made available for vendor-specific non-standard extensions.,non_CSR_parameter,enum,very_high,False, +chunk_9ee31d36,src/intro.adoc,313,Preamble > Introduction > Base Instruction-Length Encoding,The base RISC-V ISA has fixed-length 32-bit instructions that must be naturally aligned on 32-bit boundaries.,non_CSR_parameter,range,very_high,False, +chunk_545961c8,src/intro.adoc,439,"Preamble > Introduction > Exceptions, Traps, and Interrupts",Instruction encodings that are not defined here and not defined by some other means may cause a fatal trap.,non_CSR_parameter,enum,high,False, +chunk_fa950ca0,src/naming.adoc,65,Preamble > ISA Extension Naming Conventions > Additional Standard Unprivileged Extension Names,"All multi-letter extensions, including those with the ""Z"" prefix, must be separated from other multi-letter extensions by an underscore, e.g., ""RV32IMACZicsrZifencei"".",CSR_controlled,enum,very_high,False, +chunk_529b547b,src/naming.adoc,74,Preamble > ISA Extension Naming Conventions > User-Level Instruction-Set Extension Names,"Standard user-level extensions should be listed after standard unprivileged extensions, and like other multi-letter extensions, must be separated from other multi-letter extensions by an underscore.",non_CSR_parameter,enum,very_high,False, +chunk_59a5d0ad,src/naming.adoc,92,Preamble > ISA Extension Naming Conventions > Supervisor-Level Instruction-Set Extension Names,"Standard supervisor-level extensions should be listed after standard unprivileged and user-level extensions, and like other multi-letter extensions, must be separated from other multi-letter extensions by an underscore.",non_CSR_parameter,enum,very_high,False, +chunk_fea06266,src/naming.adoc,103,Preamble > ISA Extension Naming Conventions > Hypervisor-Level Instruction-Set Extension Names,"Standard hypervisor-level extensions should be listed after standard unprivileged, user-level and supervisor-level extensions, and like other multi-letter extensions, must be separated from other multi-letter extensions by an underscore.",SW_rule,enum,very_high,False, +chunk_2a35f724,src/naming.adoc,120,Preamble > ISA Extension Naming Conventions > Machine-Level Instruction-Set Extension Names,"Standard machine-level extensions should be listed after standard lesser-privileged extensions, and like other multi-letter extensions, must be separated from other multi-letter extensions by an underscore.",non_CSR_parameter,enum,very_high,False, +chunk_be42535c,src/naming.adoc,132,Preamble > ISA Extension Naming Conventions > Non-Standard Extension Names,"Non-standard extensions must be listed after all standard extensions, and, like other multi-letter extensions, must be separated from other multi-letter extensions by an underscore.",non_CSR_parameter,enum,very_high,False, +chunk_3b6a96d7,src/naming.adoc,149,Preamble > ISA Extension Naming Conventions > Version Numbers,"Because the ""P"" extension for Packed SIMD can be confused for the decimal point in a version number, it must be preceded by an underscore if it follows another extension with a version number.",non_CSR_parameter,binary,very_high,False, +chunk_fbb0d188,src/naming.adoc,155,Preamble > ISA Extension Naming Conventions > Version Numbers,"Changes in major version numbers imply a loss of backwards compatibility, whereas changes in only the minor version number must be backwards-compatible.",non_CSR_parameter,enum,very_high,False, +chunk_efe787ec,src/priv/cfi.adoc,18,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing-Pad-Enabled (LPE) State,The term `xLPE` is used to determine if forward-edge CFI using landing pads provided by the Zicfilp extension is enabled at a privilege mode.,unknown,binary,high,False, +chunk_59acce82,src/priv/cfi.adoc,21,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing-Pad-Enabled (LPE) State,"When S-mode is implemented, it is determined as follows:",unknown,unknown,high,False, +chunk_e3dcab7c,src/priv/cfi.adoc,34,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing-Pad-Enabled (LPE) State,"When S-mode is not implemented, it is determined as follows:",unknown,unknown,high,False, +chunk_4895ad36,src/priv/cfi.adoc,50,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing-Pad-Enabled (LPE) State > Preserving Expected Landing Pad State on Traps,"A trap may need to be delivered to the same or to a higher privilege mode upon completion of `JALR`/`C.JALR`/`C.JR`, but before the instruction at the target of indirect call/jump was decoded, due to:",non_CSR_parameter,enum,high,False, +chunk_6e558ddf,src/priv/cfi.adoc,54,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing-Pad-Enabled (LPE) State > Preserving Expected Landing Pad State on Traps,"Asynchronous interrupts. * Synchronous exceptions with priority higher than that of a software-check exception with `xtval` set to ""landing pad fault (code=2)"" (See of Privileged Specification).",SW_rule,unknown,high,False, +chunk_f4d03112,src/priv/cfi.adoc,59,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing-Pad-Enabled (LPE) State > Preserving Expected Landing Pad State on Traps,The software-check exception caused by Zicfilp has higher priority than an illegal-instruction exception but lower priority than instruction access-fault.,SW_rule,unknown,high,False, +chunk_e3544eaf,src/priv/cfi.adoc,63,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing-Pad-Enabled (LPE) State > Preserving Expected Landing Pad State on Traps,The software-check exception due to the instruction not being an `LPAD` instruction when `ELP` is `LPEXPECTED` or a software-check exception caused by the `LPAD` instruction itself leads to a trap being delivered to the same or to a higher privilege mode.,SW_rule,enum,high,False, +chunk_46ce2b58,src/priv/cfi.adoc,69,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing-Pad-Enabled (LPE) State > Preserving Expected Landing Pad State on Traps,"In such cases, the `ELP` prior to the trap, the previous `ELP`, must be preserved by the trap delivery such that it can be restored on a return from the trap.",non_CSR_parameter,binary,very_high,False, +chunk_2afc3f0c,src/priv/cfi.adoc,69,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing-Pad-Enabled (LPE) State > Preserving Expected Landing Pad State on Traps,"To store the previous `ELP` state on trap delivery to M-mode, an `MPELP` bit is provided in the `mstatus` CSR.",CSR_controlled,enum,high,False, +chunk_841fe5d9,src/priv/cfi.adoc,69,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing-Pad-Enabled (LPE) State > Preserving Expected Landing Pad State on Traps,"To store the previous `ELP` state on trap delivery to S/HS-mode, an `SPELP` bit is provided in the `mstatus` CSR.",CSR_controlled,enum,high,False, +chunk_430ad9ab,src/priv/cfi.adoc,69,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing-Pad-Enabled (LPE) State > Preserving Expected Landing Pad State on Traps,The `SPELP` bit in `mstatus` can be accessed through the `sstatus` CSR.,CSR_controlled,enum,high,False, +chunk_947c4270,src/priv/cfi.adoc,69,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing-Pad-Enabled (LPE) State > Preserving Expected Landing Pad State on Traps,"To store the previous `ELP` state on traps to VS-mode, a `SPELP` bit is defined in the `vsstatus` (VS-modes version of `sstatus`).",CSR_controlled,enum,high,False, +chunk_6dabd988,src/priv/cfi.adoc,69,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing-Pad-Enabled (LPE) State > Preserving Expected Landing Pad State on Traps,"To store the previous `ELP` state on transition to Debug Mode, a `pelp` bit is defined in the `dcsr` register.",CSR_controlled,enum,high,False, +chunk_ec92d094,src/priv/cfi.adoc,79,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing-Pad-Enabled (LPE) State > Preserving Expected Landing Pad State on Traps,"When a trap is taken into privilege mode `x`, the `xPELP` is set to `ELP` and `ELP` is set to `NOLPEXPECTED`.",unknown,enum,high,False, +chunk_304cdc22,src/priv/cfi.adoc,83,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing-Pad-Enabled (LPE) State > Preserving Expected Landing Pad State on Traps,"An `MRET` or `SRET` instruction is used to return from a trap in M-mode or S-mode, respectively.",unknown,unknown,high,False, +chunk_1c7e4dde,src/priv/cfi.adoc,90,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing-Pad-Enabled (LPE) State > Preserving Expected Landing Pad State on Traps,"Upon entry into Debug Mode, the `pelp` bit in `dcsr` is updated with the `ELP` at the privilege level the hart was previously in, and the `ELP` is set to `NOLPEXPECTED`.",CSR_controlled,enum,high,False, +chunk_66ffceca,src/priv/cfi.adoc,97,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing-Pad-Enabled (LPE) State > Preserving Expected Landing Pad State on Traps,See also for semantics added to the RNMI trap and the MNRET instruction when this extension is implemented.,unknown,unknown,high,False, +chunk_b72e9503,src/priv/cfi.adoc,109,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Pointer (`ssp`) CSR access control,"Attempts to access the `ssp` CSR may result in either an illegal-instruction exception or a virtual-instruction exception, contingent upon the state of the *x*`envcfg.SSE` fields.",CSR_controlled,enum,high,False, +chunk_8a6ad9f0,src/priv/cfi.adoc,114,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Pointer (`ssp`) CSR access control,"If the privilege mode is less than M and `menvcfg.SSE` is 0, an illegal-instruction exception is raised. *",CSR_controlled,range,high,False, +chunk_cb449656,src/priv/cfi.adoc,114,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Pointer (`ssp`) CSR access control,"Otherwise, if in U-mode and `senvcfg.SSE` is 0, an illegal-instruction exception is raised. *",CSR_controlled,enum,high,False, +chunk_a5ab2e84,src/priv/cfi.adoc,114,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Pointer (`ssp`) CSR access control,"Otherwise, if in VS-mode and `henvcfg.SSE` is 0, a virtual-instruction exception is raised. *",CSR_controlled,enum,high,False, +chunk_9b132194,src/priv/cfi.adoc,114,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Pointer (`ssp`) CSR access control,"Otherwise, if in VU-mode and either `henvcfg.SSE` or `senvcfg.SSE` is 0, a virtual-instruction exception is raised. *",CSR_controlled,enum,high,False, +chunk_d0a9ffe4,src/priv/cfi.adoc,114,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Pointer (`ssp`) CSR access control,"Otherwise, the access is allowed.",unknown,unknown,high,False, +chunk_674b797a,src/priv/cfi.adoc,126,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow-Stack-Enabled (SSE) State,The term `xSSE` is used to determine if backward-edge CFI using shadow stacks provided by the Zicfiss extension is enabled at a privilege mode.,unknown,binary,high,False, +chunk_73e96a24,src/priv/cfi.adoc,129,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow-Stack-Enabled (SSE) State,"When S-mode is implemented, it is determined as follows:",unknown,unknown,high,False, +chunk_220a4e5f,src/priv/cfi.adoc,142,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow-Stack-Enabled (SSE) State,"When S-mode is not implemented, then `xSSE` is 0 at both M and U privilege modes.",unknown,enum,high,False, +chunk_dfde7c23,src/priv/cfi.adoc,153,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Memory Protection,"When `menvcfg.SSE=0`, this encoding remains reserved.",CSR_controlled,enum,high,False, +chunk_7f4b2a9c,src/priv/cfi.adoc,153,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Memory Protection,"Similarly, when `V=1` and `henvcfg.SSE=0`, this encoding remains reserved at `VS` and `VU` levels.",CSR_controlled,enum,high,False, +chunk_7cb98c59,src/priv/cfi.adoc,159,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Memory Protection,"If `satp.MODE` (or `vsatp.MODE` when `V=1`) is set to `Bare` and the effective privilege mode is less than M, shadow stack instructions raise a store/AMO access-fault exception.",CSR_controlled,range,high,False, +chunk_a0d66d71,src/priv/cfi.adoc,159,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Memory Protection,"When the effective privilege mode is M, memory access by an `SSAMOSWAP.W/D` instruction results in a store/AMO access-fault exception.",non_CSR_parameter,enum,high,False, +chunk_cf57eff0,src/priv/cfi.adoc,164,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Memory Protection,Attempts will raise a store/AMO access-fault exception.,non_CSR_parameter,unknown,high,False, +chunk_08a7c3f9,src/priv/cfi.adoc,164,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Memory Protection,Access to a SS page using cache-block operation (`CBO.*`) instructions is not permitted.,non_CSR_parameter,unknown,medium,False, +chunk_4fa24c19,src/priv/cfi.adoc,164,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Memory Protection,Such accesses will raise a store/AMO access-fault exception.,non_CSR_parameter,unknown,high,False, +chunk_3147dcff,src/priv/cfi.adoc,164,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Memory Protection,"Implicit accesses, including instruction fetches to an SS page, are not permitted.",non_CSR_parameter,unknown,medium,False, +chunk_c1f2e8e4,src/priv/cfi.adoc,164,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Memory Protection,Such accesses will raise an access-fault exception appropriate to the access type.,non_CSR_parameter,unknown,high,False, +chunk_301e1065,src/priv/cfi.adoc,173,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Memory Protection,"If a shadow stack (SS) instruction raises an access-fault, page-fault, or guest-page-fault exception that is supposed to indicate the original instruction type (load or store/AMO), then the reported exception cause is respectively a store/AMO access fault (code 7), a store/AMO page fault (code 15), or a store/AMO guest-page fault (code 23).",non_CSR_parameter,unknown,high,False, +chunk_20916096,src/priv/cfi.adoc,182,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Memory Protection,"Should a shadow stack instruction access a page that is not designated as a shadow stack page and is not marked as read-only (`pte.xwr=001`), a store/AMO access-fault exception will be invoked.",non_CSR_parameter,enum,high,False, +chunk_5b44518a,src/priv/cfi.adoc,182,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Memory Protection,"Conversely, if the page being accessed by a shadow stack instruction is a read-only page, a store/AMO page-fault exception will be triggered.",unknown,unknown,high,False, +chunk_8edde9db,src/priv/cfi.adoc,191,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Memory Protection,"If the virtual address in `ssp` is not `XLEN` aligned, then the `SSPUSH`/ `C.SSPUSH`/`SSPOPCHK`/`C.SSPOPCHK` instructions cause a store/AMO access-fault exception.",unknown,unknown,high,False, +chunk_4d03ceda,src/priv/cfi.adoc,196,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Memory Protection,"If the memory referenced by `SSPUSH`/`C.SSPUSH`/`SSPOPCHK`/`C.SSPOPCHK`/`SSAMOSWAP.W/D` instructions is not idempotent, then the instructions cause a store/AMO access-fault exception.",unknown,unknown,high,False, +chunk_8f51959d,src/priv/cfi.adoc,206,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Memory Protection,"When G-stage page tables are active, the shadow stack instructions that access memory require the G-stage page table to have read-write permission for the accessed memory; else a store/AMO guest-page-fault exception is raised.",non_CSR_parameter,unknown,high,False, +chunk_2f23258e,src/priv/cfi.adoc,214,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Memory Protection,The PMA checks are extended to require memory referenced by shadow stack instructions to be idempotent.,unknown,unknown,medium,False, +chunk_2b6e5817,src/priv/cfi.adoc,214,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Memory Protection,The PMP checks are extended to require read-write permission for memory accessed by shadow stack instructions.,unknown,unknown,medium,False, +chunk_e1318df1,src/priv/cfi.adoc,214,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Memory Protection,If the PMP does not provide read-write permissions or if the accessed memory is not idempotent then a store/AMO access-fault exception is raised.,non_CSR_parameter,unknown,high,False, +chunk_8973f82e,src/priv/csrs.adoc,3,Preamble > Control and Status Registers (CSRs),The SYSTEM major opcode is used to encode all privileged instructions in the RISC-V ISA.,unknown,unknown,high,False, +chunk_1761e9f7,src/priv/csrs.adoc,3,Preamble > Control and Status Registers (CSRs),"These can be divided into two main classes: those that atomically read-modify-write control and status registers (CSRs), which are defined in the Zicsr extension, and all other privileged instructions.",CSR_controlled,enum,high,False, +chunk_23a6edb1,src/priv/csrs.adoc,3,Preamble > Control and Status Registers (CSRs),The privileged architecture requires the Zicsr extension; which other privileged instructions are required depends on the privileged-architecture feature set.,CSR_controlled,enum,high,False, +chunk_195e0171,src/priv/csrs.adoc,11,Preamble > Control and Status Registers (CSRs),"In addition to the unprivileged state described in Volume I of this manual, an implementation may contain additional CSRs, accessible by some subset of the privilege levels using the CSR instructions described in .",CSR_controlled,enum,high,False, +chunk_c9e91ae1,src/priv/csrs.adoc,11,Preamble > Control and Status Registers (CSRs),"In this chapter, we map out the CSR address space.",CSR_controlled,enum,high,False, +chunk_69affc30,src/priv/csrs.adoc,11,Preamble > Control and Status Registers (CSRs),"The following chapters describe the function of each of the CSRs according to privilege level, as well as the other privileged instructions which are generally closely associated with a particular privilege level.",CSR_controlled,enum,high,False, +chunk_b708cd0f,src/priv/csrs.adoc,21,Preamble > Control and Status Registers (CSRs),Standard CSRs do not have side effects on reads but may have side effects on writes.,CSR_controlled,enum,high,False, +chunk_8515789d,src/priv/csrs.adoc,26,Preamble > Control and Status Registers (CSRs) > CSR Address Mapping Conventions,"The standard RISC-V ISA sets aside a 12-bit encoding space (csr[11:0]) for up to 4,096 CSRs.",CSR_controlled,range,high,False, +chunk_5f25609a,src/priv/csrs.adoc,32,Preamble > Control and Status Registers (CSRs) > CSR Address Mapping Conventions,Instructions that access a non-existent CSR are reserved.,CSR_controlled,enum,high,False, +chunk_7952e257,src/priv/csrs.adoc,32,Preamble > Control and Status Registers (CSRs) > CSR Address Mapping Conventions,"Attempts to access a CSR without appropriate privilege level raise illegal-instruction exceptions or, as described in , virtual-instruction exceptions.",CSR_controlled,enum,high,False, +chunk_2f29d175,src/priv/csrs.adoc,32,Preamble > Control and Status Registers (CSRs) > CSR Address Mapping Conventions,"Attempts to write a read-only register raise illegal-instruction exceptions. A read/write register might also contain some bits that are read-only, in which case writes to the read-only bits are ignored.",CSR_controlled,unknown,high,False, +chunk_6aa4f4cf,src/priv/csrs.adoc,40,Preamble > Control and Status Registers (CSRs) > CSR Address Mapping Conventions,also indicates the convention to allocate CSR addresses between standard and custom uses.,CSR_controlled,enum,high,False, +chunk_4031e959,src/priv/csrs.adoc,40,Preamble > Control and Status Registers (CSRs) > CSR Address Mapping Conventions,The CSR addresses designated for custom uses will not be redefined by future standard extensions.,CSR_controlled,enum,high,False, +chunk_b4453927,src/priv/csrs.adoc,45,Preamble > Control and Status Registers (CSRs) > CSR Address Mapping Conventions,Machine-mode standard read-write CSRs `0x7A0`-`0x7BF` are reserved for use by the debug system.,CSR_controlled,enum,high,False, +chunk_e415d9c1,src/priv/csrs.adoc,45,Preamble > Control and Status Registers (CSRs) > CSR Address Mapping Conventions,"Of these CSRs, `0x7A0`-`0x7AF` are accessible to machine mode, whereas `0x7B0`-`0x7BF` are only visible to debug mode.",CSR_controlled,enum,high,False, +chunk_c8e046d9,src/priv/csrs.adoc,45,Preamble > Control and Status Registers (CSRs) > CSR Address Mapping Conventions,Implementations should raise illegal-instruction exceptions on machine-mode access to the latter set of registers.,non_CSR_parameter,enum,high,False, +chunk_06922558,src/priv/csrs.adoc,107,Preamble > Control and Status Registers (CSRs) > CSR Listing,list the CSRs that have currently been allocated CSR addresses.,CSR_controlled,enum,high,False, +chunk_6cfe6753,src/priv/csrs.adoc,107,Preamble > Control and Status Registers (CSRs) > CSR Listing,"The timers, counters, and floating-point CSRs are standard unprivileged CSRs.",CSR_controlled,enum,high,False, +chunk_31441a1a,src/priv/csrs.adoc,107,Preamble > Control and Status Registers (CSRs) > CSR Listing,"The other registers are used by privileged code, as described in the following chapters.",unknown,unknown,high,False, +chunk_32e53083,src/priv/csrs.adoc,166,Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V unprivileged CSR addresses,4+^|Unprivileged Zicfiss extension CSR |`0x011` + |URW + |`ssp` + |Shadow Stack Pointer. +,CSR_controlled,enum,high,False, +chunk_3826acc6,src/priv/csrs.adoc,172,Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V unprivileged CSR addresses,4+^|Unprivileged Entropy Source Extension CSR |`0x015` + |URW + |`seed` + |Seed for cryptographic random bit generators. +,CSR_controlled,enum,high,False, +chunk_a41af058,src/priv/csrs.adoc,186,Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V unprivileged CSR addresses,"|`0xC00` + `0xC01` + `0xC02` + `0xC03` + `0xC04` + {nbsp} + `0xC1F` + `0xC80` + `0xC81` + `0xC82` + `0xC83` + `0xC84` + {nbsp} + `0xC9F` |URO + URO + URO + URO + URO + {nbsp} + URO + URO + URO + URO + URO + URO + {nbsp} + URO |`cycle` + `time` + `instret` + `hpmcounter3` + `hpmcounter4` + {vertical-ellipsis} + `hpmcounter31` + `cycleh` + `timeh` + `instreth` + `hpmcounter3h` + `hpmcounter4h` + {vertical-ellipsis} + `hpmcounter31h` |Cycle counter for RDCYCLE instruction. + Timer for RDTIME instruction. + Instructions-retired counter for RDINSTRET instruction. + Performance-monitoring counter. + Performance-monitoring counter. + {nbsp} + Performance-monitoring counter. + Upper 32 bits of `cycle`, RV32 only. + Upper 32 bits of `time`, RV32 only. + Upper 32 bits of `instret`, RV32 only. + Upper 32 bits of `hpmcounter3`, RV32 only. + Upper 32 bits of `hpmcounter4`, RV32 only. + {nbsp} + Upper 32 bits of `hpmcounter31`, RV32 only. |",non_CSR_parameter,range,high,False, +chunk_071fe19c,src/priv/csrs.adoc,274,Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V supervisor-level CSR addresses,|`0x10A` |SRW |`senvcfg` |Supervisor environment configuration register.,CSR_controlled,enum,high,False, +chunk_4b18d62a,src/priv/csrs.adoc,278,Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V supervisor-level CSR addresses,|`0x120` |SRW |`scountinhibit` |Supervisor counter-inhibit register.,unknown,unknown,high,False, +chunk_0ef5e8e1,src/priv/csrs.adoc,340,Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V supervisor-level CSR addresses,|`0x180` |SRW |`satp` |Supervisor address translation and protection.,CSR_controlled,enum,high,False, +chunk_2d327a9c,src/priv/csrs.adoc,344,Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V supervisor-level CSR addresses,"|`0x14D` + `0x15D` |SRW + SRW |`stimecmp` + `stimecmph` |Supervisor timer compare. + Upper 32 bits of `stimecmp`, RV32 only.",non_CSR_parameter,range,high,False, +chunk_ad9b9893,src/priv/csrs.adoc,355,Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V supervisor-level CSR addresses,|`0x5A8` |SRW |`scontext` |Supervisor-mode context register.,unknown,unknown,high,False, +chunk_9fea1677,src/priv/csrs.adoc,357,Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V supervisor-level CSR addresses,4+^|Supervisor Resource Management Configuration |`0x181` |SRW |`srmcfg` |Supervisor Resource Management Configuration.,unknown,unknown,high,False, +chunk_8bb4e513,src/priv/csrs.adoc,436,Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V hypervisor and VS CSR addresses,|`0x643` + `0x644` + `0x645` + `0x64A` + `0xE12` |HRW + HRW + HRW + HRW + HRO |`htval` + `hip` + `hvip` + `htinst` + `hgeip` |Hypervisor trap value. + Hypervisor interrupt pending. + Hypervisor virtual interrupt pending. + Hypervisor trap instruction (transformed). + Hypervisor guest external interrupt pending.,SW_rule,unknown,high,False, +chunk_aa44c34d,src/priv/csrs.adoc,470,Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V hypervisor and VS CSR addresses,|`0x680` |HRW |`hgatp` |Hypervisor guest address translation and protection.,CSR_controlled,enum,high,False, +chunk_af5d8ec8,src/priv/csrs.adoc,474,Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V hypervisor and VS CSR addresses,|`0x6A8` |HRW |`hcontext` |Hypervisor-mode context register.,SW_rule,unknown,high,False, +chunk_778dc272,src/priv/csrs.adoc,478,Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V hypervisor and VS CSR addresses,"|`0x605` + `0x615` |HRW + HRW |`htimedelta` + `htimedeltah` |Delta for VS/VU-mode timer. + Upper 32 bits of `htimedelta`, RV32 only.",non_CSR_parameter,range,high,False, +chunk_f3a3ec8c,src/priv/csrs.adoc,593,Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V hypervisor and VS CSR addresses,"|`0x24D` + `0x25D` |HRW + HRW |`vstimecmp` + `vstimecmph` |Virtual supervisor timer compare. + Upper 32 bits of `vstimecmp`, RV32 only.",non_CSR_parameter,range,high,False, +chunk_32483a30,src/priv/csrs.adoc,622,Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V machine-level CSR addresses,|`0xF11` + `0xF12` + `0xF13` + `0xF14` + `0xF15` |MRO + MRO + MRO + MRO + MRO |`mvendorid` + `marchid` + `mimpid` + `mhartid` + `mconfigptr` |Vendor ID. + Architecture ID. + Implementation ID. + Hardware thread ID. + Pointer to configuration data structure.,CSR_controlled,enum,high,False, +chunk_d86a030e,src/priv/csrs.adoc,865,Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V machine-level CSR addresses,"|`0xB00` + `0xB02` + `0xB03` + `0xB04` + {nbsp} + `0xB1F` + `0xB80` + `0xB82` + `0xB83` + `0xB84` + {nbsp} + `0xB9F` |MRW + MRW + MRW + MRW + {nbsp} + MRW + MRW + MRW + MRW + MRW + {nbsp} + MRW + |`mcycle` + `minstret` + `mhpmcounter3` + `mhpmcounter4` + {vertical-ellipsis} + `mhpmcounter31` + `mcycleh` + `minstreth` + `mhpmcounter3h` + `mhpmcounter4h` + {vertical-ellipsis} + `mhpmcounter31h` |Machine cycle counter. + Machine instructions-retired counter. + Machine performance-monitoring counter. + Machine performance-monitoring counter. + {nbsp} + Machine performance-monitoring counter. + Upper 32 bits of `mcycle`, RV32 only. + Upper 32 bits of `minstret`, RV32 only. + Upper 32 bits of `mhpmcounter3`, RV32 only. + Upper 32 bits of `mhpmcounter4`, RV32 only. + {nbsp} + Upper 32 bits of `mhpmcounter31`, RV32 only.",CSR_controlled,range,high,False, +chunk_c6c8e934,src/priv/csrs.adoc,977,Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V machine-level CSR addresses,|`0x7A0` + `0x7A1` + `0x7A2` + `0x7A3` + `0x7A4` + `0x7A5` + `0x7A8` |MRW + MRW + MRW + MRW + MRW + MRW + MRW |`tselect` + `tdata1` + `tdata2` + `tdata3` + `tinfo` + `tcontrol` + `mcontext`,CSR_controlled,enum,high,False, +chunk_ba07850f,src/priv/csrs.adoc,1111,Preamble > Control and Status Registers (CSRs) > CSR Field Specifications,The following definitions and abbreviations are used in specifying the behavior of fields within the CSRs.,CSR_controlled,enum,high,False, +chunk_1fbc611a,src/priv/csrs.adoc,1116,"Preamble > Control and Status Registers (CSRs) > CSR Field Specifications > Reserved Writes Preserve Values, Reads Ignore Values (WPRI)",Some whole read/write fields are reserved for future use.,CSR_controlled,enum,high,False, +chunk_abb3faf2,src/priv/csrs.adoc,1116,"Preamble > Control and Status Registers (CSRs) > CSR Field Specifications > Reserved Writes Preserve Values, Reads Ignore Values (WPRI)","Software should ignore the values read from these fields, and should preserve the values held in these fields when writing values to other fields of the same register.",SW_rule,enum,high,False, +chunk_14450f18,src/priv/csrs.adoc,1116,"Preamble > Control and Status Registers (CSRs) > CSR Field Specifications > Reserved Writes Preserve Values, Reads Ignore Values (WPRI)","For forward compatibility, implementations that do not furnish these fields must make them read-only zero.",CSR_controlled,binary,very_high,False, +chunk_03a2da4f,src/priv/csrs.adoc,1116,"Preamble > Control and Status Registers (CSRs) > CSR Field Specifications > Reserved Writes Preserve Values, Reads Ignore Values (WPRI)",These fields are labeled *WPRI* in the register descriptions.,CSR_controlled,enum,very_high,False, +chunk_d8593f3b,src/priv/csrs.adoc,1125,Preamble > Control and Status Registers (CSRs) > CSR Field Specifications > Write/Read Only Legal Values (WLRL),"Some read/write CSR fields specify behavior for only a subset of possible bit encodings, with other bit encodings reserved.",CSR_controlled,enum,high,False, +chunk_fa70d9e3,src/priv/csrs.adoc,1125,Preamble > Control and Status Registers (CSRs) > CSR Field Specifications > Write/Read Only Legal Values (WLRL),These fields are labeled *WLRL* in the register descriptions.,CSR_controlled,enum,very_high,False, +chunk_7562b968,src/priv/csrs.adoc,1134,Preamble > Control and Status Registers (CSRs) > CSR Field Specifications > Write/Read Only Legal Values (WLRL),Implementations are permitted but not required to raise an illegal-instruction exception if an instruction attempts to write a non-supported value to a *WLRL* field.,CSR_controlled,enum,very_high,False, +chunk_20b33988,src/priv/csrs.adoc,1134,Preamble > Control and Status Registers (CSRs) > CSR Field Specifications > Write/Read Only Legal Values (WLRL),"Implementations can return arbitrary bit patterns on the read of a *WLRL* field when the last write was of an illegal value, but the value returned should deterministically depend on the illegal written value and the value of the field prior to the write.",CSR_controlled,enum,very_high,False, +chunk_7ee5d986,src/priv/csrs.adoc,1144,"Preamble > Control and Status Registers (CSRs) > CSR Field Specifications > Write Any Values, Reads Legal Values (WARL)","Some read/write CSR fields are only defined for a subset of bit encodings, but allow any value to be written while guaranteeing to return a legal value whenever read.",CSR_controlled,enum,high,False, +chunk_1a19fc57,src/priv/csrs.adoc,1144,"Preamble > Control and Status Registers (CSRs) > CSR Field Specifications > Write Any Values, Reads Legal Values (WARL)","Assuming that writing the CSR has no other side effects, the range of supported values can be determined by attempting to write a desired setting then reading to see if the value was retained.",CSR_controlled,enum,high,False, +chunk_53d8f04a,src/priv/csrs.adoc,1144,"Preamble > Control and Status Registers (CSRs) > CSR Field Specifications > Write Any Values, Reads Legal Values (WARL)",These fields are labeled *WARL* in the register descriptions.,CSR_controlled,enum,very_high,False, +chunk_0bf5f0a3,src/priv/csrs.adoc,1151,"Preamble > Control and Status Registers (CSRs) > CSR Field Specifications > Write Any Values, Reads Legal Values (WARL)",Implementations will not raise an exception on writes of unsupported values to a *WARL* field.,CSR_controlled,enum,very_high,False, +chunk_ef21f46d,src/priv/csrs.adoc,1151,"Preamble > Control and Status Registers (CSRs) > CSR Field Specifications > Write Any Values, Reads Legal Values (WARL)","Implementations can return any legal value on the read of a *WARL* field when the last write was of an illegal value, but the legal value returned should deterministically depend on the illegal written value and the architectural state of the hart.",CSR_controlled,enum,very_high,False, +chunk_b64d2a9a,src/priv/csrs.adoc,1160,Preamble > Control and Status Registers (CSRs) > CSR Field Modulation,"If a write to one CSR changes the set of legal values allowed for a field of a second CSR, then unless specified otherwise, the second CSR's field immediately gets an `UNSPECIFIED` value from among its new legal values.",CSR_controlled,enum,high,False, +chunk_cb7e1ef1,src/priv/csrs.adoc,1160,Preamble > Control and Status Registers (CSRs) > CSR Field Modulation,This is true even if the field's value before the write remains legal after the write; the value of the field may be changed in consequence of the write to the controlling CSR.,CSR_controlled,enum,high,False, +chunk_90cd85d3,src/priv/csrs.adoc,1167,Preamble > Control and Status Registers (CSRs) > CSR Field Modulation,A change to the value of a CSR for this reason is not a write to the affected CSR and thus does not trigger any side effects specified for that CSR.,CSR_controlled,enum,high,False, +chunk_4c5b98e0,src/priv/csrs.adoc,1173,Preamble > Control and Status Registers (CSRs) > Implicit Reads of CSRs,"Unless otherwise specified, the value returned by an implicit read of a CSR is the same value that would have been returned by an explicit read of the CSR, using a CSR-access instruction in a sufficient privilege mode.",CSR_controlled,enum,high,False, +chunk_07c6b7c0,src/priv/csrs.adoc,1189,Preamble > Control and Status Registers (CSRs) > CSR Width Modulation,The value of the previous-width CSR is copied to a temporary register of the same width. .,CSR_controlled,enum,high,False, +chunk_5ca0363f,src/priv/csrs.adoc,1189,Preamble > Control and Status Registers (CSRs) > CSR Width Modulation,"For the read-only bits of the previous-width CSR, the bits at the same positions in the temporary register are set to zeros. .",CSR_controlled,binary,high,False, +chunk_c71ffae5,src/priv/csrs.adoc,1189,Preamble > Control and Status Registers (CSRs) > CSR Width Modulation,The width of the temporary register is changed to the new width.,unknown,unknown,high,False, +chunk_fe6d10f9,src/priv/csrs.adoc,1189,Preamble > Control and Status Registers (CSRs) > CSR Width Modulation,"If the new width W is narrower than the previous width, the least-significant W bits of the temporary register are retained and the more-significant bits are discarded.",unknown,unknown,high,False, +chunk_95385ee7,src/priv/csrs.adoc,1189,Preamble > Control and Status Registers (CSRs) > CSR Width Modulation,"If the new width is wider than the previous width, the temporary register is zero-extended to the wider width. .",unknown,enum,high,False, +chunk_5d2561dc,src/priv/csrs.adoc,1189,Preamble > Control and Status Registers (CSRs) > CSR Width Modulation,Each writable field of the new-width CSR takes the value of the bits at the same positions in the temporary register.,CSR_controlled,enum,high,False, +chunk_0a6e8125,src/priv/csrs.adoc,1202,Preamble > Control and Status Registers (CSRs) > CSR Width Modulation,Changing the width of a CSR is not a read or write of the CSR and thus does not trigger any side effects.,CSR_controlled,enum,high,False, +chunk_44ae5740,src/priv/csrs.adoc,1207,Preamble > Control and Status Registers (CSRs) > Explicit Accesses to CSRs Wider than XLEN,"If a standard CSR is wider than XLEN bits, then an explicit read of the CSR returns the register's least-significant XLEN bits, and an explicit write to the CSR modifies only the register's least-significant XLEN bits, leaving the upper bits unchanged.",CSR_controlled,range,high,False, +chunk_150dc5ef,src/priv/csrs.adoc,1212,Preamble > Control and Status Registers (CSRs) > Explicit Accesses to CSRs Wider than XLEN,"Some standard CSRs, such as the counter CSRs of extension Zicntr, are always 64 bits, even when XLEN=32 (RV32).",CSR_controlled,range,high,False, +chunk_a99f7976,src/priv/csrs.adoc,1212,Preamble > Control and Status Registers (CSRs) > Explicit Accesses to CSRs Wider than XLEN,"The high-half CSR aliases bits 63:32 of its namesake 64-bit CSR, thus providing a way for RV32 software to read and modify the otherwise-unreachable 32 bits.",CSR_controlled,range,high,False, +chunk_17883028,src/priv/csrs.adoc,1221,Preamble > Control and Status Registers (CSRs) > Explicit Accesses to CSRs Wider than XLEN,Standard high-half CSRs are accessible only when the base RISC-V instruction set is RV32 (XLEN=32).,CSR_controlled,enum,high,False, +chunk_978f94ca,src/priv/hypervisor.adoc,3,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0","The hypervisor extension also adds another stage of address translation, from guest physical addresses to supervisor physical addresses, to virtualize the memory and memory-mapped I/O subsystems for a guest operating system. HS-mode acts the same as S-mode, but with additional instructions and CSRs that control the new stage of address translation and support hosting a guest OS in virtual S-mode (VS-mode).",CSR_controlled,enum,high,False, +chunk_f8e9c67f,src/priv/hypervisor.adoc,22,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0","The hypervisor extension depends on an ""I"" base integer ISA with 32 `x` registers (RV32I or RV64I), not RV32E or RV64E, which have only 16 `x` registers. CSR `mtval` must not be read-only zero, and standard page-based address translation must be supported, either Sv32 for RV32, or a minimum of Sv39 for RV64.",CSR_controlled,binary,very_high,False, +chunk_0772dc6e,src/priv/hypervisor.adoc,29,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0","The hypervisor extension is enabled by setting bit 7 in the `misa` CSR, which corresponds to the letter H. RISC-V harts that implement the hypervisor extension are encouraged not to hardwire `misa`[7], so that the extension may be disabled.",CSR_controlled,binary,high,False, +chunk_fec2dc68,src/priv/hypervisor.adoc,36,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Privilege Modes","When V=1, the hart is either in virtual S-mode (VS-mode), or in virtual U-mode (VU-mode) atop a guest OS running in VS-mode.",unknown,enum,high,False, +chunk_dd3c76fa,src/priv/hypervisor.adoc,36,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Privilege Modes","When V=0, the hart is either in M-mode, in HS-mode, or in U-mode atop an OS running in HS-mode.",unknown,enum,high,False, +chunk_0bf19a46,src/priv/hypervisor.adoc,84,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Privilege Modes","HS-mode is more privileged than VS-mode, and VS-mode is more privileged than VU-mode. VS-mode interrupts are globally disabled when executing in U-mode.",unknown,binary,high,False, +chunk_df991e2a,src/priv/hypervisor.adoc,90,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs","An OS or hypervisor running in HS-mode uses the supervisor CSRs to interact with the exception, interrupt, and address-translation subsystems.",CSR_controlled,enum,high,False, +chunk_9233c38a,src/priv/hypervisor.adoc,90,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs","Additional CSRs are provided to HS-mode, but not to VS-mode, to manage two-stage address translation and to control the behavior of a VS-mode guest: `hstatus`, `hedeleg`, `hideleg`, `hvip`, `hip`, `hie`, `hgeip`, `hgeie`, `henvcfg`, `henvcfgh`, `hcounteren`, `htimedelta`, `htimedeltah`, `htval`, `htinst`, and `hgatp`.",CSR_controlled,enum,high,False, +chunk_9547554a,src/priv/hypervisor.adoc,98,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs","Furthermore, several virtual supervisor CSRs (VS CSRs) are replicas of the normal supervisor CSRs.",CSR_controlled,enum,high,False, +chunk_27ede16e,src/priv/hypervisor.adoc,102,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs","When V=1, the VS CSRs substitute for the corresponding supervisor CSRs, taking over all functions of the usual supervisor CSRs except as specified otherwise.",CSR_controlled,enum,high,False, +chunk_7fa9df86,src/priv/hypervisor.adoc,102,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs",Instructions that normally read or modify a supervisor CSR shall instead access the corresponding VS CSR.,CSR_controlled,enum,very_high,False, +chunk_6cb618c4,src/priv/hypervisor.adoc,102,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs","When V=1, an attempt to read or write a VS CSR directly by its own separate CSR address causes a virtual-instruction exception. (Attempts from U-mode cause an illegal-instruction exception as usual.) The VS CSRs can be accessed as themselves only from M-mode or HS-mode.",CSR_controlled,enum,high,False, +chunk_a55dd77e,src/priv/hypervisor.adoc,114,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs","While V=1, the normal HS-level supervisor CSRs that are replaced by VS CSRs retain their values but do not affect the behavior of the machine unless specifically documented to do so.",CSR_controlled,enum,high,False, +chunk_abcc9cc8,src/priv/hypervisor.adoc,114,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs","Conversely, when V=0, the VS CSRs do not ordinarily affect the behavior of the machine other than being readable and writable by CSR instructions.",CSR_controlled,enum,high,False, +chunk_ee27cde6,src/priv/hypervisor.adoc,121,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs","Some standard supervisor CSRs (`senvcfg`, `scounteren`, and `scontext`, possibly others) have no matching VS CSR.",CSR_controlled,enum,high,False, +chunk_60eb6058,src/priv/hypervisor.adoc,121,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs","These supervisor CSRs continue to have their usual function and accessibility even when V=1, except with VS-mode and VU-mode substituting for HS-mode and U-mode.",CSR_controlled,enum,high,False, +chunk_613537f6,src/priv/hypervisor.adoc,121,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs",Hypervisor software is expected to manually swap the contents of these registers as needed.,SW_rule,unknown,high,False, +chunk_09143b61,src/priv/hypervisor.adoc,129,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs","In this chapter, we use the term HSXLEN to refer to the effective XLEN when executing in HS-mode, and VSXLEN to refer to the effective XLEN when executing in VS-mode.",unknown,unknown,high,False, +chunk_0ae2358b,src/priv/hypervisor.adoc,136,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register",The `hstatus` register is an HSXLEN-bit read/write register formatted as shown in when HSXLEN=32 and when HSXLEN=64.,CSR_controlled,range,high,False, +chunk_ba4e5934,src/priv/hypervisor.adoc,136,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register",The `hstatus` register provides facilities analogous to the `mstatus` register for tracking and controlling the exception behavior of a VS-mode guest.,CSR_controlled,enum,high,False, +chunk_c468caa2,src/priv/hypervisor.adoc,189,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register","The VSXL field controls the effective XLEN for VS-mode (known as VSXLEN), which may differ from the XLEN for HS-mode (HSXLEN).",non_CSR_parameter,enum,high,False, +chunk_6a9021d4,src/priv/hypervisor.adoc,189,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register","When HSXLEN=32, the VSXL field does not exist, and VSXLEN=32.",unknown,enum,high,False, +chunk_ae7d7dc2,src/priv/hypervisor.adoc,189,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register","When HSXLEN=64, VSXL is a *WARL* field that is encoded the same as the MXL field of `misa`, shown in .",CSR_controlled,enum,very_high,False, +chunk_03f4910a,src/priv/hypervisor.adoc,189,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register","In particular, an implementation may make VSXL be a read-only field whose value always ensures that VSXLEN=HSXLEN.",CSR_controlled,enum,high,False, +chunk_d82a1e36,src/priv/hypervisor.adoc,197,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register","If HSXLEN is changed from 32 to a wider width, and if field VSXL is not restricted to a single value, it gets the value corresponding to the widest supported width not wider than the new HSXLEN.",unknown,enum,high,False, +chunk_5204d0f7,src/priv/hypervisor.adoc,202,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register","The `hstatus` fields VTSR, VTW, and VTVM are defined analogously to the `mstatus` fields TSR, TW, and TVM, but affect execution only in VS-mode, and cause virtual-instruction exceptions instead of illegal-instruction exceptions.",CSR_controlled,enum,high,False, +chunk_b0afdd82,src/priv/hypervisor.adoc,202,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register","When VTSR=1, an attempt in VS-mode to execute SRET raises a virtual-instruction exception.",non_CSR_parameter,unknown,high,False, +chunk_b4adc736,src/priv/hypervisor.adoc,202,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register","When VTW=1 (and assuming `mstatus`.TW=0), an attempt in VS-mode to execute WFI raises a virtual-instruction exception if the WFI does not complete within an implementation-specific, bounded time limit.",CSR_controlled,enum,high,False, +chunk_c87d27b0,src/priv/hypervisor.adoc,202,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register","An implementation may have WFI always raise a virtual-instruction exception in VS-mode when VTW=1 (and `mstatus`.TW=0), even if there are pending globally-disabled interrupts when the instruction is executed.",CSR_controlled,binary,high,False, +chunk_84216ba4,src/priv/hypervisor.adoc,202,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register","When VTVM=1, an attempt in VS-mode to execute SFENCE.VMA or SINVAL.VMA or to access CSR `satp` raises a virtual-instruction exception.",CSR_controlled,enum,high,False, +chunk_282eb716,src/priv/hypervisor.adoc,219,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register","The VGEIN (Virtual Guest External Interrupt Number) field selects a guest external interrupt source for VS-level external interrupts. VGEIN is a *WLRL* field that must be able to hold values between zero and the maximum guest external interrupt number (known as GEILEN), inclusive.",CSR_controlled,range,very_high,False, +chunk_f4be8e69,src/priv/hypervisor.adoc,219,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register","When VGEIN=0, no guest external interrupt source is selected for VS-level external interrupts. GEILEN may be zero, in which case VGEIN may be read-only zero.",non_CSR_parameter,binary,high,False, +chunk_7e766ea5,src/priv/hypervisor.adoc,219,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register","Guest external interrupts are explained in , and the use of VGEIN is covered further in .",unknown,unknown,high,False, +chunk_587ab908,src/priv/hypervisor.adoc,230,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register","Field HU (Hypervisor in U-mode) controls whether the virtual-machine load/store instructions, HLV, HLVX, and HSV, can be used also in U-mode.",SW_rule,enum,high,False, +chunk_25c54336,src/priv/hypervisor.adoc,230,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register","When HU=1, these instructions can be executed in U-mode the same as in HS-mode.",unknown,unknown,high,False, +chunk_f0bf0b8d,src/priv/hypervisor.adoc,230,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register","When HU=0, all hypervisor instructions cause an illegal-instruction exception in U-mode.",SW_rule,unknown,high,False, +chunk_e7acfd3c,src/priv/hypervisor.adoc,237,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register","When the Ssnpm extension is not implemented, the `HUPMM` field is read-only zero.",CSR_controlled,binary,high,False, +chunk_3c929465,src/priv/hypervisor.adoc,237,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register",The `HUPMM` field is read-only zero for RV32.,CSR_controlled,binary,high,False, +chunk_213dabf9,src/priv/hypervisor.adoc,248,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register",The SPV bit (Supervisor Previous Virtualization mode) is written by the implementation whenever a trap is taken into HS-mode.,unknown,unknown,high,False, +chunk_1ac4c804,src/priv/hypervisor.adoc,248,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register","Just as the SPP bit in `sstatus` is set to the (nominal) privilege mode at the time of the trap, the SPV bit in `hstatus` is set to the value of the virtualization mode V at the time of the trap.",CSR_controlled,enum,high,False, +chunk_11341b3a,src/priv/hypervisor.adoc,248,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register","When an SRET instruction is executed when V=0, V is set to SPV.",unknown,unknown,high,False, +chunk_c9168e52,src/priv/hypervisor.adoc,255,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register","When V=1 and a trap is taken into HS-mode, bit SPVP (Supervisor Previous Virtual Privilege) is set to the nominal privilege mode at the time of the trap, the same as `sstatus`.SPP.",CSR_controlled,enum,high,False, +chunk_f171ae1f,src/priv/hypervisor.adoc,255,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register","But if V=0 before a trap, SPVP is left unchanged on trap entry. SPVP controls the effective privilege of explicit memory accesses made by the virtual-machine load/store instructions, HLV, HLVX, and HSV.",non_CSR_parameter,unknown,high,False, +chunk_f7fd13ab,src/priv/hypervisor.adoc,263,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register",Field GVA (Guest Virtual Address) is written by the implementation whenever a trap is taken into HS-mode.,unknown,enum,high,False, +chunk_75e3bfd1,src/priv/hypervisor.adoc,263,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register","For any trap (breakpoint, address misaligned, access fault, page fault, or guest-page fault) that writes a guest virtual address to `stval`, GVA is set to 1.",CSR_controlled,binary,high,False, +chunk_917dfca7,src/priv/hypervisor.adoc,263,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register","For any other trap into HS-mode, GVA is set to 0.",unknown,binary,high,False, +chunk_dc452d7b,src/priv/hypervisor.adoc,270,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register",The VSBE bit is a *WARL* field that controls the endianness of explicit memory accesses made from VS-mode.,CSR_controlled,enum,very_high,False, +chunk_97f67b28,src/priv/hypervisor.adoc,270,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register","If VSBE=0, explicit load and store memory accesses made from VS-mode are little-endian, and if VSBE=1, they are big-endian. VSBE also controls the endianness of all implicit accesses to VS-level memory management data structures, such as page tables.",non_CSR_parameter,unknown,high,False, +chunk_e96531a2,src/priv/hypervisor.adoc,270,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register",An implementation may make VSBE a read-only field that always specifies the same endianness as HS-mode.,CSR_controlled,enum,high,False, +chunk_0d9405e9,src/priv/hypervisor.adoc,281,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Delegation (`hedeleg` and `hideleg`) Registers","Register `hedeleg` is a 64-bit read/write register, formatted as shown in .",CSR_controlled,range,high,False, +chunk_860016c2,src/priv/hypervisor.adoc,281,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Delegation (`hedeleg` and `hideleg`) Registers","Register `hideleg` is an HSXLEN-bit read/write register, formatted as shown in .",CSR_controlled,range,high,False, +chunk_ef20713e,src/priv/hypervisor.adoc,281,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Delegation (`hedeleg` and `hideleg`) Registers","By default, all traps at any privilege level are handled in M-mode, though M-mode usually uses the `medeleg` and `mideleg` CSRs to delegate some traps to HS-mode.",CSR_controlled,enum,high,False, +chunk_473b8484,src/priv/hypervisor.adoc,281,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Delegation (`hedeleg` and `hideleg`) Registers",The `hedeleg` and `hideleg` CSRs allow these traps to be further delegated to a VS-mode guest; their layout is the same as `medeleg` and `mideleg`.,CSR_controlled,enum,high,False, +chunk_dbadc194,src/priv/hypervisor.adoc,299,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Delegation (`hedeleg` and `hideleg`) Registers",A synchronous trap that has been delegated to HS-mode (using `medeleg`) is further delegated to VS-mode if V=1 before the trap and the corresponding `hedeleg` bit is set.,CSR_controlled,enum,high,False, +chunk_7207d33f,src/priv/hypervisor.adoc,299,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Delegation (`hedeleg` and `hideleg`) Registers",Each bit of `hedeleg` shall be either writable or read-only zero.,CSR_controlled,binary,very_high,False, +chunk_a2418fac,src/priv/hypervisor.adoc,299,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Delegation (`hedeleg` and `hideleg`) Registers","Many bits of `hedeleg` are required specifically to be writable or zero, as enumerated in .",CSR_controlled,unknown,high,False, +chunk_7da2366e,src/priv/hypervisor.adoc,299,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Delegation (`hedeleg` and `hideleg`) Registers","Bit 0, corresponding to instruction address-misaligned exceptions, must be writable if IALIGN=32.",CSR_controlled,binary,very_high,False, +chunk_478a81a9,src/priv/hypervisor.adoc,309,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Delegation (`hedeleg` and `hideleg`) Registers","When XLEN=32, `hedelegh` is a 32-bit read/write register that aliases bits 63:32 of `hedeleg`.",CSR_controlled,range,high,False, +chunk_38ab83c6,src/priv/hypervisor.adoc,309,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Delegation (`hedeleg` and `hideleg`) Registers",Register `hedelegh` does not exist when XLEN=64.,unknown,unknown,high,False, +chunk_1e91f319,src/priv/hypervisor.adoc,314,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Delegation (`hedeleg` and `hideleg`) Registers",An interrupt that has been delegated to HS-mode (using `mideleg`) is further delegated to VS-mode if the corresponding `hideleg` bit is set.,CSR_controlled,enum,high,False, +chunk_e24ee0ef,src/priv/hypervisor.adoc,314,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Delegation (`hedeleg` and `hideleg`) Registers","Among bits 15:0 of `hideleg`, bits 10, 6, and 2 (corresponding to the standard VS-level interrupts) are writable, and bits 12, 9, 5, and 1 (corresponding to the standard S-level interrupts) are read-only zeros.",CSR_controlled,binary,high,False, +chunk_ea32b351,src/priv/hypervisor.adoc,320,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Delegation (`hedeleg` and `hideleg`) Registers","When a virtual supervisor external interrupt (code 10) is delegated to VS-mode, it is automatically translated by the machine into a supervisor external interrupt (code 9) for VS-mode, including the value written to `vscause` on an interrupt trap.",CSR_controlled,enum,high,False, +chunk_6ebcd725,src/priv/hypervisor.adoc,320,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Delegation (`hedeleg` and `hideleg`) Registers","Likewise, a virtual supervisor timer interrupt (6) is translated into a supervisor timer interrupt (5) for VS-mode, and a virtual supervisor software interrupt (2) is translated into a supervisor software interrupt (1) for VS-mode.",SW_rule,unknown,high,False, +chunk_50dad419,src/priv/hypervisor.adoc,320,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Delegation (`hedeleg` and `hideleg`) Registers",Similar translations may or may not be done for platform interrupt causes (codes 16 and above).,non_CSR_parameter,enum,high,False, +chunk_af3e8801,src/priv/hypervisor.adoc,407,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers",Bits of `hvip` that are not writable are read-only zeros.,CSR_controlled,binary,high,False, +chunk_3279daec,src/priv/hypervisor.adoc,416,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers",The standard portion (bits 15:0) of `hvip` is formatted as shown in .,unknown,unknown,high,False, +chunk_5bf211fa,src/priv/hypervisor.adoc,416,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers","Bits VSEIP, VSTIP, and VSSIP of `hvip` are writable.",CSR_controlled,enum,high,False, +chunk_00bc912b,src/priv/hypervisor.adoc,416,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers",Setting VSEIP=1 in `hvip` asserts a VS-level external interrupt; setting VSTIP asserts a VS-level timer interrupt; and setting VSSIP asserts a VS-level software interrupt.,CSR_controlled,enum,high,False, +chunk_f6dedaae,src/priv/hypervisor.adoc,427,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers",Registers `hip` and `hie` are HSXLEN-bit read/write registers that supplement HS-level’s `sip` and `sie` respectively.,CSR_controlled,range,high,False, +chunk_60678899,src/priv/hypervisor.adoc,427,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers","The `hip` register indicates pending VS-level and hypervisor-specific interrupts, while `hie` contains enable bits for the same interrupts.",SW_rule,unknown,high,False, +chunk_54d27c3d,src/priv/hypervisor.adoc,440,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers","For each writable bit in `sie`, the corresponding bit shall be read-only zero in both `hip` and `hie`.",CSR_controlled,binary,very_high,False, +chunk_d2856ad9,src/priv/hypervisor.adoc,440,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers","Hence, the nonzero bits in `sie` and `hie` are always mutually exclusive, and likewise for `sip` and `hip`.",CSR_controlled,enum,high,False, +chunk_b43173ba,src/priv/hypervisor.adoc,445,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers","An interrupt i will trap to HS-mode whenever all of the following are true: (a) either the current operating mode is HS-mode and the SIE bit in the `sstatus` register is set, or the current operating mode has less privilege than HS-mode; (b) bit i is set in both `sip` and `sie`, or in both `hip` and `hie`; and (c) bit i is not set in `hideleg`.",CSR_controlled,enum,high,False, +chunk_ce60e658,src/priv/hypervisor.adoc,452,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers","If bit i of `sie` is read-only zero, the same bit in register `hip` may be writable or may be read-only.",CSR_controlled,binary,high,False, +chunk_bda1083e,src/priv/hypervisor.adoc,452,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers","When bit i in `hip` is writable, a pending interrupt i can be cleared by writing 0 to this bit.",CSR_controlled,unknown,high,False, +chunk_11f13a4f,src/priv/hypervisor.adoc,452,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers","If interrupt i can become pending in `hip` but bit i in `hip` is read-only, then either the interrupt can be cleared by clearing bit i of `hvip`, or the implementation must provide some other mechanism for clearing the pending interrupt (which may involve a call to the execution environment).",CSR_controlled,enum,very_high,False, +chunk_20cc37b8,src/priv/hypervisor.adoc,462,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers",A bit in `hie` shall be writable if the corresponding interrupt can ever become pending in `hip`.,CSR_controlled,binary,very_high,False, +chunk_cac016a5,src/priv/hypervisor.adoc,462,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers",Bits of `hie` that are not writable shall be read-only zero.,CSR_controlled,binary,very_high,False, +chunk_a97b8e16,src/priv/hypervisor.adoc,467,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers",The standard portions (bits 15:0) of registers `hip` and `hie` are formatted as shown in and respectively.,unknown,unknown,high,False, +chunk_f8b09508,src/priv/hypervisor.adoc,485,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers","Bits `hip`.VSEIP and `hie`.VSEIE are the interrupt-pending and interrupt-enable bits for VS-level external interrupts. VSEIP is read-only in `hip`, and is the logical-OR of these interrupt sources:",CSR_controlled,unknown,high,False, +chunk_f635a34d,src/priv/hypervisor.adoc,490,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers",bit VSEIP of `hvip`; * the bit of `hgeip` selected by `hstatus`.VGEIN; and * any other platform-specific external interrupt signal directed to VS-level.,CSR_controlled,enum,high,False, +chunk_46e206e8,src/priv/hypervisor.adoc,495,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers","Bits `hip`.VSTIP and `hie`.VSTIE are the interrupt-pending and interrupt-enable bits for VS-level timer interrupts. VSTIP is read-only in `hip`, and is the logical-OR of `hvip`.VSTIP and, when the Sstc extension is implemented, the timer interrupt signal resulting from `vstimecmp`.",CSR_controlled,unknown,high,False, +chunk_7a63e393,src/priv/hypervisor.adoc,495,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers","The `hip`.VSTIP bit, in response to timer interrupts generated by `vstimecmp`, is set by writing `vstimecmp` with a value that is less than or equal to the sum of `time` and `htimedelta`, truncated to 64 bits; it is cleared by writing `vstimecmp` with a greater value.",non_CSR_parameter,range,high,False, +chunk_8ee96054,src/priv/hypervisor.adoc,495,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers",The `hip`.VSTIP bit remains defined while V=0 as well as V=1.,unknown,unknown,high,False, +chunk_4b1e5ff3,src/priv/hypervisor.adoc,505,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers",Bits `hip`.VSSIP and `hie`.VSSIE are the interrupt-pending and interrupt-enable bits for VS-level software interrupts. VSSIP in `hip` is an alias (writable) of the same bit in `hvip`.,CSR_controlled,enum,high,False, +chunk_ceb13eee,src/priv/hypervisor.adoc,510,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers","Multiple simultaneous interrupts destined for HS-mode are handled in the following decreasing priority order: SEI, SSI, STI, SGEI, VSEI, VSSI, VSTI, LCOFI.",unknown,unknown,high,False, +chunk_ebfc1a5c,src/priv/hypervisor.adoc,518,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest External Interrupt Registers (`hgeip` and `hgeie`)","The `hgeip` register is an HSXLEN-bit read-only register, formatted as shown in , that indicates pending guest external interrupts for this hart.",CSR_controlled,range,high,False, +chunk_752a82b3,src/priv/hypervisor.adoc,518,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest External Interrupt Registers (`hgeip` and `hgeie`)","The `hgeie` register is an HSXLEN-bit read/write register, formatted as shown in , that contains enable bits for the guest external interrupts at this hart.",CSR_controlled,range,high,False, +chunk_7f7ed18a,src/priv/hypervisor.adoc,518,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest External Interrupt Registers (`hgeip` and `hgeie`)",Guest external interrupt number i corresponds with bit i in both `hgeip` and `hgeie`.,unknown,unknown,high,False, +chunk_6b44d8d5,src/priv/hypervisor.adoc,535,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest External Interrupt Registers (`hgeip` and `hgeie`)",Guest external interrupts represent interrupts directed to individual virtual machines at VS-level.,unknown,unknown,high,False, +chunk_f594f86d,src/priv/hypervisor.adoc,535,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest External Interrupt Registers (`hgeip` and `hgeie`)","Each bit of `hgeip` summarizes all pending interrupts directed to one virtual hart, as collected and reported by an interrupt controller.",unknown,unknown,high,False, +chunk_dd80bf5e,src/priv/hypervisor.adoc,535,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest External Interrupt Registers (`hgeip` and `hgeie`)","To distinguish specific pending interrupts from multiple devices, software must query the interrupt controller.",SW_rule,binary,very_high,False, +chunk_99c9a65d,src/priv/hypervisor.adoc,546,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest External Interrupt Registers (`hgeip` and `hgeie`)",The number of bits implemented in `hgeip` and `hgeie` for guest external interrupts is UNSPECIFIED and may be zero.,non_CSR_parameter,enum,high,False, +chunk_d71021bd,src/priv/hypervisor.adoc,546,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest External Interrupt Registers (`hgeip` and `hgeie`)",This number is known as GEILEN.,unknown,unknown,high,False, +chunk_7b3b1dda,src/priv/hypervisor.adoc,546,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest External Interrupt Registers (`hgeip` and `hgeie`)","The least-significant bits are implemented first, apart from bit 0.",unknown,unknown,high,False, +chunk_117d05f7,src/priv/hypervisor.adoc,546,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest External Interrupt Registers (`hgeip` and `hgeie`)","Hence, if GEILEN is nonzero, bits GEILEN:1 shall be writable in `hgeie`, and all other bit positions shall be read-only zeros in both `hgeip` and `hgeie`.",CSR_controlled,binary,very_high,False, +chunk_8a8aac3e,src/priv/hypervisor.adoc,554,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest External Interrupt Registers (`hgeip` and `hgeie`)",Register `hgeie` selects the subset of guest external interrupts that cause a supervisor-level (HS-level) guest external interrupt.,unknown,enum,high,False, +chunk_45d737e4,src/priv/hypervisor.adoc,554,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest External Interrupt Registers (`hgeip` and `hgeie`)",The enable bits in `hgeie` do not affect the VS-level external interrupt signal selected from `hgeip` by `hstatus`.VGEIN.,CSR_controlled,enum,high,False, +chunk_608bb538,src/priv/hypervisor.adoc,564,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)","The `henvcfg` CSR is a 64-bit read/write register, formatted as shown in , that controls certain characteristics of the execution environment when virtualization mode V=1.",CSR_controlled,range,high,False, +chunk_96e3672e,src/priv/hypervisor.adoc,593,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)","If bit FIOM (Fence of I/O implies Memory) is set to one in `henvcfg`, FENCE instructions executed when V=1 are modified so the requirement to order accesses to device I/O implies also the requirement to order main memory accesses. details the modified interpretation of FENCE instruction bits PI, PO, SI, and SO when FIOM=1 and V=1.",CSR_controlled,binary,high,False, +chunk_50c4380b,src/priv/hypervisor.adoc,601,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)","Similarly, when FIOM=1 and V=1, if an atomic instruction that accesses a region ordered as device I/O has its aq and/or rl bit set, then that instruction is ordered as though it accesses both device I/O and memory.",unknown,unknown,high,False, +chunk_18ba4999,src/priv/hypervisor.adoc,621,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)",The PBMTE bit controls whether the Svpbmt extension is available for use in VS-stage address translation.,non_CSR_parameter,unknown,high,False, +chunk_64924240,src/priv/hypervisor.adoc,621,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)","When PBMTE=1, Svpbmt is available for VS-stage address translation.",unknown,unknown,high,False, +chunk_5bd544b3,src/priv/hypervisor.adoc,621,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)","When PBMTE=0, the implementation behaves as though Svpbmt were not implemented for VS-stage address translation.",unknown,unknown,high,False, +chunk_4e253681,src/priv/hypervisor.adoc,621,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)","If Svpbmt is not implemented, PBMTE is read-only zero.",unknown,binary,high,False, +chunk_25cf2b6c,src/priv/hypervisor.adoc,628,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)","If the Svadu extension is implemented, the ADUE bit controls whether hardware updating of PTE A/D bits is enabled for VS-stage address translation.",non_CSR_parameter,binary,high,False, +chunk_09c44b1e,src/priv/hypervisor.adoc,628,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)","When ADUE=1, hardware updating of PTE A/D bits is enabled during VS-stage address translation, and the implementation behaves as though the Svade extension were not implemented for VS-mode address translation.",unknown,binary,high,False, +chunk_0bc2487b,src/priv/hypervisor.adoc,628,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)","When ADUE=0, the implementation behaves as though Svade were implemented for VS-stage address translation.",unknown,unknown,high,False, +chunk_476f4922,src/priv/hypervisor.adoc,628,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)","If Svadu is not implemented, ADUE is read-only zero.",unknown,binary,high,False, +chunk_d3d819d2,src/priv/hypervisor.adoc,638,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)",The Sstc extension adds the `STCE` (STimecmp Enable) bit to `henvcfg` CSR.,CSR_controlled,enum,high,False, +chunk_dfe403b1,src/priv/hypervisor.adoc,638,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)","When the Sstc extension is not implemented, `STCE` is read-only zero.",unknown,binary,high,False, +chunk_04b7efc4,src/priv/hypervisor.adoc,638,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)",The `STCE` bit enables `vstimecmp` for VS-mode when set to one.,unknown,binary,high,False, +chunk_5e58890b,src/priv/hypervisor.adoc,638,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)","When `STCE` bit is `henvcfg` is zero, an attempt to access `stimecmp` (really `vstimecmp`) when V=1 raises a virtual-instruction exception, and `VSTIP` in `hip` reverts to its defined behavior as if this extension is not implemented.",CSR_controlled,enum,high,False, +chunk_32c61aed,src/priv/hypervisor.adoc,646,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)",The Zicboz extension adds the `CBZE` (Cache Block Zero instruction enable) field to `henvcfg`.,CSR_controlled,enum,high,False, +chunk_dd133a83,src/priv/hypervisor.adoc,646,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)","The `CBZE` field applies to execution of the cache block zero instruction (`CBO.ZERO`) in privilege modes VS and VU, and only when the instruction is HS-qualified.",unknown,enum,high,False, +chunk_cd2e3cf0,src/priv/hypervisor.adoc,646,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)","If the instruction is not HS-qualified, it raises an illegal-instruction exception.",non_CSR_parameter,unknown,high,False, +chunk_c43d7172,src/priv/hypervisor.adoc,646,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)","If the instruction is HS-qualified and the `CBZE` field is set to 1, the instruction is enabled for execution; otherwise, if the `CBZE` field is set to 0, it raises a virtual-instruction exception.",non_CSR_parameter,binary,high,False, +chunk_a15c3b9a,src/priv/hypervisor.adoc,646,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)","When the Zicboz extension is not implemented, `CBZE` is read-only zero.",unknown,binary,high,False, +chunk_ff7af1e3,src/priv/hypervisor.adoc,656,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)",The Zicbom extension adds the `CBCFE` (Cache Block Clean and Flush instruction Enable) field to `henvcfg`.,CSR_controlled,enum,high,False, +chunk_c35d4aac,src/priv/hypervisor.adoc,656,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)","When V=1, if the `CBO.CLEAN` and `CBO.FLUSH` instructions are not HS-qualified, they raise an illegal-instruction exception.",non_CSR_parameter,unknown,high,False, +chunk_23002ca2,src/priv/hypervisor.adoc,656,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)","If the instructions are HS-qualified and the `CBCFE` field is set to 1, the instructions are enabled for execution; otherwise, if the `CBCFE` field is set to 0, they raise a virtual-instruction exception.",non_CSR_parameter,binary,high,False, +chunk_d9e45d9b,src/priv/hypervisor.adoc,656,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)","When the Zicbom extension is not implemented, `CBCFE` is read-only zero.",unknown,binary,high,False, +chunk_146ae25e,src/priv/hypervisor.adoc,665,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)",The Zicbom extension adds the `CBIE` (Cache Block Invalidate instruction Enable) WARL field to `henvcfg`.,CSR_controlled,enum,very_high,False, +chunk_9fef964e,src/priv/hypervisor.adoc,665,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)",The `CBIE` field controls execution of the cache block invalidate instruction (`CBO.INVAL`) in privilege modes VS and VU.,non_CSR_parameter,enum,high,False, +chunk_ecd09231,src/priv/hypervisor.adoc,665,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)",The encoding `10b` is reserved.,unknown,enum,high,False, +chunk_31f743c4,src/priv/hypervisor.adoc,665,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)","When the Zicbom extension is not implemented, `CBIE` is read-only zero.",unknown,binary,high,False, +chunk_850145f6,src/priv/hypervisor.adoc,672,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)","When V=1, if the `CBO.INVAL` instruction is not HS-qualified, it raises an illegal-instruction exception.",non_CSR_parameter,unknown,high,False, +chunk_939df81e,src/priv/hypervisor.adoc,672,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)","If the instruction is HS-qualified and the `CBIE` field is set to `01b` or `11b`, the instruction is enabled for execution; otherwise, it raises a virtual-instruction exception.",non_CSR_parameter,binary,high,False, +chunk_29fd661a,src/priv/hypervisor.adoc,678,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)","If `CBO.INVAL` is enabled in HS-mode to perform a flush operation, then when the instruction is enabled in VS- or VU-mode it performs a flush operation, even if `CBIE` is set to `11b`.",unknown,binary,high,False, +chunk_ffc66722,src/priv/hypervisor.adoc,678,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)","Otherwise, when the instruction is enabled for execution, its behavior depends on the `CBIE` encoding, as follows:",non_CSR_parameter,binary,high,False, +chunk_54f4a7b6,src/priv/hypervisor.adoc,683,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)","`01b` -- The instruction is executed and performs a flush operation, even if configured by VS-mode to perform an invalidate operation. * `11b` -- The instruction is executed and performs an invalidate operation, unless configured by VS-mode to perform a flush operation.",unknown,unknown,high,False, +chunk_8e27cece,src/priv/hypervisor.adoc,688,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)","When the Ssnpm extension is not implemented, the `PMM` field is read-only zero.",CSR_controlled,binary,high,False, +chunk_7d1cfb98,src/priv/hypervisor.adoc,688,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)",The `PMM` field is read-only zero for RV32.,CSR_controlled,binary,high,False, +chunk_a1f1a0b8,src/priv/hypervisor.adoc,706,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)",The Zicfilp extension adds the `LPE` field in `henvcfg`.,CSR_controlled,enum,high,False, +chunk_54725403,src/priv/hypervisor.adoc,706,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)","When the `LPE` field is set to 1, the Zicfilp extension is enabled in VS-mode.",unknown,binary,high,False, +chunk_f01e8945,src/priv/hypervisor.adoc,706,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)","When the `LPE` field is 0, the Zicfilp extension is not enabled in VS-mode and the following rules apply to VS-mode:",unknown,binary,high,False, +chunk_d1697df4,src/priv/hypervisor.adoc,712,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)",The hart does not update the `ELP` state; it remains as `NOLPEXPECTED`. * The `LPAD` instruction operates as a no-op.,unknown,unknown,high,False, +chunk_12d848e2,src/priv/hypervisor.adoc,715,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)",The Zicfiss extension adds the `SSE` field in `henvcfg`.,CSR_controlled,enum,high,False, +chunk_371bb40a,src/priv/hypervisor.adoc,715,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)","If the `SSE` field is set to 1, the Zicfiss extension is activated in VS-mode.",unknown,binary,high,False, +chunk_2326b45d,src/priv/hypervisor.adoc,715,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)","When the `SSE` field is 0, the Zicfiss extension remains inactive in VS-mode, and the following rules apply when `V=1`:",unknown,enum,high,False, +chunk_4496f889,src/priv/hypervisor.adoc,721,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)",32-bit Zicfiss instructions will revert to their behavior as defined by Zimop. * 16-bit Zicfiss instructions will revert to their behavior as defined by Zcmop. * The `pte.xwr=010b` encoding in VS-stage page tables becomes reserved. * The `senvcfg.SSE` field will read as zero and is read-only. *,CSR_controlled,range,high,False, +chunk_1e335585,src/priv/hypervisor.adoc,721,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)","When `menvcfg.SSE` is one, `SSAMOSWAP.W/D` raises a virtual-instruction exception.",CSR_controlled,enum,high,False, +chunk_51116589,src/priv/hypervisor.adoc,728,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)",The Ssdbltrp extension adds the double-trap-enable (`DTE`) field in `henvcfg`.,CSR_controlled,enum,high,False, +chunk_e0b190af,src/priv/hypervisor.adoc,728,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)","When `henvcfg.DTE` is zero, the implementation behaves as though Ssdbltrp is not implemented for VS-mode and the `vsstatus.SDT` bit is read-only zero.",CSR_controlled,binary,high,False, +chunk_e5433e71,src/priv/hypervisor.adoc,733,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)","When XLEN=32, `henvcfgh` is a 32-bit read/write register that aliases bits 63:32 of `henvcfg`.",CSR_controlled,range,high,False, +chunk_934e063b,src/priv/hypervisor.adoc,733,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)",Register `henvcfgh` does not exist when XLEN=64.,CSR_controlled,enum,high,False, +chunk_7bcaae3b,src/priv/hypervisor.adoc,741,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Counter-Enable (`hcounteren`) Register",The counter-enable register `hcounteren` is a 32-bit register that controls the availability of the hardware performance monitoring counters to the guest virtual machine.,CSR_controlled,range,high,False, +chunk_dd736d8d,src/priv/hypervisor.adoc,749,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Counter-Enable (`hcounteren`) Register","When the CY, TM, IR, or HPMn bit in the `hcounteren` register is clear, attempts to read the `cycle`, `time`, `instret`, or `hpmcounter` n register while V=1 will cause a virtual-instruction exception if the same bit in `mcounteren` is 1.",CSR_controlled,enum,high,False, +chunk_42d052b5,src/priv/hypervisor.adoc,749,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Counter-Enable (`hcounteren`) Register","When one of these bits is set, access to the corresponding register is permitted when V=1, unless prevented for some other reason.",unknown,enum,high,False, +chunk_005eeb1a,src/priv/hypervisor.adoc,749,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Counter-Enable (`hcounteren`) Register","In VU-mode, a counter is not readable unless the applicable bits are set in both `hcounteren` and `scounteren`.",CSR_controlled,enum,high,False, +chunk_89399b82,src/priv/hypervisor.adoc,759,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Counter-Enable (`hcounteren`) Register","In addition, when the TM bit in the `hcounteren` register is clear, attempts to access the `vstimecmp` register (via `stimecmp`) while executing in VS-mode will cause a virtual-instruction exception if the same bit in `mcounteren` is set.",CSR_controlled,enum,high,False, +chunk_32832064,src/priv/hypervisor.adoc,759,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Counter-Enable (`hcounteren`) Register","When this bit and the same bit in `mcounteren` are both set, access to the `vstimecmp` register (if implemented) is permitted in VS-mode.",CSR_controlled,enum,high,False, +chunk_5d742cad,src/priv/hypervisor.adoc,766,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Counter-Enable (`hcounteren`) Register",`hcounteren` must be implemented.,CSR_controlled,enum,very_high,False, +chunk_8ce0725a,src/priv/hypervisor.adoc,766,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Counter-Enable (`hcounteren`) Register","However, any of the bits may be read-only zero, indicating reads to the corresponding counter will cause an exception when V=1.",CSR_controlled,binary,high,False, +chunk_88c9779d,src/priv/hypervisor.adoc,766,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Counter-Enable (`hcounteren`) Register","Hence, they are effectively *WARL* fields.",CSR_controlled,enum,very_high,False, +chunk_f1ab6623,src/priv/hypervisor.adoc,773,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Time Delta (`htimedelta`) Register",The `htimedelta` CSR is a 64-bit read/write register that contains the delta between the value of the `time` CSR and the value returned in VS-mode or VU-mode.,CSR_controlled,range,high,False, +chunk_040c8eed,src/priv/hypervisor.adoc,773,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Time Delta (`htimedelta`) Register","That is, reading the `time` CSR in VS or VU mode returns the sum of the contents of `htimedelta` and the actual value of `time`.",CSR_controlled,enum,high,False, +chunk_598e08ca,src/priv/hypervisor.adoc,782,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Time Delta (`htimedelta`) Register","When XLEN=32, `htimedeltah` is a 32-bit read/write register that aliases bits 63:32 of `htimedelta`.",CSR_controlled,range,high,False, +chunk_2fe9d5d8,src/priv/hypervisor.adoc,782,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Time Delta (`htimedelta`) Register",Register `htimedeltah` does not exist when XLEN=64.,unknown,unknown,high,False, +chunk_b0c36f3f,src/priv/hypervisor.adoc,787,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Time Delta (`htimedelta`) Register","If the `time` CSR is implemented, `htimedelta` (and `htimedeltah` for XLEN=32) must be implemented.",CSR_controlled,enum,very_high,False, +chunk_8dbfe785,src/priv/hypervisor.adoc,793,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Value (`htval`) Register",The `htval` register is an HSXLEN-bit read/write register formatted as shown in .,CSR_controlled,range,high,False, +chunk_20300779,src/priv/hypervisor.adoc,793,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Value (`htval`) Register","When a trap is taken into HS-mode, `htval` is written with additional exception-specific information, alongside `stval`, to assist software in handling the trap.",CSR_controlled,enum,high,False, +chunk_f1c80786,src/priv/hypervisor.adoc,803,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Value (`htval`) Register","When a guest-page-fault trap is taken into HS-mode, `htval` is written with either zero or the guest physical address that faulted, shifted right by 2 bits.",non_CSR_parameter,range,high,False, +chunk_ee471d2e,src/priv/hypervisor.adoc,803,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Value (`htval`) Register","For other traps, `htval` is set to zero, but a future standard or extension may redefine `htval's` setting for other traps.",non_CSR_parameter,binary,high,False, +chunk_5c253946,src/priv/hypervisor.adoc,818,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Value (`htval`) Register","Otherwise, for misaligned loads and stores that cause guest-page faults, a nonzero guest physical address in `htval` corresponds to the faulting portion of the access as indicated by the virtual address in `stval`.",CSR_controlled,enum,high,False, +chunk_1e095ede,src/priv/hypervisor.adoc,818,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Value (`htval`) Register","For instruction guest-page faults on systems with variable-length instructions, a nonzero `htval` corresponds to the faulting portion of the instruction as indicated by the virtual address in `stval`.",CSR_controlled,enum,high,False, +chunk_347e7e23,src/priv/hypervisor.adoc,825,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Value (`htval`) Register","`htval` is a *WARL* register that must be able to hold zero and may be capable of holding only an arbitrary subset of other 2-bit-shifted guest physical addresses, if any.",CSR_controlled,range,very_high,False, +chunk_873d0da8,src/priv/hypervisor.adoc,832,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Instruction (`htinst`) Register",The `htinst` register is an HSXLEN-bit read/write register formatted as shown in .,CSR_controlled,range,high,False, +chunk_80e6148a,src/priv/hypervisor.adoc,832,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Instruction (`htinst`) Register","When a trap is taken into HS-mode, `htinst` is written with a value that, if nonzero, provides information about the instruction that trapped, to assist software in handling the trap.",SW_rule,unknown,high,False, +chunk_e4cf4d7e,src/priv/hypervisor.adoc,832,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Instruction (`htinst`) Register",The values that may be written to `htinst` on a trap are documented in .,non_CSR_parameter,enum,high,False, +chunk_32c3747c,src/priv/hypervisor.adoc,844,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Instruction (`htinst`) Register",`htinst` is a *WARL* register that need only be able to hold the values that the implementation may automatically write to it on a trap.,CSR_controlled,enum,very_high,False, +chunk_8b31d901,src/priv/hypervisor.adoc,851,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest Address Translation and Protection (`hgatp`) Register","Similar to CSR `satp`, this register holds the physical page number (PPN) of the guest-physical root page table; a virtual machine identifier (VMID), which facilitates address-translation fences on a per-virtual-machine basis; and the MODE field, which selects the address-translation scheme for guest physical addresses.",CSR_controlled,enum,high,False, +chunk_afc7c99b,src/priv/hypervisor.adoc,851,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest Address Translation and Protection (`hgatp`) Register","When `mstatus`.TVM=1, attempts to read or write `hgatp` while executing in HS-mode will raise an illegal-instruction exception.",CSR_controlled,enum,high,False, +chunk_fb5ee0d0,src/priv/hypervisor.adoc,872,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest Address Translation and Protection (`hgatp`) Register",shows the encodings of the MODE field when HSXLEN=32 and HSXLEN=64.,unknown,enum,high,False, +chunk_e81e27d1,src/priv/hypervisor.adoc,872,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest Address Translation and Protection (`hgatp`) Register","When MODE=Bare, guest physical addresses are equal to supervisor physical addresses, and there is no further memory protection for a guest virtual machine beyond the physical memory protection scheme described in .",unknown,range,high,False, +chunk_34c1340b,src/priv/hypervisor.adoc,872,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest Address Translation and Protection (`hgatp`) Register","In this case, software must write zero to the remaining fields in `hgatp`.",CSR_controlled,enum,very_high,False, +chunk_835440b2,src/priv/hypervisor.adoc,872,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest Address Translation and Protection (`hgatp`) Register",Attempting to select MODE=Bare with a nonzero pattern in the remaining fields has an UNSPECIFIED effect on the value that the remaining fields assume and an UNSPECIFIED effect on G-stage address translation and protection behavior.,non_CSR_parameter,enum,high,False, +chunk_72e15c5a,src/priv/hypervisor.adoc,882,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest Address Translation and Protection (`hgatp`) Register","When HSXLEN=32, the only other valid setting for MODE is Sv32x4, which is a modification of the usual Sv32 paged virtual-memory scheme, extended to support 34-bit guest physical addresses.",non_CSR_parameter,range,high,False, +chunk_ac8932ec,src/priv/hypervisor.adoc,882,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest Address Translation and Protection (`hgatp`) Register","When HSXLEN=64, modes Sv39x4, Sv48x4, and Sv57x4 are defined as modifications of the Sv39, Sv48, and Sv57 paged virtual-memory schemes.",unknown,unknown,high,False, +chunk_83ee18a6,src/priv/hypervisor.adoc,882,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest Address Translation and Protection (`hgatp`) Register",All of these paged virtual-memory schemes are described in .,unknown,unknown,high,False, +chunk_aaa1d1bb,src/priv/hypervisor.adoc,891,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest Address Translation and Protection (`hgatp`) Register",The remaining MODE settings when HSXLEN=64 are reserved for future use and may define different interpretations of the other fields in `hgatp`.,CSR_controlled,enum,high,False, +chunk_cac1b60b,src/priv/hypervisor.adoc,932,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest Address Translation and Protection (`hgatp`) Register",Implementations are not required to support all defined MODE settings when HSXLEN=64.,unknown,unknown,high,False, +chunk_f7e06f06,src/priv/hypervisor.adoc,935,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest Address Translation and Protection (`hgatp`) Register",A write to `hgatp` with an unsupported MODE value is not ignored as it is for `satp`.,CSR_controlled,enum,high,False, +chunk_b937205d,src/priv/hypervisor.adoc,935,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest Address Translation and Protection (`hgatp`) Register","Instead, the fields of `hgatp` are *WARL* in the normal way, when so indicated.",CSR_controlled,enum,very_high,False, +chunk_1ae63359,src/priv/hypervisor.adoc,940,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest Address Translation and Protection (`hgatp`) Register","As explained in , for the paged virtual-memory schemes (Sv32x4, Sv39x4, Sv48x4, and Sv57x4), the root page table is 16 KiB and must be aligned to a 16-KiB boundary.",non_CSR_parameter,enum,very_high,False, +chunk_35bc382c,src/priv/hypervisor.adoc,940,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest Address Translation and Protection (`hgatp`) Register","In these modes, the lowest two bits of the physical page number (PPN) in `hgatp` always read as zeros.",CSR_controlled,enum,high,False, +chunk_1a65328e,src/priv/hypervisor.adoc,940,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest Address Translation and Protection (`hgatp`) Register",An implementation that supports only the defined paged virtual-memory schemes and/or Bare may make PPN[1:0] read-only zero.,non_CSR_parameter,binary,high,False, +chunk_406e6cdd,src/priv/hypervisor.adoc,949,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest Address Translation and Protection (`hgatp`) Register",The number of VMID bits is UNSPECIFIED and may be zero.,non_CSR_parameter,enum,high,False, +chunk_8e1a8e23,src/priv/hypervisor.adoc,949,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest Address Translation and Protection (`hgatp`) Register","The number of implemented VMID bits, termed VMIDLEN, may be determined by writing one to every bit position in the VMID field, then reading back the value in `hgatp` to see which bit positions in the VMID field hold a one.",CSR_controlled,enum,high,False, +chunk_9a74d120,src/priv/hypervisor.adoc,949,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest Address Translation and Protection (`hgatp`) Register","The maximal value of VMIDLEN, termed VMIDMAX, is 7 for Sv32x4 or 14 for Sv39x4, Sv48x4, and Sv57x4.",unknown,enum,high,False, +chunk_23986a0c,src/priv/hypervisor.adoc,958,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest Address Translation and Protection (`hgatp`) Register",The `hgatp` register is considered active for the purposes of the address-translation algorithm unless the effective privilege mode is U and `hstatus`.HU=0.,CSR_controlled,enum,high,False, +chunk_465e9d0a,src/priv/hypervisor.adoc,972,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Status (`vsstatus`) Register","The `vsstatus` register is a VSXLEN-bit read/write register that is VS-mode’s version of supervisor register `sstatus`, formatted as shown in when VSXLEN=32 and when VSXLEN=64.",CSR_controlled,range,high,False, +chunk_252d1f6c,src/priv/hypervisor.adoc,972,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Status (`vsstatus`) Register","When V=1, `vsstatus` substitutes for the usual `sstatus`, so instructions that normally read or modify `sstatus` actually access `vsstatus` instead.",CSR_controlled,enum,high,False, +chunk_1c2abfcf,src/priv/hypervisor.adoc,1036,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Status (`vsstatus`) Register","The UXL field controls the effective XLEN for VU-mode, which may differ from the XLEN for VS-mode (VSXLEN).",non_CSR_parameter,enum,high,False, +chunk_77c37a5f,src/priv/hypervisor.adoc,1036,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Status (`vsstatus`) Register","When VSXLEN=32, the UXL field does not exist, and VU-mode XLEN=32.",unknown,enum,high,False, +chunk_e66d7cb3,src/priv/hypervisor.adoc,1036,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Status (`vsstatus`) Register","When VSXLEN=64, UXL is a *WARL* field that is encoded the same as the MXL field of `misa`, shown in .",CSR_controlled,enum,very_high,False, +chunk_31126ac3,src/priv/hypervisor.adoc,1036,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Status (`vsstatus`) Register","In particular, an implementation may make UXL be a read-only copy of field VSXL of `hstatus`, forcing VU-mode XLEN=VSXLEN.",CSR_controlled,enum,high,False, +chunk_8f9cb3f9,src/priv/hypervisor.adoc,1042,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Status (`vsstatus`) Register","If VSXLEN is changed from 32 to a wider width, and if field UXL is not restricted to a single value, it gets the value corresponding to the widest supported width not wider than the new VSXLEN.",unknown,enum,high,False, +chunk_d7ce4e40,src/priv/hypervisor.adoc,1047,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Status (`vsstatus`) Register","When V=1, both `vsstatus`.FS and the HS-level `sstatus`.FS are in effect.",CSR_controlled,enum,high,False, +chunk_0facaac2,src/priv/hypervisor.adoc,1047,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Status (`vsstatus`) Register",Attempts to execute a floating-point instruction when either field is 0 (Off) raise an illegal-instruction exception.,non_CSR_parameter,enum,high,False, +chunk_574473fb,src/priv/hypervisor.adoc,1047,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Status (`vsstatus`) Register",Modifying the floating-point state when V=1 causes both fields to be set to 3 (Dirty).,unknown,enum,high,False, +chunk_da23ff96,src/priv/hypervisor.adoc,1053,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Status (`vsstatus`) Register","Similarly, when V=1, both `vsstatus`.VS and the HS-level `sstatus`.VS are in effect.",CSR_controlled,enum,high,False, +chunk_b838a66a,src/priv/hypervisor.adoc,1053,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Status (`vsstatus`) Register",Attempts to execute a vector instruction when either field is 0 (Off) raise an illegal-instruction exception.,non_CSR_parameter,enum,high,False, +chunk_5bcb2703,src/priv/hypervisor.adoc,1053,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Status (`vsstatus`) Register",Modifying the vector state when V=1 causes both fields to be set to 3 (Dirty).,unknown,enum,high,False, +chunk_60c57b9c,src/priv/hypervisor.adoc,1059,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Status (`vsstatus`) Register",Read-only fields SD and XS summarize the extension context status as it is visible to VS-mode only.,CSR_controlled,enum,high,False, +chunk_498f6576,src/priv/hypervisor.adoc,1064,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Status (`vsstatus`) Register",An implementation may make field UBE be a read-only copy of `hstatus`.VSBE.,CSR_controlled,enum,high,False, +chunk_a5782905,src/priv/hypervisor.adoc,1068,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Status (`vsstatus`) Register","When V=0, `vsstatus` does not directly affect the behavior of the machine, unless a virtual-machine load/store (HLV, HLVX, or HSV) or the MPRV feature in the `mstatus` register is used to execute a load or store as though V=1.",CSR_controlled,enum,high,False, +chunk_f0948c10,src/priv/hypervisor.adoc,1074,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Status (`vsstatus`) Register","The Zicfilp extension adds the `SPELP` field that holds the previous `ELP`, and is updated as specified in .",unknown,enum,high,False, +chunk_678fad21,src/priv/hypervisor.adoc,1074,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Status (`vsstatus`) Register",The `SPELP` field is encoded as follows:,unknown,enum,high,False, +chunk_c7ab5d22,src/priv/hypervisor.adoc,1079,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Status (`vsstatus`) Register",0 - `NOLPEXPECTED` - no landing pad instruction expected. * 1 - `LPEXPECTED` - a landing pad instruction is expected.,unknown,unknown,high,False, +chunk_4bd54f44,src/priv/hypervisor.adoc,1088,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Interrupt (`vsip` and `vsie`) Registers","The `vsip` and `vsie` registers are VSXLEN-bit read/write registers that are VS-mode’s versions of supervisor CSRs `sip` and `sie`, formatted as shown in and respectively.",CSR_controlled,range,high,False, +chunk_3c83c464,src/priv/hypervisor.adoc,1088,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Interrupt (`vsip` and `vsie`) Registers","When V=1, `vsip` and `vsie` substitute for the usual `sip` and `sie`, so instructions that normally read or modify `sip`/`sie` actually access `vsip`/`vsie` instead.",CSR_controlled,enum,high,False, +chunk_7d72f218,src/priv/hypervisor.adoc,1088,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Interrupt (`vsip` and `vsie`) Registers","However, interrupts directed to HS-level continue to be indicated in the HS-level `sip` register, not in `vsip`, when V=1.",CSR_controlled,enum,high,False, +chunk_df5f04f4,src/priv/hypervisor.adoc,1106,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Interrupt (`vsip` and `vsie`) Registers",The standard portions (bits 15:0) of registers `vsip` and `vsie` are formatted as shown in and respectively.,CSR_controlled,enum,high,False, +chunk_18ac463a,src/priv/hypervisor.adoc,1118,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Interrupt (`vsip` and `vsie`) Registers",Extension Shlcofideleg supports delegating LCOFI interrupts to VS-mode.,unknown,unknown,high,False, +chunk_10fe54f2,src/priv/hypervisor.adoc,1118,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Interrupt (`vsip` and `vsie`) Registers","If the Shlcofideleg extension is implemented, `hideleg` bit 13 is writable; otherwise, it is read-only zero.",CSR_controlled,binary,high,False, +chunk_a4ffa420,src/priv/hypervisor.adoc,1118,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Interrupt (`vsip` and `vsie`) Registers","When bit 13 of `hideleg` is zero, `vsip`.LCOFIP and `vsie`.LCOFIE are read-only zeros.",CSR_controlled,binary,high,False, +chunk_02647939,src/priv/hypervisor.adoc,1118,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Interrupt (`vsip` and `vsie`) Registers","Else, `vsip`.LCOFIP and `vsie`.LCOFIE are aliases of `sip`.LCOFIP and `sie`.LCOFIE.",CSR_controlled,enum,high,False, +chunk_2a39cc54,src/priv/hypervisor.adoc,1127,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Interrupt (`vsip` and `vsie`) Registers","When bit 10 of `hideleg` is zero, `vsip`.SEIP and `vsie`.SEIE are read-only zeros.",CSR_controlled,binary,high,False, +chunk_23d8580e,src/priv/hypervisor.adoc,1127,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Interrupt (`vsip` and `vsie`) Registers","Else, `vsip`.SEIP and `vsie`.SEIE are aliases of `hip`.VSEIP and `hie`.VSEIE.",CSR_controlled,enum,high,False, +chunk_1193d40d,src/priv/hypervisor.adoc,1132,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Interrupt (`vsip` and `vsie`) Registers","When bit 6 of `hideleg` is zero, `vsip`.STIP and `vsie`.STIE are read-only zeros.",CSR_controlled,binary,high,False, +chunk_fada99dc,src/priv/hypervisor.adoc,1132,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Interrupt (`vsip` and `vsie`) Registers","Else, `vsip`.STIP and `vsie`.STIE are aliases of `hip`.VSTIP and `hie`.VSTIE.",CSR_controlled,enum,high,False, +chunk_3f083a5f,src/priv/hypervisor.adoc,1137,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Interrupt (`vsip` and `vsie`) Registers","When bit 2 of `hideleg` is zero, `vsip`.SSIP and `vsie`.SSIE are read-only zeros.",CSR_controlled,binary,high,False, +chunk_185a33d2,src/priv/hypervisor.adoc,1137,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Interrupt (`vsip` and `vsie`) Registers","Else, `vsip`.SSIP and `vsie`.SSIE are aliases of `hip`.VSSIP and `hie`.VSSIE.",CSR_controlled,enum,high,False, +chunk_abb5e991,src/priv/hypervisor.adoc,1144,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Trap Vector Base Address (`vstvec`) Register","The `vstvec` register is a VSXLEN-bit read/write register that is VS-mode’s version of supervisor register `stvec`, formatted as shown in .",CSR_controlled,range,high,False, +chunk_b048dc7a,src/priv/hypervisor.adoc,1144,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Trap Vector Base Address (`vstvec`) Register","When V=1, `vstvec` substitutes for the usual `stvec`, so instructions that normally read or modify `stvec` actually access `vstvec` instead.",CSR_controlled,enum,high,False, +chunk_5e549c3e,src/priv/hypervisor.adoc,1144,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Trap Vector Base Address (`vstvec`) Register","When V=0, `vstvec` does not directly affect the behavior of the machine.",CSR_controlled,enum,high,False, +chunk_374ffb0f,src/priv/hypervisor.adoc,1158,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Scratch (`vsscratch`) Register","The `vsscratch` register is a VSXLEN-bit read/write register that is VS-mode’s version of supervisor register `sscratch`, formatted as shown in .",CSR_controlled,range,high,False, +chunk_39e35545,src/priv/hypervisor.adoc,1158,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Scratch (`vsscratch`) Register","When V=1, `vsscratch` substitutes for the usual `sscratch`, so instructions that normally read or modify `sscratch` actually access `vsscratch` instead.",CSR_controlled,enum,high,False, +chunk_d4f16131,src/priv/hypervisor.adoc,1158,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Scratch (`vsscratch`) Register",The contents of `vsscratch` never directly affect the behavior of the machine.,CSR_controlled,enum,high,False, +chunk_dc319ad9,src/priv/hypervisor.adoc,1172,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Exception Program Counter (`vsepc`) Register","The `vsepc` register is a VSXLEN-bit read/write register that is VS-mode’s version of supervisor register `sepc`, formatted as shown in .",CSR_controlled,range,high,False, +chunk_b80d0104,src/priv/hypervisor.adoc,1172,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Exception Program Counter (`vsepc`) Register","When V=1, `vsepc` substitutes for the usual `sepc`, so instructions that normally read or modify `sepc` actually access `vsepc` instead.",CSR_controlled,enum,high,False, +chunk_f39131fb,src/priv/hypervisor.adoc,1172,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Exception Program Counter (`vsepc`) Register","When V=0, `vsepc` does not directly affect the behavior of the machine.",CSR_controlled,enum,high,False, +chunk_4ad5ed93,src/priv/hypervisor.adoc,1180,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Exception Program Counter (`vsepc`) Register",`vsepc` is a *WARL* register that must be able to hold the same set of values that `sepc` can hold.,CSR_controlled,enum,very_high,False, +chunk_95eed6ca,src/priv/hypervisor.adoc,1190,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Cause (`vscause`) Register","The `vscause` register is a VSXLEN-bit read/write register that is VS-mode’s version of supervisor register `scause`, formatted as shown in .",CSR_controlled,range,high,False, +chunk_6f4d9f2d,src/priv/hypervisor.adoc,1190,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Cause (`vscause`) Register","When V=1, `vscause` substitutes for the usual `scause`, so instructions that normally read or modify `scause` actually access `vscause` instead.",CSR_controlled,enum,high,False, +chunk_a9f8b4fa,src/priv/hypervisor.adoc,1190,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Cause (`vscause`) Register","When V=0, `vscause` does not directly affect the behavior of the machine.",CSR_controlled,enum,high,False, +chunk_89ea1976,src/priv/hypervisor.adoc,1198,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Cause (`vscause`) Register",`vscause` is a *WLRL* register that must be able to hold the same set of values that `scause` can hold.,CSR_controlled,enum,very_high,False, +chunk_d1f523a0,src/priv/hypervisor.adoc,1208,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Trap Value (`vstval`) Register","The `vstval` register is a VSXLEN-bit read/write register that is VS-mode’s version of supervisor register `stval`, formatted as shown in .",CSR_controlled,range,high,False, +chunk_05a26484,src/priv/hypervisor.adoc,1208,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Trap Value (`vstval`) Register","When V=1, `vstval` substitutes for the usual `stval`, so instructions that normally read or modify `stval` actually access `vstval` instead.",CSR_controlled,enum,high,False, +chunk_e5ac1ecb,src/priv/hypervisor.adoc,1208,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Trap Value (`vstval`) Register","When V=0, `vstval` does not directly affect the behavior of the machine.",CSR_controlled,enum,high,False, +chunk_517503bb,src/priv/hypervisor.adoc,1216,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Trap Value (`vstval`) Register",`vstval` is a *WARL* register that must be able to hold the same set of values that `stval` can hold.,CSR_controlled,enum,very_high,False, +chunk_ac4984b6,src/priv/hypervisor.adoc,1226,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Address Translation and Protection (`vsatp`) Register","The `vsatp` register is a VSXLEN-bit read/write register that is VS-mode’s version of supervisor register `satp`, formatted as shown in for VSXLEN=32 and for VSXLEN=64.",CSR_controlled,range,high,False, +chunk_2806be78,src/priv/hypervisor.adoc,1244,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Address Translation and Protection (`vsatp`) Register",The `vsatp` register is considered active for the purposes of the address-translation algorithm unless the effective privilege mode is U and `hstatus`.HU=0.,CSR_controlled,enum,high,False, +chunk_483bef9e,src/priv/hypervisor.adoc,1244,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Address Translation and Protection (`vsatp`) Register","However, even when `vsatp` is active, VS-stage page-table entries’ A bits must not be set as a result of speculative execution, unless the effective privilege mode is VS or VU.",CSR_controlled,enum,very_high,False, +chunk_8e232382,src/priv/hypervisor.adoc,1250,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Address Translation and Protection (`vsatp`) Register","When V=0, a write to `vsatp` with an unsupported MODE value is either ignored as it is for `satp`, or the fields of `vsatp` are treated as *WARL* in the normal way.",CSR_controlled,enum,very_high,False, +chunk_53368c6a,src/priv/hypervisor.adoc,1250,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Address Translation and Protection (`vsatp`) Register","However, when V=1, a write to `satp` with an unsupported MODE value is ignored and no write to `vsatp` is effected.",CSR_controlled,enum,high,False, +chunk_5f9bd659,src/priv/hypervisor.adoc,1255,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Address Translation and Protection (`vsatp`) Register","When V=0, `vsatp` does not directly affect the behavior of the machine, unless a virtual-machine load/store (HLV, HLVX, or HSV) or the MPRV feature in the `mstatus` register is used to execute a load or store as though V=1.",CSR_controlled,enum,high,False, +chunk_6a7019b9,src/priv/hypervisor.adoc,1264,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Timer (`vstimecmp`) Register",The `vstimecmp` CSR is a 64-bit register and has 64-bit precision on all RV32 and RV64 systems.,CSR_controlled,range,high,False, +chunk_9f6a680e,src/priv/hypervisor.adoc,1264,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Timer (`vstimecmp`) Register","In RV32 only, accesses to the `vstimecmp` CSR access the low 32 bits, while accesses to the `vstimecmph` CSR access the high 32 bits of `vstimecmp`.",CSR_controlled,range,high,False, +chunk_4d000fef,src/priv/hypervisor.adoc,1269,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Timer (`vstimecmp`) Register","If the result of this comparison changes, it is guaranteed to be reflected in VSTIP eventually, but not necessarily immediately.",unknown,unknown,high,False, +chunk_38fd7041,src/priv/hypervisor.adoc,1269,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Timer (`vstimecmp`) Register",The interrupt will be taken based on the standard interrupt enable and delegation rules while V=1.,unknown,unknown,high,False, +chunk_50b9b79d,src/priv/hypervisor.adoc,1289,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Virtual-Machine Load and Store Instructions","The hypervisor virtual-machine load and store instructions are valid only in M-mode or HS-mode, or in U-mode when `hstatus`.HU=1.",CSR_controlled,enum,high,False, +chunk_d59339ab,src/priv/hypervisor.adoc,1289,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Virtual-Machine Load and Store Instructions","The effective privilege mode of the explicit memory access is VU when `hstatus`.SPVP=0, and VS when `hstatus`.SPVP=1.",CSR_controlled,enum,high,False, +chunk_7f885b9e,src/priv/hypervisor.adoc,1289,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Virtual-Machine Load and Store Instructions","As usual for VS-mode and VU-mode, two-stage address translation is applied, and the HS-level `sstatus`.SUM is ignored. HS-level `sstatus`.MXR makes execute-only pages readable by explicit loads for both stages of address translation (VS-stage and G-stage), whereas `vsstatus`.MXR affects only the first translation stage (VS-stage).",CSR_controlled,enum,high,False, +chunk_2dd6a687,src/priv/hypervisor.adoc,1312,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Virtual-Machine Load and Store Instructions","That is, the memory being read must be executable in both stages of address translation, but read permission is not required.",non_CSR_parameter,enum,very_high,False, +chunk_b1e08634,src/priv/hypervisor.adoc,1312,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Virtual-Machine Load and Store Instructions","For the supervisor physical address that results from address translation, the supervisor physical memory attributes must grant both execute and read permissions. (The supervisor physical memory attributes are the machine’s physical memory attributes as modified by physical memory protection, , for supervisor level.)",non_CSR_parameter,enum,very_high,False, +chunk_f1e1db40,src/priv/hypervisor.adoc,1324,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Virtual-Machine Load and Store Instructions","HLVX.WU is valid for RV32, even though LWU and HLV.WU are not. (For RV32, HLVX.WU can be considered a variant of HLV.W, as sign extension is irrelevant for 32-bit values.)",non_CSR_parameter,range,high,False, +chunk_e45ad577,src/priv/hypervisor.adoc,1332,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Virtual-Machine Load and Store Instructions","Attempts to execute a virtual-machine load/store instruction (HLV, HLVX, or HSV) when V=1 cause a virtual-instruction exception.",unknown,unknown,high,False, +chunk_5ad25264,src/priv/hypervisor.adoc,1332,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Virtual-Machine Load and Store Instructions",Attempts to execute one of these same instructions from U-mode when `hstatus`.HU=0 cause an illegal-instruction exception.,CSR_controlled,enum,high,False, +chunk_d40c865d,src/priv/hypervisor.adoc,1342,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Memory-Management Fence Instructions","The hypervisor memory-management fence instructions, HFENCE.VVMA and HFENCE.GVMA, perform a function similar to SFENCE.VMA (), except applying to the VS-level memory-management data structures controlled by CSR `vsatp` (HFENCE.VVMA) or the guest-physical memory-management data structures controlled by CSR `hgatp` (HFENCE.GVMA).",CSR_controlled,enum,high,False, +chunk_925c88bf,src/priv/hypervisor.adoc,1342,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Memory-Management Fence Instructions",Instruction SFENCE.VMA applies only to the memory-management data structures controlled by the current `satp` (either the HS-level `satp` when V=0 or `vsatp` when V=1).,CSR_controlled,enum,high,False, +chunk_61bead2e,src/priv/hypervisor.adoc,1359,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Memory-Management Fence Instructions","are subsequent to the HFENCE.VVMA, and * execute when `hgatp`.VMID has the same setting as it did when HFENCE.VVMA executed.",CSR_controlled,enum,high,False, +chunk_da9c6bc5,src/priv/hypervisor.adoc,1363,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Memory-Management Fence Instructions",Implicit reads need not be ordered when `hgatp`.VMID is different than at the time HFENCE.VVMA executed.,CSR_controlled,enum,high,False, +chunk_7bf6fa95,src/priv/hypervisor.adoc,1363,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Memory-Management Fence Instructions","If operand rs1!=`x0`, it specifies a single guest virtual address, and if operand rs2!=`x0`, it specifies a single guest address-space identifier (ASID).",unknown,unknown,high,False, +chunk_478d466a,src/priv/hypervisor.adoc,1367,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Memory-Management Fence Instructions","When rs2!=`x0`, bits XLEN-1:ASIDMAX of the value held in rs2 are reserved for future standard use.",unknown,unknown,high,False, +chunk_578e8358,src/priv/hypervisor.adoc,1367,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Memory-Management Fence Instructions","Until their use is defined by a standard extension, they should be zeroed by software and ignored by current implementations.",SW_rule,enum,medium,False, +chunk_241bcec5,src/priv/hypervisor.adoc,1367,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Memory-Management Fence Instructions","Furthermore, if ASIDLEN < ASIDMAX, the implementation shall ignore bits ASIDMAX-1:ASIDLEN of the value held in rs2.",non_CSR_parameter,binary,very_high,False, +chunk_9dd42bf9,src/priv/hypervisor.adoc,1375,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Memory-Management Fence Instructions",Neither `mstatus`.TVM nor `hstatus`.VTVM causes HFENCE.VVMA to trap.,CSR_controlled,enum,high,False, +chunk_42043311,src/priv/hypervisor.adoc,1378,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Memory-Management Fence Instructions","HFENCE.GVMA is valid only in HS-mode when `mstatus`.TVM=0, or in M-mode (irrespective of `mstatus`.TVM).",CSR_controlled,enum,high,False, +chunk_50e98a2d,src/priv/hypervisor.adoc,1378,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Memory-Management Fence Instructions","If operand rs1!=`x0`, it specifies a single guest physical address, shifted right by 2 bits, and if operand rs2!=`x0`, it specifies a single virtual machine identifier (VMID).",non_CSR_parameter,range,high,False, +chunk_be067f66,src/priv/hypervisor.adoc,1389,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Memory-Management Fence Instructions","When rs2!=`x0`, bits XLEN-1:VMIDMAX of the value held in rs2 are reserved for future standard use.",unknown,unknown,high,False, +chunk_dae36684,src/priv/hypervisor.adoc,1389,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Memory-Management Fence Instructions","Until their use is defined by a standard extension, they should be zeroed by software and ignored by current implementations.",SW_rule,enum,medium,False, +chunk_5b23e1a5,src/priv/hypervisor.adoc,1389,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Memory-Management Fence Instructions","Furthermore, if VMIDLEN < VMIDMAX, the implementation shall ignore bits VMIDMAX-1:VMIDLEN of the value held in rs2.",non_CSR_parameter,binary,very_high,False, +chunk_3692eb35,src/priv/hypervisor.adoc,1397,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Memory-Management Fence Instructions","If `hgatp`.MODE is changed for a given VMID, an HFENCE.GVMA with rs1=`x0` (and rs2 set to either `x0` or the VMID) must be executed to order subsequent guest translations with the MODE change—even if the old MODE or new MODE is Bare.",CSR_controlled,enum,very_high,False, +chunk_74b59b73,src/priv/hypervisor.adoc,1403,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Memory-Management Fence Instructions","Attempts to execute HFENCE.VVMA or HFENCE.GVMA when V=1 cause a virtual-instruction exception, while attempts to do the same in U-mode cause an illegal-instruction exception.",SW_rule,unknown,high,False, +chunk_6e680c28,src/priv/hypervisor.adoc,1403,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Memory-Management Fence Instructions",Attempting to execute HFENCE.GVMA in HS-mode when `mstatus`.TVM=1 also causes an illegal-instruction exception.,CSR_controlled,enum,high,False, +chunk_81a709fb,src/priv/hypervisor.adoc,1411,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs","The hypervisor extension augments or modifies machine CSRs `mstatus`, `mstatush`, `mideleg`, `mip`, and `mie`, and adds CSRs `mtval2` and `mtinst`.",CSR_controlled,enum,high,False, +chunk_7b60d1f7,src/priv/hypervisor.adoc,1417,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers","The hypervisor extension adds two fields, MPV and GVA, to the machine-level `mstatus` or `mstatush` CSR, and modifies the behavior of several existing `mstatus` fields. shows the modified `mstatus` register when the hypervisor extension is implemented and MXLEN=64.",CSR_controlled,enum,high,False, +chunk_416e3f0d,src/priv/hypervisor.adoc,1417,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers","When MXLEN=32, the hypervisor extension adds MPV and GVA not to `mstatus` but to `mstatush`. shows the `mstatush` register when the hypervisor extension is implemented and MXLEN=32.",CSR_controlled,enum,high,False, +chunk_710c7584,src/priv/hypervisor.adoc,1432,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers",The format of `mstatus` is unchanged for RV32. include::images/bytefield/hypv-mstatush.edn[],CSR_controlled,enum,high,False, +chunk_fc9ef296,src/priv/hypervisor.adoc,1436,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers",The MPV bit (Machine Previous Virtualization Mode) is written by the implementation whenever a trap is taken into M-mode.,unknown,unknown,high,False, +chunk_832e30d4,src/priv/hypervisor.adoc,1436,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers","Just as the MPP field is set to the (nominal) privilege mode at the time of the trap, the MPV bit is set to the value of the virtualization mode V at the time of the trap.",unknown,enum,high,False, +chunk_b17f9a4f,src/priv/hypervisor.adoc,1436,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers","When an MRET instruction is executed, the virtualization mode V is set to MPV, unless MPP=3, in which case V remains 0.",unknown,unknown,high,False, +chunk_1afa2ffe,src/priv/hypervisor.adoc,1444,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers",Field GVA (Guest Virtual Address) is written by the implementation whenever a trap is taken into M-mode.,unknown,enum,high,False, +chunk_7c362052,src/priv/hypervisor.adoc,1444,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers","For any trap (breakpoint, address misaligned, access fault, page fault, or guest-page fault) that writes a guest virtual address to `mtval`, GVA is set to 1.",CSR_controlled,binary,high,False, +chunk_ced2f115,src/priv/hypervisor.adoc,1444,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers","For any other trap into M-mode, GVA is set to 0.",unknown,binary,high,False, +chunk_6dddad15,src/priv/hypervisor.adoc,1451,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers","The TSR and TVM fields of `mstatus` affect execution only in HS-mode, not in VS-mode.",CSR_controlled,enum,high,False, +chunk_d5a01f59,src/priv/hypervisor.adoc,1451,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers",The TW field affects execution in all modes except M-mode.,unknown,enum,high,False, +chunk_63218cf1,src/priv/hypervisor.adoc,1456,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers","Setting TVM=1 prevents HS-mode from accessing `hgatp` or executing HFENCE.GVMA or HINVAL.GVMA, but has no effect on accesses to `vsatp` or instructions HFENCE.VVMA or HINVAL.VVMA.",CSR_controlled,enum,high,False, +chunk_0f363f65,src/priv/hypervisor.adoc,1461,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers","The hypervisor extension changes the behavior of the Modify Privilege field, MPRV, of `mstatus`.",CSR_controlled,enum,high,False, +chunk_f2128774,src/priv/hypervisor.adoc,1461,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers","When MPRV=0, translation and protection behave as normal.",unknown,unknown,high,False, +chunk_00269fc4,src/priv/hypervisor.adoc,1461,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers","When MPRV=1, explicit memory accesses are translated and protected, and endianness is applied, as though the current virtualization mode were set to MPV and the current nominal privilege mode were set to MPP. enumerates the cases.",unknown,enum,high,False, +chunk_17906cbd,src/priv/hypervisor.adoc,1476,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers",|1 |0 |0 |U-level access with HS-level translation and protection only.,unknown,unknown,high,False, +chunk_8d322266,src/priv/hypervisor.adoc,1478,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers",|1 |0 |1 |HS-level access with HS-level translation and protection only.,unknown,unknown,high,False, +chunk_e568182e,src/priv/hypervisor.adoc,1480,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers",|1 |- |3 |M-level access with no translation.,unknown,unknown,high,False, +chunk_f84de12f,src/priv/hypervisor.adoc,1482,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers",|1 |1 |0 |VU-level access with two-stage translation and protection.,unknown,unknown,high,False, +chunk_382f875f,src/priv/hypervisor.adoc,1482,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers","The HS-level MXR bit makes any executable page readable. `vsstatus`.MXR makes readable those pages marked executable at the VS translation stage, but only if readable at the guest-physical translation stage.",CSR_controlled,enum,high,False, +chunk_2ddf2fe5,src/priv/hypervisor.adoc,1487,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers",|1 |1 |1 |VS-level access with two-stage translation and protection.,unknown,unknown,high,False, +chunk_c210b6c0,src/priv/hypervisor.adoc,1487,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers","The HS-level MXR bit makes any executable page readable. `vsstatus`.MXR makes readable those pages marked executable at the VS translation stage, but only if readable at the guest-physical translation stage. `vsstatus`.SUM applies instead of the HS-level SUM bit. |",CSR_controlled,enum,high,False, +chunk_15e20f00,src/priv/hypervisor.adoc,1494,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers","MPRV does not affect the virtual-machine load/store instructions, HLV, HLVX, and HSV.",unknown,unknown,high,False, +chunk_875a74cb,src/priv/hypervisor.adoc,1494,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers","The explicit loads and stores of these instructions always act as though V=1 and the nominal privilege mode were `hstatus`.SPVP, overriding MPRV.",CSR_controlled,enum,high,False, +chunk_5c58504f,src/priv/hypervisor.adoc,1500,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers",The `mstatus` register is a superset of the HS-level `sstatus` register but is not a superset of `vsstatus`.,CSR_controlled,enum,high,False, +chunk_f95c4773,src/priv/hypervisor.adoc,1505,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Interrupt Delegation (`mideleg`) Register","When the hypervisor extension is implemented, bits 10, 6, and 2 of `mideleg` (corresponding to the standard VS-level interrupts) are each read-only one.",CSR_controlled,enum,high,False, +chunk_b5ea0401,src/priv/hypervisor.adoc,1505,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Interrupt Delegation (`mideleg`) Register","Furthermore, if any guest external interrupts are implemented (GEILEN is nonzero), bit 12 of `mideleg` (corresponding to supervisor-level guest external interrupts) is also read-only one. VS-level interrupts and guest external interrupts are always delegated past M-mode to HS-mode.",CSR_controlled,enum,high,False, +chunk_a7b9e527,src/priv/hypervisor.adoc,1514,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Interrupt Delegation (`mideleg`) Register","For bits of `mideleg` that are zero, the corresponding bits in `hideleg`, `hip`, and `hie` are read-only zeros.",CSR_controlled,binary,high,False, +chunk_da29e809,src/priv/hypervisor.adoc,1520,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers",The hypervisor extension gives registers `mip` and `mie` additional active bits for the hypervisor-added interrupts. and show the standard portions (bits 15:0) of registers `mip` and `mie` when the hypervisor extension is implemented.,CSR_controlled,enum,high,False, +chunk_8b4571db,src/priv/hypervisor.adoc,1534,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers","Bits SGEIP, VSEIP, VSTIP, and VSSIP in `mip` are aliases for the same bits in hypervisor CSR `hip`, while SGEIE, VSEIE, VSTIE, and VSSIE in `mie` are aliases for the same bits in `hie`.",CSR_controlled,enum,high,False, +chunk_fe493137,src/priv/hypervisor.adoc,1541,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Second Trap Value (`mtval2`) Register",The `mtval2` register is an MXLEN-bit read/write register formatted as shown in .,CSR_controlled,range,high,False, +chunk_4b675bb9,src/priv/hypervisor.adoc,1541,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Second Trap Value (`mtval2`) Register","When a trap is taken into M-mode, `mtval2` is written with additional exception-specific information, alongside `mtval`, to assist software in handling the trap.",CSR_controlled,enum,high,False, +chunk_7cc21a12,src/priv/hypervisor.adoc,1551,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Second Trap Value (`mtval2`) Register","When a guest-page-fault trap is taken into M-mode, `mtval2` is written with either zero or the guest physical address that faulted, shifted right by 2 bits.",CSR_controlled,range,high,False, +chunk_5c95a968,src/priv/hypervisor.adoc,1551,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Second Trap Value (`mtval2`) Register","For other traps, `mtval2` is set to zero, but a future standard or extension may redefine `mtval2's` setting for other traps.",CSR_controlled,binary,high,False, +chunk_55c0cc71,src/priv/hypervisor.adoc,1557,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Second Trap Value (`mtval2`) Register","If a guest-page fault is due to an implicit memory access during first-stage (VS-stage) address translation, a guest physical address written to `mtval2` is that of the implicit memory access that faulted.",CSR_controlled,enum,high,False, +chunk_9eccbcb3,src/priv/hypervisor.adoc,1557,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Second Trap Value (`mtval2`) Register",Additional information is provided in CSR `mtinst` to disambiguate such situations.,CSR_controlled,enum,high,False, +chunk_b4ccc89f,src/priv/hypervisor.adoc,1564,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Second Trap Value (`mtval2`) Register","Otherwise, for misaligned loads and stores that cause guest-page faults, a nonzero guest physical address in `mtval2` corresponds to the faulting portion of the access as indicated by the virtual address in `mtval`.",CSR_controlled,enum,high,False, +chunk_5789f21d,src/priv/hypervisor.adoc,1564,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Second Trap Value (`mtval2`) Register","For instruction guest-page faults on systems with variable-length instructions, a nonzero `mtval2` corresponds to the faulting portion of the instruction as indicated by the virtual address in `mtval`.",CSR_controlled,enum,high,False, +chunk_c6da0336,src/priv/hypervisor.adoc,1572,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Second Trap Value (`mtval2`) Register","`mtval2` is a *WARL* register that must be able to hold zero and may be capable of holding only an arbitrary subset of other 2-bit-shifted guest physical addresses, if any.",CSR_controlled,range,very_high,False, +chunk_ca921bc7,src/priv/hypervisor.adoc,1584,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Trap Instruction (`mtinst`) Register",The `mtinst` register is an MXLEN-bit read/write register formatted as shown in .,CSR_controlled,range,high,False, +chunk_9bebe7e3,src/priv/hypervisor.adoc,1584,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Trap Instruction (`mtinst`) Register","When a trap is taken into M-mode, `mtinst` is written with a value that, if nonzero, provides information about the instruction that trapped, to assist software in handling the trap.",SW_rule,unknown,high,False, +chunk_e07ad9d3,src/priv/hypervisor.adoc,1584,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Trap Instruction (`mtinst`) Register",The values that may be written to `mtinst` on a trap are documented in .,non_CSR_parameter,enum,high,False, +chunk_b61ada3f,src/priv/hypervisor.adoc,1596,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Trap Instruction (`mtinst`) Register",`mtinst` is a *WARL* register that need only be able to hold the values that the implementation may automatically write to it on a trap.,CSR_controlled,enum,very_high,False, +chunk_a2530cb4,src/priv/hypervisor.adoc,1603,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation","For any virtual memory access, the original virtual address is converted in the first stage by VS-level address translation, as controlled by the `vsatp` register, into a guest physical address.",CSR_controlled,enum,high,False, +chunk_32db608b,src/priv/hypervisor.adoc,1603,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation","The guest physical address is then converted in the second stage by guest physical address translation, as controlled by the `hgatp` register, into a supervisor physical address.",CSR_controlled,enum,high,False, +chunk_7b0b0112,src/priv/hypervisor.adoc,1603,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation","Although there is no option to disable two-stage address translation when V=1, either stage of translation can be effectively disabled by zeroing the corresponding `vsatp` or `hgatp` register.",CSR_controlled,binary,high,False, +chunk_9bb20607,src/priv/hypervisor.adoc,1616,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation","The `vsstatus` field MXR, which makes execute-only pages readable by explicit loads, only overrides VS-stage page protection.",CSR_controlled,enum,high,False, +chunk_bd1e0cad,src/priv/hypervisor.adoc,1622,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation","When V=1, memory accesses that would normally bypass address translation are subject to G-stage address translation alone.",unknown,unknown,high,False, +chunk_269bb636,src/priv/hypervisor.adoc,1635,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest Physical Address Translation",The mapping of guest physical addresses to supervisor physical addresses is controlled by CSR `hgatp` ().,CSR_controlled,enum,high,False, +chunk_599e7525,src/priv/hypervisor.adoc,1638,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest Physical Address Translation","When the address translation scheme selected by the MODE field of `hgatp` is Bare, guest physical addresses are equal to supervisor physical addresses without modification, and no memory protection applies in the trivial translation of guest physical addresses to supervisor physical addresses.",CSR_controlled,range,high,False, +chunk_342abb64,src/priv/hypervisor.adoc,1645,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest Physical Address Translation","When `hgatp`.MODE specifies a translation scheme of Sv32x4, Sv39x4, Sv48x4, or Sv57x4, G-stage address translation is a variation on the usual page-based virtual address translation scheme of Sv32, Sv39, Sv48, or Sv57, respectively.",CSR_controlled,enum,high,False, +chunk_f2a0152c,src/priv/hypervisor.adoc,1645,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest Physical Address Translation","In each case, the size of the incoming address is widened by 2 bits (to 34, 41, 50, or 59 bits).",non_CSR_parameter,range,medium,False, +chunk_f6fcdf64,src/priv/hypervisor.adoc,1645,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest Physical Address Translation","Matching its larger size, the root page table also must be aligned to a 16 KiB boundary instead of the usual 4 KiB page boundary.",non_CSR_parameter,enum,very_high,False, +chunk_30518d9b,src/priv/hypervisor.adoc,1674,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest Physical Address Translation","Address bits 63:41 must all be zeros, or else a guest-page-fault exception occurs.",non_CSR_parameter,binary,very_high,False, +chunk_bbd9acb6,src/priv/hypervisor.adoc,1684,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest Physical Address Translation","Address bits 63:50 must all be zeros, or else a guest-page-fault exception occurs.",non_CSR_parameter,binary,very_high,False, +chunk_b2b32942,src/priv/hypervisor.adoc,1696,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest Physical Address Translation","Address bits 63:59 must all be zeros, or else a guest-page-fault exception occurs.",non_CSR_parameter,binary,very_high,False, +chunk_6b372605,src/priv/hypervisor.adoc,1714,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest Physical Address Translation","`hgatp` substitutes for the usual `satp`; * for the translation to begin, the effective privilege mode must be VS-mode or VU-mode; * when checking the U bit, the current privilege mode is always taken to be U-mode; and * guest-page-fault exceptions are raised instead of regular page-fault exceptions.",CSR_controlled,enum,very_high,False, +chunk_1f606eb7,src/priv/hypervisor.adoc,1722,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest Physical Address Translation","Access type permissions—readable, writable, or executable—are checked during G-stage translation the same as for VS-stage translation.",unknown,unknown,high,False, +chunk_c830f541,src/priv/hypervisor.adoc,1722,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest Physical Address Translation","For a memory access made to support VS-stage address translation (such as to read/write a VS-level page table), permissions and the need to set A and/or D bits at the G-stage level are checked as though for an implicit load or store, not for the original access type.",CSR_controlled,unknown,high,False, +chunk_0419f649,src/priv/hypervisor.adoc,1722,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest Physical Address Translation","However, any exception is always reported for the original access type (instruction, load, or store/AMO).",unknown,unknown,high,False, +chunk_2d7471f8,src/priv/hypervisor.adoc,1735,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest Physical Address Translation","Until its use is defined by a standard extension, it should be cleared by software for forward compatibility, and must be ignored by hardware.",SW_rule,enum,very_high,False, +chunk_369b03a0,src/priv/hypervisor.adoc,1742,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest-Page Faults","Guest-page-fault traps may be delegated from M-mode to HS-mode under the control of CSR `medeleg`, but cannot be delegated to other privilege modes.",CSR_controlled,enum,high,False, +chunk_26de2edd,src/priv/hypervisor.adoc,1742,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest-Page Faults","On a guest-page fault, CSR `mtval` or `stval` is written with the faulting guest virtual address as usual, and `mtval2` or `htval` is written either with zero or with the faulting guest physical address, shifted right by 2 bits. CSR `mtinst` or `htinst` may also be written with information about the faulting instruction or other reason for the access, as explained in .",CSR_controlled,range,high,False, +chunk_47eb33f9,src/priv/hypervisor.adoc,1752,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest-Page Faults","When an instruction fetch or a misaligned memory access straddles a page boundary, two different address translations are involved.",unknown,unknown,high,False, +chunk_386c9d17,src/priv/hypervisor.adoc,1752,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest-Page Faults","When a guest-page fault occurs in such a circumstance, the faulting virtual address written to `mtval`/`stval` is the same as would be required for a regular page fault.",CSR_controlled,enum,high,False, +chunk_87b440f0,src/priv/hypervisor.adoc,1752,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest-Page Faults","Thus, the faulting virtual address may be a page-boundary address that is higher than the instruction's original virtual address, if the byte at that page boundary is among the accessed bytes.",non_CSR_parameter,enum,high,False, +chunk_6023d93a,src/priv/hypervisor.adoc,1762,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest-Page Faults","When a guest-page fault is not due to an implicit memory access for VS-stage address translation, a nonzero guest physical address written to `mtval2`/`htval` shall correspond to the exact virtual address written to `mtval`/`stval`.",CSR_controlled,enum,very_high,False, +chunk_31bc138b,src/priv/hypervisor.adoc,1771,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Memory-Management Fences","When V=0, the virtual-address argument is an HS-level virtual address, and the ASID argument is an HS-level ASID.",unknown,unknown,high,False, +chunk_84ddae0e,src/priv/hypervisor.adoc,1778,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Memory-Management Fences","When V=1, the virtual-address argument to SFENCE.VMA is a guest virtual address within the current virtual machine, and the ASID argument is a VS-level ASID within the current virtual machine.",SW_rule,unknown,high,False, +chunk_a589e043,src/priv/hypervisor.adoc,1778,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Memory-Management Fences","The current virtual machine is identified by the VMID field of CSR `hgatp`, and the effective ASID can be considered to be the combination of this VMID with the VS-level ASID.",CSR_controlled,enum,high,False, +chunk_a68aafcc,src/priv/hypervisor.adoc,1793,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Memory-Management Fences","It is noted there that, when PMP settings are modified in a manner that affects either the physical memory that holds page tables or the physical memory to which page tables point, M-mode software must synchronize the PMP settings with the virtual memory system.",SW_rule,enum,very_high,False, +chunk_71119529,src/priv/hypervisor.adoc,1793,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Memory-Management Fences","For HS-level address translation, this is accomplished by executing in M-mode an SFENCE.VMA instruction with rs1=`x0` and rs2=`x0`, after the PMP CSRs are written.",CSR_controlled,enum,high,False, +chunk_d245a42b,src/priv/hypervisor.adoc,1808,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Memory-Management Fences","Similarly, if the setting of the PBMTE or ADUE bits in `menvcfg` are changed, an HFENCE.GVMA instruction with rs1=`x0` and rs2=`x0` suffices to synchronize with respect to the altered interpretation of G-stage and VS-stage PTEs' PBMT and A/D bit fields, respectively.",CSR_controlled,enum,high,False, +chunk_478c5876,src/priv/hypervisor.adoc,1813,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Memory-Management Fences","By contrast, if the PBMTE or ADUE bits in `henvcfg` are changed, executing an HFENCE.VVMA with rs1=`x0` and rs2=`x0` suffices to synchronize with respect to the altered interpretation of VS-stage PTEs' PBMT and A/D bit fields for the currently active VMID.",CSR_controlled,enum,high,False, +chunk_ef9751d6,src/priv/hypervisor.adoc,1818,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Memory-Management Fences","Hence, to prevent speculative execution causing one guest's VS-stage translations to be cached under another guest's VMID, world-switch code should zero `vsatp`, then swap `hgatp`, then finally write the new `vsatp` value.",CSR_controlled,enum,high,False, +chunk_fa44f06d,src/priv/hypervisor.adoc,1818,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Memory-Management Fences","Similarly, if `henvcfg`.PBMTE/ADUE need be world-switched, they should be switched after zeroing `vsatp` but before writing the new `vsatp` value, obviating the need to execute an HFENCE.VVMA instruction.",CSR_controlled,enum,high,False, +chunk_ffbf9280,src/priv/hypervisor.adoc,1829,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Interaction with Pointer Masking","Guest physical addresses (GPAs) are 2 bits wider than the corresponding virtual address translation modes, resulting in additional address translation schemes Sv32x4, Sv39x4, Sv48x4, and Sv57x4 for translating guest physical addresses to supervisor physical addresses.",non_CSR_parameter,range,medium,False, +chunk_fc06d024,src/priv/hypervisor.adoc,1829,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Interaction with Pointer Masking","When running with virtualization in VS/VU mode with `vsatp.MODE` = Bare, this means that those two bits may be subject to pointer masking, depending on `hgatp.MODE` and `senvcfg.PMM`/`henvcfg.PMM` (for VU/VS mode).",CSR_controlled,enum,high,False, +chunk_ef4cce0b,src/priv/hypervisor.adoc,1829,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Interaction with Pointer Masking","If `vsatp.MODE` != BARE, this issue does *not* apply.",CSR_controlled,enum,high,False, +chunk_dca7c426,src/priv/hypervisor.adoc,1837,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Interaction with Pointer Masking","To support implementations where (XLEN-PMLEN) can be less than the GPA width supported by `hgatp.MODE`, hypervisors should execute an `HFENCE.GVMA` with rs1=`x0` if the `henvcfg.PMM` is changed from or to a value where (XLEN-PMLEN) is less than GPA width supported by the `hgatp` translation mode of that guest.",CSR_controlled,range,high,False, +chunk_5f5bdda9,src/priv/hypervisor.adoc,1843,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Interaction with Pointer Masking",`PMLEN=7` and `hgatp.MODE=sv57x4` * `PMLEN=16` and `hgatp.MODE=sv57x4` * `PMLEN=16` and `hgatp.MODE=sv48x4`,CSR_controlled,enum,high,False, +chunk_be4a5ca9,src/priv/hypervisor.adoc,1847,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Interaction with Pointer Masking","Implementation of an address-specific `HFENCE.GVMA` should either ignore the address argument, or should ignore the top masked GPA bits of entries when comparing for an address match.",SW_rule,enum,high,False, +chunk_f4dad70c,src/priv/hypervisor.adoc,1856,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes",The hypervisor extension augments the trap cause encoding. lists the possible M-mode and HS-mode trap cause codes when the hypervisor extension is implemented.,SW_rule,enum,high,False, +chunk_eaa6c765,src/priv/hypervisor.adoc,1856,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes","Codes are added for VS-level interrupts (interrupts 2, 6, 10), for supervisor-level guest external interrupts (interrupt 12), for virtual-instruction exceptions (exception 22), and for guest-page faults (exceptions 20, 21, 23).",unknown,unknown,high,False, +chunk_dd5b99e4,src/priv/hypervisor.adoc,2010,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes","An instruction is HS-qualified if it would be valid to execute in HS-mode (for some values of the instruction's register operands), assuming fields TSR and TVM of CSR `mstatus` are both zero.",CSR_controlled,enum,high,False, +chunk_81ab7a59,src/priv/hypervisor.adoc,2020,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes",A special rule applies for CSR instructions that access 32-bit high-half CSRs such as `cycleh` and `htimedeltah`.,CSR_controlled,range,high,False, +chunk_0cc21555,src/priv/hypervisor.adoc,2029,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes","Specifically, a virtual-instruction exception is raised for the following cases:",non_CSR_parameter,unknown,high,False, +chunk_06ee4487,src/priv/hypervisor.adoc,2032,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes","in VS-mode, attempts to access a non-high-half counter CSR when the corresponding bit in `hcounteren` is 0 and the same bit in `mcounteren` is 1;",CSR_controlled,enum,high,False, +chunk_8997343a,src/priv/hypervisor.adoc,2036,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes","in VS-mode, if XLEN=32, attempts to access a high-half counter CSR when the corresponding bit in `hcounteren` is 0 and the same bit in `mcounteren` is 1;",CSR_controlled,enum,high,False, +chunk_ff8b535a,src/priv/hypervisor.adoc,2040,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes","in VU-mode, attempts to access a non-high-half counter CSR when the corresponding bit in either `hcounteren` or `scounteren` is 0 and the same bit in `mcounteren` is 1;",CSR_controlled,enum,high,False, +chunk_9f42f1f3,src/priv/hypervisor.adoc,2044,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes","in VU-mode, if XLEN=32, attempts to access a high-half counter CSR when the corresponding bit in either `hcounteren` or `scounteren` is 0 and the same bit in `mcounteren` is 1;",CSR_controlled,enum,high,False, +chunk_fde5fa8d,src/priv/hypervisor.adoc,2051,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes","in VS-mode or VU-mode, attempts to access an implemented non-high-half hypervisor CSR or VS CSR when the same access (read/write) would be allowed in HS-mode, assuming `mstatus`.TVM=0;",CSR_controlled,enum,high,False, +chunk_db911038,src/priv/hypervisor.adoc,2055,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes","in VS-mode or VU-mode, if XLEN=32, attempts to access an implemented high-half hypervisor CSR or high-half VS CSR when the same access (read/write) to the CSR""s low-half partner would be allowed in HS-mode, assuming `mstatus`.TVM=0;",CSR_controlled,enum,high,False, +chunk_d2c6ed2a,src/priv/hypervisor.adoc,2060,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes","in VU-mode, attempts to execute WFI when `mstatus`.TW=0, or to execute a supervisor instruction (SRET or SFENCE);",CSR_controlled,enum,high,False, +chunk_0e1df0bc,src/priv/hypervisor.adoc,2064,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes","in VU-mode, attempts to access an implemented non-high-half supervisor CSR when the same access (read/write) would be allowed in HS-mode, assuming `mstatus`.TVM=0;",CSR_controlled,enum,high,False, +chunk_491c6f29,src/priv/hypervisor.adoc,2068,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes","in VU-mode, if XLEN=32, attempts to access an implemented high-half supervisor CSR when the same access to the CSR's low-half partner would be allowed in HS-mode, assuming `mstatus`.TVM=0;",CSR_controlled,enum,high,False, +chunk_29238bfa,src/priv/hypervisor.adoc,2072,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes","in VS-mode, attempts to execute WFI when `hstatus`.VTW=1 and `mstatus`.TW=0, unless the instruction completes within an implementation-specific, bounded time;",CSR_controlled,enum,high,False, +chunk_53eff9c5,src/priv/hypervisor.adoc,2076,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes","in VS-mode, attempts to execute SRET when `hstatus`.VTSR=1; and",CSR_controlled,enum,high,False, +chunk_0ccec86f,src/priv/hypervisor.adoc,2078,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes","in VS-mode, attempts to execute an SFENCE.VMA or SINVAL.VMA instruction or to access `satp`, when `hstatus`.VTVM=1.",CSR_controlled,enum,high,False, +chunk_701ba8a4,src/priv/hypervisor.adoc,2081,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes",Other extensions to the RISC-V Privileged Architecture may add to the set of circumstances that cause a virtual-instruction exception when V=1.,non_CSR_parameter,enum,high,False, +chunk_e777f3f0,src/priv/hypervisor.adoc,2085,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes","On a virtual-instruction trap, `mtval` or `stval` is written the same as for an illegal-instruction trap.",CSR_controlled,enum,high,False, +chunk_a6e433ca,src/priv/hypervisor.adoc,2089,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes",Fields FS and VS in registers `sstatus` and `vsstatus` deviate from the usual HS-qualified rule.,CSR_controlled,enum,high,False, +chunk_5775df11,src/priv/hypervisor.adoc,2105,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes","| .>|12, 20, 1 |During instruction address translation: + {nbsp}{nbsp}{nbsp}First encountered page fault, guest-page fault, or access fault",unknown,unknown,high,False, +chunk_3734ffc5,src/priv/hypervisor.adoc,2109,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes",| .>|1 |With physical address for instruction: + {nbsp}{nbsp}{nbsp}Instruction access fault,unknown,unknown,high,False, +chunk_b4e86448,src/priv/hypervisor.adoc,2112,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes","| |2 + 22 + 0 + 8, 9, 10, 11 + 3 + 3|Illegal instruction + Virtual instruction + Instruction address misaligned + Environment call + Environment break + {nbsp}{nbsp}{nbsp}Load/store/AMO address breakpoint",non_CSR_parameter,unknown,high,False, +chunk_1c8084c3,src/priv/hypervisor.adoc,2127,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes","| .>|13, 15, 21, 23, 5, 7 |During address translation for an explicit memory access: + {nbsp}{nbsp}{nbsp}First encountered page fault, guest-page fault, or access fault",unknown,unknown,high,False, +chunk_612fb897,src/priv/hypervisor.adoc,2131,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes","| .>|5, 7 |With physical address for an explicit memory access: + {nbsp}{nbsp}{nbsp}Load/store/AMO access fault",unknown,unknown,high,False, +chunk_c51ebb0f,src/priv/hypervisor.adoc,2134,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes",If not higher priority: + {nbsp}{nbsp}{nbsp}Load/store/AMO address misaligned |,unknown,unknown,high,False, +chunk_fb76568a,src/priv/hypervisor.adoc,2138,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes","If an instruction may raise multiple synchronous exceptions, the decreasing priority order of indicates which exception is taken and reported in `mcause` or `scause`.",CSR_controlled,enum,high,False, +chunk_24fc34ea,src/priv/hypervisor.adoc,2145,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Entry","When a trap occurs in HS-mode or U-mode, it goes to M-mode, unless delegated by `medeleg` or `mideleg`, in which case it goes to HS-mode.",CSR_controlled,enum,high,False, +chunk_a5a5d2dc,src/priv/hypervisor.adoc,2145,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Entry","When a trap occurs in VS-mode or VU-mode, it goes to M-mode, unless delegated by `medeleg` or `mideleg`, in which case it goes to HS-mode, unless further delegated by `hedeleg` or `hideleg`, in which case it goes to VS-mode.",CSR_controlled,enum,high,False, +chunk_a73d2a82,src/priv/hypervisor.adoc,2153,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Entry","When a trap is taken into M-mode, virtualization mode V gets set to 0, and fields MPV and MPP in `mstatus` (or `mstatush`) are set according to . A trap into M-mode also writes fields GVA, MPIE, and MIE in `mstatus`/`mstatush` and writes CSRs `mepc`, `mcause`, `mtval`, `mtval2`, and `mtinst`.",CSR_controlled,binary,high,False, +chunk_9b199fb3,src/priv/hypervisor.adoc,2160,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Entry","Upon trap return, MPV is ignored when MPP=3. | |Previous Mode |MPV |MPP |U-mode + HS-mode + M-mode|0 + 0 + 0|0 + 1 + 3 |VU-mode + VS-mode|1 + 1|0 + 1 |",unknown,unknown,high,False, +chunk_8f18df7e,src/priv/hypervisor.adoc,2178,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Entry","When a trap is taken into HS-mode, virtualization mode V is set to 0, and `hstatus`.SPV and `sstatus`.SPP are set according to .",CSR_controlled,binary,high,False, +chunk_5bbd5b3f,src/priv/hypervisor.adoc,2178,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Entry","If V was 1 before the trap, field SPVP in `hstatus` is set the same as `sstatus`.SPP; otherwise, SPVP is left unchanged. A trap into HS-mode also writes field GVA in `hstatus`, fields SPIE and SIE in `sstatus`, and CSRs `sepc`, `scause`, `stval`, `htval`, and `htinst`.",CSR_controlled,enum,high,False, +chunk_068959bb,src/priv/hypervisor.adoc,2202,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Entry","When a trap is taken into VS-mode, `vsstatus`.SPP is set according to .",CSR_controlled,enum,high,False, +chunk_be568592,src/priv/hypervisor.adoc,2202,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Entry","Register `hstatus` and the HS-level `sstatus` are not modified, and the virtualization mode V remains 1. A trap into VS-mode also writes fields SPIE and SIE in `vsstatus` and writes CSRs `vsepc`, `vscause`, and `vstval`.",CSR_controlled,enum,high,False, +chunk_c5afdc44,src/priv/hypervisor.adoc,2222,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`","On any trap into M-mode or HS-mode, one of these values is written automatically into the appropriate trap instruction CSR, `mtinst` or `htinst`:",CSR_controlled,enum,high,False, +chunk_e893690b,src/priv/hypervisor.adoc,2227,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`",zero; * a transformation of the trapping instruction; * a custom value (allowed only if the trapping instruction is non-standard); or * a special pseudoinstruction.,unknown,unknown,high,False, +chunk_df7fc916,src/priv/hypervisor.adoc,2233,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`","Except when a pseudoinstruction value is required (described later), the value written to `mtinst` or `htinst` may always be zero, indicating that the hardware is providing no information in the register for this particular trap.",non_CSR_parameter,enum,high,False, +chunk_16c619bf,src/priv/hypervisor.adoc,2238,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`","On an interrupt, the value written to the trap instruction register is always zero.",unknown,unknown,high,False, +chunk_24cc76a6,src/priv/hypervisor.adoc,2238,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`","On a synchronous exception, if a nonzero value is written, one of the following shall be true about the value:",non_CSR_parameter,enum,very_high,False, +chunk_394c6ef8,src/priv/hypervisor.adoc,2243,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`",The instruction that trapped is a non-standard instruction.,unknown,unknown,high,False, +chunk_80469efb,src/priv/hypervisor.adoc,2263,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`","These three cases exclude a large number of other possible values, such as all those having bits 1:0 equal to binary `10`. A future standard or extension may define additional cases, thus allowing values that are currently excluded.",non_CSR_parameter,range,high,False, +chunk_149ceadf,src/priv/hypervisor.adoc,2263,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`",Software may safely treat an unrecognized value in a trap instruction register the same as zero.,SW_rule,enum,high,False, +chunk_bef5959a,src/priv/hypervisor.adoc,2269,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`",shows the values that may be automatically written to the trap instruction register for each standard exception cause.,non_CSR_parameter,enum,high,False, +chunk_745587fd,src/priv/hypervisor.adoc,2269,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`","For exceptions that prevent the fetching of an instruction, only zero or a pseudoinstruction value may be written. A custom value may be automatically written only if the instruction that traps is non-standard. A future standard or extension may permit other values to be written, chosen from the set of allowed values established earlier.",non_CSR_parameter,enum,high,False, +chunk_8c1069c2,src/priv/hypervisor.adoc,2366,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`","As enumerated in the table, a synchronous exception may write to the trap instruction register a standard transformation of the trapping instruction only for exceptions that arise from explicit memory accesses (from loads, stores, and AMO instructions).",non_CSR_parameter,enum,high,False, +chunk_5ef16e19,src/priv/hypervisor.adoc,2366,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`","If a synchronous trap occurs for a standard instruction for which no transformation has been defined, the trap instruction register shall be written with zero (or, under certain circumstances, with a special pseudoinstruction value).",non_CSR_parameter,binary,very_high,False, +chunk_8647653d,src/priv/hypervisor.adoc,2396,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`","All fields are the same as the trapping instruction except bits 19:15, Addr.",unknown,enum,high,False, +chunk_8432733c,src/priv/hypervisor.adoc,2402,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`","All fields are the same as the trapping instruction except bits 19:15, Addr.",unknown,enum,high,False, +chunk_bba5be3c,src/priv/hypervisor.adoc,2406,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`",Offset field that replaces the instruction’s rs1 field in bits 19:15 is the positive difference between the faulting virtual address (written to `mtval` or `stval`) and the original virtual address.,CSR_controlled,enum,high,False, +chunk_48220cff,src/priv/hypervisor.adoc,2414,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`","For a standard compressed instruction (16-bit size), the transformed instruction is found as follows:",non_CSR_parameter,range,medium,False, +chunk_eceff6b1,src/priv/hypervisor.adoc,2417,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`",Expand the compressed instruction to its 32-bit equivalent. .,non_CSR_parameter,range,medium,False, +chunk_e3d04ea6,src/priv/hypervisor.adoc,2417,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`",Transform the 32-bit equivalent instruction. .,non_CSR_parameter,range,medium,False, +chunk_212bc87d,src/priv/hypervisor.adoc,2421,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`",Bits 1:0 of a transformed standard instruction will be binary `01` if the trapping instruction is compressed and `11` if not.,unknown,unknown,high,False, +chunk_fffc4541,src/priv/hypervisor.adoc,2421,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`","For guest-page faults, the trap instruction register is written with a special pseudoinstruction value if: (a) the fault is caused by an implicit memory access for VS-stage address translation, and (b) a nonzero value (the faulting guest physical address) is written to `mtval2` or `htval`.",CSR_controlled,enum,high,False, +chunk_2b6cc690,src/priv/hypervisor.adoc,2421,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`","If both conditions are met, the value written to `mtinst` or `htinst` must be taken from ; zero is not allowed.",non_CSR_parameter,binary,very_high,False, +chunk_9a304863,src/priv/hypervisor.adoc,2432,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`","The RV32 values are used when VSXLEN=32, and the RV64 values when VSXLEN=64. | |Value |Meaning |`0x00002000` + `0x00002020` |32-bit read for VS-stage address translation (RV32) + 32-bit write for VS-stage address translation (RV32)",non_CSR_parameter,range,high,False, +chunk_21b709a3,src/priv/hypervisor.adoc,2442,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`",|`0x00003000` + `0x00003020` |64-bit read for VS-stage address translation (RV64) + 64-bit write for VS-stage address translation (RV64) |,non_CSR_parameter,range,medium,False, +chunk_1487f3e0,src/priv/hypervisor.adoc,2468,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`","If a machine never automatically updates bits A or D in VS-level page tables (leaving this to software), the write case will never arise.",SW_rule,unknown,high,False, +chunk_8b7badfd,src/priv/hypervisor.adoc,2468,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`","The fact that such a page table update must actually be atomic, not just a simple write, is ignored for the pseudoinstruction.",non_CSR_parameter,enum,very_high,False, +chunk_0ba95008,src/priv/hypervisor.adoc,2480,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Return","The MRET instruction is used to return from a trap taken into M-mode. MRET first determines what the new privilege mode will be according to the values of MPP and MPV in `mstatus` or `mstatush`, as encoded in . MRET then in `mstatus`/`mstatush` sets MPV=0, MPP=0, MIE=MPIE, and MPIE=1.",CSR_controlled,enum,high,False, +chunk_82a02977,src/priv/hypervisor.adoc,2480,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Return","Lastly, MRET sets the privilege mode as previously determined, and sets `pc`=`mepc`.",CSR_controlled,enum,high,False, +chunk_4b5c75c2,src/priv/hypervisor.adoc,2488,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Return",The SRET instruction is used to return from a trap taken into HS-mode or VS-mode.,unknown,unknown,high,False, +chunk_e351ea1c,src/priv/hypervisor.adoc,2492,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Return","Lastly, SRET sets the privilege mode as previously determined, and sets `pc`=`sepc`.",CSR_controlled,enum,high,False, +chunk_8816ee5b,src/priv/hypervisor.adoc,2505,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Return","If the Ssdbltrp extension is implemented, when `SRET` is executed in HS-mode, if the new privilege mode is VU, the `SRET` instruction sets `vsstatus.SDT` to 0.",CSR_controlled,enum,high,False, +chunk_b1f4ca1d,src/priv/hypervisor.adoc,2505,"Preamble > ""H"" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Return","When executed in VS-mode, `vsstatus.SDT` is set to 0.",CSR_controlled,binary,high,False, +chunk_e9a76ac0,src/priv/machine.adoc,14,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs","In addition to the machine-level CSRs described in this section, M-mode code can access all CSRs at lower privilege levels.",CSR_controlled,enum,high,False, +chunk_6f06d230,src/priv/machine.adoc,20,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register",The `misa` CSR is a *WARL* read-write register reporting the ISA supported by the hart.,CSR_controlled,enum,very_high,False, +chunk_9819937e,src/priv/machine.adoc,20,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register","This register must be readable in any implementation, but a value of zero can be returned to indicate the `misa` register has not been implemented, requiring that CPU capabilities be determined through a separate non-standard mechanism.",SW_rule,enum,very_high,False, +chunk_4c7438f4,src/priv/machine.adoc,28,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register",The MXL (Machine XLEN) field encodes the native base integer ISA width as shown in .,unknown,enum,high,False, +chunk_4d93702e,src/priv/machine.adoc,28,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register",The MXL field is read-only.,CSR_controlled,enum,high,False, +chunk_fc2a1c69,src/priv/machine.adoc,28,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register","If `misa` is nonzero, the MXL field indicates the effective XLEN in M-mode, a constant termed MXLEN. XLEN is never greater than MXLEN, but XLEN might be smaller than MXLEN in less-privileged modes.",unknown,range,high,False, +chunk_22a2b799,src/priv/machine.adoc,49,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register",The `misa` CSR is MXLEN bits wide.,CSR_controlled,range,high,False, +chunk_36d79ce7,src/priv/machine.adoc,51,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register","The Extensions field encodes the presence of the standard extensions, with a single bit per letter of the alphabet (bit 0 encodes presence of extension ""A"" , bit 1 encodes presence of extension ""B"", through to bit 25 which encodes ""Z"").",unknown,enum,high,False, +chunk_991a2ee1,src/priv/machine.adoc,51,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register","The ""I"" bit will be set for the RV32I and RV64I base ISAs, and the ""E"" bit will be set for RV32E and RV64E.",unknown,unknown,high,False, +chunk_c8664878,src/priv/machine.adoc,51,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register",The Extensions field is a *WARL* field that can contain writable bits where the implementation allows the supported ISA to be modified.,CSR_controlled,enum,very_high,False, +chunk_76b3c6e2,src/priv/machine.adoc,51,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register","At reset, the Extensions field shall contain the maximal set of supported extensions, and ""I"" shall be selected over ""E"" if both are available.",non_CSR_parameter,enum,very_high,False, +chunk_862bd1c1,src/priv/machine.adoc,62,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register","When a standard extension is disabled by clearing its bit in `misa`, the instructions and CSRs defined or modified by the extension revert to their defined or reserved behaviors as if the extension is not implemented.",CSR_controlled,binary,high,False, +chunk_30c90b78,src/priv/machine.adoc,68,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register",All bits that are reserved for future use must return zero when read.,non_CSR_parameter,binary,very_high,False, +chunk_f7970e21,src/priv/machine.adoc,103,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register","The ""X"" bit will be set if there are any non-standard extensions.",unknown,unknown,high,False, +chunk_a0845f35,src/priv/machine.adoc,105,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register","When the ""B"" bit is 1, the implementation supports the instructions provided by the Zba, Zbb, and Zbs extensions.",unknown,unknown,high,False, +chunk_cb848c3e,src/priv/machine.adoc,105,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register","When the ""B"" bit is 0, it indicates that the implementation might not support one or more of the Zba, Zbb, or Zbs extensions.",unknown,unknown,high,False, +chunk_4aa6eded,src/priv/machine.adoc,109,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register","When the ""M"" bit is 1, the implementation supports all multiply and division instructions defined by the M extension.",unknown,unknown,high,False, +chunk_e9e6c591,src/priv/machine.adoc,109,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register","When the ""M"" bit is 0, it indicates that the implementation might not support those instructions.",unknown,unknown,high,False, +chunk_5f0a7a28,src/priv/machine.adoc,109,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register","However if the Zmmul extension is supported then the multiply instructions it specifies are supported irrespective of the value of the ""M"" bit.",unknown,enum,high,False, +chunk_ca9cd033,src/priv/machine.adoc,116,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register","When the ""S"" bit is 1, the implementation supports supervisor mode.",unknown,unknown,high,False, +chunk_7ba8af4b,src/priv/machine.adoc,116,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register","When the ""S"" bit is 0, the implementation might not support supervisor mode.",unknown,unknown,high,False, +chunk_edfbe79f,src/priv/machine.adoc,119,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register","When the ""U"" bit is 1, the implementation supports user mode.",unknown,unknown,high,False, +chunk_d9961f7f,src/priv/machine.adoc,119,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register","When the ""U"" bit is 0, the implementation might not support user mode.",unknown,unknown,high,False, +chunk_90269600,src/priv/machine.adoc,122,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register","Unless `misa` is all read-only zero, the ""E"" bit always reads as the complement of the ""I"" bit.",CSR_controlled,binary,high,False, +chunk_c0e72d8d,src/priv/machine.adoc,122,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register","If an execution environment supports both RV32E and RV32I, software can select RV32E by clearing the ""I"" bit.",SW_rule,enum,high,False, +chunk_dd12ae84,src/priv/machine.adoc,128,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register","If an ISA feature x depends on an ISA feature y, then attempting to enable feature x but disable feature y results in both features being disabled.",non_CSR_parameter,binary,high,False, +chunk_aa9c505e,src/priv/machine.adoc,128,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register","Similarly, setting ""U""=0 and ""S""=1"" results in both ""U"" and ""S"" being cleared.",non_CSR_parameter,unknown,high,False, +chunk_718b7630,src/priv/machine.adoc,134,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register","An implementation may impose additional constraints on the collective setting of two or more `misa` fields, in which case they function collectively as a single *WARL* field.",CSR_controlled,enum,very_high,False, +chunk_bacd4e20,src/priv/machine.adoc,134,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register",An attempt to write an unsupported combination causes those bits to be set to some supported combination.,unknown,unknown,high,False, +chunk_8e940445,src/priv/machine.adoc,138,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register","If an instruction that would write `misa` increases IALIGN, and the subsequent instruction's address is not IALIGN-bit aligned, the write to `misa` is suppressed, leaving `misa` unchanged.",unknown,unknown,high,False, +chunk_8588ac0f,src/priv/machine.adoc,143,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register","When software enables an extension that was previously disabled, then all state uniquely associated with that extension is UNSPECIFIED, unless otherwise specified by that extension.",SW_rule,binary,high,False, +chunk_db151edd,src/priv/machine.adoc,146,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register","This follows from the fact that, when a feature is not implemented, the corresponding opcodes and CSRs become reserved, not necessarily illegal.",CSR_controlled,enum,high,False, +chunk_672576dc,src/priv/machine.adoc,155,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Vendor ID (`mvendorid`) Register",The `mvendorid` CSR is a 32-bit read-only register providing the JEDEC manufacturer ID of the provider of the core.,CSR_controlled,range,high,False, +chunk_6abd382e,src/priv/machine.adoc,155,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Vendor ID (`mvendorid`) Register","This register must be readable in any implementation, but a value of 0 can be returned to indicate the field is not implemented or that this is a non-commercial implementation.",non_CSR_parameter,enum,very_high,False, +chunk_c3bcd73f,src/priv/machine.adoc,163,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Vendor ID (`mvendorid`) Register","JEDEC manufacturer IDs are ordinarily encoded as a sequence of one-byte continuation codes `0x7f`, terminated by a one-byte ID not equal to `0x7f`, with an odd parity bit in the most-significant bit of each byte. `mvendorid` encodes the number of one-byte continuation codes in the Bank field, and encodes the final byte in the Offset field, discarding the parity bit.",CSR_controlled,range,high,False, +chunk_1fbed088,src/priv/machine.adoc,175,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Architecture ID (`marchid`) Register",The `marchid` CSR is an MXLEN-bit read-only register encoding the base microarchitecture of the hart.,CSR_controlled,range,high,False, +chunk_e002291a,src/priv/machine.adoc,175,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Architecture ID (`marchid`) Register","This register must be readable in any implementation, but a value of 0 can be returned to indicate the field is not implemented.",non_CSR_parameter,enum,very_high,False, +chunk_e7e593be,src/priv/machine.adoc,175,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Architecture ID (`marchid`) Register",The combination of `mvendorid` and `marchid` should uniquely identify the type of hart microarchitecture that is implemented.,CSR_controlled,enum,high,False, +chunk_d1f138cb,src/priv/machine.adoc,184,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Architecture ID (`marchid`) Register","Open-source project architecture IDs are allocated globally by RISC-V International, and have non-zero architecture IDs with a zero most-significant-bit (MSB).",unknown,unknown,high,False, +chunk_2a9fbcfa,src/priv/machine.adoc,184,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Architecture ID (`marchid`) Register","Commercial architecture IDs are allocated by each commercial vendor independently, but must have the MSB set and cannot contain zero in the remaining MXLEN-1 bits.",non_CSR_parameter,range,very_high,False, +chunk_a84843ca,src/priv/machine.adoc,192,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Implementation ID (`mimpid`) Register",The `mimpid` CSR provides a unique encoding of the version of the processor implementation.,CSR_controlled,enum,high,False, +chunk_d6caf0d6,src/priv/machine.adoc,192,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Implementation ID (`mimpid`) Register","This register must be readable in any implementation, but a value of 0 can be returned to indicate that the field is not implemented.",non_CSR_parameter,enum,very_high,False, +chunk_2d95a171,src/priv/machine.adoc,192,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Implementation ID (`mimpid`) Register",The Implementation value should reflect the design of the RISC-V processor itself and not any surrounding system.,non_CSR_parameter,enum,high,False, +chunk_35df174f,src/priv/machine.adoc,203,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Hart ID (`mhartid`) Register",The `mhartid` CSR is an MXLEN-bit read-only register containing the integer ID of the hardware thread running the code.,CSR_controlled,range,high,False, +chunk_d3452757,src/priv/machine.adoc,203,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Hart ID (`mhartid`) Register",This register must be readable in any implementation.,non_CSR_parameter,enum,very_high,False, +chunk_86db0f32,src/priv/machine.adoc,203,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Hart ID (`mhartid`) Register","Hart IDs might not necessarily be numbered contiguously in a multiprocessor system, but one hart must have a hart ID of zero.",non_CSR_parameter,enum,very_high,False, +chunk_314a1b37,src/priv/machine.adoc,203,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Hart ID (`mhartid`) Register",Hart IDs must be unique within the execution environment.,SW_rule,enum,very_high,False, +chunk_71fa0660,src/priv/machine.adoc,216,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers",The `mstatus` register is an MXLEN-bit read/write register formatted as shown in for RV32 and for RV64.,CSR_controlled,range,high,False, +chunk_2134a124,src/priv/machine.adoc,216,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers",The `mstatus` register keeps track of and controls the hart’s current operating state. A restricted view of `mstatus` appears as the `sstatus` register in the S-level ISA.,CSR_controlled,enum,high,False, +chunk_10cb3454,src/priv/machine.adoc,229,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers","For RV32 only, `mstatush` is a 32-bit read/write register formatted as shown in .",CSR_controlled,range,high,False, +chunk_1682a7ed,src/priv/machine.adoc,229,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers",Bits 30:4 of `mstatush` generally contain the same fields found in bits 62:36 of `mstatus` for RV64.,CSR_controlled,enum,high,False, +chunk_30970987,src/priv/machine.adoc,229,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers","Fields SD, SXL, and UXL do not exist in `mstatush`.",CSR_controlled,enum,high,False, +chunk_35778d61,src/priv/machine.adoc,239,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Privilege and Global Interrupt-Enable Stack in `mstatus` register","Global interrupt-enable bits, MIE and SIE, are provided for M-mode and S-mode respectively.",CSR_controlled,enum,high,False, +chunk_31a835a3,src/priv/machine.adoc,239,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Privilege and Global Interrupt-Enable Stack in `mstatus` register",These bits are primarily used to guarantee atomicity with respect to interrupt handlers in the current privilege mode.,unknown,enum,high,False, +chunk_a6b200b1,src/priv/machine.adoc,243,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Privilege and Global Interrupt-Enable Stack in `mstatus` register","When a hart is executing in privilege mode x, interrupts are globally enabled when xIE=1 and globally disabled when xIE=0.",unknown,binary,high,False, +chunk_0130fe70,src/priv/machine.adoc,243,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Privilege and Global Interrupt-Enable Stack in `mstatus` register","Interrupts for lower-privilege modes, w Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Privilege and Global Interrupt-Enable Stack in `mstatus` register","Interrupts for higher-privilege modes, y>x, are always globally enabled regardless of the setting of the global yIE bit for the higher-privilege mode.",unknown,binary,high,False, +chunk_0b5a78e3,src/priv/machine.adoc,243,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Privilege and Global Interrupt-Enable Stack in `mstatus` register",Higher-privilege-level code can use separate per-interrupt enable bits to disable selected higher-privilege-mode interrupts before ceding control to a lower-privilege mode.,unknown,enum,high,False, +chunk_bbb39e07,src/priv/machine.adoc,243,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Privilege and Global Interrupt-Enable Stack in `mstatus` register","If supervisor mode is not implemented, then SIE and SPIE are read-only 0.",CSR_controlled,enum,high,False, +chunk_da8ed0de,src/priv/machine.adoc,255,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Privilege and Global Interrupt-Enable Stack in `mstatus` register","To support nested traps, each privilege mode x that can respond to interrupts has a two-level stack of interrupt-enable bits and privilege modes. xPIE holds the value of the interrupt-enable bit active prior to the trap, and xPP holds the previous privilege mode.",unknown,enum,high,False, +chunk_609c79f5,src/priv/machine.adoc,255,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Privilege and Global Interrupt-Enable Stack in `mstatus` register","The xPP fields can only hold privilege modes up to x, so MPP is two bits wide and SPP is one bit wide.",unknown,enum,high,False, +chunk_cc5270a8,src/priv/machine.adoc,255,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Privilege and Global Interrupt-Enable Stack in `mstatus` register","When a trap is taken from privilege mode y into privilege mode x, xPIE is set to the value of xIE; xIE is set to 0; and xPP is set to y.",unknown,binary,high,False, +chunk_2749fc79,src/priv/machine.adoc,265,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Privilege and Global Interrupt-Enable Stack in `mstatus` register",An MRET or SRET instruction is used to return from a trap in M-mode or S-mode respectively.,unknown,unknown,high,False, +chunk_72ff488f,src/priv/machine.adoc,265,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Privilege and Global Interrupt-Enable Stack in `mstatus` register","When executing an xRET instruction, supposing xPP holds the value y, xIE is set to xPIE; the privilege mode is changed to y; xPIE is set to 1; and xPP is set to the least-privileged supported mode (U if U-mode is implemented, else M).",unknown,binary,high,False, +chunk_46fb9761,src/priv/machine.adoc,265,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Privilege and Global Interrupt-Enable Stack in `mstatus` register","If y{ne}M, xRET also sets MPRV=0.",unknown,unknown,high,False, +chunk_351dd344,src/priv/machine.adoc,272,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Privilege and Global Interrupt-Enable Stack in `mstatus` register",xPP fields are *WARL* fields that can hold only privilege mode x and any implemented privilege mode lower than x.,CSR_controlled,enum,very_high,False, +chunk_ebedc1a9,src/priv/machine.adoc,272,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Privilege and Global Interrupt-Enable Stack in `mstatus` register","If privilege mode x is not implemented, then xPP must be read-only 0.",non_CSR_parameter,enum,very_high,False, +chunk_a7ea798a,src/priv/machine.adoc,278,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register","This non-reentrancy usually occurs in the early phase of trap handling, wherein the trap handler has not yet preserved the necessary state to handle and resume from the trap.",unknown,unknown,high,False, +chunk_e04aa34c,src/priv/machine.adoc,278,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register","The occurrence of a trap during this phase can lead to an overwrite of critical state information, resulting in the loss of data needed to recover from the initial trap.",unknown,unknown,high,False, +chunk_19960020,src/priv/machine.adoc,278,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register",The trap that caused this critical error condition is henceforth called the unexpected trap.,unknown,unknown,high,False, +chunk_02166ef0,src/priv/machine.adoc,278,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register","However, managing Hardware-Error exceptions, which may occur unpredictably, presents significant challenges in trap handler implementation due to the potential risk of a double trap.",non_CSR_parameter,enum,high,False, +chunk_d92018ea,src/priv/machine.adoc,292,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register",The M-mode-disable-trap (`MDT`) bit is a WARL field introduced by the Smdbltrp extension.,CSR_controlled,enum,very_high,False, +chunk_c600edad,src/priv/machine.adoc,292,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register","Upon reset, the `MDT` field is set to 1.",unknown,binary,high,False, +chunk_bc3a8d4d,src/priv/machine.adoc,292,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register","When the `MDT` bit is set to 1 by an explicit CSR write, the `MIE` (Machine Interrupt Enable) bit is cleared to 0.",CSR_controlled,binary,high,False, +chunk_4a445d7c,src/priv/machine.adoc,292,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register","For RV64, this clearing occurs regardless of the value written, if any, to the `MIE` bit by the same write.",CSR_controlled,enum,high,False, +chunk_03fcbbf7,src/priv/machine.adoc,292,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register","The `MIE` bit can only be set to 1 by an explicit CSR write if the `MDT` bit is already 0 or, for RV64, is being set to 0 by the same write (For RV32, the `MDT` bit is in `mstatush` and the `MIE` bit in `mstatus` register).",CSR_controlled,binary,high,False, +chunk_1a182aaa,src/priv/machine.adoc,302,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register","When a trap is to be taken into M-mode, if the `MDT` bit is currently 0, it is then set to 1, and the trap is delivered as expected.",unknown,binary,high,False, +chunk_1fecd47e,src/priv/machine.adoc,302,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register","However, if `MDT` is already set to 1, then this is an unexpected trap.",unknown,binary,high,False, +chunk_e020ed27,src/priv/machine.adoc,302,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register","When the Smrnmi extension is implemented, a trap caused by an RNMI is not considered an unexpected trap irrespective of the state of the `MDT` bit. A trap caused by an RNMI does not set the `MDT` bit.",unknown,unknown,high,False, +chunk_073212d6,src/priv/machine.adoc,302,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register","However, a trap that occurs when executing in M-mode with `mnstatus.NMIE` set to 0 is an unexpected trap.",CSR_controlled,binary,high,False, +chunk_b595cf2e,src/priv/machine.adoc,311,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register","In the event of a unexpected trap, the handling is as follows:",unknown,unknown,high,False, +chunk_6ba95d38,src/priv/machine.adoc,313,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register","When the Smrnmi extension is implemented and `mnstatus.NMIE` is 1, the hart traps to the RNMI handler.",CSR_controlled,enum,high,False, +chunk_184a4598,src/priv/machine.adoc,313,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register","To deliver this trap, the `mnepc` and `mncause` registers are written with the values that the unexpected trap would have written to the `mepc` and `mcause` registers respectively.",CSR_controlled,enum,high,False, +chunk_380d0cb2,src/priv/machine.adoc,313,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register",The privilege mode information fields in the `mnstatus` register are written to indicate M-mode and its `NMIE` field is set to 0.,CSR_controlled,binary,high,False, +chunk_b77fa1e6,src/priv/machine.adoc,320,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register","When the Smrnmi extension is not implemented, or if the Smrnmi extension is implemented and `mnstatus.NMIE` is 0, the hart enters a critical-error state without updating any architectural state, including the `pc`.",CSR_controlled,enum,high,False, +chunk_e460edb6,src/priv/machine.adoc,320,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register","This state involves ceasing execution, disabling all interrupts (including NMIs), and asserting a `critical-error` signal to the platform.",unknown,unknown,high,False, +chunk_e0437150,src/priv/machine.adoc,320,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register",Whether performance counters and timers are updated in the critical-error state is UNSPECIFIED.,non_CSR_parameter,unknown,high,False, +chunk_0247cb47,src/priv/machine.adoc,327,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register","When the Smdbltrp extension is implemented, executing an `MRET` instruction, or executing an `SRET` instruction while the current privilege mode is M, has the following additional effects.",unknown,enum,high,False, +chunk_8696b437,src/priv/machine.adoc,327,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register",The `MDT` bit is set to 0.,unknown,binary,high,False, +chunk_bf6ee958,src/priv/machine.adoc,327,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register","If the Ssdbltrp extension is also implemented, and the new privilege mode is U, VS, or VU, then `sstatus.SDT` is also set to 0.",CSR_controlled,binary,high,False, +chunk_d57a0235,src/priv/machine.adoc,327,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register","Additionally, if it is VU, then `vsstatus.SDT` is also set to 0.",CSR_controlled,binary,high,False, +chunk_b09dc8dd,src/priv/machine.adoc,334,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register","When the Smdbltrp extension is implemented, the `MNRET` instruction, provided by the Smrnmi extension, sets the `MDT` bit to 0 if the new privilege mode is not M.",unknown,enum,high,False, +chunk_8d52acae,src/priv/machine.adoc,334,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register","If the Ssdbltrp extension is also implemented, and the new privilege mode is U, VS, or VU, then `sstatus.SDT` is also set to 0.",CSR_controlled,binary,high,False, +chunk_47c7f685,src/priv/machine.adoc,334,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register","Additionally, if it is VU, then `vsstatus.SDT` is also set to 0.",CSR_controlled,binary,high,False, +chunk_a1b012e3,src/priv/machine.adoc,341,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Base ISA Control in `mstatus` Register","For RV64 harts, the SXL and UXL fields are *WARL* fields that control the value of XLEN for S-mode and U-mode, respectively.",CSR_controlled,enum,very_high,False, +chunk_3a138f63,src/priv/machine.adoc,341,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Base ISA Control in `mstatus` Register","The encoding of these fields is the same as the MXL field of `misa`, shown in .",unknown,enum,high,False, +chunk_ff6c63e4,src/priv/machine.adoc,341,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Base ISA Control in `mstatus` Register","The effective XLEN in S-mode and U-mode are termed SXLEN and UXLEN, respectively.",unknown,unknown,high,False, +chunk_946ccc8c,src/priv/machine.adoc,346,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Base ISA Control in `mstatus` Register","When MXLEN=32, the SXL and UXL fields do not exist, and SXLEN=32 and UXLEN=32.",unknown,enum,high,False, +chunk_eafe42d2,src/priv/machine.adoc,349,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Base ISA Control in `mstatus` Register","When MXLEN=64, if S-mode is not supported, then SXL is read-only zero.",unknown,binary,high,False, +chunk_baf0fbc7,src/priv/machine.adoc,349,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Base ISA Control in `mstatus` Register","Otherwise, it is a *WARL* field that encodes the current value of SXLEN.",CSR_controlled,enum,very_high,False, +chunk_9e5e553b,src/priv/machine.adoc,349,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Base ISA Control in `mstatus` Register","In particular, an implementation may make SXL be a read-only field whose value always ensures that SXLEN=MXLEN.",CSR_controlled,enum,high,False, +chunk_aec67cce,src/priv/machine.adoc,354,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Base ISA Control in `mstatus` Register","When MXLEN=64, if U-mode is not supported, then UXL is read-only zero.",unknown,binary,high,False, +chunk_3685ed6f,src/priv/machine.adoc,354,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Base ISA Control in `mstatus` Register","Otherwise, it is a *WARL* field that encodes the current value of UXLEN.",CSR_controlled,enum,very_high,False, +chunk_2cf32d37,src/priv/machine.adoc,354,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Base ISA Control in `mstatus` Register","In particular, an implementation may make UXL be a read-only field whose value always ensures that UXLEN=MXLEN or UXLEN=SXLEN.",CSR_controlled,enum,high,False, +chunk_e129cc9c,src/priv/machine.adoc,359,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Base ISA Control in `mstatus` Register","If S-mode is implemented, the set of legal values that the UXL field may assume excludes those that would cause UXLEN to be greater than SXLEN.",non_CSR_parameter,range,high,False, +chunk_4d4a9656,src/priv/machine.adoc,363,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Base ISA Control in `mstatus` Register","Whenever XLEN in any mode is set to a value less than the widest supported XLEN, all operations must ignore source operand register bits above the configured XLEN, and must sign-extend results to fill the entire widest supported XLEN in the destination register.",non_CSR_parameter,range,very_high,False, +chunk_c78bec76,src/priv/machine.adoc,363,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Base ISA Control in `mstatus` Register","Similarly, `pc` bits above XLEN are ignored, and when the `pc` is written, it is sign-extended to fill the widest supported XLEN.",unknown,enum,high,False, +chunk_e2d7e143,src/priv/machine.adoc,371,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Base ISA Control in `mstatus` Register","When such a HINT is executed with XLEN < MXLEN and bits MXLEN..XLEN of the destination register not all equal to bit XLEN-1, it is implementation-defined whether bits MXLEN..XLEN of the destination register are unchanged or are overwritten with copies of bit XLEN-1.",non_CSR_parameter,range,high,False, +chunk_48ebcb18,src/priv/machine.adoc,380,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Base ISA Control in `mstatus` Register",The implementation choice is observable only by privilege modes with an XLEN setting greater than the current XLEN; it is invisible to the current privilege mode.,unknown,range,high,False, +chunk_6d2d35a6,src/priv/machine.adoc,390,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Memory Privilege in `mstatus` Register","When MPRV=0, explicit memory accesses behave as normal, using the translation and protection mechanisms of the current privilege mode.",unknown,enum,high,False, +chunk_62353e79,src/priv/machine.adoc,390,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Memory Privilege in `mstatus` Register","When MPRV=1, load and store memory addresses are translated and protected, and endianness is applied, as though the current privilege mode were set to MPP.",unknown,enum,high,False, +chunk_9d60b6e8,src/priv/machine.adoc,390,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Memory Privilege in `mstatus` Register",Instruction address-translation and protection are unaffected by the setting of MPRV. MPRV is read-only 0 if U-mode is not supported.,unknown,unknown,high,False, +chunk_cfc2ea64,src/priv/machine.adoc,401,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Memory Privilege in `mstatus` Register",An MRET or SRET instruction that changes the privilege mode to a mode less privileged than M also sets MPRV=0.,unknown,enum,high,False, +chunk_34d3623c,src/priv/machine.adoc,404,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Memory Privilege in `mstatus` Register",The MXR (Make eXecutable Readable) bit modifies the privilege with which loads access virtual memory.,unknown,unknown,high,False, +chunk_71fc36af,src/priv/machine.adoc,404,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Memory Privilege in `mstatus` Register","When MXR=0, only loads from pages marked readable (R=1 in ) will succeed.",unknown,unknown,high,False, +chunk_fb6571cf,src/priv/machine.adoc,404,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Memory Privilege in `mstatus` Register","When MXR=1, loads from pages marked either readable or executable (R=1 or X=1) will succeed. MXR has no effect when page-based virtual memory is not in effect. MXR is read-only 0 if S-mode is not supported.",unknown,enum,high,False, +chunk_f63b2089,src/priv/machine.adoc,410,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Memory Privilege in `mstatus` Register",The SUM (permit Supervisor User Memory access) bit modifies the privilege with which S-mode loads and stores access virtual memory.,unknown,unknown,high,False, +chunk_9065dcbb,src/priv/machine.adoc,410,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Memory Privilege in `mstatus` Register","When SUM=0, S-mode memory accesses to pages that are accessible by U-mode (U=1 in ) will fault.",unknown,unknown,high,False, +chunk_72e75926,src/priv/machine.adoc,410,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Memory Privilege in `mstatus` Register","When SUM=1, these accesses are permitted. SUM has no effect when page-based virtual memory is not in effect.",unknown,unknown,high,False, +chunk_7d4c7b1c,src/priv/machine.adoc,419,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Memory Privilege in `mstatus` Register",The MXR and SUM mechanisms only affect the interpretation of permissions encoded in page-table entries.,unknown,enum,high,False, +chunk_f93d3c8d,src/priv/machine.adoc,419,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Memory Privilege in `mstatus` Register","In particular, they have no impact on whether access-fault exceptions are raised due to PMAs or PMP.",non_CSR_parameter,unknown,high,False, +chunk_e2d37e88,src/priv/machine.adoc,426,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Endianness Control in `mstatus` and `mstatush` Registers","The MBE, SBE, and UBE bits in `mstatus` and `mstatush` are *WARL* fields that control the endianness of memory accesses other than instruction fetches.",CSR_controlled,enum,very_high,False, +chunk_6ead09ae,src/priv/machine.adoc,426,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Endianness Control in `mstatus` and `mstatush` Registers",Instruction fetches are always little-endian.,unknown,unknown,high,False, +chunk_14c469a4,src/priv/machine.adoc,430,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Endianness Control in `mstatus` and `mstatush` Registers",MBE controls whether non-instruction-fetch memory accesses made from M-mode (assuming `mstatus`.MPRV=0) are little-endian (MBE=0) or big-endian (MBE=1).,CSR_controlled,enum,high,False, +chunk_d40c9bce,src/priv/machine.adoc,435,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Endianness Control in `mstatus` and `mstatush` Registers","If S-mode is not supported, SBE is read-only 0.",unknown,unknown,high,False, +chunk_1544547e,src/priv/machine.adoc,435,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Endianness Control in `mstatus` and `mstatush` Registers","Otherwise, SBE controls whether explicit load and store memory accesses made from S-mode are little-endian (SBE=0) or big-endian (SBE=1).",non_CSR_parameter,unknown,high,False, +chunk_abc95956,src/priv/machine.adoc,440,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Endianness Control in `mstatus` and `mstatush` Registers","If U-mode is not supported, UBE is read-only 0.",unknown,unknown,high,False, +chunk_f7bd115a,src/priv/machine.adoc,440,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Endianness Control in `mstatus` and `mstatush` Registers","Otherwise, UBE controls whether explicit load and store memory accesses made from U-mode are little-endian (UBE=0) or big-endian (UBE=1).",non_CSR_parameter,unknown,high,False, +chunk_c3daa802,src/priv/machine.adoc,445,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Endianness Control in `mstatus` and `mstatush` Registers","For implicit accesses to supervisor-level memory management data structures, such as page tables, endianness is always controlled by SBE.",unknown,unknown,high,False, +chunk_78a11b95,src/priv/machine.adoc,445,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Endianness Control in `mstatus` and `mstatush` Registers","Since changing SBE alters the implementation’s interpretation of these data structures, if any such data structures remain in use across a change to SBE, M-mode software must follow such a change to SBE by executing an SFENCE.VMA instruction with rs1=`x0` and rs2=`x0`.",SW_rule,binary,very_high,False, +chunk_9106cc6f,src/priv/machine.adoc,452,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Endianness Control in `mstatus` and `mstatush` Registers","If S-mode is supported, an implementation may make SBE be a read-only copy of MBE.",non_CSR_parameter,enum,high,False, +chunk_ffd4982b,src/priv/machine.adoc,452,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Endianness Control in `mstatus` and `mstatush` Registers","If U-mode is supported, an implementation may make UBE be a read-only copy of either MBE or SBE.",non_CSR_parameter,enum,high,False, +chunk_47aebbd0,src/priv/machine.adoc,460,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Virtualization Support in `mstatus` Register",The TVM (Trap Virtual Memory) bit is a *WARL* field that supports intercepting supervisor virtual-memory management operations.,CSR_controlled,enum,very_high,False, +chunk_c5327415,src/priv/machine.adoc,460,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Virtualization Support in `mstatus` Register","When TVM=1, attempts to read or write the `satp` CSR or execute an SFENCE.VMA or SINVAL.VMA instruction while executing in S-mode will raise an illegal-instruction exception.",CSR_controlled,enum,high,False, +chunk_9dee9a7c,src/priv/machine.adoc,460,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Virtualization Support in `mstatus` Register","When TVM=0, these operations are permitted in S-mode. TVM is read-only 0 when S-mode is not supported.",unknown,unknown,high,False, +chunk_50316df6,src/priv/machine.adoc,468,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Virtualization Support in `mstatus` Register","When TW=0, the WFI instruction may execute in modes less privileged than M when not prevented for some other reason.",non_CSR_parameter,enum,high,False, +chunk_fc1a5149,src/priv/machine.adoc,468,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Virtualization Support in `mstatus` Register","When TW=1, then if WFI is executed in any less-privileged mode, and it does not complete within an implementation-specific, bounded time limit, the WFI instruction causes an illegal-instruction exception.",non_CSR_parameter,unknown,high,False, +chunk_cad1ac2e,src/priv/machine.adoc,468,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Virtualization Support in `mstatus` Register","An implementation may have WFI always raise an illegal-instruction exception in modes less privileged than M when TW=1, even if there are pending globally-disabled interrupts when the instruction is executed. TW is read-only 0 when there are no modes less privileged than M.",non_CSR_parameter,binary,high,False, +chunk_351767e6,src/priv/machine.adoc,482,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Virtualization Support in `mstatus` Register","When S-mode is implemented, then executing WFI in U-mode causes an illegal-instruction exception, regardless of the value of the TW bit, unless the instruction completes within an implementation-specific, bounded time limit.",non_CSR_parameter,enum,high,False, +chunk_61926087,src/priv/machine.adoc,486,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Virtualization Support in `mstatus` Register","The TSR (Trap SRET) bit is a *WARL* field that supports intercepting the supervisor exception return instruction, SRET.",CSR_controlled,enum,very_high,False, +chunk_fc7dcdf1,src/priv/machine.adoc,486,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Virtualization Support in `mstatus` Register","When TSR=1, attempts to execute SRET while executing in S-mode will raise an illegal-instruction exception.",non_CSR_parameter,unknown,high,False, +chunk_10ffba0c,src/priv/machine.adoc,486,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Virtualization Support in `mstatus` Register","When TSR=0, this operation is permitted in S-mode. TSR is read-only 0 when S-mode is not supported.",unknown,unknown,high,False, +chunk_100bf3d9,src/priv/machine.adoc,495,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register","Supporting substantial extensions is one of the primary goals of RISC-V, and hence we define a standard interface to allow unchanged privileged-mode code, particularly a supervisor-level OS, to support arbitrary user-mode state extensions.",unknown,enum,high,False, +chunk_a17aa295,src/priv/machine.adoc,500,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register",The FS[1:0] and VS[1:0] *WARL* fields and the XS[1:0] read-only field are used to reduce the cost of context save and restore by setting and tracking the current state of the floating-point unit and any other user-mode extensions respectively.,CSR_controlled,enum,very_high,False, +chunk_d23c4559,src/priv/machine.adoc,500,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register","The FS field encodes the status of the floating-point unit state, including the floating-point registers `f0`–`f31` and the CSRs `fcsr`, `frm`, and `fflags`.",CSR_controlled,enum,high,False, +chunk_cfa4f4cd,src/priv/machine.adoc,500,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register","The VS field encodes the status of the vector extension state, including the vector registers `v0`–`v31` and the CSRs `vcsr`, `vxrm`, `vxsat`, `vstart`, `vl`, `vtype`, and `vlenb`.",CSR_controlled,enum,high,False, +chunk_989c0a49,src/priv/machine.adoc,500,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register",The XS field encodes the status of additional user-mode extensions and associated state.,unknown,enum,high,False, +chunk_d6c57a2e,src/priv/machine.adoc,500,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register",These fields can be checked by a context switch routine to quickly determine whether a state save or restore is required.,unknown,enum,high,False, +chunk_2a6076a9,src/priv/machine.adoc,519,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register","The FS, VS, and XS fields use the same status encoding as shown in , with the four possible status values being Off, Initial, Clean, and Dirty.",unknown,enum,high,False, +chunk_0684048e,src/priv/machine.adoc,542,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register","If the F extension is implemented, the FS field shall not be read-only zero.",CSR_controlled,binary,very_high,False, +chunk_e1e1eb9f,src/priv/machine.adoc,545,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register","If neither the F extension nor S-mode is implemented, then FS is read-only zero.",unknown,binary,high,False, +chunk_72bdee1e,src/priv/machine.adoc,545,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register","If S-mode is implemented but the F extension is not, FS may optionally be read-only zero.",non_CSR_parameter,binary,high,False, +chunk_c66ba3f4,src/priv/machine.adoc,549,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register","If the `v` registers are implemented, the VS field shall not be read-only zero.",CSR_controlled,binary,very_high,False, +chunk_9af5df91,src/priv/machine.adoc,552,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register","If neither the `v` registers nor S-mode is implemented, then VS is read-only zero.",unknown,binary,high,False, +chunk_5060ccc5,src/priv/machine.adoc,552,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register","If S-mode is implemented but the `v` registers are not, VS may optionally be read-only zero.",non_CSR_parameter,binary,high,False, +chunk_719bff2a,src/priv/machine.adoc,557,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register","In harts without additional user extensions requiring new state, the XS field is read-only zero.",CSR_controlled,binary,high,False, +chunk_3dd742ab,src/priv/machine.adoc,557,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register",Every additional extension with state provides a CSR field that encodes the equivalent of the XS states.,CSR_controlled,enum,high,False, +chunk_d467dc7b,src/priv/machine.adoc,557,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register",The XS field represents a summary of all extensions' status as shown in .,unknown,enum,high,False, +chunk_62d171a7,src/priv/machine.adoc,564,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register","The SD bit is a read-only bit that summarizes whether either the FS, VS, or XS fields signal the presence of some dirty state that will require saving extended user context to memory.",CSR_controlled,enum,high,False, +chunk_b0d2a550,src/priv/machine.adoc,564,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register","If FS, XS, and VS are all read-only zero, then SD is also always zero.",unknown,binary,high,False, +chunk_6f32dc69,src/priv/machine.adoc,570,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register","When an extension's status is set to Off, any instruction that attempts to read or write the corresponding state will cause an illegal-instruction exception.",non_CSR_parameter,unknown,high,False, +chunk_c03874a5,src/priv/machine.adoc,570,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register","When the status is Initial, the corresponding state should have an initial constant value.",non_CSR_parameter,enum,high,False, +chunk_52848716,src/priv/machine.adoc,570,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register","When the status is Clean, the corresponding state is potentially different from the initial value, but matches the last value stored on a context swap.",unknown,unknown,high,False, +chunk_b892e66b,src/priv/machine.adoc,570,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register","When the status is Dirty, the corresponding state has potentially been modified since the last context save.",unknown,unknown,high,False, +chunk_a8626944,src/priv/machine.adoc,581,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register","During a context save, the responsible privileged code need only write out the corresponding state if its status is Dirty, and can then reset the extension's status to Clean.",unknown,unknown,high,False, +chunk_d3cc2786,src/priv/machine.adoc,581,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register","During a context restore, the context need only be loaded from memory if the status is Clean (it should never be Dirty at restore).",non_CSR_parameter,enum,high,False, +chunk_d140aeec,src/priv/machine.adoc,581,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register","If the status is Initial, the context must be set to an initial constant value on context restore to avoid a security hole, but this can be done without accessing memory.",non_CSR_parameter,binary,very_high,False, +chunk_0129e0ad,src/priv/machine.adoc,591,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register",The FS and XS fields are read by the privileged code before saving the context.,unknown,enum,high,False, +chunk_588da1df,src/priv/machine.adoc,591,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register","The FS field is set directly by privileged code when resuming a user context, while the XS field is set indirectly by writing to the status register of the individual extensions.",unknown,enum,high,False, +chunk_2f74b83c,src/priv/machine.adoc,591,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register","The status fields will also be updated during execution of instructions, regardless of privilege mode.",unknown,enum,high,False, +chunk_b0b87ad3,src/priv/machine.adoc,598,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register","Extensions to the user-mode ISA often include additional user-mode state, and this state can be considerably larger than the base integer registers.",unknown,unknown,high,False, +chunk_436175c7,src/priv/machine.adoc,598,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register","The extensions might only be used for some applications, or might only be needed for short phases within a single application.",unknown,unknown,high,False, +chunk_e56b6a0c,src/priv/machine.adoc,598,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register","To improve performance, the user-mode extension can define additional instructions to allow user-mode software to return the unit to an initial state or even to turn off the unit.",SW_rule,unknown,high,False, +chunk_f3636b32,src/priv/machine.adoc,606,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register",The unconfigured state would be represented as the Initial state for context save.,unknown,unknown,high,False, +chunk_b7653af0,src/priv/machine.adoc,616,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register","Executing a user-mode instruction to disable a unit and place it into the Off state will cause an illegal-instruction exception to be raised if any subsequent instruction tries to use the unit before it is turned back on. A user-mode instruction to turn a unit on must also ensure the unit's state is properly initialized, as the unit might have been used by another context meantime.",non_CSR_parameter,binary,very_high,False, +chunk_fa9dc3be,src/priv/machine.adoc,623,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register",Changing the setting of FS has no effect on the contents of the floating-point register state.,unknown,unknown,high,False, +chunk_1d9af2f0,src/priv/machine.adoc,623,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register","In particular, setting FS=Off does not destroy the state, nor does setting FS=Initial clear the contents.",unknown,unknown,high,False, +chunk_ffc61c8e,src/priv/machine.adoc,623,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register","Similarly, the setting of VS has no effect on the contents of the vector register state.",unknown,unknown,high,False, +chunk_1b88bbce,src/priv/machine.adoc,623,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register","Other extensions, however, might not preserve state when set to Off.",unknown,unknown,high,False, +chunk_8a97197e,src/priv/machine.adoc,630,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register",Implementations may choose to track the dirtiness of the floating-point register state imprecisely by reporting the state to be dirty even when it has not been modified.,non_CSR_parameter,enum,high,False, +chunk_6afc95af,src/priv/machine.adoc,630,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register","On some implementations, some instructions that do not mutate the floating-point state may cause the state to transition from Initial or Clean to Dirty.",non_CSR_parameter,enum,high,False, +chunk_d692b836,src/priv/machine.adoc,630,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register","On other implementations, dirtiness might not be tracked at all, in which case the valid FS states are Off and Dirty, and an attempt to set FS to Initial or Clean causes it to be set to Dirty.",unknown,unknown,high,False, +chunk_966e351f,src/priv/machine.adoc,641,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register","If an instruction explicitly or implicitly writes a floating-point register or the `fcsr` but does not alter its contents, and FS=Initial or FS=Clean, it is implementation-defined whether FS transitions to Dirty.",CSR_controlled,enum,high,False, +chunk_4fee64ca,src/priv/machine.adoc,646,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register","Implementations may choose to track the dirtiness of the vector register state in an analogous imprecise fashion, including possibly setting VS to Dirty when software attempts to set VS=Initial or VS=Clean.",SW_rule,enum,high,False, +chunk_6177f235,src/priv/machine.adoc,646,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register","When VS=Initial or VS=Clean, it is implementation-defined whether an instruction that writes a vector register or vector CSR but does not alter its contents causes VS to transition to Dirty.",CSR_controlled,enum,high,False, +chunk_440c0271,src/priv/machine.adoc,653,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register","shows all the possible state transitions for the FS, VS, or XS status bits.",unknown,unknown,high,False, +chunk_c937eee4,src/priv/machine.adoc,668,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register","[width=75,align=center,float=center,cols=""<,<,<,<,<""] | 5+^|At context save in privileged code",unknown,unknown,high,False, +chunk_dac566d1,src/priv/machine.adoc,672,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register",|Save state? + Next state |No + Off |No + Initial |No + Clean |Yes + Clean |,unknown,unknown,high,False, +chunk_5397685e,src/priv/machine.adoc,684,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register","[width=75,align=center,float=center,cols=""<,<,<,<,<""] | 5+^|At context restore in privileged code",unknown,unknown,high,False, +chunk_9f4e4282,src/priv/machine.adoc,688,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register","|Restore state? + Next state |No + Off |Yes, to initial + Initial |Yes, from memory + Clean |N/A + N/A |",unknown,unknown,high,False, +chunk_ec8ecfa4,src/priv/machine.adoc,700,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register","[width=75,align=center,float=center,cols=""<,<,<,<,<""] | 5+^|Execute instruction to read state",unknown,unknown,high,False, +chunk_917169fc,src/priv/machine.adoc,704,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register",|Action? + Next state |Exception + Off |Execute + Initial |Execute + Clean |Execute + Dirty |,unknown,unknown,high,False, +chunk_1ab2ddac,src/priv/machine.adoc,716,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register","[width=75,align=center,float=center,cols=""<,<,<,<,<""] | 5+^|Execute instruction that possibly modifies state, including configuration",unknown,unknown,high,False, +chunk_ad0876b7,src/priv/machine.adoc,720,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register",|Action? + Next state |Exception + Off |Execute + Dirty |Execute + Dirty |Execute + Dirty |,unknown,unknown,high,False, +chunk_bfb06166,src/priv/machine.adoc,732,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register","[width=75,align=center,float=center,cols=""<,<,<,<,<""] | 5+^|Execute instruction to unconfigure unit",unknown,unknown,high,False, +chunk_1cd88952,src/priv/machine.adoc,736,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register",|Action? + Next state |Exception + Off |Execute + Initial |Execute + Initial |Execute + Initial |,unknown,unknown,high,False, +chunk_3cafd6f1,src/priv/machine.adoc,748,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register","[width=75,align=center,float=center,cols=""<,<,<,<,<""] | 5+^|Execute instruction to disable unit",unknown,unknown,high,False, +chunk_289f8f4c,src/priv/machine.adoc,752,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register",|Action? + Next state |Execute + Off |Execute + Off |Execute + Off |Execute + Off |,unknown,unknown,high,False, +chunk_4172ff3d,src/priv/machine.adoc,764,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register","[width=75,align=center,float=center,cols=""<,<,<,<,<""] | 5+^|Execute instruction to enable unit",unknown,unknown,high,False, +chunk_e7d34a1b,src/priv/machine.adoc,768,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register",|Action? + Next state |Execute + Initial |Execute + Initial |Execute + Initial |Execute + Initial |,unknown,unknown,high,False, +chunk_e89be2e8,src/priv/machine.adoc,780,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register","Standard privileged instructions to initialize, save, and restore extension state are provided to insulate privileged code from details of the added extension state by treating the state as an opaque object.",unknown,unknown,high,False, +chunk_8f7b962b,src/priv/machine.adoc,784,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register","The XS field provides a summary of all added extension state, but additional microarchitectural bits might be maintained in the extension to further reduce context save and restore overhead.",unknown,enum,high,False, +chunk_5beffcc5,src/priv/machine.adoc,793,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register","The floating-point unit state is always initialized, saved, and restored using standard instructions (F, D, and/or Q), and privileged code must be aware of FLEN to determine the appropriate space to reserve for each `f` register.",non_CSR_parameter,enum,very_high,False, +chunk_e7897050,src/priv/machine.adoc,798,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register","Machine and Supervisor modes share a single copy of the FS, VS, and XS bits.",unknown,unknown,high,False, +chunk_a213a100,src/priv/machine.adoc,798,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register","Supervisor-level software normally uses the FS, VS, and XS bits directly to record the status with respect to the supervisor-level saved context.",SW_rule,unknown,high,False, +chunk_e951506a,src/priv/machine.adoc,798,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register",Machine-level software must be more conservative in saving and restoring the extension state in their corresponding version of the context.,SW_rule,enum,very_high,False, +chunk_73c2549a,src/priv/machine.adoc,807,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Previous Expected Landing Pad (ELP) State in `mstatus` Register","The Zicfilp extension adds the `SPELP` and `MPELP` fields that hold the previous `ELP`, and are updated as specified in .",unknown,enum,high,False, +chunk_568f2c06,src/priv/machine.adoc,807,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Previous Expected Landing Pad (ELP) State in `mstatus` Register",The *x*`PELP` fields are encoded as follows:,unknown,enum,high,False, +chunk_ea60f834,src/priv/machine.adoc,817,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap-Vector Base-Address (`mtvec`) Register","The `mtvec` register is an MXLEN-bit *WARL* read/write register that holds trap vector configuration, consisting of a vector base address (BASE) and a vector mode (MODE).",CSR_controlled,range,very_high,False, +chunk_f047c73f,src/priv/machine.adoc,825,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap-Vector Base-Address (`mtvec`) Register","The `mtvec` register must always be implemented, but can contain a read-only value.",CSR_controlled,enum,very_high,False, +chunk_05da97e7,src/priv/machine.adoc,825,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap-Vector Base-Address (`mtvec`) Register","If `mtvec` is writable, the set of values the register may hold can vary by implementation.",CSR_controlled,enum,high,False, +chunk_7f24c6fc,src/priv/machine.adoc,825,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap-Vector Base-Address (`mtvec`) Register","The value in the BASE field must always be aligned on a 4-byte boundary, and the MODE setting may impose additional alignment constraints on the value in the BASE field.",non_CSR_parameter,range,very_high,False, +chunk_b5c6215c,src/priv/machine.adoc,825,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap-Vector Base-Address (`mtvec`) Register","When used as an address, the lower two bits are filled with zeroes to obtain an XLEN-bit address that is always aligned on a 4-byte boundary.",non_CSR_parameter,range,high,False, +chunk_ee78fe45,src/priv/machine.adoc,853,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap-Vector Base-Address (`mtvec`) Register",The encoding of the MODE field is shown in .,unknown,enum,high,False, +chunk_f847aa6a,src/priv/machine.adoc,853,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap-Vector Base-Address (`mtvec`) Register","When MODE=Direct, all traps into machine mode cause the `pc` to be set to the address in the BASE field.",unknown,enum,high,False, +chunk_043f6209,src/priv/machine.adoc,853,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap-Vector Base-Address (`mtvec`) Register","When MODE=Vectored, all synchronous exceptions into machine mode cause the `pc` to be set to the address in the BASE field, whereas interrupts cause the `pc` to be set to the address in the BASE field plus four times the interrupt cause number.",unknown,enum,high,False, +chunk_0997ae61,src/priv/machine.adoc,862,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap-Vector Base-Address (`mtvec`) Register",An implementation may have different alignment constraints for different modes.,non_CSR_parameter,enum,high,False, +chunk_5614962a,src/priv/machine.adoc,862,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap-Vector Base-Address (`mtvec`) Register","In particular, MODE=Vectored may have stricter alignment constraints than MODE=Direct.",non_CSR_parameter,enum,high,False, +chunk_44f96bcf,src/priv/machine.adoc,868,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Delegation (`medeleg` and `mideleg`) Registers","By default, all traps at any privilege level are handled in machine mode, though a machine-mode handler can redirect traps back to the appropriate level with the MRET instruction ().",unknown,enum,high,False, +chunk_fdebccfe,src/priv/machine.adoc,868,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Delegation (`medeleg` and `mideleg`) Registers","To increase performance, implementations can provide individual read/write bits within `medeleg` and `mideleg` to indicate that certain exceptions and interrupts should be processed directly by a lower privilege level.",CSR_controlled,enum,high,False, +chunk_6b83fe4a,src/priv/machine.adoc,868,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Delegation (`medeleg` and `mideleg`) Registers",The machine exception delegation register (`medeleg`) is a 64-bit read/write register.,CSR_controlled,range,high,False, +chunk_2a87bcf3,src/priv/machine.adoc,868,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Delegation (`medeleg` and `mideleg`) Registers",The machine interrupt delegation (`mideleg`) register is an MXLEN-bit read/write register.,CSR_controlled,range,high,False, +chunk_18ad37ff,src/priv/machine.adoc,878,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Delegation (`medeleg` and `mideleg`) Registers","In harts with S-mode, the `medeleg` and `mideleg` registers must exist, and setting a bit in `medeleg` or `mideleg` will delegate the corresponding trap, when occurring in S-mode or U-mode, to the S-mode trap handler.",CSR_controlled,enum,very_high,False, +chunk_5f254348,src/priv/machine.adoc,878,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Delegation (`medeleg` and `mideleg`) Registers","In harts without S-mode, the `medeleg` and `mideleg` registers should not exist.",CSR_controlled,enum,high,False, +chunk_6c8748bf,src/priv/machine.adoc,884,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Delegation (`medeleg` and `mideleg`) Registers","When a trap is delegated to S-mode, the `scause` register is written with the trap cause; the `sepc` register is written with the virtual address of the instruction that took the trap; the `stval` register is written with an exception-specific datum; the SPP field of `mstatus` is written with the active privilege mode at the time of the trap; the SPIE field of `mstatus` is written with the value of the SIE field at the time of the trap; and the SIE field of `mstatus` is cleared.",CSR_controlled,enum,high,False, +chunk_149fb50f,src/priv/machine.adoc,884,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Delegation (`medeleg` and `mideleg`) Registers","The `mcause`, `mepc`, and `mtval` registers and the MPP and MPIE fields of `mstatus` are not written.",CSR_controlled,enum,high,False, +chunk_20b10e8f,src/priv/machine.adoc,895,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Delegation (`medeleg` and `mideleg`) Registers","An implementation can choose to subset the delegatable traps, with the supported delegatable bits found by writing one to every bit location, then reading back the value in `medeleg` or `mideleg` to see which bit positions hold a one.",CSR_controlled,enum,high,False, +chunk_7a6ffcef,src/priv/machine.adoc,900,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Delegation (`medeleg` and `mideleg`) Registers","An implementation shall not have any bits of `medeleg` be read-only one, i.e., any synchronous trap that can be delegated must support not being delegated.",CSR_controlled,enum,very_high,False, +chunk_022eb3c5,src/priv/machine.adoc,900,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Delegation (`medeleg` and `mideleg`) Registers","Similarly, an implementation shall not fix as read-only one any bits of `mideleg` corresponding to machine-level interrupts (but may do so for lower-level interrupts).",CSR_controlled,enum,very_high,False, +chunk_27edf377,src/priv/machine.adoc,907,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Delegation (`medeleg` and `mideleg`) Registers",Traps never transition from a more-privileged mode to a less-privileged mode.,unknown,unknown,high,False, +chunk_45e80975,src/priv/machine.adoc,907,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Delegation (`medeleg` and `mideleg`) Registers","By contrast, traps may be taken horizontally.",non_CSR_parameter,enum,high,False, +chunk_debc397f,src/priv/machine.adoc,907,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Delegation (`medeleg` and `mideleg`) Registers","Using the same example, if M-mode has delegated illegal-instruction exceptions to S-mode, and S-mode software later executes an illegal instruction, the trap is taken in S-mode.",SW_rule,unknown,high,False, +chunk_bc1cf57d,src/priv/machine.adoc,916,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Delegation (`medeleg` and `mideleg`) Registers",Delegated interrupts result in the interrupt being masked at the delegator privilege level.,unknown,enum,high,False, +chunk_13ce9b57,src/priv/machine.adoc,916,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Delegation (`medeleg` and `mideleg`) Registers","By contrast, if `mideleg`[5] is clear, STIs can be taken in any mode and regardless of current mode will transfer control to M-mode.",CSR_controlled,enum,high,False, +chunk_62276a87,src/priv/machine.adoc,933,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Delegation (`medeleg` and `mideleg`) Registers","When XLEN=32, `medelegh` is a 32-bit read/write register that aliases bits 63:32 of `medeleg`.",CSR_controlled,range,high,False, +chunk_5fd8225e,src/priv/machine.adoc,933,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Delegation (`medeleg` and `mideleg`) Registers",The `medelegh` register does not exist when XLEN=64.,CSR_controlled,enum,high,False, +chunk_75711217,src/priv/machine.adoc,945,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Delegation (`medeleg` and `mideleg`) Registers","For exceptions that cannot occur in less privileged modes, the corresponding `medeleg` bits should be read-only zero.",CSR_controlled,binary,high,False, +chunk_0d125a7d,src/priv/machine.adoc,945,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Delegation (`medeleg` and `mideleg`) Registers","In particular, `medeleg`[11] is read-only zero.",CSR_controlled,binary,high,False, +chunk_cde33edf,src/priv/machine.adoc,949,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Delegation (`medeleg` and `mideleg`) Registers",The `medeleg`[16] is read-only zero as double trap is not delegatable.,CSR_controlled,binary,high,False, +chunk_afc7a9e4,src/priv/machine.adoc,953,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers","The `mip` register is an MXLEN-bit read/write register containing information on pending interrupts, while `mie` is the corresponding MXLEN-bit read/write register containing interrupt enable bits.",CSR_controlled,range,high,False, +chunk_8f4d107b,src/priv/machine.adoc,953,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers","Interrupt cause number i (as reported in CSR `mcause`, ) corresponds with bit i in both `mip` and `mie`.",CSR_controlled,enum,high,False, +chunk_ad33922a,src/priv/machine.adoc,953,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers","Bits 15:0 are allocated to standard interrupt causes only, while bits 16 and above are designated for platform use.",unknown,unknown,high,False, +chunk_aabb9955,src/priv/machine.adoc,972,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers","An interrupt i will trap to M-mode (causing the privilege mode to change to M-mode) if all of the following are true: (a) either the current privilege mode is M and the MIE bit in the `mstatus` register is set, or the current privilege mode has less privilege than M-mode; (b) bit i is set in both `mip` and `mie`; and (c) if register `mideleg` exists, bit i is not set in `mideleg`.",CSR_controlled,enum,high,False, +chunk_c2e1138f,src/priv/machine.adoc,979,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers","These conditions for an interrupt trap to occur must be evaluated in a bounded amount of time from when an interrupt becomes, or ceases to be, pending in `mip`, and must also be evaluated immediately following the execution of an xRET instruction or an explicit write to a CSR on which these interrupt trap conditions expressly depend (including `mip`, `mie`, `mstatus`, and `mideleg`).",CSR_controlled,enum,very_high,False, +chunk_bb4ee897,src/priv/machine.adoc,986,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers",Interrupts to M-mode take priority over any interrupts to lower privilege modes.,unknown,enum,high,False, +chunk_73a69f90,src/priv/machine.adoc,989,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers",Each individual bit in register `mip` may be writable or may be read-only.,CSR_controlled,enum,high,False, +chunk_99271441,src/priv/machine.adoc,989,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers","When bit i in `mip` is writable, a pending interrupt i can be cleared by writing 0 to this bit.",CSR_controlled,enum,high,False, +chunk_bf4e1876,src/priv/machine.adoc,989,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers","If interrupt i can become pending but bit i in `mip` is read-only, the implementation must provide some other mechanism for clearing the pending interrupt.",CSR_controlled,enum,very_high,False, +chunk_4645bc7f,src/priv/machine.adoc,995,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers",A bit in `mie` must be writable if the corresponding interrupt can ever become pending.,CSR_controlled,enum,very_high,False, +chunk_a317f98e,src/priv/machine.adoc,995,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers",Bits of `mie` that are not writable must be read-only zero.,CSR_controlled,binary,very_high,False, +chunk_665e5c10,src/priv/machine.adoc,998,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers",The standard portions (bits 15:0) of the `mip` and `mie` registers are formatted as shown in and respectively.,CSR_controlled,enum,high,False, +chunk_b9a51f08,src/priv/machine.adoc,1009,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers","Bits `mip`.MEIP and `mie`.MEIE are the interrupt-pending and interrupt-enable bits for machine-level external interrupts. MEIP is read-only in `mip`, and is set and cleared by a platform-specific interrupt controller.",CSR_controlled,enum,high,False, +chunk_5c0af0c2,src/priv/machine.adoc,1014,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers","Bits `mip`.MTIP and `mie`.MTIE are the interrupt-pending and interrupt-enable bits for machine timer interrupts. MTIP is read-only in the `mip` register, and is cleared by writing to the memory-mapped machine-mode timer compare register.",CSR_controlled,enum,high,False, +chunk_7d31576a,src/priv/machine.adoc,1019,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers","Bits `mip`.MSIP and `mie`.MSIE are the interrupt-pending and interrupt-enable bits for machine-level software interrupts. MSIP is read-only in `mip`, and is written by accesses to memory-mapped control registers, which are used to provide machine-level interprocessor interrupts.",CSR_controlled,enum,high,False, +chunk_acaae705,src/priv/machine.adoc,1024,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers","A hart's memory-mapped `msip` register is a 32-bit read/write register, where bits 31--1 read as zero and bit 0 contains the MSIP bit.",CSR_controlled,range,high,False, +chunk_2720da7b,src/priv/machine.adoc,1024,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers","When the memory-mapped `msip` register changes, it is guaranteed to be reflected in `mip`.MSIP eventually, but not necessarily immediately.",CSR_controlled,enum,high,False, +chunk_052e4f52,src/priv/machine.adoc,1024,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers","If a system has only one hart, or if a platform standard supports the delivery of machine-level interprocessor interrupts through external interrupts (MEI) instead, then `mip`.MSIP and `mie`.MSIE may both be read-only zeros.",CSR_controlled,binary,high,False, +chunk_02c683bf,src/priv/machine.adoc,1033,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers","If supervisor mode is not implemented, bits SEIP, STIP, and SSIP of `mip` and SEIE, STIE, and SSIE of `mie` are read-only zeros.",CSR_controlled,binary,high,False, +chunk_de20dc96,src/priv/machine.adoc,1036,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers","If supervisor mode is implemented, bits `mip`.SEIP and `mie`.SEIE are the interrupt-pending and interrupt-enable bits for supervisor-level external interrupts. SEIP is writable in `mip`, and may be written by M-mode software to indicate to S-mode that an external interrupt is pending.",CSR_controlled,enum,high,False, +chunk_9f2de32d,src/priv/machine.adoc,1036,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers","Additionally, the platform-level interrupt controller may generate supervisor-level external interrupts.",non_CSR_parameter,enum,high,False, +chunk_df8119c0,src/priv/machine.adoc,1036,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers",Supervisor-level external interrupts are made pending based on the logical-OR of the software-writable SEIP bit and the signal from the external interrupt controller.,CSR_controlled,unknown,high,False, +chunk_34847606,src/priv/machine.adoc,1036,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers","When `mip` is read with a CSR instruction, the value of the SEIP bit returned in the `rd` destination register is the logical-OR of the software-writable bit and the interrupt signal from the interrupt controller, but the signal from the interrupt controller is not used to calculate the value written to SEIP.",CSR_controlled,enum,high,False, +chunk_f816d1c7,src/priv/machine.adoc,1036,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers",Only the software-writable SEIP bit participates in the read-modify-write sequence of a CSRRS or CSRRC instruction.,CSR_controlled,enum,high,False, +chunk_175de799,src/priv/machine.adoc,1051,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers","If supervisor mode is implemented, its `mip`.STIP and `mie`.STIE are the interrupt-pending and interrupt-enable bits for supervisor-level timer interrupts.",CSR_controlled,enum,high,False, +chunk_c6528dd5,src/priv/machine.adoc,1051,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers","If the stimecmp register is not implemented, STIP is writable in mip, and may be written by M-mode software to deliver timer interrupts to S-mode.",CSR_controlled,enum,high,False, +chunk_bcf865e1,src/priv/machine.adoc,1051,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers","If the `stimecmp` (supervisor-mode timer compare) register is implemented, STIP is read-only in mip and reflects the supervisor-level timer interrupt signal resulting from stimecmp.",CSR_controlled,enum,high,False, +chunk_7e415153,src/priv/machine.adoc,1051,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers",This timer interrupt signal is cleared by writing `stimecmp` with a value greater than the current time value.,unknown,range,high,False, +chunk_48370bce,src/priv/machine.adoc,1060,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers","If supervisor mode is implemented, bits `mip`.SSIP and `mie`.SSIE are the interrupt-pending and interrupt-enable bits for supervisor-level software interrupts. SSIP is writable in `mip` and may also be set to 1 by a platform-specific interrupt controller.",CSR_controlled,binary,high,False, +chunk_2fcb736a,src/priv/machine.adoc,1065,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers","If the Sscofpmf extension is implemented, bits `mip`.LCOFIP and `mie`.LCOFIE are the interrupt-pending and interrupt-enable bits for local-counter-overflow interrupts. LCOFIP is read-write in `mip` and reflects the occurrence of a local counter-overflow overflow interrupt request resulting from any of the `mhpmeventn`.OF bits being set.",CSR_controlled,enum,high,False, +chunk_c89ff2b9,src/priv/machine.adoc,1065,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers","If the Sscofpmf extension is not implemented, `mip`.LCOFIP and `mie`.LCOFIE are read-only zeros.",CSR_controlled,binary,high,False, +chunk_4f54e58a,src/priv/machine.adoc,1072,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers","Multiple simultaneous interrupts destined for M-mode are handled in the following decreasing priority order: MEI, MSI, MTI, SEI, SSI, STI, LCOFI.",unknown,unknown,high,False, +chunk_02680a48,src/priv/machine.adoc,1075,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers",Restricted views of the `mip` and `mie` registers appear as the `sip` and `sie` registers for supervisor level.,CSR_controlled,enum,high,False, +chunk_b19698c6,src/priv/machine.adoc,1075,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers","If an interrupt is delegated to S-mode by setting a bit in the `mideleg` register, it becomes visible in the `sip` register and is maskable using the `sie` register.",CSR_controlled,enum,high,False, +chunk_d6768a36,src/priv/machine.adoc,1075,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers","Otherwise, the corresponding bits in `sip` and `sie` are read-only zero.",CSR_controlled,binary,high,False, +chunk_bf331c5a,src/priv/machine.adoc,1083,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Hardware Performance Monitor",M-mode includes a basic hardware performance-monitoring facility.,unknown,unknown,high,False, +chunk_28843ab6,src/priv/machine.adoc,1083,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Hardware Performance Monitor",The `mcycle` CSR counts the number of clock cycles executed by the processor core on which the hart is running.,CSR_controlled,enum,high,False, +chunk_fa498d97,src/priv/machine.adoc,1083,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Hardware Performance Monitor",The `minstret` CSR counts the number of instructions the hart has retired.,CSR_controlled,enum,high,False, +chunk_def4c87f,src/priv/machine.adoc,1083,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Hardware Performance Monitor",The `mcycle` and `minstret` registers have 64-bit precision on all RV32 and RV64 harts.,non_CSR_parameter,range,high,False, +chunk_89beb2c1,src/priv/machine.adoc,1089,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Hardware Performance Monitor","The counter registers have an arbitrary value after the hart is reset, and can be written with a given value.",unknown,unknown,high,False, +chunk_31e379cc,src/priv/machine.adoc,1089,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Hardware Performance Monitor",Any CSR write takes effect after the writing instruction has otherwise completed.,CSR_controlled,enum,high,False, +chunk_a1d94f46,src/priv/machine.adoc,1089,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Hardware Performance Monitor","The `mcycle` CSR may be shared between harts on the same core, in which case writes to `mcycle` will be visible to those harts.",CSR_controlled,enum,high,False, +chunk_d642867e,src/priv/machine.adoc,1089,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Hardware Performance Monitor",The platform should provide a mechanism to indicate which harts share an `mcycle` CSR.,CSR_controlled,enum,high,False, +chunk_25bfdec6,src/priv/machine.adoc,1097,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Hardware Performance Monitor","The hardware performance monitor includes 29 additional 64-bit event counters, `mhpmcounter3`-`mhpmcounter31`.",CSR_controlled,range,high,False, +chunk_cbc5e064,src/priv/machine.adoc,1097,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Hardware Performance Monitor","The event selector CSRs, `mhpmevent3`-`mhpmevent31`, are 64-bit *WARL* registers that control which event causes the corresponding counter to increment.",CSR_controlled,range,very_high,False, +chunk_a0d4e58a,src/priv/machine.adoc,1097,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Hardware Performance Monitor","The meaning of these events is defined by the platform, but event 0 is defined to mean ""no event."" All counters should be implemented, but a legal implementation is to make both the counter and its corresponding event selector be read-only 0.",non_CSR_parameter,enum,high,False, +chunk_c3b9c545,src/priv/machine.adoc,1110,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Hardware Performance Monitor",The `mhpmcounters` are *WARL* registers that support up to 64 bits of precision on RV32 and RV64.,CSR_controlled,range,very_high,False, +chunk_10faa860,src/priv/machine.adoc,1113,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Hardware Performance Monitor","When XLEN=32, reads of the `mcycle`, `minstret`, `mhpmcountern`, and `mhpmeventn` CSRs return bitj 31-0 of the corresponding register, and writes change only bits 31-0; reads of the `mcycleh`, `minstreth`, `mhpmcounternh`, and `mhpmeventnh` CSRs return bits 63-32 of the corresponding register, and writes change only bits 63-32.",CSR_controlled,enum,high,False, +chunk_6574111b,src/priv/machine.adoc,1113,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Hardware Performance Monitor",The `mhpmeventnh` CSRs are provided only if the Sscofpmf extension is implemented.,CSR_controlled,enum,high,False, +chunk_1f0ee636,src/priv/machine.adoc,1122,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Counter-Enable (`mcounteren`) Register",The counter-enable `mcounteren` register is a 32-bit register that controls the availability of the hardware performance-monitoring counters to the next-lower privileged mode.,CSR_controlled,range,high,False, +chunk_336159c2,src/priv/machine.adoc,1130,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Counter-Enable (`mcounteren`) Register",The settings in this register only control accessibility.,unknown,unknown,high,False, +chunk_bd565d3e,src/priv/machine.adoc,1130,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Counter-Enable (`mcounteren`) Register","The act of reading or writing this register does not affect the underlying counters, which continue to increment even when not accessible.",unknown,unknown,high,False, +chunk_448ffd84,src/priv/machine.adoc,1134,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Counter-Enable (`mcounteren`) Register","When the CY, TM, IR, or HPMn bit in the `mcounteren` register is clear, attempts to read the `cycle`, `time`, `instret`, or `hpmcountern` register while executing in S-mode or U-mode will cause an illegal-instruction exception.",CSR_controlled,enum,high,False, +chunk_a76bcb84,src/priv/machine.adoc,1134,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Counter-Enable (`mcounteren`) Register","When one of these bits is set, access to the corresponding register is permitted in the next implemented privilege mode (S-mode if implemented, otherwise U-mode).",unknown,enum,high,False, +chunk_f737b3c9,src/priv/machine.adoc,1142,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Counter-Enable (`mcounteren`) Register","In addition, when the TM bit in the `mcounteren` register is clear, attempts to access the `stimecmp` or `vstimecmp` register while executing in a mode less privileged than M will cause an illegal-instruction exception.",CSR_controlled,enum,high,False, +chunk_0d64f639,src/priv/machine.adoc,1142,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Counter-Enable (`mcounteren`) Register","When this bit is set, access to the `stimecmp` or `vstimecmp` register is permitted in S-mode if implemented, and access to the `vstimecmp` register (via `stimecmp`) is permitted in VS-mode if implemented and not otherwise prevented by the TM bit in `hcounteren`.",CSR_controlled,enum,high,False, +chunk_02d4a97d,src/priv/machine.adoc,1150,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Counter-Enable (`mcounteren`) Register","The `cycle`, `instret`, and `hpmcountern` CSRs are read-only shadows of `mcycle`, `minstret`, and `mhpmcounter n`, respectively.",CSR_controlled,enum,high,False, +chunk_279fed9a,src/priv/machine.adoc,1150,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Counter-Enable (`mcounteren`) Register",The `time` CSR is a read-only shadow of the memory-mapped `mtime` register.,CSR_controlled,enum,high,False, +chunk_748e7efb,src/priv/machine.adoc,1150,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Counter-Enable (`mcounteren`) Register","Analogously, when XLEN=32, the `cycleh`, `instreth` and `hpmcounternh` CSRs are read-only shadows of `mcycleh`, `minstreth` and `mhpmcounternh`, respectively.",CSR_controlled,enum,high,False, +chunk_9d412348,src/priv/machine.adoc,1150,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Counter-Enable (`mcounteren`) Register","When XLEN=32, the `timeh` CSR is a read-only shadow of the upper 32 bits of the memory-mapped `mtime` register, while `time` shadows only the lower 32 bits of `mtime`.",CSR_controlled,range,high,False, +chunk_d70331a3,src/priv/machine.adoc,1158,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Counter-Enable (`mcounteren`) Register","In harts with U-mode, the `mcounteren` must be implemented, but all fields are *WARL* and may be read-only zero, indicating reads to the corresponding counter will cause an illegal-instruction exception when executing in a less-privileged mode.",CSR_controlled,binary,very_high,False, +chunk_ad7adaf0,src/priv/machine.adoc,1158,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Counter-Enable (`mcounteren`) Register","In harts without U-mode, the `mcounteren` register should not exist.",CSR_controlled,enum,high,False, +chunk_46e15e4b,src/priv/machine.adoc,1171,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Counter-Inhibit (`mcountinhibit`) Register",The counter-inhibit register `mcountinhibit` is a 32-bit *WARL* register that controls which of the hardware performance-monitoring counters increment.,CSR_controlled,range,very_high,False, +chunk_6ec94bf3,src/priv/machine.adoc,1171,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Counter-Inhibit (`mcountinhibit`) Register",The settings in this register only control whether the counters increment; their accessibility is not affected by the setting of this register.,unknown,unknown,high,False, +chunk_645c1ceb,src/priv/machine.adoc,1177,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Counter-Inhibit (`mcountinhibit`) Register","When the CY, IR, or HPMn bit in the `mcountinhibit` register is clear, the `mcycle`, `minstret`, or `mhpmcountern` register increments as usual.",CSR_controlled,enum,high,False, +chunk_5dbe48e8,src/priv/machine.adoc,1177,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Counter-Inhibit (`mcountinhibit`) Register","When the CY, IR, or HPMn bit is set, the corresponding counter does not increment.",unknown,unknown,high,False, +chunk_93ff94a8,src/priv/machine.adoc,1182,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Counter-Inhibit (`mcountinhibit`) Register","The `mcycle` CSR may be shared between harts on the same core, in which case the `mcountinhibit.CY` field is also shared between those harts, and so writes to `mcountinhibit.CY` will be visible to those harts.",CSR_controlled,enum,high,False, +chunk_4a5ca476,src/priv/machine.adoc,1186,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Counter-Inhibit (`mcountinhibit`) Register","If the `mcountinhibit` register is not implemented, the implementation behaves as though the register were set to zero.",unknown,binary,high,False, +chunk_0f23ff77,src/priv/machine.adoc,1191,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Scratch (`mscratch`) Register",The `mscratch` register is an MXLEN-bit read/write register dedicated for use by machine mode.,CSR_controlled,range,high,False, +chunk_33769378,src/priv/machine.adoc,1202,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Exception Program Counter (`mepc`) Register",`mepc` is an MXLEN-bit read/write register formatted as shown in .,CSR_controlled,range,high,False, +chunk_894c0c7e,src/priv/machine.adoc,1202,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Exception Program Counter (`mepc`) Register",The low bit of `mepc` (`mepc[0]`) is always zero.,CSR_controlled,enum,high,False, +chunk_c78bea8c,src/priv/machine.adoc,1205,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Exception Program Counter (`mepc`) Register",This masking occurs also for the implicit read by the MRET instruction.,unknown,unknown,high,False, +chunk_400d5857,src/priv/machine.adoc,1205,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Exception Program Counter (`mepc`) Register","Though masked, `mepc[1]` remains writable when IALIGN=32.",CSR_controlled,enum,high,False, +chunk_a3273ca0,src/priv/machine.adoc,1211,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Exception Program Counter (`mepc`) Register",`mepc` is a *WARL* register that must be able to hold all valid virtual addresses.,CSR_controlled,enum,very_high,False, +chunk_9e9d6e72,src/priv/machine.adoc,1211,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Exception Program Counter (`mepc`) Register",It need not be capable of holding all possible invalid addresses.,non_CSR_parameter,enum,high,False, +chunk_7e79b09c,src/priv/machine.adoc,1211,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Exception Program Counter (`mepc`) Register","Prior to writing `mepc`, implementations may convert an invalid address into some other invalid address that `mepc` is capable of holding.",CSR_controlled,enum,high,False, +chunk_2ce18db2,src/priv/machine.adoc,1216,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Exception Program Counter (`mepc`) Register","When a trap is taken into M-mode, `mepc` is written with the virtual address of the instruction that was interrupted or that encountered the exception.",CSR_controlled,enum,high,False, +chunk_79085299,src/priv/machine.adoc,1216,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Exception Program Counter (`mepc`) Register","Otherwise, `mepc` is never written by the implementation, though it may be explicitly written by software.",CSR_controlled,enum,high,False, +chunk_974d8b2b,src/priv/machine.adoc,1228,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Cause (`mcause`) Register",The `mcause` register is an MXLEN-bit read-write register formatted as shown in .,CSR_controlled,range,high,False, +chunk_cd2a0388,src/priv/machine.adoc,1228,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Cause (`mcause`) Register","When a trap is taken into M-mode, `mcause` is written with a code indicating the event that caused the trap.",CSR_controlled,enum,high,False, +chunk_3225e09a,src/priv/machine.adoc,1228,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Cause (`mcause`) Register","Otherwise, `mcause` is never written by the implementation, though it may be explicitly written by software.",CSR_controlled,enum,high,False, +chunk_7f146307,src/priv/machine.adoc,1235,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Cause (`mcause`) Register",The Interrupt bit in the `mcause` register is set if the trap was caused by an interrupt.,CSR_controlled,enum,high,False, +chunk_90c085b1,src/priv/machine.adoc,1235,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Cause (`mcause`) Register",The Exception Code field contains a code identifying the last exception or interrupt. lists the possible machine-level exception codes.,unknown,enum,high,False, +chunk_1a7a51a1,src/priv/machine.adoc,1235,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Cause (`mcause`) Register","The Exception Code is a *WLRL* field, so is only guaranteed to hold supported exception codes.",CSR_controlled,enum,very_high,False, +chunk_f7fe7e88,src/priv/machine.adoc,1250,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Cause (`mcause`) Register","If an instruction may raise multiple synchronous exceptions, the decreasing priority order of indicates which exception is taken and reported in `mcause`.",CSR_controlled,enum,high,False, +chunk_a01cd9ba,src/priv/machine.adoc,1250,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Cause (`mcause`) Register",The priority of any custom synchronous exceptions is implementation-defined.,non_CSR_parameter,unknown,high,False, +chunk_dc4b8d54,src/priv/machine.adoc,1275,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Cause (`mcause`) Register",|1 + 1 + 1 + 1 |4 + 5 + 6 + 7 |Reserved + Supervisor timer interrupt + Reserved + Machine timer interrupt |1 + 1 + 1 + 1 |8 + 9 + 10 + 11 |Reserved + Supervisor external interrupt + Reserved + Machine external interrupt |1 + 1 + 1 + 1 |12 + 13 + 14-15 + {ge}16 |Reserved + Counter-overflow interrupt + Reserved + Designated for platform use |0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 |0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 11 + 12 + 13 + 14 + 15 + 16 + 17 + 18 + 19 + 20-23 + 24-31 + 32-47 + 48-63 + {ge}64 |Instruction address misaligned + Instruction access fault + Illegal instruction + Breakpoint + Load address misaligned + Load access fault + Store/AMO address misaligned + Store/AMO access fault + Environment call from U-mode + Environment call from S-mode + Reserved + Environment call from M-mode + Instruction page fault + Load page fault + Reserved + Store/AMO page fault + Double trap + Reserved + Software check + Hardware error + Reserved + Designated for custom use + Reserved + Designated for custom use + Reserved |,SW_rule,unknown,high,False, +chunk_59198742,src/priv/machine.adoc,1401,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Cause (`mcause`) Register","| .>|2 + 0 + 8,9,11 + 3 + 3 .<|Illegal instruction + Instruction address misaligned + Environment call + Environment break + Load/store/AMO address breakpoint",non_CSR_parameter,unknown,high,False, +chunk_01630f9a,src/priv/machine.adoc,1411,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Cause (`mcause`) Register",If not higher priority: + Load/store/AMO address misaligned |,unknown,unknown,high,False, +chunk_7d41c0f4,src/priv/machine.adoc,1421,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Cause (`mcause`) Register","When a virtual address is translated into a physical address, the address translation algorithm determines what specific exception may be raised.",non_CSR_parameter,enum,high,False, +chunk_8b2ae533,src/priv/machine.adoc,1425,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Cause (`mcause`) Register",Load/store/AMO address-misaligned exceptions may have either higher or lower priority than load/store/AMO page-fault and access-fault exceptions.,non_CSR_parameter,enum,high,False, +chunk_b3de19a0,src/priv/machine.adoc,1430,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register",The `mtval` register is an MXLEN-bit read-write register formatted as shown in .,CSR_controlled,range,high,False, +chunk_c6bb5c39,src/priv/machine.adoc,1430,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register","When a trap is taken into M-mode, `mtval` is either set to zero or written with exception-specific information to assist software in handling the trap.",CSR_controlled,binary,high,False, +chunk_926a2a42,src/priv/machine.adoc,1430,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register","Otherwise, `mtval` is never written by the implementation, though it may be explicitly written by software.",CSR_controlled,enum,high,False, +chunk_86032fce,src/priv/machine.adoc,1430,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register","The hardware platform will specify which exceptions must set `mtval` informatively, which may unconditionally set it to zero, and which may exhibit either behavior, depending on the underlying event that caused the exception.",CSR_controlled,enum,very_high,False, +chunk_793ceab0,src/priv/machine.adoc,1430,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register","If the hardware platform specifies that no exceptions set `mtval` to a nonzero value, then `mtval` is read-only zero.",CSR_controlled,binary,high,False, +chunk_534a4458,src/priv/machine.adoc,1444,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register","If `mtval` is written with a nonzero value when a breakpoint, address-misaligned, access-fault, page-fault, or hardware-error exception occurs on an instruction fetch, load, or store, then `mtval` will contain the faulting virtual address.",CSR_controlled,enum,high,False, +chunk_4e9f7500,src/priv/machine.adoc,1449,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register","On a breakpoint exception raised by an EBREAK or C.EBREAK instruction, `mtval` is written with either zero or the virtual address of the instruction.",CSR_controlled,enum,high,False, +chunk_781d6ea8,src/priv/machine.adoc,1452,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register",Recording the same address in `mtval` is redundant; the option is provided for backwards compatibility.,CSR_controlled,enum,high,False, +chunk_79005a81,src/priv/machine.adoc,1457,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register","When page-based virtual memory is enabled, `mtval` is written with the faulting virtual address, even for physical-memory access-fault exceptions.",CSR_controlled,binary,high,False, +chunk_4aa9808b,src/priv/machine.adoc,1457,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register","This design reduces datapath cost for most implementations, particularly those with hardware page-table walkers.",unknown,unknown,high,False, +chunk_4a820417,src/priv/machine.adoc,1466,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register","If `mtval` is written with a nonzero value when a misaligned load or store causes an access-fault, page-fault, or hardware-error exception, then `mtval` will contain the virtual address of the portion of the access that caused the fault.",CSR_controlled,enum,high,False, +chunk_eae12ebf,src/priv/machine.adoc,1470,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register","If `mtval` is written with a nonzero value when an instruction access-fault, page-fault, or hardware-error exception occurs on a hart with variable-length instructions, then `mtval` will contain the virtual address of the portion of the instruction that caused the fault, while `mepc` will point to the beginning of the instruction.",CSR_controlled,enum,high,False, +chunk_517a9e58,src/priv/machine.adoc,1476,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register",The `mtval` register can optionally also be used to return the faulting instruction bits on an illegal-instruction exception (`mepc` points to the faulting instruction in memory).,CSR_controlled,enum,high,False, +chunk_f212f1d7,src/priv/machine.adoc,1476,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register","If `mtval` is written with a nonzero value when an illegal-instruction exception occurs, then `mtval` will contain the shortest of:",CSR_controlled,enum,high,False, +chunk_96e13513,src/priv/machine.adoc,1485,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register",the first ILEN bits of the faulting instruction,unknown,unknown,high,False, +chunk_5bd38fb8,src/priv/machine.adoc,1487,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register",the first MXLEN bits of the faulting instruction,unknown,range,high,False, +chunk_7ae3e0e3,src/priv/machine.adoc,1489,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register",The value loaded into `mtval` on an illegal-instruction exception is right-justified and all unused upper bits are cleared to zero.,CSR_controlled,binary,high,False, +chunk_b4ad84cb,src/priv/machine.adoc,1492,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register","On a trap caused by a software-check exception, the `mtval` register holds the cause for the exception.",CSR_controlled,enum,high,False, +chunk_7fddd41d,src/priv/machine.adoc,1495,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register",Defined by the Zicfilp extension (). * 3 - Shadow Stack Fault.,unknown,unknown,high,False, +chunk_b357cf49,src/priv/machine.adoc,1495,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register",Defined by the Zicfiss extension ().,unknown,unknown,high,False, +chunk_01ce2592,src/priv/machine.adoc,1500,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register","For other traps, `mtval` is set to zero, but a future standard may redefine `mtval`’s setting for other traps.",CSR_controlled,binary,high,False, +chunk_222a5514,src/priv/machine.adoc,1503,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register","If `mtval` is not read-only zero, it is a *WARL* register that must be able to hold all valid virtual addresses and the value zero.",CSR_controlled,binary,very_high,False, +chunk_d6a14e20,src/priv/machine.adoc,1503,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register",It need not be capable of holding all possible invalid addresses.,non_CSR_parameter,enum,high,False, +chunk_7158f972,src/priv/machine.adoc,1503,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register","Prior to writing `mtval`, implementations may convert an invalid address into some other invalid address that `mtval` is capable of holding.",CSR_controlled,enum,high,False, +chunk_26152e75,src/priv/machine.adoc,1503,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register","If the feature to return the faulting instruction bits is implemented, `mtval` must also be able to hold all values less than 2^N^, where N is the smaller of MXLEN and ILEN.",CSR_controlled,range,very_high,False, +chunk_0e2bd3cd,src/priv/machine.adoc,1514,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Configuration Pointer (`mconfigptr`) Register","The `mconfigptr` register is an MXLEN-bit read-only CSR formatted as shown in , that holds the physical address of a configuration data structure.",CSR_controlled,range,high,False, +chunk_b37b4366,src/priv/machine.adoc,1514,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Configuration Pointer (`mconfigptr`) Register","Software can traverse this data structure to discover information about the harts, the platform, and their configuration.",SW_rule,unknown,high,False, +chunk_fa8f1791,src/priv/machine.adoc,1523,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Configuration Pointer (`mconfigptr`) Register","The pointer alignment in bits must be no smaller than MXLEN: i.e., if MXLEN is 8{times}n, then `mconfigptr`[log~2n~-1:0] must be zero.",non_CSR_parameter,binary,very_high,False, +chunk_f759daba,src/priv/machine.adoc,1526,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Configuration Pointer (`mconfigptr`) Register","The `mconfigptr` register must be implemented, but it may be zero to indicate the configuration data structure does not exist or that an alternative mechanism must be used to locate it.",non_CSR_parameter,enum,very_high,False, +chunk_6b5d94e6,src/priv/machine.adoc,1534,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register","The `menvcfg` CSR is a 64-bit read/write register, formatted as shown in , that controls certain characteristics of the execution environment for modes less privileged than M.",CSR_controlled,range,high,False, +chunk_b26cd47f,src/priv/machine.adoc,1543,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register","If bit FIOM (Fence of I/O implies Memory) is set to one in `menvcfg`, FENCE instructions executed in modes less privileged than M are modified so the requirement to order accesses to device I/O implies also the requirement to order main memory accesses. details the modified interpretation of FENCE instruction bits PI, PO, SI, and SO for modes less privileged than M when FIOM=1.",CSR_controlled,binary,high,False, +chunk_c6bedfde,src/priv/machine.adoc,1550,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register","Similarly, for modes less privileged than M when FIOM=1, if an atomic instruction that accesses a region ordered as device I/O has its aq and/or rl bit set, then that instruction is ordered as though it accesses both device I/O and memory.",unknown,unknown,high,False, +chunk_1a819b2c,src/priv/machine.adoc,1555,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register","If S-mode is not supported, or if `satp`.MODE is read-only zero (always Bare), the implementation may make FIOM read-only zero.",CSR_controlled,binary,high,False, +chunk_b5c82b97,src/priv/machine.adoc,1573,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register","When PBMTE=1, Svpbmt is available for S-mode and G-stage address translation.",unknown,unknown,high,False, +chunk_c7535f8e,src/priv/machine.adoc,1573,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register","When PBMTE=0, the implementation behaves as though Svpbmt were not implemented.",unknown,unknown,high,False, +chunk_5d6cfd13,src/priv/machine.adoc,1573,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register","If Svpbmt is not implemented, PBMTE is read-only zero.",unknown,binary,high,False, +chunk_01e2e285,src/priv/machine.adoc,1573,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register","Furthermore, for implementations with the hypervisor extension, `henvcfg`.PBMTE is read-only zero if `menvcfg`.PBMTE is zero.",CSR_controlled,binary,high,False, +chunk_9177ce98,src/priv/machine.adoc,1583,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register","After changing `menvcfg`.PBMTE, executing an SFENCE.VMA instruction with rs1=`x0` and rs2=`x0` suffices to synchronize address-translation caches with respect to the altered interpretation of page-table entries' PBMT fields.",CSR_controlled,enum,high,False, +chunk_63b376fc,src/priv/machine.adoc,1583,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register",See for additional synchronization requirements when the hypervisor extension is implemented.,SW_rule,unknown,high,False, +chunk_2ea06bc7,src/priv/machine.adoc,1589,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register","If the Svadu extension is implemented, the ADUE bit controls whether hardware updating of PTE A/D bits is enabled for S-mode and G-stage address translations.",non_CSR_parameter,binary,high,False, +chunk_32026e87,src/priv/machine.adoc,1589,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register","When ADUE=1, hardware updating of PTE A/D bits is enabled during S-mode address translation, and the implementation behaves as though the Svade extension were not implemented for S-mode address translation.",unknown,binary,high,False, +chunk_1c2cd140,src/priv/machine.adoc,1589,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register","When the hypervisor extension is implemented, if ADUE=1, hardware updating of PTE A/D bits is enabled during G-stage address translation, and the implementation behaves as though the Svade extension were not implemented for G-stage address translation.",SW_rule,binary,high,False, +chunk_63e6cf67,src/priv/machine.adoc,1589,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register","When ADUE=0, the implementation behaves as though Svade were implemented for S-mode and G-stage address translation.",unknown,unknown,high,False, +chunk_1713000e,src/priv/machine.adoc,1589,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register","If Svadu is not implemented, ADUE is read-only zero.",unknown,binary,high,False, +chunk_8c077b4e,src/priv/machine.adoc,1589,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register","Furthermore, for implementations with the hypervisor extension, `henvcfg`.ADUE is read-only zero if `menvcfg`.ADUE is zero.",CSR_controlled,binary,high,False, +chunk_959d9d23,src/priv/machine.adoc,1604,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register","After changing `menvcfg`.ADUE, executing an SFENCE.VMA instruction with rs1=`x0` and rs2=`x0` suffices to synchronize address-translation caches with respect to the altered interpretation of page-table entries' A/D bits.",CSR_controlled,enum,high,False, +chunk_8e0f208d,src/priv/machine.adoc,1604,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register",See for additional synchronization requirements when the hypervisor extension is implemented.,SW_rule,unknown,high,False, +chunk_02ef84a2,src/priv/machine.adoc,1613,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register","If the Smcdeleg extension is implemented, the CDE (Counter Delegation Enable) bit controls whether Zicntr and Zihpm counters can be delegated to S-mode.",non_CSR_parameter,unknown,high,False, +chunk_c2cae747,src/priv/machine.adoc,1613,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register","When CDE=0, the Smcdeleg and Ssccfg extensions appear to be not implemented.",unknown,unknown,high,False, +chunk_19f6cc0e,src/priv/machine.adoc,1613,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register","If Smcdeleg is not implemented, CDE is read-only zero.",unknown,binary,high,False, +chunk_6eea3e76,src/priv/machine.adoc,1618,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register",The Sstc extension adds the `STCE` (STimecmp Enable) bit to `menvcfg` CSR.,CSR_controlled,enum,high,False, +chunk_fbe0044a,src/priv/machine.adoc,1618,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register","When the Sstc extension is not implemented, `STCE` is read-only zero.",unknown,binary,high,False, +chunk_9acac6ae,src/priv/machine.adoc,1618,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register",The `STCE` bit enables `stimecmp` for S-mode when set to one.,unknown,binary,high,False, +chunk_418c4aa9,src/priv/machine.adoc,1618,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register","When this extension is implemented and `STCE` in `menvcfg` is zero, an attempt to access `stimecmp` in a mode other than M-mode raises an illegal-instruction exception, `STCE` in `henvcfg` is read-only zero, and `STIP` in `mip` and `sip` reverts to its defined behavior as if this extension is not implemented.",CSR_controlled,binary,high,False, +chunk_bf49779f,src/priv/machine.adoc,1618,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register","Further, if the H extension is implemented, then `hip`.VSTIP also reverts its defined behavior as if this extension is not implemented.",unknown,unknown,high,False, +chunk_32c01454,src/priv/machine.adoc,1628,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register",The Zicboz extension adds the `CBZE` (Cache Block Zero instruction enable) field to `menvcfg`.,CSR_controlled,enum,high,False, +chunk_b0abffbc,src/priv/machine.adoc,1628,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register","When the `CBZE` field is set to 1, it enables execution of the cache block zero instruction, `CBO.ZERO`, in modes less privileged than M.",unknown,binary,high,False, +chunk_daa32a31,src/priv/machine.adoc,1628,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register","Otherwise, the instruction raises an illegal-instruction exception in modes less privileged than M.",non_CSR_parameter,unknown,high,False, +chunk_dee85240,src/priv/machine.adoc,1628,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register","When the Zicboz extension is not implemented, `CBZE` is read-only zero.",unknown,binary,high,False, +chunk_e87db62f,src/priv/machine.adoc,1635,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register",The Zicbom extension adds the `CBCFE` (Cache Block Clean and Flush instruction Enable) field to `menvcfg`.,CSR_controlled,enum,high,False, +chunk_6347d506,src/priv/machine.adoc,1635,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register","When the `CBCFE` field is set to 1, it enables execution of the cache block clean instruction (`CBO.CLEAN`) and the cache block flush instruction (`CBO.FLUSH`) in modes less privileged than M.",unknown,binary,high,False, +chunk_33bcce79,src/priv/machine.adoc,1635,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register","Otherwise, these instructions raise an illegal-instruction exception in modes less privileged than M.",non_CSR_parameter,unknown,high,False, +chunk_15592db1,src/priv/machine.adoc,1635,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register","When the Zicbom extension is not implemented, `CBCFE` is read-only zero.",unknown,binary,high,False, +chunk_3c696e69,src/priv/machine.adoc,1642,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register",The Zicbom extension adds the `CBIE` (Cache Block Invalidate instruction Enable) WARL field to `menvcfg` to control execution of the cache block invalidate instruction (`CBO.INVAL`) in modes less privileged than M.,CSR_controlled,enum,very_high,False, +chunk_f8bb0d24,src/priv/machine.adoc,1642,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register","When `CBIE` is set to `00b`, the instruction raises an illegal-instruction exception in modes less privileged than M.",non_CSR_parameter,unknown,high,False, +chunk_c9bfe064,src/priv/machine.adoc,1642,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register","When the Zicbom extension is not implemented, `CBIE` is read-only zero.",unknown,binary,high,False, +chunk_be418e42,src/priv/machine.adoc,1642,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register",The encoding `10b` is reserved.,unknown,enum,high,False, +chunk_f992dc0a,src/priv/machine.adoc,1642,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register","When `CBIE` is set to `01b` or `11b`, and when enabled for execution in modes less privileged than M, it behaves as follows:",unknown,binary,high,False, +chunk_68bcc158,src/priv/machine.adoc,1660,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register","If Smnpm is not implemented, `PMM` is read-only zero.",unknown,binary,high,False, +chunk_2d2afed6,src/priv/machine.adoc,1660,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register",The `PMM` field is read-only zero for RV32.,CSR_controlled,binary,high,False, +chunk_8d373a3d,src/priv/machine.adoc,1678,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register",The Zicfilp extension adds the `LPE` field in `menvcfg`.,CSR_controlled,enum,high,False, +chunk_b1cf0b58,src/priv/machine.adoc,1678,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register","When the `LPE` field is set to 1 and S-mode is implemented, the Zicfilp extension is enabled in S-mode.",unknown,binary,high,False, +chunk_70faa1c2,src/priv/machine.adoc,1678,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register","If `LPE` field is set to 1 and S-mode is not implemented, the Zicfilp extension is enabled in U-mode.",unknown,binary,high,False, +chunk_269adcd5,src/priv/machine.adoc,1678,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register","When the `LPE` field is 0, the Zicfilp extension is not enabled in S-mode, and the following rules apply to S-mode.",unknown,binary,high,False, +chunk_b8f6606f,src/priv/machine.adoc,1678,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register","If the `LPE` field is 0 and S-mode is not implemented, then the same rules apply to U-mode.",unknown,enum,high,False, +chunk_a8b987e5,src/priv/machine.adoc,1689,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register",The Zicfiss extension adds the `SSE` field to `menvcfg`.,CSR_controlled,enum,high,False, +chunk_91215264,src/priv/machine.adoc,1689,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register",When the `SSE` field is set to 1 the Zicfiss extension is activated in S-mode.,unknown,binary,high,False, +chunk_d2e9f392,src/priv/machine.adoc,1689,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register","When `SSE` field is 0, the following rules apply to privilege modes that are less than M:",unknown,range,high,False, +chunk_98301486,src/priv/machine.adoc,1699,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register","When `menvcfg.SSE` is 0, the `henvcfg.SSE` and `senvcfg.SSE` fields are read-only zero.",CSR_controlled,binary,high,False, +chunk_5ae49243,src/priv/machine.adoc,1702,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register",The Ssdbltrp extension adds the double-trap-enable (`DTE`) field in `menvcfg`.,CSR_controlled,enum,high,False, +chunk_2947ff05,src/priv/machine.adoc,1702,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register","When `menvcfg.DTE` is zero, the implementation behaves as though Ssdbltrp is not implemented.",CSR_controlled,enum,high,False, +chunk_4c4e0154,src/priv/machine.adoc,1702,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register","When Ssdbltrp is not implemented `sstatus.SDT`, `vsstatus.SDT`, and `henvcfg.DTE` bits are read-only zero.",CSR_controlled,binary,high,False, +chunk_5097ea49,src/priv/machine.adoc,1707,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register","When XLEN=32, `menvcfgh` is a 32-bit read/write register that aliases bits 63:32 of `menvcfg`.",CSR_controlled,range,high,False, +chunk_f2a9aeca,src/priv/machine.adoc,1707,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register",The `menvcfgh` register does not exist when XLEN=64.,CSR_controlled,enum,high,False, +chunk_0c666e52,src/priv/machine.adoc,1711,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register","If U-mode is not supported, then registers `menvcfg` and `menvcfgh` do not exist.",CSR_controlled,enum,high,False, +chunk_ba5dab71,src/priv/machine.adoc,1718,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register","`mseccfg` is a 64-bit read/write register, formatted as shown in , that controls security features.",CSR_controlled,range,high,False, +chunk_bd90e5f9,src/priv/machine.adoc,1718,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register",It exists if any extension that adds a field to `mseccfg` is implemented.,unknown,enum,high,False, +chunk_c30b6906,src/priv/machine.adoc,1718,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register","Otherwise, it is reserved.",unknown,unknown,high,False, +chunk_bf73c9ea,src/priv/machine.adoc,1726,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register",The Zkr extension adds the `SSEED` and `USEED` fields to the `mseccfg` CSR to control access to the `seed` CSR from modes less privileged than M.,CSR_controlled,enum,high,False, +chunk_4b4ffe32,src/priv/machine.adoc,1730,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register","When `USEED` is 0, access to the `seed` CSR in U-mode raises an illegal-instruction exception.",CSR_controlled,enum,high,False, +chunk_fc2f2afc,src/priv/machine.adoc,1730,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register","When `USEED` is 1, read-write access to the `seed` CSR from U-mode is allowed; all other types of accesses raise an illegal-instruction exception.",CSR_controlled,enum,high,False, +chunk_9fb7b0b0,src/priv/machine.adoc,1730,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register","If Zkr or U-mode is not implemented, `USEED` is read-only zero.",unknown,binary,high,False, +chunk_977fa0d9,src/priv/machine.adoc,1736,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register","When `SSEED` is 0, access to the `seed` CSR from S-/HS-mode raises an illegal-instruction exception.",CSR_controlled,enum,high,False, +chunk_bbc65491,src/priv/machine.adoc,1736,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register","When `SSEED` is 1, read-write access to the `seed` CSR from S-/HS-mode is allowed; all other types of accesses raise an illegal-instruction exception.",CSR_controlled,enum,high,False, +chunk_fa844029,src/priv/machine.adoc,1736,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register","If Zkr or S-mode is not implemented, `SSEED` is read-only zero.",unknown,binary,high,False, +chunk_10bc0f07,src/priv/machine.adoc,1742,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register","When the H extension is also implemented, access to the `seed` CSR from an HS-qualified instruction leads to a virtual-instruction exception in VS and VU modes; all other types of accesses raise an illegal-instruction exception.",CSR_controlled,enum,high,False, +chunk_18bfe2c7,src/priv/machine.adoc,1747,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register",No exception is raised for read-write. | S/HS | `0` | - | Any `seed` CSR access raises an illegal-instruction exception. | S/HS | `1` | - | The `seed` CSR is accessible as normal.,CSR_controlled,enum,high,False, +chunk_482b8a7e,src/priv/machine.adoc,1747,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register","No exception is raised for read-write. | VS/VU | `0` | - | Any `seed` CSR access raises an illegal-instruction exception. | VS/VU | `1` | - | A read-write `seed` access raises a virtual-instruction exception, while other access conditions raise an illegal-instruction exception. |",CSR_controlled,enum,high,False, +chunk_ef244b8f,src/priv/machine.adoc,1772,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register","The Smepmp extension adds the `RLB`, `MMWP`, and the `MML` fields in `mseccfg`.",unknown,enum,high,False, +chunk_f2035520,src/priv/machine.adoc,1776,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register",When `mseccfg.RLB` (Rule Locking Bypass) a WARL field that provides a mechanism to temporarily modify *Locked* PMP rules.,CSR_controlled,enum,very_high,False, +chunk_0c2a37d0,src/priv/machine.adoc,1776,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register","When `mseccfg.RLB` is 1, locked PMP rules may be removed or modified and locked PMP rules may be edited.",non_CSR_parameter,enum,high,False, +chunk_b412b8e1,src/priv/machine.adoc,1776,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register","When `mseccfg.RLB` is 0 and `pmpcfg.L` is 1 in any rule or entry (including disabled entries), then `mseccfg.RLB` remains 0 and any further modifications to `mseccfg.RLB` are ignored until a *PMP reset*.",CSR_controlled,binary,high,False, +chunk_b7608473,src/priv/machine.adoc,1784,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register",The `mseccfg.MMWP` (Machine-Mode Allowlist Policy) is a WARL field.,CSR_controlled,enum,very_high,False, +chunk_ca67e96a,src/priv/machine.adoc,1784,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register",This field changes the default PMP policy for Machine mode when accessing memory regions that don't have a matching PMP rule.,unknown,enum,high,False, +chunk_35ed255e,src/priv/machine.adoc,1784,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register","This is a sticky bit, meaning that once set it cannot be unset until a *PMP reset*.",unknown,unknown,high,False, +chunk_de2ac11f,src/priv/machine.adoc,1784,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register","When set it changes the default PMP policy for M-mode when accessing memory regions that don’t have a matching *PMP rule*, to *denied* instead of *ignored*.",unknown,unknown,high,False, +chunk_9d4a853a,src/priv/machine.adoc,1792,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register",The `mseccfg.MML` (Machine Mode Lockdown) is a WARL field.,CSR_controlled,enum,very_high,False, +chunk_4f10e145,src/priv/machine.adoc,1792,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register",The `MML` bit changes the interpretation of the `pmpcfg.L` bit defined in .,CSR_controlled,enum,high,False, +chunk_3e56a5dc,src/priv/machine.adoc,1792,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register","This is a sticky bit, meaning that once set it cannot be unset until a *PMP reset*.",unknown,unknown,high,False, +chunk_7f8150d9,src/priv/machine.adoc,1792,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register",When `mseccfg.MML` is set the system's behavior changes in the following way:,unknown,unknown,high,False, +chunk_4f692d0e,src/priv/machine.adoc,1798,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register","The meaning of `pmpcfg.L` changes: Instead of marking a rule as *locked* and *enforced* in all modes, it now marks a rule as *M-mode-only* when set and *S/U-mode-only* when unset.",CSR_controlled,enum,high,False, +chunk_f400c8d8,src/priv/machine.adoc,1798,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register","The formerly reserved encoding of `pmpcfg.RW=01`, and the encoding `pmpcfg.LRWX=1111`, now encode a *Shared-Region*. + + An M-mode-only rule is *enforced* on Machine mode and *denied* in Supervisor or User mode.",CSR_controlled,enum,high,False, +chunk_810446a6,src/priv/machine.adoc,1816,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register","A Shared-Region rule where `pmpcfg.L` is not set can be used for sharing data between M-mode and S/U-mode, so is not executable. M-mode has read/write access to that region, and S/U-mode has read access if `pmpcfg.X` is not set, or read/write access if `pmpcfg.X` is set. + * A Shared-Region rule where `pmpcfg.L` is set can be used for sharing code between M-mode and S/U-mode, so is not writable.",CSR_controlled,enum,high,False, +chunk_95dcaca5,src/priv/machine.adoc,1816,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register","Both M-mode and S/U-mode have execute access on the region, and M-mode also has read access if `pmpcfg.X` is set.",CSR_controlled,enum,high,False, +chunk_27199825,src/priv/machine.adoc,1816,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register","The rule remains *locked* so that any further modifications to its associated configuration or address registers are ignored until a *PMP reset*, unless `mseccfg.RLB` is set.",unknown,unknown,high,False, +chunk_c219f1f2,src/priv/machine.adoc,1834,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register","Adding a rule with executable privileges that either is *M-mode-only* or a *locked* *Shared-Region* is not possible and such `pmpcfg` writes are ignored, leaving `pmpcfg` unchanged.",CSR_controlled,enum,high,False, +chunk_3903bbd9,src/priv/machine.adoc,1839,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register",Executing code with Machine mode privileges is only possible from memory regions with a matching *M-mode-only* rule or a *locked* *Shared-Region* rule with executable privileges.,unknown,unknown,high,False, +chunk_8e06b98c,src/priv/machine.adoc,1839,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register",Executing code from a region without a matching rule or with a matching S/U-mode-only rule is *denied*.,unknown,unknown,high,False, +chunk_a39d18cd,src/priv/machine.adoc,1844,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register","If `mseccfg.MML` is not set, the combination of `pmpcfg.RW=01` remains reserved for future standard use.",CSR_controlled,enum,high,False, +chunk_593f6985,src/priv/machine.adoc,1847,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register","If Smmpm is not implemented, `PMM` is read-only zero.",unknown,binary,high,False, +chunk_d24af57b,src/priv/machine.adoc,1847,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register",The `PMM` field is read-only zero for RV32.,CSR_controlled,binary,high,False, +chunk_64ea3a7c,src/priv/machine.adoc,1864,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register",The Zicfilp extension adds the `MLPE` field in `mseccfg`.,unknown,enum,high,False, +chunk_ebd343ec,src/priv/machine.adoc,1864,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register","When `MLPE` field is 1, Zicfilp extension is enabled in M-mode.",unknown,binary,high,False, +chunk_dba9a7c1,src/priv/machine.adoc,1864,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register","When the `MLPE` field is 0, the Zicfilp extension is not enabled in M-mode and the following rules apply to M-mode.",unknown,binary,high,False, +chunk_eefb9289,src/priv/machine.adoc,1873,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register","When XLEN=32 only, `mseccfgh` is a 32-bit read/write register that aliases bits 63:32 of `mseccfg`.",CSR_controlled,range,high,False, +chunk_892519ce,src/priv/machine.adoc,1873,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register",Register `mseccfgh` exists when XLEN=32 and `mseccfg` is implemented; it does not exist when XLEN=64.,unknown,unknown,high,False, +chunk_65b21959,src/priv/machine.adoc,1882,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level Memory-Mapped Registers > Machine Timer (`mtime` and `mtimecmp`) Registers","Platforms provide a real-time counter, exposed as a memory-mapped machine-mode read-write register, `mtime`. `mtime` must increment at constant frequency, and the platform must provide a mechanism for determining the period of an `mtime` tick.",non_CSR_parameter,enum,very_high,False, +chunk_7800d79c,src/priv/machine.adoc,1882,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level Memory-Mapped Registers > Machine Timer (`mtime` and `mtimecmp`) Registers",The `mtime` register will wrap around if the count overflows.,unknown,unknown,high,False, +chunk_97e21d90,src/priv/machine.adoc,1889,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level Memory-Mapped Registers > Machine Timer (`mtime` and `mtimecmp`) Registers",The `mtime` register has a 64-bit precision on all RV32 and RV64 systems.,non_CSR_parameter,range,high,False, +chunk_54ecfd74,src/priv/machine.adoc,1889,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level Memory-Mapped Registers > Machine Timer (`mtime` and `mtimecmp`) Registers","Platforms provide a 64-bit memory-mapped machine-mode timer compare register (`mtimecmp`). A machine timer interrupt becomes pending whenever `mtime` contains a value greater than or equal to `mtimecmp`, treating the values as unsigned integers.",non_CSR_parameter,range,high,False, +chunk_90307464,src/priv/machine.adoc,1889,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level Memory-Mapped Registers > Machine Timer (`mtime` and `mtimecmp`) Registers",The interrupt will only be taken if interrupts are enabled and the MTIE bit is set in the `mie` register.,CSR_controlled,binary,high,False, +chunk_a1e92fba,src/priv/machine.adoc,1908,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level Memory-Mapped Registers > Machine Timer (`mtime` and `mtimecmp`) Registers","If the result of the comparison between `mtime` and `mtimecmp` changes, it is guaranteed to be reflected in MTIP eventually, but not necessarily immediately.",unknown,unknown,high,False, +chunk_79f3e2fa,src/priv/machine.adoc,1911,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level Memory-Mapped Registers > Machine Timer (`mtime` and `mtimecmp`) Registers","In RV32, memory-mapped writes to `mtimecmp` modify only one 32-bit part of the register.",non_CSR_parameter,range,high,False, +chunk_7f162edb,src/priv/machine.adoc,1911,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level Memory-Mapped Registers > Machine Timer (`mtime` and `mtimecmp`) Registers",The following code sequence sets a 64-bit `mtimecmp` value without spuriously generating a timer interrupt due to the intermediate value of the comparand:,non_CSR_parameter,range,high,False, +chunk_24712c10,src/priv/machine.adoc,1916,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level Memory-Mapped Registers > Machine Timer (`mtime` and `mtimecmp`) Registers","For RV64, naturally aligned 64-bit memory accesses to the `mtime` and `mtimecmp` registers are additionally supported and are atomic.",non_CSR_parameter,range,high,False, +chunk_2e11952f,src/priv/machine.adoc,1929,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level Memory-Mapped Registers > Machine Timer (`mtime` and `mtimecmp`) Registers",The `time` CSR is a read-only shadow of the memory-mapped `mtime` register.,CSR_controlled,enum,high,False, +chunk_006b0259,src/priv/machine.adoc,1929,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level Memory-Mapped Registers > Machine Timer (`mtime` and `mtimecmp`) Registers","When XLEN=32, the `timeh` CSR is a read-only shadow of the upper 32 bits of the memory-mapped `mtime` register, while `time` shadows only the lower 32 bits of `mtime`.",CSR_controlled,range,high,False, +chunk_7791f5a5,src/priv/machine.adoc,1929,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Level Memory-Mapped Registers > Machine Timer (`mtime` and `mtimecmp`) Registers","When `mtime` changes, it is guaranteed to be reflected in `time` and `timeh` eventually, but not necessarily immediately.",unknown,unknown,high,False, +chunk_edb19234,src/priv/machine.adoc,1943,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Mode Privileged Instructions > Environment Call and Breakpoint","When executed in U-mode, S-mode, or M-mode, it generates an environment-call-from-U-mode exception, environment-call-from-S-mode exception, or environment-call-from-M-mode exception, respectively, and performs no other operation.",unknown,unknown,high,False, +chunk_b34539c3,src/priv/machine.adoc,1950,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Mode Privileged Instructions > Environment Call and Breakpoint","Unless overridden by an external debug environment, EBREAK raises a breakpoint exception and performs no other operation.",non_CSR_parameter,unknown,high,False, +chunk_ff65dbc6,src/priv/machine.adoc,1956,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Mode Privileged Instructions > Environment Call and Breakpoint","As ECALL and EBREAK cause synchronous exceptions, they are not considered to retire, and should not increment the `minstret` CSR.",CSR_controlled,enum,high,False, +chunk_aff32645,src/priv/machine.adoc,1966,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Mode Privileged Instructions > Trap-Return Instructions",Instructions to return from trap are encoded under the PRIV minor opcode.,unknown,enum,high,False, +chunk_04fc3024,src/priv/machine.adoc,1972,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Mode Privileged Instructions > Trap-Return Instructions","To return after handling a trap, there are separate trap return instructions per privilege level, MRET and SRET. MRET is always provided. SRET must be provided if supervisor mode is supported, and should raise an illegal-instruction exception otherwise. SRET should also raise an illegal-instruction exception when TSR=1 in `mstatus`, as described in .",CSR_controlled,enum,very_high,False, +chunk_b472bbc9,src/priv/machine.adoc,1972,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Mode Privileged Instructions > Trap-Return Instructions","An xRET instruction can be executed in privilege mode x or higher, where executing a lower-privilege xRET instruction will pop the relevant lower-privilege interrupt enable and privilege mode stack.",unknown,enum,high,False, +chunk_e0ca707b,src/priv/machine.adoc,1972,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Mode Privileged Instructions > Trap-Return Instructions",Attempting to execute an xRET instruction in a mode less privileged than x will raise an illegal-instruction exception.,non_CSR_parameter,unknown,high,False, +chunk_45390cc1,src/priv/machine.adoc,1989,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Mode Privileged Instructions > Trap-Return Instructions","If the Zalrsc extension is supported, the xRET instruction is allowed to clear any outstanding LR address reservation but is not required to.",non_CSR_parameter,enum,high,False, +chunk_0f05e3d9,src/priv/machine.adoc,1997,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Mode Privileged Instructions > Wait for Interrupt",The Wait for Interrupt instruction (WFI) informs the implementation that the current hart can be stalled until an interrupt might need servicing.,unknown,unknown,high,False, +chunk_03c4951a,src/priv/machine.adoc,1997,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Mode Privileged Instructions > Wait for Interrupt","Execution of the WFI instruction can also be used to inform the hardware platform that suitable interrupts should preferentially be routed to this hart. WFI is available in all privileged modes, and optionally available to U-mode.",non_CSR_parameter,enum,high,False, +chunk_b65aadba,src/priv/machine.adoc,1997,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Mode Privileged Instructions > Wait for Interrupt","This instruction may raise an illegal-instruction exception when TW=1 in `mstatus`, as described in .",CSR_controlled,enum,high,False, +chunk_00a8dd91,src/priv/machine.adoc,2014,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Mode Privileged Instructions > Wait for Interrupt","Implementations are permitted to resume execution for any reason, even if an enabled interrupt has not become pending.",unknown,binary,high,False, +chunk_9c93ef29,src/priv/machine.adoc,2018,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Mode Privileged Instructions > Wait for Interrupt",The WFI instruction can also be executed when interrupts are disabled.,unknown,binary,high,False, +chunk_e5b652e9,src/priv/machine.adoc,2018,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Mode Privileged Instructions > Wait for Interrupt","The operation of WFI must be unaffected by the global interrupt bits in `mstatus` (MIE and SIE) and the delegation register `mideleg` (i.e., the hart must resume if a locally enabled interrupt becomes pending, even if it has been delegated to a less-privileged mode), but should honor the individual interrupt enables (e.g, MTIE) (i.e., implementations should avoid resuming the hart if the interrupt is pending but not individually enabled). WFI is also required to resume execution for locally enabled interrupts pending at any privilege level, regardless of the global interrupt enable at each privilege level.",CSR_controlled,binary,very_high,False, +chunk_df1342f6,src/priv/machine.adoc,2029,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Mode Privileged Instructions > Wait for Interrupt","If the event that causes the hart to resume execution does not cause an interrupt to be taken, execution will resume at `pc` + 4, and software must determine what action to take, including looping back to repeat the WFI if there was no actionable event.",SW_rule,binary,very_high,False, +chunk_25fda74a,src/priv/machine.adoc,2036,"Preamble > Machine-Level ISA, Version 1.13 > Machine-Mode Privileged Instructions > Custom SYSTEM Instructions","It is recommended that these instructions use bits 29:28 to designate the minimum required privilege mode, as do other SYSTEM instructions.",unknown,range,high,False, +chunk_1c8c97b6,src/priv/machine.adoc,2046,"Preamble > Machine-Level ISA, Version 1.13 > Reset",The `mstatus` fields MIE and MPRV are reset to 0.,CSR_controlled,binary,high,False, +chunk_186ccbca,src/priv/machine.adoc,2046,"Preamble > Machine-Level ISA, Version 1.13 > Reset","If little-endian memory accesses are supported, the `mstatus`/`mstatush` field MBE is reset to 0.",CSR_controlled,binary,high,False, +chunk_b8c74e12,src/priv/machine.adoc,2046,"Preamble > Machine-Level ISA, Version 1.13 > Reset",The `mcause` register is set to a value indicating the cause of the reset.,CSR_controlled,enum,high,False, +chunk_93700694,src/priv/machine.adoc,2046,"Preamble > Machine-Level ISA, Version 1.13 > Reset","Writable PMP registers’ A and L fields are set to 0, unless the platform mandates a different reset value for some PMP registers’ A and L fields.",CSR_controlled,binary,high,False, +chunk_480c0e35,src/priv/machine.adoc,2046,"Preamble > Machine-Level ISA, Version 1.13 > Reset","If the hypervisor extension is implemented, the `hgatp`.MODE and `vsatp`.MODE fields are reset to 0.",CSR_controlled,binary,high,False, +chunk_dd88cbd0,src/priv/machine.adoc,2046,"Preamble > Machine-Level ISA, Version 1.13 > Reset","If the Smrnmi extension is implemented, the `mnstatus`.NMIE field is reset to 0.",CSR_controlled,binary,high,False, +chunk_11c7f5e7,src/priv/machine.adoc,2046,"Preamble > Machine-Level ISA, Version 1.13 > Reset",No *WARL* field contains an illegal value.,CSR_controlled,enum,very_high,False, +chunk_eca283a6,src/priv/machine.adoc,2046,"Preamble > Machine-Level ISA, Version 1.13 > Reset","If the Zicfilp extension is implemented, the `mseccfg`.MLPE field is reset to 0.",unknown,binary,high,False, +chunk_b9ee0be9,src/priv/machine.adoc,2065,"Preamble > Machine-Level ISA, Version 1.13 > Reset","The `MML`, `MMWP`, and `RLB` fields of the `mseccfg` register are set to 0, unless the platform mandates a different reset value.",unknown,binary,high,False, +chunk_9a10caea,src/priv/machine.adoc,2068,"Preamble > Machine-Level ISA, Version 1.13 > Reset","The `mcause` values after reset have implementation-specific interpretation, but the value 0 should be returned on implementations that do not distinguish different reset conditions.",CSR_controlled,enum,high,False, +chunk_1a2848d5,src/priv/machine.adoc,2068,"Preamble > Machine-Level ISA, Version 1.13 > Reset",Implementations that distinguish different reset conditions should only use 0 to indicate the most complete reset.,non_CSR_parameter,enum,medium,False, +chunk_fa505870,src/priv/machine.adoc,2074,"Preamble > Machine-Level ISA, Version 1.13 > Reset",The `USEED` and `SSEED` fields of the `mseccfg` CSR must have defined reset values.,CSR_controlled,enum,very_high,False, +chunk_f3258bf2,src/priv/machine.adoc,2074,"Preamble > Machine-Level ISA, Version 1.13 > Reset",The system must not allow them to be in an undefined state after reset.,non_CSR_parameter,enum,very_high,False, +chunk_fa97c770,src/priv/machine.adoc,2081,"Preamble > Machine-Level ISA, Version 1.13 > Non-Maskable Interrupts","Non-maskable interrupts (NMIs) are only used for hardware error conditions, and cause an immediate jump to an implementation-defined NMI vector running in M-mode regardless of the state of a hart’s interrupt enable bits.",non_CSR_parameter,unknown,high,False, +chunk_712fbb13,src/priv/machine.adoc,2081,"Preamble > Machine-Level ISA, Version 1.13 > Non-Maskable Interrupts","The `mepc` register is written with the virtual address of the instruction that was interrupted, and `mcause` is set to a value indicating the source of the NMI.",CSR_controlled,enum,high,False, +chunk_54ad5d46,src/priv/machine.adoc,2081,"Preamble > Machine-Level ISA, Version 1.13 > Non-Maskable Interrupts",The NMI can thus overwrite state in an active machine-mode interrupt handler.,unknown,unknown,high,False, +chunk_653548de,src/priv/machine.adoc,2089,"Preamble > Machine-Level ISA, Version 1.13 > Non-Maskable Interrupts",The values written to `mcause` on an NMI are implementation-defined.,CSR_controlled,enum,high,False, +chunk_43254bed,src/priv/machine.adoc,2089,"Preamble > Machine-Level ISA, Version 1.13 > Non-Maskable Interrupts",The high Interrupt bit of `mcause` should be set to indicate that this was an interrupt.,CSR_controlled,enum,high,False, +chunk_21daabb2,src/priv/machine.adoc,2089,"Preamble > Machine-Level ISA, Version 1.13 > Non-Maskable Interrupts","An Exception Code of 0 is reserved to mean ""unknown cause"" and implementations that do not distinguish sources of NMIs via the `mcause` register should return 0 in the Exception Code.",CSR_controlled,enum,high,False, +chunk_4dc84b16,src/priv/machine.adoc,2129,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes","While many other architectures specify some PMAs in the virtual memory page tables and use the TLB to inform the pipeline of these properties, this approach injects platform-specific information into a virtualized layer and can cause system errors unless attributes are correctly initialized in each page-table entry for each physical memory region.",unknown,unknown,high,False, +chunk_c43827a6,src/priv/machine.adoc,2143,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes","To aid in system debugging, we strongly recommend that, where possible, RISC-V processors precisely trap physical memory accesses that fail PMA checks.",unknown,unknown,high,False, +chunk_b87799a4,src/priv/machine.adoc,2143,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes","Precisely trapped PMA violations manifest as instruction, load, or store access-fault exceptions, distinct from virtual-memory page-fault exceptions.",unknown,unknown,high,False, +chunk_2818e023,src/priv/machine.adoc,2143,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes","In this case, error responses from peripheral devices will be reported as imprecise bus-error interrupts.",unknown,unknown,high,False, +chunk_f64e8f25,src/priv/machine.adoc,2163,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes","PMAs must also be readable by software to correctly access certain devices or to correctly configure other hardware components that access memory, such as DMA engines.",SW_rule,enum,very_high,False, +chunk_9cf0e652,src/priv/machine.adoc,2163,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes","Some devices, particularly legacy buses, do not support discovery of PMAs and so will give error responses or time out if an unsupported access is attempted.",unknown,unknown,high,False, +chunk_cc33ae7e,src/priv/machine.adoc,2199,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Supported Access Type PMAs","Access types specify which access widths, from 8-bit byte to long multi-word burst, are supported, and also whether misaligned accesses are supported for each access width.",non_CSR_parameter,range,medium,False, +chunk_15791c2c,src/priv/machine.adoc,2221,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Atomicity PMAs > AMO PMA","For each level of support, naturally aligned AMOs of a given width are supported if the underlying memory region supports reads and writes of that width.",unknown,unknown,high,False, +chunk_ba6ed978,src/priv/machine.adoc,2221,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Atomicity PMAs > AMO PMA",Main memory and I/O regions may only support a subset or none of the processor-supported atomic operations.,non_CSR_parameter,enum,medium,False, +chunk_a9aff880,src/priv/machine.adoc,2276,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Misaligned Atomicity Granule PMA","This PMA, if present, specifies the size of a misaligned atomicity granule, a naturally aligned power-of-two number of bytes.",unknown,unknown,high,False, +chunk_69e8598b,src/priv/machine.adoc,2292,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Misaligned Atomicity Granule PMA","If a misaligned AMO accesses a region that does not specify a misaligned atomicity granule PMA, or if not all accessed bytes lie within the same misaligned atomicity granule, then an exception is raised.",non_CSR_parameter,unknown,high,False, +chunk_1f538eb5,src/priv/machine.adoc,2292,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Misaligned Atomicity Granule PMA","For regular loads and stores that access such a region or for which not all accessed bytes lie within the same atomicity granule, then either an exception is raised, or the access proceeds but is not guaranteed to be atomic.",non_CSR_parameter,enum,high,False, +chunk_27842136,src/priv/machine.adoc,2292,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Misaligned Atomicity Granule PMA","Implementations may raise access-fault exceptions instead of address-misaligned exceptions for some misaligned accesses, indicating the instruction should not be emulated by a trap handler.",non_CSR_parameter,enum,high,False, +chunk_d0db9795,src/priv/machine.adoc,2302,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Misaligned Atomicity Granule PMA","Vector memory accesses are also unaffected, so might execute non-atomically even when contained within a misaligned atomicity granule.",unknown,unknown,high,False, +chunk_2107401a,src/priv/machine.adoc,2325,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Memory-Ordering PMAs","Accesses by one hart to an I/O region are observable not only by other harts and bus mastering devices but also by the targeted I/O devices, and I/O regions may be accessed with either relaxed or strong ordering.",non_CSR_parameter,enum,medium,False, +chunk_e2552b54,src/priv/machine.adoc,2371,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Coherence and Cacheability PMAs","The cacheability of a memory region should not affect the software view of the region except for differences reflected in other PMAs, such as main memory versus I/O classification, memory ordering, supported accesses and atomic operations, and coherence.",SW_rule,enum,medium,False, +chunk_df341b31,src/priv/machine.adoc,2378,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Coherence and Cacheability PMAs","Where a platform supports configurable cacheability settings for a memory region, a platform-specific machine-mode routine will change the settings and flush caches if necessary, so the system is only incoherent during the transition between cacheability settings.",SW_rule,unknown,high,False, +chunk_5c7fec53,src/priv/machine.adoc,2378,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Coherence and Cacheability PMAs",This transitory state should not be visible to lower privilege levels.,non_CSR_parameter,enum,medium,False, +chunk_97d0b08a,src/priv/machine.adoc,2384,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Coherence and Cacheability PMAs","If a PMA indicates non-cacheability, then accesses to that region must be satisfied by the memory itself, not by any caches.",SW_rule,binary,very_high,False, +chunk_27164f05,src/priv/machine.adoc,2389,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Idempotency PMAs","If accesses are non-idempotent, i.e., there is potentially a side effect on any read or write access, then speculative or redundant accesses must be avoided.",non_CSR_parameter,binary,very_high,False, +chunk_3d3b8d47,src/priv/machine.adoc,2400,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Idempotency PMAs","For non-idempotent regions, implicit reads and writes must not be performed early or speculatively, with the following exceptions.",non_CSR_parameter,binary,very_high,False, +chunk_36b74aa7,src/priv/machine.adoc,2400,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Idempotency PMAs",The results of these additional reads may be used to satisfy subsequent early or speculative implicit reads.,non_CSR_parameter,enum,medium,False, +chunk_9cfc895a,src/priv/machine.adoc,2400,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Idempotency PMAs","The size of these naturally aligned power-of-2 regions is implementation-defined, but, for systems with page-based virtual memory, must not exceed the smallest supported page size.",non_CSR_parameter,enum,very_high,False, +chunk_02c83330,src/priv/machine.adoc,2418,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection","To support secure processing and contain faults, it is desirable to limit the physical addresses accessible by software running on a hart.",SW_rule,unknown,high,False, +chunk_cfb7ad97,src/priv/machine.adoc,2432,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection","PMP checks are applied to all accesses whose effective privilege mode is S or U, including instruction fetches and data accesses in S and U mode, and data accesses in M-mode when the MPRV bit in `mstatus` is set and the MPP field in `mstatus` contains S or U. PMP checks are also applied to page-table accesses for virtual-address translation, for which the effective privilege mode is S.",CSR_controlled,enum,high,False, +chunk_d07a7e9c,src/priv/machine.adoc,2432,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection","Optionally, PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset.",SW_rule,enum,medium,False, +chunk_fbcd883c,src/priv/machine.adoc,2432,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection","In effect, PMP can grant permissions to S and U modes, which by default have none, and can revoke permissions from M-mode, which by default has full permissions.",unknown,unknown,high,False, +chunk_66a4b598,src/priv/machine.adoc,2444,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection",PMP violations are always trapped precisely at the processor.,unknown,unknown,high,False, +chunk_39adcd66,src/priv/machine.adoc,2448,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs",PMP entries are described by an 8-bit configuration register and one MXLEN-bit address register.,non_CSR_parameter,range,high,False, +chunk_c7415812,src/priv/machine.adoc,2448,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs",Some PMP settings additionally use the address register associated with the preceding PMP entry.,unknown,unknown,high,False, +chunk_37be932e,src/priv/machine.adoc,2448,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs",Up to 64 PMP entries are supported.,unknown,unknown,high,False, +chunk_b0840b21,src/priv/machine.adoc,2448,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs","Implementations may implement zero, 16, or 64 PMP entries; the lowest-numbered PMP entries must be implemented first.",non_CSR_parameter,enum,very_high,False, +chunk_315d20eb,src/priv/machine.adoc,2448,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs",All PMP CSR fields are *WARL* and may be read-only zero. PMP CSRs are only accessible to M-mode.,CSR_controlled,binary,very_high,False, +chunk_d3babf96,src/priv/machine.adoc,2456,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs",The PMP configuration registers are densely packed into CSRs to minimize context-switch time.,CSR_controlled,enum,high,False, +chunk_b88f7218,src/priv/machine.adoc,2456,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs","For RV32, sixteen CSRs, `pmpcfg0`–`pmpcfg15`, hold the configurations `pmp0cfg`–`pmp63cfg` for the 64 PMP entries, as shown in .",CSR_controlled,enum,high,False, +chunk_c910668e,src/priv/machine.adoc,2456,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs","For RV64, eight even-numbered CSRs, `pmpcfg0`, `pmpcfg2`, …, `pmpcfg14`, hold the configurations for the 64 PMP entries, as shown in .",CSR_controlled,enum,high,False, +chunk_029134cb,src/priv/machine.adoc,2456,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs","For RV64, the odd-numbered configuration registers, `pmpcfg1`, `pmpcfg3`, …, `pmpcfg15`, are illegal.",CSR_controlled,enum,high,False, +chunk_c33146c3,src/priv/machine.adoc,2474,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs",The PMP address registers are CSRs named `pmpaddr0`-`pmpaddr63`.,CSR_controlled,enum,high,False, +chunk_b10d3bfe,src/priv/machine.adoc,2474,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs","Each PMP address register encodes bits 33-2 of a 34-bit physical address for RV32, as shown in .",non_CSR_parameter,range,high,False, +chunk_a7037147,src/priv/machine.adoc,2474,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs","For RV64, each PMP address register encodes bits 55-2 of a 56-bit physical address, as shown in .",non_CSR_parameter,range,high,False, +chunk_f3d4cf8f,src/priv/machine.adoc,2474,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs","Not all physical address bits may be implemented, and so the `pmpaddr` registers are *WARL*.",CSR_controlled,enum,very_high,False, +chunk_8f6c8459,src/priv/machine.adoc,2490,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs",shows the layout of a PMP configuration register.,unknown,unknown,high,False, +chunk_bb75a842,src/priv/machine.adoc,2490,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs","The R, W, and X bits, when set, indicate that the PMP entry permits read, write, and instruction execution, respectively.",unknown,unknown,high,False, +chunk_17fe049a,src/priv/machine.adoc,2490,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs","When one of these bits is clear, the corresponding access type is denied.",unknown,enum,high,False, +chunk_4fdb3d75,src/priv/machine.adoc,2490,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs","The R, W, and X fields form a collective *WARL* field for which the combinations with R=0 and W=1 are reserved.",CSR_controlled,enum,very_high,False, +chunk_e187dd03,src/priv/machine.adoc,2490,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs","The remaining two fields, A and L, are described in the following sections.",unknown,enum,high,False, +chunk_b7e0171b,src/priv/machine.adoc,2501,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs",Attempting to fetch an instruction from a PMP region that does not have execute permissions raises an instruction access-fault exception.,non_CSR_parameter,unknown,high,False, +chunk_044bc19c,src/priv/machine.adoc,2501,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs","Attempting to execute a load, load-reserved, or cache-block management instruction which accesses a physical address within a PMP region without read permissions raises a load access-fault exception.",non_CSR_parameter,unknown,high,False, +chunk_df8eacd0,src/priv/machine.adoc,2501,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs","Attempting to execute a store, store-conditional, AMO, or cache-block zero instruction which accesses a physical address within a PMP region without write permissions raises a store access-fault exception.",non_CSR_parameter,unknown,high,False, +chunk_b225f014,src/priv/machine.adoc,2514,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Address Matching",The A field in a PMP entry's configuration register encodes the address-matching mode of the associated PMP address register.,unknown,enum,high,False, +chunk_be99f1eb,src/priv/machine.adoc,2514,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Address Matching",The encoding of this field is shown in .,unknown,enum,high,False, +chunk_589b512e,src/priv/machine.adoc,2514,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Address Matching","When A=0, this PMP entry is disabled and matches no addresses.",unknown,binary,high,False, +chunk_2c0aad10,src/priv/machine.adoc,2514,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Address Matching","Two other address-matching modes are supported: naturally aligned power-of-2 regions (NAPOT), including the special case of naturally aligned four-byte regions (NA4); and the top boundary of an arbitrary range (TOR).",unknown,unknown,high,False, +chunk_1f3345ca,src/priv/machine.adoc,2514,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Address Matching",These modes support four-byte granularity.,unknown,unknown,high,False, +chunk_2b93d05a,src/priv/machine.adoc,2543,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Address Matching","NAPOT ranges make use of the low-order bits of the associated address register to encode the size of the range, as shown in .",unknown,unknown,high,False, +chunk_6cbd5943,src/priv/machine.adoc,2581,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Address Matching","If TOR is selected, the associated address register forms the top of the address range, and the preceding PMP address register forms the bottom of the address range.",unknown,enum,high,False, +chunk_e5722906,src/priv/machine.adoc,2581,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Address Matching","If PMP entry i's A field is set to TOR, the entry matches any address y such that `pmpaddr~i-1~`{le}y<``pmpaddr~i~`` (irrespective of the value of `pmpcfg~i-1~`).",CSR_controlled,enum,high,False, +chunk_e8eb7f06,src/priv/machine.adoc,2581,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Address Matching","If PMP entry 0's A field is set to TOR, zero is used for the lower bound, and so it matches any address `y Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Address Matching","Although the PMP mechanism supports regions as small as four bytes, platforms may specify coarser PMP regions.",non_CSR_parameter,enum,high,False, +chunk_ed876d35,src/priv/machine.adoc,2587,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Address Matching","In general, the PMP grain is 2^G+2^ bytes and must be the same across all PMP regions.",non_CSR_parameter,enum,very_high,False, +chunk_4fb93a2b,src/priv/machine.adoc,2587,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Address Matching","When G {ge} 1, the NA4 mode is not selectable.",unknown,enum,high,False, +chunk_292e2019,src/priv/machine.adoc,2587,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Address Matching","Although changing pmpcfg~i~.A[1] affects the value read from pmpaddr~i~, it does not affect the underlying value stored in that register—in particular, pmpaddr~i~[G-1] retains its original value when pmpcfg~i~.A is changed from NAPOT to TOR/OFF then back to NAPOT.",CSR_controlled,enum,high,False, +chunk_36f74c78,src/priv/machine.adoc,2607,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Locking and Privilege Mode",Locked PMP entries remain locked until the hart is reset.,unknown,unknown,high,False, +chunk_6aa5df8a,src/priv/machine.adoc,2607,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Locking and Privilege Mode","If PMP entry i is locked, writes to ``pmp``i``cfg`` and ``pmpaddr``i are ignored.",CSR_controlled,enum,high,False, +chunk_0876d10c,src/priv/machine.adoc,2607,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Locking and Privilege Mode","Additionally, if PMP entry i is locked and ``pmp``i``cfg.A`` is set to TOR, writes to ``pmpaddr``i-1 are ignored.",CSR_controlled,enum,high,False, +chunk_f77c4075,src/priv/machine.adoc,2614,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Locking and Privilege Mode","In addition to locking the PMP entry, the L bit indicates whether the R/W/X permissions are additionally enforced on M-mode accesses.",unknown,unknown,high,False, +chunk_2b3b76c0,src/priv/machine.adoc,2614,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Locking and Privilege Mode","When the L bit is set, these permissions are enforced for all privilege modes.",unknown,enum,high,False, +chunk_56ab5df8,src/priv/machine.adoc,2614,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Locking and Privilege Mode","When the L bit is clear, any M-mode access matching the PMP entry will succeed; the R/W/X permissions apply only to S and U modes.",unknown,unknown,high,False, +chunk_4a738f29,src/priv/machine.adoc,2623,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Priority and Matching Logic","On some implementations, misaligned loads, stores, and instruction fetches may be decomposed into multiple memory operations, some of which may succeed before an access-fault exception occurs, as described in the RVWMO specification. PMP checking is performed on each memory operation independently.",non_CSR_parameter,enum,high,False, +chunk_a77473e2,src/priv/machine.adoc,2623,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Priority and Matching Logic","In particular, a portion of a misaligned store that passes the PMP check may become visible, even if another portion fails the PMP check.",non_CSR_parameter,enum,high,False, +chunk_10ce2509,src/priv/machine.adoc,2632,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Priority and Matching Logic",PMP entries are statically prioritized.,unknown,unknown,high,False, +chunk_63aa1c7a,src/priv/machine.adoc,2632,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Priority and Matching Logic",The lowest-numbered PMP entry that matches any byte of a memory operation determines whether that operation succeeds or fails.,unknown,unknown,high,False, +chunk_56fef4bd,src/priv/machine.adoc,2632,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Priority and Matching Logic","The matching PMP entry must match all bytes of a memory operation, or the operation fails, irrespective of the L, R, W, and X bits.",non_CSR_parameter,enum,very_high,False, +chunk_d334ea0d,src/priv/machine.adoc,2641,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Priority and Matching Logic","If a PMP entry matches all bytes of a memory operation, then the L, R, W, and X bits determine whether the operation succeeds or fails.",unknown,unknown,high,False, +chunk_9f8880aa,src/priv/machine.adoc,2641,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Priority and Matching Logic","If the L bit is clear and the privilege mode of the access is M, the operation succeeds.",unknown,enum,high,False, +chunk_207b6df6,src/priv/machine.adoc,2641,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Priority and Matching Logic","Otherwise, if the L bit is set or the privilege mode of the access is S or U, then the operation succeeds only if the R, W, or X bit corresponding to the access type is set.",unknown,enum,high,False, +chunk_f8e9da60,src/priv/machine.adoc,2648,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Priority and Matching Logic","If no PMP entry matches an M-mode memory operation, the operation succeeds.",unknown,unknown,high,False, +chunk_a0fe55e7,src/priv/machine.adoc,2648,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Priority and Matching Logic","If no PMP entry matches an S-mode or U-mode memory operation, but at least one PMP entry is implemented, the operation fails.",unknown,range,high,False, +chunk_8eeaa6dd,src/priv/machine.adoc,2652,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Priority and Matching Logic","Failed memory operations generate an instruction, load, or store access-fault exception.",unknown,unknown,high,False, +chunk_4efc87e7,src/priv/machine.adoc,2652,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Priority and Matching Logic","An access-fault exception is generated if at least one memory operation generated by an instruction fails, though other memory operations generated by that instruction may succeed with visible side effects.",non_CSR_parameter,range,high,False, +chunk_74d14c90,src/priv/machine.adoc,2652,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Priority and Matching Logic","Notably, instructions that reference virtual memory are decomposed into multiple memory operations.",unknown,unknown,high,False, +chunk_fb9695f4,src/priv/machine.adoc,2664,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection and Paging","When paging is enabled, instructions that access virtual memory may result in multiple physical-memory accesses, including implicit references to the page tables.",non_CSR_parameter,binary,high,False, +chunk_9df68475,src/priv/machine.adoc,2672,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection and Paging",The PMP settings for the resulting physical address may be checked (and possibly cached) at any point between the address translation and the explicit memory access.,non_CSR_parameter,enum,medium,False, +chunk_fcd39486,src/priv/machine.adoc,2672,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection and Paging","Hence, when the PMP settings are modified, M-mode software must synchronize the PMP settings with the virtual memory system and any PMP or address-translation caches.",SW_rule,binary,very_high,False, +chunk_491400db,src/priv/machine.adoc,2672,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection and Paging","This is accomplished by executing an SFENCE.VMA instruction with rs1=`x0` and rs2=`x0`, after the PMP CSRs are written.",CSR_controlled,enum,high,False, +chunk_a3728ac9,src/priv/machine.adoc,2672,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection and Paging",See for additional synchronization requirements when the hypervisor extension is implemented.,SW_rule,unknown,high,False, +chunk_d385b92d,src/priv/machine.adoc,2687,"Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection and Paging","If page-based virtual memory is not implemented, memory accesses check the PMP settings synchronously, so no SFENCE.VMA is needed.",SW_rule,unknown,high,False, +chunk_b6092f08,src/priv/preface.adoc,233,Preamble > Preface,"Defined the `misa`.B field to reflect that the B extension has been implemented. * Defined the `misa`.V field to reflect that the V extension has been implemented. * Defined the RV32-only `medelegh` and `hedelegh` CSRs. * Defined the misaligned atomicity granule PMA, superseding the proposed Zam extension. * Allocated interrupt 13 for Sscofpmf LCOFI interrupt. * Defined hardware-error and software-check exception codes. * Specified synchronization requirements when changing the PBMTE and ADUE fields in `menvcfg` and `henvcfg`. * Exposed count-overflow interrupts to VS-mode via the Shlcofideleg extension. * Relaxed behavior of some HINTs when MXLEN > XLEN. * Defined the format of the memory-mapped `msip` registers.",CSR_controlled,enum,high,False, +chunk_b84b62b5,src/priv/preface.adoc,291,Preamble > Preface,"The previous specification implied that PPO rules other than fences and acquire/release annotations did not apply. * Constrained the LR/SC reservation set size and shape when using page-based virtual memory. * PMP changes require an SFENCE.VMA on any hart that implements page-based virtual memory, even if VM is not currently enabled. * Allowed for speculative updates of page table entry A bits. * Clarify that if the address-translation algorithm non-speculatively reaches a PTE in which a bit reserved for future standard use is set, a page-fault exception must be raised.",SW_rule,binary,very_high,False, +chunk_4bf4c453,src/priv/preface.adoc,310,Preamble > Preface,"Removed the N extension. * Defined the mandatory RV32-only CSR `mstatush`, which contains most of the same fields as the upper 32 bits of RV64’s `mstatus`. * Defined the mandatory CSR `mconfigptr`, which if nonzero contains the address of a configuration data structure. * Defined `mseccfg` and `mseccfgh` CSRs, which control the machine’s security configuration. * Defined `menvcfg`, `henvcfg`, and `senvcfg` CSRs (and RV32-only `menvcfgh` and `henvcfgh` CSRs), which control various characteristics of the execution environment. * Designated part of SYSTEM major opcode for custom use. * Permitted the unconditional delegation of less-privileged interrupts. * Added optional big-endian and bi-endian support. * Made priority of load/store/AMO address-misaligned exceptions implementation-defined relative to load/store/AMO page-fault and access-fault exceptions. * PMP reset values are now platform-defined. * An additional 48 optional PMP registers have been defined. * Slightly relaxed the atomicity requirement for A and D bit updates performed by the implementation. * Clarify the architectural behavior of address-translation caches * Added Sv57 and Sv57x4 address translation modes. * Software breakpoint exceptions are permitted to write either 0 or the `pc` to `xtval`. * Clarified that bare S-mode need not support the SFENCE.VMA instruction. * Specified relaxed constraints for implicit reads of non-idempotent regions. * Added the Svnapot Standard Extension, along with the N bit in Sv39, Sv48, and Sv57 PTEs. * Added the Svpbmt Standard Extension, along with the PBMT bits in Sv39, Sv48, and Sv57 PTEs. * Added the Svinval Standard Extension and associated instructions.",CSR_controlled,range,high,False, +chunk_e57d1083,src/priv/preface.adoc,399,Preamble > Preface,"The encoding space has been reserved and may be repurposed at a later date. * A mechanism to improve virtualization performance by trapping S-mode virtual-memory management operations has been added. * The Supervisor Binary Interface (SBI) chapter has been removed, so that it can be maintained as a separate specification.",non_CSR_parameter,enum,high,False, +chunk_efd41272,src/priv/preface.adoc,462,Preamble > Preface,Numerous additions and improvements to the commentary sections. * Change configuration string proposal to be use a search process that supports various formats including Device Tree String and flattened Device Tree. * Made `misa` optionally writable to support modifying base and supported ISA extensions. CSR address of `misa` changed. * Added description of debug mode and debug CSRs. * Added a hardware performance monitoring scheme.,CSR_controlled,enum,high,False, +chunk_6b04766d,src/priv/rationale.adoc,17,"Preamble > Historical Rationale for Extensions > ""Smepmp"" Extension for PMP Enhancements for memory access and execution prevention in Machine mode","Since a CSR for security and / or global PMP behavior settings is not available with the current spec, we needed to define a new `mseccfg` CSR.",CSR_controlled,enum,high,False, +chunk_935cb5e2,src/priv/rationale.adoc,17,"Preamble > Historical Rationale for Extensions > ""Smepmp"" Extension for PMP Enhancements for memory access and execution prevention in Machine mode",This new CSR will allow us to add further security configuration options in the future and also allow developers to verify the existence of the new mechanisms defined on this extension.,CSR_controlled,enum,high,False, +chunk_58464ad0,src/priv/rationale.adoc,19,"Preamble > Historical Rationale for Extensions > ""Smepmp"" Extension for PMP Enhancements for memory access and execution prevention in Machine mode","This is a waste of PMP rules and since it’s only needed during boot, ``mseccfg.RLB`` is a simple workaround that can be used temporarily and then disabled and locked down. + Also when ``mseccfg.MML`` is set, according to 4b it’s not possible to add a Shared-Region rule with executable privileges.",unknown,binary,high,False, +chunk_300be726,src/priv/rationale.adoc,19,"Preamble > Historical Rationale for Extensions > ""Smepmp"" Extension for PMP Enhancements for memory access and execution prevention in Machine mode","If developers / vendors have no use for such functionality, they should never set ``mseccfg.RLB`` and if possible hard-wire it to 0.",non_CSR_parameter,enum,high,False, +chunk_ac7e0ee8,src/priv/rationale.adoc,19,"Preamble > Historical Rationale for Extensions > ""Smepmp"" Extension for PMP Enhancements for memory access and execution prevention in Machine mode","In any case *RLB should be disabled and locked as soon as possible*. + + [IMPORTANT] Since PMP rules with a higher priority override rules with a lower priority, locked rules must precede non-locked rules.",non_CSR_parameter,binary,very_high,False, +chunk_8c7ab6c7,src/priv/rationale.adoc,34,"Preamble > Historical Rationale for Extensions > ""Smepmp"" Extension for PMP Enhancements for memory access and execution prevention in Machine mode",With the current spec M-mode can access any memory region unless restricted by a PMP rule with the ``pmpcfg.L`` bit set.,CSR_controlled,enum,high,False, +chunk_350815ba,src/priv/rationale.adoc,34,"Preamble > Historical Rationale for Extensions > ""Smepmp"" Extension for PMP Enhancements for memory access and execution prevention in Machine mode","Having the option to block anything by default, and use PMP as an allowlist for M-mode is considered a safer approach.",unknown,unknown,high,False, +chunk_3a4d7f68,src/priv/rationale.adoc,34,"Preamble > Historical Rationale for Extensions > ""Smepmp"" Extension for PMP Enhancements for memory access and execution prevention in Machine mode","This functionality may be used during the boot process or upon *PMP reset*, using initial register settings. +",non_CSR_parameter,enum,medium,False, +chunk_89dfbe07,src/priv/rationale.adoc,36,"Preamble > Historical Rationale for Extensions > ""Smepmp"" Extension for PMP Enhancements for memory access and execution prevention in Machine mode",The current dual meaning of the ``pmpcfg.L`` bit that marks a rule as Locked and *enforced* on all modes is neither flexible nor clean.,CSR_controlled,enum,high,False, +chunk_0342c8ec,src/priv/rationale.adoc,36,"Preamble > Historical Rationale for Extensions > ""Smepmp"" Extension for PMP Enhancements for memory access and execution prevention in Machine mode",With the introduction of Machine Mode Lock-down the ``pmpcfg.L`` bit distinguishes between rules that are *enforced* *only* in M-mode (M-mode-only) or *only* in S/U-modes (S/U-mode-only).,CSR_controlled,enum,high,False, +chunk_af1423d0,src/priv/rationale.adoc,36,"Preamble > Historical Rationale for Extensions > ""Smepmp"" Extension for PMP Enhancements for memory access and execution prevention in Machine mode","The rule locking becomes part of the definition of an M-mode-only rule, since when a rule is added in M mode, if not locked, can be modified or removed in a few instructions.",unknown,unknown,high,False, +chunk_2e78e7bf,src/priv/rationale.adoc,38,"Preamble > Historical Rationale for Extensions > ""Smepmp"" Extension for PMP Enhancements for memory access and execution prevention in Machine mode","This separation between M-mode-only and S/U-mode-only rules also allows us to distinguish which regions are to be used by processes in Machine mode (``pmpcfg.L 1``) and which by Supervisor or User mode processes (``pmpcfg.L 0``), in the same way the U bit on the Virtual Memory’s PTEs marks which Virtual Memory pages are to be used by User mode applications (U=1) and which by the Supervisor / OS (U=0).",CSR_controlled,enum,high,False, +chunk_34f5a83a,src/priv/rationale.adoc,38,"Preamble > Historical Rationale for Extensions > ""Smepmp"" Extension for PMP Enhancements for memory access and execution prevention in Machine mode","With this distinction in place we are able to implement memory access and execution prevention in M-mode for any physical memory region that is not M-mode-only. + An attacker that manages to tamper with a memory region used by S/U mode, even after successfully tricking a process running in M-mode to use or execute that region, will fail to perform a successful attack since that region will be S/U-mode-only hence any access when in M-mode will trigger an access exception. + +",unknown,unknown,high,False, +chunk_9b8de246,src/priv/rationale.adoc,44,"Preamble > Historical Rationale for Extensions > ""Smepmp"" Extension for PMP Enhancements for memory access and execution prevention in Machine mode","This is similar to the vDSO approach followed on Linux, that allows user space code to execute kernel code without having to perform a system call. + To make sure that shared data regions can’t be executed and shared code regions can’t be modified, the encoding changes the meaning of the ``pmpcfg.X bit``.",CSR_controlled,enum,high,False, +chunk_e6a2f20e,src/priv/rationale.adoc,44,"Preamble > Historical Rationale for Extensions > ""Smepmp"" Extension for PMP Enhancements for memory access and execution prevention in Machine mode","In case of shared data regions, with the exception of the ``pmpcfg.LRWX=1111`` encoding, the ``pmpcfg.X`` bit marks the capability of S/U-mode to write to that region, so it’s not possible to encode an executable shared data region.",CSR_controlled,enum,high,False, +chunk_f3468413,src/priv/rationale.adoc,44,"Preamble > Historical Rationale for Extensions > ""Smepmp"" Extension for PMP Enhancements for memory access and execution prevention in Machine mode","In case of shared code regions, the ``pmpcfg.X`` bit marks the capability of M-mode to read from that region, and since ``pmpcfg.RW=01`` is used for encoding the shared region, it’s not possible to encode a shared writable code region. + + + ..",CSR_controlled,enum,high,False, +chunk_7e181d60,src/priv/rationale.adoc,44,"Preamble > Historical Rationale for Extensions > ""Smepmp"" Extension for PMP Enhancements for memory access and execution prevention in Machine mode","Since we want to limit the attack surface of the system as much as possible, it makes sense to disallow any new code regions which may include malicious code, to be added/executed in M-mode.",non_CSR_parameter,enum,medium,False, +chunk_e0c0cd63,src/priv/rationale.adoc,55,"Preamble > Historical Rationale for Extensions > ""Smepmp"" Extension for PMP Enhancements for memory access and execution prevention in Machine mode","We are only using the encoding ``pmpcfg.RW=01`` together with ``mseccfg.MML``, if ``mseccfg.MML`` is not set the encoding remains usable for future use.",CSR_controlled,enum,high,False, +chunk_2ec682e0,src/priv/shcounterenw.adoc,3,"Preamble > Shcounterenw Extension for Counter-Enable Writability, Version 1.0","If the Shcounterenw extension is implemented, then for any `hpmcounter` that is not read-only zero, the corresponding bit in `hcounteren` must be writable.",CSR_controlled,binary,very_high,False, +chunk_e037e8ad,src/priv/shgatpa.adoc,3,"Preamble > Shgatpa Extension for Translation Mode Support, Version 1.0","If the Shgatpa extension is implemented, then for each supported virtual memory scheme SvNN supported in `satp`, the corresponding hgatp SvNNx4 mode must be supported.",CSR_controlled,enum,very_high,False, +chunk_0044086f,src/priv/shgatpa.adoc,3,"Preamble > Shgatpa Extension for Translation Mode Support, Version 1.0","Furthermore, the `hgatp` mode Bare must also be supported.",CSR_controlled,enum,very_high,False, +chunk_382de062,src/priv/shtvala.adoc,3,"Preamble > Shtvala Extension for Trap Value Reporting, Version 1.0","If the Shtvala extension is implemented, `htval` must be written with the faulting guest physical address in all circumstances permitted by the ISA.",non_CSR_parameter,binary,very_high,False, +chunk_43523cc0,src/priv/shvsatpa.adoc,3,"Preamble > Shvsatpa Extension for Translation Mode Support, Version 1.0","If the Shvsatpa extension is implemented, all translation modes supported in `satp` must be supported in `vsatp`.",CSR_controlled,enum,very_high,False, +chunk_ccce9266,src/priv/shvstvala.adoc,3,"Preamble > Shvstvala Extension for Trap Value Reporting, Version 1.0","If the Shvstvala extension is implemented, `vstval` must be written in all cases described in for `stval`.",CSR_controlled,enum,very_high,False, +chunk_3b1276de,src/priv/shvstvecd.adoc,3,"Preamble > Shvstvecd Extension for Direct Trap Vectoring, Version 1.0","If the Shvstvecd extension is implemented, then `vstvec.MODE` must be capable of holding the value 0 (Direct).",CSR_controlled,enum,very_high,False, +chunk_3c2beeae,src/priv/shvstvecd.adoc,3,"Preamble > Shvstvecd Extension for Direct Trap Vectoring, Version 1.0","Furthermore, when `vstvec.MODE`=Direct, `vstvec.BASE` must be capable of holding any valid four-byte-aligned address.",CSR_controlled,enum,very_high,False, +chunk_83134a3e,src/priv/smcdeleg.adoc,3,"Preamble > ""Smcdeleg/Ssccfg"" Counter Delegation Extensions, Version 1.0","Counters may be configured with differing scopes, in some cases counting events system-wide, while in others counting events on behalf of a single virtual machine or application.",non_CSR_parameter,enum,medium,False, +chunk_e74fe235,src/priv/smcdeleg.adoc,16,"Preamble > ""Smcdeleg/Ssccfg"" Counter Delegation Extensions, Version 1.0","These extensions also defines one new CSR, scountinhibit.",CSR_controlled,enum,high,False, +chunk_e4ca12e3,src/priv/smcdeleg.adoc,22,"Preamble > ""Smcdeleg/Ssccfg"" Counter Delegation Extensions, Version 1.0","For a Machine-level environment, extension *Smcdeleg* (‘Sm’ for Privileged architecture and Machine-level extension, ‘cdeleg’ for Counter Delegation) encompasses all added CSRs and all behavior modifications for a hart, over all privilege levels.",CSR_controlled,enum,high,False, +chunk_62671138,src/priv/smcdeleg.adoc,22,"Preamble > ""Smcdeleg/Ssccfg"" Counter Delegation Extensions, Version 1.0","For a Supervisor-level environment, extension *Ssccfg* (‘Ss’ for Privileged architecture and Supervisor-level extension, ‘ccfg’ for Counter Configuration) provides access to delegated counters, and to new supervisor-level state.For a RISC-V hardware platform, Smcdeleg and Ssccfg must always be implemented in tandem.",non_CSR_parameter,enum,very_high,False, +chunk_49857356,src/priv/smcdeleg.adoc,31,"Preamble > ""Smcdeleg/Ssccfg"" Counter Delegation Extensions, Version 1.0",The Smcdeleg and Ssccfg extensions both depend on the Sscsrind extension.,CSR_controlled,enum,high,False, +chunk_4aa7cee0,src/priv/smcdeleg.adoc,35,"Preamble > ""Smcdeleg/Ssccfg"" Counter Delegation Extensions, Version 1.0 > Counter Delegation",The `mcounteren` register allows M-mode to provide the next-lower privilege mode with read access to select counters.,CSR_controlled,enum,high,False, +chunk_dcb1006e,src/priv/smcdeleg.adoc,35,"Preamble > ""Smcdeleg/Ssccfg"" Counter Delegation Extensions, Version 1.0 > Counter Delegation","When the Smcdeleg/Ssccfg extensions are enabled (`menvcfg`.CDE=1), it further allows M-mode to delegate select counters to S-mode.",CSR_controlled,binary,high,False, +chunk_878ae6ef,src/priv/smcdeleg.adoc,38,"Preamble > ""Smcdeleg/Ssccfg"" Counter Delegation Extensions, Version 1.0 > Counter Delegation",The counter state accessible via alias CSRs is shown in the table below.,CSR_controlled,enum,high,False, +chunk_748f83d3,src/priv/smcdeleg.adoc,63,"Preamble > ""Smcdeleg/Ssccfg"" Counter Delegation Extensions, Version 1.0 > Counter Delegation",`hpmeventi` may represent a subset of the state accessed by the `mhpmeventi` register.,CSR_controlled,enum,high,False, +chunk_10c5066c,src/priv/smcdeleg.adoc,63,"Preamble > ""Smcdeleg/Ssccfg"" Counter Delegation Extensions, Version 1.0 > Counter Delegation","Specifically, if Sscofpmf is implemented, event selector bit 62 (MINH) is read-only 0 when accessed through `sireg*`.",CSR_controlled,enum,high,False, +chunk_5f477f61,src/priv/smcdeleg.adoc,66,"Preamble > ""Smcdeleg/Ssccfg"" Counter Delegation Extensions, Version 1.0 > Counter Delegation","Likewise, `cyclecfg` and `instretcfg` may represent a subset of the state accessed by the `mcyclecfg` and `minstretcfg` registers, respectively.",non_CSR_parameter,enum,medium,False, +chunk_ce83bbfc,src/priv/smcdeleg.adoc,66,"Preamble > ""Smcdeleg/Ssccfg"" Counter Delegation Extensions, Version 1.0 > Counter Delegation","If Smcntrpmf is implemented, counter configuration register bit 62 (MINH) is read-only 0 when accessed through `sireg*`.",CSR_controlled,unknown,high,False, +chunk_6f1ab629,src/priv/smcdeleg.adoc,69,"Preamble > ""Smcdeleg/Ssccfg"" Counter Delegation Extensions, Version 1.0 > Counter Delegation","If extension Smstateen is implemented, refer to extensions Smcsrind/Sscsrind () for how setting bit 60 of CSR `mstateen0` to zero prevents access to registers `siselect`, `sireg*`, `vsiselect`, and `vsireg*` from privileged modes less privileged than M-mode, and likewise how setting bit 60 of `hstateen0` to zero prevents access to `siselect` and `sireg*` (really `vsiselect` and `vsireg*`) from VS-mode.",CSR_controlled,enum,high,False, +chunk_f6f3bd57,src/priv/smcdeleg.adoc,76,"Preamble > ""Smcdeleg/Ssccfg"" Counter Delegation Extensions, Version 1.0 > Counter Delegation",The remaining rules of this section apply only when access to a CSR is not blocked by `mstateen0`[60] = 0 or `hstateen0`[60] = 0.,CSR_controlled,enum,high,False, +chunk_6db73c0a,src/priv/smcdeleg.adoc,79,"Preamble > ""Smcdeleg/Ssccfg"" Counter Delegation Extensions, Version 1.0 > Counter Delegation","While the privilege mode is M or S and `siselect` holds a value in the range 0x40-0x5F, illegal-instruction exceptions are raised for the following cases:",non_CSR_parameter,range,high,False, +chunk_fc355b31,src/priv/smcdeleg.adoc,83,"Preamble > ""Smcdeleg/Ssccfg"" Counter Delegation Extensions, Version 1.0 > Counter Delegation","attempts to access any `sireg*` when `menvcfg`.CDE = 0; * attempts to access `sireg3` or `sireg6`; * attempts to access `sireg4` or `sireg5` when XLEN = 64; * attempts to access `sireg*` when `siselect` = 0x41, or when the counter selected by `siselect` is not delegated to S-mode (the corresponding bit in `mcounteren` = 0).",CSR_controlled,enum,high,False, +chunk_c32f9869,src/priv/smcdeleg.adoc,94,"Preamble > ""Smcdeleg/Ssccfg"" Counter Delegation Extensions, Version 1.0 > Counter Delegation","If any extension upon which the underlying state depends is not implemented, an attempt from M or S mode to access the given state through `sireg*` raises an illegal-instruction exception.",non_CSR_parameter,unknown,high,False, +chunk_d610cf5e,src/priv/smcdeleg.adoc,98,"Preamble > ""Smcdeleg/Ssccfg"" Counter Delegation Extensions, Version 1.0 > Counter Delegation","If the hypervisor (H) extension is also implemented, then as specified by extensions Smcsrind/Sscsrind, a virtual-instruction exception is raised for attempts from VS-mode or VU-mode to directly access `vsiselect` or `vsireg*`, or attempts from VU-mode to access `siselect` or `sireg*`.",CSR_controlled,enum,high,False, +chunk_48900364,src/priv/smcdeleg.adoc,104,"Preamble > ""Smcdeleg/Ssccfg"" Counter Delegation Extensions, Version 1.0 > Counter Delegation","An attempt to access any `vsireg*` from M or S mode raises an illegal-instruction exception. * An attempt from VS-mode to access any `sireg*` (really `vsireg*`) raises an illegal-instruction exception if `menvcfg`.CDE = 0, or a virtual-instruction exception if `menvcfg`.CDE = 1.",CSR_controlled,enum,high,False, +chunk_fd5c0600,src/priv/smcdeleg.adoc,109,"Preamble > ""Smcdeleg/Ssccfg"" Counter Delegation Extensions, Version 1.0 > Counter Delegation > Supervisor Counter Inhibit (`scountinhibit`) Register","Smcdeleg/Ssccfg defines a new `scountinhibit` register, a masked alias of `mcountinhibit`.",unknown,unknown,high,False, +chunk_ca239e01,src/priv/smcdeleg.adoc,109,"Preamble > ""Smcdeleg/Ssccfg"" Counter Delegation Extensions, Version 1.0 > Counter Delegation > Supervisor Counter Inhibit (`scountinhibit`) Register","For counters delegated to S-mode, the associated `mcountinhibit` bits can be accessed via `scountinhibit`.For counters not delegated to S-mode, the associated bits in `scountinhibit` are read-only zero.",CSR_controlled,binary,high,False, +chunk_279d9af9,src/priv/smcdeleg.adoc,111,"Preamble > ""Smcdeleg/Ssccfg"" Counter Delegation Extensions, Version 1.0 > Counter Delegation > Supervisor Counter Inhibit (`scountinhibit`) Register","When `menvcfg`.CDE=0, attempts to access `scountinhibit` raise an illegal-instruction exception.",CSR_controlled,enum,high,False, +chunk_db81802b,src/priv/smcdeleg.adoc,111,"Preamble > ""Smcdeleg/Ssccfg"" Counter Delegation Extensions, Version 1.0 > Counter Delegation > Supervisor Counter Inhibit (`scountinhibit`) Register","When Supervisor Counter Delegation is enabled, attempts to access `scountinhibit` from VS-mode or VU-mode raise a virtual-instruction exception.",non_CSR_parameter,binary,high,False, +chunk_ecf8e9ed,src/priv/smcdeleg.adoc,118,"Preamble > ""Smcdeleg/Ssccfg"" Counter Delegation Extensions, Version 1.0 > Counter Delegation > Virtualizing `scountovf`","For implementations that support Smcdeleg/Ssccfg, Sscofpmf, and the H extension, when `menvcfg`.CDE=1, attempts to read `scountovf` from VS-mode or VU-mode raise a virtual-instruction exception.",CSR_controlled,enum,high,False, +chunk_c7ac1bbc,src/priv/smcdeleg.adoc,125,"Preamble > ""Smcdeleg/Ssccfg"" Counter Delegation Extensions, Version 1.0 > Counter Delegation > Virtualizing Local-Counter-Overflow Interrupts","For implementations that support Smcdeleg, Sscofpmf, and Smaia, the local-counter-overflow interrupt (LCOFI) bit (bit 13) in each of CSRs `mvip` and `mvien` is implemented and writable.",CSR_controlled,enum,high,False, +chunk_fd5d0c71,src/priv/smcdeleg.adoc,130,"Preamble > ""Smcdeleg/Ssccfg"" Counter Delegation Extensions, Version 1.0 > Counter Delegation > Virtualizing Local-Counter-Overflow Interrupts","For implementations that support Smcdeleg/Ssccfg, Sscofpmf, Smaia/Ssaia, and the H extension, the LCOFI bit (bit 13) in each of `hvip` and `hvien` is implemented and writable.",CSR_controlled,unknown,high,False, +chunk_d0c03ac9,src/priv/smcntrpmf.adoc,17,"Preamble > ""Smcntrpmf"" Cycle and Instret Privilege Mode Filtering, Version 1.0 > Introduction > CSRs > Machine Counter Configuration (`mcyclecfg`, `minstretcfg`) Registers","mcyclecfg and minstretcfg are 64-bit registers that configure privilege mode filtering for the cycle and instret counters, respectively.",non_CSR_parameter,range,high,False, +chunk_00dba3fc,src/priv/smcntrpmf.adoc,19,"Preamble > ""Smcntrpmf"" Cycle and Instret Privilege Mode Filtering, Version 1.0 > Introduction > CSRs > Machine Counter Configuration (`mcyclecfg`, `minstretcfg`) Registers","[cols=""^1,^1,^1,^1,^1,^1,^5"",stripes=even,options=""header""] | |63 |62 |61 |60 |59 |58 |57:0 |0 |MINH |SINH |UINH |VSINH |VUINH |WPRI |",CSR_controlled,enum,very_high,False, +chunk_18b409dc,src/priv/smcntrpmf.adoc,25,"Preamble > ""Smcntrpmf"" Cycle and Instret Privilege Mode Filtering, Version 1.0 > Introduction > CSRs > Machine Counter Configuration (`mcyclecfg`, `minstretcfg`) Registers","[cols=""15%,85%"",options=""header""] | | Field | Description | MINH |",unknown,enum,high,False, +chunk_e666e66f,src/priv/smcntrpmf.adoc,25,"Preamble > ""Smcntrpmf"" Cycle and Instret Privilege Mode Filtering, Version 1.0 > Introduction > CSRs > Machine Counter Configuration (`mcyclecfg`, `minstretcfg`) Registers","If set, then counting of events in M-mode is inhibited | SINH |",unknown,unknown,high,False, +chunk_38ac7f97,src/priv/smcntrpmf.adoc,25,"Preamble > ""Smcntrpmf"" Cycle and Instret Privilege Mode Filtering, Version 1.0 > Introduction > CSRs > Machine Counter Configuration (`mcyclecfg`, `minstretcfg`) Registers","If set, then counting of events in S/HS-mode is inhibited | UINH |",unknown,unknown,high,False, +chunk_6e5f5b35,src/priv/smcntrpmf.adoc,25,"Preamble > ""Smcntrpmf"" Cycle and Instret Privilege Mode Filtering, Version 1.0 > Introduction > CSRs > Machine Counter Configuration (`mcyclecfg`, `minstretcfg`) Registers","If set, then counting of events in U-mode is inhibited | VSINH |",unknown,unknown,high,False, +chunk_9ed49eda,src/priv/smcntrpmf.adoc,25,"Preamble > ""Smcntrpmf"" Cycle and Instret Privilege Mode Filtering, Version 1.0 > Introduction > CSRs > Machine Counter Configuration (`mcyclecfg`, `minstretcfg`) Registers","If set, then counting of events in VS-mode is inhibited | VUINH |",unknown,unknown,high,False, +chunk_d239895c,src/priv/smcntrpmf.adoc,25,"Preamble > ""Smcntrpmf"" Cycle and Instret Privilege Mode Filtering, Version 1.0 > Introduction > CSRs > Machine Counter Configuration (`mcyclecfg`, `minstretcfg`) Registers","If set, then counting of events in VU-mode is inhibited |",unknown,unknown,high,False, +chunk_d57e784f,src/priv/smcntrpmf.adoc,35,"Preamble > ""Smcntrpmf"" Cycle and Instret Privilege Mode Filtering, Version 1.0 > Introduction > CSRs > Machine Counter Configuration (`mcyclecfg`, `minstretcfg`) Registers","When all xINH bits are zero, event counting is enabled in all modes.",unknown,binary,high,False, +chunk_9762522c,src/priv/smcntrpmf.adoc,37,"Preamble > ""Smcntrpmf"" Cycle and Instret Privilege Mode Filtering, Version 1.0 > Introduction > CSRs > Machine Counter Configuration (`mcyclecfg`, `minstretcfg`) Registers","For each bit in 61:58, if the associated privilege mode is not implemented, the bit is read-only zero.",CSR_controlled,binary,high,False, +chunk_3554f327,src/priv/smcntrpmf.adoc,39,"Preamble > ""Smcntrpmf"" Cycle and Instret Privilege Mode Filtering, Version 1.0 > Introduction > CSRs > Machine Counter Configuration (`mcyclecfg`, `minstretcfg`) Registers","For RV32, bits 63:32 of mcyclecfg can be accessed via the mcyclecfgh CSR, and bits 63:32 of minstretcfg can be accessed via the minstretcfgh CSR.",CSR_controlled,enum,high,False, +chunk_22201705,src/priv/smcntrpmf.adoc,41,"Preamble > ""Smcntrpmf"" Cycle and Instret Privilege Mode Filtering, Version 1.0 > Introduction > CSRs > Machine Counter Configuration (`mcyclecfg`, `minstretcfg`) Registers",The content of these registers may be accessible from Supervisor level if the Smcdeleg/Ssccfg extensions are implemented.,non_CSR_parameter,enum,high,False, +chunk_f10a10c9,src/priv/smcntrpmf.adoc,48,"Preamble > ""Smcntrpmf"" Cycle and Instret Privilege Mode Filtering, Version 1.0 > Introduction > Counter Behavior","Mode transition operations (traps and trap returns) may take multiple clock cycles, and the change of privilege mode may be reported as occurring in any one of those cycles (possibly different for each occurrence of a trap or trap return).",non_CSR_parameter,enum,high,False, +chunk_12eecd33,src/priv/smcntrpmf.adoc,51,"Preamble > ""Smcntrpmf"" Cycle and Instret Privilege Mode Filtering, Version 1.0 > Introduction > Counter Behavior","There are two types of instructions that can affect a privilege mode change: instructions that cause synchronous exceptions to a more privileged mode, and xRET instructions that return to a less privileged mode.",unknown,enum,high,False, +chunk_34a84a41,src/priv/smcntrpmf.adoc,51,"Preamble > ""Smcntrpmf"" Cycle and Instret Privilege Mode Filtering, Version 1.0 > Introduction > Counter Behavior","The latter do retire, and should increment instret only if the originating privilege mode is not inhibited.",non_CSR_parameter,enum,high,False, +chunk_99412fe5,src/priv/smcsrind.adoc,5,"Preamble > ""Smcsrind/Sscsrind"" Indirect CSR Access, Version 1.0 > Introduction","Smcsrind/Sscsrind is an ISA extension that extends the indirect CSR access mechanism originally defined as part of the https://github.com/riscv/riscv-aia[[.underline]Smaia/Ssaia extensions], in order to make it available for use by other extensions without creating an unnecessary dependence on Smaia/Ssaia.",CSR_controlled,enum,high,False, +chunk_2dcada5e,src/priv/smcsrind.adoc,13,"Preamble > ""Smcsrind/Sscsrind"" Indirect CSR Access, Version 1.0 > Introduction",It provides a means to access an array of registers via CSRs without requiring allocation of large chunks of the limited CSR address space.,CSR_controlled,enum,high,False, +chunk_442f8c71,src/priv/smcsrind.adoc,16,"Preamble > ""Smcsrind/Sscsrind"" Indirect CSR Access, Version 1.0 > Introduction","It enables software to access each of an array of registers by index, without requiring a switch statement with a case for each register.",SW_rule,unknown,high,False, +chunk_410c7637,src/priv/smcsrind.adoc,19,"Preamble > ""Smcsrind/Sscsrind"" Indirect CSR Access, Version 1.0 > Introduction","The machine-level extension *Smcsrind* encompasses all added CSRs and all behavior modifications for a hart, over all privilege levels.",CSR_controlled,enum,high,False, +chunk_7a181ac2,src/priv/smcsrind.adoc,19,"Preamble > ""Smcsrind/Sscsrind"" Indirect CSR Access, Version 1.0 > Introduction","For a supervisor-level environment, extension *Sscsrind* is essentially the same as Smcsrind except excluding the machine-level CSRs and behavior not directly visible to supervisor level.",CSR_controlled,enum,high,False, +chunk_8b8b93ed,src/priv/smcsrind.adoc,29,"Preamble > ""Smcsrind/Sscsrind"" Indirect CSR Access, Version 1.0 > Introduction > Machine-level CSRs","[width=""100%"",cols=""15%,12%,12%,15%,46%"",options=""header"",] | |*Number* |*Privilege* |*Width* |*Name* |*Description* |0x350 |MRW |XLEN |`miselect` |Machine indirect register select |0x351 |MRW |XLEN |`mireg` |Machine indirect register alias |0x352 |MRW |XLEN |`mireg2` |Machine indirect register alias 2 |0x353 |MRW |XLEN |`mireg3` |Machine indirect register alias 3 |0x355 |MRW |XLEN |`mireg4` |Machine indirect register alias 4 |0x356 |MRW |XLEN |`mireg5` |Machine indirect register alias 5 |0x357 |MRW |XLEN |`mireg6` |Machine indirect register alias 6 |",unknown,enum,high,False, +chunk_4807eaa9,src/priv/smcsrind.adoc,41,"Preamble > ""Smcsrind/Sscsrind"" Indirect CSR Access, Version 1.0 > Introduction > Machine-level CSRs",The CSRs listed in the table above provide a window for accessing register state indirectly.,CSR_controlled,enum,high,False, +chunk_a42124f7,src/priv/smcsrind.adoc,41,"Preamble > ""Smcsrind/Sscsrind"" Indirect CSR Access, Version 1.0 > Introduction > Machine-level CSRs","The value of `miselect` determines which register is accessed upon read or write of each of the machine indirect alias CSRs (`mireg*`). `miselect` value ranges are allocated to dependent extensions, which specify the register state accessible via each `miregi` register, for each `miselect` value. `miselect` is a WARL register.",CSR_controlled,enum,very_high,False, +chunk_1a8ce64a,src/priv/smcsrind.adoc,50,"Preamble > ""Smcsrind/Sscsrind"" Indirect CSR Access, Version 1.0 > Introduction > Machine-level CSRs",The `miselect` register implements at least enough bits to support all implemented `miselect` values (corresponding to the implemented extensions that utilize `miselect`/`mireg*` to indirectly access register state).,unknown,range,high,False, +chunk_e777efac,src/priv/smcsrind.adoc,50,"Preamble > ""Smcsrind/Sscsrind"" Indirect CSR Access, Version 1.0 > Introduction > Machine-level CSRs",The `miselect` register may be read-only zero if there are no extensions implemented that utilize it.,non_CSR_parameter,binary,high,False, +chunk_0ee28202,src/priv/smcsrind.adoc,56,"Preamble > ""Smcsrind/Sscsrind"" Indirect CSR Access, Version 1.0 > Introduction > Machine-level CSRs","Values of `miselect` with the most-significant bit set (bit XLEN - 1 = 1) are designated only for custom use, presumably for accessing custom registers through the alias CSRs.",CSR_controlled,enum,high,False, +chunk_6c4d9909,src/priv/smcsrind.adoc,56,"Preamble > ""Smcsrind/Sscsrind"" Indirect CSR Access, Version 1.0 > Introduction > Machine-level CSRs",Values of `miselect` with the most-significant bit clear are designated only for standard use and are reserved until allocated to a standard architecture extension.,unknown,enum,high,False, +chunk_3f2cfa85,src/priv/smcsrind.adoc,56,"Preamble > ""Smcsrind/Sscsrind"" Indirect CSR Access, Version 1.0 > Introduction > Machine-level CSRs","If XLEN is changed, the most-significant bit of `miselect` moves to the new position, retaining its value from before.",unknown,enum,high,False, +chunk_af8c65b2,src/priv/smcsrind.adoc,65,"Preamble > ""Smcsrind/Sscsrind"" Indirect CSR Access, Version 1.0 > Introduction > Machine-level CSRs","The behavior upon accessing `mireg*` from M-mode, while `miselect` holds a value that is not implemented, is UNSPECIFIED.",non_CSR_parameter,enum,high,False, +chunk_28d8c52c,src/priv/smcsrind.adoc,69,"Preamble > ""Smcsrind/Sscsrind"" Indirect CSR Access, Version 1.0 > Introduction > Machine-level CSRs","Attempts to access `mireg*` while `miselect` holds a number in an allocated and implemented range results in a specific behavior that, for each combination of `miselect` and `miregi`, is defined by the extension to which the `miselect` value is allocated.",non_CSR_parameter,enum,high,False, +chunk_99378fd8,src/priv/smcsrind.adoc,80,"Preamble > ""Smcsrind/Sscsrind"" Indirect CSR Access, Version 1.0 > Introduction > Supervisor-level CSRs","[width=""100%"",cols=""15%,12%,12%,15%,46%"",options=""header"",] | |*Number* |*Privilege* |*Width* |*Name* |*Description* |0x150 |SRW |XLEN |`siselect` |Supervisor indirect register select |0x151 |SRW |XLEN |`sireg` |Supervisor indirect register alias |0x152 |SRW |XLEN |`sireg2` |Supervisor indirect register alias 2 |0x153 |SRW |XLEN |`sireg3` |Supervisor indirect register alias 3 |0x155 |SRW |XLEN |`sireg4` |Supervisor indirect register alias 4 |0x156 |SRW |XLEN |`sireg5` |Supervisor indirect register alias 5 |0x157 |SRW |XLEN |`sireg6` |Supervisor indirect register alias 6 |",unknown,enum,high,False, +chunk_c6334109,src/priv/smcsrind.adoc,92,"Preamble > ""Smcsrind/Sscsrind"" Indirect CSR Access, Version 1.0 > Introduction > Supervisor-level CSRs",The CSRs in the table above are required if S-mode is implemented.,CSR_controlled,enum,high,False, +chunk_01318e78,src/priv/smcsrind.adoc,94,"Preamble > ""Smcsrind/Sscsrind"" Indirect CSR Access, Version 1.0 > Introduction > Supervisor-level CSRs",The `siselect` register will support the value range 0..0xFFF at a minimum. A future extension may define a value range outside of this minimum range.,non_CSR_parameter,range,high,False, +chunk_ec84c31f,src/priv/smcsrind.adoc,94,"Preamble > ""Smcsrind/Sscsrind"" Indirect CSR Access, Version 1.0 > Introduction > Supervisor-level CSRs",Only if such an extension is implemented will `siselect` be required to support larger values.,unknown,enum,high,False, +chunk_da50edfe,src/priv/smcsrind.adoc,99,"Preamble > ""Smcsrind/Sscsrind"" Indirect CSR Access, Version 1.0 > Introduction > Supervisor-level CSRs","Values of `siselect` with the most-significant bit set (bit XLEN - 1 = 1) are designated only for custom use, presumably for accessing custom registers through the alias CSRs.",CSR_controlled,enum,high,False, +chunk_fee5dcb5,src/priv/smcsrind.adoc,99,"Preamble > ""Smcsrind/Sscsrind"" Indirect CSR Access, Version 1.0 > Introduction > Supervisor-level CSRs",Values of `siselect` with the most-significant bit clear are designated only for standard use and are reserved until allocated to a standard architecture extension.,unknown,enum,high,False, +chunk_f5e7c146,src/priv/smcsrind.adoc,99,"Preamble > ""Smcsrind/Sscsrind"" Indirect CSR Access, Version 1.0 > Introduction > Supervisor-level CSRs","If XLEN is changed, the most-significant bit of `siselect` moves to the new position, retaining its value from before.",unknown,enum,high,False, +chunk_19c0635f,src/priv/smcsrind.adoc,109,"Preamble > ""Smcsrind/Sscsrind"" Indirect CSR Access, Version 1.0 > Introduction > Supervisor-level CSRs","The behavior upon accessing `sireg*` from M-mode or S-mode, while `siselect` holds a value that is not implemented at supervisor level, is UNSPECIFIED.",non_CSR_parameter,enum,high,False, +chunk_3572442b,src/priv/smcsrind.adoc,113,"Preamble > ""Smcsrind/Sscsrind"" Indirect CSR Access, Version 1.0 > Introduction > Supervisor-level CSRs","Otherwise, attempts to access `sireg*` from M-mode or S-mode while `siselect` holds a number in a standard-defined and implemented range result in specific behavior that, for each combination of `siselect` and `siregi`, is defined by the extension to which the `siselect` value is allocated.",unknown,enum,high,False, +chunk_55e2d6ea,src/priv/smcsrind.adoc,132,"Preamble > ""Smcsrind/Sscsrind"" Indirect CSR Access, Version 1.0 > Introduction > Virtual Supervisor-level CSRs","[width=""100%"",cols=""15%,12%,12%,15%,46%"",options=""header"",] | |*Number* |*Privilege* |*Width* |*Name* |*Description* |0x250 |HRW |XLEN |`vsiselect` |Virtual supervisor indirect register select",unknown,enum,high,False, +chunk_0d3ddfcb,src/priv/smcsrind.adoc,138,"Preamble > ""Smcsrind/Sscsrind"" Indirect CSR Access, Version 1.0 > Introduction > Virtual Supervisor-level CSRs",|0x251 |HRW |XLEN |`vsireg` |Virtual supervisor indirect register alias,unknown,unknown,high,False, +chunk_f151bffa,src/priv/smcsrind.adoc,140,"Preamble > ""Smcsrind/Sscsrind"" Indirect CSR Access, Version 1.0 > Introduction > Virtual Supervisor-level CSRs",|0x252 |HRW |XLEN |`vsireg2` |Virtual supervisor indirect register alias 2,unknown,unknown,high,False, +chunk_e02e17c8,src/priv/smcsrind.adoc,142,"Preamble > ""Smcsrind/Sscsrind"" Indirect CSR Access, Version 1.0 > Introduction > Virtual Supervisor-level CSRs",|0x253 |HRW |XLEN |`vsireg3` |Virtual supervisor indirect register alias 3,unknown,unknown,high,False, +chunk_e246e3d7,src/priv/smcsrind.adoc,144,"Preamble > ""Smcsrind/Sscsrind"" Indirect CSR Access, Version 1.0 > Introduction > Virtual Supervisor-level CSRs",|0x255 |HRW |XLEN |`vsireg4` |Virtual supervisor indirect register alias 4,unknown,unknown,high,False, +chunk_50427e6b,src/priv/smcsrind.adoc,146,"Preamble > ""Smcsrind/Sscsrind"" Indirect CSR Access, Version 1.0 > Introduction > Virtual Supervisor-level CSRs",|0x256 |HRW |XLEN |`vsireg5` |Virtual supervisor indirect register alias 5,unknown,unknown,high,False, +chunk_dae53d26,src/priv/smcsrind.adoc,148,"Preamble > ""Smcsrind/Sscsrind"" Indirect CSR Access, Version 1.0 > Introduction > Virtual Supervisor-level CSRs",|0x257 |HRW |XLEN |`vsireg6` |Virtual supervisor indirect register alias 6 |,unknown,unknown,high,False, +chunk_0aed0a37,src/priv/smcsrind.adoc,151,"Preamble > ""Smcsrind/Sscsrind"" Indirect CSR Access, Version 1.0 > Introduction > Virtual Supervisor-level CSRs",The CSRs in the table above are required if the hypervisor extension is implemented.,CSR_controlled,enum,high,False, +chunk_1e9a6115,src/priv/smcsrind.adoc,151,"Preamble > ""Smcsrind/Sscsrind"" Indirect CSR Access, Version 1.0 > Introduction > Virtual Supervisor-level CSRs","These VS CSRs all match supervisor CSRs, and substitute for those supervisor CSRs when executing in a virtual machine (in VS-mode or VU-mode).",CSR_controlled,enum,high,False, +chunk_bb5e326c,src/priv/smcsrind.adoc,156,"Preamble > ""Smcsrind/Sscsrind"" Indirect CSR Access, Version 1.0 > Introduction > Virtual Supervisor-level CSRs",The `vsiselect` register will support the value range 0..0xFFF at a minimum. A future extension may define a value range outside of this minimum range.,non_CSR_parameter,range,high,False, +chunk_d82fd6b3,src/priv/smcsrind.adoc,156,"Preamble > ""Smcsrind/Sscsrind"" Indirect CSR Access, Version 1.0 > Introduction > Virtual Supervisor-level CSRs",Only if such an extension is implemented will `vsiselect` be required to support larger values.,unknown,enum,high,False, +chunk_4e5ad7f5,src/priv/smcsrind.adoc,161,"Preamble > ""Smcsrind/Sscsrind"" Indirect CSR Access, Version 1.0 > Introduction > Virtual Supervisor-level CSRs","Values of `vsiselect` with the most-significant bit set (bit XLEN - 1 = 1) are designated only for custom use, presumably for accessing custom registers through the alias CSRs.",CSR_controlled,enum,high,False, +chunk_a048db28,src/priv/smcsrind.adoc,161,"Preamble > ""Smcsrind/Sscsrind"" Indirect CSR Access, Version 1.0 > Introduction > Virtual Supervisor-level CSRs",Values of `vsiselect` with the most-significant bit clear are designated only for standard use and are reserved until allocated to a standard architecture extension.,unknown,enum,high,False, +chunk_8229a054,src/priv/smcsrind.adoc,161,"Preamble > ""Smcsrind/Sscsrind"" Indirect CSR Access, Version 1.0 > Introduction > Virtual Supervisor-level CSRs","If XLEN is changed, the most-significant bit of `vsiselect` moves to the new position, retaining its value from before.",unknown,enum,high,False, +chunk_f3121074,src/priv/smcsrind.adoc,171,"Preamble > ""Smcsrind/Sscsrind"" Indirect CSR Access, Version 1.0 > Introduction > Virtual Supervisor-level CSRs","For alias CSRs `sireg*` and `vsireg*`, the hypervisor extension’s usual rules for when to raise a virtual-instruction exception (based on whether an instruction is HS-qualified) are not applicable.",CSR_controlled,enum,high,False, +chunk_f67ac4da,src/priv/smcsrind.adoc,171,"Preamble > ""Smcsrind/Sscsrind"" Indirect CSR Access, Version 1.0 > Introduction > Virtual Supervisor-level CSRs","The rules given in this section for `sireg` and `vsireg` apply instead, unless overridden by the requirements specified in the section below, which take precedence over this section when extension Smstateen is also implemented.",unknown,unknown,high,False, +chunk_69b8f6cf,src/priv/smcsrind.adoc,179,"Preamble > ""Smcsrind/Sscsrind"" Indirect CSR Access, Version 1.0 > Introduction > Virtual Supervisor-level CSRs","A virtual-instruction exception is raised for attempts from VS-mode or VU-mode to directly access `vsiselect` or `vsireg*`, or attempts from VU-mode to access `siselect` or `sireg*`.",non_CSR_parameter,enum,high,False, +chunk_dd05e6ac,src/priv/smcsrind.adoc,182,"Preamble > ""Smcsrind/Sscsrind"" Indirect CSR Access, Version 1.0 > Introduction > Virtual Supervisor-level CSRs","The behavior upon accessing `vsireg*` from M-mode or HS-mode, or accessing `sireg*` (really `vsireg*`) from VS-mode, while `vsiselect` holds a value that is not implemented at HS level, is UNSPECIFIED.",non_CSR_parameter,enum,high,False, +chunk_223ce912,src/priv/smcsrind.adoc,184,"Preamble > ""Smcsrind/Sscsrind"" Indirect CSR Access, Version 1.0 > Introduction > Virtual Supervisor-level CSRs","Otherwise, while `vsiselect` holds a number in a standard-defined and implemented range, attempts to access `vsireg*` from a sufficiently privileged mode, or to access `sireg*` (really `vsireg*`) from VS-mode, result in specific behavior that, for each combination of `vsiselect` and `vsiregi`, is defined by the extension to which the `vsiselect` value is allocated.",unknown,enum,high,False, +chunk_7c91d130,src/priv/smcsrind.adoc,193,"Preamble > ""Smcsrind/Sscsrind"" Indirect CSR Access, Version 1.0 > Introduction > Virtual Supervisor-level CSRs","Like `siselect` and `sireg*`, the widths of `vsiselect` and `vsireg*` are always the current XLEN rather than VSXLEN.",unknown,enum,high,False, +chunk_9e12b56b,src/priv/smcsrind.adoc,203,"Preamble > ""Smcsrind/Sscsrind"" Indirect CSR Access, Version 1.0 > Introduction > Access control by the state-enable CSRs","If extension Smstateen is implemented together with Smcsrind, bit 60 of state-enable register `mstateen0` controls access to `siselect`, `sireg*`, `vsiselect`, and `vsireg*`.",CSR_controlled,enum,high,False, +chunk_2f75b3b7,src/priv/smcsrind.adoc,203,"Preamble > ""Smcsrind/Sscsrind"" Indirect CSR Access, Version 1.0 > Introduction > Access control by the state-enable CSRs","When `mstateen0`[60]=0, an attempt to access one of these CSRs from a privilege mode less privileged than M-mode results in an illegal-instruction exception.",CSR_controlled,enum,high,False, +chunk_43fca7cc,src/priv/smcsrind.adoc,203,"Preamble > ""Smcsrind/Sscsrind"" Indirect CSR Access, Version 1.0 > Introduction > Access control by the state-enable CSRs","As always, the state-enable CSRs do not affect the accessibility of any state when in M-mode, only in less privileged modes.",CSR_controlled,enum,high,False, +chunk_b5d92640,src/priv/smcsrind.adoc,203,"Preamble > ""Smcsrind/Sscsrind"" Indirect CSR Access, Version 1.0 > Introduction > Access control by the state-enable CSRs","For more explanation, see the documentation for extension Smstateen in .",unknown,unknown,high,False, +chunk_887c1d5a,src/priv/smcsrind.adoc,212,"Preamble > ""Smcsrind/Sscsrind"" Indirect CSR Access, Version 1.0 > Introduction > Access control by the state-enable CSRs","Other extensions may specify that certain mstateen bits control access to registers accessed indirectly through `siselect` + `sireg*`, and/or `vsiselect` + `vsireg*`.",non_CSR_parameter,enum,high,False, +chunk_58994864,src/priv/smcsrind.adoc,220,"Preamble > ""Smcsrind/Sscsrind"" Indirect CSR Access, Version 1.0 > Introduction > Access control by the state-enable CSRs","If the hypervisor extension is implemented, the same bit is defined also in hypervisor CSR `hstateen0`, but controls access to only `siselect` and `sireg*` (really `vsiselect` and `vsireg*`), which is the state potentially accessible to a virtual machine executing in VS or VU-mode.",CSR_controlled,enum,high,False, +chunk_29894ed4,src/priv/smcsrind.adoc,220,"Preamble > ""Smcsrind/Sscsrind"" Indirect CSR Access, Version 1.0 > Introduction > Access control by the state-enable CSRs","When `hstateen0`[60]=0 and `mstateen0`[60]=1, all attempts from VS or VU-mode to access `siselect` or `sireg*` raise a virtual-instruction exception, not an illegal-instruction exception, regardless of the value of `vsiselect` or any other mstateen bit.",non_CSR_parameter,enum,high,False, +chunk_93de1157,src/priv/smcsrind.adoc,230,"Preamble > ""Smcsrind/Sscsrind"" Indirect CSR Access, Version 1.0 > Introduction > Access control by the state-enable CSRs",Extension Ssstateen is defined as the supervisor-level view of Smstateen.,unknown,unknown,high,False, +chunk_5fc36007,src/priv/smcsrind.adoc,230,"Preamble > ""Smcsrind/Sscsrind"" Indirect CSR Access, Version 1.0 > Introduction > Access control by the state-enable CSRs","Therefore, the combination of Sscsrind and Ssstateen incorporates the bit defined above for `hstateen0` but not that for `mstateen0`, since machine-level CSRs are not visible to supervisor level.",CSR_controlled,enum,high,False, +chunk_f9b020e1,src/priv/smctr.adoc,4,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0","Control flow transfers refer to jump instructions (including function calls and returns), taken branch instructions, traps, and trap returns.",unknown,unknown,high,False, +chunk_790bd387,src/priv/smctr.adoc,4,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0","Profiling tools, such as Linux perf, collect control transfer history when sampling software execution, thereby enabling tools, like AutoFDO, to identify hot paths for optimization.",SW_rule,unknown,high,False, +chunk_41eae867,src/priv/smctr.adoc,12,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0","Recorded transfers are inserted at the write pointer, which is then incremented, while older recorded transfers may be overwritten once the buffer is full.",non_CSR_parameter,enum,medium,False, +chunk_e153672e,src/priv/smctr.adoc,14,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0","The CTR buffer is accessible through an indirect CSR interface, such that software can specify which logical entry in the buffer it wishes to read or write.",CSR_controlled,enum,high,False, +chunk_1f1c0f5c,src/priv/smctr.adoc,16,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0","The machine-level extension, *Smctr*, encompasses all newly added Control Status Registers (CSRs), instructions, and behavior modifications for a hart across all privilege levels.",CSR_controlled,enum,high,False, +chunk_a8861305,src/priv/smctr.adoc,18,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0",Smctr and Ssctr depend on both the implementation of S-mode and the Sscsrind extension.,CSR_controlled,enum,high,False, +chunk_ba0955c4,src/priv/smctr.adoc,24,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`)",The `mctrctl` register is a 64-bit read/write register that enables and configures the CTR capability.,CSR_controlled,range,high,False, +chunk_bb8c826e,src/priv/smctr.adoc,68,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`)",|RASEMU |Enables RAS (Return Address Stack) Emulation Mode.,unknown,unknown,high,False, +chunk_a96a8a01,src/priv/smctr.adoc,70,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`)",|MTE |Enables recording of traps to M-mode when M=0.,unknown,unknown,high,False, +chunk_2592483c,src/priv/smctr.adoc,72,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`)",|STE |Enables recording of traps to S-mode when S=0.,unknown,unknown,high,False, +chunk_be3c8962,src/priv/smctr.adoc,74,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`)",|BPFRZ |Set `sctrstatus`.FROZEN on a breakpoint exception that traps to M-mode or S-mode.,unknown,unknown,high,False, +chunk_af59dbda,src/priv/smctr.adoc,76,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`)",|LCOFIFRZ |Set `sctrstatus`.FROZEN on local-counter-overflow interrupt (LCOFI) that traps to M-mode or S-mode.,unknown,unknown,high,False, +chunk_45f46ff7,src/priv/smctr.adoc,78,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`)",|EXCINH |Inhibit recording of exceptions.,unknown,unknown,high,False, +chunk_79b24ba1,src/priv/smctr.adoc,80,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`)",|INTRINH |Inhibit recording of interrupts.,unknown,unknown,high,False, +chunk_11ad52e8,src/priv/smctr.adoc,82,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`)",|TRETINH |Inhibit recording of trap returns.,unknown,unknown,high,False, +chunk_ddcaabb5,src/priv/smctr.adoc,84,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`)",|NTBREN |Enable recording of not-taken branches.,unknown,unknown,high,False, +chunk_6280ad1c,src/priv/smctr.adoc,86,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`)",|TKBRINH |Inhibit recording of taken branches.,unknown,unknown,high,False, +chunk_43b14103,src/priv/smctr.adoc,88,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`)",|INDCALLINH |Inhibit recording of indirect calls.,unknown,unknown,high,False, +chunk_ad2ce281,src/priv/smctr.adoc,90,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`)",|DIRCALLINH |Inhibit recording of direct calls.,unknown,unknown,high,False, +chunk_92691a1d,src/priv/smctr.adoc,92,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`)",|INDJMPINH |Inhibit recording of indirect jumps (without linkage).,unknown,unknown,high,False, +chunk_128826e0,src/priv/smctr.adoc,94,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`)",|DIRJMPINH |Inhibit recording of direct jumps (without linkage).,unknown,unknown,high,False, +chunk_87cd7f1d,src/priv/smctr.adoc,96,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`)",|CORSWAPINH |Inhibit recording of co-routine swaps.,unknown,unknown,high,False, +chunk_672bad5c,src/priv/smctr.adoc,98,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`)",|RETINH |Inhibit recording of function returns.,unknown,unknown,high,False, +chunk_9c2c23c5,src/priv/smctr.adoc,100,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`)",|INDLJMPINH |Inhibit recording of other indirect jumps (with linkage).,unknown,unknown,high,False, +chunk_253b70fc,src/priv/smctr.adoc,102,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`)",|DIRLJMPINH |Inhibit recording of other direct jumps (with linkage).,unknown,unknown,high,False, +chunk_65789fe1,src/priv/smctr.adoc,102,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`)",The value 0 must correspond to standard behavior.,non_CSR_parameter,enum,very_high,False, +chunk_6be88f73,src/priv/smctr.adoc,106,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`)","-- All fields are optional except for M, S, U, and BPFRZ.",unknown,enum,high,False, +chunk_70cc9fe4,src/priv/smctr.adoc,106,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`)","All unimplemented fields are read-only 0, while all implemented fields are writable.",CSR_controlled,enum,high,False, +chunk_09dd034b,src/priv/smctr.adoc,106,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`)","If the Sscofpmf extension is implemented, LCOFIFRZ must be writable. --",non_CSR_parameter,binary,very_high,False, +chunk_ea73c3e5,src/priv/smctr.adoc,113,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Control Register (`sctrctl`)",The `sctrctl` register provides supervisor mode access to a subset of `mctrctl`.,unknown,unknown,high,False, +chunk_b0efef86,src/priv/smctr.adoc,115,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Control Register (`sctrctl`)",Bits 2 and 9 in `sctrctl` are read-only 0.,CSR_controlled,unknown,high,False, +chunk_207f07ec,src/priv/smctr.adoc,115,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Control Register (`sctrctl`)","As a result, the M and MTE fields in `mctrctl` are not accessible through `sctrctl`.",unknown,enum,high,False, +chunk_7d718fb6,src/priv/smctr.adoc,115,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Control Register (`sctrctl`)",All other `mctrctl` fields are accessible through `sctrctl`.,unknown,enum,high,False, +chunk_d61a1e7b,src/priv/smctr.adoc,119,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Virtual Supervisor Control Transfer Records Control Register (`vsctrctl`)","If the H extension is implemented, the `vsctrctl` register is a 64-bit read/write register that is VS-mode's version of supervisor register `sctrctl`.",CSR_controlled,range,high,False, +chunk_ad34e144,src/priv/smctr.adoc,119,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Virtual Supervisor Control Transfer Records Control Register (`vsctrctl`)","When V=1, `vsctrctl` substitutes for the usual `sctrctl`, so instructions that normally read or modify `sctrctl` actually access `vsctrctl` instead.",unknown,unknown,high,False, +chunk_b21b52f2,src/priv/smctr.adoc,154,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Virtual Supervisor Control Transfer Records Control Register (`vsctrctl`)",The optional fields implemented in `vsctrctl` should match those implemented in `sctrctl`. |,non_CSR_parameter,enum,high,False, +chunk_70a0279e,src/priv/smctr.adoc,167,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Virtual Supervisor Control Transfer Records Control Register (`vsctrctl`)","[NOTE] Unlike the CTR status register or the CTR entry registers, the CTR control register has a VS-mode version.",unknown,unknown,high,False, +chunk_c2a13761,src/priv/smctr.adoc,175,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Depth Register (`sctrdepth`)",The 32-bit `sctrdepth` register specifies the depth of the CTR buffer.,non_CSR_parameter,range,high,False, +chunk_87032c87,src/priv/smctr.adoc,207,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Depth Register (`sctrdepth`)",The depth of the CTR buffer dictates the number of entries to which the hardware records transfers.,unknown,unknown,high,False, +chunk_9761bce1,src/priv/smctr.adoc,207,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Depth Register (`sctrdepth`)","For a depth of N, the hardware records transfers to entries 0..N-1.",unknown,unknown,high,False, +chunk_25a75b38,src/priv/smctr.adoc,207,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Depth Register (`sctrdepth`)",All read as '0' and are read-only when the selected entry is in the range N to 255.,unknown,range,high,False, +chunk_65865305,src/priv/smctr.adoc,207,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Depth Register (`sctrdepth`)","When the depth is increased, the newly accessible entries contain unspecified but legal values.",non_CSR_parameter,unknown,high,False, +chunk_ba33e58d,src/priv/smctr.adoc,209,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Depth Register (`sctrdepth`)",It is implementation-specific which DEPTH value(s) are supported. |,non_CSR_parameter,unknown,high,False, +chunk_eee848d0,src/priv/smctr.adoc,212,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Depth Register (`sctrdepth`)","Attempts to access `sctrdepth` from VS-mode or VU-mode raise a virtual-instruction exception, unless CTR state enable access restrictions apply.",non_CSR_parameter,unknown,high,False, +chunk_1fe7b524,src/priv/smctr.adoc,214,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Depth Register (`sctrdepth`)","[NOTE] It is expected that operating systems (OSs) will access `sctrdepth` only at boot, to select the maximum supported depth value.",SW_rule,range,high,False, +chunk_5eda4df6,src/priv/smctr.adoc,214,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Depth Register (`sctrdepth`)","More frequent accesses may result in reduced performance in virtualization scenarios, as a result of traps from VS-mode incurred.",non_CSR_parameter,enum,high,False, +chunk_8bfca76c,src/priv/smctr.adoc,219,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Depth Register (`sctrdepth`)","There may be scenarios where software chooses to operate on only a subset of the entries, to reduce overhead.",SW_rule,enum,high,False, +chunk_e5b4be85,src/priv/smctr.adoc,219,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Depth Register (`sctrdepth`)","In such cases tools may choose to read only the lower entries, and OSs may choose to save/restore only on the lower entries while using SCTRCLR to clear the others.",non_CSR_parameter,enum,high,False, +chunk_8c6f0d48,src/priv/smctr.adoc,221,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Depth Register (`sctrdepth`)",The value in configurable depth lies in supporting VM migration.,unknown,unknown,high,False, +chunk_fbc6879f,src/priv/smctr.adoc,221,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Depth Register (`sctrdepth`)","It is expected that a platform spec may specify that one or more CTR depth values must be supported. A hypervisor may wish to restrict guests to using one of these required depths, in order to ensure that such guests can be migrated to any system that complies with the platform spec.",SW_rule,enum,very_high,False, +chunk_b85d17aa,src/priv/smctr.adoc,221,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Depth Register (`sctrdepth`)",The trapping behavior specified for VS-mode accesses to `sctrdepth` ensures that the hypervisor can impose such restrictions.,SW_rule,unknown,high,False, +chunk_09c5ec6b,src/priv/smctr.adoc,226,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Status Register (`sctrstatus`)",The 32-bit `sctrstatus` register grants access to CTR status information and is updated by the hardware whenever CTR is active. CTR is active when the current privilege mode is enabled for recording and CTR is not frozen.,non_CSR_parameter,binary,high,False, +chunk_867243fd,src/priv/smctr.adoc,239,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Status Register (`sctrstatus`)","For a given CTR depth (where depth = 2^(DEPTH+4)^), WRPTR wraps to 0 on an increment when the value matches depth-1, and to depth-1 on a decrement when the value is 0.",unknown,unknown,high,False, +chunk_82899a2a,src/priv/smctr.adoc,239,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Status Register (`sctrstatus`)","On depth changes, WRPTR holds an unspecified but legal value. |FROZEN |Inhibit transfer recording.",non_CSR_parameter,unknown,high,False, +chunk_39b3c0b6,src/priv/smctr.adoc,248,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Status Register (`sctrstatus`)",Undefined bits in `sctrstatus` are WPRI.,CSR_controlled,enum,very_high,False, +chunk_31a4bac6,src/priv/smctr.adoc,248,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Status Register (`sctrstatus`)","Status fields may be added by future extensions, and software should ignore but preserve any fields that it does not recognize.",SW_rule,enum,high,False, +chunk_dec9d6be,src/priv/smctr.adoc,251,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Status Register (`sctrstatus`)","[NOTE] Logical entry 0, accessed via `sireg*` when `siselect`=0x200, is always the physical buffer entry preceding the WRPTR entry.",unknown,enum,high,False, +chunk_a6f13db6,src/priv/smctr.adoc,251,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Status Register (`sctrstatus`)","More generally, the physical buffer entry Y associated with logical entry X (X < depth) can be determined using the formula Y = (WRPTR - X - 1) % depth, where depth = 2^(DEPTH+4)^.",unknown,unknown,high,False, +chunk_b2664905,src/priv/smctr.adoc,251,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Status Register (`sctrstatus`)","Software may wish to ensure that CTR is inactive before performing a read-modify-write, by ensuring that either `sctrstatus`.FROZEN=1, or that the current privilege mode is not enabled for recording.",SW_rule,binary,high,False, +chunk_60fba317,src/priv/smctr.adoc,261,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Status Register (`sctrstatus`)","When restoring CTR state, `sctrstatus` should be written before CTR entry state is restored.",non_CSR_parameter,enum,high,False, +chunk_b8770ade,src/priv/smctr.adoc,264,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Status Register (`sctrstatus`)",[NOTE] Exposing the WRPTR provides a more efficient means for synthesizing CTR entries.,unknown,unknown,high,False, +chunk_b0d2ef9d,src/priv/smctr.adoc,264,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Status Register (`sctrstatus`)","If a qualified control transfer is emulated, the emulator can simply increment the WRPTR, then write the synthesized record to logical entry 0.",unknown,unknown,high,False, +chunk_7bfd925b,src/priv/smctr.adoc,264,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Status Register (`sctrstatus`)","If a qualified function return is emulated while RASEMU=1, the emulator can clear `ctrsource`.V for logical entry 0, then decrement the WRPTR.",unknown,unknown,high,False, +chunk_ce238fb8,src/priv/smctr.adoc,269,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Status Register (`sctrstatus`)",Exposing the WRPTR may also allow support for Linux perf's https://lwn.net/Articles/802821[[.underline]stack stitching] capability.,SW_rule,enum,high,False, +chunk_26b49422,src/priv/smctr.adoc,272,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Status Register (`sctrstatus`)","If, in the future, it becomes desirable to remove this dependency, an extension could add `mctrdepth` and `mctrstatus` CSRs that reflect the same state as `sctrdepth` and `sctrstatus`, respectively.",CSR_controlled,enum,high,False, +chunk_477db704,src/priv/smctr.adoc,272,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Status Register (`sctrstatus`)","Further, such an extension should make CTR entries accessible via `miselect`/`mireg*`.",non_CSR_parameter,enum,high,False, +chunk_613a7fc9,src/priv/smctr.adoc,280,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers","Control transfer records are stored in a CTR buffer, such that each buffer entry stores information about a single transfer.",unknown,unknown,high,False, +chunk_a7259bee,src/priv/smctr.adoc,280,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers",The CTR buffer entries are logically accessed via the indirect register access mechanism defined by the Sscsrind extension.,CSR_controlled,enum,high,False, +chunk_520ac0ce,src/priv/smctr.adoc,280,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers",The `siselect` index range 0x200 through 0x2FF is reserved for CTR logical entries 0 through 255.,unknown,enum,high,False, +chunk_9d5b277b,src/priv/smctr.adoc,280,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers","When `siselect` holds a value in this range, `sireg` provides access to `ctrsource`, `sireg2` provides access to `ctrtarget`, and `sireg3` provides access to `ctrdata`. `sireg4`, `sireg5`, and `sireg6` are read-only 0.",unknown,enum,high,False, +chunk_26bc344e,src/priv/smctr.adoc,282,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers","When `vsiselect` holds a value in 0x200..0x2FF, the `vsireg*` registers provide access to the same CTR entry register state as the analogous `sireg*` registers.",unknown,enum,high,False, +chunk_d786fc3c,src/priv/smctr.adoc,282,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers",There is not a separate set of entry registers for V=1.,unknown,unknown,high,False, +chunk_f308fee0,src/priv/smctr.adoc,284,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers",See for cases where CTR accesses from S-mode and VS-mode may be restricted.,non_CSR_parameter,enum,high,False, +chunk_7b5b4b73,src/priv/smctr.adoc,288,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers > Control Transfer Record Source Register (`ctrsource`)","The `ctrsource` register contains the source program counter, which is the `pc` of the recorded control transfer instruction, or the epc of the recorded trap.",unknown,unknown,high,False, +chunk_8e2ff478,src/priv/smctr.adoc,288,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers > Control Transfer Record Source Register (`ctrsource`)","The valid (V) bit is set by the hardware when a transfer is recorded in the selected CTR buffer entry, and implies that data in `ctrsource`, `ctrtarget`, and `ctrdata` is valid for this entry.",unknown,enum,high,False, +chunk_ef76ea5c,src/priv/smctr.adoc,290,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers > Control Transfer Record Source Register (`ctrsource`)",`ctrsource` is an MXLEN-bit WARL register that must be able to hold all valid virtual or physical addresses that can serve as a `pc`.,CSR_controlled,range,very_high,False, +chunk_6939fe47,src/priv/smctr.adoc,290,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers > Control Transfer Record Source Register (`ctrsource`)",It need not be able to hold any invalid addresses; implementations may convert an invalid address into a valid address that the register is capable of holding.,non_CSR_parameter,enum,high,False, +chunk_1e3b0fcf,src/priv/smctr.adoc,290,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers > Control Transfer Record Source Register (`ctrsource`)","When XLEN < MXLEN, both explicit writes (by software) and implicit writes (for recorded transfers) will be zero-extended.",SW_rule,enum,high,False, +chunk_9fddb3ae,src/priv/smctr.adoc,302,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers > Control Transfer Record Source Register (`ctrsource`)","[NOTE] CTR entry registers are defined as MXLEN, despite the `xireg*` CSRs used to access them being XLEN, to ensure that entries recorded in RV64 are not truncated, as a result of CSR Width Modulation, on a transition to RV32.",CSR_controlled,enum,high,False, +chunk_765711c1,src/priv/smctr.adoc,310,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers > Control Transfer Record Target Register (`ctrtarget`)",The `ctrtarget` register contains the target (destination) program counter of the recorded transfer.,unknown,unknown,high,False, +chunk_31d4fd6a,src/priv/smctr.adoc,310,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers > Control Transfer Record Target Register (`ctrtarget`)","For a not-taken branch, `ctrtarget` holds the PC of the next sequential instruction following the branch.",unknown,unknown,high,False, +chunk_b3b5f3d1,src/priv/smctr.adoc,310,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers > Control Transfer Record Target Register (`ctrtarget`)",The optional MISP bit is set by the hardware when the recorded transfer is an instruction whose target or taken/not-taken direction was mispredicted by the branch predictor. MISP is read-only 0 when not implemented.,CSR_controlled,unknown,high,False, +chunk_15e34b2f,src/priv/smctr.adoc,318,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers > Control Transfer Record Target Register (`ctrtarget`)",`ctrtarget` is an MXLEN-bit WARL register that must be able to hold all valid virtual or physical addresses that can serve as a `pc`.,CSR_controlled,range,very_high,False, +chunk_70281a0a,src/priv/smctr.adoc,318,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers > Control Transfer Record Target Register (`ctrtarget`)",It need not be able to hold any invalid addresses; implementations may convert an invalid address into a valid address that the register is capable of holding.,non_CSR_parameter,enum,high,False, +chunk_7fbe9ac5,src/priv/smctr.adoc,318,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers > Control Transfer Record Target Register (`ctrtarget`)","When XLEN < MXLEN, both explicit writes (by software) and implicit writes (by recorded transfers) will be zero-extended.",SW_rule,enum,high,False, +chunk_9eca8f29,src/priv/smctr.adoc,333,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers > Control Transfer Record Metadata Register (`ctrdata`)",The `ctrdata` register contains metadata for the recorded transfer.,unknown,unknown,high,False, +chunk_53b2689d,src/priv/smctr.adoc,333,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers > Control Transfer Record Metadata Register (`ctrdata`)","This register must be implemented, though all fields within it are optional.",non_CSR_parameter,enum,very_high,False, +chunk_abfacf16,src/priv/smctr.adoc,333,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers > Control Transfer Record Metadata Register (`ctrdata`)",Unimplemented fields are read-only 0. `ctrdata` is a 64-bit register.,CSR_controlled,range,high,False, +chunk_8f50de3e,src/priv/smctr.adoc,350,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers > Control Transfer Record Metadata Register (`ctrdata`)",Implementations that do not support this field will report 0. |WARL,CSR_controlled,enum,very_high,False, +chunk_1d7a1b92,src/priv/smctr.adoc,361,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers > Control Transfer Record Metadata Register (`ctrdata`)","|CC[15:0] |Cycle Count, composed of the Cycle Count Exponent (CCE, in CC[15:12]) and Cycle Count Mantissa (CCM, in CC[11:0]).",unknown,unknown,high,False, +chunk_f115fcb6,src/priv/smctr.adoc,366,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers > Control Transfer Record Metadata Register (`ctrdata`)",Undefined bits in `ctrdata` are WPRI.,CSR_controlled,enum,very_high,False, +chunk_8738f8a6,src/priv/smctr.adoc,366,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers > Control Transfer Record Metadata Register (`ctrdata`)","Undefined bits must be implemented as read-only 0, unless a is implemented and enabled.",CSR_controlled,binary,very_high,False, +chunk_84b7ff90,src/priv/smctr.adoc,388,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Instructions > Supervisor CTR Clear Instruction",The SCTRCLR instruction performs the following operations:,unknown,unknown,high,False, +chunk_6f530c6d,src/priv/smctr.adoc,393,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Instructions > Supervisor CTR Clear Instruction","Any read of `ctrsource`, `ctrtarget`, or `ctrdata` that follows SCTRCLR, such that it precedes the next qualified control transfer, will return the value 0.",unknown,unknown,high,False, +chunk_a8cef291,src/priv/smctr.adoc,393,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Instructions > Supervisor CTR Clear Instruction","Further, the first recorded transfer following SCTRCLR will have `ctrdata`.CCV=0.",unknown,unknown,high,False, +chunk_95dbb71b,src/priv/smctr.adoc,395,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Instructions > Supervisor CTR Clear Instruction","SCTRCLR raises an illegal-instruction exception in U-mode, and a virtual-instruction exception in VU-mode, unless CTR state enable access restrictions apply.",non_CSR_parameter,unknown,high,False, +chunk_fcaad9d8,src/priv/smctr.adoc,399,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > State Enable Access Control","When Smstateen is implemented, the `mstateen0`.CTR bit controls access to CTR register state from privilege modes less privileged than M-mode.",non_CSR_parameter,enum,high,False, +chunk_252b4e51,src/priv/smctr.adoc,399,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > State Enable Access Control","When `mstateen0`.CTR=1, accesses to CTR register state behave as described in and above, while SCTRCLR behaves as described in .",unknown,unknown,high,False, +chunk_afa970fa,src/priv/smctr.adoc,399,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > State Enable Access Control","When `mstateen0`.CTR=0 and the privilege mode is less privileged than M-mode, the following operations raise an illegal-instruction exception:",non_CSR_parameter,enum,high,False, +chunk_d5a87d45,src/priv/smctr.adoc,401,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > State Enable Access Control","Attempts to access `sctrctl`, `vsctrctl`, `sctrdepth`, or `sctrstatus` * Attempts to access `sireg*` when `siselect` is in 0x200..0x2FF, or `vsireg*` when `vsiselect` is in 0x200..0x2FF * Execution of the SCTRCLR instruction",unknown,enum,high,False, +chunk_ea199b0b,src/priv/smctr.adoc,405,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > State Enable Access Control","When `mstateen0`.CTR=0, qualified control transfers executed in privilege modes less privileged than M-mode will continue to implicitly update entry registers and `sctrstatus`.",unknown,enum,high,False, +chunk_64b89ea3,src/priv/smctr.adoc,407,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > State Enable Access Control","If the H extension is implemented and `mstateen0`.CTR=1, the `hstateen0`.CTR bit controls access to supervisor CTR state when V=1.",non_CSR_parameter,unknown,high,False, +chunk_e9e1bc82,src/priv/smctr.adoc,407,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > State Enable Access Control","This state includes `sctrctl` (really `vsctrctl`), `sctrstatus`, and `sireg*` (really `vsireg*`) when `siselect` (really `vsiselect`) is in 0x200..0x2FF. `hstateen0`.CTR is read-only 0 when `mstateen0`.CTR=0.",unknown,enum,high,False, +chunk_08871923,src/priv/smctr.adoc,409,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > State Enable Access Control","When `mstateen0`.CTR=1 and `hstateen0`.CTR=1, VS-mode accesses to supervisor CTR state behave as described in and above, while SCTRCLR behaves as described in .",unknown,unknown,high,False, +chunk_8bfcdb23,src/priv/smctr.adoc,409,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > State Enable Access Control","When `mstateen0`.CTR=1 and `hstateen0`.CTR=0, both VS-mode accesses to supervisor CTR state and VS-mode execution of SCTRCLR raise a virtual-instruction exception.",non_CSR_parameter,unknown,high,False, +chunk_2cb0a9b1,src/priv/smctr.adoc,411,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > State Enable Access Control",[NOTE] `sctrdepth` is not included in the above list of supervisor CTR state controlled by `hstateen0`.CTR since accesses to `sctrdepth` from VS-mode raise a virtual-instruction exception regardless of the value of `hstateen0`.CTR.,non_CSR_parameter,enum,high,False, +chunk_5a1159ee,src/priv/smctr.adoc,417,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > State Enable Access Control","When `hstateen0`.CTR=0, qualified control transfers executed while V=1 will continue to implicitly update entry registers and `sctrstatus`.",unknown,unknown,high,False, +chunk_b4bf0e99,src/priv/smctr.adoc,419,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > State Enable Access Control",[NOTE] See for how bit 60 in `mstateen0` and `hstateen0` can also restrict access to `sireg*`/`siselect` and `vsireg*`/`vsiselect` from privilege modes less privileged than M-mode.,unknown,enum,high,False, +chunk_c341addb,src/priv/smctr.adoc,425,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > State Enable Access Control",[NOTE] Implementations that support Smctr/Ssctr but not Smstateen/Ssstateen may observe reduced performance.,non_CSR_parameter,enum,high,False, +chunk_3b94ebfc,src/priv/smctr.adoc,425,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > State Enable Access Control","Without Smstateen/Ssstateen, a hypervisor is required to save/restore guest CTR state on every context switch.",SW_rule,unknown,high,False, +chunk_578499bf,src/priv/smctr.adoc,433,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior",CTR records qualified control transfers.,unknown,unknown,high,False, +chunk_48846170,src/priv/smctr.adoc,433,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior",Control transfers are qualified if they meet the following criteria:,unknown,unknown,high,False, +chunk_e5afe181,src/priv/smctr.adoc,435,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior",The current privilege mode is enabled * The transfer type is not inhibited * `sctrstatus`.FROZEN is not set * The transfer completes/retires,unknown,binary,high,False, +chunk_60de82fb,src/priv/smctr.adoc,440,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior",Such qualified transfers update the at logical entry 0.,unknown,unknown,high,False, +chunk_a121a929,src/priv/smctr.adoc,440,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior","As a result, older entries are pushed down the stack; the record previously in logical entry 0 moves to logical entry 1, the record in logical entry 1 moves to logical entry 2, and so on.",unknown,unknown,high,False, +chunk_fb6ed0bb,src/priv/smctr.adoc,440,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior","If the CTR buffer is full, the oldest recorded entry (previously at entry depth-1) is lost.",unknown,unknown,high,False, +chunk_5af3bb8c,src/priv/smctr.adoc,442,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior","Recorded transfers will set the `ctrsource`.V bit to 1, and will update all implemented record fields.",unknown,enum,high,False, +chunk_a52d9144,src/priv/smctr.adoc,452,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions",Transfers that change the privilege mode are a special case.,unknown,enum,high,False, +chunk_193fea55,src/priv/smctr.adoc,452,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions","What is recorded, if anything, depends on whether the source privilege mode and/or target privilege mode are enabled for recording, and on the transfer type (trap or trap return).",non_CSR_parameter,binary,high,False, +chunk_fa54eddb,src/priv/smctr.adoc,457,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions",Traps between enabled privilege modes are recorded as normal.,unknown,binary,high,False, +chunk_398704a7,src/priv/smctr.adoc,457,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions","Traps from a disabled privilege mode to an enabled privilege mode are partially recorded, such that the `ctrsource`.PC is 0.",unknown,binary,high,False, +chunk_835321d7,src/priv/smctr.adoc,457,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions","Traps from an enabled mode to a disabled mode, known as external traps, are not recorded by default.",unknown,binary,high,False, +chunk_23b00efd,src/priv/smctr.adoc,457,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions",See for how they can be recorded.,unknown,unknown,high,False, +chunk_ccb71808,src/priv/smctr.adoc,459,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions",Trap returns have similar treatment.,unknown,unknown,high,False, +chunk_b6fe3489,src/priv/smctr.adoc,459,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions",Trap returns between enabled privilege modes are recorded as normal.,unknown,binary,high,False, +chunk_c24f54a8,src/priv/smctr.adoc,459,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions","Trap returns from an enabled mode back to a disabled mode are partially recorded, such that `ctrtarget`.PC is 0.",unknown,binary,high,False, +chunk_d68ac1a6,src/priv/smctr.adoc,459,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions",Trap returns from a disabled mode to an enabled mode are not recorded.,unknown,binary,high,False, +chunk_5f488a20,src/priv/smctr.adoc,461,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions",Recording in Debug Mode is always inhibited.,unknown,unknown,high,False, +chunk_d4425507,src/priv/smctr.adoc,461,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions",Transfers into and out of Debug Mode are never recorded.,unknown,unknown,high,False, +chunk_7324870a,src/priv/smctr.adoc,463,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions",The table below provides details on recording of privilege mode transitions.,unknown,enum,high,False, +chunk_6e8efb9c,src/priv/smctr.adoc,463,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions","Standard dependencies on FROZEN and transfer type inhibits also apply, but are not covered by the table.",unknown,unknown,high,False, +chunk_400982ee,src/priv/smctr.adoc,473,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions","|*Disabled* |Recorded, `ctrsource`.PC is 0. |Not recorded.",unknown,binary,high,False, +chunk_bb52246c,src/priv/smctr.adoc,482,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions > Virtualization Mode Transitions","Transitions between VS/VU-mode and M/HS-mode are unique in that they effect a change in the active CTR control register, and hence the CTR configuration.",unknown,unknown,high,False, +chunk_37147815,src/priv/smctr.adoc,482,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions > Virtualization Mode Transitions","What is recorded, if anything, on these virtualization mode transitions depends upon fields from both `[ms]ctrctl` and `vsctrctl`.",unknown,enum,high,False, +chunk_c075602b,src/priv/smctr.adoc,491,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions > External Traps",External traps are traps from a privilege mode enabled for CTR recording to a privilege mode that is not enabled for CTR recording.,unknown,binary,high,False, +chunk_281639c6,src/priv/smctr.adoc,491,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions > External Traps","By default external traps are not recorded, but privileged software running in the target mode of the trap can opt-in to allowing CTR to record external traps into that mode.",SW_rule,unknown,high,False, +chunk_c525952d,src/priv/smctr.adoc,491,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions > External Traps","The `xctrctl`.xTE bits allow M-mode, S-mode, and VS-mode to opt-in separately.",unknown,unknown,high,False, +chunk_bccfbb3e,src/priv/smctr.adoc,493,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions > External Traps","External trap recording depends not only on the target mode, but on any intervening modes, which are modes that are more privileged than the source mode but less privileged than the target mode.",unknown,unknown,high,False, +chunk_87af05a4,src/priv/smctr.adoc,493,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions > External Traps","Not only must the external trap enable bit for the target mode be set, but the external trap enable bit(s) for any intervening modes must also be set.",non_CSR_parameter,binary,very_high,False, +chunk_8c559435,src/priv/smctr.adoc,493,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions > External Traps",See the table below for details.,unknown,unknown,high,False, +chunk_4908794a,src/priv/smctr.adoc,495,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions > External Traps",[NOTE] Requiring intervening modes to be enabled for external traps simplifies software management of CTR.,SW_rule,binary,high,False, +chunk_fc4f897c,src/priv/smctr.adoc,495,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions > External Traps","Consider a scenario where S-mode software is configuring CTR for U-mode contexts A and B, such that external traps (to any mode) are enabled for A but not for B.",SW_rule,binary,high,False, +chunk_d48cb815,src/priv/smctr.adoc,495,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions > External Traps","When switching between the two contexts, S-mode can simply toggle `sctrctl`.STE, rather than requiring a trap to M-mode to additionally toggle `mctrctl`.MTE.",unknown,unknown,high,False, +chunk_9d36bd0d,src/priv/smctr.adoc,500,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions > External Traps",This method does not provide the flexibility to record external traps to a more privileged mode but not to all intervening mode(s).,unknown,unknown,high,False, +chunk_8182555b,src/priv/smctr.adoc,518,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions > External Traps","In records for external traps, the `ctrtarget`.PC is 0.",unknown,unknown,high,False, +chunk_90a5dee2,src/priv/smctr.adoc,529,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions > External Traps","Thus, when external traps are enabled, both external interrupts and external exceptions are recorded.",unknown,binary,high,False, +chunk_849662d5,src/priv/smctr.adoc,534,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions > External Traps",STE allows recording of traps from U-mode to S-mode as well as from VS/VU-mode to HS-mode.,unknown,unknown,high,False, +chunk_4e00e5c6,src/priv/smctr.adoc,534,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions > External Traps",The hypervisor can flip `sctrctl`.STE before entering a guest if it wants different behavior for U-to-S vs VS/VU-to-HS.,SW_rule,unknown,high,False, +chunk_329f5aad,src/priv/smctr.adoc,537,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions > External Traps","If external trap recording is implemented, `mctrctl`.MTE and `sctrctl`.STE must be implemented, while `vsctrctl`.STE must be implemented if the H extension is implemented.",non_CSR_parameter,binary,very_high,False, +chunk_84b6f46f,src/priv/smctr.adoc,541,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Transfer Type Filtering","By setting transfer type filter bits, software can opt out of recording select transfer types, or opt into recording non-default operations.",SW_rule,enum,high,False, +chunk_81a04b71,src/priv/smctr.adoc,541,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Transfer Type Filtering",All transfer type filter bits are optional.,unknown,unknown,high,False, +chunk_fcbe53a6,src/priv/smctr.adoc,543,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Transfer Type Filtering",Non-default operations require opt-in rather than opt-out.,unknown,unknown,high,False, +chunk_987bbe9d,src/priv/smctr.adoc,549,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Transfer Type Filtering","For completeness, the definitions are reproduced below.",unknown,unknown,high,False, +chunk_5a68aaa6,src/priv/smctr.adoc,577,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Transfer Type Filtering",Encodings 8 through 15 refer to various encodings of jump instructions.,unknown,enum,high,False, +chunk_58b9e033,src/priv/smctr.adoc,577,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Transfer Type Filtering",The types are distinguished as described below.,unknown,unknown,high,False, +chunk_7f47089d,src/priv/smctr.adoc,606,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Transfer Type Filtering","If implementation of any transfer type filter bit results in reduced software performance, perhaps due to additional retirement restrictions, it is strongly recommended that this reduced performance apply only when the bit is set.",SW_rule,unknown,high,False, +chunk_2473f6d8,src/priv/smctr.adoc,606,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Transfer Type Filtering","Alternatively, support for the bit may be omitted.",non_CSR_parameter,enum,high,False, +chunk_60d93379,src/priv/smctr.adoc,606,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Transfer Type Filtering","Maintaining software performance for the default CTR configuration, when all transfer type bits are cleared, is recommended.",SW_rule,unknown,high,False, +chunk_680281cc,src/priv/smctr.adoc,615,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Cycle Counting",The `ctrdata` register may optionally include a count of CPU cycles elapsed since the prior CTR record.,non_CSR_parameter,enum,high,False, +chunk_a986df1b,src/priv/smctr.adoc,615,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Cycle Counting","The elapsed cycle count value is represented by the CC field, which has a 12-bit mantissa component (Cycle Count Mantissa, or CCM) and a 4-bit exponent component (Cycle Count Exponent, or CCE).",non_CSR_parameter,range,high,False, +chunk_ba90120b,src/priv/smctr.adoc,617,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Cycle Counting",The elapsed cycle counter (CtrCycleCounter) increments at the same rate as the `mcycle` counter.,unknown,unknown,high,False, +chunk_9a9a7717,src/priv/smctr.adoc,617,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Cycle Counting","Only cycles while CTR is active are counted, where active implies that the current privilege mode is enabled for recording and CTR is not frozen.",unknown,binary,high,False, +chunk_8fb0ab8b,src/priv/smctr.adoc,617,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Cycle Counting","The CC field is encoded such that CCE holds 0 if the CtrCycleCounter value is less than 4096, otherwise it holds the index of the most significant one bit in the CtrCycleCounter value, minus 11. CCM holds CtrCycleCounter bits CCE+10:CCE-1.",unknown,range,high,False, +chunk_fa6ad78d,src/priv/smctr.adoc,619,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Cycle Counting",The elapsed cycle count can then be calculated by software using the following formula:,SW_rule,unknown,high,False, +chunk_1d12c7b4,src/priv/smctr.adoc,621,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Cycle Counting","[subs=""specialchars,quotes""] ---- if (CCE0): return CCM else: return (2^12^ + CCM) << CCE-1 endif ----",unknown,unknown,high,False, +chunk_d5c71da1,src/priv/smctr.adoc,631,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Cycle Counting","The CtrCycleCounter is reset on writes to `xctrctl`, and on execution of SCTRCLR, to ensure that any accumulated cycle counts do not persist across a context switch.",unknown,unknown,high,False, +chunk_ffa9783a,src/priv/smctr.adoc,633,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Cycle Counting","An implementation that supports cycle counting must implement CCV and all CCM bits, but may implement 0..4 exponent bits in CCE.",non_CSR_parameter,enum,very_high,False, +chunk_26c2d7dc,src/priv/smctr.adoc,633,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Cycle Counting",Unimplemented CCE bits are read-only 0.,CSR_controlled,unknown,high,False, +chunk_7611551b,src/priv/smctr.adoc,633,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Cycle Counting","For implementations that support transfer type filtering, it is recommended to implement at least 3 exponent bits.",non_CSR_parameter,range,high,False, +chunk_35a43031,src/priv/smctr.adoc,640,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Cycle Counting",The size of the CtrCycleCounter required to support each CCE width is given in the table below.,unknown,unknown,high,False, +chunk_9425ee1f,src/priv/smctr.adoc,654,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Cycle Counting","When CCE>1, the granularity of the reported cycle count is reduced.",unknown,unknown,high,False, +chunk_fdd45350,src/priv/smctr.adoc,654,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Cycle Counting","As a result, the reported value represents an undercount of elapsed cycles for most cases (when the unreported bits are non-zero).",unknown,unknown,high,False, +chunk_556be5a6,src/priv/smctr.adoc,654,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Cycle Counting","On average, the undercount will be (2^CCE-1^-1)/2.",unknown,unknown,high,False, +chunk_0a310148,src/priv/smctr.adoc,654,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Cycle Counting",Software can reduce the average undercount to 0 by adding (2^CCE-1^-1)/2 to each computed cycle count value when CCE>1.,SW_rule,unknown,high,False, +chunk_5f746d51,src/priv/smctr.adoc,659,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Cycle Counting","Though this compressed method of representation results in some imprecision for larger cycle count values, it produces meaningful area savings, reducing storage per entry from 27 bits to 16.",non_CSR_parameter,range,high,False, +chunk_41dac95d,src/priv/smctr.adoc,662,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Cycle Counting",The CC value saturates when all implemented bits in CCM and CCE are 1.,unknown,unknown,high,False, +chunk_2c23500d,src/priv/smctr.adoc,664,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Cycle Counting",The CC value is valid only when the Cycle Count Valid (CCV) bit is set.,unknown,unknown,high,False, +chunk_6758bcca,src/priv/smctr.adoc,664,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Cycle Counting","If CCV=0, the CC value might not hold the correct count of elapsed active cycles since the last recorded transfer.",unknown,unknown,high,False, +chunk_5fbe2386,src/priv/smctr.adoc,664,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Cycle Counting","The next record will have CCV=0 after a write to `xctrctl`, or execution of SCTRCLR, since CtrCycleCounter is reset. CCV should additionally be cleared after any other implementation-specific scenarios where active cycles might not be counted in CtrCycleCounter.",non_CSR_parameter,enum,high,False, +chunk_af12b971,src/priv/smctr.adoc,668,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > RAS (Return Address Stack) Emulation Mode","When the optional `xctrctl`.RASEMU bit is implemented and set to 1, transfer recording behavior is altered to emulate the behavior of a return-address stack (RAS).",unknown,binary,high,False, +chunk_3cb64063,src/priv/smctr.adoc,670,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > RAS (Return Address Stack) Emulation Mode","Indirect and direct calls are recorded as normal * Function returns pop the most recent call, by decrementing the WRPTR then invalidating the WRPTR entry (by setting ctrsource.V=0).",unknown,unknown,high,False, +chunk_d7503270,src/priv/smctr.adoc,670,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > RAS (Return Address Stack) Emulation Mode","As a result, logical entry 0 is invalidated and moves to logical entry depth-1, while logical entries 1..depth-1 move to 0..depth-2. * Co-routine swaps affect both a return and a call.",unknown,unknown,high,False, +chunk_a81de96d,src/priv/smctr.adoc,677,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > RAS (Return Address Stack) Emulation Mode",[NOTE] Profiling tools often collect call stacks along with each sample.,unknown,unknown,high,False, +chunk_e1da1ea7,src/priv/smctr.adoc,677,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > RAS (Return Address Stack) Emulation Mode","With RAS emulation, tools can ask CTR hardware to save call stacks even for unmodified code.",unknown,unknown,high,False, +chunk_4a6213a8,src/priv/smctr.adoc,686,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > RAS (Return Address Stack) Emulation Mode",CTR RAS emulation has limitations.,unknown,unknown,high,False, +chunk_5d645f0b,src/priv/smctr.adoc,686,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > RAS (Return Address Stack) Emulation Mode","The CTR buffer will contain only partial stacks in cases where the call stack depth was greater than the CTR depth, CTR recording was enabled at a lower point in the call stack than main(), or where the CTR buffer was cleared since main().",unknown,binary,high,False, +chunk_75556d1b,src/priv/smctr.adoc,691,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > RAS (Return Address Stack) Emulation Mode","[NOTE] As described in , when CCV=1, the CC field provides the elapsed cycles since the prior CTR entry was recorded.",unknown,enum,high,False, +chunk_4371650f,src/priv/smctr.adoc,691,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > RAS (Return Address Stack) Emulation Mode","The implication is that returns that pop a call entry not only do not reset the cycle counter, but instead add the CC field from the popped entry to the counter.",unknown,enum,high,False, +chunk_eadcb771,src/priv/smctr.adoc,691,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > RAS (Return Address Stack) Emulation Mode","For simplicity, an implementation may opt to record CCV=0 for all calls, or those whose parent call was popped, when RASEMU=1.",non_CSR_parameter,enum,high,False, +chunk_92caf200,src/priv/smctr.adoc,707,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Freeze","When `sctrstatus`.FROZEN=1, transfer recording is inhibited.",unknown,unknown,high,False, +chunk_39f27071,src/priv/smctr.adoc,707,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Freeze","This bit can be set by hardware, as described below, or by software.",SW_rule,unknown,high,False, +chunk_7bcf6eb2,src/priv/smctr.adoc,709,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Freeze","When `sctrctl`.LCOFIFRZ=1 and a local-counter-overflow interrupt (LCOFI) traps (as a result of an HPM counter overflow) to M-mode or to S-mode, `sctrstatus`.FROZEN is set by hardware.",unknown,unknown,high,False, +chunk_aead4baa,src/priv/smctr.adoc,709,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Freeze",This inhibits CTR recording until software clears FROZEN.,SW_rule,unknown,high,False, +chunk_dbb85987,src/priv/smctr.adoc,709,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Freeze","The LCOFI trap itself is not recorded. [NOTE] Freeze on LCOFI ensures that the execution path leading to the sampled instruction (`xepc`) is preserved, and that the local-counter-overflow interrupt (LCOFI) and associated Interrupt Service Routine (ISR) do not displace any recorded transfer history state.",unknown,unknown,high,False, +chunk_11d2724b,src/priv/smctr.adoc,709,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Freeze","It is the responsibility of the ISR to clear FROZEN before xRET, if continued control transfer recording is desired.",unknown,unknown,high,False, +chunk_df4d9463,src/priv/smctr.adoc,721,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Freeze",LCOFI refers only to architectural traps directly caused by a local counter overflow.,unknown,unknown,high,False, +chunk_81833cde,src/priv/smctr.adoc,721,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Freeze","If a local-counter-overflow interrupt is recognized without a trap, FROZEN is not automatically set.",unknown,unknown,high,False, +chunk_4ec90ff6,src/priv/smctr.adoc,721,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Freeze","As a result, some or all CTR history may be overwritten while handling the LCOFI.",non_CSR_parameter,enum,high,False, +chunk_f4e44b8f,src/priv/smctr.adoc,721,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Freeze","Similarly, on a breakpoint exception that traps to M-mode or S-mode with `sctrctl`.BPFRZ=1, FROZEN is set by hardware.",unknown,unknown,high,False, +chunk_6f3a80e4,src/priv/smctr.adoc,721,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Freeze",The breakpoint exception itself is not recorded.,unknown,unknown,high,False, +chunk_cbc842bc,src/priv/smctr.adoc,725,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Freeze","[NOTE] Breakpoint exception refers to synchronous exceptions with a cause value of Breakpoint (3), regardless of source (ebreak, c.ebreak, Sdtrig); it does not include entry into Debug Mode, even in cores where this is implemented as an exception.",unknown,enum,high,False, +chunk_6dfa8a5b,src/priv/smctr.adoc,731,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Freeze","If the H extension is implemented, freeze behavior for LCOFIs and breakpoint exceptions that trap to VS-mode is determined by the LCOFIFRZ and BPFRZ values, respectively, in `vsctrctl`.",non_CSR_parameter,unknown,high,False, +chunk_29b1328b,src/priv/smctr.adoc,731,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Freeze",This includes virtual LCOFIs pended by a hypervisor.,SW_rule,unknown,high,False, +chunk_27fac302,src/priv/smctr.adoc,733,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Freeze","When a guest uses the SBI Supervisor Software Events (SSE) extension, the LCOFI will trap to HS-mode, which will then invoke a registered VS-mode LCOFI handler routine.",SW_rule,unknown,high,False, +chunk_4e51707f,src/priv/smctr.adoc,733,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Freeze","If `vsctrctl`.LCOFIFRZ=1, the HS-mode handler will need to emulate the freeze by setting `sctrstatus`.FROZEN=1 before invoking the registered handler routine.",unknown,unknown,high,False, +chunk_7d2ccf89,src/priv/smctr.adoc,742,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Custom Extensions",Any custom CTR extension must be associated with a non-zero value within the designated custom bits in `xctrctl`.,non_CSR_parameter,enum,very_high,False, +chunk_22cd190e,src/priv/smctr.adoc,742,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Custom Extensions","When the custom bits hold a non-zero value that enables a custom extension, the extension may alter standard CTR behavior, and may define new custom status fields within `sctrstatus` or the CTR .",non_CSR_parameter,enum,high,False, +chunk_d4efda54,src/priv/smctr.adoc,742,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Custom Extensions","All custom status fields, and standard status fields whose behavior is altered by the custom extension, must revert to standard behavior when the custom bits hold zero.",non_CSR_parameter,enum,very_high,False, +chunk_3b99f8d0,src/priv/smctr.adoc,742,"Preamble > ""Smctr"" Control Transfer Records Extension, Version 1.0 > CSRs > Custom Extensions",This includes read-only 0 behavior for any bits undefined by any implemented standard extensions.,CSR_controlled,unknown,high,False, +chunk_f5415624,src/priv/smdbltrp.adoc,3,"Preamble > ""Smdbltrp"" Double Trap Extension, Version 1.0","When the Smrnmi extension () is implemented, it enables invocation of the RNMI handler on a double trap in M-mode to handle the critical error.",unknown,unknown,high,False, +chunk_efc606e9,src/priv/smdbltrp.adoc,3,"Preamble > ""Smdbltrp"" Double Trap Extension, Version 1.0","If the Smrnmi extension is not implemented or if a double trap occurs during the RNMI handler's execution, this extension helps transition the hart to a critical error state and enables signaling the critical error to the platform.",unknown,unknown,high,False, +chunk_feba7989,src/priv/smdbltrp.adoc,11,"Preamble > ""Smdbltrp"" Double Trap Extension, Version 1.0",The extension introduces a mechanism to enter Debug Mode instead of asserting a critical-error signal to the platform when the hart is in a critical error state.,unknown,unknown,high,False, +chunk_8fb88904,src/priv/smepmp.adoc,3,"Preamble > ""Smepmp"" Extension for PMP Enhancements for memory access and execution prevention in Machine mode, Version 1.0","Being able to access the memory of a process running at a high privileged execution mode, such as the Supervisor or Machine mode, from a lower privileged mode such as the User mode, introduces an obvious attack vector since it allows for an attacker to perform privilege escalation, and tamper with the code and/or data of that process. A less obvious attack vector exists when the reverse happens, in which case an attacker instead of tampering with code and/or data that belong to a high-privileged process, can tamper with the memory of an unprivileged / less-privileged process and trick the high-privileged process to use or execute it.",unknown,unknown,high,False, +chunk_e1251d7e,src/priv/smepmp.adoc,5,"Preamble > ""Smepmp"" Extension for PMP Enhancements for memory access and execution prevention in Machine mode, Version 1.0","The first one prevents the OS from accessing the memory of an unprivileged process unless a specific code path is followed, and the second one prevents the OS from executing the memory of an unprivileged process at all times. RISC-V already includes support for the former through the ``sstatus.SUM`` bit, and for the latter by always denying supervisor execution of virtual memory pages marked with the U bit.",CSR_controlled,enum,high,False, +chunk_57fdab67,src/priv/smepmp.adoc,25,"Preamble > ""Smepmp"" Extension for PMP Enhancements for memory access and execution prevention in Machine mode, Version 1.0 > Threat model > Smepmp Physical Memory Protection Rules","To address the threat model outlined in Section , this extension introduces the `RLB`, `MMWP`, and `MML` fields in the `mseccfg` CSR and their associated rules.",CSR_controlled,enum,high,False, +chunk_7e0aa8a0,src/priv/smepmp.adoc,25,"Preamble > ""Smepmp"" Extension for PMP Enhancements for memory access and execution prevention in Machine mode, Version 1.0 > Threat model > Smepmp Physical Memory Protection Rules",See for the detailed specification of these fields and the corresponding rules.,unknown,enum,high,False, +chunk_aec572a2,src/priv/smepmp.adoc,30,"Preamble > ""Smepmp"" Extension for PMP Enhancements for memory access and execution prevention in Machine mode, Version 1.0 > Threat model > Smepmp Physical Memory Protection Rules",The physical memory protection rules when `mseccfg.MML` is set to 1 are summarized in the truth table below.,unknown,binary,high,False, +chunk_b806a90c,src/priv/smepmp.adoc,62,"Preamble > ""Smepmp"" Extension for PMP Enhancements for memory access and execution prevention in Machine mode, Version 1.0 > Threat model > Smepmp software discovery","Since all fields defined in ``mseccfg`` as part of this extension are locked when set (``MMWP``/``MML``) or locked when cleared (``RLB``), software can't poll them for determining the presence of Smepmp.",SW_rule,enum,high,False, +chunk_da96c693,src/priv/smrnmi.adoc,3,"Preamble > ""Smrnmi"" Extension for Resumable Non-Maskable Interrupts, Version 1.0","The base machine-level architecture supports only unresumable non-maskable interrupts (UNMIs), where the NMI jumps to a handler in machine mode, overwriting the current `mepc` and `mcause` register values.",CSR_controlled,enum,high,False, +chunk_e5a96994,src/priv/smrnmi.adoc,3,"Preamble > ""Smrnmi"" Extension for Resumable Non-Maskable Interrupts, Version 1.0","If the hart had been executing machine-mode code in a trap handler, the previous values in `mepc` and `mcause` would not be recoverable and so execution is not generally resumable.",CSR_controlled,enum,high,False, +chunk_83c991ab,src/priv/smrnmi.adoc,10,"Preamble > ""Smrnmi"" Extension for Resumable Non-Maskable Interrupts, Version 1.0",The Smrnmi extension adds support for resumable non-maskable interrupts (RNMIs) to RISC-V.,unknown,unknown,high,False, +chunk_bdbbcbcb,src/priv/smrnmi.adoc,10,"Preamble > ""Smrnmi"" Extension for Resumable Non-Maskable Interrupts, Version 1.0","The extension adds four new CSRs (`mnepc`, `mncause`, `mnstatus`, and `mnscratch`) to hold the interrupted state, and one new instruction, MNRET, to resume from the RNMI handler.",CSR_controlled,enum,high,False, +chunk_5f64c535,src/priv/smrnmi.adoc,17,"Preamble > ""Smrnmi"" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals",The `rnmi` interrupt signals are inputs to the hart.,unknown,unknown,high,False, +chunk_4f9b7705,src/priv/smrnmi.adoc,17,"Preamble > ""Smrnmi"" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals",These interrupts have higher priority than any other interrupt or exception on the hart and cannot be disabled by software.,SW_rule,binary,high,False, +chunk_d0c694c2,src/priv/smrnmi.adoc,17,"Preamble > ""Smrnmi"" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals","Specifically, they are not disabled by clearing the `mstatus`.MIE register.",CSR_controlled,binary,high,False, +chunk_13b80bc1,src/priv/smrnmi.adoc,24,"Preamble > ""Smrnmi"" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI Handler Addresses",The RNMI interrupt trap handler address is implementation-defined.,non_CSR_parameter,unknown,high,False, +chunk_43cce05f,src/priv/smrnmi.adoc,26,"Preamble > ""Smrnmi"" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI Handler Addresses","RNMI also has an associated exception trap handler address, which is implementation defined.",unknown,unknown,high,False, +chunk_34c1a629,src/priv/smrnmi.adoc,34,"Preamble > ""Smrnmi"" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs",This extension adds additional M-mode CSRs to enable a resumable non-maskable interrupt (RNMI).,CSR_controlled,enum,high,False, +chunk_d593a6e4,src/priv/smrnmi.adoc,40,"Preamble > ""Smrnmi"" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs",The `mnscratch` CSR holds an MXLEN-bit read-write register which enables the RNMI trap handler to save and restore the context that was interrupted.,CSR_controlled,range,high,False, +chunk_24226da1,src/priv/smrnmi.adoc,47,"Preamble > ""Smrnmi"" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs",The `mnepc` CSR is an MXLEN-bit read-write register which on entry to the RNMI trap handler holds the PC of the instruction that took the interrupt.,CSR_controlled,range,high,False, +chunk_698c033f,src/priv/smrnmi.adoc,51,"Preamble > ""Smrnmi"" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs",The low bit of `mnepc` (`mnepc[0]`) is always zero.,unknown,unknown,high,False, +chunk_8effac9b,src/priv/smrnmi.adoc,55,"Preamble > ""Smrnmi"" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs",This masking occurs also for the implicit read by the MNRET instruction.,unknown,unknown,high,False, +chunk_c04f6355,src/priv/smrnmi.adoc,55,"Preamble > ""Smrnmi"" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs","Though masked, `mnepc[1]` remains writable when IALIGN=32.",unknown,unknown,high,False, +chunk_8895fd7d,src/priv/smrnmi.adoc,61,"Preamble > ""Smrnmi"" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs",`mnepc` is a *WARL* register that must be able to hold all valid virtual addresses.,CSR_controlled,enum,very_high,False, +chunk_8488b26b,src/priv/smrnmi.adoc,61,"Preamble > ""Smrnmi"" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs",It need not be capable of holding all possible invalid addresses.,non_CSR_parameter,enum,high,False, +chunk_d230e57f,src/priv/smrnmi.adoc,61,"Preamble > ""Smrnmi"" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs","Prior to writing `mnepc`, implementations may convert an invalid address into some other invalid address that `mnepc` is capable of holding.",non_CSR_parameter,enum,high,False, +chunk_08264a8a,src/priv/smrnmi.adoc,71,"Preamble > ""Smrnmi"" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs",The `mncause` CSR holds the reason for the RNMI.,CSR_controlled,enum,high,False, +chunk_1d4ccac2,src/priv/smrnmi.adoc,71,"Preamble > ""Smrnmi"" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs","If the reason is an interrupt, bit MXLEN-1 is set to 1, and the RNMI cause is encoded in the least-significant bits.",unknown,binary,high,False, +chunk_6841b407,src/priv/smrnmi.adoc,71,"Preamble > ""Smrnmi"" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs","If the reason is an interrupt and RNMI causes are not supported, bit MXLEN-1 is set to 1, and zero is written to the least-significant bits.",unknown,binary,high,False, +chunk_67586a35,src/priv/smrnmi.adoc,71,"Preamble > ""Smrnmi"" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs","If the reason is an exception within M-mode that results in a double trap as specified in the Smdbltrp extension, bit MXLEN-1 is set to 0 and the least-significant bits are set to the cause code corresponding to the exception that precipitated the double trap.",non_CSR_parameter,binary,high,False, +chunk_1af0eedd,src/priv/smrnmi.adoc,85,"Preamble > ""Smrnmi"" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs","The `mnstatus` CSR holds a two-bit field, MNPP, which on entry to the RNMI trap handler holds the privilege mode of the interrupted context, encoded in the same manner as `mstatus`.MPP.",CSR_controlled,enum,high,False, +chunk_edf5180e,src/priv/smrnmi.adoc,85,"Preamble > ""Smrnmi"" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs","If the H extension is also implemented, `mnstatus` also holds a one-bit field, MNPV, which on entry to the RNMI trap handler holds the virtualization mode of the interrupted context, encoded in the same manner as `mstatus`.MPV.",CSR_controlled,enum,high,False, +chunk_15885066,src/priv/smrnmi.adoc,93,"Preamble > ""Smrnmi"" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs","If the Zicfilp extension is implemented, `mnstatus` also holds the MNPELP field, which on entry to the RNMI trap handler holds the previous `ELP` state.",unknown,enum,high,False, +chunk_afcd26b6,src/priv/smrnmi.adoc,93,"Preamble > ""Smrnmi"" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs","When an RNMI trap is taken, MNPELP is set to `ELP` and `ELP` is set to 0.",unknown,binary,high,False, +chunk_e41a6c7e,src/priv/smrnmi.adoc,97,"Preamble > ""Smrnmi"" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs",`mnstatus` also holds the NMIE bit.,CSR_controlled,enum,high,False, +chunk_b5684f3b,src/priv/smrnmi.adoc,97,"Preamble > ""Smrnmi"" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs","When NMIE=1, non-maskable interrupts are enabled.",CSR_controlled,binary,high,False, +chunk_ecc4122c,src/priv/smrnmi.adoc,97,"Preamble > ""Smrnmi"" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs","When NMIE=0, all interrupts are disabled.",CSR_controlled,binary,high,False, +chunk_de22693d,src/priv/smrnmi.adoc,100,"Preamble > ""Smrnmi"" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs","When NMIE=0, the hart behaves as though `mstatus`.MPRV were clear, regardless of the current setting of `mstatus`.MPRV.",CSR_controlled,enum,high,False, +chunk_ae0ab819,src/priv/smrnmi.adoc,103,"Preamble > ""Smrnmi"" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs","Upon reset, NMIE contains the value 0.",CSR_controlled,enum,high,False, +chunk_7d89266a,src/priv/smrnmi.adoc,105,"Preamble > ""Smrnmi"" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs","Software can set NMIE to 1, but attempts to clear NMIE have no effect.",CSR_controlled,enum,high,False, +chunk_b44ceea2,src/priv/smrnmi.adoc,107,"Preamble > ""Smrnmi"" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs","For the purposes of the WFI instruction, NMIE is a global interrupt enable, meaning that the setting of NMIE does not affect the operation of the WFI instruction.",CSR_controlled,enum,high,False, +chunk_92e788bd,src/priv/smrnmi.adoc,111,"Preamble > ""Smrnmi"" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs",The other bits in `mnstatus` are reserved; software should write zeros and hardware implementations should return zeros.,SW_rule,enum,high,False, +chunk_4c1c6aa7,src/priv/smrnmi.adoc,116,"Preamble > ""Smrnmi"" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > MNRET Instruction","MNRET is an M-mode-only instruction that uses the values in `mnepc` and `mnstatus` to return to the program counter, privilege mode, and virtualization mode of the interrupted context.",unknown,enum,high,False, +chunk_49733ea8,src/priv/smrnmi.adoc,116,"Preamble > ""Smrnmi"" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > MNRET Instruction",This instruction also sets `mnstatus`.NMIE.,CSR_controlled,enum,high,False, +chunk_550ae943,src/priv/smrnmi.adoc,116,"Preamble > ""Smrnmi"" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > MNRET Instruction","If MNRET changes the privilege mode to a mode less privileged than M, it also sets `mstatus`.MPRV to 0.",CSR_controlled,enum,high,False, +chunk_0bfe971d,src/priv/smrnmi.adoc,125,"Preamble > ""Smrnmi"" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI Operation","When an RNMI interrupt is detected, the interrupted PC is written to the `mnepc` CSR, the type of RNMI to the `mncause` CSR, and the privilege mode of the interrupted context to the `mnstatus` CSR.",CSR_controlled,enum,high,False, +chunk_333947ae,src/priv/smrnmi.adoc,125,"Preamble > ""Smrnmi"" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI Operation","The `mnstatus`.NMIE bit is cleared, masking all interrupts.",CSR_controlled,enum,high,False, +chunk_1079042c,src/priv/smrnmi.adoc,130,"Preamble > ""Smrnmi"" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI Operation",The hart then enters machine-mode and jumps to the RNMI trap handler address.,unknown,unknown,high,False, +chunk_3442dbc0,src/priv/smrnmi.adoc,133,"Preamble > ""Smrnmi"" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI Operation","The RNMI handler can resume original execution using the new MNRET instruction, which restores the PC from `mnepc`, the privilege mode from `mnstatus`, and also sets `mnstatus`.NMIE, which re-enables interrupts.",CSR_controlled,enum,high,False, +chunk_bfcb3a07,src/priv/smrnmi.adoc,137,"Preamble > ""Smrnmi"" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI Operation","If the hart encounters an exception while executing in M-mode with the `mnstatus`.NMIE bit clear, the actions taken are the same as if the exception had occurred while `mnstatus`.NMIE were set, except that the program counter is set to the RNMI exception trap handler address.",CSR_controlled,enum,high,False, +chunk_938e0486,src/priv/smstateen.adoc,3,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0","The problem occurs when an extension adds processor state -- usually explicit registers, but possibly other forms of state -- that the main OS or hypervisor is unaware of (and hence won't context-switch) but that can be modified/written by one user thread or guest OS and perceived/examined/read by another.",SW_rule,unknown,high,False, +chunk_778a976d,src/priv/smstateen.adoc,22,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0","The `f` registers of the RISC-V floating-point extensions and the `v` registers of the vector extension would similarly be potential covert channels between user threads, except for the existence of the FS and VS fields in the `sstatus` register.",CSR_controlled,enum,high,False, +chunk_f217d9c9,src/priv/smstateen.adoc,22,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0","Even if an OS is unaware of, say, the vector extension and its `v` registers, access to those registers is blocked when the VS field is initialized to zero, either at machine level or by the OS itself initializing `sstatus`.",CSR_controlled,enum,high,False, +chunk_e480e4d5,src/priv/smstateen.adoc,30,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0","Obviously, one way to prevent the use of new user-level CSRs as covert channels would be to add to `mstatus` or `sstatus` an ""XS"" field for each relevant extension, paralleling the V extension's VS field.",CSR_controlled,enum,high,False, +chunk_ee371de0,src/priv/smstateen.adoc,30,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0","However, this is not considered a general solution to the problem due to the number of potential future extensions that may add small amounts of state.",non_CSR_parameter,enum,medium,False, +chunk_5a00e8bd,src/priv/smstateen.adoc,30,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0","Even with a 64-bit `sstatus` (necessitating adding `sstatush` for RV32), it is not certain there are enough remaining bits in `sstatus` to accommodate all future user-level extensions.",CSR_controlled,range,high,False, +chunk_924e962e,src/priv/smstateen.adoc,30,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0","In any event, there is no need to strain `sstatus` (and add `sstatush`) for this purpose.",CSR_controlled,enum,high,False, +chunk_72ae618c,src/priv/smstateen.adoc,30,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0","The ""enable"" flags that are needed to plug covert channels are not generally expected to require swapping on context switches of user threads, making them a less-than-compelling candidate for inclusion in `sstatus`.",CSR_controlled,enum,high,False, +chunk_6898bf03,src/priv/smstateen.adoc,45,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0 > State Enable Extensions","The Smstateen extension specification comprises the mstateen*, sstateen*, and hstateen* CSRs and their functionality.",CSR_controlled,enum,high,False, +chunk_6c4eaf2b,src/priv/smstateen.adoc,45,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0 > State Enable Extensions",The Ssstateen extension specification comprises only the sstateen* and hstateen* CSRs and their functionality.,CSR_controlled,enum,high,False, +chunk_0baedc44,src/priv/smstateen.adoc,51,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0 > State Enable Extensions","For RV64 harts, this extension adds four new 64-bit CSRs at machine level: `mstateen0` (Machine State Enable 0), `mstateen1`, `mstateen2`, and `mstateen3`.",CSR_controlled,range,high,False, +chunk_1e3097be,src/priv/smstateen.adoc,55,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0 > State Enable Extensions","If supervisor mode is implemented, another four CSRs are defined at supervisor level: `sstateen0`, `sstateen1`, `sstateen2`, and `sstateen3`.",CSR_controlled,enum,high,False, +chunk_5d4e42ce,src/priv/smstateen.adoc,60,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0 > State Enable Extensions","And if the hypervisor extension is implemented, another set of CSRs is added: `hstateen0`, `hstateen1`, `hstateen2`, and `hstateen3`.",CSR_controlled,enum,high,False, +chunk_76350f1c,src/priv/smstateen.adoc,64,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0 > State Enable Extensions","For RV32, there are CSR addresses for accessing the upper 32 bits of corresponding machine-level and hypervisor CSRs: `mstateen0h`, `mstateen1h`, `mstateen2h`, `mstateen3h`, `hstateen0h`, `hstateen1h`, `hstateen2h`, and `hstateen3h`.",CSR_controlled,range,high,False, +chunk_f59172cd,src/priv/smstateen.adoc,74,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0 > State Enable Extensions","Each bit of a `stateen` CSR controls less-privileged access to an extension's state, for an extension that was not deemed ""worthy"" of a full XS field in `sstatus` like the FS and VS fields for the F and V extensions.",CSR_controlled,enum,high,False, +chunk_3f1a0e13,src/priv/smstateen.adoc,74,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0 > State Enable Extensions",The exact number four is an attempted compromise between providing too few bits on the one hand and going overboard with CSRs that will never be used on the other. A possible future doubling of the number of `stateen` CSRs is covered later.,CSR_controlled,enum,high,False, +chunk_9a0ae304,src/priv/smstateen.adoc,85,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0 > State Enable Extensions",This is analogous to how the existing `counteren` CSRs control access to performance counter registers.,CSR_controlled,enum,high,False, +chunk_fd80e2a6,src/priv/smstateen.adoc,85,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0 > State Enable Extensions","Just as with the `counteren` CSRs, when a `stateen` CSR prevents access to state by less-privileged levels, an attempt in one of those privilege modes to execute an instruction that would read or write the protected state raises an illegal-instruction exception, or, if executing in VS or VU mode and the circumstances for a virtual-instruction exception apply, raises a virtual-instruction exception instead of an illegal-instruction exception.",CSR_controlled,enum,high,False, +chunk_16aec837,src/priv/smstateen.adoc,96,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0 > State Enable Extensions","When this extension is not implemented, all state added by an extension is accessible as defined by that extension.",unknown,unknown,high,False, +chunk_90dacb87,src/priv/smstateen.adoc,99,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0 > State Enable Extensions","When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute in that privilege mode an instruction that implicitly updates the state without reading it may or may not raise an illegal-instruction or virtual-instruction exception.",CSR_controlled,enum,high,False, +chunk_8f6c5b89,src/priv/smstateen.adoc,99,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0 > State Enable Extensions",Such cases must be disambiguated by being explicitly specified one way or the other.,non_CSR_parameter,enum,very_high,False, +chunk_23686fd8,src/priv/smstateen.adoc,106,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0 > State Enable Extensions","In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the ISA extensions that introduce the controlled state.",CSR_controlled,enum,high,False, +chunk_602c2c66,src/priv/smstateen.adoc,109,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0 > State Enable Extensions",Each bit of a supervisor-level `sstateen` CSR controls user-level access (from U-mode or VU-mode) to an extension's state.,CSR_controlled,enum,high,False, +chunk_6139a2d6,src/priv/smstateen.adoc,109,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0 > State Enable Extensions","The intention is to allocate the bits of `sstateen` CSRs starting at the least-significant end, bit 0, through to bit 31, and then on to the next-higher-numbered `sstateen` CSR.",CSR_controlled,enum,high,False, +chunk_4c2219d3,src/priv/smstateen.adoc,114,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0 > State Enable Extensions","For every bit with a defined purpose in an `sstateen` CSR, the same bit is defined in the matching `mstateen` CSR to control access below machine level to the same state.",CSR_controlled,enum,high,False, +chunk_fd09fd7f,src/priv/smstateen.adoc,114,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0 > State Enable Extensions","The upper 32 bits of an `mstateen` CSR (or for RV32, the corresponding high-half CSR) control access to state that is inherently inaccessible to user level, so no corresponding enable bits in the supervisor-level `sstateen` CSR are applicable.",CSR_controlled,range,high,False, +chunk_0652f098,src/priv/smstateen.adoc,114,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0 > State Enable Extensions","The intention is to allocate bits for this purpose starting at the most-significant end, bit 63, through to bit 32, and then on to the next-higher `mstateen` CSR.",CSR_controlled,enum,high,False, +chunk_7b5e69be,src/priv/smstateen.adoc,114,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0 > State Enable Extensions","If the rate that bits are being allocated from the least-significant end for `sstateen` CSRs is sufficiently low, allocation from the most-significant end of `mstateen` CSRs may be allowed to encroach on the lower 32 bits before jumping to the next-higher `mstateen` CSR.",CSR_controlled,range,high,False, +chunk_dc631047,src/priv/smstateen.adoc,114,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0 > State Enable Extensions","In that case, the bit positions of ""encroaching"" bits will remain forever read-only zeros in the matching `sstateen` CSRs.",CSR_controlled,binary,high,False, +chunk_67d880bc,src/priv/smstateen.adoc,128,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0 > State Enable Extensions","With the hypervisor extension, the `hstateen` CSRs have identical encodings to the `mstateen` CSRs, except controlling accesses for a virtual machine (from VS and VU modes).",CSR_controlled,enum,high,False, +chunk_5f25de74,src/priv/smstateen.adoc,133,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0 > State Enable Extensions","Each standard-defined bit of a `stateen` CSR is WARL and may be read-only zero or one, subject to the following conditions.",CSR_controlled,binary,very_high,False, +chunk_c896b4c3,src/priv/smstateen.adoc,137,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0 > State Enable Extensions",Bits in any `stateen` CSR that are defined to control state that a hart doesn't implement are read-only zeros for that hart.,CSR_controlled,binary,high,False, +chunk_f29d7205,src/priv/smstateen.adoc,137,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0 > State Enable Extensions","Likewise, all reserved bits not yet given a defined meaning are also read-only zeros.",CSR_controlled,binary,high,False, +chunk_ed6462fb,src/priv/smstateen.adoc,137,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0 > State Enable Extensions","For every bit in an `mstateen` CSR that is zero (whether read-only zero or set to zero), the same bit appears as read-only zero in the matching `hstateen` and `sstateen` CSRs.",CSR_controlled,binary,high,False, +chunk_270a99d3,src/priv/smstateen.adoc,137,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0 > State Enable Extensions","For every bit in an `hstateen` CSR that is zero (whether read-only zero or set to zero), the same bit appears as read-only zero in `sstateen` when accessed in VS-mode.",CSR_controlled,binary,high,False, +chunk_1fd560f2,src/priv/smstateen.adoc,147,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0 > State Enable Extensions","A bit in a supervisor-level `sstateen` CSR cannot be read-only one unless the same bit is read-only one in the matching `mstateen` CSR and, if it exists, in the matching `hstateen` CSR. A bit in an `hstateen` CSR cannot be read-only one unless the same bit is read-only one in the matching `mstateen` CSR.",CSR_controlled,enum,high,False, +chunk_adfeb87e,src/priv/smstateen.adoc,152,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0 > State Enable Extensions","On reset, all writable `mstateen` bits are initialized by the hardware to zeros.",CSR_controlled,unknown,high,False, +chunk_b489fb78,src/priv/smstateen.adoc,152,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0 > State Enable Extensions","If machine-level software changes these values, it is responsible for initializing the corresponding writable bits of the `hstateen` and `sstateen` CSRs to zeros too.",CSR_controlled,enum,high,False, +chunk_224a83f3,src/priv/smstateen.adoc,152,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0 > State Enable Extensions",Software at each privilege level should set its respective `stateen` CSRs to indicate the state it is prepared to allow less-privileged software to access.,CSR_controlled,enum,high,False, +chunk_00474514,src/priv/smstateen.adoc,161,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0 > State Enable Extensions","For each `mstateen` CSR, bit 63 is defined to control access to the matching `sstateen` and `hstateen` CSRs.",CSR_controlled,enum,high,False, +chunk_18cb01d6,src/priv/smstateen.adoc,161,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0 > State Enable Extensions","Likewise, bit 63 of each `hstateen` correspondingly controls access to the matching `sstateen` CSR.",CSR_controlled,enum,high,False, +chunk_9e6b8968,src/priv/smstateen.adoc,167,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0 > State Enable Extensions",A hypervisor may need this control over accesses to the `sstateen` CSRs if it ever must emulate for a virtual machine an extension that is supposed to be affected by a bit in an `sstateen` CSR.,CSR_controlled,enum,very_high,False, +chunk_cc7217c0,src/priv/smstateen.adoc,167,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0 > State Enable Extensions","Even if such emulation is uncommon, it should not be excluded.",non_CSR_parameter,enum,high,False, +chunk_558119ab,src/priv/smstateen.adoc,172,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0 > State Enable Extensions","That is, machine level needs control over accesses to the supervisor-level `sstateen` CSRs in order to emulate the `hstateen` CSRs, which have such control.",CSR_controlled,enum,high,False, +chunk_fcd0897b,src/priv/smstateen.adoc,177,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0 > State Enable Extensions",Bit 63 of each `mstateen` CSR may be read-only zero only if the hypervisor extension is not implemented and the matching supervisor-level `sstateen` CSR is all read-only zeros.,CSR_controlled,binary,high,False, +chunk_fb796634,src/priv/smstateen.adoc,177,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0 > State Enable Extensions","In that case, machine-level software should emulate attempts to access the affected `sstateen` CSR from S-mode, ignoring writes and returning zero for reads.",CSR_controlled,enum,high,False, +chunk_592ee623,src/priv/smstateen.adoc,177,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0 > State Enable Extensions",Bit 63 of each `hstateen` CSR is always writable (not read-only).,CSR_controlled,enum,high,False, +chunk_1e69cfad,src/priv/smstateen.adoc,238,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0 > State Enable Extensions > State Enable 0 Registers",The C bit controls access to any and all custom state.,non_CSR_parameter,unknown,high,False, +chunk_f835e2f7,src/priv/smstateen.adoc,238,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0 > State Enable Extensions > State Enable 0 Registers","The C bit of these registers is not custom state itself; it is a standard field of a standard CSR, either `mstateen0`, `hstateen0`, or `sstateen0`.",CSR_controlled,enum,high,False, +chunk_fccce0ed,src/priv/smstateen.adoc,243,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0 > State Enable Extensions > State Enable 0 Registers","The FCSR bit controls access to `fcsr` for the case when floating-point instructions operate on `x` registers instead of `f` registers as specified by the Zfinx and related extensions (Zdinx, etc.). [mstateen0fcsrroz]Whenever `misa.F` = 1, FCSR bit of `mstateen0` is read-only zero (and hence read-only zero in `hstateen0` and `sstateen0` too).",CSR_controlled,binary,high,False, +chunk_75109212,src/priv/smstateen.adoc,243,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0 > State Enable Extensions > State Enable 0 Registers","For convenience, when the `stateen` CSRs are implemented and `misa.F` = 0, then if the FCSR bit of a controlling `stateen0` CSR is zero, all floating-point instructions cause an illegal-instruction exception (or virtual-instruction exception, if relevant), as though they all access `fcsr`, regardless of whether they really do.",CSR_controlled,enum,high,False, +chunk_b642d77f,src/priv/smstateen.adoc,253,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0 > State Enable Extensions > State Enable 0 Registers",The JVT bit controls access to the `jvt` CSR provided by the Zcmt extension.,CSR_controlled,enum,high,False, +chunk_5a34402e,src/priv/smstateen.adoc,256,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0 > State Enable Extensions > State Enable 0 Registers","The SE0 bit in `mstateen0` controls access to the `hstateen0`, `hstateen0h`, and the `sstateen0` CSRs.",CSR_controlled,enum,high,False, +chunk_370407ad,src/priv/smstateen.adoc,256,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0 > State Enable Extensions > State Enable 0 Registers",The SE0 bit in `hstateen0` controls access to the `sstateen0` CSR.,CSR_controlled,enum,high,False, +chunk_9b424a29,src/priv/smstateen.adoc,260,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0 > State Enable Extensions > State Enable 0 Registers","The ENVCFG bit in `mstateen0` controls access to the `henvcfg`, `henvcfgh`, and the `senvcfg` CSRs.",CSR_controlled,enum,high,False, +chunk_c169c627,src/priv/smstateen.adoc,260,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0 > State Enable Extensions > State Enable 0 Registers",The ENVCFG bit in `hstateen0` controls access to the `senvcfg` CSRs.,CSR_controlled,enum,high,False, +chunk_d0ffcb71,src/priv/smstateen.adoc,264,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0 > State Enable Extensions > State Enable 0 Registers","The CSRIND bit in `mstateen0` controls access to the `siselect`, `sireg*`, `vsiselect`, and the `vsireg*` CSRs provided by the Sscsrind extensions.",CSR_controlled,enum,high,False, +chunk_44ddd04e,src/priv/smstateen.adoc,264,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0 > State Enable Extensions > State Enable 0 Registers","The CSRIND bit in `hstateen0` controls access to the `siselect` and the `sireg*`, (really `vsiselect` and `vsireg*`) CSRs provided by the Sscsrind extensions.",CSR_controlled,enum,high,False, +chunk_5d160585,src/priv/smstateen.adoc,270,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0 > State Enable Extensions > State Enable 0 Registers","The IMSIC bit in `mstateen0` controls access to the IMSIC state, including CSRs `stopei` and `vstopei`, provided by the Ssaia extension.",CSR_controlled,enum,high,False, +chunk_d7794bf3,src/priv/smstateen.adoc,270,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0 > State Enable Extensions > State Enable 0 Registers","The IMSIC bit in `hstateen0` controls access to the guest IMSIC state, including CSRs `stopei` (really `vstopei`), provided by the Ssaia extension.",CSR_controlled,enum,high,False, +chunk_6b5a4da2,src/priv/smstateen.adoc,275,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0 > State Enable Extensions > State Enable 0 Registers",The AIA bit in `mstateen0` controls access to all state introduced by the Ssaia extension and not controlled by either the CSRIND or the IMSIC bits.,CSR_controlled,enum,high,False, +chunk_3b3cb54d,src/priv/smstateen.adoc,275,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0 > State Enable Extensions > State Enable 0 Registers",The AIA bit in `hstateen0` controls access to all state introduced by the Ssaia extension and not controlled by either the CSRIND or the IMSIC bits of `hstateen0`.,CSR_controlled,enum,high,False, +chunk_130df240,src/priv/smstateen.adoc,281,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0 > State Enable Extensions > State Enable 0 Registers",The CONTEXT bit in `mstateen0` controls access to the `scontext` and `hcontext` CSRs provided by the Sdtrig extension.,CSR_controlled,enum,high,False, +chunk_00d41809,src/priv/smstateen.adoc,281,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0 > State Enable Extensions > State Enable 0 Registers",The CONTEXT bit in `hstateen0` controls access to the `scontext` CSR provided by the Sdtrig extension.,CSR_controlled,enum,high,False, +chunk_204deed5,src/priv/smstateen.adoc,286,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0 > State Enable Extensions > State Enable 0 Registers",The P1P13 bit in `mstateen0` controls access to the `hedelegh` introduced by Privileged Specification Version 1.13.,non_CSR_parameter,unknown,high,False, +chunk_45ed0a06,src/priv/smstateen.adoc,290,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0 > State Enable Extensions > State Enable 0 Registers",The SRMCFG bit in `mstateen0` controls access to the `srmcfg` CSR introduced by the Ssqosid extension.,CSR_controlled,enum,high,False, +chunk_fafdbc35,src/priv/smstateen.adoc,296,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0 > State Enable Extensions > Usage","After the writable bits of the machine-level `mstateen` CSRs are initialized to zeros on reset, machine-level software can set bits in these registers to enable less-privileged access to the controlled state.",CSR_controlled,enum,high,False, +chunk_cd6942ae,src/priv/smstateen.adoc,296,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0 > State Enable Extensions > Usage","This may be either because machine-level software knows how to swap the state or, more likely, because machine-level software isn't swapping supervisor-level environments. (Recall that the main reason the `mstateen` CSRs must exist is so machine level can emulate the hypervisor extension.",CSR_controlled,enum,very_high,False, +chunk_854cc8a1,src/priv/smstateen.adoc,296,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0 > State Enable Extensions > Usage","When machine level isn't emulating the hypervisor extension, it is likely there will be no need to keep any implemented `mstateen` bits zero.)",SW_rule,unknown,high,False, +chunk_072bab29,src/priv/smstateen.adoc,306,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0 > State Enable Extensions > Usage","If machine level sets any writable `mstateen` bits to nonzero, it must initialize the matching `hstateen` CSRs, if they exist, by writing zeros to them.",CSR_controlled,enum,very_high,False, +chunk_cc139555,src/priv/smstateen.adoc,306,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0 > State Enable Extensions > Usage","And if any `mstateen` bits that are set to one have matching bits in the `sstateen` CSRs, machine-level software must also initialize those `sstateen` CSRs by writing zeros to them.",CSR_controlled,binary,very_high,False, +chunk_0153048e,src/priv/smstateen.adoc,306,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0 > State Enable Extensions > Usage","Ordinarily, machine-level software will want to set bit 63 of all `mstateen` CSRs, necessitating that it write zero to all `hstateen` CSRs.",CSR_controlled,enum,high,False, +chunk_bed8f6e3,src/priv/smstateen.adoc,313,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0 > State Enable Extensions > Usage",Software should ensure that all writable bits of `sstateen` CSRs are initialized to zeros when an OS at supervisor level is first entered.,CSR_controlled,enum,high,False, +chunk_0c8f2b2f,src/priv/smstateen.adoc,318,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0 > State Enable Extensions > Usage","For the `sstateen` CSRs whose access by a guest OS is permitted by bit 63 of the corresponding `hstateen` CSRs, a hypervisor must include the `sstateen` CSRs in the context it swaps for a guest OS.",CSR_controlled,enum,very_high,False, +chunk_9a127dc0,src/priv/smstateen.adoc,318,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0 > State Enable Extensions > Usage","When it starts a new guest OS, it must ensure the writable bits of those `sstateen` CSRs are initialized to zeros, and it must emulate accesses to any other `sstateen` CSRs.",CSR_controlled,enum,very_high,False, +chunk_d5c477bb,src/priv/smstateen.adoc,324,"Preamble > ""Smstateen/Ssstateen"" Extensions, Version 1.0 > State Enable Extensions > Usage","If software at any privilege level does not support multiple contexts for less-privilege levels, then it may choose to maximize less-privileged access to all state by writing a value of all ones to the `stateen` CSRs at its level (the `mstateen` CSRs for machine level, the `sstateen` CSRs for an OS, and the `hstateen` CSRs for a hypervisor), without knowing all the state to which it is granting access.",CSR_controlled,enum,high,False, +chunk_645ba08b,src/priv/ssccptr.adoc,3,"Preamble > Ssccptr Extension for Main Memory Page-Table Reads, Version 1.0","If the Ssccptr extension is implemented, then main memory regions with both the cacheability and coherence PMAs must support hardware page-table reads.",SW_rule,binary,very_high,False, +chunk_38122cb5,src/priv/sscofpmf.adoc,3,"Preamble > ""Sscofpmf"" Extension for Count Overflow and Mode-Based Filtering, Version 1.0","The current Privileged specification defines mhpmevent CSRs to select and control event counting by the associated hpmcounter CSRs, but provides no standardization of any fields within these CSRs.",CSR_controlled,enum,high,False, +chunk_4cd40f48,src/priv/sscofpmf.adoc,12,"Preamble > ""Sscofpmf"" Extension for Count Overflow and Mode-Based Filtering, Version 1.0",This extension serves to accomplish exactly this within the existing mhpmevent CSRs (and correspondingly avoids the unnecessary creation of whole new sets of CSRs - past just one new CSR).,CSR_controlled,enum,high,False, +chunk_4c94a103,src/priv/sscofpmf.adoc,30,"Preamble > ""Sscofpmf"" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control",The following bits are added to `mhpmevent`:,CSR_controlled,enum,high,False, +chunk_1e59997e,src/priv/sscofpmf.adoc,32,"Preamble > ""Sscofpmf"" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control","[cols=""^1,^1,^1,^1,^1,^1,^1,^1"",stripes=even,options=""header""] | |63 |62 |61 |60 |59 |58 |57 |56 |OF |MINH |SINH |UINH |VSINH |VUINH |WPRI |WPRI |",CSR_controlled,enum,very_high,False, +chunk_f0f6efc5,src/priv/sscofpmf.adoc,38,"Preamble > ""Sscofpmf"" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control","[cols=""15%,85%"",options=""header""] | | Field | Description | OF | Overflow status and interrupt disable bit that is set when counter overflows | MINH |",unknown,enum,high,False, +chunk_a0a92c01,src/priv/sscofpmf.adoc,38,"Preamble > ""Sscofpmf"" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control","If set, then counting of events in M-mode is inhibited | SINH |",unknown,unknown,high,False, +chunk_81feab7c,src/priv/sscofpmf.adoc,38,"Preamble > ""Sscofpmf"" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control","If set, then counting of events in S/HS-mode is inhibited | UINH |",unknown,unknown,high,False, +chunk_a93cfc48,src/priv/sscofpmf.adoc,38,"Preamble > ""Sscofpmf"" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control","If set, then counting of events in U-mode is inhibited | VSINH |",unknown,unknown,high,False, +chunk_08dc351d,src/priv/sscofpmf.adoc,38,"Preamble > ""Sscofpmf"" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control","If set, then counting of events in VS-mode is inhibited | VUINH |",unknown,unknown,high,False, +chunk_4a00819f,src/priv/sscofpmf.adoc,38,"Preamble > ""Sscofpmf"" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control","If set, then counting of events in VU-mode is inhibited | WPRI | Reserved | WPRI | Reserved |",CSR_controlled,enum,very_high,False, +chunk_8b07ffdd,src/priv/sscofpmf.adoc,51,"Preamble > ""Sscofpmf"" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control","For each ``x``INH bit, if the associated privilege mode is not implemented, the bit is read-only zero.",CSR_controlled,binary,high,False, +chunk_5ec72fdd,src/priv/sscofpmf.adoc,54,"Preamble > ""Sscofpmf"" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control","Each of the five ``x``INH bits, when set, inhibit counting of events while in privilege mode ``x``.",unknown,enum,high,False, +chunk_130aea5f,src/priv/sscofpmf.adoc,54,"Preamble > ""Sscofpmf"" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control",All-zeroes for these bits results in counting of events in all modes.,non_CSR_parameter,unknown,high,False, +chunk_dc9733f3,src/priv/sscofpmf.adoc,59,"Preamble > ""Sscofpmf"" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control","The OF bit is set when the corresponding hpmcounter overflows, and remains set until written by software.",SW_rule,unknown,high,False, +chunk_b952b228,src/priv/sscofpmf.adoc,59,"Preamble > ""Sscofpmf"" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control","Since hpmcounter values are unsigned values, overflow is defined as unsigned overflow of the implemented counter bits.",unknown,unknown,high,False, +chunk_05505729,src/priv/sscofpmf.adoc,65,"Preamble > ""Sscofpmf"" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control","If supervisor mode is implemented, the 32-bit scountovf register contains read-only shadow copies of the OF bits in all 29 mhpmevent registers.",CSR_controlled,range,high,False, +chunk_41299b0f,src/priv/sscofpmf.adoc,68,"Preamble > ""Sscofpmf"" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control","If an hpmcounter overflows while the associated OF bit is zero, then a ""count overflow interrupt request"" is generated.",unknown,unknown,high,False, +chunk_552be716,src/priv/sscofpmf.adoc,68,"Preamble > ""Sscofpmf"" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control","If the OF bit is one, then no interrupt request is generated.",unknown,unknown,high,False, +chunk_57fd774b,src/priv/sscofpmf.adoc,68,"Preamble > ""Sscofpmf"" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control",Consequently the OF bit also functions as a count overflow interrupt disable for the associated hpmcounter.,unknown,unknown,high,False, +chunk_c1263bcc,src/priv/sscofpmf.adoc,74,"Preamble > ""Sscofpmf"" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control","Count overflow never results from writes to the mhpmcountern or mhpmeventn registers, only from hardware increments of counter registers.",CSR_controlled,enum,high,False, +chunk_b82df2fb,src/priv/sscofpmf.adoc,78,"Preamble > ""Sscofpmf"" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control",This count-overflow-interrupt-request signal is treated as a standard local interrupt that corresponds to bit 13 in the `mip`/`mie`/`sip`/`sie` registers.,CSR_controlled,enum,high,False, +chunk_ded338b3,src/priv/sscofpmf.adoc,78,"Preamble > ""Sscofpmf"" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control","The `mip`/`sip` LCOFIP and `mie`/`sie` LCOFIE bits are, respectively, the interrupt-pending and interrupt-enable bits for this interrupt. ('LCOFI' represents 'Local Count Overflow Interrupt'.)",CSR_controlled,enum,high,False, +chunk_02796860,src/priv/sscofpmf.adoc,84,"Preamble > ""Sscofpmf"" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control",Generation of a count-overflow-interrupt request by an `hpmcounter` sets the associated OF bit.,unknown,unknown,high,False, +chunk_dd7f2532,src/priv/sscofpmf.adoc,84,"Preamble > ""Sscofpmf"" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control","When an OF bit is set, it eventually, but not necessarily immediately, sets the LCOFIP bit in the `mip`/`sip` registers.",CSR_controlled,enum,high,False, +chunk_b5aa7906,src/priv/sscofpmf.adoc,84,"Preamble > ""Sscofpmf"" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control",The LCOFIP bit is cleared by software before servicing the count overflow interrupt resulting from one or more count overflows.,SW_rule,unknown,high,False, +chunk_4100a2ea,src/priv/sscofpmf.adoc,84,"Preamble > ""Sscofpmf"" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control",The `mideleg` register controls the delegation of this interrupt to S-mode versus M-mode.,CSR_controlled,enum,high,False, +chunk_3d279abb,src/priv/sscofpmf.adoc,94,"Preamble > ""Sscofpmf"" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control > Supervisor Count Overflow (`scountovf`) Register","This extension adds the `scountovf` CSR, a 32-bit read-only register that contains shadow copies of the OF bits in the 29 mhpmevent CSRs (mhpmevent3 - mhpmevent31) - where scountovf bit X corresponds to mhpmeventX.",CSR_controlled,range,high,False, +chunk_d0a27286,src/priv/sscofpmf.adoc,100,"Preamble > ""Sscofpmf"" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control > Supervisor Count Overflow (`scountovf`) Register",This register enables supervisor-level overflow interrupt handler software to quickly and easily determine which counter(s) have overflowed (without needing to make an execution environment call or series of calls ultimately up to M-mode).,SW_rule,unknown,high,False, +chunk_252a37a6,src/priv/sscofpmf.adoc,105,"Preamble > ""Sscofpmf"" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control > Supervisor Count Overflow (`scountovf`) Register",Read access to bit X is subject to the same mcounteren (or mcounteren and hcounteren) CSRs that mediate access to the hpmcounter CSRs by S-mode (or VS-mode).,CSR_controlled,enum,high,False, +chunk_88bcdb03,src/priv/sscofpmf.adoc,105,"Preamble > ""Sscofpmf"" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control > Supervisor Count Overflow (`scountovf`) Register","In M-mode, scountovf bit X is always readable.",unknown,unknown,high,False, +chunk_5ea06e91,src/priv/sscofpmf.adoc,105,"Preamble > ""Sscofpmf"" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control > Supervisor Count Overflow (`scountovf`) Register","In S/HS-mode, scountovf bit X is readable when mcounteren bit X is set, and otherwise reads as zero.",CSR_controlled,enum,high,False, +chunk_6187dfa9,src/priv/sscofpmf.adoc,105,"Preamble > ""Sscofpmf"" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control > Supervisor Count Overflow (`scountovf`) Register","Similarly, in VS mode, scountovf bit X is readable when mcounteren bit X and hcounteren bit X are both set, and otherwise reads as zero.",CSR_controlled,enum,high,False, +chunk_79a40914,src/priv/sscounterenw.adoc,3,"Preamble > Sscounterenw Extension for Counter-Enable Writability, Version 1.0","If the Sscounterenw extension is implemented, then for any `hpmcounter` that is not read-only zero, the corresponding bit in `scounteren` must be writable.",CSR_controlled,binary,very_high,False, +chunk_9be67576,src/priv/ssdbltrp.adoc,3,"Preamble > ""Ssdbltrp"" Double Trap Extension, Version 1.0",It enables HS-mode to invoke a critical error handler in a virtual machine on a double trap in VS-mode.,unknown,unknown,high,False, +chunk_1a45ecb6,src/priv/ssdbltrp.adoc,3,"Preamble > ""Ssdbltrp"" Double Trap Extension, Version 1.0",It also allows M-mode to invoke a critical error handler in the OS/Hypervisor on a double trap in S/HS-mode.,SW_rule,unknown,high,False, +chunk_14c95ffe,src/priv/ssqosid.adoc,8,"Preamble > ""Ssqosid"" Extension for Quality-of-Service (QoS) Identifiers, Version 1.0","When multiple workloads execute concurrently on modern processors—equipped with large core counts, multiple cache hierarchies, and multiple memory controllers— the performance of any given workload becomes less deterministic, or even non-deterministic, due to shared resource contention.",unknown,unknown,high,False, +chunk_4971e847,src/priv/ssqosid.adoc,13,"Preamble > ""Ssqosid"" Extension for Quality-of-Service (QoS) Identifiers, Version 1.0","For resource management, hardware should provide monitoring features that allow system software to profile workload resource consumption and allocate resources accordingly.",SW_rule,enum,medium,False, +chunk_a67581c7,src/priv/ssqosid.adoc,26,"Preamble > ""Ssqosid"" Extension for Quality-of-Service (QoS) Identifiers, Version 1.0",Resource controllers may use this metadata for differentiated service such as a different capacity allocation for code storage vs. data storage.,non_CSR_parameter,enum,medium,False, +chunk_0f7c8806,src/priv/ssqosid.adoc,44,"Preamble > ""Ssqosid"" Extension for Quality-of-Service (QoS) Identifiers, Version 1.0 > Supervisor Resource Management Configuration (`srmcfg`) register",The `srmcfg` register is an SXLEN-bit read/write register used to configure a Resource Control ID (`RCID`) and a Monitoring Counter ID (`MCID`).,CSR_controlled,range,high,False, +chunk_ab60fe2b,src/priv/ssqosid.adoc,44,"Preamble > ""Ssqosid"" Extension for Quality-of-Service (QoS) Identifiers, Version 1.0 > Supervisor Resource Management Configuration (`srmcfg`) register",Both `RCID` and `MCID` are WARL fields.,CSR_controlled,enum,very_high,False, +chunk_9ce9cb34,src/priv/ssqosid.adoc,44,"Preamble > ""Ssqosid"" Extension for Quality-of-Service (QoS) Identifiers, Version 1.0 > Supervisor Resource Management Configuration (`srmcfg`) register",The register is formatted as shown in when SXLEN=64 and when SXLEN=32.,unknown,unknown,high,False, +chunk_665022e4,src/priv/ssqosid.adoc,49,"Preamble > ""Ssqosid"" Extension for Quality-of-Service (QoS) Identifiers, Version 1.0 > Supervisor Resource Management Configuration (`srmcfg`) register",The `RCID` and `MCID` accompany each request made by the hart to shared resource controllers.,unknown,unknown,high,False, +chunk_822de12c,src/priv/ssqosid.adoc,49,"Preamble > ""Ssqosid"" Extension for Quality-of-Service (QoS) Identifiers, Version 1.0 > Supervisor Resource Management Configuration (`srmcfg`) register",The `MCID` is used to identify a counter to monitor resource usage.,unknown,unknown,high,False, +chunk_bc2e8718,src/priv/ssqosid.adoc,80,"Preamble > ""Ssqosid"" Extension for Quality-of-Service (QoS) Identifiers, Version 1.0 > Supervisor Resource Management Configuration (`srmcfg`) register","The `RCID` and `MCID` configured in the `srmcfg` CSR apply to all privilege modes of software execution on that hart by default, but this behavior may be overridden by future extensions.",CSR_controlled,enum,high,False, +chunk_9df40c16,src/priv/ssqosid.adoc,84,"Preamble > ""Ssqosid"" Extension for Quality-of-Service (QoS) Identifiers, Version 1.0 > Supervisor Resource Management Configuration (`srmcfg`) register","If extension Smstateen is implemented together with Ssqosid, then Ssqosid also requires the SRMCFG bit in `mstateen0` to be implemented.",non_CSR_parameter,unknown,high,False, +chunk_3a72c478,src/priv/ssqosid.adoc,84,"Preamble > ""Ssqosid"" Extension for Quality-of-Service (QoS) Identifiers, Version 1.0 > Supervisor Resource Management Configuration (`srmcfg`) register","If `mstateen0`.SRMCFG is 0, attempts to access `srmcfg` in privilege modes less privileged than M-mode raise an illegal-instruction exception.",non_CSR_parameter,enum,high,False, +chunk_2bc0efa4,src/priv/ssqosid.adoc,84,"Preamble > ""Ssqosid"" Extension for Quality-of-Service (QoS) Identifiers, Version 1.0 > Supervisor Resource Management Configuration (`srmcfg`) register","If `mstateen0`.SRMCFG is 1 or if extension Smstateen is not implemented, attempts to access `srmcfg` when `V=1` raise a virtual-instruction exception.",non_CSR_parameter,unknown,high,False, +chunk_9ac14be5,src/priv/ssstrict.adoc,3,"Preamble > Ssstrict Extension for Extension Conformance, Version 1.0","If the Ssstrict extension is implemented, then no non-conforming extensions are present.",unknown,unknown,high,False, +chunk_efac294c,src/priv/ssstrict.adoc,3,"Preamble > Ssstrict Extension for Extension Conformance, Version 1.0","Furthermore, attempts to execute unimplemented opcodes or access unimplemented CSRs in the standard or reserved encoding spaces raises an illegal instruction exception that results in a contained trap to the supervisor-mode trap handler.",CSR_controlled,enum,high,False, +chunk_73f30ac9,src/priv/sstc.adoc,3,"Preamble > ""Sstc"" Extension for Supervisor-mode Timer Interrupts, Version 1.0",The current Privileged arch specification only defines a hardware mechanism for generating machine-mode timer interrupts (based on the mtime and mtimecmp registers).,unknown,unknown,high,False, +chunk_b1a7a46d,src/priv/sstc.adoc,3,"Preamble > ""Sstc"" Extension for Supervisor-mode Timer Interrupts, Version 1.0","With the resultant requirement that timer services for S-mode/HS-mode (and for VS-mode) have to all be provided by M-mode - via SBI calls from S/HS-mode up to M-mode (or VS-mode calls to HS-mode and then to M-mode). M-mode software then multiplexes these multiple logical timers onto its one physical M-mode timer facility, and the M-mode timer interrupt handler passes timer interrupts back down to the appropriate lower privilege mode.",SW_rule,enum,high,False, +chunk_d23fd309,src/priv/sstc.adoc,12,"Preamble > ""Sstc"" Extension for Supervisor-mode Timer Interrupts, Version 1.0",This extension serves to provide supervisor mode with its own CSR-based timer interrupt facility that it can directly manage to provide its own timer service (in the form of having its own `stimecmp` register) - thus eliminating the large overheads for emulating S/HS-mode timers and timer interrupt generation up in M-mode.,CSR_controlled,enum,high,False, +chunk_e641060d,src/priv/sstc.adoc,19,"Preamble > ""Sstc"" Extension for Supervisor-mode Timer Interrupts, Version 1.0",This extension adds the S-level `stimecmp` CSR () and the VS-level `vstimecmp` CSR ().,CSR_controlled,enum,high,False, +chunk_27458ddc,src/priv/sstc.adoc,19,"Preamble > ""Sstc"" Extension for Supervisor-mode Timer Interrupts, Version 1.0",This extension adds the `STCE` bit to the `menvcfg` () and `henvcfg` () CSRs.,CSR_controlled,enum,high,False, +chunk_57aa35ec,src/priv/sstvala.adoc,3,"Preamble > Sstvala Extension for Trap Value Reporting, Version 1.0","If the Sstvala extension is implemented, then `stval` must be written with the faulting virtual address for load, store, and instruction page-fault, access-fault, and misaligned exceptions, and for breakpoint exceptions that are defined to write an address to stval, other than those caused by execution of the `EBREAK` or `C.EBREAK` instructions.",CSR_controlled,enum,very_high,False, +chunk_b78e9bc7,src/priv/sstvala.adoc,3,"Preamble > Sstvala Extension for Trap Value Reporting, Version 1.0","For virtual-instruction and illegal-instruction exceptions, `stval` must be written with the faulting instruction.",CSR_controlled,enum,very_high,False, +chunk_41405924,src/priv/sstvecd.adoc,3,"Preamble > Sstvecd Extension for Direct Trap Vectoring, Version 1.0","If the Sstvecd extension is implemented, then `stvec.MODE` must be capable of holding the value 0 (Direct).",CSR_controlled,enum,very_high,False, +chunk_48cc8229,src/priv/sstvecd.adoc,3,"Preamble > Sstvecd Extension for Direct Trap Vectoring, Version 1.0","Furthermore, when `stvec.MODE=Direct`, `stvec.BASE` must be capable of holding any valid four-byte-aligned address.",CSR_controlled,enum,very_high,False, +chunk_a1fc1e3b,src/priv/ssu64xl.adoc,3,"Preamble > Ssu64xl Extension for UXLEN=64 Support, Version 1.0","If the Ssu64xl extension is implemented, then `sstatus.UXL` must be capable of holding the value 2 (i.e., UXLEN=64 must be supported).",CSR_controlled,enum,very_high,False, +chunk_f25654ae,src/priv/supervisor.adoc,9,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs",A number of CSRs are provided for the supervisor.,CSR_controlled,enum,high,False, +chunk_54181556,src/priv/supervisor.adoc,14,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register",The `sstatus` register is an SXLEN-bit read/write register formatted as shown in when SXLEN=32 and when SXLEN=64.,CSR_controlled,range,high,False, +chunk_63e0692e,src/priv/supervisor.adoc,14,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register",The `sstatus` register keeps track of the processor's current operating state.,CSR_controlled,enum,high,False, +chunk_de778c2a,src/priv/supervisor.adoc,76,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register",The SPP bit indicates the privilege level at which a hart was executing before entering supervisor mode.,unknown,enum,high,False, +chunk_63987dc9,src/priv/supervisor.adoc,76,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register","When a trap is taken, SPP is set to 0 if the trap originated from user mode, or 1 otherwise.",unknown,binary,high,False, +chunk_71dbf032,src/priv/supervisor.adoc,85,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register",The SIE bit enables or disables all interrupts in supervisor mode.,CSR_controlled,enum,high,False, +chunk_aa5b09d7,src/priv/supervisor.adoc,85,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register","When SIE is clear, interrupts are not taken while in supervisor mode.",CSR_controlled,enum,high,False, +chunk_747cd038,src/priv/supervisor.adoc,85,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register","When the hart is running in user-mode, the value in SIE is ignored, and supervisor-level interrupts are enabled.",CSR_controlled,binary,high,False, +chunk_f3430c38,src/priv/supervisor.adoc,85,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register",The supervisor can disable individual interrupt sources using the `sie` CSR.,CSR_controlled,enum,high,False, +chunk_885fa826,src/priv/supervisor.adoc,92,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register",The SPIE bit indicates whether supervisor interrupts were enabled prior to trapping into supervisor mode.,unknown,binary,high,False, +chunk_835eed4b,src/priv/supervisor.adoc,92,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register","When a trap is taken into supervisor mode, SPIE is set to SIE, and SIE is set to 0.",CSR_controlled,binary,high,False, +chunk_7b81b37f,src/priv/supervisor.adoc,92,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register","When an SRET instruction is executed, SIE is set to SPIE, then SPIE is set to 1.",CSR_controlled,binary,high,False, +chunk_d67668e0,src/priv/supervisor.adoc,98,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register",The `sstatus` register is a subset of the `mstatus` register.,CSR_controlled,enum,high,False, +chunk_fe705b60,src/priv/supervisor.adoc,102,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Base ISA Control in `sstatus` Register","The UXL field controls the value of XLEN for U-mode, termed UXLEN, which may differ from the value of XLEN for S-mode, termed SXLEN.",non_CSR_parameter,enum,high,False, +chunk_3fc59373,src/priv/supervisor.adoc,102,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Base ISA Control in `sstatus` Register","The encoding of UXL is the same as that of the MXL field of `misa`, shown in .",unknown,enum,high,False, +chunk_5997f0a7,src/priv/supervisor.adoc,108,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Base ISA Control in `sstatus` Register","When SXLEN=32, the UXL field does not exist, and UXLEN=32.",unknown,enum,high,False, +chunk_8f23f2a7,src/priv/supervisor.adoc,108,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Base ISA Control in `sstatus` Register","When SXLEN=64, it is a *WARL* field that encodes the current value of UXLEN.",CSR_controlled,enum,very_high,False, +chunk_65977b71,src/priv/supervisor.adoc,108,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Base ISA Control in `sstatus` Register","In particular, an implementation may make UXL be a read-only field whose value always ensures that UXLEN=SXLEN.",CSR_controlled,enum,high,False, +chunk_da142b34,src/priv/supervisor.adoc,114,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Base ISA Control in `sstatus` Register","If UXLEN!=SXLEN, instructions executed in the narrower mode must ignore source register operand bits above the configured XLEN, and must sign-extend results to fill the widest supported XLEN in the destination register.",non_CSR_parameter,binary,very_high,False, +chunk_5c7ca72c,src/priv/supervisor.adoc,120,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Base ISA Control in `sstatus` Register","If UXLEN < SXLEN, user-mode instruction-fetch addresses and load and store effective addresses are taken modulo 2^UXLEN^.",unknown,unknown,high,False, +chunk_edc7df9b,src/priv/supervisor.adoc,125,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Base ISA Control in `sstatus` Register","When such a HINT is executed with XLEN < SXLEN and bits SXLEN..XLEN of the destination register not all equal to bit XLEN-1, it is implementation-defined whether bits SXLEN..XLEN of the destination register are unchanged or are overwritten with copies of bit XLEN-1.",non_CSR_parameter,range,high,False, +chunk_e24766a0,src/priv/supervisor.adoc,134,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Base ISA Control in `sstatus` Register",The implementation choice is observable only by S-mode with SXLEN > UXLEN; it is invisible to U-mode.,unknown,unknown,high,False, +chunk_0250015b,src/priv/supervisor.adoc,143,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Memory Privilege in `sstatus` Register",The MXR (Make eXecutable Readable) bit modifies the privilege with which loads access virtual memory.,unknown,unknown,high,False, +chunk_cb5c0166,src/priv/supervisor.adoc,143,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Memory Privilege in `sstatus` Register","When MXR=0, only loads from pages marked readable (R=1 in ) will succeed.",unknown,unknown,high,False, +chunk_a44d7762,src/priv/supervisor.adoc,143,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Memory Privilege in `sstatus` Register","When MXR=1, loads from pages marked either readable or executable (R=1 or X=1) will succeed. MXR has no effect when page-based virtual memory is not in effect.",unknown,enum,high,False, +chunk_50c3324c,src/priv/supervisor.adoc,151,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Memory Privilege in `sstatus` Register",The SUM (permit Supervisor User Memory access) bit modifies the privilege with which S-mode loads and stores access virtual memory.,unknown,unknown,high,False, +chunk_17a302c5,src/priv/supervisor.adoc,151,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Memory Privilege in `sstatus` Register","When SUM=0, S-mode memory accesses to pages that are accessible by U-mode (U=1 in ) will fault.",unknown,unknown,high,False, +chunk_cd21ff8c,src/priv/supervisor.adoc,151,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Memory Privilege in `sstatus` Register","When SUM=1, these accesses are permitted. SUM has no effect when page-based virtual memory is not in effect, nor when executing in U-mode.",unknown,unknown,high,False, +chunk_d93e9f16,src/priv/supervisor.adoc,161,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Memory Privilege in `sstatus` Register",SUM is read-only 0 if `satp`.MODE is read-only 0.,CSR_controlled,enum,high,False, +chunk_92c68a14,src/priv/supervisor.adoc,166,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Endianness Control in `sstatus` Register","The UBE bit is a *WARL* field that controls the endianness of explicit memory accesses made from U-mode, which may differ from the endianness of memory accesses in S-mode.",CSR_controlled,enum,very_high,False, +chunk_1a29bfb8,src/priv/supervisor.adoc,166,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Endianness Control in `sstatus` Register",An implementation may make UBE be a read-only field that always specifies the same endianness as for S-mode.,CSR_controlled,enum,high,False, +chunk_75f4203b,src/priv/supervisor.adoc,172,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Endianness Control in `sstatus` Register",UBE controls whether explicit load and store memory accesses made from U-mode are little-endian (UBE=0) or big-endian (UBE=1).,non_CSR_parameter,unknown,high,False, +chunk_1447b71c,src/priv/supervisor.adoc,175,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Endianness Control in `sstatus` Register","UBE has no effect on instruction fetches, which are implicit memory accesses that are always little-endian.",unknown,unknown,high,False, +chunk_4a83dc5c,src/priv/supervisor.adoc,179,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Endianness Control in `sstatus` Register","For implicit accesses to supervisor-level memory management data structures, such as page tables, S-mode endianness always applies and UBE is ignored.",unknown,unknown,high,False, +chunk_83157bc9,src/priv/supervisor.adoc,185,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Previous Expected Landing Pad (ELP) State in `sstatus` Register","Access to the `SPELP` field, added by Zicfilp, accesses the homonymous fields of `mstatus` when `V=0`, and the homonymous fields of `vsstatus` when `V=1`.",CSR_controlled,enum,high,False, +chunk_17d9aa3a,src/priv/supervisor.adoc,198,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Double Trap Control in `sstatus` Register","When the `SDT` bit is set to 1 by an explicit CSR write, the `SIE` (Supervisor Interrupt Enable) bit is cleared to 0.",CSR_controlled,binary,high,False, +chunk_15550752,src/priv/supervisor.adoc,198,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Double Trap Control in `sstatus` Register","This clearing occurs regardless of the value written, if any, to the `SIE` bit by the same write.",CSR_controlled,enum,high,False, +chunk_b242f0d1,src/priv/supervisor.adoc,198,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Double Trap Control in `sstatus` Register",The `SIE` bit can only be set to 1 by an explicit CSR write if the `SDT` bit is being set to 0 by the same write or is already 0.,CSR_controlled,binary,high,False, +chunk_40c9933b,src/priv/supervisor.adoc,205,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Double Trap Control in `sstatus` Register","When a trap is to be taken into S-mode, if the `SDT` bit is currently 0, it is then set to 1, and the trap is delivered as expected.",unknown,binary,high,False, +chunk_84d67d22,src/priv/supervisor.adoc,205,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Double Trap Control in `sstatus` Register","However, if `SDT` is already set to 1, then this is an unexpected trap.",unknown,binary,high,False, +chunk_3b054108,src/priv/supervisor.adoc,205,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Double Trap Control in `sstatus` Register","In the event of an unexpected trap, a double-trap exception trap is delivered into M-mode.",unknown,unknown,high,False, +chunk_c75db91f,src/priv/supervisor.adoc,205,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Double Trap Control in `sstatus` Register","To deliver this trap, the hart writes registers, except `mcause` and `mtval2`, with the same information that the unexpected trap would have written if it was taken into M-mode.",CSR_controlled,enum,high,False, +chunk_d579b146,src/priv/supervisor.adoc,205,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Double Trap Control in `sstatus` Register",The `mtval2` register is then set to what would be otherwise written into the `mcause` register by the unexpected trap.,CSR_controlled,enum,high,False, +chunk_7a4d3133,src/priv/supervisor.adoc,205,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Double Trap Control in `sstatus` Register","The `mcause` register is set to 16, the double-trap exception code.",CSR_controlled,binary,high,False, +chunk_e8e5d179,src/priv/supervisor.adoc,216,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Double Trap Control in `sstatus` Register",An `SRET` instruction sets the `SDT` bit to 0.,unknown,unknown,high,False, +chunk_00231009,src/priv/supervisor.adoc,221,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Vector Base Address (`stvec`) Register","The `stvec` register is an SXLEN-bit read/write register that holds trap vector configuration, consisting of a vector base address (BASE) and a vector mode (MODE).",CSR_controlled,range,high,False, +chunk_77594abf,src/priv/supervisor.adoc,230,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Vector Base Address (`stvec`) Register","The BASE field in `stvec` is a field that can hold any valid virtual or physical address, subject to the following alignment constraints: the address must be 4-byte aligned, and MODE settings other than Direct might impose additional alignment constraints on the value in the BASE field.",CSR_controlled,range,very_high,False, +chunk_a9728561,src/priv/supervisor.adoc,230,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Vector Base Address (`stvec`) Register","When used as an address, the lower two bits are filled with zeroes to obtain an XLEN-bit address that is always aligned on a 4-byte boundary.",non_CSR_parameter,range,high,False, +chunk_5a617a99,src/priv/supervisor.adoc,256,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Vector Base Address (`stvec`) Register",The encoding of the MODE field is shown in .,unknown,enum,high,False, +chunk_39b32a6a,src/priv/supervisor.adoc,256,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Vector Base Address (`stvec`) Register","When MODE=Direct, all traps into supervisor mode cause the `pc` to be set to the address in the BASE field.",unknown,enum,high,False, +chunk_210ff355,src/priv/supervisor.adoc,256,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Vector Base Address (`stvec`) Register","When MODE=Vectored, all synchronous exceptions into supervisor mode cause the `pc` to be set to the address in the BASE field, whereas interrupts cause the `pc` to be set to the address in the BASE field plus four times the interrupt cause number.",unknown,enum,high,False, +chunk_06b51d51,src/priv/supervisor.adoc,256,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Vector Base Address (`stvec`) Register",Setting MODE=Vectored may impose a stricter alignment constraint on BASE.,non_CSR_parameter,enum,high,False, +chunk_3ba5c989,src/priv/supervisor.adoc,269,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers","The `sip` register is an SXLEN-bit read/write register containing information on pending interrupts, while `sie` is the corresponding SXLEN-bit read/write register containing interrupt enable bits.",CSR_controlled,range,high,False, +chunk_02b70345,src/priv/supervisor.adoc,269,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers","Interrupt cause number i (as reported in CSR `scause`, ) corresponds with bit i in both `sip` and `sie`.",CSR_controlled,enum,high,False, +chunk_d6824594,src/priv/supervisor.adoc,269,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers","Bits 15:0 are allocated to standard interrupt causes only, while bits 16 and above are designated for platform use.",unknown,unknown,high,False, +chunk_e26004db,src/priv/supervisor.adoc,284,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers","An interrupt i will trap to S-mode if both of the following are true: (a) either the current privilege mode is S and the SIE bit in the `sstatus` register is set, or the current privilege mode has less privilege than S-mode; and (b) bit i is set in both `sip` and `sie`.",CSR_controlled,enum,high,False, +chunk_e840808b,src/priv/supervisor.adoc,290,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers","These conditions for an interrupt trap to occur must be evaluated in a bounded amount of time from when an interrupt becomes, or ceases to be, pending in `sip`, and must also be evaluated immediately following the execution of an SRET instruction or an explicit write to a CSR on which these interrupt trap conditions expressly depend (including `sip`, `sie` and `sstatus`).",CSR_controlled,enum,very_high,False, +chunk_1b0a0ccb,src/priv/supervisor.adoc,298,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers",Interrupts to S-mode take priority over any interrupts to lower privilege modes.,unknown,enum,high,False, +chunk_bba95e36,src/priv/supervisor.adoc,302,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers",Each individual bit in register `sip` may be writable or may be read-only.,CSR_controlled,enum,high,False, +chunk_2898268e,src/priv/supervisor.adoc,302,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers","When bit i in `sip` is writable, a pending interrupt i can be cleared by writing 0 to this bit.",CSR_controlled,enum,high,False, +chunk_66af41fd,src/priv/supervisor.adoc,302,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers","If interrupt i can become pending but bit i in `sip` is read-only, the implementation must provide some other mechanism for clearing the pending interrupt (which may involve a call to the execution environment).",CSR_controlled,enum,very_high,False, +chunk_4d36b896,src/priv/supervisor.adoc,309,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers",A bit in `sie` must be writable if the corresponding interrupt can ever become pending.,CSR_controlled,enum,very_high,False, +chunk_f1ea7265,src/priv/supervisor.adoc,309,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers",Bits of `sie` that are not writable are read-only zero.,CSR_controlled,binary,high,False, +chunk_dfca4c2f,src/priv/supervisor.adoc,312,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers",The standard portions (bits 15:0) of registers `sip` and `sie` are formatted as shown in Figures and respectively.,CSR_controlled,enum,high,False, +chunk_9de9f2ad,src/priv/supervisor.adoc,325,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers",Bits `sip`.SEIP and `sie`.SEIE are the interrupt-pending and interrupt-enable bits for supervisor-level external interrupts.,CSR_controlled,enum,high,False, +chunk_0d622e7c,src/priv/supervisor.adoc,332,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers",Bits `sip`.STIP and `sie`.STIE are the interrupt-pending and interrupt-enable bits for supervisor-level timer interrupts.,CSR_controlled,enum,high,False, +chunk_5f722d8b,src/priv/supervisor.adoc,332,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers","If implemented, STIP is read-only in `sip`.",CSR_controlled,enum,high,False, +chunk_8e179382,src/priv/supervisor.adoc,332,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers","When the Sstc extension is not implemented, STIP is set and cleared by the execution environment.",SW_rule,unknown,high,False, +chunk_13ac4f3f,src/priv/supervisor.adoc,332,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers","When the Sstc extension is implemented, STIP reflects the timer interrupt signal resulting from `stimecmp`.",unknown,unknown,high,False, +chunk_8a6d9942,src/priv/supervisor.adoc,332,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers","The `sip`.STIP bit, in response to timer interrupts generated by `stimecmp`, is set by writing `stimecmp` with a value that is less than or equal to `time`, and is cleared by writing `stimecmp` with a value greater than `time`.",CSR_controlled,range,high,False, +chunk_e286e6e6,src/priv/supervisor.adoc,342,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers",Bits `sip`.SSIP and `sie`.SSIE are the interrupt-pending and interrupt-enable bits for supervisor-level software interrupts.,CSR_controlled,enum,high,False, +chunk_687c427e,src/priv/supervisor.adoc,342,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers","If implemented, SSIP is writable in `sip` and may also be set to 1 by a platform-specific interrupt controller.",CSR_controlled,binary,high,False, +chunk_ce48dba0,src/priv/supervisor.adoc,348,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers","If the Sscofpmf extension is implemented, bits `sip`.LCOFIP and `sie`.LCOFIE are the interrupt-pending and interrupt-enable bits for local-counter-overflow interrupts. LCOFIP is read-write in `sip` and reflects the occurrence of a local counter-overflow overflow interrupt request resulting from any of the `mhpmeventn`.OF bits being set.",CSR_controlled,enum,high,False, +chunk_e5e80644,src/priv/supervisor.adoc,348,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers","If the Sscofpmf extension is not implemented, `sip`.LCOFIP and `sie`.LCOFIE are read-only zeros.",CSR_controlled,binary,high,False, +chunk_3ef8a2ea,src/priv/supervisor.adoc,358,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers","Each standard interrupt type (SEI, STI, SSI, or LCOFI) may not be implemented, in which case the corresponding interrupt-pending and interrupt-enable bits are read-only zeros.",CSR_controlled,binary,high,False, +chunk_f4e7f983,src/priv/supervisor.adoc,358,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers",All bits in `sip` and `sie` are *WARL* fields.,CSR_controlled,enum,very_high,False, +chunk_0a8b3905,src/priv/supervisor.adoc,358,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers","The implemented interrupts may be found by writing one to every bit location in `sie`, then reading back to see which bit positions hold a one.",CSR_controlled,enum,high,False, +chunk_d9e3a039,src/priv/supervisor.adoc,365,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers","Multiple simultaneous interrupts destined for supervisor mode are handled in the following decreasing priority order: SEI, SSI, STI, LCOFI.",unknown,unknown,high,False, +chunk_f9d6825c,src/priv/supervisor.adoc,372,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Timers and Performance Counters","Supervisor software uses the same hardware performance monitoring facility as user-mode software, including the `time`, `cycle`, and `instret` CSRs.",CSR_controlled,enum,high,False, +chunk_73704ba3,src/priv/supervisor.adoc,372,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Timers and Performance Counters",The implementation should provide a mechanism to modify the counter values.,non_CSR_parameter,enum,high,False, +chunk_1bab23f3,src/priv/supervisor.adoc,377,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Timers and Performance Counters","The implementation must provide a facility for scheduling timer interrupts in terms of the real-time counter, `time`.",non_CSR_parameter,binary,very_high,False, +chunk_e30c42e7,src/priv/supervisor.adoc,386,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Counter-Enable (`scounteren`) Register",The counter-enable (`scounteren`) CSR is a 32-bit register that controls the availability of the hardware performance monitoring counters to U-mode.,CSR_controlled,range,high,False, +chunk_a3836258,src/priv/supervisor.adoc,391,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Counter-Enable (`scounteren`) Register","When the CY, TM, IR, or HPMn bit in the `scounteren` register is clear, attempts to read the `cycle`, `time`, `instret`, or `hpmcountern` register while executing in U-mode will cause an illegal-instruction exception.",CSR_controlled,enum,high,False, +chunk_630a5ab0,src/priv/supervisor.adoc,391,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Counter-Enable (`scounteren`) Register","When one of these bits is set, access to the corresponding register is permitted.",unknown,enum,high,False, +chunk_36674757,src/priv/supervisor.adoc,398,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Counter-Enable (`scounteren`) Register",`scounteren` must be implemented.,CSR_controlled,enum,very_high,False, +chunk_c0984d7c,src/priv/supervisor.adoc,398,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Counter-Enable (`scounteren`) Register","However, any of the bits may be read-only zero, indicating reads to the corresponding counter will cause an exception when executing in U-mode.",CSR_controlled,binary,high,False, +chunk_af89893f,src/priv/supervisor.adoc,398,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Counter-Enable (`scounteren`) Register","Hence, they are effectively *WARL* fields.",CSR_controlled,enum,very_high,False, +chunk_cb25cead,src/priv/supervisor.adoc,406,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Scratch (`sscratch`) Register","The `sscratch` CSR is an SXLEN-bit read/write register, dedicated for use by the supervisor.",CSR_controlled,range,high,False, +chunk_54fcf669,src/priv/supervisor.adoc,406,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Scratch (`sscratch`) Register","At the beginning of a trap handler, software normally uses a CSRRW instruction to swap `sscratch` with an integer register to obtain an initial working register.",CSR_controlled,enum,high,False, +chunk_52c689a6,src/priv/supervisor.adoc,420,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Exception Program Counter (`sepc`) Register",`sepc` is an SXLEN-bit read/write CSR formatted as shown in .,CSR_controlled,range,high,False, +chunk_2a06c1f4,src/priv/supervisor.adoc,420,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Exception Program Counter (`sepc`) Register",The low bit of `sepc` (`sepc[0]`) is always zero.,CSR_controlled,enum,high,False, +chunk_41cf0693,src/priv/supervisor.adoc,424,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Exception Program Counter (`sepc`) Register",This masking occurs also for the implicit read by the SRET instruction.,unknown,unknown,high,False, +chunk_825b6a5c,src/priv/supervisor.adoc,424,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Exception Program Counter (`sepc`) Register","Though masked, `sepc[1]` remains writable when IALIGN=32.",CSR_controlled,enum,high,False, +chunk_101f499a,src/priv/supervisor.adoc,431,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Exception Program Counter (`sepc`) Register",`sepc` is a *WARL* register that must be able to hold all valid virtual addresses.,CSR_controlled,enum,very_high,False, +chunk_e444caf5,src/priv/supervisor.adoc,431,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Exception Program Counter (`sepc`) Register",It need not be capable of holding all possible invalid addresses.,non_CSR_parameter,enum,high,False, +chunk_13c29364,src/priv/supervisor.adoc,431,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Exception Program Counter (`sepc`) Register","Prior to writing `sepc`, implementations may convert an invalid address into some other invalid address that `sepc` is capable of holding.",CSR_controlled,enum,high,False, +chunk_6e028514,src/priv/supervisor.adoc,438,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Exception Program Counter (`sepc`) Register","When a trap is taken into S-mode, `sepc` is written with the virtual address of the instruction that was interrupted or that encountered the exception.",CSR_controlled,enum,high,False, +chunk_159c42e7,src/priv/supervisor.adoc,438,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Exception Program Counter (`sepc`) Register","Otherwise, `sepc` is never written by the implementation, though it may be explicitly written by software.",CSR_controlled,enum,high,False, +chunk_a50bbb18,src/priv/supervisor.adoc,451,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Cause (`scause`) Register",The `scause` CSR is an SXLEN-bit read-write register formatted as shown in .,CSR_controlled,range,high,False, +chunk_67f5898e,src/priv/supervisor.adoc,451,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Cause (`scause`) Register","When a trap is taken into S-mode, `scause` is written with a code indicating the event that caused the trap.",CSR_controlled,enum,high,False, +chunk_e96a903b,src/priv/supervisor.adoc,451,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Cause (`scause`) Register","Otherwise, `scause` is never written by the implementation, though it may be explicitly written by software.",CSR_controlled,enum,high,False, +chunk_1d4f67c9,src/priv/supervisor.adoc,458,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Cause (`scause`) Register",The Interrupt bit in the `scause` register is set if the trap was caused by an interrupt.,CSR_controlled,enum,high,False, +chunk_6bcd2f21,src/priv/supervisor.adoc,458,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Cause (`scause`) Register",The Exception Code field contains a code identifying the last exception or interrupt. lists the possible exception codes for the current supervisor ISAs.,unknown,enum,high,False, +chunk_4b58b9ae,src/priv/supervisor.adoc,458,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Cause (`scause`) Register",The Exception Code is a *WLRL* field.,CSR_controlled,enum,very_high,False, +chunk_a8e5c3cd,src/priv/supervisor.adoc,458,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Cause (`scause`) Register","It is required to hold the values 0–31 (i.e., bits 4–0 must be implemented), but otherwise it is only guaranteed to hold supported exception codes.",non_CSR_parameter,binary,very_high,False, +chunk_7f6cc73e,src/priv/supervisor.adoc,471,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Cause (`scause`) Register",Synchronous exception priorities are given by . | |Interrupt |Exception Code |Description |1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 |0 + 1 + 2-4 + 5 + 6-8 + 9 + 10-12 + 13 + 14-15 + {ge}16 |Reserved + Supervisor software interrupt + Reserved + Supervisor timer interrupt + Reserved + Supervisor external interrupt + Reserved + Counter-overflow interrupt + Reserved + Designated for platform use,SW_rule,unknown,high,False, +chunk_69ea684c,src/priv/supervisor.adoc,507,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Cause (`scause`) Register",|0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 |0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10-11 + 12 + 13 + 14 + 15 + 16-17 + 18 + 19 + 20-23 + 24-31 + 32-47 + 48-63 + {ge}64 |Instruction address misaligned + Instruction access fault + Illegal instruction + Breakpoint + Load address misaligned + Load access fault + Store/AMO address misaligned + Store/AMO access fault + Environment call from U-mode + Environment call from S-mode + Reserved + Instruction page fault + Load page fault + Reserved + Store/AMO page fault + Reserved + Software check + Hardware error + Reserved + Designated for custom use + Reserved + Designated for custom use + Reserved |,SW_rule,unknown,high,False, +chunk_4d4b4f96,src/priv/supervisor.adoc,580,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Value (`stval`) Register",The `stval` CSR is an SXLEN-bit read-write register formatted as shown in .,CSR_controlled,range,high,False, +chunk_02bf8bfb,src/priv/supervisor.adoc,580,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Value (`stval`) Register","When a trap is taken into S-mode, `stval` is written with exception-specific information to assist software in handling the trap.",CSR_controlled,enum,high,False, +chunk_21d221cd,src/priv/supervisor.adoc,580,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Value (`stval`) Register","Otherwise, `stval` is never written by the implementation, though it may be explicitly written by software.",CSR_controlled,enum,high,False, +chunk_a6011783,src/priv/supervisor.adoc,580,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Value (`stval`) Register","The hardware platform will specify which exceptions must set `stval` informatively, which may unconditionally set it to zero, and which may exhibit either behavior, depending on the underlying event that caused the exception.",CSR_controlled,enum,very_high,False, +chunk_6e67ec91,src/priv/supervisor.adoc,591,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Value (`stval`) Register","If `stval` is written with a nonzero value when a breakpoint, address-misaligned, access-fault, page-fault, or hardware-error exception occurs on an instruction fetch, load, or store, then `stval` will contain the faulting virtual address.",CSR_controlled,enum,high,False, +chunk_780a1717,src/priv/supervisor.adoc,598,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Value (`stval`) Register","On a breakpoint exception raised by an EBREAK or C.EBREAK instruction, `stval` is written with either zero or the virtual address of the instruction.",CSR_controlled,enum,high,False, +chunk_2ac91267,src/priv/supervisor.adoc,606,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Value (`stval`) Register","If `stval` is written with a nonzero value when a misaligned load or store causes an access-fault, page-fault, or hardware-error exception, then `stval` will contain the virtual address of the portion of the access that caused the fault.",CSR_controlled,enum,high,False, +chunk_8cb5831f,src/priv/supervisor.adoc,613,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Value (`stval`) Register","If `stval` is written with a nonzero value when an instruction access-fault, page-fault, or hardware-error exception occurs on a hart with variable-length instructions, then `stval` will contain the virtual address of the portion of the instruction that caused the fault, while `sepc` will point to the beginning of the instruction.",CSR_controlled,enum,high,False, +chunk_4a4f76e5,src/priv/supervisor.adoc,620,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Value (`stval`) Register",The `stval` register can optionally also be used to return the faulting instruction bits on an illegal-instruction exception (`sepc` points to the faulting instruction in memory).,CSR_controlled,enum,high,False, +chunk_30d0f022,src/priv/supervisor.adoc,620,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Value (`stval`) Register","If `stval` is written with a nonzero value when an illegal-instruction exception occurs, then `stval` will contain the shortest of:",CSR_controlled,enum,high,False, +chunk_ae2004f7,src/priv/supervisor.adoc,627,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Value (`stval`) Register",the actual faulting instruction * the first ILEN bits of the faulting instruction * the first SXLEN bits of the faulting instruction,unknown,range,high,False, +chunk_41abd606,src/priv/supervisor.adoc,631,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Value (`stval`) Register",The value loaded into `stval` on an illegal-instruction exception is right-justified and all unused upper bits are cleared to zero.,CSR_controlled,binary,high,False, +chunk_0dd14fa7,src/priv/supervisor.adoc,635,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Value (`stval`) Register","On a trap caused by a software-check exception, the `stval` register holds the cause for the exception.",CSR_controlled,enum,high,False, +chunk_dad0b092,src/priv/supervisor.adoc,639,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Value (`stval`) Register",0 - No information provided. * 2 - Landing Pad Fault.,unknown,unknown,high,False, +chunk_ec7b962f,src/priv/supervisor.adoc,639,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Value (`stval`) Register",Defined by the Zicfilp extension (). * 3 - Shadow Stack Fault.,unknown,unknown,high,False, +chunk_12252fac,src/priv/supervisor.adoc,639,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Value (`stval`) Register",Defined by the Zicfiss extension ().,unknown,unknown,high,False, +chunk_fa28d3bf,src/priv/supervisor.adoc,643,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Value (`stval`) Register","For other traps, `stval` is set to zero, but a future standard may redefine `stval`’s setting for other traps.",CSR_controlled,binary,high,False, +chunk_d991b772,src/priv/supervisor.adoc,647,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Value (`stval`) Register",`stval` is a *WARL* register that must be able to hold all valid virtual addresses and the value 0.,CSR_controlled,enum,very_high,False, +chunk_f3f8b7b1,src/priv/supervisor.adoc,647,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Value (`stval`) Register",It need not be capable of holding all possible invalid addresses.,non_CSR_parameter,enum,high,False, +chunk_46567333,src/priv/supervisor.adoc,647,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Value (`stval`) Register","Prior to writing `stval`, implementations may convert an invalid address into some other invalid address that `stval` is capable of holding.",CSR_controlled,enum,high,False, +chunk_dea5ba2c,src/priv/supervisor.adoc,647,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Value (`stval`) Register","If the feature to return the faulting instruction bits is implemented, `stval` must also be able to hold all values less than 2^N^, where N is the smaller of SXLEN and ILEN.",CSR_controlled,range,very_high,False, +chunk_bd58296d,src/priv/supervisor.adoc,660,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register","The `senvcfg` CSR is an SXLEN-bit read/write register, formatted as shown in , that controls certain characteristics of the U-mode execution environment.",CSR_controlled,range,high,False, +chunk_9c2522d9,src/priv/supervisor.adoc,698,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register","If bit FIOM (Fence of I/O implies Memory) is set to one in `senvcfg`, FENCE instructions executed in U-mode are modified so the requirement to order accesses to device I/O implies also the requirement to order main memory accesses. details the modified interpretation of FENCE instruction bits PI, PO, SI, and SO in U-mode when FIOM=1.",CSR_controlled,binary,high,False, +chunk_ab8b5beb,src/priv/supervisor.adoc,706,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register","Similarly, for U-mode when FIOM=1, if an atomic instruction that accesses a region ordered as device I/O has its aq and/or rl bit set, then that instruction is ordered as though it accesses both device I/O and memory.",unknown,unknown,high,False, +chunk_e19c23fe,src/priv/supervisor.adoc,712,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register","If `satp`.MODE is read-only zero (always Bare), the implementation may make FIOM read-only zero.",CSR_controlled,binary,high,False, +chunk_dca2802a,src/priv/supervisor.adoc,731,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register",The Zicboz extension adds the `CBZE` (Cache Block Zero instruction enable) field to `senvcfg`.,CSR_controlled,enum,high,False, +chunk_beedd315,src/priv/supervisor.adoc,731,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register",The `CBZE` field controls execution of the cache block zero instruction (`CBO.ZERO`) in U-mode.,non_CSR_parameter,enum,high,False, +chunk_de7a421e,src/priv/supervisor.adoc,731,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register","Execution of `CBO.ZERO` in U-mode is enabled only if execution of the instruction is enabled for use in S-mode and `CBZE` is set to 1; otherwise, an illegal-instruction exception is raised.",non_CSR_parameter,binary,high,False, +chunk_1d1e9393,src/priv/supervisor.adoc,731,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register","When the Zicboz extension is not implemented, `CBZE` is read-only zero.",unknown,binary,high,False, +chunk_a72a56ff,src/priv/supervisor.adoc,739,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register",The Zicbom extension adds the `CBCFE` (Cache Block Clean and Flush instruction Enable) field to `senvcfg` to control execution of the `CBO.CLEAN` and `CBO.FLUSH` instructions in U-mode.,CSR_controlled,enum,high,False, +chunk_703720bd,src/priv/supervisor.adoc,739,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register","Execution of these instructions in U-mode is enabled only if execution of these instructions is enabled for use in S-mode and `CBCFE` is set to 1; otherwise, an illegal-instruction exception is raised.",non_CSR_parameter,binary,high,False, +chunk_19023b2e,src/priv/supervisor.adoc,739,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register","When the Zicbom extension is not implemented, `CBCFE` is read-only zero.",unknown,binary,high,False, +chunk_b3c6c806,src/priv/supervisor.adoc,747,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register",The Zicbom extension adds the `CBIE` (Cache Block Invalidate instruction Enable) WARL field to `senvcfg` to control execution of the `CBO.INVAL` instruction in U-mode.,CSR_controlled,enum,very_high,False, +chunk_00cd15bd,src/priv/supervisor.adoc,747,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register",The encoding `10b` is reserved.,unknown,enum,high,False, +chunk_51f2b558,src/priv/supervisor.adoc,747,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register","When the Zicbom extension is not implemented, `CBIE` is read-only zero.",unknown,binary,high,False, +chunk_e53554b1,src/priv/supervisor.adoc,747,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register","Execution of `CBO.INVAL` in U-mode is enabled only if execution of the instruction is enabled for use in S-mode and `CBIE` is set to `01b` or `11b`; otherwise, an illegal-instruction exception is raised.",non_CSR_parameter,binary,high,False, +chunk_04d9d67a,src/priv/supervisor.adoc,756,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register","If `CBO.INVAL` is enabled in S-mode to perform a flush operation, then when the instruction is enabled in U-mode it performs a flush operation, even if `CBIE` is set to `11b`.",unknown,binary,high,False, +chunk_1913d647,src/priv/supervisor.adoc,756,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register","Otherwise, the instruction behaves as follows, depending on the `CBIE` encoding:",unknown,enum,high,False, +chunk_8bff7acb,src/priv/supervisor.adoc,761,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register",`01b` -- The instruction is executed and performs a flush operation. * `11b` -- The instruction is executed and performs an invalidate operation.,unknown,unknown,high,False, +chunk_a9027501,src/priv/supervisor.adoc,764,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register","If Ssnpm is not implemented, `PMM` is read-only zero.",unknown,binary,high,False, +chunk_169d0fd6,src/priv/supervisor.adoc,764,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register",The `PMM` field is read-only zero for RV32.,CSR_controlled,binary,high,False, +chunk_e41df48b,src/priv/supervisor.adoc,783,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register",The Zicfilp extension adds the `LPE` field in `senvcfg`.,CSR_controlled,enum,high,False, +chunk_d65e9566,src/priv/supervisor.adoc,783,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register","When the `LPE` field is set to 1, the Zicfilp extension is enabled in VU/U-mode.",unknown,binary,high,False, +chunk_06052883,src/priv/supervisor.adoc,783,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register","When the `LPE` field is 0, the Zicfilp extension is not enabled in VU/U-mode and the following rules apply to VU/U-mode:",unknown,binary,high,False, +chunk_3dad2541,src/priv/supervisor.adoc,789,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register",The hart does not update the `ELP` state; it remains as `NOLPEXPECTED`. * The `LPAD` instruction operates as a no-op.,unknown,unknown,high,False, +chunk_b19c7752,src/priv/supervisor.adoc,792,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register",The Zicfiss extension adds the `SSE` field in `senvcfg`.,CSR_controlled,enum,high,False, +chunk_a4c98d55,src/priv/supervisor.adoc,792,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register","When the `SSE` field is set to 1, the Zicfiss extension is activated in VU/U-mode.",unknown,binary,high,False, +chunk_a219612a,src/priv/supervisor.adoc,792,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register","When the `SSE` field is 0, the Zicfiss extension remains inactive in VU/U-mode, and the following rules apply:",unknown,enum,high,False, +chunk_073a1e59,src/priv/supervisor.adoc,798,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register",32-bit Zicfiss instructions will revert to their behavior as defined by Zimop. * 16-bit Zicfiss instructions will revert to their behavior as defined by Zcmop. *,non_CSR_parameter,range,high,False, +chunk_031481d9,src/priv/supervisor.adoc,798,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register","When `menvcfg.SSE` is one, `SSAMOSWAP.W/D` raises an illegal-instruction exception in U-mode and a virtual-instruction exception in VU-mode.",CSR_controlled,enum,high,False, +chunk_b11dd896,src/priv/supervisor.adoc,806,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Address Translation and Protection (`satp`) Register","The `satp` CSR is an SXLEN-bit read/write register, formatted as shown in for SXLEN=32 and for SXLEN=64, which controls supervisor-mode address translation and protection.",CSR_controlled,range,high,False, +chunk_a9be8fa8,src/priv/supervisor.adoc,806,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Address Translation and Protection (`satp`) Register",Further details on the access to this register are described in .,unknown,unknown,high,False, +chunk_6545c7e7,src/priv/supervisor.adoc,826,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Address Translation and Protection (`satp`) Register",shows the encodings of the MODE field when SXLEN=32 and SXLEN=64.,unknown,enum,high,False, +chunk_f77f341e,src/priv/supervisor.adoc,826,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Address Translation and Protection (`satp`) Register","When MODE=Bare, supervisor virtual addresses are equal to supervisor physical addresses, and there is no additional memory protection beyond the physical memory protection scheme described in .",unknown,range,high,False, +chunk_a56a26cb,src/priv/supervisor.adoc,826,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Address Translation and Protection (`satp`) Register","To select MODE=Bare, software must write zero to the remaining fields of `satp` (bits 30–0 when SXLEN=32, or bits 59–0 when SXLEN=64).",CSR_controlled,enum,very_high,False, +chunk_ef6056e2,src/priv/supervisor.adoc,826,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Address Translation and Protection (`satp`) Register",Attempting to select MODE=Bare with a nonzero pattern in the remaining fields has an UNSPECIFIED effect on the value that the remaining fields assume and an UNSPECIFIED effect on address translation and protection behavior.,non_CSR_parameter,enum,high,False, +chunk_f30ec461,src/priv/supervisor.adoc,838,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Address Translation and Protection (`satp`) Register","When SXLEN=32, the `satp` encodings corresponding to MODE=Bare and ASID[8:7]=3 are designated for custom use, whereas the encodings corresponding to MODE=Bare and ASID[8:7]!=3 are reserved for future standard use.",CSR_controlled,enum,high,False, +chunk_36cf0e92,src/priv/supervisor.adoc,838,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Address Translation and Protection (`satp`) Register","When SXLEN=64, all `satp` encodings corresponding to MODE=Bare are reserved for future standard use.",CSR_controlled,enum,high,False, +chunk_f8790670,src/priv/supervisor.adoc,844,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Address Translation and Protection (`satp`) Register","If an implementation supports the Svbare extension, then the `satp` register's MODE field must be capable of holding the value Bare.",CSR_controlled,enum,very_high,False, +chunk_1e0064c9,src/priv/supervisor.adoc,848,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Address Translation and Protection (`satp`) Register","When SXLEN=32, the only other valid setting for MODE is Sv32, a paged virtual-memory scheme described in .",unknown,unknown,high,False, +chunk_df06bbd5,src/priv/supervisor.adoc,852,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Address Translation and Protection (`satp`) Register","When SXLEN=64, three paged virtual-memory schemes are defined: Sv39, Sv48, and Sv57, described in , , and , respectively.",unknown,unknown,high,False, +chunk_02733136,src/priv/supervisor.adoc,852,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Address Translation and Protection (`satp`) Register","One additional scheme, Sv64, will be defined in a later version of this specification.",unknown,unknown,high,False, +chunk_4e95ee24,src/priv/supervisor.adoc,852,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Address Translation and Protection (`satp`) Register",The remaining MODE settings are reserved for future use and may define different interpretations of the other fields in `satp`.,CSR_controlled,enum,high,False, +chunk_1c14813c,src/priv/supervisor.adoc,860,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Address Translation and Protection (`satp`) Register","Implementations are not required to support all MODE settings, and if `satp` is written with an unsupported MODE, the entire write has no effect; no fields in `satp` are modified.",CSR_controlled,enum,high,False, +chunk_312e1f10,src/priv/supervisor.adoc,865,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Address Translation and Protection (`satp`) Register",The number of ASID bits is UNSPECIFIED and may be zero.,non_CSR_parameter,enum,high,False, +chunk_1b836177,src/priv/supervisor.adoc,865,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Address Translation and Protection (`satp`) Register","The number of implemented ASID bits, termed ASIDLEN, may be determined by writing one to every bit position in the ASID field, then reading back the value in `satp` to see which bit positions in the ASID field hold a one.",CSR_controlled,enum,high,False, +chunk_3281511b,src/priv/supervisor.adoc,865,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Address Translation and Protection (`satp`) Register","The maximal value of ASIDLEN, termed ASIDMAX, is 9 for Sv32 or 16 for Sv39, Sv48, and Sv57.",unknown,enum,high,False, +chunk_7bf25866,src/priv/supervisor.adoc,917,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Address Translation and Protection (`satp`) Register",The `satp` CSR is considered active when the effective privilege mode is S-mode or U-mode.,CSR_controlled,enum,high,False, +chunk_537571f9,src/priv/supervisor.adoc,917,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Address Translation and Protection (`satp`) Register",Executions of the address-translation algorithm may only begin using a given value of `satp` when `satp` is active.,CSR_controlled,enum,high,False, +chunk_468078d5,src/priv/supervisor.adoc,935,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Timer (`stimecmp`) Register",The `stimecmp` CSR is a 64-bit register and has 64-bit precision on all RV32 and RV64 systems.,CSR_controlled,range,high,False, +chunk_b32f1bad,src/priv/supervisor.adoc,935,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Timer (`stimecmp`) Register","In RV32 only, accesses to the `stimecmp` CSR access the low 32 bits, while accesses to the `stimecmph` CSR access the high 32 bits of `stimecmp`.",CSR_controlled,range,high,False, +chunk_a38dc791,src/priv/supervisor.adoc,940,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Timer (`stimecmp`) Register","A supervisor timer interrupt becomes pending, as reflected in the STIP bit in the `mip` and `sip` registers whenever `time` contains a value greater than or equal to `stimecmp`, treating the values as unsigned integers.",CSR_controlled,range,high,False, +chunk_539c94fa,src/priv/supervisor.adoc,940,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Timer (`stimecmp`) Register","If the result of this comparison changes, it is guaranteed to be reflected in STIP eventually, but not necessarily immediately.",unknown,unknown,high,False, +chunk_b341b1f2,src/priv/supervisor.adoc,940,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Timer (`stimecmp`) Register",The interrupt will be taken based on the standard interrupt enable and delegation rules.,unknown,unknown,high,False, +chunk_17a0f8d9,src/priv/supervisor.adoc,977,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction",The behavior of SFENCE.VMA depends on rs1 and rs2 as follows:,SW_rule,unknown,medium,False, +chunk_496e38fa,src/priv/supervisor.adoc,985,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction","If rs1=`x0` and rs2=`x0`, the fence orders all reads and writes made to any level of the page tables, for all address spaces.",SW_rule,unknown,high,False, +chunk_6b47438c,src/priv/supervisor.adoc,990,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction","If rs1=`x0` and rs2{ne}``x0``, the fence orders all reads and writes made to any level of the page tables, but only for the address space identified by integer register rs2.",SW_rule,unknown,high,False, +chunk_36d5504d,src/priv/supervisor.adoc,998,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction","If rs1{ne}``x0`` and rs2=`x0`, the fence orders only reads and writes made to leaf page table entries corresponding to the virtual address in rs1, for all address spaces.",SW_rule,unknown,high,False, +chunk_acb66772,src/priv/supervisor.adoc,1005,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction","If rs1{ne}``x0`` and rs2{ne}``x0``, the fence orders only reads and writes made to leaf page table entries corresponding to the virtual address in rs1, for the address space identified by integer register rs2.",SW_rule,unknown,high,False, +chunk_1f453b67,src/priv/supervisor.adoc,1014,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction","If the value held in rs1 is not a valid virtual address, then the SFENCE.VMA instruction has no effect.",SW_rule,unknown,high,False, +chunk_6426d50a,src/priv/supervisor.adoc,1014,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction",No exception is raised in this case.,non_CSR_parameter,unknown,high,False, +chunk_60a848de,src/priv/supervisor.adoc,1019,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction","When rs2{ne}``x0``, bits SXLEN-1:ASIDMAX of the value held in rs2 are reserved for future standard use.",unknown,unknown,high,False, +chunk_2f2c6058,src/priv/supervisor.adoc,1019,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction","Until their use is defined by a standard extension, they should be zeroed by software and ignored by current implementations.",SW_rule,enum,medium,False, +chunk_d67df9cc,src/priv/supervisor.adoc,1019,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction","Furthermore, if ASIDLEN Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction",An implicit read of the memory-management data structures may return any translation for an address that was valid at any time since the most recent SFENCE.VMA that subsumes that address.,SW_rule,enum,medium,False, +chunk_c7f606c6,src/priv/supervisor.adoc,1027,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction",These implicit loads also need not otherwise obey normal program order semantics with respect to prior loads or stores to the same address.,non_CSR_parameter,enum,medium,False, +chunk_0089507b,src/priv/supervisor.adoc,1042,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction","Implementations must only perform implicit reads of the translation data structures pointed to by the current contents of the `satp` register or a subsequent valid (V=1) translation data structure entry, and must only raise exceptions for implicit accesses that are generated as a result of instruction execution, not those that are performed speculatively.",CSR_controlled,enum,very_high,False, +chunk_32db1b59,src/priv/supervisor.adoc,1049,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction","Changes to the `sstatus` fields SUM and MXR take effect immediately, without the need to execute an SFENCE.VMA instruction.",CSR_controlled,enum,high,False, +chunk_9d004688,src/priv/supervisor.adoc,1049,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction","Changing `satp`.MODE from Bare to other modes and vice versa also takes effect immediately, without the need to execute an SFENCE.VMA instruction.",CSR_controlled,enum,high,False, +chunk_42ef9f79,src/priv/supervisor.adoc,1049,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction","Likewise, changes to `satp`.ASID take effect immediately.",CSR_controlled,enum,high,False, +chunk_c6432aaf,src/priv/supervisor.adoc,1056,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction","If a hart employs an address-translation cache, that cache must appear to be private to that hart.",non_CSR_parameter,binary,very_high,False, +chunk_fbd42ad4,src/priv/supervisor.adoc,1056,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction","In particular, the meaning of an ASID is local to a hart; software may choose to use the same ASID to refer to different address spaces on different harts.",SW_rule,enum,medium,False, +chunk_29b5dd44,src/priv/supervisor.adoc,1062,"Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction","For implementations that make `satp`.MODE read-only zero (always Bare), attempts to execute an SFENCE.VMA instruction might raise an illegal-instruction exception.",CSR_controlled,binary,high,False, +chunk_17b51e81,src/priv/supervisor.adoc,1086,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection","Sv32 implementations support a 32-bit virtual address space, divided into 4 KiB pages.",non_CSR_parameter,range,medium,False, +chunk_6e96c167,src/priv/supervisor.adoc,1086,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection","When Sv32 virtual memory mode is selected in the MODE field of the `satp` register, supervisor virtual addresses are translated into supervisor physical addresses via a two-level page table.",CSR_controlled,enum,high,False, +chunk_faf01682,src/priv/supervisor.adoc,1086,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection","The 20-bit VPN is translated into a 22-bit physical page number (PPN), while the 12-bit page offset is untranslated.",non_CSR_parameter,range,medium,False, +chunk_de2359ad,src/priv/supervisor.adoc,1086,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection","If necessary, supervisor-level physical addresses are zero-extended to the number of physical address bits found in the implementation.",unknown,enum,high,False, +chunk_3c81eded,src/priv/supervisor.adoc,1104,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection","Sv32 page tables consist of 2^10^ page-table entries (PTEs), each of four bytes. A page table is exactly the size of a page and must always be aligned to a page boundary.",non_CSR_parameter,enum,very_high,False, +chunk_9c96dfbe,src/priv/supervisor.adoc,1104,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection",The physical page number of the root page table is stored in the `satp` register.,CSR_controlled,enum,high,False, +chunk_15744a89,src/priv/supervisor.adoc,1117,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection","The V bit indicates whether the PTE is valid; if it is 0, all other bits in the PTE are don’t-cares and may be used freely by software.",SW_rule,enum,high,False, +chunk_325f20bf,src/priv/supervisor.adoc,1117,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection","The permission bits, R, W, and X, indicate whether the page is readable, writable, and executable, respectively.",CSR_controlled,unknown,high,False, +chunk_813c23c8,src/priv/supervisor.adoc,1117,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection","When all three are zero, the PTE is a pointer to the next level of the page table; otherwise, it is a leaf PTE.",unknown,unknown,high,False, +chunk_28fda033,src/priv/supervisor.adoc,1117,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection",Writable pages must also be marked readable; the contrary combinations are reserved for future use. summarizes the encoding of the permission bits.,CSR_controlled,enum,very_high,False, +chunk_37f24126,src/priv/supervisor.adoc,1166,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection",Attempting to fetch an instruction from a page that does not have execute permissions raises a fetch page-fault exception.,non_CSR_parameter,unknown,high,False, +chunk_41900185,src/priv/supervisor.adoc,1166,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection","Attempting to execute a load, load-reserved, or cache-block management instruction whose effective address lies within a page without read permissions raises a load page-fault exception.",non_CSR_parameter,unknown,high,False, +chunk_e99af61b,src/priv/supervisor.adoc,1166,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection","Attempting to execute a store, store-conditional, AMO, or cache-block zero instruction instruction whose effective address lies within a page without write permissions raises a store page-fault exception.",non_CSR_parameter,unknown,high,False, +chunk_0a493f27,src/priv/supervisor.adoc,1175,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection",The U bit indicates whether the page is accessible to user mode. U-mode software may only access the page when U=1.,SW_rule,enum,high,False, +chunk_5aad4584,src/priv/supervisor.adoc,1175,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection","If the SUM bit in the `sstatus` register is set, supervisor mode software may also access pages with U=1.",CSR_controlled,enum,high,False, +chunk_2a845d8f,src/priv/supervisor.adoc,1175,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection","However, supervisor code normally operates with the SUM bit clear, in which case, supervisor code will fault on accesses to user-mode pages.",unknown,unknown,high,False, +chunk_f6cc4408,src/priv/supervisor.adoc,1175,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection","Irrespective of SUM, the supervisor may not execute code on pages with U=1.",non_CSR_parameter,enum,medium,False, +chunk_14b76ccd,src/priv/supervisor.adoc,1183,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection",The G bit designates a global mapping.,unknown,unknown,high,False, +chunk_17540267,src/priv/supervisor.adoc,1192,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection",The RSW field is reserved for use by supervisor software; the implementation shall ignore this field.,SW_rule,enum,very_high,False, +chunk_a413a6fd,src/priv/supervisor.adoc,1207,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection","When the Svade extension is not implemented, the following scheme applies. + +",unknown,unknown,high,False, +chunk_8951da72,src/priv/supervisor.adoc,1207,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection","When a virtual page is accessed and the A bit is clear, the PTE is updated to set the A bit.",unknown,unknown,high,False, +chunk_3e560fe5,src/priv/supervisor.adoc,1207,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection","When the virtual page is written and the D bit is clear, the PTE is updated to set the D bit.",unknown,unknown,high,False, +chunk_498a5dff,src/priv/supervisor.adoc,1207,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection","When G-stage address translation is in use and is not Bare, the G-stage virtual pages may be accessed or written by implicit accesses to VS-level memory management data structures, such as page tables. + +",non_CSR_parameter,enum,high,False, +chunk_754c2dd8,src/priv/supervisor.adoc,1207,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection","When two-stage address translation is in use, an explicit access may cause both VS-stage and G-stage PTEs to be updated.",non_CSR_parameter,enum,high,False, +chunk_d22df458,src/priv/supervisor.adoc,1207,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection","The following rules apply to all PTE updates caused by an explicit or an implicit memory accesses. + + The PTE update must be atomic with respect to other accesses to the PTE, and must atomically perform all page-table walk checks for that leaf PTE as part of, and before, conditionally updating the PTE value.",non_CSR_parameter,enum,very_high,False, +chunk_32ffc581,src/priv/supervisor.adoc,1207,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection","Updates of the A bit may be performed as a result of speculation, even if the associated memory access ultimately is not performed architecturally.",non_CSR_parameter,enum,high,False, +chunk_af6c9656,src/priv/supervisor.adoc,1207,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection","However, updates to the D bit, resulting from an explicit store, must be exact (i.e., non-speculative), and observed in program order by the local hart.",non_CSR_parameter,enum,very_high,False, +chunk_f91d2b79,src/priv/supervisor.adoc,1207,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection","When two-stage address translation is active, updates to the D bit in G-stage PTEs may be performed by an implicit access to a VS-stage PTE, if the G-stage PTE provides write permission, before any speculative access to the VS-stage PTE. + + The PTE update must appear in the global memory order before the memory access that caused the PTE update and before any subsequent explicit memory access to that virtual page by the local hart.",non_CSR_parameter,binary,very_high,False, +chunk_80f11ed7,src/priv/supervisor.adoc,1207,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection",The ordering on loads and stores provided by FENCE instructions and the acquire/release bits on atomic instructions also orders the PTE updates associated with those loads and stores as observed by remote harts. + + The PTE update is not required to be atomic with respect to the memory access that caused the update and a trap may occur between the PTE update and the memory access that caused the PTE update.,SW_rule,enum,high,False, +chunk_3434b777,src/priv/supervisor.adoc,1207,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection",If a trap occurs then the A and/or D bit may be updated but the memory access that caused the PTE update might not occur.,non_CSR_parameter,enum,high,False, +chunk_a7bf66ff,src/priv/supervisor.adoc,1207,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection",The hart must not perform the memory access that caused the PTE update before the PTE update is globally visible. + + The page tables must be located in memory with hardware page-table write access and RsrvEventual PMA.,non_CSR_parameter,enum,very_high,False, +chunk_f31be6ec,src/priv/supervisor.adoc,1251,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection",All harts in a system must employ the same PTE-update scheme as each other.,non_CSR_parameter,enum,very_high,False, +chunk_744f9187,src/priv/supervisor.adoc,1254,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection","Any level of PTE may be a leaf PTE, so in addition to 4 KiB pages, Sv32 supports 4 MiB megapages. A megapage must be virtually and physically aligned to a 4 MiB boundary; a page-fault exception is raised if the physical address is insufficiently aligned.",non_CSR_parameter,binary,very_high,False, +chunk_aab201fe,src/priv/supervisor.adoc,1259,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection","Until their use is defined by a standard extension, they must be cleared by software for forward compatibility.",SW_rule,enum,very_high,False, +chunk_ae9dae05,src/priv/supervisor.adoc,1263,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection","For implementations with both page-based virtual memory and the ""A"" standard extension, the LR/SC reservation set must lie completely within a single base physical page (i.e., a naturally aligned 4 KiB physical-memory region).",non_CSR_parameter,enum,very_high,False, +chunk_8b568299,src/priv/supervisor.adoc,1268,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection","On some implementations, misaligned loads, stores, and instruction fetches may also be decomposed into multiple accesses, some of which may succeed before a page-fault exception occurs.",non_CSR_parameter,enum,high,False, +chunk_c899916f,src/priv/supervisor.adoc,1268,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection","In particular, a portion of a misaligned store that passes the exception check may become visible, even if another portion fails the exception check.",non_CSR_parameter,enum,high,False, +chunk_6c464627,src/priv/supervisor.adoc,1283,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process","Let a be ``satp``.ppn×PAGESIZE, and let i=LEVELS-1. (For Sv32, PAGESIZE=2^12^ and LEVELS=2.) The `satp` register must be active, i.e., the effective privilege mode must be S-mode or U-mode.",CSR_controlled,enum,very_high,False, +chunk_24313df8,src/priv/supervisor.adoc,1286,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process","Let pte be the value of the PTE at address a+va.vpn[i]×PTESIZE. (For Sv32, PTESIZE=4.)",unknown,enum,high,False, +chunk_523bf330,src/priv/supervisor.adoc,1286,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process","If accessing pte violates a PMA or PMP check, raise an access-fault exception corresponding to the original access type.",non_CSR_parameter,unknown,high,False, +chunk_e09616d4,src/priv/supervisor.adoc,1288,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process","If pte.v=0, or if pte.r=0 and pte.w=1, or if any bits or encodings that are reserved for future standard use are set within pte, stop and raise a page-fault exception corresponding to the original access type.",non_CSR_parameter,enum,high,False, +chunk_cac71583,src/priv/supervisor.adoc,1290,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process","If pte.r=1 or pte.x=1, go to step 5.",unknown,unknown,high,False, +chunk_8d4ce2ab,src/priv/supervisor.adoc,1290,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process","If i<0, stop and raise a page-fault exception corresponding to the original access type.",non_CSR_parameter,unknown,high,False, +chunk_69644df2,src/priv/supervisor.adoc,1293,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process","If i>0 and pte.ppn[i-1:0] != 0, this is a misaligned superpage; stop and raise a page-fault exception corresponding to the original access type.",non_CSR_parameter,unknown,high,False, +chunk_5abde674,src/priv/supervisor.adoc,1295,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process","Determine if the requested memory access is allowed by the pte.u bit, given the current privilege mode and the value of the SUM and MXR fields of the *mstatus* register.",CSR_controlled,enum,high,False, +chunk_4727038e,src/priv/supervisor.adoc,1295,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process","If not, stop and raise a page-fault exception corresponding to the original access type.",non_CSR_parameter,unknown,high,False, +chunk_e945aaea,src/priv/supervisor.adoc,1297,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process","Determine if the requested memory access is allowed by the pte.r, pte.w, and pte.x bits, given the Shadow Stack Memory Protection rules.",unknown,unknown,high,False, +chunk_fe1d67e1,src/priv/supervisor.adoc,1297,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process","If not, stop and raise an access-fault exception.",non_CSR_parameter,unknown,high,False, +chunk_7b5c5734,src/priv/supervisor.adoc,1299,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process","Determine if the requested memory access is allowed by the pte.r, pte.w, and pte.x bits.",unknown,unknown,high,False, +chunk_86bd38e9,src/priv/supervisor.adoc,1299,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process","If not, stop and raise a page-fault exception corresponding to the original access type.",non_CSR_parameter,unknown,high,False, +chunk_69483509,src/priv/supervisor.adoc,1301,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process","If pte.a=0, or if the original memory access is a store and pte.d=0:",unknown,unknown,high,False, +chunk_9fd8d38f,src/priv/supervisor.adoc,1303,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process","If the Svade extension is implemented, stop and raise a page-fault exception corresponding to the original access type. *",non_CSR_parameter,unknown,high,False, +chunk_264d174f,src/priv/supervisor.adoc,1303,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process","If a store to the PTE at address a+va.vpn[i]×PTESIZE would violate a PMA or PMP check, raise an access-fault exception corresponding to the original access type. * Perform the following steps atomically: ** Compare pte to the value of the PTE at address a+va.vpn[i]×PTESIZE. **",non_CSR_parameter,enum,high,False, +chunk_afa22934,src/priv/supervisor.adoc,1303,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process","If the values match, set pte.a to 1 and, if the original memory access is a store, also set pte.d to 1.",unknown,unknown,high,False, +chunk_69d3817c,src/priv/supervisor.adoc,1303,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process","If the comparison fails, return to step 2.",unknown,unknown,high,False, +chunk_c2ff426c,src/priv/supervisor.adoc,1313,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process","If i>0, then this is a superpage translation and pa.ppn[i-1:0] = va.vpn[i-1:0]. * pa.ppn[LEVELS-1:i] = pte.ppn[LEVELS-1:i].",unknown,unknown,high,False, +chunk_9e32d6f3,src/priv/supervisor.adoc,1322,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process","The results of implicit address-translation reads in step 2 may be held in a read-only, incoherent address-translation cache but not shared with other harts.",non_CSR_parameter,enum,high,False, +chunk_6f492440,src/priv/supervisor.adoc,1322,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process","The address-translation cache may hold an arbitrary number of entries, including an arbitrary number of entries for the same address and ASID.",non_CSR_parameter,enum,high,False, +chunk_72605428,src/priv/supervisor.adoc,1322,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process",Entries in the address-translation cache may then satisfy subsequent step 2 reads if the ASID associated with the entry matches the ASID loaded in step 0 or if the entry is associated with a global mapping.,non_CSR_parameter,enum,high,False, +chunk_505d8512,src/priv/supervisor.adoc,1322,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process","To ensure that implicit reads observe writes to the same memory locations, an SFENCE.VMA instruction must be executed after the writes to flush the relevant cached translations.",SW_rule,enum,very_high,False, +chunk_d28700cd,src/priv/supervisor.adoc,1333,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process",The address-translation cache cannot be used in step 9; accessed and dirty bits may only be updated in memory directly.,non_CSR_parameter,enum,high,False, +chunk_0946d34b,src/priv/supervisor.adoc,1333,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process","Implementations may also execute the address-translation algorithm speculatively at any time, for any virtual address, as long as `satp` is active (as defined in ).",CSR_controlled,enum,high,False, +chunk_ca42fdc2,src/priv/supervisor.adoc,1341,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process","Speculative executions of the address-translation algorithm behave as non-speculative executions of the algorithm do, except that they must not set the dirty bit for a PTE, they must not trigger an exception, and they must not create address-translation cache entries if those entries would have been invalidated by any SFENCE.VMA instruction executed by the hart since the speculative execution of the algorithm began.",SW_rule,binary,very_high,False, +chunk_05a94186,src/priv/supervisor.adoc,1351,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv39: Page-Based 39-bit Virtual-Memory System","This section describes a simple paged virtual-memory system for SXLEN=64, which supports 39-bit virtual address spaces.",non_CSR_parameter,range,medium,False, +chunk_296d31c8,src/priv/supervisor.adoc,1359,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv39: Page-Based 39-bit Virtual-Memory System > Addressing and Memory Protection","Sv39 implementations support a 39-bit virtual address space, divided into 4 KiB pages.",non_CSR_parameter,range,medium,False, +chunk_fe810c78,src/priv/supervisor.adoc,1359,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv39: Page-Based 39-bit Virtual-Memory System > Addressing and Memory Protection","Instruction fetch addresses and load and store effective addresses, which are 64 bits, must have bits 63–39 all equal to bit 38, or else a page-fault exception will occur.",non_CSR_parameter,range,very_high,False, +chunk_df00bbad,src/priv/supervisor.adoc,1359,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv39: Page-Based 39-bit Virtual-Memory System > Addressing and Memory Protection","The 27-bit VPN is translated into a 44-bit PPN via a three-level page table, while the 12-bit page offset is untranslated.",non_CSR_parameter,range,medium,False, +chunk_63f824d2,src/priv/supervisor.adoc,1382,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv39: Page-Based 39-bit Virtual-Memory System > Addressing and Memory Protection","Sv39 page tables contain 2^9^ page table entries (PTEs), eight bytes each. A page table is exactly the size of a page and must always be aligned to a page boundary.",non_CSR_parameter,enum,very_high,False, +chunk_b151e915,src/priv/supervisor.adoc,1382,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv39: Page-Based 39-bit Virtual-Memory System > Addressing and Memory Protection",The physical page number of the root page table is stored in the `satp` register's PPN field.,CSR_controlled,enum,high,False, +chunk_28164943,src/priv/supervisor.adoc,1389,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv39: Page-Based 39-bit Virtual-Memory System > Addressing and Memory Protection","If Svnapot is not implemented, bit 63 remains reserved and must be zeroed by software for forward compatibility, or else a page-fault exception is raised.",SW_rule,binary,very_high,False, +chunk_d2dbfb9b,src/priv/supervisor.adoc,1389,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv39: Page-Based 39-bit Virtual-Memory System > Addressing and Memory Protection","If Svpbmt is not implemented, bits 62-61 remain reserved and must be zeroed by software for forward compatibility, or else a page-fault exception is raised.",SW_rule,binary,very_high,False, +chunk_54bb3c07,src/priv/supervisor.adoc,1389,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv39: Page-Based 39-bit Virtual-Memory System > Addressing and Memory Protection","Bits 60-54 are reserved for future standard use and, until their use is defined by some standard extension, must be zeroed by software for forward compatibility.",SW_rule,enum,very_high,False, +chunk_869b42cc,src/priv/supervisor.adoc,1389,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv39: Page-Based 39-bit Virtual-Memory System > Addressing and Memory Protection","If any of these bits are set, a page-fault exception is raised.",non_CSR_parameter,unknown,high,False, +chunk_a6efeb0a,src/priv/supervisor.adoc,1405,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv39: Page-Based 39-bit Virtual-Memory System > Addressing and Memory Protection","Any level of PTE may be a leaf PTE, so in addition to 4 KiB pages, Sv39 supports 2 MiB megapages and 1 GiB gigapages, each of which must be virtually and physically aligned to a boundary equal to its size. A page-fault exception is raised if the physical address is insufficiently aligned.",non_CSR_parameter,range,very_high,False, +chunk_f88ecfd1,src/priv/supervisor.adoc,1421,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv48: Page-Based 48-bit Virtual-Memory System","This section describes a simple paged virtual-memory system for SXLEN=64, which supports 48-bit virtual address spaces.",non_CSR_parameter,range,medium,False, +chunk_966da16d,src/priv/supervisor.adoc,1429,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv48: Page-Based 48-bit Virtual-Memory System",Implementations that support Sv48 must also support Sv39.,non_CSR_parameter,enum,very_high,False, +chunk_c5a71c5e,src/priv/supervisor.adoc,1435,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv48: Page-Based 48-bit Virtual-Memory System > Addressing and Memory Protection","Sv48 implementations support a 48-bit virtual address space, divided into 4 KiB pages.",non_CSR_parameter,range,medium,False, +chunk_7a3726f1,src/priv/supervisor.adoc,1435,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv48: Page-Based 48-bit Virtual-Memory System > Addressing and Memory Protection","Instruction fetch addresses and load and store effective addresses, which are 64 bits, must have bits 63–48 all equal to bit 47, or else a page-fault exception will occur.",non_CSR_parameter,range,very_high,False, +chunk_9d79fc84,src/priv/supervisor.adoc,1435,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv48: Page-Based 48-bit Virtual-Memory System > Addressing and Memory Protection","The 36-bit VPN is translated into a 44-bit PPN via a four-level page table, while the 12-bit page offset is untranslated.",non_CSR_parameter,range,medium,False, +chunk_3a54f8db,src/priv/supervisor.adoc,1458,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv48: Page-Based 48-bit Virtual-Memory System > Addressing and Memory Protection","Any level of PTE may be a leaf PTE, so in addition to 4 KiB pages, Sv48 supports 2 MiB megapages, 1 GiB gigapages, and 512 GiB terapages, each of which must be virtually and physically aligned to a boundary equal to its size. A page-fault exception is raised if the physical address is insufficiently aligned.",non_CSR_parameter,range,very_high,False, +chunk_7a44760f,src/priv/supervisor.adoc,1478,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv57: Page-Based 57-bit Virtual-Memory System","This section describes a simple paged virtual-memory system designed for RV64 systems, which supports 57-bit virtual address spaces.",non_CSR_parameter,range,high,False, +chunk_daf051ba,src/priv/supervisor.adoc,1486,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv57: Page-Based 57-bit Virtual-Memory System",Implementations that support Sv57 must also support Sv48.,non_CSR_parameter,enum,very_high,False, +chunk_14820799,src/priv/supervisor.adoc,1492,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv57: Page-Based 57-bit Virtual-Memory System > Addressing and Memory Protection","Sv57 implementations support a 57-bit virtual address space, divided into 4 KiB pages.",non_CSR_parameter,range,medium,False, +chunk_9abb44f7,src/priv/supervisor.adoc,1492,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv57: Page-Based 57-bit Virtual-Memory System > Addressing and Memory Protection","Instruction fetch addresses and load and store effective addresses, which are 64 bits, must have bits 63–57 all equal to bit 56, or else a page-fault exception will occur.",non_CSR_parameter,range,very_high,False, +chunk_e787bf9b,src/priv/supervisor.adoc,1492,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv57: Page-Based 57-bit Virtual-Memory System > Addressing and Memory Protection","The 45-bit VPN is translated into a 44-bit PPN via a five-level page table, while the 12-bit page offset is untranslated.",non_CSR_parameter,range,medium,False, +chunk_d81cf6eb,src/priv/supervisor.adoc,1515,"Preamble > Supervisor-Level ISA, Version 1.13 > Sv57: Page-Based 57-bit Virtual-Memory System > Addressing and Memory Protection","Any level of PTE may be a leaf PTE, so in addition to 4 KiB pages, Sv57 supports 2 MiB megapages, 1 GiB gigapages, 512 GiB terapages, and 256 TiB petapages, each of which must be virtually and physically aligned to a boundary equal to its size. A page-fault exception is raised if the physical address is insufficiently aligned.",non_CSR_parameter,range,very_high,False, +chunk_8d249b33,src/priv/svadu.adoc,3,"Preamble > ""Svadu"" Extension for Hardware Updating of A/D Bits, Version 1.0",The Svadu extension adds support and CSR controls for hardware updating of PTE A/D bits.,CSR_controlled,enum,high,False, +chunk_39cd4c4f,src/priv/svadu.adoc,5,"Preamble > ""Svadu"" Extension for Hardware Updating of A/D Bits, Version 1.0","If the Svadu extension is implemented, the `menvcfg`.ADUE field is writable.",CSR_controlled,enum,high,False, +chunk_e8a5d8bc,src/priv/svadu.adoc,5,"Preamble > ""Svadu"" Extension for Hardware Updating of A/D Bits, Version 1.0","If the hypervisor extension is additionally implemented, the `henvcfg`.ADUE field is also writable.",CSR_controlled,enum,high,False, +chunk_201b3816,src/priv/svadu.adoc,5,"Preamble > ""Svadu"" Extension for Hardware Updating of A/D Bits, Version 1.0",See and for the definitions of those fields.,unknown,enum,high,False, +chunk_733de6c7,src/priv/svadu.adoc,10,"Preamble > ""Svadu"" Extension for Hardware Updating of A/D Bits, Version 1.0","When hardware updating of A/D bits is disabled, the Svade extension, which mandates exceptions when A/D bits need be set, instead takes effect.",unknown,binary,high,False, +chunk_92ddd2e2,src/priv/svinval.adoc,29,"Preamble > ""Svinval"" Extension for Fine-Grained Address-Translation Cache Invalidation, Version 1.0","When executed in order (but not necessarily consecutively) by a single hart, the sequence SFENCE.W.INVAL, SINVAL.VMA, and SFENCE.INVAL.IR has the same effect as a hypothetical SFENCE.VMA instruction in which:",SW_rule,unknown,high,False, +chunk_caad67f7,src/priv/svinval.adoc,44,"Preamble > ""Svinval"" Extension for Fine-Grained Address-Translation Cache Invalidation, Version 1.0","If the hypervisor extension is implemented, the Svinval extension also provides two additional instructions: HINVAL.VVMA and HINVAL.GVMA.",SW_rule,unknown,high,False, +chunk_a8944c07,src/priv/svinval.adoc,51,"Preamble > ""Svinval"" Extension for Fine-Grained Address-Translation Cache Invalidation, Version 1.0","SINVAL.VMA, HINVAL.VVMA, and HINVAL.GVMA require the same permissions and raise the same exceptions as SFENCE.VMA, HFENCE.VVMA, and HFENCE.GVMA, respectively.",SW_rule,unknown,high,False, +chunk_250539d5,src/priv/svinval.adoc,51,"Preamble > ""Svinval"" Extension for Fine-Grained Address-Translation Cache Invalidation, Version 1.0","In particular, an attempt to execute any of these instructions in U-mode always raises an illegal-instruction exception.",non_CSR_parameter,unknown,high,False, +chunk_4db70e23,src/priv/svinval.adoc,51,"Preamble > ""Svinval"" Extension for Fine-Grained Address-Translation Cache Invalidation, Version 1.0",An attempt to execute SINVAL.VMA or HINVAL.GVMA in S-mode or HS-mode when `mstatus`.TVM=1 also raises an illegal-instruction exception.,CSR_controlled,enum,high,False, +chunk_e2aac167,src/priv/svinval.adoc,51,"Preamble > ""Svinval"" Extension for Fine-Grained Address-Translation Cache Invalidation, Version 1.0","An attempt to execute HINVAL.VVMA or HINVAL.GVMA in VS-mode or VU-mode, or to execute SINVAL.VMA in VU-mode, raises a virtual-instruction exception.",non_CSR_parameter,unknown,high,False, +chunk_331e379d,src/priv/svinval.adoc,51,"Preamble > ""Svinval"" Extension for Fine-Grained Address-Translation Cache Invalidation, Version 1.0","When `hstatus`.VTVM=1, an attempt to execute SINVAL.VMA in VS-mode also raises a virtual-instruction exception.",CSR_controlled,enum,high,False, +chunk_3ceb82f7,src/priv/svinval.adoc,64,"Preamble > ""Svinval"" Extension for Fine-Grained Address-Translation Cache Invalidation, Version 1.0",Attempting to execute SFENCE.W.INVAL or SFENCE.INVAL.IR in U-mode raises an illegal-instruction exception.,SW_rule,unknown,high,False, +chunk_b05e4f51,src/priv/svinval.adoc,64,"Preamble > ""Svinval"" Extension for Fine-Grained Address-Translation Cache Invalidation, Version 1.0",Doing so in VU-mode raises a virtual-instruction exception. SFENCE.W.INVAL and SFENCE.INVAL.IR are unaffected by the `mstatus`.TVM and `hstatus`.VTVM fields and hence are always permitted in S-mode and VS-mode.,CSR_controlled,enum,high,False, +chunk_ecd6f9de,src/priv/svnapot.adoc,3,"Preamble > ""Svnapot"" Extension for NAPOT Translation Contiguity, Version 1.0","In Sv39, Sv48, and Sv57, when a PTE has N=1, the PTE represents a translation that is part of a range of contiguous virtual-to-physical translations with the same values for PTE bits 5–0.",unknown,unknown,high,False, +chunk_66d2331c,src/priv/svnapot.adoc,3,"Preamble > ""Svnapot"" Extension for NAPOT Translation Contiguity, Version 1.0",Such ranges must be of a naturally aligned power-of-2 (NAPOT) granularity larger than the base page size.,non_CSR_parameter,enum,very_high,False, +chunk_7202caf4,src/priv/svnapot.adoc,48,"Preamble > ""Svnapot"" Extension for NAPOT Translation Contiguity, Version 1.0","If the encoding in pte is reserved according to , then a page-fault exception must be raised.",non_CSR_parameter,enum,very_high,False, +chunk_faa2188a,src/priv/svnapot.adoc,58,"Preamble > ""Svnapot"" Extension for NAPOT Translation Contiguity, Version 1.0","Implicit reads of NAPOT page table entries may create address-translation cache entries mapping a + j×PTESIZE to a copy of pte in which pte.ppn[i][pte.napotbits-1:0] is replaced by vpn[i][pte.napotbits-1:0], for any or all j such that j >> napotbits = vpn[i] >> napotbits, all for the address space identified in satp as loaded by step 1.",CSR_controlled,enum,high,False, +chunk_0a841634,src/priv/svnapot.adoc,66,"Preamble > ""Svnapot"" Extension for NAPOT Translation Contiguity, Version 1.0","If the hypervisor extension is also implemented, Svnapot is also supported in G-stage translation.",SW_rule,unknown,high,False, +chunk_949e305e,src/priv/svpbmt.adoc,8,"Preamble > ""Svpbmt"" Extension for Page-Based Memory Types, Version 1.0",The Svpbmt extension depends on the Sv39 extension.,non_CSR_parameter,unknown,medium,False, +chunk_ce829e0a,src/priv/svpbmt.adoc,29,"Preamble > ""Svpbmt"" Extension for Page-Based Memory Types, Version 1.0",Implementations may override additional PMAs not explicitly listed in .,non_CSR_parameter,enum,medium,False, +chunk_2bf0ed54,src/priv/svpbmt.adoc,36,"Preamble > ""Svpbmt"" Extension for Page-Based Memory Types, Version 1.0","Until their use is defined by a standard extension, they must be cleared by software for forward compatibility, or else a page-fault exception is raised.",SW_rule,binary,very_high,False, +chunk_7dc4d6dd,src/priv/svpbmt.adoc,41,"Preamble > ""Svpbmt"" Extension for Page-Based Memory Types, Version 1.0","Until this value is defined by a standard extension, using this reserved value in a leaf PTE raises a page-fault exception.",non_CSR_parameter,unknown,high,False, +chunk_9a0950c8,src/priv/svpbmt.adoc,46,"Preamble > ""Svpbmt"" Extension for Page-Based Memory Types, Version 1.0","When PBMT settings override a main memory page into I/O or vice versa, memory accesses to such pages obey the memory ordering rules of the final effective attribute, as follows.",unknown,unknown,high,False, +chunk_0a01fde2,src/priv/svpbmt.adoc,50,"Preamble > ""Svpbmt"" Extension for Page-Based Memory Types, Version 1.0","If the underlying physical memory attribute for a page is I/O, and the page has PBMT=NC, then accesses to that page obey RVWMO.",unknown,unknown,high,False, +chunk_3b9c65a4,src/priv/svpbmt.adoc,56,"Preamble > ""Svpbmt"" Extension for Page-Based Memory Types, Version 1.0","If the underlying physical memory attribute for a page is main memory, and the page has PBMT=IO, then accesses to that page obey strong channel 0 I/O ordering rules.",unknown,unknown,high,False, +chunk_7ee25014,src/priv/svpbmt.adoc,64,"Preamble > ""Svpbmt"" Extension for Page-Based Memory Types, Version 1.0","When Svpbmt is used with non-zero PBMT encodings, it is possible for multiple virtual aliases of the same physical page to exist simultaneously with different memory attributes.",unknown,enum,high,False, +chunk_91dd53d1,src/priv/svpbmt.adoc,64,"Preamble > ""Svpbmt"" Extension for Page-Based Memory Types, Version 1.0",It is also possible for a U-mode or S-mode mapping through a PTE with Svpbmt enabled to observe different memory attributes for a given region of physical memory than a concurrent access to the same page performed by M-mode or when MODE=Bare.,unknown,binary,high,False, +chunk_483457c4,src/priv/svpbmt.adoc,64,"Preamble > ""Svpbmt"" Extension for Page-Based Memory Types, Version 1.0","In such cases, the behaviors dictated by the attributes (including coherence, which is otherwise unaffected) may be violated.",non_CSR_parameter,enum,medium,False, +chunk_0e9cb553,src/priv/svpbmt.adoc,82,"Preamble > ""Svpbmt"" Extension for Page-Based Memory Types, Version 1.0",Accessing the same location using different cacheability attributes may cause loss of coherence.,SW_rule,enum,medium,False, +chunk_0ab2df1f,src/priv/svpbmt.adoc,90,"Preamble > ""Svpbmt"" Extension for Page-Based Memory Types, Version 1.0","When two-stage address translation is enabled within the H extension, the page-based memory types are also applied in two stages.",unknown,binary,high,False, +chunk_c6573d85,src/priv/svpbmt.adoc,90,"Preamble > ""Svpbmt"" Extension for Page-Based Memory Types, Version 1.0","First, if `hgatp`.MODE is not equal to zero, non-zero G-stage PTE PBMT bits override the attributes in the PMA to produce an intermediate set of attributes.",CSR_controlled,range,high,False, +chunk_b3b02c59,src/priv/svpbmt.adoc,90,"Preamble > ""Svpbmt"" Extension for Page-Based Memory Types, Version 1.0","Second, if `vsatp`.MODE is not equal to zero, non-zero VS-stage PTE PBMT bits override the intermediate attributes to produce the final set of attributes used by accesses to the page in question.",CSR_controlled,range,high,False, +chunk_777716e1,src/priv/svrsw60t59b.adoc,3,"Preamble > ""Svrsw60t59b"" Extension for PTE Reserved-for-Software Bits 60-59, Version 1.0","If the Svrsw60t59b extension is implemented, then bits 60-59 of the page table entries (PTEs) are reserved for use by supervisor software and are ignored by the implementation.",SW_rule,unknown,high,False, +chunk_f9f6c4f7,src/priv/svrsw60t59b.adoc,7,"Preamble > ""Svrsw60t59b"" Extension for PTE Reserved-for-Software Bits 60-59, Version 1.0","If the Hypervisor (H) extension is also implemented, then bits 60-59 of the G-stage PTEs are reserved for use by supervisor software and are ignored by the implementation.",SW_rule,unknown,high,False, +chunk_7c0a003a,src/priv/svvptc.adoc,3,"Preamble > ""Svvptc"" Extension for Obviating Memory-Management Instructions after Marking PTEs Valid, Version 1.0","When the Svvptc extension is implemented, explicit stores by a hart that update the Valid bit of leaf and/or non-leaf PTEs from 0 to 1 and are visible to a hart will eventually become visible within a bounded timeframe to subsequent implicit accesses by that hart to such PTEs.",unknown,unknown,high,False, +chunk_7a5af1ed,src/priv/zpm.adoc,5,"Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction","RISC-V Pointer Masking (PM) is a feature that, when enabled, causes the CPU to ignore the upper bits of the effective address (these terms will be defined more precisely in the Background section).",unknown,binary,high,False, +chunk_94721f37,src/priv/zpm.adoc,5,"Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction","When an address is accessed, the tag stored in the masked bits can be compared against a range-based tag.",unknown,unknown,high,False, +chunk_78883db8,src/priv/zpm.adoc,7,"Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction",HWASAN leverages tags in the upper bits of the address to identify memory errors such as use-after-free or buffer overflow errors.,unknown,enum,high,False, +chunk_52100761,src/priv/zpm.adoc,7,"Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction","By storing a *pointer tag* in the upper bits of the address and checking it against a *memory tag* stored in a side table, it can identify whether a pointer is pointing to a valid location.",unknown,enum,high,False, +chunk_ebe5c58a,src/priv/zpm.adoc,9,"Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction","If implemented in software, pointer masking still provides performance benefits since non-checked accesses do not need to transform the address before every memory access.",SW_rule,unknown,high,False, +chunk_aceb5398,src/priv/zpm.adoc,9,"Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction",We anticipate that future extensions may build on pointer masking to support this functionality in hardware.,non_CSR_parameter,enum,medium,False, +chunk_fbc8d538,src/priv/zpm.adoc,11,"Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction","It is worth mentioning that while HWASAN is the primary use-case for the current pointer masking extension, a number of other hardware/software features may be implemented leveraging Pointer Masking.",SW_rule,enum,medium,False, +chunk_9422a2ab,src/priv/zpm.adoc,29,"Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Definitions","For a virtual address to be valid, all bits in the unused portion of the address must be the same as the Most Significant Bit (MSB) of the used portion.",non_CSR_parameter,enum,very_high,False, +chunk_c8278984,src/priv/zpm.adoc,29,"Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Definitions","For example, when page-based 48-bit virtual memory (Sv48) is used, load/store effective addresses, which are 64 bits, must have bits 63–48 all set to bit 47, or else a page-fault exception will occur.",non_CSR_parameter,range,very_high,False, +chunk_3f6adea4,src/priv/zpm.adoc,29,"Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Definitions","For physical addresses, validity means that bits XLEN-1 to PABITS are zero, where PABITS is the number of physical address bits supported by the processor.",SW_rule,unknown,high,False, +chunk_0365e5ec,src/priv/zpm.adoc,38,"Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > The “Ignore” Transformation","For virtual addresses, it replaces the upper PMLEN bits with the sign extension of the PMLEN+1st bit.",unknown,unknown,high,False, +chunk_1c81162f,src/priv/zpm.adoc,63,"Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > The “Ignore” Transformation",Pointer masking with the same value of PMLEN always has the same effect for the same type of address (virtual or physical).,unknown,enum,high,False, +chunk_99b6538c,src/priv/zpm.adoc,67,"Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Example",shows an example of the pointer masking transformation on a virtual address when PM is enabled for RV64 under Sv57 (PMLEN=7).,unknown,binary,high,False, +chunk_898786fb,src/priv/zpm.adoc,86,"Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Example","If the address was a physical address rather than a virtual address with Sv57, the transformed address with PMLEN=7 would be 0x1FFFFFF12345678.",unknown,unknown,high,False, +chunk_4c79b038,src/priv/zpm.adoc,90,"Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Determining the Value of PMLEN","In particular, applying the above transformation is cheap if it covers only bits that are not used by **any** supported address translation mode (as it is equivalent to switching off validity checks).",unknown,unknown,high,False, +chunk_02d6eb76,src/priv/zpm.adoc,90,"Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Determining the Value of PMLEN","Masking NVBITS beyond those bits is more expensive as it requires ignoring them in the TLB tag, and even more expensive if the masked bits extend into the VBITS portion of the address (as it requires performing the actual sign extension).",non_CSR_parameter,unknown,high,False, +chunk_1c4eaa8a,src/priv/zpm.adoc,90,"Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Determining the Value of PMLEN","Similarly, when running in Bare or M mode, it is common for implementations to not use a particular number of bits at the top of the physical address range and fix them to zero.",unknown,unknown,high,False, +chunk_969c9b50,src/priv/zpm.adoc,90,"Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Determining the Value of PMLEN","Applying the ignore transformation to those bits is cheap as well, since it will result in a valid physical address with all the upper bits fixed to 0.",unknown,enum,high,False, +chunk_c693c7f7,src/priv/zpm.adoc,92,"Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Determining the Value of PMLEN","In such future standards, different supported values of PMLEN may be defined for each privilege mode (U/VU, S/HS, and M).",non_CSR_parameter,enum,medium,False, +chunk_a6f133bc,src/priv/zpm.adoc,96,"Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Pointer Masking and Privilege Modes",Different privilege modes may have different pointer masking settings active simultaneously and the hardware will automatically apply the pointer masking settings of the currently active privilege mode. A privilege mode's pointer masking setting is configured by bits in configuration registers of the next-higher privilege mode.,non_CSR_parameter,enum,high,False, +chunk_3a71c473,src/priv/zpm.adoc,114,"Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Memory Accesses Subject to Pointer Masking","For other extensions, pointer masking applies to all explicit memory accesses by default.",unknown,unknown,high,False, +chunk_d464fac8,src/priv/zpm.adoc,114,"Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Memory Accesses Subject to Pointer Masking",Future extensions may add specific language to indicate whether particular accesses are or are not included in pointer masking.,non_CSR_parameter,enum,medium,False, +chunk_606de516,src/priv/zpm.adoc,120,"Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Memory Accesses Subject to Pointer Masking","In other words, the accessed bytes should be identical to the bytes that would be accessed if the pointer masking transformation was individually applied to every byte of the access without pointer masking.",non_CSR_parameter,enum,high,False, +chunk_5fbc989b,src/priv/zpm.adoc,122,"Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Memory Accesses Subject to Pointer Masking","No pointer masking operations are applied when software reads/writes to CSRs, including those meant to hold addresses.",CSR_controlled,enum,high,False, +chunk_d5fa3ce8,src/priv/zpm.adoc,122,"Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Memory Accesses Subject to Pointer Masking","If software stores tagged addresses into such CSRs, data load or data store operations based on those addresses are subject to pointer masking only if they are explicit () and pointer masking is enabled for the privilege mode that performs the access.",CSR_controlled,binary,high,False, +chunk_a1328fcc,src/priv/zpm.adoc,124,"Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Memory Accesses Subject to Pointer Masking","Pointer masking is also applied, when applicable, to the memory access address when matching address triggers in debug.",unknown,unknown,high,False, +chunk_2d2f10a5,src/priv/zpm.adoc,126,"Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Memory Accesses Subject to Pointer Masking","However, when delivering an exception, the hardware applies pointer masking to any address written into `stval` if pointer masking is applicable to that address.",CSR_controlled,enum,high,False, +chunk_bfe9321c,src/priv/zpm.adoc,131,"Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Pointer Masking Extensions",Profiles and implementations may choose to support an arbitrary subset of these extensions and must define valid ranges for their corresponding values of PMLEN.,non_CSR_parameter,enum,very_high,False, +chunk_ffdb1584,src/priv/zpm.adoc,135,"Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Pointer Masking Extensions","See , , , and . * **Smnpm**: A machine-level extension that provides pointer masking for the next lower privilege mode (S/HS if S-mode is implemented, or U-mode otherwise).",unknown,enum,high,False, +chunk_abd2209d,src/priv/zpm.adoc,146,"Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Pointer Masking Extensions","In RV32, trying to enable pointer masking will result in an illegal WARL write and not update the pointer masking configuration bits (see , , , and for details).",CSR_controlled,enum,very_high,False, +chunk_a63e63dc,src/priv/zpm.adoc,146,"Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Pointer Masking Extensions",The same is the case on RV64 or larger systems when UXL/SXL/MXL is set to 1 for the corresponding privilege mode.,unknown,binary,high,False, +chunk_68637b97,src/priv/zpm.adoc,150,"Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Number of Masked Bits","As described in , the supported values of PMLEN may depend on the effective privilege mode.",non_CSR_parameter,enum,medium,False, +chunk_211e7d6b,src/priv/zpm.adoc,150,"Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Number of Masked Bits","The current standard only defines PMLEN=XLEN-48 and PMLEN=XLEN-57, but this assumption may be relaxed in future extensions and profiles.",non_CSR_parameter,enum,medium,False, +chunk_9bc8489d,src/priv/zpm.adoc,150,"Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Number of Masked Bits",Trying to enable pointer masking in an unsupported scenario represents an illegal write to the corresponding pointer masking enable bit and follows WARL semantics.,CSR_controlled,enum,very_high,False, +chunk_57183289,src/priv/zpm.adoc,150,"Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Number of Masked Bits",Future profiles may choose to define certain combinations of privilege modes and supported values of PMLEN as mandatory.,non_CSR_parameter,enum,medium,False, +chunk_15e60371,src/profiles/intro.adoc,2,Preamble > Introduction,"In addition, users may add their own custom extensions.",non_CSR_parameter,enum,medium,False, +chunk_80de899b,src/profiles/intro.adoc,18,Preamble > Introduction,"Similarly, hardware vendors should aim to structure their offerings around standard profiles to increase the likelihood their designs will have mainstream software support.",SW_rule,enum,medium,False, +chunk_2770a245,src/profiles/intro.adoc,100,Preamble > Introduction > Components of a Profile > Profile Family,"A profile family may be updated no more than annually, and the release calendar year is treated as part of the profile family name.",non_CSR_parameter,enum,medium,False, +chunk_7d2c8e02,src/profiles/intro.adoc,134,Preamble > Introduction > Components of a Profile > Profile Privilege Mode,A profile may specify that certain conditions will cause a requested trap (such as an `ecall` made in the highest-supported privilege mode) or fatal trap to the enclosing execution environment.,SW_rule,enum,high,False, +chunk_2fbe7cda,src/profiles/intro.adoc,134,Preamble > Introduction > Components of a Profile > Profile Privilege Mode,The profile does not specify the behavior of the enclosing execution environment in handling requested or fatal traps.,SW_rule,unknown,high,False, +chunk_2c154bb9,src/profiles/intro.adoc,149,Preamble > Introduction > Components of a Profile > Profile Privilege Mode,A profile does not specify any invisible traps.,unknown,unknown,high,False, +chunk_b335a923,src/profiles/intro.adoc,174,Preamble > Introduction > Components of a Profile > Profile ISA Features,Implementations of the profile must provide these.,non_CSR_parameter,enum,very_high,False, +chunk_f2edd591,src/profiles/intro.adoc,180,Preamble > Introduction > Components of a Profile > Profile ISA Features,"The Optional category (also known as options) contains extensions that may be added as options, and which are expected to be generally supported as options by the software ecosystem for this profile.",SW_rule,enum,medium,False, +chunk_b756df3c,src/profiles/intro.adoc,184,Preamble > Introduction > Components of a Profile > Profile ISA Features,"Users would expect that software claiming compatibility with a profile would make use of any available supported options, but as a bare minimum software should not report errors or warnings when supported options are present in a system.",SW_rule,range,high,False, +chunk_7e0a106d,src/profiles/intro.adoc,191,Preamble > Introduction > Components of a Profile > Profile ISA Features,An optional extension may comprise many individually named and ratified extensions but a profile option requires all constituent extensions are present.,non_CSR_parameter,enum,medium,False, +chunk_96f9daf0,src/profiles/intro.adoc,191,Preamble > Introduction > Components of a Profile > Profile ISA Features,"In particular, unless explicitly listed as a profile option, individual extensions are not by themselves a profile option even when required as part of a profile option.",unknown,unknown,high,False, +chunk_9ffe54a6,src/profiles/intro.adoc,203,Preamble > Introduction > Components of a Profile > Profile ISA Features,All components of a ratified profile must themselves have been ratified.,non_CSR_parameter,enum,very_high,False, +chunk_247e3794,src/profiles/intro.adoc,206,Preamble > Introduction > Components of a Profile > Profile ISA Features,Platforms may provide a discovery mechanism to determine what optional extensions are present.,non_CSR_parameter,enum,medium,False, +chunk_e369cd93,src/profiles/intro.adoc,241,Preamble > Introduction > Components of a Profile > Profile Naming Convention,"RVI20U32 basic unprivileged instructions for RV32I - RVI20U64 basic unprivileged instructions for RV64I - RVA20U64, RVA20S64 64-bit application-processor profiles",non_CSR_parameter,range,medium,False, +chunk_80a99345,src/profiles/intro.adoc,268,Preamble > Introduction > Components of a Profile > RVA Profiles Rationale,The RISC-V International ISA extension ratification process ensures that all processor vendors have agreed to the specification of a standard extension if present.,unknown,unknown,high,False, +chunk_e2e689f3,src/profiles/intro.adoc,279,Preamble > Introduction > Components of a Profile > RVA Profiles Rationale,"Without proactive alignment through RVA profiles, RISC-V will be uncompetitive, as even if a particular vendor implements a certain feature, if other vendors do not, then binary distributions will not generally use that feature and all implementations will suffer.",unknown,unknown,high,False, +chunk_f2406c1c,src/profiles/intro.adoc,279,Preamble > Introduction > Components of a Profile > RVA Profiles Rationale,"While certain features may be discoverable, and alternate code provided in case of presence/absence of a feature, the added cost to support such options is only justified for certain limited cases, and binary app markets will not support a wide range of optional features, particularly for the nascent RISC-V binary app ecosystems.",non_CSR_parameter,enum,medium,False, +chunk_8d010d53,src/profiles/intro.adoc,296,Preamble > Introduction > Components of a Profile > RVA Profiles Rationale,"To maintain alignment and increase RISC-V competitiveness over time, the mandatory set of extensions must increase over time in successive generations of RVA profile. (RVA profiles may eventually have to deprecate previously mandatory instructions, but that is unlikely in the near future.) Note that the RISC-V ISA will continue to evolve, regardless of whether a given software ecosystem settles on a certain generation of profile as the baseline for their ecosystem for many years or even decades.",SW_rule,enum,very_high,False, +chunk_a6e7f95f,src/profiles/intro.adoc,323,Preamble > Introduction > Components of a Profile > RVA Profiles Rationale,"Processor vendors and software toolchain providers will have varying development schedules, and providing an optional phase in a new extension's lifecycle provides some flexibility while maintaining overall alignment, and is particularly appropriate when hardware or software development for the extension is complex.",SW_rule,unknown,high,False, +chunk_26d28117,src/profiles/intro.adoc,323,Preamble > Introduction > Components of a Profile > RVA Profiles Rationale,Denoting an extension as a development option signals to the community that development should be prioritized for such extensions as they will become mandatory.,non_CSR_parameter,enum,medium,False, +chunk_3e279dae,src/profiles/intro.adoc,335,Preamble > Introduction > Components of a Profile > RVA Profiles Rationale,"The third kind of optional extension are expansion options, which are those that may have a large implementation cost but are not always needed in a particular platform, and which can be readily handled by discovery.",non_CSR_parameter,enum,medium,False, +chunk_26341481,src/profiles/intro.adoc,335,Preamble > Introduction > Components of a Profile > RVA Profiles Rationale,Some unprivileged extensions that may fall into this category are possible future matrix extensions.,non_CSR_parameter,enum,medium,False, +chunk_79555281,src/profiles/intro.adoc,347,Preamble > Introduction > Components of a Profile > RVA Profiles Rationale,"The fourth kind of optional extensions are transitory options, where it is not clear if the extension will change to a mandatory, localized, or expansion option, or be possibly dropped over time.",unknown,unknown,high,False, +chunk_997e100b,src/profiles/intro.adoc,347,Preamble > Introduction > Components of a Profile > RVA Profiles Rationale,"Denoting an option as transitory signals to the community that this extension may be removed in a future profile, though the time scale may span many years.",non_CSR_parameter,enum,medium,False, +chunk_c80eb3e8,src/profiles/intro.adoc,361,Preamble > Introduction > Components of a Profile > RVA Profiles Rationale,"Binary distributions of applications willing to invest in discovery can use an optional extension, and customers compiling their own applications can take advantage of the feature on a particular implementation, even when that system is mostly running binary distributions that ignore the new extension.",unknown,unknown,high,False, +chunk_b5b626cd,src/profiles/preface.adoc,33,Preamble > Preface,Clarified that profile name can be used as ISA base string - Renamed Ssptead to Svade - Fixed Ssu64xl to make supporting UXL=64 mandatory - Added section listing new extension names in profiles document - Added new extension name Sscounterenw - Removed outdated text on Zicntr/Zihpm ratification plan,CSR_controlled,enum,high,False, +chunk_0fda19b9,src/profiles/rva20.adoc,21,Preamble > RVA20 Profiles > RVA20U64 Profile,The RVA20U64 profile specifies the ISA features available to user-mode execution environments in 64-bit applications processors.,SW_rule,range,medium,False, +chunk_155d4f9b,src/profiles/rva20.adoc,120,Preamble > RVA20 Profiles > RVA20S64 Profile,The RVA20S64 profile specifies the ISA features available to a supervisor-mode execution environment in 64-bit applications processors. RVA20S64 is based on privileged architecture version 1.11.,SW_rule,range,medium,False, +chunk_4168f1ab,src/profiles/rva22.adoc,8,Preamble > RVA22 Profiles > RVA22U64 Profile,The RVA22U64 profile specifies the ISA features available to user-mode execution environments in 64-bit applications processors.,SW_rule,range,medium,False, +chunk_a68349fe,src/profiles/rva22.adoc,128,Preamble > RVA22 Profiles > RVA22U64 Profile > RVA22U64 Optional Extensions,Profile implementers should provide all of the instructions in a given algorithm suite as part of the Zkn or Zks supported options.,non_CSR_parameter,enum,medium,False, +chunk_dda53980,src/profiles/rva22.adoc,153,Preamble > RVA22 Profiles > RVA22S64 Profile,The RVA22S64 profile specifies the ISA features available to a supervisor-mode execution environment in 64-bit applications processors. RVA22S64 is based on privileged architecture version 1.12.,SW_rule,range,medium,False, +chunk_44b8fbfe,src/profiles/rva23.adoc,15,Preamble > RVA23 Profiles > RVA23U64 Profile,The RVA23U64 profile specifies the ISA features available to user-mode execution environments in 64-bit applications processors.,SW_rule,range,medium,False, +chunk_8ef0b68d,src/profiles/rva23.adoc,30,Preamble > RVA23 Profiles > RVA23U64 Profile > RVA23U64 Mandatory Extensions,"These are implied by presence of F. - Base counters and timers. - Hardware performance counters. - Main memory regions with both the cacheability and coherence PMAs must support instruction fetch, and any instruction fetches of naturally aligned power-of-2 sizes up to min(ILEN,XLEN) (i.e., 32 bits for RVA23) are atomic. - Main memory regions with both the cacheability and coherence PMAs must support RsrvEventual. - Main memory regions with both the cacheability and coherence PMAs must support all atomics in the Zaamo extension. - Misaligned loads and stores to main memory regions with both the cacheability and coherence PMAs must be supported. - Reservation sets are contiguous, naturally aligned, and a maximum of 64 bytes. - Pause hint. - Cache blocks must be 64 bytes in size, naturally aligned in the address space. - Cache-block management instructions. - Cache-block prefetch instructions. - Cache-Block Zero Instructions. - ext:zfhmin[] Half-precision floating-point. - Data-independent execution latency.",SW_rule,range,very_high,False, +chunk_374cbbf6,src/profiles/rva23.adoc,160,Preamble > RVA23 Profiles > RVA23S64 Profile,The RVA23S64 profile specifies the ISA features available to a supervisor-mode execution environment in 64-bit applications processors. RVA23S64 is based on privileged architecture version 1.13.,SW_rule,range,medium,False, +chunk_2ad5f49d,src/profiles/rvb23.adoc,13,Preamble > RVB23 Profiles,"However, individual software ecosystems may build upon RVB profiles to produce a more targeted standard interface for a certain market.",SW_rule,enum,medium,False, +chunk_c81064e0,src/profiles/rvb23.adoc,24,Preamble > RVB23 Profiles > RVB23U64 Profile,The RVB23U64 profile specifies the ISA features available to user-mode execution environments in 64-bit RVB applications processors.,SW_rule,range,medium,False, +chunk_e06353df,src/profiles/rvb23.adoc,38,Preamble > RVB23 Profiles > RVB23U64 Profile > RVB23U64 Mandatory Extensions,"These are implied by presence of F. - Base counters and timers. - Hardware performance counters. - Main memory regions with both the cacheability and coherence PMAs must support instruction fetch, and any instruction fetches of naturally aligned power-of-2 sizes up to min(ILEN,XLEN) (i.e., 32 bits for RVB23) are atomic. - Main memory regions with both the cacheability and coherence PMAs must support RsrvEventual. - Main memory regions with both the cacheability and coherence PMAs must support all atomics in the Zaamo extension. - Misaligned loads and stores to main memory regions with both the cacheability and coherence PMAs must be supported. - Reservation sets are contiguous, naturally aligned, and a maximum of 64 bytes. - Pause hint. - Cache blocks must be 64 bytes in size, naturally aligned in the address space. - Cache-block management instructions. - Cache-block prefetch instructions. - Cache-block zero instructions. - Data-independent execution latency.",SW_rule,range,very_high,False, +chunk_b2aa2c8c,src/profiles/rvb23.adoc,163,Preamble > RVB23 Profiles > RVB23S64 Profile,The RVB23S64 profile specifies the ISA features available to a supervisor-mode execution environment in 64-bit applications processors. RVB23S64 is based on privileged architecture version 1.13.,SW_rule,range,medium,False, +chunk_45997cfd,src/profiles/rvb23.adoc,262,Preamble > RVB23 Profiles > RVB23S64 Profile > RVB23S64 Optional Extensions > Expansion Options,"When the hypervisor extension is implemented, the following are also mandatory:",SW_rule,unknown,high,False, +chunk_1a2d97bd,src/profiles/rvb23.adoc,264,Preamble > RVB23 Profiles > RVB23S64 Profile > RVB23S64 Optional Extensions > Expansion Options,"If the hypervisor extension is implemented and pointer masking (Ssnpm) is supported then `henvcfg.PMM` must support at minimum, settings PMLEN=0 and PMLEN=7.",CSR_controlled,range,very_high,False, +chunk_9593181a,src/profiles/rvi20.adoc,8,Preamble > RVI20 Profiles,"Code using this profile can run in any privilege mode, and so requested and fatal traps may be horizontal traps into an execution environment running in the same privilege mode.",SW_rule,enum,high,False, +chunk_dde43ce4,src/rv32.adoc,59,"Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Base Instruction Formats",All are a fixed 32 bits in length.,non_CSR_parameter,range,medium,False, +chunk_72a433ee,src/rv32.adoc,59,"Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Base Instruction Formats","The base ISA has `IALIGN=32`, meaning that instructions must be aligned on a four-byte boundary in memory.",non_CSR_parameter,enum,very_high,False, +chunk_f8060209,src/rv32.adoc,59,"Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Base Instruction Formats",An instruction-address-misaligned exception is generated on a taken branch or unconditional jump if the target address is not `IALIGN-bit` aligned.,unknown,unknown,high,False, +chunk_e7a49c43,src/rv32.adoc,59,"Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Base Instruction Formats","This exception is reported on the branch or jump instruction, not on the target instruction.",unknown,unknown,high,False, +chunk_3a4aa590,src/rv32.adoc,59,"Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Base Instruction Formats",No instruction-address-misaligned exception is generated for a conditional branch that is not taken.,unknown,unknown,high,False, +chunk_9319c030,src/rv32.adoc,70,"Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Base Instruction Formats","Except for the 5-bit immediates used in , immediates are always sign-extended, and are generally packed towards the leftmost available bits in the instruction and have been allocated to reduce hardware complexity.",non_CSR_parameter,range,high,False, +chunk_4594bc74,src/rv32.adoc,70,"Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Base Instruction Formats","In particular, the sign bit for all immediates is always in bit 31 of the instruction to speed sign-extension circuitry.",unknown,unknown,high,False, +chunk_0fbea2de,src/rv32.adoc,91,"Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Immediate Encoding Variants",The only difference between the S and B formats is that the 12-bit immediate field is used to encode branch offsets in multiples of 2 in the B format.,non_CSR_parameter,range,high,False, +chunk_0a395b3c,src/rv32.adoc,98,"Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Immediate Encoding Variants","Similarly, the only difference between the U and J formats is that the 20-bit immediate is shifted left by 12 bits to form U immediates and by 1 bit to form J immediates.",non_CSR_parameter,range,medium,False, +chunk_b05bec50,src/rv32.adoc,120,"Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Immediate Encoding Variants",The fields are labeled with the instruction bits used to construct their value.,unknown,enum,high,False, +chunk_ad69f5da,src/rv32.adoc,126,"Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions",Integer computational instructions are either encoded as register-immediate operations using the I-type format or as register-register operations using the R-type format.,unknown,enum,high,False, +chunk_49059c53,src/rv32.adoc,126,"Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions",No integer computational instructions cause arithmetic exceptions.,unknown,unknown,high,False, +chunk_94ce4b43,src/rv32.adoc,139,"Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Immediate Instructions",ADDI adds the sign-extended 12-bit immediate to register rs1.,non_CSR_parameter,range,high,False, +chunk_84b1ff1d,src/rv32.adoc,151,"Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Immediate Instructions","ANDI, ORI, XORI are logical operations that perform bitwise AND, OR, and XOR on register rs1 and the sign-extended 12-bit immediate and place the result in rd.",non_CSR_parameter,range,high,False, +chunk_4b7c9b86,src/rv32.adoc,160,"Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Immediate Instructions",Shifts by a constant are encoded as a specialization of the I-type format.,unknown,enum,high,False, +chunk_12f0b8cc,src/rv32.adoc,160,"Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Immediate Instructions","The operand to be shifted is in rs1, and the shift amount is encoded in the lower 5 bits of the I-immediate field.",non_CSR_parameter,range,high,False, +chunk_e620a15d,src/rv32.adoc,160,"Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Immediate Instructions",The right-shift type is encoded in bit 30. SLLI is a logical left shift (zeros are shifted into the lower bits); SRLI is a logical right shift (zeros are shifted into the upper bits); and SRAI is an arithmetic right shift (the original sign bit is copied into the vacated upper bits).,unknown,enum,high,False, +chunk_b359ead1,src/rv32.adoc,172,"Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Immediate Instructions","LUI (load upper immediate) is used to build 32-bit constants and uses the U-type format. LUI places the 32-bit U-immediate value into the destination register rd, filling in the lowest 12 bits with zeros.",non_CSR_parameter,range,high,False, +chunk_ce0e4a7b,src/rv32.adoc,176,"Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Immediate Instructions","AUIPC (add upper immediate to `pc`) is used to build `pc`-relative addresses and uses the U-type format. AUIPC forms a 32-bit offset from the U-immediate, filling in the lowest 12 bits with zeros, adds this offset to the address of the AUIPC instruction, then places the result in register rd.",non_CSR_parameter,range,high,False, +chunk_915f6f0d,src/rv32.adoc,185,"Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Register Instructions",RV32I defines several arithmetic R-type operations.,unknown,unknown,high,False, +chunk_bdfe71e4,src/rv32.adoc,185,"Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Register Instructions",All operations read the rs1 and rs2 registers as source operands and write the result into register rd.,unknown,unknown,high,False, +chunk_7b519a6d,src/rv32.adoc,185,"Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Register Instructions",The funct7 and funct3 fields select the type of operation.,unknown,enum,high,False, +chunk_34f52cee,src/rv32.adoc,193,"Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Register Instructions",ADD performs the addition of rs1 and rs2. SUB performs the subtraction of rs2 from rs1.,unknown,unknown,high,False, +chunk_2bfdf820,src/rv32.adoc,193,"Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Register Instructions","Overflows are ignored and the low XLEN bits of results are written to the destination rd. SLT and SLTU perform signed and unsigned compares respectively, writing 1 to rd if rs1 < rs2, 0 otherwise.",unknown,range,high,False, +chunk_1905f0e5,src/rv32.adoc,202,"Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Register Instructions","SLL, SRL, and SRA perform logical left, logical right, and arithmetic right shifts on the value in register rs1 by the shift amount held in the lower 5 bits of register rs2.",non_CSR_parameter,range,high,False, +chunk_f37f2594,src/rv32.adoc,212,"Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > NOP Instruction","The NOP instruction does not change any architecturally visible state, except for advancing the `pc` and incrementing any applicable performance counters. NOP is encoded as ADDI x0, x0, 0.",unknown,enum,high,False, +chunk_ec88eefb,src/rv32.adoc,223,"Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Control Transfer Instructions","If an instruction access-fault or instruction page-fault exception occurs on the target of a jump or taken branch, the exception is reported on the target instruction, not on the jump or branch instruction.",unknown,unknown,high,False, +chunk_d81dc38f,src/rv32.adoc,228,"Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Control Transfer Instructions > Unconditional Jumps","The jump and link (JAL) instruction uses the J-type format, where the J-immediate encodes a signed offset in multiples of 2 bytes.",non_CSR_parameter,range,medium,False, +chunk_917bdbde,src/rv32.adoc,228,"Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Control Transfer Instructions > Unconditional Jumps",The offset is sign-extended and added to the address of the jump instruction to form the jump target address.,unknown,enum,high,False, +chunk_01cc4f0c,src/rv32.adoc,237,"Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Control Transfer Instructions > Unconditional Jumps",Plain unconditional jumps (assembler pseudoinstruction J) are encoded as a JAL with rd=`x0`.,unknown,enum,high,False, +chunk_e8acee9e,src/rv32.adoc,244,"Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Control Transfer Instructions > Unconditional Jumps","The target address is obtained by adding the sign-extended 12-bit I-immediate to the register rs1, then setting the least-significant bit of the result to zero.",non_CSR_parameter,range,high,False, +chunk_ece4ef36,src/rv32.adoc,253,"Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Control Transfer Instructions > Unconditional Jumps",Plain unconditional indirect jumps (assembler pseudoinstruction JR) are encoded as a JALR with rd=`x0`.,unknown,enum,high,False, +chunk_9ecf4a48,src/rv32.adoc,253,"Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Control Transfer Instructions > Unconditional Jumps","Procedure returns in the standard calling convention (assembler pseudoinstruction RET) are encoded as a JALR with rd=`x0`, rs1=`x1`, and imm=0.",SW_rule,enum,high,False, +chunk_dfe1ce09,src/rv32.adoc,263,"Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Control Transfer Instructions > Unconditional Jumps",The JAL and JALR instructions will generate an instruction-address-misaligned exception if the target address is not aligned to a four-byte boundary.,unknown,unknown,high,False, +chunk_9f5519b1,src/rv32.adoc,268,"Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Control Transfer Instructions > Unconditional Jumps","For RISC-V, hints as to the instructions' usage are encoded implicitly via the register numbers used. A JAL instruction should push the return address onto a return-address stack (RAS) only when rd is `x1` or `x5`. JALR instructions should push/pop a RAS as shown in .",non_CSR_parameter,enum,high,False, +chunk_f184ab33,src/rv32.adoc,295,"Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Control Transfer Instructions > Conditional Branches",The 12-bit B-immediate encodes signed offsets in multiples of 2 bytes.,non_CSR_parameter,range,high,False, +chunk_44817fbd,src/rv32.adoc,295,"Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Control Transfer Instructions > Conditional Branches",The offset is sign-extended and added to the address of the branch instruction to give the target address.,unknown,enum,high,False, +chunk_9914be09,src/rv32.adoc,304,"Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Control Transfer Instructions > Conditional Branches","Branch instructions compare two registers. BEQ and BNE take the branch if registers rs1 and rs2 are equal or unequal respectively. BLT and BLTU take the branch if rs1 is less than rs2, using signed and unsigned comparison respectively. BGE and BGEU take the branch if rs1 is greater than or equal to rs2, using signed and unsigned comparison respectively.",unknown,range,high,False, +chunk_69267ea6,src/rv32.adoc,313,"Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Control Transfer Instructions > Conditional Branches","Software should be optimized such that the sequential code path is the most common path, with less-frequently taken code paths placed out of line.",SW_rule,enum,medium,False, +chunk_bbd08a71,src/rv32.adoc,313,"Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Control Transfer Instructions > Conditional Branches","Software should also assume that backward branches will be predicted taken and forward branches as not taken, at least the first time they are encountered.",SW_rule,range,medium,False, +chunk_c1aeac41,src/rv32.adoc,313,"Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Control Transfer Instructions > Conditional Branches",Dynamic predictors should quickly learn any predictable branch behavior.,non_CSR_parameter,enum,medium,False, +chunk_33e4b2e1,src/rv32.adoc,320,"Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Control Transfer Instructions > Conditional Branches","Unlike some other architectures, the RISC-V jump (JAL with rd=`x0`) instruction should always be used for unconditional branches instead of a conditional branch instruction with an always-true condition. RISC-V jumps are also PC-relative and support a much wider offset range than branches, and will not pollute conditional-branch prediction tables.",non_CSR_parameter,enum,medium,False, +chunk_c28b211b,src/rv32.adoc,326,"Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Control Transfer Instructions > Conditional Branches",The conditional branch instructions will generate an instruction-address-misaligned exception if the target address is not aligned to a four-byte boundary and the branch condition evaluates to true.,unknown,unknown,high,False, +chunk_e7513289,src/rv32.adoc,326,"Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Control Transfer Instructions > Conditional Branches","If the branch condition evaluates to false, the instruction-address-misaligned exception will not be raised.",non_CSR_parameter,unknown,high,False, +chunk_ca8fd2de,src/rv32.adoc,335,"Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Load and Store Instructions","RV32I is a load-store architecture, where only load and store instructions access memory and arithmetic instructions only operate on CPU registers. RV32I provides a 32-bit address space that is byte-addressed.",non_CSR_parameter,range,medium,False, +chunk_ae16cad0,src/rv32.adoc,335,"Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Load and Store Instructions",Loads with a destination of `x0` must still raise any exceptions and cause any other side effects even though the load value is discarded.,non_CSR_parameter,binary,very_high,False, +chunk_5569c979,src/rv32.adoc,352,"Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Load and Store Instructions",Loads are encoded in the I-type format and stores are S-type.,unknown,enum,high,False, +chunk_2a8af18e,src/rv32.adoc,352,"Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Load and Store Instructions",The effective address is obtained by adding register rs1 to the sign-extended 12-bit offset.,non_CSR_parameter,range,high,False, +chunk_4da3d9dc,src/rv32.adoc,359,"Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Load and Store Instructions","The LW instruction loads a 32-bit value from memory into rd. LH loads a 16-bit value from memory, then sign-extends to 32-bits before storing in rd. LHU loads a 16-bit value from memory but then zero extends to 32-bits before storing in rd. LB and LBU are defined analogously for 8-bit values.",non_CSR_parameter,range,high,False, +chunk_57fdf6ef,src/rv32.adoc,359,"Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Load and Store Instructions","The SW, SH, and SB instructions store 32-bit, 16-bit, and 8-bit values from the low bits of register rs2 to memory.",non_CSR_parameter,range,medium,False, +chunk_d8c7e353,src/rv32.adoc,368,"Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Load and Store Instructions","Regardless of EEI, loads and stores whose effective addresses are naturally aligned shall not raise an address-misaligned exception.",non_CSR_parameter,binary,very_high,False, +chunk_ae37b9d2,src/rv32.adoc,374,"Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Load and Store Instructions","An EEI may guarantee that misaligned loads and stores are fully supported, and so the software running inside the execution environment will never experience a contained or fatal address-misaligned trap.",SW_rule,enum,high,False, +chunk_260889fa,src/rv32.adoc,374,"Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Load and Store Instructions","In this case, the misaligned loads and stores can be handled in hardware, or via an invisible trap into the execution environment implementation, or possibly a combination of hardware and invisible trap depending on address.",SW_rule,unknown,high,False, +chunk_55916c7b,src/rv32.adoc,381,"Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Load and Store Instructions",An EEI may not guarantee misaligned loads and stores are handled invisibly.,non_CSR_parameter,enum,medium,False, +chunk_ae5fb4ba,src/rv32.adoc,381,"Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Load and Store Instructions","In this case, loads and stores that are not naturally aligned may either complete execution successfully or raise an exception.",non_CSR_parameter,enum,high,False, +chunk_e1beb254,src/rv32.adoc,381,"Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Load and Store Instructions",The exception raised can be either an address-misaligned exception or an access-fault exception.,non_CSR_parameter,enum,high,False, +chunk_6cd82589,src/rv32.adoc,381,"Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Load and Store Instructions","When an EEI does not guarantee misaligned loads and stores are handled invisibly, the EEI must define if exceptions caused by address misalignment result in a contained trap (allowing software running inside the execution environment to handle the trap) or a fatal trap (terminating execution).",SW_rule,binary,very_high,False, +chunk_37e765b8,src/rv32.adoc,410,"Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Memory Ordering Instructions","Any combination of device input (I), device output (O), memory reads \(R), and memory writes (W) may be ordered with respect to any combination of the same.",non_CSR_parameter,enum,medium,False, +chunk_aaf24c03,src/rv32.adoc,425,"Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Memory Ordering Instructions","The EEI will define what I/O operations are possible, and in particular, which memory addresses when accessed by load and store instructions will be treated and ordered as device input and device output operations respectively rather than memory reads and writes.",unknown,unknown,high,False, +chunk_e40002b0,src/rv32.adoc,435,"Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Memory Ordering Instructions","[float=""center"",align=""center"",cols=""^1,^1,<3"",options=""header""] .Fence mode encoding | |fm field |Mnemonic suffix|Meaning |0000 |none |Normal Fence |1000 |.TSO |With `FENCE RW,RW`: exclude write-to-read ordering; otherwise: Reserved for future use. |other|other |Reserved for future use. |",SW_rule,enum,high,False, +chunk_0e740e7a,src/rv32.adoc,445,"Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Memory Ordering Instructions",The FENCE mode field fm defines the semantics of the FENCE instruction. A `FENCE` (with fm=`0000`) orders all memory operations in its predecessor set before all memory operations in its successor set.,SW_rule,enum,high,False, +chunk_1a58f3c1,src/rv32.adoc,450,"Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Memory Ordering Instructions","A `FENCE.TSO` instruction is encoded as a FENCE instruction with fm=`1000`, predecessor=`RW`, and successor=`RW`. `FENCE.TSO` orders all load operations in its predecessor set before all memory operations in its successor set, and all store operations in its predecessor set before all store operations in its successor set.",SW_rule,enum,high,False, +chunk_6b260b03,src/rv32.adoc,459,"Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Memory Ordering Instructions",The unused fields in the FENCE instructions--rs1 and rd--are reserved for finer-grain fences in future extensions.,SW_rule,enum,high,False, +chunk_6d645c2d,src/rv32.adoc,459,"Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Memory Ordering Instructions","For forward compatibility, base implementations shall ignore these fields, and standard software shall zero these fields.",SW_rule,enum,very_high,False, +chunk_ed1e2d3c,src/rv32.adoc,459,"Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Memory Ordering Instructions","Base implementations shall treat all such reserved configurations as `FENCE` instructions (with fm=`0000`), and standard software shall use only non-reserved configurations.",SW_rule,enum,very_high,False, +chunk_bdd6d9f3,src/rv32.adoc,472,"Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Environment Call and Breakpoints",`SYSTEM` instructions are used to access system functionality that might require privileged access and are encoded using the I-type instruction format.,unknown,enum,high,False, +chunk_9a736d87,src/rv32.adoc,472,"Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Environment Call and Breakpoints","These can be divided into two main classes: those that atomically read-modify-write control and status registers (CSRs), and all other potentially privileged instructions. CSR instructions are described in , and the base unprivileged instructions are described in the following section.",CSR_controlled,enum,high,False, +chunk_761f8a99,src/rv32.adoc,484,"Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Environment Call and Breakpoints",These two instructions cause a precise requested trap to the supporting execution environment.,SW_rule,unknown,high,False, +chunk_eb9fbe58,src/rv32.adoc,500,"Preamble > RV32I Base Integer Instruction Set, Version 2.1 > HINT Instructions",Implementations are always allowed to ignore the encoded hints.,unknown,enum,high,False, +chunk_e33f8e72,src/rv32.adoc,507,"Preamble > RV32I Base Integer Instruction Set, Version 2.1 > HINT Instructions",Most RV32I HINTs are encoded as integer computational instructions with rd=`x0`.,unknown,enum,high,False, +chunk_c3d6c8d0,src/rv32.adoc,507,"Preamble > RV32I Base Integer Instruction Set, Version 2.1 > HINT Instructions",The other RV32I HINTs are encoded as FENCE instructions with a null predecessor or successor set and with fm=0.,SW_rule,enum,high,False, +chunk_42c80d6c,src/rv32e.adoc,3,"Preamble > RV32E and RV64E Base Integer Instruction Sets, Version 2.0","This chapter only outlines the differences between RV32E/RV64E and RV32I/RV64I, and so should be read after and .",non_CSR_parameter,enum,medium,False, +chunk_705a2320,src/rv64.adoc,3,"Preamble > RV64I Base Integer Instruction Set, Version 2.1","This chapter presents only the differences with RV32I, so should be read in conjunction with the earlier chapter.",non_CSR_parameter,enum,medium,False, +chunk_93b43291,src/rv64.adoc,10,"Preamble > RV64I Base Integer Instruction Set, Version 2.1 > Register State",RV64I widens the integer registers and supported user address space to 64 bits (XLEN=64 in ).,non_CSR_parameter,range,high,False, +chunk_f3a36c8b,src/rv64.adoc,15,"Preamble > RV64I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions","Additional instruction variants are provided to manipulate 32-bit values in RV64I, indicated by a 'W' suffix to the opcode.",non_CSR_parameter,range,medium,False, +chunk_6b73e97b,src/rv64.adoc,31,"Preamble > RV64I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Immediate Instructions",ADDIW is an RV64I instruction that adds the sign-extended 12-bit immediate to register rs1 and produces the proper sign extension of a 32-bit result in rd.,non_CSR_parameter,range,high,False, +chunk_3168746c,src/rv64.adoc,42,"Preamble > RV64I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Immediate Instructions",Shifts by a constant are encoded as a specialization of the I-type format using the same instruction opcode as RV32I.,unknown,enum,high,False, +chunk_8f71ba9f,src/rv64.adoc,42,"Preamble > RV64I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Immediate Instructions","The operand to be shifted is in rs1, and the shift amount is encoded in the lower 6 bits of the I-immediate field for RV64I.",non_CSR_parameter,range,high,False, +chunk_404f8bd5,src/rv64.adoc,42,"Preamble > RV64I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Immediate Instructions",The right-shift type is encoded in bit 30. SLLI is a logical left shift (zeros are shifted into the lower bits); SRLI is a logical right shift (zeros are shifted into the upper bits); and SRAI is an arithmetic right shift (the original sign bit is copied into the vacated upper bits).,unknown,enum,high,False, +chunk_dbcbdead,src/rv64.adoc,67,"Preamble > RV64I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Immediate Instructions","LUI (load upper immediate) uses the same opcode as RV32I. LUI places the 32-bit U-immediate into register rd, filling in the lowest 12 bits with zeros.",non_CSR_parameter,range,high,False, +chunk_744d2c07,src/rv64.adoc,67,"Preamble > RV64I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Immediate Instructions",The 32-bit result is sign-extended to 64 bits.,non_CSR_parameter,range,high,False, +chunk_f6f4fcf3,src/rv64.adoc,73,"Preamble > RV64I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Immediate Instructions","AUIPC (add upper immediate to `pc`) uses the same opcode as RV32I. AUIPC is used to build `pc`-relative addresses and uses the U-type format. AUIPC forms a 32-bit offset from the U-immediate, filling in the lowest 12 bits with zeros, sign-extends the result to 64 bits, adds it to the address of the AUIPC instruction, then places the result in register rd.",non_CSR_parameter,range,high,False, +chunk_1d4e289c,src/rv64.adoc,86,"Preamble > RV64I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Register Operations",ADDW and SUBW are RV64I-only instructions that are defined analogously to ADD and SUB but operate on 32-bit values and produce signed 32-bit results.,non_CSR_parameter,range,high,False, +chunk_fcd1d6d8,src/rv64.adoc,93,"Preamble > RV64I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Register Operations","SLL, SRL, and SRA perform logical left, logical right, and arithmetic right shifts on the value in register rs1 by the shift amount held in register rs2.",unknown,unknown,high,False, +chunk_257157c9,src/rv64.adoc,93,"Preamble > RV64I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Register Operations","In RV64I, only the low 6 bits of rs2 are considered for the shift amount.",non_CSR_parameter,range,high,False, +chunk_345ea0be,src/rv64.adoc,98,"Preamble > RV64I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Register Operations","SLLW, SRLW, and SRAW are RV64I-only instructions that are analogously defined but operate on 32-bit values and sign-extend their 32-bit results to 64 bits.",non_CSR_parameter,range,high,False, +chunk_e51f954c,src/rv64.adoc,98,"Preamble > RV64I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Register Operations",The shift amount is given by rs2[4:0].,unknown,unknown,high,False, +chunk_e9dca960,src/rv64.adoc,107,"Preamble > RV64I Base Integer Instruction Set, Version 2.1 > Load and Store Instructions",RV64I extends the address space to 64 bits.,non_CSR_parameter,range,medium,False, +chunk_078852ca,src/rv64.adoc,114,"Preamble > RV64I Base Integer Instruction Set, Version 2.1 > Load and Store Instructions",The LD instruction loads a 64-bit value from memory into register rd for RV64I.,non_CSR_parameter,range,medium,False, +chunk_f9ee47d5,src/rv64.adoc,118,"Preamble > RV64I Base Integer Instruction Set, Version 2.1 > Load and Store Instructions",The LW instruction loads a 32-bit value from memory and sign-extends this to 64 bits before storing it in register rd for RV64I.,non_CSR_parameter,range,high,False, +chunk_aa3d0f8f,src/rv64.adoc,118,"Preamble > RV64I Base Integer Instruction Set, Version 2.1 > Load and Store Instructions","The LWU instruction, on the other hand, zero-extends the 32-bit value from memory for RV64I. LH and LHU are defined analogously for 16-bit values, as are LB and LBU for 8-bit values.",non_CSR_parameter,range,high,False, +chunk_6fb41617,src/rv64.adoc,118,"Preamble > RV64I Base Integer Instruction Set, Version 2.1 > Load and Store Instructions","The SD, SW, SH, and SB instructions store 64-bit, 32-bit, 16-bit, and 8-bit values from the low bits of register rs2 to memory respectively.",non_CSR_parameter,range,medium,False, +chunk_835623bc,src/scalar-crypto.adoc,25,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Introduction > Intended Audience","Where possible, we have written this specification to be understandable by all, though we recognise that the motivations and references to algorithms or other specifications and standards may be unfamiliar to those who are not domain experts.",non_CSR_parameter,enum,medium,False, +chunk_715aa5be,src/scalar-crypto.adoc,32,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Introduction > Intended Audience","We hope this aids people's understanding of which aspects of the specification are particularly relevant to them, and which they may (safely!) ignore or pass to a colleague.",non_CSR_parameter,enum,medium,False, +chunk_cf9fe0f9,src/scalar-crypto.adoc,41,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Introduction > Intended Audience","They should understand fairly obviously the motivations for the instructions we include, and be familiar with most of the algorithms and outside standards to which we refer.",non_CSR_parameter,enum,medium,False, +chunk_bb3f5c91,src/scalar-crypto.adoc,60,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Introduction > Intended Audience","In particular, they should be aware of the literature around efficiently implementing AES and SM4 SBoxes in hardware.",non_CSR_parameter,enum,medium,False, +chunk_1b532d9a,src/scalar-crypto.adoc,134,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Introduction > Policies","It is anticipated that the NIST Lightweight Cryptography contest and the NIST Post-Quantum Cryptography contest may be dealt with this way, depending on timescales.",non_CSR_parameter,enum,medium,False, +chunk_1dad1470,src/scalar-crypto.adoc,145,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Introduction > Policies",The standard will not try to anticipate new useful low-level operations which may be useful as building blocks for future cryptographic constructs.,non_CSR_parameter,enum,medium,False, +chunk_9b188cc8,src/scalar-crypto.adoc,153,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Introduction > Policies","Regarding side-channel countermeasures: Where relevant, proposed instructions must aim to remove the possibility of any timing side-channels.",non_CSR_parameter,enum,very_high,False, +chunk_f50080cd,src/scalar-crypto.adoc,331,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Extensions Overview > `Zkr` - Entropy Source Extension",The entropy source extension defines the `seed` CSR at address `0x015`.,CSR_controlled,enum,high,False, +chunk_68a2f271,src/scalar-crypto.adoc,358,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Extensions Overview > `Zkn` - NIST Algorithm Suite",A core which implements `Zkn` must implement all of the above extensions.,non_CSR_parameter,enum,very_high,False, +chunk_c2899614,src/scalar-crypto.adoc,378,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Extensions Overview > `Zks` - ShangMi Algorithm Suite",A core which implements `Zks` must implement all of the above extensions.,non_CSR_parameter,enum,very_high,False, +chunk_b9e43f9d,src/scalar-crypto.adoc,396,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Extensions Overview > `Zk` - Standard scalar cryptography extension",A core which implements `Zk` must implement all of the above extensions.,non_CSR_parameter,enum,very_high,False, +chunk_92071d43,src/scalar-crypto.adoc,437,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes32dsi",This instruction must always be implemented such that its execution latency does not depend on the data being operated on.,non_CSR_parameter,enum,very_high,False, +chunk_80254b05,src/scalar-crypto.adoc,501,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes32dsmi",This instruction must always be implemented such that its execution latency does not depend on the data being operated on.,non_CSR_parameter,enum,very_high,False, +chunk_05b04f05,src/scalar-crypto.adoc,566,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes32esi",This instruction must always be implemented such that its execution latency does not depend on the data being operated on.,non_CSR_parameter,enum,very_high,False, +chunk_b055d155,src/scalar-crypto.adoc,630,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes32esmi",This instruction must always be implemented such that its execution latency does not depend on the data being operated on.,non_CSR_parameter,enum,very_high,False, +chunk_d19e8377,src/scalar-crypto.adoc,695,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64ds",This instruction must always be implemented such that its execution latency does not depend on the data being operated on.,non_CSR_parameter,enum,very_high,False, +chunk_71a82971,src/scalar-crypto.adoc,771,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64dsm",This instruction must always be implemented such that its execution latency does not depend on the data being operated on.,non_CSR_parameter,enum,very_high,False, +chunk_5e278710,src/scalar-crypto.adoc,848,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64es",This instruction must always be implemented such that its execution latency does not depend on the data being operated on.,non_CSR_parameter,enum,very_high,False, +chunk_56d7c71d,src/scalar-crypto.adoc,924,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64esm",This instruction must always be implemented such that its execution latency does not depend on the data being operated on.,non_CSR_parameter,enum,very_high,False, +chunk_28f0a134,src/scalar-crypto.adoc,1002,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64im",This instruction must always be implemented such that its execution latency does not depend on the data being operated on.,non_CSR_parameter,enum,very_high,False, +chunk_a1b9c042,src/scalar-crypto.adoc,1070,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64ks1i",This instruction must always be implemented such that its execution latency does not depend on the data being operated on.,non_CSR_parameter,enum,very_high,False, +chunk_9647158e,src/scalar-crypto.adoc,1145,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64ks2",This instruction must always be implemented such that its execution latency does not depend on the data being operated on.,non_CSR_parameter,enum,very_high,False, +chunk_076b266c,src/scalar-crypto.adoc,1315,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > clmul",foreach (i from 0 to (xlen - 1) by 1) { output = if ((rs2val >> i) & 1) then output ^ (rs1val << i); else output; },unknown,unknown,high,False, +chunk_022f233d,src/scalar-crypto.adoc,1374,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > clmulh",foreach (i from 1 to xlen by 1) { output = if ((rs2val >> i) & 1) then output ^ (rs1val >> (xlen - i)); else output; },unknown,unknown,high,False, +chunk_d8cd33b2,src/scalar-crypto.adoc,1707,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > rol","Operation:: [source,sail] -- let shamt = if xlen 32 then X(rs2)[4..0] else X(rs2)[5..0]; let result = (X(rs1) (xlen - shamt));",unknown,unknown,high,False, +chunk_d74b96a4,src/scalar-crypto.adoc,1758,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > rolw",The resulting word value is sign-extended by copying bit 31 to all of the more-significant bits.,unknown,enum,high,False, +chunk_7e7a5bc3,src/scalar-crypto.adoc,1814,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > ror","Operation:: [source,sail] -- let shamt = if xlen 32 then X(rs2)[4..0] else X(rs2)[5..0]; let result = (X(rs1) >> shamt) | (X(rs1) << (xlen - shamt));",unknown,unknown,high,False, +chunk_c3b2cbc9,src/scalar-crypto.adoc,1882,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > rori","Operation:: [source,sail] -- let shamt = if xlen 32 then shamt[4..0] else shamt[5..0]; let result = (X(rs1) >> shamt) | (X(rs1) << (xlen - shamt));",unknown,unknown,high,False, +chunk_e615fbc6,src/scalar-crypto.adoc,1933,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > roriw",The resulting word value is sign-extended by copying bit 31 to all of the more-significant bits.,unknown,enum,high,False, +chunk_ccf07a80,src/scalar-crypto.adoc,1989,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > rorw",The resultant word is sign-extended by copying bit 31 to all of the more-significant bits.,unknown,enum,high,False, +chunk_355a7b7f,src/scalar-crypto.adoc,2045,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha256sig0","For RV64, the low `32` bits of the source register are operated on, and the result sign extended to `XLEN` bits.",unknown,unknown,high,False, +chunk_4df9c70a,src/scalar-crypto.adoc,2045,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha256sig0",This instruction must always be implemented such that its execution latency does not depend on the data being operated on.,non_CSR_parameter,enum,very_high,False, +chunk_1e1e5800,src/scalar-crypto.adoc,2113,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha256sig1","For RV64, the low `32` bits of the source register are operated on, and the result sign extended to `XLEN` bits.",unknown,unknown,high,False, +chunk_d38aa277,src/scalar-crypto.adoc,2113,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha256sig1",This instruction must always be implemented such that its execution latency does not depend on the data being operated on.,non_CSR_parameter,enum,very_high,False, +chunk_959d20f8,src/scalar-crypto.adoc,2181,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha256sum0","For RV64, the low `32` bits of the source register are operated on, and the result sign extended to `XLEN` bits.",unknown,unknown,high,False, +chunk_d131292a,src/scalar-crypto.adoc,2181,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha256sum0",This instruction must always be implemented such that its execution latency does not depend on the data being operated on.,non_CSR_parameter,enum,very_high,False, +chunk_0dcd8f3d,src/scalar-crypto.adoc,2249,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha256sum1","For RV64, the low `32` bits of the source register are operated on, and the result sign extended to `XLEN` bits.",unknown,unknown,high,False, +chunk_a106de6a,src/scalar-crypto.adoc,2249,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha256sum1",This instruction must always be implemented such that its execution latency does not depend on the data being operated on.,non_CSR_parameter,enum,very_high,False, +chunk_d2accadf,src/scalar-crypto.adoc,2317,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig0h","The transform is a 64-bit to 64-bit function, so the input and output are each represented by two 32-bit registers.",non_CSR_parameter,range,medium,False, +chunk_6239e14b,src/scalar-crypto.adoc,2317,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig0h",This instruction must always be implemented such that its execution latency does not depend on the data being operated on.,non_CSR_parameter,enum,very_high,False, +chunk_0847b8dc,src/scalar-crypto.adoc,2326,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig0h",[NOTE] .Note to software developers The entire Sigma0 transform for SHA2-512 may be computed on RV32 using the following instruction sequence:,SW_rule,enum,medium,False, +chunk_909aad4b,src/scalar-crypto.adoc,2393,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig0l","The transform is a 64-bit to 64-bit function, so the input and output are each represented by two 32-bit registers.",non_CSR_parameter,range,medium,False, +chunk_2fa66283,src/scalar-crypto.adoc,2393,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig0l",This instruction must always be implemented such that its execution latency does not depend on the data being operated on.,non_CSR_parameter,enum,very_high,False, +chunk_5d2dfd93,src/scalar-crypto.adoc,2402,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig0l",[NOTE] .Note to software developers The entire Sigma0 transform for SHA2-512 may be computed on RV32 using the following instruction sequence:,SW_rule,enum,medium,False, +chunk_38f6c313,src/scalar-crypto.adoc,2469,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig1h","The transform is a 64-bit to 64-bit function, so the input and output are each represented by two 32-bit registers.",non_CSR_parameter,range,medium,False, +chunk_cd32f903,src/scalar-crypto.adoc,2469,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig1h",This instruction must always be implemented such that its execution latency does not depend on the data being operated on.,non_CSR_parameter,enum,very_high,False, +chunk_51a6b367,src/scalar-crypto.adoc,2478,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig1h",[NOTE] .Note to software developers The entire Sigma1 transform for SHA2-512 may be computed on RV32 using the following instruction sequence:,SW_rule,enum,medium,False, +chunk_1343e810,src/scalar-crypto.adoc,2545,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig1l","The transform is a 64-bit to 64-bit function, so the input and output are each represented by two 32-bit registers.",non_CSR_parameter,range,medium,False, +chunk_35a1679a,src/scalar-crypto.adoc,2545,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig1l",This instruction must always be implemented such that its execution latency does not depend on the data being operated on.,non_CSR_parameter,enum,very_high,False, +chunk_fa494a2e,src/scalar-crypto.adoc,2554,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig1l",[NOTE] .Note to software developers The entire Sigma1 transform for SHA2-512 may be computed on RV32 using the following instruction sequence:,SW_rule,enum,medium,False, +chunk_8428bd12,src/scalar-crypto.adoc,2621,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sum0r","The transform is a 64-bit to 64-bit function, so the input and output is represented by two 32-bit registers.",non_CSR_parameter,range,medium,False, +chunk_8697ed66,src/scalar-crypto.adoc,2621,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sum0r",This instruction must always be implemented such that its execution latency does not depend on the data being operated on.,non_CSR_parameter,enum,very_high,False, +chunk_1507bd07,src/scalar-crypto.adoc,2629,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sum0r",[NOTE] .Note to software developers The entire Sum0 transform for SHA2-512 may be computed on RV32 using the following instruction sequence:,SW_rule,enum,medium,False, +chunk_b755681f,src/scalar-crypto.adoc,2697,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sum1r","The transform is a 64-bit to 64-bit function, so the input and output is represented by two 32-bit registers.",non_CSR_parameter,range,medium,False, +chunk_211b5593,src/scalar-crypto.adoc,2697,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sum1r",This instruction must always be implemented such that its execution latency does not depend on the data being operated on.,non_CSR_parameter,enum,very_high,False, +chunk_23f24493,src/scalar-crypto.adoc,2705,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sum1r",[NOTE] .Note to software developers The entire Sum1 transform for SHA2-512 may be computed on RV32 using the following instruction sequence:,SW_rule,enum,medium,False, +chunk_f92dace2,src/scalar-crypto.adoc,2773,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig0",This instruction must always be implemented such that its execution latency does not depend on the data being operated on.,non_CSR_parameter,enum,very_high,False, +chunk_c5115b0d,src/scalar-crypto.adoc,2835,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig1",This instruction must always be implemented such that its execution latency does not depend on the data being operated on.,non_CSR_parameter,enum,very_high,False, +chunk_2c264432,src/scalar-crypto.adoc,2897,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sum0",This instruction must always be implemented such that its execution latency does not depend on the data being operated on.,non_CSR_parameter,enum,very_high,False, +chunk_8b569b24,src/scalar-crypto.adoc,2959,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sum1",This instruction must always be implemented such that its execution latency does not depend on the data being operated on.,non_CSR_parameter,enum,very_high,False, +chunk_35100e6d,src/scalar-crypto.adoc,3021,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sm3p0",This instruction must always be implemented such that its execution latency does not depend on the data being operated on.,non_CSR_parameter,enum,very_high,False, +chunk_82228d2d,src/scalar-crypto.adoc,3082,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sm3p1",This instruction must always be implemented such that its execution latency does not depend on the data being operated on.,non_CSR_parameter,enum,very_high,False, +chunk_6f672564,src/scalar-crypto.adoc,3143,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sm4ed","On RV64, the 32-bit result is sign extended to XLEN bits.",non_CSR_parameter,range,high,False, +chunk_0d17d254,src/scalar-crypto.adoc,3143,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sm4ed",This instruction must always be implemented such that its execution latency does not depend on the data being operated on.,non_CSR_parameter,enum,very_high,False, +chunk_4bad67d6,src/scalar-crypto.adoc,3214,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sm4ks","On RV64, the 32-bit result is sign extended to XLEN bits.",non_CSR_parameter,range,high,False, +chunk_d3755de8,src/scalar-crypto.adoc,3214,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sm4ks",This instruction must always be implemented such that its execution latency does not depend on the data being operated on.,non_CSR_parameter,enum,very_high,False, +chunk_218c2c93,src/scalar-crypto.adoc,3392,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > xperm8",The rs1 register contains a vector of XLEN/8 8-bit elements.,non_CSR_parameter,range,medium,False, +chunk_84db91b7,src/scalar-crypto.adoc,3392,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > xperm8",The rs2 register contains a vector of XLEN/8 8-bit indexes.,non_CSR_parameter,range,medium,False, +chunk_f66271b1,src/scalar-crypto.adoc,3454,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > xperm4",The rs1 register contains a vector of XLEN/4 4-bit elements.,non_CSR_parameter,range,medium,False, +chunk_d8a64be2,src/scalar-crypto.adoc,3454,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > xperm4",The rs2 register contains a vector of XLEN/4 4-bit indexes.,non_CSR_parameter,range,medium,False, +chunk_71134e7d,src/scalar-crypto.adoc,3558,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source",The `seed` CSR provides an interface to a NIST SP 800-90B cite:[TuBaKe:18] or BSI AIS-31 cite:[KiSc11] compliant physical Entropy Source (ES).,CSR_controlled,enum,high,False, +chunk_2b864b44,src/scalar-crypto.adoc,3576,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR",`seed` is an unprivileged CSR located at address `0x015`.,CSR_controlled,enum,high,False, +chunk_255cd5cc,src/scalar-crypto.adoc,3576,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR",The 32-bit contents of `seed` are as follows:,non_CSR_parameter,range,high,False, +chunk_0d0b4d16,src/scalar-crypto.adoc,3583,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR","|`31:30` |`OPST` |Status: `BIST` (00), `WAIT` (01), `ES16` (10), `DEAD` (11).",unknown,unknown,high,False, +chunk_04eb520f,src/scalar-crypto.adoc,3586,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR",|`29:24` |reserved |For future use by the RISC-V specification.,unknown,unknown,high,False, +chunk_1f09fd42,src/scalar-crypto.adoc,3588,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR",|`23:16` |custom |Designated for custom and experimental use.,unknown,unknown,high,False, +chunk_381c5b55,src/scalar-crypto.adoc,3590,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR","|`15: 0` |`entropy` |16 bits of randomness, only when `OPST=ES16`. |",non_CSR_parameter,range,high,False, +chunk_58410c01,src/scalar-crypto.adoc,3593,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR",Attempts to access the `seed` CSR using a read-only CSR-access instruction (`CSRRS`/`CSRRC` with rs1=`x0` or `CSRRSI`/`CSRRCI` with uimm=0) raise an illegal-instruction exception; any other CSR-access instruction may be used to access `seed`.,CSR_controlled,enum,high,False, +chunk_a9cc350a,src/scalar-crypto.adoc,3593,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR",The write value (in `rs1` or `uimm`) must be ignored by implementations.,non_CSR_parameter,enum,very_high,False, +chunk_ddceffaf,src/scalar-crypto.adoc,3593,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR",The purpose of the write is to signal polling and flushing.,unknown,unknown,high,False, +chunk_d7c8c3d1,src/scalar-crypto.adoc,3600,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR","Software normally uses the instruction `csrrw rd, seed, x0` to read the `seed` CSR.",CSR_controlled,enum,high,False, +chunk_aa84b942,src/scalar-crypto.adoc,3615,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR","The `seed` CSR is also access controlled by execution mode, and attempted read or write access will raise an illegal-instruction exception outside M mode unless access is explicitly granted.",CSR_controlled,enum,high,False, +chunk_46defd3e,src/scalar-crypto.adoc,3620,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR","The status bits `seed[31:30]` = `OPST` may be `ES16` (10), indicating successful polling, or one of three entropy polling failure statuses `BIST` (00), `WAIT` (01), or `DEAD` (11), discussed below.",non_CSR_parameter,enum,high,False, +chunk_518a5702,src/scalar-crypto.adoc,3624,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR","Each returned `seed[15:0]` = `entropy` value represents unique randomness when `OPST`=`ES16` (`seed[31:30]` = `10`), even if its numerical value is the same as that of a previously polled `entropy` value.",unknown,unknown,high,False, +chunk_cf0d0c43,src/scalar-crypto.adoc,3624,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR",The implementation requirements of `entropy` bits are defined in .,unknown,unknown,high,False, +chunk_80484094,src/scalar-crypto.adoc,3624,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR","When `OPST` is not `ES16`, `entropy` must be set to 0.",non_CSR_parameter,binary,very_high,False, +chunk_1c68bfee,src/scalar-crypto.adoc,3624,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR",An implementation may safely set reserved and custom bits to zeros.,non_CSR_parameter,enum,high,False, +chunk_0276a697,src/scalar-crypto.adoc,3631,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR","For security reasons, the interface guarantees that secret `entropy` words are not made available multiple times.",unknown,unknown,high,False, +chunk_8c53a16b,src/scalar-crypto.adoc,3631,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR",Hence polling (reading) must also have the side effect of clearing (wipe-on-read) the `entropy` contents and changing the state to `WAIT` (unless there is `entropy` immediately available for `ES16`).,non_CSR_parameter,binary,very_high,False, +chunk_0d904830,src/scalar-crypto.adoc,3631,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR","Other states (`BIST`, `WAIT`, and `DEAD`) may be unaffected by polling.",non_CSR_parameter,enum,high,False, +chunk_07f285f6,src/scalar-crypto.adoc,3640,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR","`00` - `BIST` indicates that Built-In Self-Test ""on-demand"" (BIST) testing is being performed.",unknown,unknown,high,False, +chunk_570967d3,src/scalar-crypto.adoc,3640,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR","If `OPST` returns temporarily to `BIST` from any other state, this signals a non-fatal self-test alarm, which is non-actionable, apart from being logged.",unknown,unknown,high,False, +chunk_ee9f77b9,src/scalar-crypto.adoc,3640,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR",Such a `BIST` alarm must be latched until polled at least once to enable software to record its occurrence.,SW_rule,range,very_high,False, +chunk_48b386c6,src/scalar-crypto.adoc,3648,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR",`01` - `WAIT` means that a sufficient amount of entropy is not yet available.,unknown,unknown,high,False, +chunk_dd30c8e8,src/scalar-crypto.adoc,3648,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR",This is not an error condition and may (in fact) be more frequent than ES16 since physical entropy sources often have low bandwidth.,non_CSR_parameter,enum,high,False, +chunk_b9b15a68,src/scalar-crypto.adoc,3658,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR",`11` - `DEAD` is an unrecoverable self-test error.,unknown,unknown,high,False, +chunk_bbe877cf,src/scalar-crypto.adoc,3658,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR","This may indicate a hardware fault, a security issue, or (extremely rarely) a type-1 statistical false positive in the continuous testing procedures.",non_CSR_parameter,enum,high,False, +chunk_5da81d74,src/scalar-crypto.adoc,3658,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR","In case of a fatal failure, an immediate lockdown may also be an appropriate response in dedicated security devices.",non_CSR_parameter,enum,high,False, +chunk_e4b6b488,src/scalar-crypto.adoc,3682,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements","The main requirement is that 2-to-1 cryptographic post-processing in 256-bit input blocks will yield 128-bit ""full entropy"" output blocks.",non_CSR_parameter,range,medium,False, +chunk_77f3c373,src/scalar-crypto.adoc,3682,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements",Entropy source users may make this conservative assumption but are not prohibited from using more than twice the number of seed bits relative to the desired resulting entropy.,non_CSR_parameter,enum,high,False, +chunk_e19bb927,src/scalar-crypto.adoc,3691,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements",An implementation of the entropy source should meet at least one of the following requirements sets in order to be considered a secure and safe design:,non_CSR_parameter,range,medium,False, +chunk_31436a65,src/scalar-crypto.adoc,3699,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements",The source must also meet the NIST 800-90B min-entropy rate 192/256 = 0.75.,non_CSR_parameter,enum,very_high,False, +chunk_e100a35e,src/scalar-crypto.adoc,3704,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements",It must have at least a 256-bit (Post-Quantum Category 5) internal security level.,non_CSR_parameter,range,very_high,False, +chunk_9b8e2426,src/scalar-crypto.adoc,3708,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements","All implementations must signal initialization, test mode, and health alarms as required by respective standards.",non_CSR_parameter,enum,very_high,False, +chunk_6e36a6a2,src/scalar-crypto.adoc,3708,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements","This may require the implementer to add non-standard (custom) test interfaces in a secure and safe manner, an example of which is described in",non_CSR_parameter,enum,medium,False, +chunk_d3cf7c26,src/scalar-crypto.adoc,3717,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements > NIST SP 800-90B / FIPS 140-3 Requirements",All NIST SP 800-90B cite:[TuBaKe:18] required components and health test mechanisms must be implemented.,non_CSR_parameter,enum,very_high,False, +chunk_cd11cdb1,src/scalar-crypto.adoc,3727,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements > NIST SP 800-90B / FIPS 140-3 Requirements","Instead, the implication is that every 256-bit sequence should have min-entropy of at least 128+64 = 192 bits, as discussed in SP 800-90C cite:[BaKeMc:25]; the likelihood of successfully ""guessing"" an individual 256-bit output sequence should not be higher than 2^-192^ even with (almost) unconstrained amount of entropy source data and computational power.",non_CSR_parameter,range,high,False, +chunk_52c7ef06,src/scalar-crypto.adoc,3735,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements > NIST SP 800-90B / FIPS 140-3 Requirements","Rather than attempting to define all the mathematical and architectural properties that the entropy source must satisfy, we define that the physical entropy source be strong and robust enough to pass the equivalent of NIST SP 800-90 evaluation and certification for full entropy when conditioned cryptographically in ratio 2:1 with 128-bit output blocks.",non_CSR_parameter,range,very_high,False, +chunk_b931694f,src/scalar-crypto.adoc,3741,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements > NIST SP 800-90B / FIPS 140-3 Requirements","Even though the requirement is defined in terms of 128-bit full entropy blocks, we recommend 256-bit security.",non_CSR_parameter,range,medium,False, +chunk_aed9c8c6,src/scalar-crypto.adoc,3741,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements > NIST SP 800-90B / FIPS 140-3 Requirements",This can be accomplished by using at least 512 `entropy` bits to initialize a DRBG that has 256-bit security.,non_CSR_parameter,range,medium,False, +chunk_83e6df61,src/scalar-crypto.adoc,3748,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements > BSI AIS-31 PTG.2 / Common Criteria Requirements","For alternative Common Criteria certification (or self-certification), AIS 31 PTG.2 class cite:[KiSc11] (Sect. 4.3.) required hardware components and mechanisms must be implemented.",non_CSR_parameter,enum,very_high,False, +chunk_564cc192,src/scalar-crypto.adoc,3748,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements > BSI AIS-31 PTG.2 / Common Criteria Requirements",These two metrics should not be equated or confused with each other.,non_CSR_parameter,enum,medium,False, +chunk_d75b4f88,src/scalar-crypto.adoc,3761,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements > Virtual Sources: Security Requirement",It is defined for the benefit of the RISC-V security ecosystem so that virtual systems may have a consistent level of security.,non_CSR_parameter,enum,medium,False, +chunk_3586d4be,src/scalar-crypto.adoc,3765,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements > Virtual Sources: Security Requirement","Despite limited trust, implementers should try to guarantee that even such environments have sufficient entropy available for secure cryptographic operations.",non_CSR_parameter,enum,medium,False, +chunk_6a31d449,src/scalar-crypto.adoc,3772,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements > Virtual Sources: Security Requirement","A virtual source traps access to the `seed` CSR, emulates it, or otherwise implements it, possibly without direct access to a physical entropy source.",CSR_controlled,enum,high,False, +chunk_16a0bf00,src/scalar-crypto.adoc,3772,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements > Virtual Sources: Security Requirement","The output can be cryptographically secure pseudorandomness instead of real entropy, but must have at least 256-bit security, as defined below. A virtual source is intended especially for guest operating systems, sandboxes, emulators, and similar use cases.",SW_rule,range,very_high,False, +chunk_c18d934f,src/scalar-crypto.adoc,3787,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements > Virtual Sources: Security Requirement",Any implementation of the `seed` CSR that limits the security strength shall not reduce it to less than 256 bits.,CSR_controlled,range,very_high,False, +chunk_61b3ff74,src/scalar-crypto.adoc,3787,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements > Virtual Sources: Security Requirement","If the security level is under 256 bits, then the interface must not be available.",non_CSR_parameter,range,very_high,False, +chunk_bf037a77,src/scalar-crypto.adoc,3791,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements > Virtual Sources: Security Requirement",It should fail (`DEAD`) if the host DRBG or entropy source fails and there is insufficient seeding material for the host DRBG.,non_CSR_parameter,enum,high,False, +chunk_974c56f2,src/scalar-crypto.adoc,3799,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Access Control to `seed`","The Zkr extension adds the `SSEED` and `USEED` fields to the `mseccfg` CSR to control access to the `seed` CSR from U, S, or HS modes (see Privileged ISA specification).",CSR_controlled,enum,high,False, +chunk_a36b6293,src/scalar-crypto.adoc,3803,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Access Control to `seed`",Systems should implement carefully considered access control policies from lower privilege modes to physical entropy sources.,non_CSR_parameter,enum,medium,False, +chunk_9eec2530,src/scalar-crypto.adoc,3803,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Access Control to `seed`",The system can trap attempted access to `seed` and feed a less privileged client virtual entropy source data () instead of invoking an SP 800-90B () or PTG.2 () physical entropy source.,unknown,unknown,high,False, +chunk_80d4b3d5,src/scalar-crypto.adoc,3813,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Access Control to `seed`","Implementations may implement `mseccfg` such that `[s,u]seed` is a read-only constant value `0`.",non_CSR_parameter,enum,high,False, +chunk_60a541a2,src/scalar-crypto.adoc,3813,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Access Control to `seed`","Software may discover if access to the `seed` CSR can be enabled in U and S mode by writing a `1` to `[s,u]seed` and reading back the result.",CSR_controlled,binary,high,False, +chunk_ee488e55,src/scalar-crypto.adoc,3822,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt","This property is commonly called ""constant-time"" although should not be taken with that literal meaning.",non_CSR_parameter,enum,medium,False, +chunk_0fa5bd64,src/scalar-crypto.adoc,3841,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt > Scope and Goal",Zkt does not define a set of instructions available in the core; it just restricts the behaviour of certain instructions if those are implemented.,unknown,unknown,high,False, +chunk_13f08413,src/scalar-crypto.adoc,3858,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt > Scope and Goal","The stated goal is that OpenSSL, BoringSSL (Android), the Linux Kernel, and similar trusted software will not have directly observable timing side channels when compiled and running on a Zkt-enabled RISC-V target.",SW_rule,binary,high,False, +chunk_64e66675,src/scalar-crypto.adoc,3864,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt > Scope and Goal","Vendors do not have to implement all of the list's instructions to be Zkt compliant; however, if they claim to have Zkt and implement any of the listed instructions, it must have data-independent latency.",non_CSR_parameter,binary,very_high,False, +chunk_32e5bed5,src/scalar-crypto.adoc,3875,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt > Scope and Goal",The guiding principle should be that no information about the data being operated on should be leaked based on the execution latency.,non_CSR_parameter,enum,medium,False, +chunk_de86ad76,src/scalar-crypto.adoc,3897,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt > Background","Timing attacks are much more powerful than was realised before the 2010s, which has led to a significant mitigation effort in current cryptographic code-bases. * Cryptography developers use static and dynamic security testing tools to trace the handling of secret information and detect occasions where it influences a branch or is used for a table lookup. * Architectural testing for Zkt can be pragmatic and semi-formal; security by design against basic timing attacks can usually be achieved via conscious implementation (of relevant iterative multi-cycle instructions or instructions composed of micro-ops) in way that avoids data-dependent latency. * Laboratory testing may utilize statistical timing attack leakage analysis techniques such as those described in ISO/IEC 17825 cite:[IS16]. * Binary executables should not contain secrets in the instruction encodings (Kerckhoffs's principle), so instruction timing may leak information about immediates, ordering of input registers, etc.",non_CSR_parameter,enum,medium,False, +chunk_76e8a993,src/scalar-crypto.adoc,3897,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt > Background",There may be an exception to this in systems where a binary loader modifies the executable for purposes of relocation -- and it is desirable to keep the execution location (PC) secret.,non_CSR_parameter,enum,high,False, +chunk_6282c8e8,src/scalar-crypto.adoc,3897,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt > Background","If a secret ends up in address calculation affecting a load or store, that is a violation.",unknown,unknown,high,False, +chunk_97125d05,src/scalar-crypto.adoc,3897,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt > Background","If a secret affects a branch's condition, that is also a violation. A secret variable location or register becomes a non-secret via specific zeroization/sanitisation or by being declared ciphertext (or otherwise no-longer-secret information).",unknown,unknown,high,False, +chunk_d814d69a,src/scalar-crypto.adoc,3967,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt > Zkt listings","Rather, every one of these instructions that the core does implement must adhere to the requirements of `Zkt`.",non_CSR_parameter,enum,very_high,False, +chunk_02d01f83,src/scalar-crypto.adoc,4097,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt > Zkt listings > RVK (Scalar Cryptography)","Additionally, `seed` CSR latency should be independent of `ES16` state output `entropy` bits, as that is a sensitive security parameter.",CSR_controlled,enum,high,False, +chunk_37b2c135,src/scalar-crypto.adoc,4184,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instruction Rationale > AES Instructions",The 32-bit instructions were derived from work in cite:[MJS:LWAES:20] and contributed to the RISC-V cryptography extension.,non_CSR_parameter,range,medium,False, +chunk_ab2da50e,src/scalar-crypto.adoc,4184,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instruction Rationale > AES Instructions",The 64-bit instructions were developed collaboratively by task group members on our mailing list.,non_CSR_parameter,range,medium,False, +chunk_e07e3e32,src/scalar-crypto.adoc,4256,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instruction Rationale > Bitmanip Instructions for Cryptography > Rotations","Algorithms making use of 32-bit rotations: SHA256, AES (Shift Rows), ChaCha20, SM3. * Algorithms making use of 64-bit rotations: SHA512, SHA3.",non_CSR_parameter,range,medium,False, +chunk_7c2c6b17,src/scalar-crypto.adoc,4380,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instruction Rationale > Bitmanip Instructions for Cryptography > Crossbar Permutation Instructions",The `xperm4` instruction operates on nibbles. `GPR[rs1]` contains a vector of `XLEN/4` 4-bit elements. `GPR[rs2]` contains a vector of `XLEN/4` 4-bit indexes.,non_CSR_parameter,range,medium,False, +chunk_e7c90dc8,src/scalar-crypto.adoc,4386,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instruction Rationale > Bitmanip Instructions for Cryptography > Crossbar Permutation Instructions",The `xperm8` instruction operates on bytes. `GPR[rs1]` contains a vector of `XLEN/8` 8-bit elements. `GPR[rs2]` contains a vector of `XLEN/8` 8-bit indexes.,non_CSR_parameter,range,medium,False, +chunk_5d139d38,src/scalar-crypto.adoc,4401,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instruction Rationale > Bitmanip Instructions for Cryptography > Crossbar Permutation Instructions","Lightweight block ciphers using 4-bit SBoxes include: PRESENT cite:[block:present], Rectangle cite:[block:rectangle], GIFT cite:[block:gift], Twine cite:[block:twine], Skinny, MANTIS cite:[block:skinny], Midori cite:[block:midori].",non_CSR_parameter,range,medium,False, +chunk_4b3cb13e,src/scalar-crypto.adoc,4409,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instruction Rationale > Bitmanip Instructions for Cryptography > Crossbar Permutation Instructions","National ciphers using 8-bit SBoxes include: Camellia cite:[block:camellia] (Japan), Aria cite:[block:aria] (Korea), AES cite:[nist:fips:197] (USA, Belgium), SM4 cite:[gbt:sm4] (China) Kuznyechik (Russia).",non_CSR_parameter,range,medium,False, +chunk_7de735cf,src/scalar-crypto.adoc,4427,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations",Hence we also discuss non-ISA system features that may be needed for cryptographic standards compliance and security testing.,non_CSR_parameter,enum,medium,False, +chunk_9d9af863,src/scalar-crypto.adoc,4444,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Checklists for Design and Self-Certification","The scope of RISC-V ISA architectural tests are those behaviors that are independent of the physical entropy source details. A smoke test ES module may be helpful in design phase. * *Technical justification for entropy.* This may take the form of a stochastic model or a heuristic argument that explains why the noise source output is from a random, rather than pseudorandom (deterministic) process, and is not easily predictable or externally observable. A complete physical model is not necessary; research literature can be cited.",non_CSR_parameter,enum,medium,False, +chunk_f378e173,src/scalar-crypto.adoc,4444,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Checklists for Design and Self-Certification","For example, one can show that a good ring oscillator noise derives an amount of physical entropy from local, spontaneously occurring Johnson-Nyquist thermal noise cite:[Sa21], and is therefore not merely ""random-looking"". * *Entropy Source Design Review.* An entropy source is more than a noise source, and must have features such as health tests (), a conditioner (), and a security boundary with clearly defined interfaces.",non_CSR_parameter,enum,very_high,False, +chunk_dbadf7a4,src/scalar-crypto.adoc,4444,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Checklists for Design and Self-Certification","One may tabulate the SHALL statements of SP 800-90B cite:[TuBaKe:18], FIPS 140-3 Implementation Guidance cite:[NICC21], AIS-31 cite:[KiSc11] or other standards being used.",non_CSR_parameter,enum,very_high,False, +chunk_d9996046,src/scalar-crypto.adoc,4444,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Checklists for Design and Self-Certification","Official and non-official checklist tables are available: https://github.com/usnistgov/90B-Shall-Statements * *Experimental Tests.* The raw noise source is subjected to entropy estimation as defined in NIST 800-90B, Section 3 cite:[TuBaKe:18].",non_CSR_parameter,enum,very_high,False, +chunk_5e778158,src/scalar-crypto.adoc,4444,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Checklists for Design and Self-Certification","For SP 800-90B, NIST has made a min-entropy estimation package freely available: https://github.com/usnistgov/SP800-90BEntropyAssessment * **Resilience.** Above physical engineering steps should consider the operational environment of the device, which may be unexpected or hostile (actively attempting to exploit vulnerabilities in the design).",SW_rule,enum,medium,False, +chunk_e30406a5,src/scalar-crypto.adoc,4487,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Checklists for Design and Self-Certification","Compared to older (FIPS 140-2) RNG and DRBG modules, an entropy source module may have a relatively small area (just a few thousand NAND2 gate equivalent). CMVP is introducing an ""Entropy Source Validation Scope"" which potentially allows 90B validations to be reused for different (FIPS 140-3) modules.",non_CSR_parameter,enum,medium,False, +chunk_b7fc22f7,src/scalar-crypto.adoc,4506,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Standards and Terminology","These standards set many of the technical requirements for the RISC-V entropy source design, and we use their terminology if possible.",unknown,unknown,high,False, +chunk_a3384916,src/scalar-crypto.adoc,4509,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Standards and Terminology","image::esdataflow.svg[align=""center"",scaledwidth=50%] The `seed` CSR provides an Entropy Source (ES) interface, not a stateful random number generator.",CSR_controlled,enum,high,False, +chunk_e9af56e2,src/scalar-crypto.adoc,4523,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Standards and Terminology > Entropy Source (ES)","Since these are directly based on natural phenomena and are subject to environmental conditions (which may be adversarial), they require features that monitor the ""health"" and quality of those sources.",non_CSR_parameter,enum,medium,False, +chunk_d11701bf,src/scalar-crypto.adoc,4549,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Standards and Terminology > Conditioning: Cryptographic and Non-Cryptographic","Non-cryptographic conditioners and extractors such as von Neumann's ""debiased coin tossing"" cite:[Ne51] are easier to implement efficiently but may reduce entropy content (in individual bits removed) more than cryptographic hashes, which mix the input entropy very efficiently.",CSR_controlled,enum,high,False, +chunk_a8630b22,src/scalar-crypto.adoc,4566,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Standards and Terminology > Pseudorandom Number Generator (PRNG)","Non-cryptographic PRNGs, such as LFSRs and the linear-congruential generators found in many programming libraries, may generate statistically satisfactory random numbers but must never be used for cryptographic keying.",non_CSR_parameter,enum,very_high,False, +chunk_89978e21,src/scalar-crypto.adoc,4578,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Standards and Terminology > Deterministic Random Bit Generator (DRBG)",The DRBG should still be frequently refreshed (reseeded) for forward and backward security.,non_CSR_parameter,enum,medium,False, +chunk_afb4ff93,src/scalar-crypto.adoc,4600,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > The `seed` CSR","An entropy source does not require a high-bandwidth interface; a single DRBG source initialization only requires 512 bits (256 bits of entropy), and DRBG output can be shared by any number of callers.",non_CSR_parameter,range,high,False, +chunk_0aea1c13,src/scalar-crypto.adoc,4600,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > The `seed` CSR","Once initiated, a DRBG requires new entropy only to mitigate the risk of state compromise.",non_CSR_parameter,unknown,high,False, +chunk_bc5205da,src/scalar-crypto.adoc,4606,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > The `seed` CSR","From a security perspective, it is essential that the side effect of flushing the secret entropy bits occurs upon reading.",unknown,unknown,high,False, +chunk_fc8f92ca,src/scalar-crypto.adoc,4606,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > The `seed` CSR",Hence we mandate a write operation on this particular CSR.,CSR_controlled,enum,high,False, +chunk_0c6bdf30,src/scalar-crypto.adoc,4610,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > The `seed` CSR","A blocking instruction may have been easier to use, but most users should be querying a (D)RBG instead of an entropy source.",CSR_controlled,enum,high,False, +chunk_0c584d48,src/scalar-crypto.adoc,4610,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > The `seed` CSR","Without a polling-style mechanism, the entropy source could hang for thousands of cycles under some circumstances. A `wfi` or `pause` mechanism (at least potentially) allows energy-saving sleep on MCUs and context switching on higher-end CPUs.",unknown,range,high,False, +chunk_b1f58541,src/scalar-crypto.adoc,4617,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > The `seed` CSR",The reason for the particular `OPST = seed[31:0]` two-bit mechanism is to provide redundancy.,unknown,unknown,high,False, +chunk_819b73e0,src/scalar-crypto.adoc,4617,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > The `seed` CSR","The ""fault"" bit combinations `11` (`DEAD`) and `00` (`BIST`) are more likely for electrical reasons if feature discovery fails and the entropy source is actually not available.",unknown,unknown,high,False, +chunk_917fae76,src/scalar-crypto.adoc,4622,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > The `seed` CSR","The 16-bit bandwidth was a compromise motivated by the desire to provide redundancy in the return value, some protection against potential Power/EM leakage (further alleviated by the 2:1 cryptographic conditioning discussed in ), and the desire to have all of the bits ""in the same place"" on both RV32 and RV64 architectures for programming convenience.",non_CSR_parameter,range,high,False, +chunk_6d42042e,src/scalar-crypto.adoc,4633,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > NIST SP 800-90B","Hence NIST SP 800-90B cite:[TuBaKe:18] min-entropy assessment must guarantee at least 128 + 64 = 192 bits input entropy per 256-bit block (cite:[BaKeMc:25], Sections 4.1. and 4.3.2).",non_CSR_parameter,range,very_high,False, +chunk_fadc1b89,src/scalar-crypto.adoc,4633,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > NIST SP 800-90B",Only then a hashing of 16 * 16 = 256 bits from the entropy source will produce the desired 128 bits of full entropy.,non_CSR_parameter,range,medium,False, +chunk_3f4742f2,src/scalar-crypto.adoc,4656,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > NIST SP 800-90B","If NIST SP 800-90B certification is chosen, the entropy source should implement at least the health tests defined in Section 4.4 of cite:[TuBaKe:18]: the repetition count test and adaptive proportion test, or show that the same flaws will be detected by vendor-defined tests.",non_CSR_parameter,range,high,False, +chunk_df4fd91e,src/scalar-crypto.adoc,4671,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > BSI AIS-31","For validation purposes, the PTG.2 requirements may be mapped to security controls T1-3 () and the interface as follows:",non_CSR_parameter,enum,medium,False, +chunk_d4faae6d,src/scalar-crypto.adoc,4675,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > BSI AIS-31","P1 *[PTG.2.1]* Start-up tests map to T1 and reset-triggered (on-demand) `BIST` tests. * P2 *[PTG.2.2]* Continuous testing total failure maps to T2 and the `DEAD` state. * P3 *[PTG.2.3]* Online tests are continuous tests of T2 – entropy output is prevented in the `BIST` state. * P4 *[PTG.2.4]* Is related to the design of effective entropy source health tests, which we encourage. * P5 *[PTG.2.5]* Raw random sequence may be checked via the GetNoise interface (). * P6 *[PTG.2.6]* Test Procedure A cite:[KiSc11] (Sect 2.4.4.1) is a part of the evaluation process, and we suggest self-evaluation using these tests even if AIS-31 certification is not sought. * P7 *[PTG.2.7]* Average Shannon entropy of ""internal random bits"" exceeds 0.997.",non_CSR_parameter,enum,high,False, +chunk_543b1060,src/scalar-crypto.adoc,4706,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > Virtual Sources",The entropy source must be able to support current and future security standards and applications.,non_CSR_parameter,enum,very_high,False, +chunk_d087e925,src/scalar-crypto.adoc,4706,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > Virtual Sources","The 256-bit requirement maps to ""Category 5"" of NIST Post-Quantum Cryptography (4.A.5 ""Security Strength Categories"" in cite:[NI16]) and TOP SECRET schemes in Suite B and the newer U.S.",non_CSR_parameter,range,medium,False, +chunk_9aa89725,src/scalar-crypto.adoc,4719,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > Security Considerations for Direct Hardware Access",The ISA implementation and system design must try to ensure that the hardware-software interface minimizes avenues for adversarial information flow even if not explicitly forbidden in the specification.,SW_rule,binary,very_high,False, +chunk_7b59297f,src/scalar-crypto.adoc,4723,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > Security Considerations for Direct Hardware Access",It is recommended if a single physical entropy source is shared between multiple different virtual machines or if the guest OS is untrusted. A virtual entropy source is significantly more resistant to depletion attacks and also lessens the risk from covert channels.,unknown,unknown,high,False, +chunk_c8ba5855,src/scalar-crypto.adoc,4729,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > Security Considerations for Direct Hardware Access","The direct `mseccfg.[s,u]seed` option allows one to draw a security boundary around a component in relation to Sensitive Security Parameter (SSP) flows, even if that component is not in M mode.",unknown,unknown,high,False, +chunk_c25c8bcb,src/scalar-crypto.adoc,4729,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > Security Considerations for Direct Hardware Access",This is helpful when implementing trusted enclaves.,unknown,unknown,high,False, +chunk_81486d45,src/scalar-crypto.adoc,4763,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > Security Considerations for Direct Hardware Access",All information flows and interaction mechanisms must be considered from an adversarial viewpoint: the fewer the better.,non_CSR_parameter,enum,very_high,False, +chunk_b495a948,src/scalar-crypto.adoc,4769,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > Security Considerations for Direct Hardware Access","If it does, additional countermeasures are necessary.",unknown,unknown,high,False, +chunk_2066a0c8,src/scalar-crypto.adoc,4781,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests","In almost all cases, a hardware entropy source must implement appropriate security controls to guarantee unpredictability, prevent leakage, detect attacks, and deny adversarial control over the entropy output or ts generation mechanism.",SW_rule,enum,very_high,False, +chunk_379d8339,src/scalar-crypto.adoc,4797,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests",Hence the default action in case of a failure should be aimed at damage control: Limiting further output and preventing weak crypto keys from being generated.,non_CSR_parameter,enum,high,False, +chunk_e7a1e83e,src/scalar-crypto.adoc,4808,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests > T1: On-demand testing","The implementation will simply return `BIST` during the initial start-up self-test period; in any case, the driver must wait for them to finish before starting cryptographic operations.",non_CSR_parameter,enum,very_high,False, +chunk_67999daa,src/scalar-crypto.adoc,4824,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests > T2: Continuous checks","If an error is detected in continuous tests or environmental sensors, the entropy source will enter a no-output state.",unknown,unknown,high,False, +chunk_33d6149d,src/scalar-crypto.adoc,4824,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests > T2: Continuous checks",We define that a non-critical alarm is signaled if the entropy source returns to `BIST` state from live (`WAIT` or `ES16`) states.,unknown,unknown,high,False, +chunk_27503b07,src/scalar-crypto.adoc,4824,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests > T2: Continuous checks","Critical failures will result in `DEAD` state immediately. A hardware-based continuous testing mechanism must not make statistical information externally available, and it must be zeroized periodically or upon demand via reset, power-up, or similar signal.",non_CSR_parameter,enum,very_high,False, +chunk_474b7d61,src/scalar-crypto.adoc,4833,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests > T2: Continuous checks",The design should avoid guiding such active attacks by revealing detailed status information.,non_CSR_parameter,enum,medium,False, +chunk_8d37cdad,src/scalar-crypto.adoc,4833,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests > T2: Continuous checks","Upon detection of an attack, the default action should be aimed at damage control -- to prevent weak crypto keys from being generated.",non_CSR_parameter,enum,high,False, +chunk_eb9afb91,src/scalar-crypto.adoc,4840,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests > T2: Continuous checks","There may also be requirements for signaling of non-fatal alarms; AIS 31 specifies ""noise alarms"" that can go off with non-negligible probability even if the device is functioning correctly; these can be signaled with `BIST`.",SW_rule,enum,high,False, +chunk_cefa4f3e,src/scalar-crypto.adoc,4840,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests > T2: Continuous checks","There rarely is anything that can or should be done about a non-fatal alarm condition in an operator-free, autonomous system.",non_CSR_parameter,enum,medium,False, +chunk_1948121a,src/scalar-crypto.adoc,4854,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests > T3: Fatal error states","Since the security of most cryptographic operations depends on the entropy source, a system-wide ""default deny"" security policy approach is appropriate for most entropy source failures. A hardware test failure should at least result in the `DEAD` state and possibly reset/halt.",non_CSR_parameter,range,high,False, +chunk_9fd34c6f,src/scalar-crypto.adoc,4854,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests > T3: Fatal error states",It’s a show stopper: The entropy source (or its cryptographic client application) must not be allowed to run if its secure operation can’t be guaranteed.,non_CSR_parameter,binary,very_high,False, +chunk_5135b5ea,src/scalar-crypto.adoc,4866,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests > T3: Fatal error states","However, even such ""innocent"" failure modes may indicate a fault attack cite:[KaScVe13] and therefore should be addressed as a system integrity failure rather than as a diagnostic issue.",non_CSR_parameter,enum,high,False, +chunk_4b36f457,src/scalar-crypto.adoc,4872,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests > T3: Fatal error states","Security architects will understand to use permanent or hard-to-recover ""security-fuse"" lockdowns only if the threshold of a test is such that the probability of false-positive is negligible over the entire device lifetime.",SW_rule,unknown,high,False, +chunk_eccca728,src/scalar-crypto.adoc,4885,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests > Information Flows","For the same reasons, only complete and fully processed random words shall be made available via `entropy` (ES16 status of `seed`).",non_CSR_parameter,enum,very_high,False, +chunk_d5ba3935,src/scalar-crypto.adoc,4892,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests > Information Flows",Importantly the test interface and the main interface should not be operational at the same time.,non_CSR_parameter,enum,medium,False, +chunk_709927df,src/scalar-crypto.adoc,4897,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests > Information Flows","[quote, NIST SP 800-90B, Noise Source Requirements] The noise source state shall be protected from adversarial knowledge or influence to the greatest extent possible.",non_CSR_parameter,enum,very_high,False, +chunk_4a3dd97e,src/scalar-crypto.adoc,4897,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests > Information Flows","The methods used for this shall be documented, including a description of the (conceptual) security boundary's role in protecting the noise source from adversarial observation or influence.",non_CSR_parameter,enum,very_high,False, +chunk_82df096a,src/scalar-crypto.adoc,4920,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies","When considering implementation options and trade-offs, one must look at the entire information flow.",non_CSR_parameter,binary,very_high,False, +chunk_b131ce4a,src/scalar-crypto.adoc,4923,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies","This raw data also needs to be protected by the design. . *Continuous health tests* ensure that the noise source and its environment meet their operational parameters. . *Non-cryptographic conditioners* remove much of the bias and correlation in input noise. . *Cryptographic conditioners* produce full entropy output, completely indistinguishable from ideal random. . *DRBG* takes in `>=256` bits of seed entropy as keying material and uses a ""one way"" cryptographic process to rapidly generate bits on demand (without revealing the seed/state).",unknown,unknown,high,False, +chunk_e6b5f0fa,src/scalar-crypto.adoc,4937,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies",Steps 1-4 (possibly 5) are considered to be part of the Entropy Source (ES) and provided by the `seed` CSR.,CSR_controlled,enum,high,False, +chunk_9c194382,src/scalar-crypto.adoc,4948,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Ring Oscillators",The sampled bit sequence may be expected to be relatively uncorrelated (close to IID) if the sample rate is suitably low cite:[KiSc11].,non_CSR_parameter,enum,high,False, +chunk_b728bc1b,src/scalar-crypto.adoc,4973,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Ring Oscillators","Their output is sometimes highly dependent on temperature, which must be taken into account in testing and modeling.",non_CSR_parameter,enum,very_high,False, +chunk_250bceb3,src/scalar-crypto.adoc,4973,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Ring Oscillators","Countermeasures are related to circuit design; environmental sensors, electrical filters, and usage of a differential oscillator may help.",non_CSR_parameter,enum,medium,False, +chunk_e1e67d7c,src/scalar-crypto.adoc,4999,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Other types of noise","It may be possible to certify more exotic noise sources and designs, although their stochastic model needs to be equally well understood, and their CPU interfaces must be secure.",non_CSR_parameter,enum,very_high,False, +chunk_4e9f12e6,src/scalar-crypto.adoc,5008,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Continuous Health Tests",The tests should be designed in a way that a specific number of samples guarantees a state flush (no hung states).,non_CSR_parameter,enum,medium,False, +chunk_71af6c13,src/scalar-crypto.adoc,5015,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Continuous Health Tests","Repetition count is reset every time the output sample value changes; if the count reaches a certain cutoff limit, a noise alarm (`BIST`) or failure (`DEAD`) is signaled.",unknown,unknown,high,False, +chunk_2b1ad5e8,src/scalar-crypto.adoc,5015,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Continuous Health Tests","We see that the structure of the mandatory tests is such that, if well implemented, no information is carried beyond a limit of `W` samples.",unknown,unknown,high,False, +chunk_4c4143f0,src/scalar-crypto.adoc,5033,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Continuous Health Tests","Especially if a non-cryptographic conditioner is used in hardware, it is possible that the AIS 31 cite:[KiSc11] online tests are implemented by driver software.",SW_rule,unknown,high,False, +chunk_7c5d7029,src/scalar-crypto.adoc,5033,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Continuous Health Tests","For some security profiles, AIS 31 mandates that their tolerances are set in a way that the probability of an alarm is at least 10^-6^ yearly under ""normal usage."" Such requirements are problematic in modern applications since their probability is too high for critical systems.",SW_rule,range,medium,False, +chunk_3527cd09,src/scalar-crypto.adoc,5042,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Continuous Health Tests","There rarely is anything that can or should be done about a non-fatal alarm condition in an operator-free, autonomous system.",non_CSR_parameter,enum,medium,False, +chunk_94a3ce45,src/scalar-crypto.adoc,5042,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Continuous Health Tests","However, AIS 31 allows the DRBG component to keep running despite a failure in its Entropy Source, so we suggest re-entering a temporary `BIST` state () to signal a non-fatal statistical error if such (non-actionable) signaling is necessary.",unknown,unknown,high,False, +chunk_110f0933,src/scalar-crypto.adoc,5042,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Continuous Health Tests","Drivers and applications can react to this appropriately (or simply log it), but it will not directly affect the availability of the TRNG. A permanent error condition should result in `DEAD` state.",SW_rule,enum,medium,False, +chunk_08fdad7f,src/scalar-crypto.adoc,5065,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Non-cryptographic Conditioners",One may take a set of bits from a noise source and XOR them together to produce a less biased (and more independent) bit.,non_CSR_parameter,enum,high,False, +chunk_3184ba57,src/scalar-crypto.adoc,5065,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Non-cryptographic Conditioners","However, such an XOR may introduce ""pseudorandomness"" and make the output difficult to analyze. * The von Neumann extractor cite:[Ne51] looks at consecutive pairs of bits, rejects 00 and 11, and outputs 0 or 1 for 01 and 10, respectively.",non_CSR_parameter,enum,high,False, +chunk_788ef845,src/scalar-crypto.adoc,5065,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Non-cryptographic Conditioners","If its assumptions hold, it also removes dependencies, creating an independent and identically distributed (IID) source. * Other linear and non-linear correctors such as those discussed by Dichtl and Lacharme cite:[La08].",unknown,unknown,high,False, +chunk_a46bac67,src/scalar-crypto.adoc,5085,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Non-cryptographic Conditioners","If well designed, they can be evaluated in conjunction with a stochastic model of the noise source itself.",unknown,unknown,high,False, +chunk_a3cdec66,src/scalar-crypto.adoc,5095,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Cryptographic Conditioners",They may also be implemented on the hardware side if necessary.,non_CSR_parameter,enum,high,False, +chunk_4b09bc92,src/scalar-crypto.adoc,5095,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Cryptographic Conditioners","In any case, the `entropy` ES16 output must always be compressed 2:1 (or more) before being used as keying material or considered ""full entropy.""",non_CSR_parameter,enum,very_high,False, +chunk_b32cff0f,src/scalar-crypto.adoc,5110,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Cryptographic Conditioners","On the other hand, simpler non-cryptographic conditioners may be too wasteful on input entropy if high-quality random output is required -- (ARM TrustZone TRBG cite:[AR17] outputs only 10Kbit/sec at 200 MHz.) Hence a resource-saving compromise is made between hardware and software generation.",SW_rule,enum,high,False, +chunk_767c5dd1,src/scalar-crypto.adoc,5123,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > The Final Random: DRBGs",All random bits reaching end users and applications must come from a cryptographic DRBG.,non_CSR_parameter,enum,very_high,False, +chunk_b90d64a0,src/scalar-crypto.adoc,5123,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > The Final Random: DRBGs",The RISC-V AES and SHA instruction set extensions should be used if available since they offer additional security features such as timing attack resistance.,non_CSR_parameter,enum,high,False, +chunk_d80165d5,src/scalar-crypto.adoc,5129,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > The Final Random: DRBGs",These are significantly easier to implement in software than in hardware.,CSR_controlled,enum,high,False, +chunk_cc6918ae,src/scalar-crypto.adoc,5168,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Quantum vs. Classical Random",This security model means that many of the available QRNG devices do not use cryptographic conditioning and may fail cryptographic statistical requirements cite:[HuHe20].,non_CSR_parameter,enum,medium,False, +chunk_8f76eda7,src/scalar-crypto.adoc,5168,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Quantum vs. Classical Random",Many implementers may consider them to be entropy sources instead.,non_CSR_parameter,enum,medium,False, +chunk_f1e13901,src/scalar-crypto.adoc,5194,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Post-Quantum Cryptography","Of course, one must avoid DRBGs that are based on problems that are easily solvable with quantum computers, such as factoring cite:[Sh94] in the case of the Blum-Blum-Shub generator cite:[BlBlSh86].",non_CSR_parameter,binary,very_high,False, +chunk_a25f96f8,src/scalar-crypto.adoc,5200,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Post-Quantum Cryptography","While even ""64-bit"" quantum security is extremely difficult to break, many applications specify a higher security requirement. NIST cite:[NI16] defines AES-128 to be ""Category 1"" equivalent post-quantum security, while AES-256 is ""Category 5"" (highest).",non_CSR_parameter,range,medium,False, +chunk_ea4b9ac0,src/scalar-crypto.adoc,5219,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Suggested GetNoise Test Interface","Since this type of interface is both necessary for security testing and also constitutes a potential backdoor to the cryptographic key generation process, we define a safety behavior that compliant implementations can have for temporarily disabling the entropy source `seed` CSR interface during test.",CSR_controlled,enum,high,False, +chunk_14e3315f,src/scalar-crypto.adoc,5225,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Suggested GetNoise Test Interface","In order for shared RISC-V self-certification scripts (and drivers) to accommodate the test interface in a secure fashion, we suggest that it is implemented as a custom, M-mode only CSR, denoted here as `mnoise`.",CSR_controlled,enum,high,False, +chunk_434131ac,src/scalar-crypto.adoc,5229,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Suggested GetNoise Test Interface","We define the semantics for single bit for this interface, `mnoise[31]`, which is named `NOISETEST`, which will affect the behavior of `seed` if implemented.",unknown,unknown,high,False, +chunk_8a163af0,src/scalar-crypto.adoc,5235,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Suggested GetNoise Test Interface","When `NOISETEST = 1` in `mnoise`, the `seed` CSR must not return anything via `ES16`; it should be in `BIST` state unless the source is `DEAD`.",CSR_controlled,enum,very_high,False, +chunk_6ae842cc,src/scalar-crypto.adoc,5235,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Suggested GetNoise Test Interface","When `NOISETEST` is again disabled, the entropy source shall return from `BIST` via an appropriate zeroization and self-test mechanism.",non_CSR_parameter,binary,very_high,False, +chunk_93b2f655,src/scalar-crypto.adoc,5241,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Suggested GetNoise Test Interface","The behavior of other input and output bits is largely left to the vendor (as they depend on the technical details of the physical entropy source), as is the address of the custom `mnoise` CSR.",CSR_controlled,enum,high,False, +chunk_2763a284,src/scalar-crypto.adoc,5241,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Suggested GetNoise Test Interface","Other contents and behavior of the CSR only can be interpreted in the context of `mvendorid`, `marchid`, and `mimpid` CSR identifiers.",CSR_controlled,enum,high,False, +chunk_ad7f258b,src/scalar-crypto.adoc,5252,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Suggested GetNoise Test Interface",Implementation of test interfaces that directly affect ES16 entropy output from the `seed` CSR interface is discouraged.,CSR_controlled,enum,high,False, +chunk_a34eb39b,src/scalar-crypto.adoc,5252,"Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Suggested GetNoise Test Interface",Hence even a temporary lapse in `entropy` security may have serious security implications.,non_CSR_parameter,enum,medium,False, +chunk_d800fa01,src/unpriv/bitmanip-examples.adoc,9,Preamble > Bit Manipulation Extensions Assembly Code Examples > strlen,"the result of *orc.b* on a chunk that does not contain any *NUL* bytes will be all-ones, and * after a bitwise-negation of the result of *orc.b*, the number of data bytes before the first *NUL* byte (if any) can be detected by *ctz*/*clz* (depending on the endianness of data).",unknown,unknown,high,False, +chunk_e6028ff0,src/unpriv/bitmanip-examples.adoc,109,Preamble > Bit Manipulation Extensions Assembly Code Examples > strlen > strcmp,"Get bytes in big-endian order and compare. if BYTEORDER ORDERLITTLEENDIAN rev8 a2, a2 rev8 a3, a3 endif Synthesize (a2 >= a3) ? 1 : -1 in a branchless sequence. sltu a0, a2, a3 neg a0, a0 ori a0, a0, 1 ret",unknown,unknown,high,False, +chunk_a5a4afaf,src/unpriv/bitmanip-examples.adoc,121,Preamble > Bit Manipulation Extensions Assembly Code Examples > strlen > strcmp,"If words don't match, fall back to simple loop. bne a2, a3, .Lsimpleloop",unknown,unknown,high,False, +chunk_d5c591df,src/unpriv/c-st-ext.adoc,13,Preamble > ext:c[] Extension for Compressed Instructions,"If XLEN=32 and the F extension is present, the ext:c[] extension additionally depends upon the extlink:zcf[] extension.",unknown,unknown,high,False, +chunk_76dbbf83,src/unpriv/c-st-ext.adoc,16,Preamble > ext:c[] Extension for Compressed Instructions,"If the D extension is present, the ext:c[] extension additionally depends upon the extlink:zcd[] extension.",unknown,unknown,high,False, +chunk_a5541f68,src/unpriv/cfi.adoc,13,Preamble > Control-flow Integrity (CFI),Conditional branches encode an offset in the immediate field of the instruction and are thus direct branches that are not susceptible to control-flow subversion.,unknown,enum,high,False, +chunk_ff57a87c,src/unpriv/cfi.adoc,13,Preamble > Control-flow Integrity (CFI),Unconditional indirect jumps using the `JALR` obtain their branch target by adding the sign extended 12-bit immediate encoded in the instruction to the `rs1` register.,non_CSR_parameter,range,high,False, +chunk_c616789b,src/unpriv/cfi.adoc,22,Preamble > Control-flow Integrity (CFI),The RV32I/RV64I does not have a dedicated instruction for calling a procedure or returning from a procedure. A `JAL` or `JALR` may be used to perform a procedure call and `JALR` to return from a procedure.,non_CSR_parameter,enum,medium,False, +chunk_c639dd6a,src/unpriv/cfi.adoc,31,Preamble > Control-flow Integrity (CFI),The `C.J` and `C.JAL` instructions encode an offset in the immediate field of the instruction and thus are not susceptible to control-flow subversion.,unknown,enum,high,False, +chunk_dd1685e2,src/unpriv/cfi.adoc,70,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp),The `LPAD` instruction must be placed at the program locations that are valid targets of indirect jumps or calls.,non_CSR_parameter,enum,very_high,False, +chunk_fdc515eb,src/unpriv/cfi.adoc,81,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp),"When the Zicfilp is active, the hart tracks an expected landing pad (`ELP`) state that is updated by an indirectcall or indirectjump to require a landing pad instruction at the target of the branch.",unknown,unknown,high,False, +chunk_0d038889,src/unpriv/cfi.adoc,81,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp),"If the instruction at the target is not a landing pad, then a software-check exception is raised.",SW_rule,unknown,high,False, +chunk_c07a1444,src/unpriv/cfi.adoc,89,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp),A landing pad may be optionally associated with a 20-bit label.,non_CSR_parameter,range,high,False, +chunk_78cbda99,src/unpriv/cfi.adoc,89,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp),"When labeling of landing pads is used, indirect call or indirect jump site can specify the expected label of the landing pad and thereby constrain the set of landing pads that may be reached from each indirect call or indirect jump site in the program.",non_CSR_parameter,enum,high,False, +chunk_05841818,src/unpriv/cfi.adoc,98,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp),"By constraining gadgets to be preceded by a landing pad instruction that marks the start of indirect callable functions, the program can significantly reduce the available gadget space. A second form of label generation may generate a signature, such as a MAC, using the prototype of the function.",non_CSR_parameter,enum,medium,False, +chunk_0b1a2a8f,src/unpriv/cfi.adoc,98,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp),"Such programs may further use multiple labels per function, which means that if a function is called from two or more call sites, the functions can be labeled as being reachable from each of the call sites.",non_CSR_parameter,enum,high,False, +chunk_f5a7f46a,src/unpriv/cfi.adoc,98,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp),"However, if function Y was assigned two labels - one corresponding to call site A and the other to call site B, then Y can be invoked by both call sites, but X can only be invoked by call site A and Z can only be invoked by call site B.",unknown,unknown,high,False, +chunk_d99afebb,src/unpriv/cfi.adoc,98,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp),"This would allow the function to be labeled with multiple labels, each corresponding to a specific call site. A portion of the label space may be dedicated to labeled landing pads that are only valid targets of an indirect jump (and not an indirect call).",non_CSR_parameter,enum,medium,False, +chunk_f5842660,src/unpriv/cfi.adoc,127,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp),"When Zicfilp is not active at a privilege level or when the extension is not implemented, the landing pad instruction executes as a no-op. A program that is built with `LPAD` instructions can thus continue to operate correctly, but without forward-edge control-flow integrity, on processors that do not support the Zicfilp extension or if the Zicfilp extension is not active.",unknown,enum,high,False, +chunk_f507952e,src/unpriv/cfi.adoc,134,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp),Compilers and linkers should provide an attribute flag to indicate if the program has been compiled with the Zicfilp extension and use that to determine if the Zicfilp extension should be activated.,non_CSR_parameter,enum,high,False, +chunk_fecd75f8,src/unpriv/cfi.adoc,134,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp),The dynamic loader should activate the use of Zicfilp extension for an application only if all executables (the application and the dependent dynamically linked libraries) used by that application use the Zicfilp extension.,non_CSR_parameter,enum,high,False, +chunk_40e9212b,src/unpriv/cfi.adoc,141,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp),"When Zicfilp extension is not active or not implemented, the hart does not require landing pad instructions at the targets of indirect calls/jumps, and the landing instructions revert to being no-ops.",unknown,unknown,high,False, +chunk_410b183a,src/unpriv/cfi.adoc,147,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp),The Zicfilp extensions may be activated for use individually and independently for each privilege mode.,non_CSR_parameter,enum,medium,False, +chunk_b2ac7cce,src/unpriv/cfi.adoc,150,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp),The Zicfilp extension depends on the Zicsr extension.,CSR_controlled,enum,high,False, +chunk_871c41a4,src/unpriv/cfi.adoc,154,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing Pad Enforcement,"To enforce that the target of an indirect call or indirect jump must be a valid landing pad instruction, the hart maintains an expected landing pad (`ELP`) state to determine if a landing pad instruction is required at the target of an indirect call or an indirect jump.",non_CSR_parameter,binary,very_high,False, +chunk_6e14207f,src/unpriv/cfi.adoc,164,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing Pad Enforcement,"The Zicfilp extension, when enabled, determines if an indirect call or an indirect jump must land on a landing pad, as specified in .",non_CSR_parameter,binary,very_high,False, +chunk_0f5d631f,src/unpriv/cfi.adoc,164,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing Pad Enforcement,"If `islpexpected` is 1, then the hart updates the `ELP` to `LPEXPECTED`.",unknown,unknown,high,False, +chunk_1816d7b0,src/unpriv/cfi.adoc,183,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing Pad Enforcement,The landing pad may be labeled.,non_CSR_parameter,enum,medium,False, +chunk_c1df2e5a,src/unpriv/cfi.adoc,183,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing Pad Enforcement,The `LPAD` instruction is encoded with a 20-bit immediate value called the landing-pad-label (`LPL`) that is matched to the expected landing pad label.,non_CSR_parameter,range,high,False, +chunk_e5f11012,src/unpriv/cfi.adoc,183,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing Pad Enforcement,"When `LPL` is encoded as zero, the `LPAD` instruction does not perform the label check and in programs built with this single label mode of operation the indirect call/jump sites do not need to establish an expected landing pad label value in `x7`.",unknown,enum,high,False, +chunk_efa1a38f,src/unpriv/cfi.adoc,193,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing Pad Enforcement,"When `ELP` is set to `LPEXPECTED`, if the next instruction in the instruction stream is not 4-byte aligned, or is not `LPAD`, or if the landing pad label encoded in `LPAD` is not zero and does not match the expected landing pad label in bits 31:12 of the `x7` register, then a software-check exception (cause=18) with `xtval` set to ""landing pad fault (code=2)"" is raised else the `ELP` is updated to `NOLPEXPECTED`.",SW_rule,range,high,False, +chunk_0c5f0d86,src/unpriv/cfi.adoc,206,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing Pad Enforcement > Landing Pad Instruction,"When Zicfilp is enabled, `LPAD` is the only instruction allowed to execute when the `ELP` state is `LPEXPECTED`.",unknown,binary,high,False, +chunk_e73ff3d6,src/unpriv/cfi.adoc,206,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing Pad Enforcement > Landing Pad Instruction,If Zicfilp is not enabled then the instruction is a no-op.,unknown,binary,high,False, +chunk_5b363bc7,src/unpriv/cfi.adoc,206,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing Pad Enforcement > Landing Pad Instruction,"If Zicfilp is enabled, the `LPAD` instruction causes a software-check exception with `xtval` set to ""landing pad fault (code=2)"" if any of the following conditions are true:",SW_rule,binary,high,False, +chunk_75394296,src/unpriv/cfi.adoc,212,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing Pad Enforcement > Landing Pad Instruction,The `pc` is not 4-byte aligned and `ELP` is `LPEXPECTED`. * The `ELP` is `LPEXPECTED` and the `LPL` is not zero and the `LPL` does not match the expected landing pad label in bits 31:12 of the `x7` register.,non_CSR_parameter,range,high,False, +chunk_f439a0f0,src/unpriv/cfi.adoc,215,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing Pad Enforcement > Landing Pad Instruction,If a software-check exception is not caused then the `ELP` is updated to `NOLPEXPECTED`.,SW_rule,unknown,high,False, +chunk_a4e42b97,src/unpriv/cfi.adoc,230,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing Pad Enforcement > Landing Pad Instruction,If PC not 4-byte aligned then software-check exception if pc[1:0] != 0 raise software-check exception //,SW_rule,range,high,False, +chunk_37d3e12d,src/unpriv/cfi.adoc,230,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing Pad Enforcement > Landing Pad Instruction,If landing pad label not matched -> software-check exception else if (inst.LPL != x7[31:12] && inst.LPL != 0) raise software-check exception else ELP = NOLPEXPECTED else no-op endif ---- <<<,SW_rule,unknown,high,False, +chunk_f099cf05,src/unpriv/cfi.adoc,252,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss),The Zicfiss extension introduces a shadow stack to enforce backward-edge control-flow integrity. A shadow stack is a second stack used to store a shadow copy of the return address in the link register if it needs to be spilled.,unknown,unknown,high,False, +chunk_a858386a,src/unpriv/cfi.adoc,262,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss),"The shadow stack is used to spill the link register, if required, by non-leaf functions.",unknown,unknown,high,False, +chunk_4e4bdadc,src/unpriv/cfi.adoc,282,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss),"When such a function returns (the epilogue), the function loads the link register from the regular stack and the shadow copy of the link register from the shadow stack.",unknown,unknown,high,False, +chunk_77fcb688,src/unpriv/cfi.adoc,282,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss),"Then, the link register value from the regular stack and the shadow link register value from the shadow stack are compared. A mismatch of the two values is indicative of a subversion of the return address control variable and causes a software-check exception.",SW_rule,unknown,high,False, +chunk_a2b1a9d1,src/unpriv/cfi.adoc,293,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss),"The Zicfiss instructions, except `SSAMOSWAP.W/D`, are encoded using a subset of May-Be-Operation instructions defined by the Zimop and Zcmop extensions.",unknown,enum,high,False, +chunk_309ec18a,src/unpriv/cfi.adoc,293,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss),"This subset of instructions revert to their Zimop/Zcmop defined behavior when the Zicfiss extension is not implemented or if the extension has not been activated. A program that is built with Zicfiss instructions can thus continue to operate correctly, but without backward-edge control-flow integrity, on processors that do not support the Zicfiss extension or if the Zicfiss extension is not active.",unknown,unknown,high,False, +chunk_88341973,src/unpriv/cfi.adoc,293,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss),The Zicfiss extension may be activated for use individually and independently for each privilege mode.,non_CSR_parameter,enum,medium,False, +chunk_fe0e295b,src/unpriv/cfi.adoc,310,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss),The dynamic loader should activate the use of Zicfiss extension for an application only if all executables (the application and the dependent dynamically-linked libraries) used by that application use the Zicfiss extension.,non_CSR_parameter,enum,high,False, +chunk_ffe57f52,src/unpriv/cfi.adoc,325,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss),"The Zicfiss extension depends on the Zicsr, Zimop and Zaamo extensions.",CSR_controlled,enum,high,False, +chunk_5d7c1318,src/unpriv/cfi.adoc,325,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss),"Furthermore, if the Zcmop extension is implemented, the Zicfiss extension also provides the `C.SSPUSH` and `C.SSPOPCHK` instructions.",unknown,unknown,high,False, +chunk_27aaf883,src/unpriv/cfi.adoc,348,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Zicfiss Instructions Summary,"When a `MOP.RR.7` or `MOP.R.28` encoding is not used by the Zicfiss extension, the corresponding instruction adheres to its Zimop-defined behavior, unless redefined by another extension.",unknown,enum,high,False, +chunk_9942154e,src/unpriv/cfi.adoc,355,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Pointer (`ssp`),The `ssp` CSR is an unprivileged read-write (URW) CSR that reads and writes `XLEN` low order bits of the shadow stack pointer (`ssp`).,CSR_controlled,enum,high,False, +chunk_84e9d6dd,src/unpriv/cfi.adoc,355,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Pointer (`ssp`),There is no high CSR defined as the `ssp` is always as wide as the `XLEN` of the current privilege mode.,CSR_controlled,enum,high,False, +chunk_32a94b69,src/unpriv/cfi.adoc,355,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Pointer (`ssp`),The bits 1:0 of `ssp` are read-only zero.,CSR_controlled,binary,high,False, +chunk_c3016c27,src/unpriv/cfi.adoc,355,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Pointer (`ssp`),"If the UXLEN or SXLEN may never be 32, then the bit 2 is also read-only zero.",CSR_controlled,binary,high,False, +chunk_fe86b5d0,src/unpriv/cfi.adoc,398,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Push to the Shadow Stack,Zicfiss provides a 16-bit version of the `SSPUSH x1` instruction using the Zcmop defined `C.MOP.1` encoding.,non_CSR_parameter,range,medium,False, +chunk_7f13ff0f,src/unpriv/cfi.adoc,455,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Pop from the Shadow Stack,Zicfiss provides a 16-bit version of the `SSPOPCHK x5` using the Zcmop defined `C.MOP.5` encoding.,non_CSR_parameter,range,medium,False, +chunk_e3093bf4,src/unpriv/cfi.adoc,459,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Pop from the Shadow Stack,"When returning from these non-leaf functions, such programs pop the link register from the regular stack and pop a shadow copy of the link register from the shadow stack.",unknown,unknown,high,False, +chunk_6d3fded7,src/unpriv/cfi.adoc,459,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Pop from the Shadow Stack,"If the values do not match, it is indicative of a corruption of the return address variable on the regular stack.",unknown,unknown,high,False, +chunk_6b0fdd34,src/unpriv/cfi.adoc,472,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Pop from the Shadow Stack,"While any register may be used as link register, conventionally the `x1` or `x5` registers are used.",non_CSR_parameter,enum,medium,False, +chunk_172d1c6a,src/unpriv/cfi.adoc,485,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Pop from the Shadow Stack,Only x1 and x5 may be used as src raise software-check exception else ssp = ssp + (XLEN/8) increment ssp by XLEN/8. endif endif ----,SW_rule,enum,high,False, +chunk_fb3e3fe3,src/unpriv/cfi.adoc,501,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Pop from the Shadow Stack,"If the value loaded from the address in `ssp` does not match the value in `rs1`, a software-check exception (cause=18) is raised with `xtval` set to ""shadow stack fault (code=3)"".",SW_rule,unknown,high,False, +chunk_87bc98ef,src/unpriv/cfi.adoc,501,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Pop from the Shadow Stack,The software-check exception caused by `SSPOPCHK`/ `C.SSPOPCHK` is lower in priority than a load/store/AMO access-fault exception.,SW_rule,unknown,high,False, +chunk_f46b0060,src/unpriv/cfi.adoc,507,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Pop from the Shadow Stack,The `ssp` is incremented by `SSPOPCHK` and `C.SSPOPCHK` only if the load from the shadow stack completes successfully and no software-check exception is raised.,SW_rule,unknown,high,False, +chunk_28b2d36b,src/unpriv/cfi.adoc,518,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Read `ssp` into a Register,The `SSRDP` instruction is provided to move the contents of `ssp` to a destination register.,unknown,unknown,high,False, +chunk_3e1e7a49,src/unpriv/cfi.adoc,533,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Read `ssp` into a Register,Encoding rd as `x0` is not supported for `SSRDP`.,unknown,enum,high,False, +chunk_dea0297e,src/unpriv/cfi.adoc,535,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Read `ssp` into a Register,The operation of the `SSRDP` instructions is as follows:,unknown,unknown,high,False, +chunk_f1a02f36,src/unpriv/cfi.adoc,568,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Atomic Swap from a Shadow Stack Location,"For RV32, `SSAMOSWAP.W` atomically loads a 32-bit data value from address of a shadow stack location in `rs1`, puts the loaded value into register `rd`, and stores the 32-bit value held in `rs2` to the original address in `rs1`. `SSAMOSWAP.D` (RV64 only) is similar to `SSAMOSWAP.W` but operates on 64-bit data values.",non_CSR_parameter,range,medium,False, +chunk_d75f186b,src/unpriv/cfi.adoc,594,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Atomic Swap from a Shadow Stack Location,"For RV64, `SSAMOSWAP.W` atomically loads a 32-bit data value from address of a shadow stack location in `rs1`, sign-extends the loaded value and puts it in `rd`, and stores the lower 32 bits of the value held in `rs2` to the original address in `rs1`.",non_CSR_parameter,range,high,False, +chunk_8ff591c2,src/unpriv/cfi.adoc,620,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Atomic Swap from a Shadow Stack Location,The same exception options apply if the address is not naturally aligned.,unknown,unknown,high,False, +chunk_f04d142b,src/unpriv/cfi.adoc,626,Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Atomic Swap from a Shadow Stack Location,An `SSAMOSWAP.W/D` operation has acquire semantics if `aq=1` and release semantics if `rl=1`.,unknown,unknown,high,False, +chunk_70b9e13d,src/unpriv/cmo.adoc,17,Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Introduction,"A management instruction manipulates cached copies of data with respect to a set of agents that can access the data * A zero instruction zeros out a range of memory locations, potentially allocating cached copies of data in one or more caches * A prefetch instruction indicates to hardware that data at a given memory location may be accessed in the near future, potentially allocating cached copies of data in one or more caches",non_CSR_parameter,enum,medium,False, +chunk_0f8f6d33,src/unpriv/cmo.adoc,37,Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Introduction,The execution behavior of the above instructions is also modified by CSR state added by this specification.,CSR_controlled,enum,high,False, +chunk_4d246f59,src/unpriv/cmo.adoc,62,Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Background > Memory and Caches,"Any number of caches may be interspersed between an agent and a memory location, and load and store operations from an agent may be satisfied by a cache instead of the memory location.",non_CSR_parameter,enum,medium,False, +chunk_fef45040,src/unpriv/cmo.adoc,67,Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Background > Memory and Caches,"In the initial set of CMO extensions, the size of a cache block shall be uniform throughout the system.",non_CSR_parameter,enum,very_high,False, +chunk_c5a53ad0,src/unpriv/cmo.adoc,76,Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Background > Memory and Caches,"Implementation techniques such as speculative execution or hardware prefetching may cause a given cache to allocate or deallocate a copy of a cache block at any time, provided the corresponding physical addresses are accessible according to the supported access type PMA and are cacheable according to the cacheability PMA.",SW_rule,enum,medium,False, +chunk_25dd6779,src/unpriv/cmo.adoc,76,Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Background > Memory and Caches,"Allocating a copy of a cache block results in a read transfer from another cache or from memory, while deallocating a copy of a cache block may result in a write transfer to another cache or to memory depending on whether the data in the copy were modified by a store operation.",non_CSR_parameter,enum,medium,False, +chunk_f30d8b44,src/unpriv/cmo.adoc,98,Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Background > Cache-Block Operations,A clean operation performs a write transfer to another cache or to memory if the data in the copy of the cache block have been modified by a store operation,unknown,unknown,high,False, +chunk_c6d70ed4,src/unpriv/cmo.adoc,108,Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Background > Cache-Block Operations,"Unless specified otherwise, the store operations generated by a cache-block zero instruction have the same general properties and behaviors that other store instructions in the architecture have.",unknown,unknown,high,False, +chunk_ad671992,src/unpriv/cmo.adoc,108,Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Background > Cache-Block Operations,An implementation may or may not update the entire set of bytes atomically with a single store operation.,non_CSR_parameter,enum,medium,False, +chunk_a013b8fe,src/unpriv/cmo.adoc,133,Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches,"The coherent agents within such a set shall access a given memory location with the same physical address and the same physical memory attributes; however, if the coherence PMA for a given agent indicates a given memory location is not coherent, that agent shall not be a member of a set of coherent agents with any other agent for that memory location and shall be the sole member of a set of coherent agents consisting of itself.",non_CSR_parameter,binary,very_high,False, +chunk_75f4f251,src/unpriv/cmo.adoc,145,Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches,Caches introduce the possibility that multiple copies of a given cache block may be present in a system at the same time.,non_CSR_parameter,enum,medium,False, +chunk_4abb473e,src/unpriv/cmo.adoc,145,Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches,"Additionally, if a coherent agent in the set executes a CBO instruction that specifies the cache block, the resulting operation shall apply to any and all of the copies in the caches that can be accessed by the load and store operations from the coherent agents.",non_CSR_parameter,binary,very_high,False, +chunk_216bd557,src/unpriv/cmo.adoc,160,Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches,"A coherent cache is permitted to perform a write transfer to memory provided that a store operation has modified the data in the cache block since the most recent invalidate, clean, or flush operation on the cache block",unknown,unknown,high,False, +chunk_d491fb56,src/unpriv/cmo.adoc,170,Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches,"A coherent cache is required to perform a write transfer to memory if a store operation has modified the data in the cache block since the most recent invalidate, clean, or flush operation on the cache block and if the next clean or flush operation requires a write transfer to memory",non_CSR_parameter,unknown,high,False, +chunk_d93d1724,src/unpriv/cmo.adoc,175,Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches,A non-coherent agent may initiate a cache-block operation that operates on the set of coherent caches accessed by a set of coherent agents.,non_CSR_parameter,enum,medium,False, +chunk_ff1e4842,src/unpriv/cmo.adoc,187,Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Memory Ordering > Preserved Program Order,"Specifically, if a precedes b in program order, then a will precede b in the global memory order if:",unknown,unknown,high,False, +chunk_9157077d,src/unpriv/cmo.adoc,210,Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Memory Ordering > Load Values,An invalidate operation may change the set of values that can be returned by a load.,non_CSR_parameter,enum,medium,False, +chunk_9abaea11,src/unpriv/cmo.adoc,213,Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Memory Ordering > Load Values,"If an invalidate operation i precedes a load r and operates on a byte x returned by r, and no store to x appears between i and r in program order or in the global memory order, then r returns any of the following values for x:",unknown,unknown,high,False, +chunk_1f9748b3,src/unpriv/cmo.adoc,218,Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Memory Ordering > Load Values,"If no clean or flush operations on x precede i in the global memory order, either the initial value of x or the value of any store to x that precedes i",unknown,enum,high,False, +chunk_905ce2ff,src/unpriv/cmo.adoc,222,Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Memory Ordering > Load Values,"If no store to x precedes a clean or flush operation on x in the global memory order and if the clean or flush operation on x precedes i in the global memory order, either the initial value of x or the value of any store to x that precedes i",unknown,enum,high,False, +chunk_4edfbf82,src/unpriv/cmo.adoc,227,Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Memory Ordering > Load Values,"If a store to x precedes a clean or flush operation on x in the global memory order and if the clean or flush operation on x precedes i in the global memory order, either the value of the latest store to x that precedes the latest clean or flush operation on x or the value of any store to x that both precedes i and succeeds the latest clean or flush operation on x that precedes i",unknown,enum,high,False, +chunk_8c4588d9,src/unpriv/cmo.adoc,234,Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Memory Ordering > Load Values,The value of any store to x by a non-coherent agent regardless of the above conditions,unknown,enum,high,False, +chunk_17c5d1b2,src/unpriv/cmo.adoc,239,Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Traps,"Execution of certain CMO instructions may result in traps due to CSR state, described in the section, or due to the address translation and protection mechanisms.",CSR_controlled,enum,high,False, +chunk_2047f520,src/unpriv/cmo.adoc,239,Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Traps,The trapping behavior of CMO instructions is described in the following sections.,unknown,unknown,high,False, +chunk_135b9f22,src/unpriv/cmo.adoc,246,Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Traps > Illegal-Instruction and Virtual-Instruction Exceptions,Cache-block management instructions and cache-block zero instructions may raise illegal-instruction exceptions or virtual-instruction exceptions depending on the current privilege mode and the state of the CMO control registers described in the section.,non_CSR_parameter,enum,high,False, +chunk_91674397,src/unpriv/cmo.adoc,251,Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Traps > Illegal-Instruction and Virtual-Instruction Exceptions,Cache-block prefetch instructions raise neither illegal-instruction exceptions nor virtual-instruction exceptions.,non_CSR_parameter,enum,high,False, +chunk_ba012004,src/unpriv/cmo.adoc,262,"Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Traps > Page-Fault, Guest-Page-Fault, and Access-Fault Exceptions","The PMP access control bits shall be the same for all physical addresses in the cache block, and if write permission is granted by the PMP access control bits, read permission shall also be granted",non_CSR_parameter,binary,very_high,False, +chunk_0ba97f21,src/unpriv/cmo.adoc,266,"Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Traps > Page-Fault, Guest-Page-Fault, and Access-Fault Exceptions","The PMAs shall be the same for all physical addresses in the cache block, and if write permission is granted by the supported access type PMAs, read permission shall also be granted",non_CSR_parameter,binary,very_high,False, +chunk_bdba7395,src/unpriv/cmo.adoc,270,"Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Traps > Page-Fault, Guest-Page-Fault, and Access-Fault Exceptions","If the above constraints are not met, the behavior of a CBO instruction is UNSPECIFIED.",non_CSR_parameter,unknown,high,False, +chunk_3aa7bb28,src/unpriv/cmo.adoc,273,"Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Traps > Page-Fault, Guest-Page-Fault, and Access-Fault Exceptions","Main memory regions are required to support accesses by cache-block zero instructions; however, I/O regions may specify whether accesses by cache-block zero instructions are supported.",non_CSR_parameter,enum,medium,False, +chunk_bc844375,src/unpriv/cmo.adoc,278,"Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Traps > Page-Fault, Guest-Page-Fault, and Access-Fault Exceptions","If neither a load instruction nor store instruction is permitted to access the physical addresses, but an instruction fetch is permitted to access the physical addresses, whether a cache-block management instruction is permitted to access the cache block is UNSPECIFIED.",non_CSR_parameter,enum,high,False, +chunk_e9b47295,src/unpriv/cmo.adoc,278,"Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Traps > Page-Fault, Guest-Page-Fault, and Access-Fault Exceptions","If access to the cache block is not permitted, a cache-block management instruction raises a store page-fault or store guest-page-fault exception if address translation does not permit any access or raises a store access-fault exception otherwise.",non_CSR_parameter,unknown,high,False, +chunk_15e20446,src/unpriv/cmo.adoc,278,"Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Traps > Page-Fault, Guest-Page-Fault, and Access-Fault Exceptions","During address translation, the instruction also checks the accessed bit and may either raise an exception or set the bit as required.",non_CSR_parameter,enum,high,False, +chunk_7ddf3070,src/unpriv/cmo.adoc,290,"Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Traps > Page-Fault, Guest-Page-Fault, and Access-Fault Exceptions",A cache-block zero instruction is permitted to access the specified cache block whenever a store instruction is permitted to access the corresponding physical addresses and when the PMAs indicate that cache-block zero instructions are a supported access type.,unknown,unknown,high,False, +chunk_4661739b,src/unpriv/cmo.adoc,290,"Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Traps > Page-Fault, Guest-Page-Fault, and Access-Fault Exceptions","If access to the cache block is not permitted, a cache-block zero instruction raises a store page-fault or store guest-page-fault exception if address translation does not permit write access or raises a store access-fault exception otherwise.",non_CSR_parameter,unknown,high,False, +chunk_cd91ad39,src/unpriv/cmo.adoc,290,"Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Traps > Page-Fault, Guest-Page-Fault, and Access-Fault Exceptions","During address translation, the instruction also checks the accessed and dirty bits and may either raise an exception or set the bits as required.",non_CSR_parameter,enum,high,False, +chunk_18de9b48,src/unpriv/cmo.adoc,300,"Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Traps > Page-Fault, Guest-Page-Fault, and Access-Fault Exceptions","If access to the cache block is not permitted, a cache-block prefetch instruction does not raise any exceptions and shall not access any caches or memory.",non_CSR_parameter,binary,very_high,False, +chunk_afcc32a5,src/unpriv/cmo.adoc,300,"Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Traps > Page-Fault, Guest-Page-Fault, and Access-Fault Exceptions","During address translation, the instruction does not check the accessed and dirty bits and neither raises an exception nor sets the bits.",non_CSR_parameter,enum,high,False, +chunk_28d4d64b,src/unpriv/cmo.adoc,314,Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Traps > Address-Misaligned Exceptions,CMO instructions do not generate address-misaligned exceptions.,unknown,unknown,high,False, +chunk_2543dec1,src/unpriv/cmo.adoc,319,Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Traps > Breakpoint Exceptions and Debug Mode Entry,"Unless otherwise defined by the debug architecture specification, the behavior of trigger modules with respect to CMO instructions is UNSPECIFIED.",non_CSR_parameter,unknown,high,False, +chunk_767b8f61,src/unpriv/cmo.adoc,324,Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Traps > Hypervisor Extension,"For the purposes of writing the `mtinst` or `htinst` register on a trap, the following standard transformation is defined for cache-block management instructions and cache-block zero instructions:",unknown,unknown,high,False, +chunk_9981bf2a,src/unpriv/cmo.adoc,340,Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Traps > Hypervisor Extension,The `operation` field corresponds to the 12 most significant bits of the trapping instruction.,unknown,enum,high,False, +chunk_34f5dcaf,src/unpriv/cmo.adoc,361,Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Software Discovery,Other general cache characteristics may also be specified in the discovery mechanism.,non_CSR_parameter,enum,medium,False, +chunk_f9fbcf96,src/unpriv/cmo.adoc,367,Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > CSR controls for CMO instructions,"The x{csrname} registers control CBO instruction execution based on the current privilege mode and the state of the appropriate CSRs, as detailed below.",CSR_controlled,enum,high,False, +chunk_97ffe78d,src/unpriv/cmo.adoc,370,Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > CSR controls for CMO instructions,A `CBO.INVAL` instruction executes or raises either an illegal-instruction exception or a virtual-instruction exception based on the state of the `x{csrname}.CBIE` fields:,CSR_controlled,enum,high,False, +chunk_0e5171b7,src/unpriv/cmo.adoc,408,Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > CSR controls for CMO instructions,A `CBO.CLEAN` or `CBO.FLUSH` instruction executes or raises an illegal-instruction or virtual-instruction exception based on the state of the `x{csrname}.CBCFE` bits:,CSR_controlled,enum,high,False, +chunk_895a12b5,src/unpriv/cmo.adoc,436,Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > CSR controls for CMO instructions,"Finally, a `CBO.ZERO` instruction executes or raises an illegal-instruction or virtual-instruction exception based on the state of the `x{csrname}.CBZE` bits:",CSR_controlled,enum,high,False, +chunk_4ede1bb0,src/unpriv/cmo.adoc,463,Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > CSR controls for CMO instructions,The CBIE/CBCFE/CBZE fields in each `x{csrname}` register do not affect the read and write behavior of the same fields in the other `x{csrname}` registers.,CSR_controlled,enum,high,False, +chunk_d81e9d78,src/unpriv/cmo.adoc,467,Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > CSR controls for CMO instructions,"Each `x{csrname}` register is WARL; however, software should determine the legal values from the execution environment discovery mechanism.",CSR_controlled,enum,very_high,False, +chunk_00a69760,src/unpriv/cmo.adoc,541,Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Extensions > Cache-Block Zero Instructions,"An implementation may update the bytes in any order and with any granularity and atomicity, including individual bytes.",non_CSR_parameter,enum,medium,False, +chunk_693f42c3,src/unpriv/cmo.adoc,574,Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Extensions > Cache-Block Prefetch Instructions,"These instructions operate on the cache block whose effective address is the sum of the base address specified in rs1 and the sign-extended offset encoded in imm[11:0], where imm[4:0] shall equal `0b00000`.",non_CSR_parameter,enum,very_high,False, +chunk_ec901148,src/unpriv/cmo.adoc,632,Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > cbo.clean,"The offset operand may be omitted; otherwise, any expression that computes the offset shall evaluate to zero.",non_CSR_parameter,enum,very_high,False, +chunk_8e913bcc,src/unpriv/cmo.adoc,661,Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > cbo.flush,"On faults, the faulting virtual address is considered to be the value in rs1, rather than the base address of the cache block.",unknown,unknown,high,False, +chunk_71e6f59d,src/unpriv/cmo.adoc,668,Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > cbo.flush,The assembly offset operand may be omitted.,non_CSR_parameter,enum,medium,False, +chunk_457bb6ed,src/unpriv/cmo.adoc,668,Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > cbo.flush,If it isn't then any expression that computes the offset shall evaluate to zero.,non_CSR_parameter,binary,very_high,False, +chunk_18780dda,src/unpriv/cmo.adoc,694,Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > cbo.inval,"On faults, the faulting virtual address is considered to be the value in rs1, rather than the base address of the cache block.",unknown,unknown,high,False, +chunk_21893a48,src/unpriv/cmo.adoc,701,Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > cbo.inval,"Depending on CSR programming, the instruction may perform a flush operation instead of an invalidate operation.",CSR_controlled,enum,high,False, +chunk_21d81d84,src/unpriv/cmo.adoc,704,Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > cbo.inval,The assembly offset operand may be omitted.,non_CSR_parameter,enum,medium,False, +chunk_501d0fd9,src/unpriv/cmo.adoc,704,Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > cbo.inval,If it isn't then any expression that computes the offset shall evaluate to zero.,non_CSR_parameter,binary,very_high,False, +chunk_225a2730,src/unpriv/cmo.adoc,730,Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > cbo.zero,"On faults, the faulting virtual address is considered to be the value in rs1, rather than the base address of the cache block.",unknown,unknown,high,False, +chunk_3a72bf01,src/unpriv/cmo.adoc,730,Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > cbo.zero,An implementation may or may not update the entire set of bytes atomically.,non_CSR_parameter,enum,medium,False, +chunk_da05c2dc,src/unpriv/cmo.adoc,737,Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > cbo.zero,The assembly offset operand may be omitted.,non_CSR_parameter,enum,medium,False, +chunk_1b10ed25,src/unpriv/cmo.adoc,737,Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > cbo.zero,If it isn't then any expression that computes the offset shall evaluate to zero.,non_CSR_parameter,binary,very_high,False, +chunk_34be1a43,src/unpriv/cmo.adoc,766,Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > prefetch.i,"A *prefetch.i* instruction indicates to hardware that the cache block whose effective address is the sum of the base address specified in rs1 and the sign-extended offset encoded in imm[11:0], where imm[4:0] equals `0b00000`, is likely to be accessed by an instruction fetch in the near future.",unknown,enum,high,False, +chunk_6aea78ce,src/unpriv/d-st-ext.adoc,12,"Preamble > ""D"" Extension for Double-Precision Floating-Point, Version 2.2 > D Register State","The D extension widens the 32 floating-point registers, `f0-f31`, to 64 bits (FLEN=64 in ).",non_CSR_parameter,range,high,False, +chunk_fdcb2901,src/unpriv/d-st-ext.adoc,12,"Preamble > ""D"" Extension for Double-Precision Floating-Point, Version 2.2 > D Register State",The `f` registers can now hold either 32-bit or 64-bit floating-point values as described below in .,non_CSR_parameter,range,high,False, +chunk_31603a1b,src/unpriv/d-st-ext.adoc,22,"Preamble > ""D"" Extension for Double-Precision Floating-Point, Version 2.2 > D Register State > NaN Boxing of Narrower Values","When multiple floating-point precisions are supported, then valid values of narrower n-bit types, n ""D"" Extension for Double-Precision Floating-Point, Version 2.2 > D Register State > NaN Boxing of Narrower Values",The upper bits of a valid NaN-boxed value must be all 1s.,non_CSR_parameter,enum,very_high,False, +chunk_556104c7,src/unpriv/d-st-ext.adoc,22,"Preamble > ""D"" Extension for Double-Precision Floating-Point, Version 2.2 > D Register State > NaN Boxing of Narrower Values","Valid NaN-boxed n-bit values therefore appear as negative quiet NaNs (qNaNs) when viewed as any wider m-bit value, n < m {le} FLEN.",unknown,unknown,high,False, +chunk_4614bfa3,src/unpriv/d-st-ext.adoc,22,"Preamble > ""D"" Extension for Double-Precision Floating-Point, Version 2.2 > D Register State > NaN Boxing of Narrower Values",Any operation that writes a narrower result to an 'f' register must write all 1s to the uppermost FLEN-n bits to yield a legal NaN-boxedvalue.,non_CSR_parameter,enum,very_high,False, +chunk_2c0ef9fa,src/unpriv/d-st-ext.adoc,29,"Preamble > ""D"" Extension for Double-Precision Floating-Point, Version 2.2 > D Register State > NaN Boxing of Narrower Values","Floating-point n-bit transfer operations move external values held in the IEEE 754-2008 formats into and out of the `f` registers, and comprise floating-point loads and stores (FLn/FSn) and floating-point move instructions (FMV.n.X/FMV.X.n). A narrower n-bit transfer, n ""D"" Extension for Double-Precision Floating-Point, Version 2.2 > D Register State > NaN Boxing of Narrower Values","If so, the n least-significant bits of the input are used as the input value, otherwise the input value is treated as an n-bit canonical NaN.",unknown,unknown,high,False, +chunk_dc48bb74,src/unpriv/d-st-ext.adoc,51,"Preamble > ""D"" Extension for Double-Precision Floating-Point, Version 2.2 > D Register State > Double-Precision Load and Store Instructions",The FLD instruction loads a double-precision floating-point value from memory into floating-point register rd. FSD stores a double-precision value from the floating-point registers to memory.,unknown,unknown,high,False, +chunk_95a9506d,src/unpriv/d-st-ext.adoc,60,"Preamble > ""D"" Extension for Double-Precision Floating-Point, Version 2.2 > D Register State > Double-Precision Load and Store Instructions",FLD and FSD are only guaranteed to execute atomically if the effective address is naturally aligned and XLEN{ge}64.,unknown,unknown,high,False, +chunk_5653d8f5,src/unpriv/d-st-ext.adoc,64,"Preamble > ""D"" Extension for Double-Precision Floating-Point, Version 2.2 > D Register State > Double-Precision Load and Store Instructions","FLD and FSD do not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved.",unknown,unknown,high,False, +chunk_0bc742e7,src/unpriv/d-st-ext.adoc,70,"Preamble > ""D"" Extension for Double-Precision Floating-Point, Version 2.2 > D Register State > Double-Precision Floating-Point Computational Instructions","The double-precision floating-point computational instructions are defined analogously to their single-precision counterparts, but operate on double-precision operands and produce double-precision results.",unknown,unknown,high,False, +chunk_0931643d,src/unpriv/d-st-ext.adoc,81,"Preamble > ""D"" Extension for Double-Precision Floating-Point, Version 2.2 > D Register State > Double-Precision Floating-Point Conversion and Move Instructions","Floating-point-to-integer and integer-to-floating-point conversion instructions are encoded in the OP-FP major opcode space. FCVT.W.D or FCVT.L.D converts a double-precision floating-point number in floating-point register rs1 to a signed 32-bit or 64-bit integer, respectively, in integer register rd. FCVT.D.W or FCVT.D.L converts a 32-bit or 64-bit signed integer, respectively, in integer register rs1 into a double-precision floating-point number in floating-point register rd. FCVT.WU.D, FCVT.LU.D, FCVT.D.WU, and FCVT.D.LU variants convert to or from unsigned integer values.",non_CSR_parameter,range,high,False, +chunk_5c3d0e09,src/unpriv/d-st-ext.adoc,81,"Preamble > ""D"" Extension for Double-Precision Floating-Point, Version 2.2 > D Register State > Double-Precision Floating-Point Conversion and Move Instructions","For RV64, FCVT.W[U].D sign-extends the 32-bit result. FCVT.L[U].D and FCVT.D.L[U] are RV64-only instructions.",non_CSR_parameter,range,high,False, +chunk_6818df56,src/unpriv/d-st-ext.adoc,81,"Preamble > ""D"" Extension for Double-Precision Floating-Point, Version 2.2 > D Register State > Double-Precision Floating-Point Conversion and Move Instructions",The range of valid inputs for FCVT.int.D and the behavior for invalid inputs are the same as for FCVT.int.S.,unknown,unknown,high,False, +chunk_2330def6,src/unpriv/d-st-ext.adoc,95,"Preamble > ""D"" Extension for Double-Precision Floating-Point, Version 2.2 > D Register State > Double-Precision Floating-Point Conversion and Move Instructions",All floating-point to integer and integer to floating-point conversion instructions round according to the rm field.,unknown,enum,high,False, +chunk_1878cf7c,src/unpriv/d-st-ext.adoc,103,"Preamble > ""D"" Extension for Double-Precision Floating-Point, Version 2.2 > D Register State > Double-Precision Floating-Point Conversion and Move Instructions","The double-precision to single-precision and single-precision to double-precision conversion instructions, FCVT.S.D and FCVT.D.S, are encoded in the OP-FP major opcode space and both the source and destination are floating-point registers.",unknown,enum,high,False, +chunk_6a39c27f,src/unpriv/d-st-ext.adoc,103,"Preamble > ""D"" Extension for Double-Precision Floating-Point, Version 2.2 > D Register State > Double-Precision Floating-Point Conversion and Move Instructions","The rs2 field encodes the datatype of the source, and the fmt field encodes the datatype of the destination. FCVT.S.D rounds according to the RM field; FCVT.D.S will never round.",unknown,enum,high,False, +chunk_eb9f8dfe,src/unpriv/d-st-ext.adoc,117,"Preamble > ""D"" Extension for Double-Precision Floating-Point, Version 2.2 > D Register State > Double-Precision Floating-Point Conversion and Move Instructions","Floating-point to floating-point sign-injection instructions, FSGNJ.D, FSGNJN.D, and FSGNJX.D are defined analogously to the single-precision sign-injection instruction. //FSGNJ.D, FSGNJN.D, and FSGNJX.D",unknown,unknown,high,False, +chunk_f5028b11,src/unpriv/d-st-ext.adoc,126,"Preamble > ""D"" Extension for Double-Precision Floating-Point, Version 2.2 > D Register State > Double-Precision Floating-Point Conversion and Move Instructions","For XLEN{ge}64 only, instructions are provided to move bit patterns between the floating-point and integer registers. FMV.X.D moves the double-precision value in floating-point register rs1 to a representation in the IEEE 754-2008 encoding in integer register rd. FMV.D.X moves the double-precision value encoded in the IEEE 754-2008 encoding from the integer register rs1 to the floating-point register rd.",unknown,enum,high,False, +chunk_c85c11f0,src/unpriv/d-st-ext.adoc,134,"Preamble > ""D"" Extension for Double-Precision Floating-Point, Version 2.2 > D Register State > Double-Precision Floating-Point Conversion and Move Instructions","FMV.X.D and FMV.D.X do not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved.",unknown,unknown,high,False, +chunk_c8703113,src/unpriv/d-st-ext.adoc,156,"Preamble > ""D"" Extension for Double-Precision Floating-Point, Version 2.2 > D Register State > Double-Precision Floating-Point Classify Instruction","The double-precision floating-point classify instruction, FCLASS.D, is defined analogously to its single-precision counterpart, but operates on double-precision operands.",unknown,unknown,high,False, +chunk_1991a1a4,src/unpriv/f-st-ext.adoc,3,"Preamble > ""F"" Extension for Single-Precision Floating-Point, Version 2.2","The F extension depends on the ""Zicsr"" extension for control and status register access.",CSR_controlled,enum,high,False, +chunk_b615d00e,src/unpriv/f-st-ext.adoc,11,"Preamble > ""F"" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State","The F extension adds 32 floating-point registers, `f0-f31`, each 32 bits wide, and a floating-point control and status register `fcsr`, which contains the operating mode and exception status of the floating-point unit.",CSR_controlled,range,high,False, +chunk_72d74173,src/unpriv/f-st-ext.adoc,11,"Preamble > ""F"" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State",This additional state is shown in .,unknown,unknown,high,False, +chunk_2e164b71,src/unpriv/f-st-ext.adoc,11,"Preamble > ""F"" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State","We use the term FLEN to describe the width of the floating-point registers in the RISC-V ISA, and FLEN=32 for the F single-precision floating-point extension.",unknown,unknown,high,False, +chunk_f67b35ab,src/unpriv/f-st-ext.adoc,11,"Preamble > ""F"" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State",Most floating-point instructions operate on values in the floating-point register file.,unknown,unknown,high,False, +chunk_b1d800b5,src/unpriv/f-st-ext.adoc,11,"Preamble > ""F"" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State",Floating-point load and store instructions transfer floating-point values between registers and memory.,unknown,unknown,high,False, +chunk_95bd5a0f,src/unpriv/f-st-ext.adoc,11,"Preamble > ""F"" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State",Instructions to transfer values to and from the integer register file are also provided.,unknown,unknown,high,False, +chunk_0cc999d8,src/unpriv/f-st-ext.adoc,67,"Preamble > ""F"" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Floating-Point Control and Status Register","The floating-point control and status register, `fcsr`, is a RISC-V control and status register (CSR).",CSR_controlled,enum,high,False, +chunk_b53db82e,src/unpriv/f-st-ext.adoc,67,"Preamble > ""F"" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Floating-Point Control and Status Register","It is a 32-bit read/write register that selects the dynamic rounding mode for floating-point arithmetic operations and holds the accrued exception flags, as shown in .",CSR_controlled,range,high,False, +chunk_79ad7d38,src/unpriv/f-st-ext.adoc,77,"Preamble > ""F"" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Floating-Point Control and Status Register","The `fcsr` register can be read and written with the FRCSR and FSCSR instructions, which are assembler pseudoinstructions built on the underlying CSR access instructions. FRCSR reads `fcsr` by copying it into integer register rd. FSCSR swaps the value in `fcsr` by copying the original value into integer register rd, and then writing a new value obtained from integer register rs1 into `fcsr`.",CSR_controlled,enum,high,False, +chunk_e3f82d9d,src/unpriv/f-st-ext.adoc,84,"Preamble > ""F"" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Floating-Point Control and Status Register","The fields within the `fcsr` can also be accessed individually through different CSR addresses, and separate assembler pseudoinstructions are defined for these accesses.",CSR_controlled,enum,high,False, +chunk_868eec54,src/unpriv/f-st-ext.adoc,84,"Preamble > ""F"" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Floating-Point Control and Status Register","The FRRM instruction reads the Rounding Mode field `frm` (`fcsr` bits 7--5) and copies it into the least-significant three bits of integer register rd, with zero in all other bits. FSRM swaps the value in `frm` by copying the original value into integer register rd, and then writing a new value obtained from the three least-significant bits of integer register rs1 into `frm`. FRFLAGS and FSFLAGS are defined analogously for the Accrued Exception Flags field `fflags` (`fcsr` bits 4--0).",CSR_controlled,enum,high,False, +chunk_444044d0,src/unpriv/f-st-ext.adoc,95,"Preamble > ""F"" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Floating-Point Control and Status Register",Bits 31--8 of the `fcsr` are reserved for other standard extensions.,CSR_controlled,enum,high,False, +chunk_bb9e1a1c,src/unpriv/f-st-ext.adoc,95,"Preamble > ""F"" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Floating-Point Control and Status Register","If these extensions are not present, implementations shall ignore writes to these bits and supply a zero value when read.",non_CSR_parameter,binary,very_high,False, +chunk_9140a189,src/unpriv/f-st-ext.adoc,95,"Preamble > ""F"" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Floating-Point Control and Status Register",Standard software should preserve the contents of these bits.,SW_rule,enum,high,False, +chunk_494a48e8,src/unpriv/f-st-ext.adoc,101,"Preamble > ""F"" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Floating-Point Control and Status Register","Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in `frm`.",CSR_controlled,enum,high,False, +chunk_a9563045,src/unpriv/f-st-ext.adoc,101,"Preamble > ""F"" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Floating-Point Control and Status Register",Rounding modes are encoded as shown in . A value of 111 in the instruction's rm field selects the dynamic rounding mode held in `frm`.,CSR_controlled,enum,high,False, +chunk_16d46055,src/unpriv/f-st-ext.adoc,101,"Preamble > ""F"" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Floating-Point Control and Status Register","The behavior of floating-point instructions that depend on rounding mode when executed with a reserved rounding mode is reserved, including both static reserved rounding modes (101-110) and dynamic reserved rounding modes (101-111).",unknown,unknown,high,False, +chunk_d255edd5,src/unpriv/f-st-ext.adoc,101,"Preamble > ""F"" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Floating-Point Control and Status Register","Some instructions, including widening conversions, have the rm field but are nevertheless mathematically unaffected by the rounding mode; software should set their rm field to RNE (000) but implementations must treat the rm field as usual (in particular, with regard to decoding legal vs. reserved encodings).",SW_rule,enum,very_high,False, +chunk_2e4cd33b,src/unpriv/f-st-ext.adoc,125,"Preamble > ""F"" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Floating-Point Control and Status Register","The accrued exception flags indicate the exception conditions that have arisen on any floating-point arithmetic instruction since the field was last reset by software, as shown in .",SW_rule,enum,high,False, +chunk_a4c47ee2,src/unpriv/f-st-ext.adoc,125,"Preamble > ""F"" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Floating-Point Control and Status Register",The base RISC-V ISA does not support generating a trap on the setting of a floating-point exception flag.,unknown,unknown,high,False, +chunk_3a461859,src/unpriv/f-st-ext.adoc,147,"Preamble > ""F"" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > NaN Generation and Propagation","Except when otherwise stated, if the result of a floating-point operation is NaN, it is the canonical NaN.",unknown,unknown,high,False, +chunk_06458eda,src/unpriv/f-st-ext.adoc,147,"Preamble > ""F"" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > NaN Generation and Propagation","The canonical NaN has a positive sign and all significand bits clear except the MSB, a.k.a. the quiet bit.",unknown,unknown,high,False, +chunk_f938b6e7,src/unpriv/f-st-ext.adoc,147,"Preamble > ""F"" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > NaN Generation and Propagation","For single-precision floating-point, this corresponds to the pattern `0x7fc00000`.",unknown,unknown,high,False, +chunk_a4b85a69,src/unpriv/f-st-ext.adoc,159,"Preamble > ""F"" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Subnormal Arithmetic",Operations on subnormal numbers are handled in accordance with IEEE 754-2008.,unknown,unknown,high,False, +chunk_17d82abe,src/unpriv/f-st-ext.adoc,164,"Preamble > ""F"" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Subnormal Arithmetic","In the parlance of IEEE 754-2008, tininess is detected after rounding.",unknown,unknown,high,False, +chunk_71f88c81,src/unpriv/f-st-ext.adoc,170,"Preamble > ""F"" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Load and Store Instructions",The FLW instruction loads a single-precision floating-point value from memory into floating-point register rd. FSW stores a single-precision value from floating-point register rs2 to memory.,unknown,unknown,high,False, +chunk_c2ab8c6b,src/unpriv/f-st-ext.adoc,177,"Preamble > ""F"" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Load and Store Instructions",FLW and FSW are only guaranteed to execute atomically if the effective address is naturally aligned.,unknown,unknown,high,False, +chunk_cd3fb6b8,src/unpriv/f-st-ext.adoc,181,"Preamble > ""F"" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Load and Store Instructions","FLW and FSW do not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved.",unknown,unknown,high,False, +chunk_5e5094c2,src/unpriv/f-st-ext.adoc,184,"Preamble > ""F"" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Load and Store Instructions","As described in , the execution environment defines whether misaligned floating-point loads and stores are handled invisibly or raise a contained or fatal trap.",SW_rule,unknown,high,False, +chunk_326f8d50,src/unpriv/f-st-ext.adoc,190,"Preamble > ""F"" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Computational Instructions","Floating-point arithmetic instructions with one or two source operands use the R-type format with the OP-FP major opcode. FADD.S and FMUL.S perform single-precision floating-point addition and multiplication respectively, between rs1 and rs2. FSUB.S performs the single-precision floating-point subtraction of rs2 from rs1. FDIV.S performs the single-precision floating-point division of rs1 by rs2. FSQRT.S computes the square root of rs1.",unknown,unknown,high,False, +chunk_ce8cdf68,src/unpriv/f-st-ext.adoc,196,"Preamble > ""F"" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Computational Instructions",The 2-bit floating-point format field fmt is encoded as shown in .,non_CSR_parameter,range,high,False, +chunk_a84ac5e3,src/unpriv/f-st-ext.adoc,196,"Preamble > ""F"" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Computational Instructions",It is set to S (00) for all instructions in the F extension.,unknown,unknown,high,False, +chunk_ff1dc099,src/unpriv/f-st-ext.adoc,211,"Preamble > ""F"" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Computational Instructions",All floating-point operations that perform rounding can select the rounding mode using the rm field with the encoding shown in .,unknown,enum,high,False, +chunk_0d0ae83c,src/unpriv/f-st-ext.adoc,216,"Preamble > ""F"" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Computational Instructions","Floating-point minimum-number and maximum-number instructions FMIN.S and FMAX.S write, respectively, the smaller or larger of rs1 and rs2 to rd.",unknown,range,high,False, +chunk_43317650,src/unpriv/f-st-ext.adoc,216,"Preamble > ""F"" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Computational Instructions","For the purposes of these instructions only, the value −0.0 is considered to be less than the value +0.0.",unknown,range,high,False, +chunk_d32b33b7,src/unpriv/f-st-ext.adoc,227,"Preamble > ""F"" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Computational Instructions","Floating-point fused multiply-add instructions require a new standard instruction format. R4-type instructions specify three source registers (rs1, rs2, and rs3) and a destination register (rd).",unknown,unknown,high,False, +chunk_3ba124e7,src/unpriv/f-st-ext.adoc,227,"Preamble > ""F"" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Computational Instructions",This format is only used by the floating-point fused multiply-add instructions.,unknown,unknown,high,False, +chunk_5d1cc062,src/unpriv/f-st-ext.adoc,231,"Preamble > ""F"" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Computational Instructions","FMADD.S multiplies the values in rs1 and rs2, adds the value in rs3, and writes the final result to rd. FMADD.S computes (rs1×rs2)+rs3.",unknown,unknown,high,False, +chunk_7d1ddcab,src/unpriv/f-st-ext.adoc,236,"Preamble > ""F"" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Computational Instructions","FMSUB.S multiplies the values in rs1 and rs2, subtracts the value in rs3, and writes the final result to rd. FMSUB.S computes (rs1×rs2)−rs3.",unknown,unknown,high,False, +chunk_2af17f24,src/unpriv/f-st-ext.adoc,240,"Preamble > ""F"" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Computational Instructions","FNMSUB.S multiplies the values in rs1 and rs2, negates the product, adds the value in rs3, and writes the final result to rd. FNMSUB.S computes −(rs1×rs2)+rs3.",unknown,unknown,high,False, +chunk_f2d14872,src/unpriv/f-st-ext.adoc,243,"Preamble > ""F"" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Computational Instructions","FNMADD.S multiplies the values in rs1 and rs2, negates the product, subtracts the value in rs3, and writes the final result to rd. FNMADD.S computes −(rs1×rs2)−rs3.",unknown,unknown,high,False, +chunk_757afb3e,src/unpriv/f-st-ext.adoc,250,"Preamble > ""F"" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Computational Instructions","The fused multiply-add instructions must set the invalid operation exception flag when the multiplicands are {inf} and zero, even when the addend is a quiet NaN.",non_CSR_parameter,binary,very_high,False, +chunk_bad21167,src/unpriv/f-st-ext.adoc,256,"Preamble > ""F"" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Conversion and Move Instructions","Floating-point-to-integer and integer-to-floating-point conversion instructions are encoded in the OP-FP major opcode space. FCVT.W.S or FCVT.L.S converts a floating-point number in floating-point register rs1 to a signed 32-bit or 64-bit integer, respectively, in integer register rd. FCVT.S.W or FCVT.S.L converts a 32-bit or 64-bit signed integer, respectively, in integer register rs1 into a floating-point number in floating-point register rd. FCVT.WU.S, FCVT.LU.S, FCVT.S.WU, and FCVT.S.LU variants convert to or from unsigned integer values.",non_CSR_parameter,range,high,False, +chunk_b7d1643a,src/unpriv/f-st-ext.adoc,256,"Preamble > ""F"" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Conversion and Move Instructions","For XLEN>32, FCVT.W[U].S sign-extends the 32-bit result to the destination register width. FCVT.L[U].S and FCVT.S.L[U] are RV64-only instructions.",non_CSR_parameter,range,high,False, +chunk_d13667ad,src/unpriv/f-st-ext.adoc,256,"Preamble > ""F"" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Conversion and Move Instructions","If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set. gives the range of valid inputs for FCVT.int.S and the behavior for invalid inputs.",unknown,unknown,high,False, +chunk_72f7ad4c,src/unpriv/f-st-ext.adoc,272,"Preamble > ""F"" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Conversion and Move Instructions","All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, `x0`, which will never set any exception flags.",unknown,enum,high,False, +chunk_70285fd6,src/unpriv/f-st-ext.adoc,286,"Preamble > ""F"" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Conversion and Move Instructions",|Maximum valid input (after rounding) |2^31^−1 |2^32^−1 |2^63^−1 |2^64^−1,unknown,range,high,False, +chunk_81f8baf0,src/unpriv/f-st-ext.adoc,289,"Preamble > ""F"" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Conversion and Move Instructions",|Output for out-of-range negative input |−2^31^ |0 |−2^63^ |0,unknown,unknown,high,False, +chunk_b943541a,src/unpriv/f-st-ext.adoc,292,"Preamble > ""F"" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Conversion and Move Instructions",|Output for -{inf} |−2^31^ |0 |−2^63^ |0,unknown,unknown,high,False, +chunk_75c9707b,src/unpriv/f-st-ext.adoc,295,"Preamble > ""F"" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Conversion and Move Instructions",|Output for out-of-range positive input |2^31^−1 |2^32^−1 |2^63^−1 |2^64^−1,unknown,unknown,high,False, +chunk_0b976431,src/unpriv/f-st-ext.adoc,298,"Preamble > ""F"" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Conversion and Move Instructions",|Output for +{inf} or NaN |2^31^−1 |2^32^−1 |2^63^−1 |2^64^−1 |,unknown,unknown,high,False, +chunk_6e497bf8,src/unpriv/f-st-ext.adoc,302,"Preamble > ""F"" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Conversion and Move Instructions",All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set.,unknown,unknown,high,False, +chunk_d4a1c607,src/unpriv/f-st-ext.adoc,311,"Preamble > ""F"" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Conversion and Move Instructions","Floating-point to floating-point sign-injection instructions, FSGNJ.S, FSGNJN.S, and FSGNJX.S, produce a result that takes all bits except the sign bit from rs1.",unknown,unknown,high,False, +chunk_681d4ebc,src/unpriv/f-st-ext.adoc,311,"Preamble > ""F"" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Conversion and Move Instructions","For FSGNJ, the result's sign bit is rs2's sign bit; for FSGNJN, the result's sign bit is the opposite of rs2's sign bit; and for FSGNJX, the sign bit is the XOR of the sign bits of rs1 and rs2.",unknown,unknown,high,False, +chunk_9f3245bb,src/unpriv/f-st-ext.adoc,311,"Preamble > ""F"" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Conversion and Move Instructions","Sign-injection instructions do not set floating-point exception flags, nor do they canonicalize NaNs.",unknown,unknown,high,False, +chunk_92952ae5,src/unpriv/f-st-ext.adoc,326,"Preamble > ""F"" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Conversion and Move Instructions",Instructions are provided to move bit patterns between the floating-point and integer registers. FMV.X.W moves the single-precision value in floating-point register rs1 represented in the IEEE 754-2008 encoding to the lower 32 bits of integer register rd.,non_CSR_parameter,range,high,False, +chunk_11c338ae,src/unpriv/f-st-ext.adoc,326,"Preamble > ""F"" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Conversion and Move Instructions","The bits are not modified in the transfer, and in particular, the payloads of non-canonical NaNs are preserved.",unknown,unknown,high,False, +chunk_785a50a5,src/unpriv/f-st-ext.adoc,326,"Preamble > ""F"" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Conversion and Move Instructions","For RV64, the higher 32 bits of the destination register are filled with copies of the floating-point number's sign bit.",non_CSR_parameter,range,high,False, +chunk_810b099e,src/unpriv/f-st-ext.adoc,335,"Preamble > ""F"" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Conversion and Move Instructions",FMV.W.X moves the single-precision value encoded in the IEEE 754-2008 encoding from the lower 32 bits of integer register rs1 to the floating-point register rd.,non_CSR_parameter,range,high,False, +chunk_f2d4eb2b,src/unpriv/f-st-ext.adoc,335,"Preamble > ""F"" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Conversion and Move Instructions","The bits are not modified in the transfer, and in particular, the payloads of non-canonical NaNs are preserved.",unknown,unknown,high,False, +chunk_80a974f2,src/unpriv/f-st-ext.adoc,354,"Preamble > ""F"" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Compare Instructions","FLT.S and FLE.S perform what IEEE 754-2008 refers to as signaling comparisons: that is, they set the invalid operation exception flag if either input is NaN. FEQ.S performs a quiet comparison: it only sets the invalid operation exception flag if either input is a signaling NaN.",unknown,enum,high,False, +chunk_f2689ca4,src/unpriv/f-st-ext.adoc,367,"Preamble > ""F"" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Classify Instruction",The FCLASS.S instruction examines the value in floating-point register rs1 and writes to integer register rd a 10-bit mask that indicates the class of the floating-point number.,non_CSR_parameter,range,high,False, +chunk_1dac62c1,src/unpriv/f-st-ext.adoc,367,"Preamble > ""F"" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Classify Instruction",The format of the mask is described in .,unknown,unknown,high,False, +chunk_42a5c06a,src/unpriv/f-st-ext.adoc,367,"Preamble > ""F"" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Classify Instruction",The corresponding bit in rd will be set if the property is true and clear otherwise.,unknown,unknown,high,False, +chunk_f826b56f,src/unpriv/f-st-ext.adoc,367,"Preamble > ""F"" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Classify Instruction",All other bits in rd are cleared.,unknown,unknown,high,False, +chunk_29703e4e,src/unpriv/m-st-ext.adoc,17,"Preamble > ""M"" Extension for Integer Multiplication and Division, Version 2.0 > Multiplication Operations","MUL performs an XLEN-bit×XLEN-bit multiplication of `rs1` by `rs2` and places the lower XLEN bits in the destination register. MULH, MULHU, and MULHSU perform the same multiplication but return the upper XLEN bits of the full 2×XLEN-bit product, for signed×signed, unsigned×unsigned, and `rs1`×unsigned `rs2` multiplication.",unknown,range,high,False, +chunk_3835b90b,src/unpriv/m-st-ext.adoc,17,"Preamble > ""M"" Extension for Integer Multiplication and Division, Version 2.0 > Multiplication Operations","If both the high and low bits of the same product are required, then the recommended code sequence is: `MULH[[S]U] rdh, rs1, rs2; MUL rdl, rs1, rs2` (source register specifiers must be in same order and `rdh` cannot be the same as `rs1` or `rs2`).",non_CSR_parameter,binary,very_high,False, +chunk_4e75dc79,src/unpriv/m-st-ext.adoc,25,"Preamble > ""M"" Extension for Integer Multiplication and Division, Version 2.0 > Multiplication Operations","MULW is an RV64 instruction that multiplies the lower 32 bits of the source registers, placing the sign extension of the lower 32 bits of the result into the destination register.",non_CSR_parameter,range,high,False, +chunk_e59c8ef2,src/unpriv/m-st-ext.adoc,37,"Preamble > ""M"" Extension for Integer Multiplication and Division, Version 2.0 > Multiplication Operations > Division Operations","DIV and DIVU perform an XLEN bits by XLEN bits signed and unsigned integer division of `rs1` by `rs2`, rounding towards zero. REM and REMU provide the remainder of the corresponding division operation.",unknown,range,high,False, +chunk_c6dabebb,src/unpriv/m-st-ext.adoc,42,"Preamble > ""M"" Extension for Integer Multiplication and Division, Version 2.0 > Multiplication Operations > Division Operations","If both the quotient and remainder are required from the same division, the recommended code sequence is: `DIV[U] rdq, rs1, rs2; REM[U] rdr,` `rs1, rs2` (`rdq` cannot be the same as `rs1` or `rs2`).",unknown,unknown,high,False, +chunk_553e68a0,src/unpriv/m-st-ext.adoc,48,"Preamble > ""M"" Extension for Integer Multiplication and Division, Version 2.0 > Multiplication Operations > Division Operations","DIVW and DIVUW are RV64 instructions that divide the lower 32 bits of `rs1` by the lower 32 bits of `rs2`, treating them as signed and unsigned integers, placing the 32-bit quotient in `rd`, sign-extended to 64 bits. REMW and REMUW are RV64 instructions that provide the corresponding signed and unsigned remainder operations.",non_CSR_parameter,range,high,False, +chunk_aaba239b,src/unpriv/m-st-ext.adoc,48,"Preamble > ""M"" Extension for Integer Multiplication and Division, Version 2.0 > Multiplication Operations > Division Operations","Both REMW and REMUW always sign-extend the 32-bit result to 64 bits, including on a divide by zero.",non_CSR_parameter,range,high,False, +chunk_d863e630,src/unpriv/m-st-ext.adoc,57,"Preamble > ""M"" Extension for Integer Multiplication and Division, Version 2.0 > Multiplication Operations > Division Operations","The quotient of division by zero has all bits set, and the remainder of division by zero equals the dividend.",unknown,unknown,high,False, +chunk_6d42e327,src/unpriv/m-st-ext.adoc,57,"Preamble > ""M"" Extension for Integer Multiplication and Division, Version 2.0 > Multiplication Operations > Division Operations",Signed division overflow occurs only when the most-negative integer is divided by −1.,unknown,unknown,high,False, +chunk_fe45fafe,src/unpriv/mm-explanatory.adoc,3,Preamble > RVWMO Explanatory Material,This appendix should be treated as commentary; all normative material is provided in and in the rest of the main body of the ISA specification.,non_CSR_parameter,enum,medium,False, +chunk_3d7fb806,src/unpriv/mm-explanatory.adoc,36,Preamble > RVWMO Explanatory Material > Why RVWMO?,"To facilitate the porting of code from other architectures, some hardware implementations may choose to implement the Ztso extension, which provides stricter RVTSO ordering semantics by default.",non_CSR_parameter,enum,high,False, +chunk_c9d8eaf3,src/unpriv/mm-explanatory.adoc,36,Preamble > RVWMO Explanatory Material > Why RVWMO?,"Each implementation must therefore choose whether to prioritize compatibility with RVTSO code (e.g., to facilitate porting from x86) or whether to instead prioritize compatibility with other RISC-V cores implementing RVWMO.",non_CSR_parameter,enum,very_high,False, +chunk_57e8e6f4,src/unpriv/mm-explanatory.adoc,47,Preamble > RVWMO Explanatory Material > Why RVWMO?,"However, these fences must remain present in the code if compatibility with non-Ztso implementations is desired.",SW_rule,binary,very_high,False, +chunk_266ffadd,src/unpriv/mm-explanatory.adoc,57,Preamble > RVWMO Explanatory Material > Why RVWMO? > Litmus Tests,"As a convention for this figure and for all figures that follow in this chapter, we assume that `s0-s2` are pre-set to the same value in all harts and that `s0` holds the address labeled `x`, `s1` holds `y`, and `s2` holds `z`, where `x`, `y`, and `z` are disjoint memory locations aligned to 8 byte boundaries.",non_CSR_parameter,range,medium,False, +chunk_15fcb8c9,src/unpriv/mm-explanatory.adoc,97,Preamble > RVWMO Explanatory Material > Why RVWMO? > Litmus Tests,"However, in this example, the final value of `a0` in Hart 0 will never be 1 or 3; intuitively, the value 1 will no longer be visible at the time the load executes, and the value 3 will not yet be visible by the time the load executes.",unknown,enum,high,False, +chunk_398406bc,src/unpriv/mm-explanatory.adoc,171,Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Preserved Program Order and Global Memory Order,Preserved program order represents the subset of program order that must be respected within the global memory order.,non_CSR_parameter,enum,very_high,False, +chunk_e5c3042b,src/unpriv/mm-explanatory.adoc,171,Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Preserved Program Order and Global Memory Order,"Conceptually, events from the same hart that are ordered by preserved program order must appear in that order from the perspective of other harts and/or observers.",non_CSR_parameter,enum,very_high,False, +chunk_08477fb4,src/unpriv/mm-explanatory.adoc,171,Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Preserved Program Order and Global Memory Order,"Events from the same hart that are not ordered by preserved program order, on the other hand, may appear reordered from the perspective of other harts and/or observers.",non_CSR_parameter,enum,medium,False, +chunk_b646fb5e,src/unpriv/mm-explanatory.adoc,179,Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Preserved Program Order and Global Memory Order,"Informally, the global memory order represents the order in which loads and stores perform.",unknown,unknown,medium,False, +chunk_837804ad,src/unpriv/mm-explanatory.adoc,179,Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Preserved Program Order and Global Memory Order,"In this sense, the global memory order also represents the contribution of the coherence protocol and/or the rest of the memory system to interleave the (possibly reordered) memory accesses being issued by each hart into a single total order agreed upon by all harts.",unknown,unknown,medium,False, +chunk_200fa231,src/unpriv/mm-explanatory.adoc,191,Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Preserved Program Order and Global Memory Order,The order in which loads perform does not always directly correspond to the relative age of the values those two loads return.,unknown,unknown,medium,False, +chunk_0de93172,src/unpriv/mm-explanatory.adoc,191,Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Preserved Program Order and Global Memory Order,This discrepancy captures (among other things) the reordering effects of buffering placed between the core and memory.,unknown,unknown,medium,False, +chunk_91d9bcf7,src/unpriv/mm-explanatory.adoc,191,Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Preserved Program Order and Global Memory Order,"To account for this, at the time each load performs, the value it returns is determined by the load value axiom, not just strictly by determining the most recent store to the same address in the global memory order, as described below.",non_CSR_parameter,unknown,medium,False, +chunk_bffe76cd,src/unpriv/mm-explanatory.adoc,221,Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Load value axiom,Preserved program order is not required to respect the ordering of a store followed by a load to an overlapping address.,non_CSR_parameter,enum,medium,False, +chunk_47e30fde,src/unpriv/mm-explanatory.adoc,221,Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Load value axiom,"Informally, the load may perform (return a value) by forwarding from the store while the store is still in the store buffer, and hence before the store itself performs (writes back to globally visible memory).",non_CSR_parameter,enum,medium,False, +chunk_8474558f,src/unpriv/mm-explanatory.adoc,230,Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Load value axiom,"When running this program on an implementation with store buffers, it is possible to arrive at the final outcome `a0=1, a1=0, a2=1, a3=0` as follows:",unknown,unknown,high,False, +chunk_7609f830,src/unpriv/mm-explanatory.adoc,270,Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Load value axiom,"Therefore, the memory model must be able to account for this behavior.",non_CSR_parameter,enum,very_high,False, +chunk_7ae2cdf8,src/unpriv/mm-explanatory.adoc,272,Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Load value axiom,"To put it another way, suppose the definition of preserved program order did include the following hypothetical rule: memory access a precedes memory access b in preserved program order (and hence also in the global memory order) if a precedes b in program order and a and b are accesses to the same memory location, a is a write, and b is a read.",unknown,unknown,high,False, +chunk_81544ef3,src/unpriv/mm-explanatory.adoc,281,Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Load value axiom,"Otherwise, if (e) preceded (d), then (d) would be required to return the value 1. (This is a perfectly legal execution; it's just not the one in question) * (e) precedes (f): by rule X * (f) precedes (h): by rule * (h) precedes (a): by the load value axiom, as above.",unknown,unknown,high,False, +chunk_6b9da712,src/unpriv/mm-explanatory.adoc,290,Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Load value axiom,"The global memory order must be a total order and cannot be cyclic, because a cycle would imply that every event in the cycle happens before itself, which is impossible.",non_CSR_parameter,enum,very_high,False, +chunk_f63968df,src/unpriv/mm-explanatory.adoc,297,Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Load value axiom,"Nevertheless, even if (b) precedes (a) and/or (f) precedes (e) in the global memory order, the only sensible possibility in this example is for (b) to return the value written by (a), and likewise for (f) and (e).",unknown,unknown,high,False, +chunk_257d9110,src/unpriv/mm-explanatory.adoc,361,Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Atomicity axiom,"If r and w are paired load and store operations generated by aligned LR and SC instructions in a hart h, s is a store to byte x, and r returns a value written by s, then s must precede w in the global memory order, and there can be no store from a hart other than h to byte x following s and preceding w in the global memory order.",non_CSR_parameter,binary,very_high,False, +chunk_a1876c4c,src/unpriv/mm-explanatory.adoc,371,Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Atomicity axiom,"Unlike architectures such as TSO, RISC-V atomics under RVWMO do not impose any ordering requirements by default.",unknown,unknown,high,False, +chunk_2521ad7a,src/unpriv/mm-explanatory.adoc,376,Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Atomicity axiom,"These conceptually behave differently, in the following way. LR/SC behave as if the old value is brought up to the core, modified, and written back to memory, all while a reservation is held on that memory location. AMOs on the other hand conceptually behave as if they are performed directly in memory. AMOs are therefore inherently atomic, while LR/SC pairs are atomic in the slightly different sense that the memory location in question will not be modified by another hart during the time the original hart holds the reservation.",unknown,unknown,high,False, +chunk_87d77c1b,src/unpriv/mm-explanatory.adoc,418,Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Atomicity axiom,"Likewise, scenarios in which stores from the same hart between an LR/SC pair actually overlap the memory location(s) referenced by the LR or SC are expected to be rare compared to scenarios where the intervening store may simply fall onto the same cache line.",non_CSR_parameter,enum,medium,False, +chunk_37f42644,src/unpriv/mm-explanatory.adoc,429,Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Progress axiom,[IMPORTANT] : No memory operation may be preceded in the global memory order by an infinite sequence of other memory operations.,non_CSR_parameter,enum,medium,False, +chunk_ae0b1a68,src/unpriv/mm-explanatory.adoc,448,Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Progress axiom,Implementations with non-coherent caches may have to provide some other mechanism to ensure the eventual visibility of all stores (or successors thereof) to all harts.,non_CSR_parameter,enum,medium,False, +chunk_228e1b1a,src/unpriv/mm-explanatory.adoc,457,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)",Same-address orderings where the latter is a store are straightforward: a load or store can never be reordered with a later store to an overlapping memory location.,unknown,unknown,medium,False, +chunk_d31b3468,src/unpriv/mm-explanatory.adoc,457,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)","From a microarchitecture perspective, generally speaking, it is difficult or impossible to undo a speculatively reordered store if the speculation turns out to be invalid, so such behavior is simply disallowed by the model.",unknown,unknown,high,False, +chunk_da5feae2,src/unpriv/mm-explanatory.adoc,457,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)","Same-address orderings from a store to a later load, on the other hand, do not need to be enforced.",unknown,unknown,medium,False, +chunk_e79a418f,src/unpriv/mm-explanatory.adoc,457,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)","As discussed in , this reflects the observable behavior of implementations that forward values from buffered stores to later loads.",unknown,unknown,medium,False, +chunk_800783f0,src/unpriv/mm-explanatory.adoc,469,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)",Same-address load-load ordering requirements are far more subtle.,unknown,unknown,medium,False, +chunk_22c11ce5,src/unpriv/mm-explanatory.adoc,469,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)",The basic requirement is that a younger load must not return a value that is older than a value returned by an older load in the same hart to the same address.,non_CSR_parameter,enum,very_high,False, +chunk_3d208768,src/unpriv/mm-explanatory.adoc,469,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)","This is often known as ""CoRR"" (Coherence for Read-Read pairs), or as part of a broader ""coherence"" or ""sequential consistency per location"" requirement.",unknown,unknown,medium,False, +chunk_77dc127d,src/unpriv/mm-explanatory.adoc,469,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)","Some architectures in the past have relaxed same-address load-load ordering, but in hindsight this is generally considered to complicate the programming model too much, and so RVWMO requires CoRR ordering to be enforced.",non_CSR_parameter,unknown,medium,False, +chunk_f748fd84,src/unpriv/mm-explanatory.adoc,486,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)","[float=""center"",align=""center"",cols="".^1a,.^1a"",frame=""none"",grid=""none"",options=""noheader""] .Litmus test MP+fence.w.w+fre-rfi-addr (outcome permitted) | | ! 2+!Hart 0 2+^!Hart 1 !!li t1, 1 !!li t2, 2 >!(a) !sw t1,0(s0) >!(d) !lw a0,0(s1) >!(b) !fence w, w >!(e) !sw t2,0(s1) >!(c) !sw t1,0(s1) >!(f) !lw a1,0(s1) ! ! >!(g) !xor t3,a1,a1 ! ! >!(h) !add s0,s0,t3 ! ! >!(i) !lw a2,0(s0) 4+^!Outcome: `a0=1`, `a1=2`, `a2=0` ! | ! //a! graphviz::images/graphviz/litmusmpfencewwfrirfiaddr.txt[] a! image::graphviz/litmusmpfencewwfrirfiaddr.png[] ! | Consider the litmus test of , which is one particular instance of the more general ""fri-rfi"" pattern.",SW_rule,unknown,medium,False, +chunk_8c9f8eab,src/unpriv/mm-explanatory.adoc,514,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)","From a microarchitectural perspective, outcome `a0=1`, `a1=2`, `a2=0` is legal (as are various other less subtle outcomes).",unknown,unknown,medium,False, +chunk_cced40b8,src/unpriv/mm-explanatory.adoc,514,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)","Intuitively, the following would produce the outcome in question:",unknown,unknown,medium,False, +chunk_2a826d86,src/unpriv/mm-explanatory.adoc,518,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)","(d) stalls (for whatever reason; perhaps it's stalled waiting for some other preceding instruction) * (e) executes and enters the store buffer (but does not yet drain to memory) * (f) executes and forwards from (e) in the store buffer * (g), (h), and (i) execute * (a) executes and drains to memory, (b) executes, and (c) executes and drains to memory * (d) unstalls and executes * (e) drains from the store buffer to memory",unknown,unknown,medium,False, +chunk_4cbc9dc8,src/unpriv/mm-explanatory.adoc,529,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)","This corresponds to a global memory order of (f), (i), (a), (c), (d), (e).",unknown,unknown,medium,False, +chunk_a2489796,src/unpriv/mm-explanatory.adoc,529,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)","Therefore, this execution is legal and does not violate the CoRR requirements.",unknown,unknown,medium,False, +chunk_b7c1e039,src/unpriv/mm-explanatory.adoc,534,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)","Likewise, if two back-to-back loads return the values written by the same store, then they may also appear out-of-order in the global memory order without violating CoRR.",non_CSR_parameter,enum,high,False, +chunk_8ca57382,src/unpriv/mm-explanatory.adoc,566,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)",Consider the litmus test of .,unknown,unknown,medium,False, +chunk_3a31cbf7,src/unpriv/mm-explanatory.adoc,566,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)","The outcome `a0=1`, `a1=v`, `a2=v`, `a3=0` (where v is some value written by another hart) can be observed by allowing (g) and (h) to be reordered.",unknown,unknown,medium,False, +chunk_1a1ff413,src/unpriv/mm-explanatory.adoc,566,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)","The global memory order corresponding to this execution would be (h),(k),(a),(c),(d),(g).",unknown,unknown,medium,False, +chunk_32d525f8,src/unpriv/mm-explanatory.adoc,578,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)",Executions of the test in in which `a1` does not equal `a2` do in fact require that (g) appears before (h) in the global memory order.,unknown,range,medium,False, +chunk_0dae7f9f,src/unpriv/mm-explanatory.adoc,578,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)","Therefore, forbids this CoRR violation from occurring.",unknown,unknown,medium,False, +chunk_ad8310f1,src/unpriv/mm-explanatory.adoc,578,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)","As such, strikes a careful balance between enforcing CoRR in all cases while simultaneously being weak enough to permit ""RSW"" and ""fri-rfi"" patterns that commonly appear in real microarchitectures.",unknown,unknown,medium,False, +chunk_716cfd0d,src/unpriv/mm-explanatory.adoc,589,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)","There is one more overlapping-address rule: simply states that a value cannot be returned from an AMO or SC to a subsequent load until the AMO or SC has (in the case of the SC, successfully) performed globally.",unknown,unknown,high,False, +chunk_0c374289,src/unpriv/mm-explanatory.adoc,589,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)",This follows somewhat naturally from the conceptual view that both AMOs and SC instructions are meant to be performed atomically in memory.,unknown,unknown,medium,False, +chunk_683d9840,src/unpriv/mm-explanatory.adoc,589,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)","However, notably, states that hardware may not even non-speculatively forward the value being stored by an AMOSWAP to a subsequent load, even though for AMOSWAP that store value is not actually semantically dependent on the previous value in memory, as is the case for the other AMOs.",non_CSR_parameter,enum,medium,False, +chunk_93fa0c09,src/unpriv/mm-explanatory.adoc,589,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)",The same holds true even when forwarding from SC store values that are not semantically dependent on the value returned by the paired LR.,unknown,unknown,high,False, +chunk_22622c1d,src/unpriv/mm-explanatory.adoc,603,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)",The three PPO rules above also apply when the memory accesses in question only overlap partially.,unknown,unknown,high,False, +chunk_9ce06704,src/unpriv/mm-explanatory.adoc,603,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)","When misaligned memory accesses are being used, the overlapping-address PPO rules apply to each of the component memory accesses independently.",unknown,unknown,high,False, +chunk_f5cfc595,src/unpriv/mm-explanatory.adoc,614,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Fences (<>)",[IMPORTANT] Rule : There is a FENCE instruction that orders a before b,SW_rule,unknown,medium,False, +chunk_8b91df59,src/unpriv/mm-explanatory.adoc,619,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Fences (<>)","By default, the FENCE instruction ensures that all memory accesses from instructions preceding the fence in program order (the ""predecessor set"") appear earlier in the global memory order than memory accesses from instructions appearing after the fence in program order (the ""successor set"").",SW_rule,unknown,high,False, +chunk_5a85c353,src/unpriv/mm-explanatory.adoc,619,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Fences (<>)","However, fences can optionally further restrict the predecessor set and/or the successor set to a smaller set of memory accesses in order to provide some speedup.",SW_rule,unknown,medium,False, +chunk_7feda3a7,src/unpriv/mm-explanatory.adoc,631,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Fences (<>)","The FENCE encoding currently has nine non-trivial combinations of the four bits PR, PW, SR, and SW, plus one extra encoding FENCE.TSO which facilitates mapping of ""acquire+release"" or RVTSO semantics.",SW_rule,enum,medium,False, +chunk_b07961e7,src/unpriv/mm-explanatory.adoc,631,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Fences (<>)",The remaining seven combinations have empty predecessor and/or successor sets and hence are no-ops.,unknown,unknown,medium,False, +chunk_26eea979,src/unpriv/mm-explanatory.adoc,645,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Fences (<>)","FENCE instructions using other combinations of PR, PW, SR, and SW are not normally used in the Linux or C++ memory models but are otherwise well defined.",SW_rule,unknown,medium,False, +chunk_3325b338,src/unpriv/mm-explanatory.adoc,649,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Fences (<>)","Fences in RISC-V are not cumulative, as they are in some non-multi-copy-atomic memory models.",SW_rule,unknown,medium,False, +chunk_e8541e2a,src/unpriv/mm-explanatory.adoc,657,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Explicit Synchronization (<>)",[IMPORTANT] : a has an acquire annotation,unknown,unknown,medium,False, +chunk_2e91cc08,src/unpriv/mm-explanatory.adoc,668,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Explicit Synchronization (<>)","An acquire operation, as would be used at the start of a critical section, requires all memory operations following the acquire in program order to also follow the acquire in the global memory order.",non_CSR_parameter,unknown,medium,False, +chunk_e7e47582,src/unpriv/mm-explanatory.adoc,668,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Explicit Synchronization (<>)","Acquire ordering can be enforced in one of two ways: with an acquire annotation, which enforces ordering with respect to just the synchronization variable itself, or with a FENCE R,RW, which enforces ordering with respect to all previous loads.",SW_rule,enum,medium,False, +chunk_7c3dd790,src/unpriv/mm-explanatory.adoc,696,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Explicit Synchronization (<>)","However, assuming `a0`, `a1`, and `a2` point to different memory locations, the loads and stores in the critical section may or may not appear after the ""Arbitrary unrelated load"" at the beginning of the example in the global memory order.",non_CSR_parameter,enum,high,False, +chunk_8bf019e7,src/unpriv/mm-explanatory.adoc,724,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Explicit Synchronization (<>)","Now, consider the alternative in .",unknown,unknown,medium,False, +chunk_46c704d1,src/unpriv/mm-explanatory.adoc,724,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Explicit Synchronization (<>)","In this case, even though the AMOSWAP does not enforce ordering with an aq bit, the fence nevertheless enforces that the acquire AMOSWAP appears earlier in the global memory order than all loads and stores in the critical section.",SW_rule,unknown,medium,False, +chunk_cd4a3926,src/unpriv/mm-explanatory.adoc,737,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Explicit Synchronization (<>)","Release orderings work exactly the same as acquire orderings, just in the opposite direction.",unknown,unknown,medium,False, +chunk_e4e24863,src/unpriv/mm-explanatory.adoc,737,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Explicit Synchronization (<>)",Release semantics require all loads and stores preceding the release operation in program order to also precede the release operation in the global memory order.,unknown,unknown,medium,False, +chunk_3199643c,src/unpriv/mm-explanatory.adoc,737,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Explicit Synchronization (<>)","Just as for acquire semantics, release semantics can be enforced using release annotations or with a FENCE RW,W operation.",SW_rule,unknown,medium,False, +chunk_42af797c,src/unpriv/mm-explanatory.adoc,737,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Explicit Synchronization (<>)","Using the same examples, the ordering between the loads and stores in the critical section and the ""Arbitrary unrelated store"" at the end of the code snippet is enforced only by the FENCE RW,W in , not by the rl in .",SW_rule,unknown,medium,False, +chunk_f5f2f575,src/unpriv/mm-explanatory.adoc,750,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Explicit Synchronization (<>)","With RCpc annotations alone, store-release-to-load-acquire ordering is not enforced.",unknown,unknown,medium,False, +chunk_20df72ac,src/unpriv/mm-explanatory.adoc,750,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Explicit Synchronization (<>)",This facilitates the porting of code written under the TSO and/or RCpc memory models.,unknown,unknown,medium,False, +chunk_278d847d,src/unpriv/mm-explanatory.adoc,750,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Explicit Synchronization (<>)","To enforce store-release-to-load-acquire ordering, the code must use store-release-RCsc and load-acquire-RCsc operations so that PPO rule 7 applies. RCpc alone is sufficient for many use cases in C/C\++ but is insufficient for many other use cases in C/C++, Java, and Linux, to name just a few examples; see for details.",non_CSR_parameter,enum,very_high,False, +chunk_2ddf8df0,src/unpriv/mm-explanatory.adoc,759,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Explicit Synchronization (<>)",PPO rule 8 indicates that an SC must appear after its paired LR in the global memory order.,non_CSR_parameter,enum,very_high,False, +chunk_2d970656,src/unpriv/mm-explanatory.adoc,759,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Explicit Synchronization (<>)",This will follow naturally from the common use of LR/SC to perform an atomic read-modify-write operation due to the inherent data dependency.,unknown,unknown,medium,False, +chunk_784281ac,src/unpriv/mm-explanatory.adoc,759,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Explicit Synchronization (<>)","However, PPO rule 8 also applies even when the value being stored does not syntactically depend on the value returned by the paired LR.",unknown,unknown,high,False, +chunk_88c2cdc4,src/unpriv/mm-explanatory.adoc,772,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)",[IMPORTANT] : b has a syntactic address dependency on a,unknown,unknown,medium,False, +chunk_775577a1,src/unpriv/mm-explanatory.adoc,779,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)",": b is a store, and b has a syntactic control dependency on a",unknown,unknown,medium,False, +chunk_5cae2326,src/unpriv/mm-explanatory.adoc,782,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)",Dependencies from a load to a later memory operation in the same hart are respected by the RVWMO memory model.,unknown,unknown,medium,False, +chunk_a92bd0dd,src/unpriv/mm-explanatory.adoc,782,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)","The Alpha memory model was notable for choosing not to enforce the ordering of such dependencies, but most modern hardware and software memory models consider allowing dependent instructions to be reordered too confusing and counterintuitive.",SW_rule,unknown,medium,False, +chunk_1bd015c1,src/unpriv/mm-explanatory.adoc,782,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)","Furthermore, modern code sometimes intentionally uses such dependencies as a particularly lightweight ordering enforcement mechanism.",unknown,unknown,medium,False, +chunk_b66d9a31,src/unpriv/mm-explanatory.adoc,791,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)",Instructions are said to carry dependencies from their source register(s) to their destination register(s) whenever the value written into each destination register is a function of the source register(s).,unknown,unknown,medium,False, +chunk_46b5fa49,src/unpriv/mm-explanatory.adoc,791,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)","For most instructions, this means that the destination register(s) carry a dependency from all source register(s).",unknown,unknown,medium,False, +chunk_0fa48a47,src/unpriv/mm-explanatory.adoc,791,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)","In the case of memory instructions, the value written into the destination register ultimately comes from the memory system rather than from the source register(s) directly, and so this breaks the chain of dependencies carried from the source register(s).",unknown,unknown,high,False, +chunk_81c0005f,src/unpriv/mm-explanatory.adoc,791,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)","In the case of unconditional jumps, the value written into the destination register comes from the current `pc` (which is never considered a source register by the memory model), and so likewise, JALR (the only jump with a source register) does not carry a dependency from rs1 to rd.",unknown,unknown,high,False, +chunk_b9271c44,src/unpriv/mm-explanatory.adoc,822,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)","Like other modern memory models, the RVWMO memory model uses syntactic rather than semantic dependencies.",unknown,unknown,medium,False, +chunk_1740af5c,src/unpriv/mm-explanatory.adoc,822,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)","In other words, this definition depends on the identities of the registers being accessed by different instructions, not the actual contents of those registers.",non_CSR_parameter,unknown,medium,False, +chunk_bcadfec1,src/unpriv/mm-explanatory.adoc,822,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)","This means that an address, control, or data dependency must be enforced even if the calculation could seemingly be `optimized away`.",non_CSR_parameter,binary,very_high,False, +chunk_94e5d203,src/unpriv/mm-explanatory.adoc,822,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)",This choice ensures that RVWMO remains compatible with code that uses these false syntactic dependencies as a lightweight ordering mechanism.,unknown,unknown,medium,False, +chunk_f35d4f33,src/unpriv/mm-explanatory.adoc,848,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)",The benefit of using dependencies as a lightweight synchronization mechanism is that the ordering enforcement requirement is limited only to the specific two instructions in question.,unknown,unknown,medium,False, +chunk_ec01a702,src/unpriv/mm-explanatory.adoc,848,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)",Other non-dependent instructions may be freely reordered by aggressive implementations.,non_CSR_parameter,enum,medium,False, +chunk_49c76ffe,src/unpriv/mm-explanatory.adoc,848,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)","One alternative would be to use a load-acquire, but this would enforce ordering for the first load with respect to all subsequent instructions.",unknown,unknown,medium,False, +chunk_2a63edc0,src/unpriv/mm-explanatory.adoc,868,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)",Control dependencies behave differently from address and data dependencies in the sense that a control dependency always extends to all instructions following the original target in program order.,unknown,unknown,medium,False, +chunk_37c9b3a6,src/unpriv/mm-explanatory.adoc,868,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)","Consider the instruction at `next` will always execute, but the memory operation generated by that last instruction nevertheless still has a control dependency from the memory operation generated by the first instruction.",unknown,unknown,medium,False, +chunk_e48cf20c,src/unpriv/mm-explanatory.adoc,885,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)","Even though both branch outcomes have the same target, there is still a control dependency from the memory operation generated by the first instruction in this snippet to the memory operation generated by the last instruction.",unknown,unknown,medium,False, +chunk_c16fc9f0,src/unpriv/mm-explanatory.adoc,894,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)","However, since control, address, and data dependencies are defined over memory operations, and since an unsuccessful SC does not generate a memory operation, no order is enforced between unsuccessful SC and its dependent instructions.",unknown,unknown,medium,False, +chunk_6bc31ff4,src/unpriv/mm-explanatory.adoc,894,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)","Moreover, since SC is defined to carry dependencies from its source registers to rd only when the SC is successful, an unsuccessful SC has no effect on the global memory order.",unknown,unknown,high,False, +chunk_2fec39d2,src/unpriv/mm-explanatory.adoc,934,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)","In addition, the choice to respect dependencies originating at store-conditional instructions ensures that certain out-of-thin-air-like behaviors will be prevented.",unknown,unknown,medium,False, +chunk_5f5212cd,src/unpriv/mm-explanatory.adoc,934,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)",Suppose a hypothetical implementation could occasionally make some early guarantee that a store-conditional operation will succeed.,unknown,unknown,medium,False, +chunk_9632fb82,src/unpriv/mm-explanatory.adoc,934,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)","In this case, (c) could return 0 to `a2` early (before actually executing), allowing the sequence (d), (e), (f), (a), and then (b) to execute, and then (c) might execute (successfully) only at that point.",unknown,unknown,medium,False, +chunk_49f49f22,src/unpriv/mm-explanatory.adoc,948,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)",For example: a syntactic dependency between two `F` instructions via one of the `accumulating CSRs` in does not imply that the two `F` instructions must be executed in order.,CSR_controlled,enum,very_high,False, +chunk_13bc7288,src/unpriv/mm-explanatory.adoc,948,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)",Such a dependency would only serve to ultimately set up later a dependency from both `F` instructions to a later CSR instruction accessing the CSR flag in question.,CSR_controlled,enum,high,False, +chunk_d60de3c4,src/unpriv/mm-explanatory.adoc,962,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Pipeline Dependencies (<>)","[IMPORTANT] : b is a load, and there exists some store m between a and b in program order such that m has an address or data dependency on a, and b returns a value written by m",unknown,unknown,medium,False, +chunk_56dabc33,src/unpriv/mm-explanatory.adoc,969,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Pipeline Dependencies (<>)",": b is a store, and there exists some instruction m between a and b in program order such that m has an address dependency on a",unknown,unknown,medium,False, +chunk_c1d0bdd7,src/unpriv/mm-explanatory.adoc,996,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Pipeline Dependencies (<>)",PPO rules and reflect behaviors of almost all real processor pipeline implementations.,unknown,unknown,medium,False, +chunk_9e54dbae,src/unpriv/mm-explanatory.adoc,996,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Pipeline Dependencies (<>)",Rule states that a load cannot forward from a store until the address and data for that store are known.,unknown,unknown,medium,False, +chunk_3196163e,src/unpriv/mm-explanatory.adoc,996,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Pipeline Dependencies (<>)","Consider (f) cannot be executed until the data for (e) has been resolved, because (f) must return the value written by (e) (or by something even later in the global memory order), and the old value must not be clobbered by the write-back of (e) before (d) has had a chance to perform.",non_CSR_parameter,enum,very_high,False, +chunk_cd4dd644,src/unpriv/mm-explanatory.adoc,996,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Pipeline Dependencies (<>)","Therefore, (f) will never perform before (d) has performed.",unknown,unknown,medium,False, +chunk_3b45583f,src/unpriv/mm-explanatory.adoc,1008,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Pipeline Dependencies (<>)","[float=""center"",align=""center"",cols="".^1a,.^1a"",frame=""none"",grid=""none"",options=""noheader""] | | ! 2+!Hart 0 2+!Hart 1 2+!li t1, 1 2+^!li t1, 1 !(a) !sw t1,0(s0) !(d) !lw a0, 0(s1) !(b) !fence w, w !(e) !sw a0, 0(s2) !(c) !sw t1,0(s1) !(f) !sw t1, 0(s2) ! ! !(g) !lw a1, 0(s2) ! ! ! !xor a2,a1,a1 ! ! ! !add s0,s0,a2 ! ! !(h) !lw a3,0(s0) 4+!Outcome: `a0=1`, `a3=0` ! | ! //a! graphviz::images/graphviz/litmusdatacoirfi.txt[] a! image::graphviz/litmusdatacoirfi.png[] ! |",SW_rule,unknown,medium,False, +chunk_4841da90,src/unpriv/mm-explanatory.adoc,1037,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Pipeline Dependencies (<>)",Rule makes a similar observation to the previous rule: a store cannot be performed at memory until all previous loads that might access the same address have themselves been performed.,unknown,unknown,medium,False, +chunk_9fb64c76,src/unpriv/mm-explanatory.adoc,1037,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Pipeline Dependencies (<>)","Such a load must appear to execute before the store, but it cannot do so if the store were to overwrite the value in memory before the load had a chance to read the old value.",non_CSR_parameter,binary,very_high,False, +chunk_29b31706,src/unpriv/mm-explanatory.adoc,1037,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Pipeline Dependencies (<>)","Likewise, a store generally cannot be performed until it is known that preceding instructions will not cause an exception due to failed address resolution, and in this sense, rule 13 can be seen as somewhat of a special case of rule .",unknown,unknown,high,False, +chunk_266e9c70,src/unpriv/mm-explanatory.adoc,1069,"Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Pipeline Dependencies (<>)","Therefore, (f) cannot be sent to memory before (d) has executed and confirmed whether the addresses do indeed overlap.",unknown,unknown,medium,False, +chunk_fc160f8d,src/unpriv/mm-explanatory.adoc,1088,Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > Coherence and Cacheability,"The RISC-V Privileged ISA defines Physical Memory Attributes (PMAs) which specify, among other things, whether portions of the address space are coherent and/or cacheable.",unknown,unknown,medium,False, +chunk_8828b3dc,src/unpriv/mm-explanatory.adoc,1088,Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > Coherence and Cacheability,See the RISC-V Privileged ISA Specification for the complete details.,unknown,unknown,medium,False, +chunk_8e7a7a9f,src/unpriv/mm-explanatory.adoc,1088,Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > Coherence and Cacheability,"Here, we simply discuss how the various details in each PMA relate to the memory model:",unknown,unknown,medium,False, +chunk_281cf3db,src/unpriv/mm-explanatory.adoc,1094,Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > Coherence and Cacheability,"Non-cacheable regions may have more restrictive behavior than cacheable regions, but the set of allowed behaviors does not change regardless.",non_CSR_parameter,enum,medium,False, +chunk_def092c8,src/unpriv/mm-explanatory.adoc,1094,Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > Coherence and Cacheability,"However, some platform-specific and/or device-specific cacheability settings may differ. * Coherence PMAs: The memory consistency model for memory regions marked as non-coherent in PMAs is currently platform-specific and/or device-specific: the load-value axiom, the atomicity axiom, and the progress axiom all may be violated with non-coherent memory.",SW_rule,enum,medium,False, +chunk_91242b40,src/unpriv/mm-explanatory.adoc,1094,Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > Coherence and Cacheability,This distinction does not affect the memory model.,unknown,unknown,medium,False, +chunk_85a15741,src/unpriv/mm-explanatory.adoc,1120,Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > I/O Ordering,"Nevertheless, the following preserved program order rules still generally apply for accesses to I/O memory: memory access a precedes memory access b in global memory order if a precedes b in program order and one or more of the following holds:",unknown,unknown,high,False, +chunk_b06fc445,src/unpriv/mm-explanatory.adoc,1145,Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > I/O Ordering,"To enforce ordering between I/O operations and main memory operations, code must use a FENCE with PI, PO, SI, and/or SO, plus PR, PW, SR, and/or SW.",SW_rule,enum,very_high,False, +chunk_33c74417,src/unpriv/mm-explanatory.adoc,1160,Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > I/O Ordering,"When a fence is in fact used, implementations must assume that the device may attempt to access memory immediately after receiving the MMIO signal, and subsequent memory accesses from that device to memory must observe the effects of all accesses ordered prior to that MMIO operation.",SW_rule,binary,very_high,False, +chunk_1b270c5b,src/unpriv/mm-explanatory.adoc,1160,Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > I/O Ordering,"In other words, in , suppose `0(a0)` is in main memory and `0(a1)` is the address of a device register in I/O memory.",unknown,unknown,medium,False, +chunk_a14543c5,src/unpriv/mm-explanatory.adoc,1160,Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > I/O Ordering,"If the device accesses `0(a0)` upon receiving the MMIO write, then that load must conceptually appear after the first store to `0(a0)` according to the rules of the RVWMO memory model.",non_CSR_parameter,binary,very_high,False, +chunk_c48c1f22,src/unpriv/mm-explanatory.adoc,1160,Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > I/O Ordering,"Other implementations may find ways to be more aggressive, while others still may not need to do anything different at all for I/O and main memory accesses.",non_CSR_parameter,enum,medium,False, +chunk_2d7c04cd,src/unpriv/mm-explanatory.adoc,1160,Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > I/O Ordering,"Nevertheless, the RVWMO memory model does not distinguish between these options; it simply provides an implementation-agnostic mechanism to specify the orderings that must be enforced.",non_CSR_parameter,enum,very_high,False, +chunk_64f8ae35,src/unpriv/mm-explanatory.adoc,1178,Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > I/O Ordering,"Many architectures include separate notions of ""ordering"" and ""completion"" fences, especially as it relates to I/O (as opposed to regular main memory).",SW_rule,unknown,medium,False, +chunk_30e09741,src/unpriv/mm-explanatory.adoc,1178,Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > I/O Ordering,"Ordering fences simply ensure that memory operations stay in order, while completion fences ensure that predecessor accesses have all completed before any successors are made visible. RISC-V does not explicitly distinguish between ordering and completion fences.",SW_rule,unknown,medium,False, +chunk_4060cee4,src/unpriv/mm-explanatory.adoc,1178,Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > I/O Ordering,"Instead, this distinction is simply inferred from different uses of the FENCE bits.",SW_rule,unknown,medium,False, +chunk_a9259dc5,src/unpriv/mm-explanatory.adoc,1187,Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > I/O Ordering,"For implementations that conform to the RISC-V Unix Platform Specification, I/O devices and DMA operations are required to access memory coherently and via strongly ordered I/O channels.",unknown,unknown,medium,False, +chunk_534db460,src/unpriv/mm-explanatory.adoc,1187,Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > I/O Ordering,"Therefore, accesses to regular main memory regions that are concurrently accessed by external devices can also use the standard synchronization mechanisms.",unknown,unknown,medium,False, +chunk_d5302fbc,src/unpriv/mm-explanatory.adoc,1187,Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > I/O Ordering,Implementations that do not conform to the Unix Platform Specification and/or in which devices do not access memory coherently will need to use mechanisms (which are currently platform-specific or device-specific) to enforce coherency.,unknown,unknown,medium,False, +chunk_f427ee08,src/unpriv/mm-explanatory.adoc,1197,Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > I/O Ordering,I/O regions in the address space should be considered non-cacheable regions in the PMAs for those regions.,non_CSR_parameter,enum,medium,False, +chunk_14737dc4,src/unpriv/mm-explanatory.adoc,1197,Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > I/O Ordering,Such regions can be considered coherent by the PMA if they are not cached by any agent.,unknown,unknown,high,False, +chunk_68f3b50c,src/unpriv/mm-explanatory.adoc,1201,Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > I/O Ordering,The ordering guarantees in this section may not apply beyond a platform-specific boundary between the RISC-V cores and the device.,non_CSR_parameter,enum,medium,False, +chunk_848aa8fc,src/unpriv/mm-explanatory.adoc,1201,Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > I/O Ordering,Ordering must be enforced in such situations according to the platform-specific rules of those external devices and buses.,non_CSR_parameter,enum,very_high,False, +chunk_b86b06d8,src/unpriv/mm-explanatory.adoc,1223,Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines,"Normal x86 loads and stores are all inherently acquire-RCpc and release-RCpc operations: TSO enforces all load-load, load-store, and store-store ordering by default.",non_CSR_parameter,unknown,high,False, +chunk_68f4d020,src/unpriv/mm-explanatory.adoc,1223,Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines,"Therefore, under RVWMO, all TSO loads must be mapped onto a load followed by FENCE R,RW, and all TSO stores must be mapped onto FENCE RW,W followed by a store. TSO atomic read-modify-writes and x86 instructions using the LOCK prefix are fully ordered and can be implemented either via an AMO with both aq and rl set, or via an LR with aq set, the arithmetic operation in question, an SC with both aq and rl set, and a conditional branch checking the success condition.",SW_rule,enum,very_high,False, +chunk_29398847,src/unpriv/mm-explanatory.adoc,1237,Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines,"However, since RVWMO PPO Rule forbids forwarding of values from AMOs to subsequent loads, the use of AMOSWAP for stores may negatively affect performance. A TSO load can be mapped using LR with aq set: all such LR instructions will be unpaired, but that fact in and of itself does not preclude the use of LR for loads.",non_CSR_parameter,enum,medium,False, +chunk_24509e60,src/unpriv/mm-explanatory.adoc,1237,Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines,"However, again, this mapping may also negatively affect performance if it puts more pressure on the reservation mechanism than was originally intended.",non_CSR_parameter,enum,high,False, +chunk_8e821c28,src/unpriv/mm-explanatory.adoc,1286,Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines,"Since RISC-V does not currently have plain load and store opcodes with aq or rl annotations, ARM load-acquire and store-release operations should be mapped using fences instead.",SW_rule,enum,medium,False, +chunk_3ee19ac0,src/unpriv/mm-explanatory.adoc,1286,Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines,"Furthermore, in order to enforce store-release-to-load-acquire ordering, there must be a FENCE RW,RW between the store-release and load-acquire; enforces this by always placing the fence in front of each acquire operation. ARM load-exclusive and store-exclusive instructions can likewise map onto their RISC-V LR and SC equivalents, but instead of placing a FENCE RW,RW in front of an LR with aq set, we simply also set rl instead. ARM ISB maps on RISC-V to FENCE.I followed by FENCE R,R similarly to how ISYNC maps for Power.",SW_rule,enum,very_high,False, +chunk_ac91305b,src/unpriv/mm-explanatory.adoc,1350,Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines,"With regards to , other constructs (such as spinlocks) should follow accordingly.",non_CSR_parameter,enum,medium,False, +chunk_9c582431,src/unpriv/mm-explanatory.adoc,1350,Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines,Platforms or devices with non-coherent DMA may need additional synchronization (such as cache flush or invalidate mechanisms); currently any such extra synchronization will be device-specific.,non_CSR_parameter,enum,medium,False, +chunk_7352d7b8,src/unpriv/mm-explanatory.adoc,1356,Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines,Platforms with non-coherent DMA may also require a mechanism by which cache lines can be flushed and/or invalidated.,non_CSR_parameter,enum,medium,False, +chunk_daf05007,src/unpriv/mm-explanatory.adoc,1366,Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines,"The Linux mappings for release operations may seem stronger than necessary, but these mappings are needed to cover some cases in which Linux requires stronger orderings than the more intuitive mappings would provide.",non_CSR_parameter,enum,medium,False, +chunk_8d6ec7ea,src/unpriv/mm-explanatory.adoc,1425,Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines,"If load and store opcodes with aq and rl modifiers are introduced, then the mappings in will suffice.",unknown,unknown,high,False, +chunk_2ed1e9ec,src/unpriv/mm-explanatory.adoc,1425,Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines,"Even more importantly, a sequentially consistent store, followed by a sequentially consistent load can be reordered unless the mapping of stores is strengthened by either adding a second fence or mapping the store to `amoswap.rl` instead.",SW_rule,enum,high,False, +chunk_3697bf9d,src/unpriv/mm-explanatory.adoc,1559,Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines,2+!^*^ must be `lr.{w|d}.aqrl` in order to interoperate with code mapped per |,non_CSR_parameter,enum,very_high,False, +chunk_8e0d01b3,src/unpriv/mm-explanatory.adoc,1562,Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines,"Any AMO can be emulated by an LR/SC pair, but care must be taken to ensure that any PPO orderings that originate from the LR are also made to originate from the SC, and that any PPO orderings that terminate at the SC are also made to terminate at the LR.",non_CSR_parameter,enum,very_high,False, +chunk_66011a49,src/unpriv/mm-explanatory.adoc,1562,Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines,"For example, the LR must also be made to respect any data dependencies that the AMO has, given that load operations do not otherwise have any notion of a data dependency.",non_CSR_parameter,enum,very_high,False, +chunk_0aec14f4,src/unpriv/mm-explanatory.adoc,1562,Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines,"Likewise, the effect a FENCE R,R elsewhere in the same hart must also be made to apply to the SC, which would not otherwise respect that fence.",SW_rule,enum,very_high,False, +chunk_91a03d69,src/unpriv/mm-explanatory.adoc,1588,Preamble > RVWMO Explanatory Material > Why RVWMO? > Implementation Guidelines,"That said, to help people understand the actual implementations of the memory model, in this section we provide some guidelines on how architects and programmers should interpret the models' rules.",non_CSR_parameter,enum,medium,False, +chunk_1c08c596,src/unpriv/mm-explanatory.adoc,1602,Preamble > RVWMO Explanatory Material > Why RVWMO? > Implementation Guidelines,Both RVWMO and RVTSO are multi-copy atomic (or other-multi-copy-atomic): any store value that is visible to a hart other than the one that originally issued it must also be conceptually visible to all other harts in the system.,non_CSR_parameter,enum,very_high,False, +chunk_5bc24164,src/unpriv/mm-explanatory.adoc,1602,Preamble > RVWMO Explanatory Material > Why RVWMO? > Implementation Guidelines,"In other words, harts may forward from their own previous stores before those stores have become globally visible to all harts, but no early inter-hart forwarding is permitted.",non_CSR_parameter,enum,medium,False, +chunk_d62be608,src/unpriv/mm-explanatory.adoc,1602,Preamble > RVWMO Explanatory Material > Why RVWMO? > Implementation Guidelines,Multi-copy atomicity may be enforced in a number of ways.,non_CSR_parameter,enum,medium,False, +chunk_399dd0f2,src/unpriv/mm-explanatory.adoc,1602,Preamble > RVWMO Explanatory Material > Why RVWMO? > Implementation Guidelines,"It might hold inherently due to the physical design of the caches and store buffers, it may be enforced via a single-writer/multiple-reader cache coherence protocol, or it might hold due to some other mechanism.",non_CSR_parameter,enum,medium,False, +chunk_35da5759,src/unpriv/mm-explanatory.adoc,1613,Preamble > RVWMO Explanatory Material > Why RVWMO? > Implementation Guidelines,Nor may a cache coherence protocol forward a value from one hart to another until the coherence protocol has invalidated all older copies from other caches.,non_CSR_parameter,enum,medium,False, +chunk_0cf2a857,src/unpriv/mm-explanatory.adoc,1613,Preamble > RVWMO Explanatory Material > Why RVWMO? > Implementation Guidelines,"Of course, microarchitectures may (and high-performance implementations likely will) violate these rules under the covers through speculation or other optimizations, as long as any non-compliant behaviors are not exposed to the programmer.",non_CSR_parameter,enum,medium,False, +chunk_5a4c1660,src/unpriv/mm-explanatory.adoc,1629,Preamble > RVWMO Explanatory Material > Why RVWMO? > Implementation Guidelines,programmers will use PPO rules and regularly and actively. * expert programmers will use PPO rules to speed up critical paths of important data structures. * even expert programmers will rarely if ever use PPO rules and directly.,unknown,unknown,high,False, +chunk_c6cdfa9b,src/unpriv/mm-explanatory.adoc,1643,Preamble > RVWMO Explanatory Material > Why RVWMO? > Implementation Guidelines,"PPO rules and reflect well-understood rules that should pose few surprises to architects. * PPO rule reflects a natural and common hardware optimization, but one that is very subtle and hence is worth double checking carefully. * PPO rule may not be immediately obvious to architects, but it is a standard memory model requirement * The load value axiom, the atomicity axiom, and PPO rules reflect rules that most hardware implementations will enforce naturally, unless they contain extreme optimizations.",non_CSR_parameter,range,high,False, +chunk_784480d3,src/unpriv/mm-explanatory.adoc,1643,Preamble > RVWMO Explanatory Material > Why RVWMO? > Implementation Guidelines,"Of course, implementations should make sure to double check these rules nevertheless.",non_CSR_parameter,enum,medium,False, +chunk_75711236,src/unpriv/mm-explanatory.adoc,1643,Preamble > RVWMO Explanatory Material > Why RVWMO? > Implementation Guidelines,Hardware must also ensure that syntactic dependencies are not `optimized away`.,non_CSR_parameter,enum,very_high,False, +chunk_7b8892e2,src/unpriv/mm-explanatory.adoc,1681,Preamble > RVWMO Explanatory Material > Why RVWMO? > Implementation Guidelines,"Ignore all fences that do not have both PW and SR (unless the fence also orders I/O) * Ignore all PPO rules except for rules through , since the rest are redundant with other PPO rules under RVTSO assumptions",SW_rule,unknown,high,False, +chunk_59970993,src/unpriv/mm-explanatory.adoc,1688,Preamble > RVWMO Explanatory Material > Why RVWMO? > Implementation Guidelines,"Microarchitectures that attempt to implement silent stores must take care to ensure that the memory model is still obeyed, particularly in cases such as RSW which tend to be incompatible with silent stores. * Writes may be merged (i.e., two consecutive writes to the same address may be merged) or subsumed (i.e., the earlier of two back-to-back writes to the same address may be elided) as long as the resulting behavior does not otherwise violate the memory model semantics.",non_CSR_parameter,enum,very_high,False, +chunk_3ad4c20e,src/unpriv/mm-explanatory.adoc,1725,Preamble > RVWMO Explanatory Material > Why RVWMO? > Implementation Guidelines,"As written, if the load (d) reads value 1, then (a) must precede (f) in the global memory order:",non_CSR_parameter,binary,very_high,False, +chunk_7ee8c80f,src/unpriv/mm-explanatory.adoc,1734,Preamble > RVWMO Explanatory Material > Why RVWMO? > Implementation Guidelines,In other words the final value of the memory location whose address is in `s0` must be 2 (the value written by the store (f)) and cannot be 3 (the value written by the store (a)).,non_CSR_parameter,enum,very_high,False, +chunk_5ff37e32,src/unpriv/mm-explanatory.adoc,1808,Preamble > RVWMO Explanatory Material > Why RVWMO? > Known Issues > Mixed-size RSW,"To address this, we may choose to add something like the following new PPO rule: Memory operation a precedes memory operation b in preserved program order (and hence also in the global memory order) if a precedes b in program order, a and b both access regular main memory (rather than I/O regions), a is a load, b is a store, there is a load m between a and b, there is a byte x that both a and m read, there is no store between a and m that writes to x, and m precedes b in PPO.",non_CSR_parameter,enum,high,False, +chunk_b2861666,src/unpriv/mm-explanatory.adoc,1808,Preamble > RVWMO Explanatory Material > Why RVWMO? > Known Issues > Mixed-size RSW,"In other words, in herd syntax, we may choose to add `(po-loc & rsw);ppo;[W]` to PPO.",non_CSR_parameter,enum,medium,False, +chunk_0071b77a,src/unpriv/mm-formal.adoc,8,"Preamble > Formal Memory Model Specifications, Version 0.1",This appendix should be treated as commentary; all normative material is provided in and in the rest of the main body of the ISA specification.,non_CSR_parameter,enum,medium,False, +chunk_ea4128dc,src/unpriv/mm-formal.adoc,17,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy",We present a formal specification of the RVWMO memory model in Alloy (http://alloy.mit.edu).,unknown,unknown,medium,False, +chunk_7aba8faa,src/unpriv/mm-formal.adoc,17,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy",This model is available online at https://github.com/daniellustig/riscv-memory-model.,unknown,unknown,medium,False, +chunk_f6da777a,src/unpriv/mm-formal.adoc,94,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy",sig Hart { // hardware thread start : one Event } sig Address {} abstract sig Event { po: lone Event // program order },unknown,unknown,medium,False, +chunk_4b37c4bc,src/unpriv/mm-formal.adoc,102,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy","abstract sig MemoryEvent extends Event { address: one Address, acquireRCpc: lone MemoryEvent, acquireRCsc: lone MemoryEvent, releaseRCpc: lone MemoryEvent, releaseRCsc: lone MemoryEvent, addrdep: set MemoryEvent, ctrldep: set Event, datadep: set MemoryEvent, gmo: set MemoryEvent, // global memory order rf: set MemoryEvent } sig LoadNormal extends MemoryEvent {} // l{b|h|w|d} sig LoadReserve extends MemoryEvent { // lr pair: lone StoreConditional } sig StoreNormal extends MemoryEvent {} // s{b|h|w|d} // all StoreConditionals in the model are assumed to be successful sig StoreConditional extends MemoryEvent {} // sc sig AMO extends MemoryEvent {} // amo sig NOP extends Event {}",unknown,unknown,medium,False, +chunk_a831b369,src/unpriv/mm-formal.adoc,124,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy",fun Load : Event { LoadNormal + LoadReserve + AMO } fun Store : Event { StoreNormal + StoreConditional + AMO },unknown,unknown,medium,False, +chunk_5f3b8157,src/unpriv/mm-formal.adoc,127,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy","sig Fence extends Event { pr: lone Fence, // opcode bit pw: lone Fence, // opcode bit sr: lone Fence, // opcode bit sw: lone Fence // opcode bit } sig FenceTSO extends Fence {}",SW_rule,unknown,medium,False, +chunk_ba82bf2c,src/unpriv/mm-formal.adoc,235,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy",pred restricttocurrentencodings { no (LoadNormal + StoreNormal) & (Acquire + Release) },unknown,enum,medium,False, +chunk_97468130,src/unpriv/mm-formal.adoc,251,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > Formal Axiomatic Specification in Herd",The tool [.sans-serif]herd takes a memory model and a litmus test as input and simulates the execution of the test on top of the memory model.,unknown,unknown,medium,False, +chunk_70c79372,src/unpriv/mm-formal.adoc,251,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > Formal Axiomatic Specification in Herd",Memory models are written in the domain specific language Cat.,unknown,unknown,medium,False, +chunk_de8a0591,src/unpriv/mm-formal.adoc,251,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > Formal Axiomatic Specification in Herd",This section provides two Cat memory model of RVWMO.,unknown,unknown,medium,False, +chunk_3ae362c7,src/unpriv/mm-formal.adoc,251,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > Formal Axiomatic Specification in Herd","The first model, , follows the global memory order, , definition of RVWMO, as much as is possible for a Cat model.",unknown,unknown,medium,False, +chunk_5d81e359,src/unpriv/mm-formal.adoc,251,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > Formal Axiomatic Specification in Herd","The second model, , is an equivalent, more efficient, partial order based RVWMO model.",unknown,unknown,medium,False, +chunk_10ba83fe,src/unpriv/mm-formal.adoc,261,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > Formal Axiomatic Specification in Herd",The simulator `herd` is part of the `diy` tool suite — see http://diy.inria.fr for software and documentation.,SW_rule,unknown,medium,False, +chunk_a547799e,src/unpriv/mm-formal.adoc,292,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > Formal Axiomatic Specification in Herd","(* Same address, no W to the same address in-between *) let po-loc-no-w = po-loc \ (po-loc?;[W];po-loc) (* Read same write *) let rsw = rf^-1;rf (* Acquire, or stronger *) let AQ = Acq|AcqRel (* Release or stronger *) and RL = RelAcqRel (* All RCsc *) let RCsc = Acq|Rel|AcqRel (* Amo events are both R and W, relation rmw relates paired lr/sc *) let AMO = R & W let StCond = range(rmw)",unknown,unknown,medium,False, +chunk_8b24712b,src/unpriv/mm-formal.adoc,310,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > Formal Axiomatic Specification in Herd",(* Overlapping-Address Orderings *) let r1 = [M];po-loc;[W] and r2 = ([R];po-loc-no-w;[R]) \ rsw and r3 = [AMO|StCond];rfi;[R] (* Explicit Synchronization *) and r4 = fence and r5 = [AQ];po;[M] and r6 = [M];po;[RL] and r7 = [RCsc];po;[RCsc] and r8 = rmw (* Syntactic Dependencies *) and r9 = [M];addr;[M] and r10 = [M];data;[W] and r11 = [M];ctrl;[W] (* Pipeline Dependencies *) and r12 = [R];(addr|data);[W];rfi;[R] and r13 = [R];addr;[M];po;[W],SW_rule,unknown,medium,False, +chunk_751b821a,src/unpriv/mm-formal.adoc,336,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > Formal Axiomatic Specification in Herd",(* Notice that herd has defined its own rf relation *),unknown,unknown,medium,False, +chunk_cf70252d,src/unpriv/mm-formal.adoc,341,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > Formal Axiomatic Specification in Herd",(********************************) (* Generate global memory order *) (********************************),unknown,unknown,medium,False, +chunk_93533f52,src/unpriv/mm-formal.adoc,345,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > Formal Axiomatic Specification in Herd",let gmo0 = (* precursor: ie build gmo as an total order that include gmo0 *) loc & (W\FW) * FW | Final write after any write to the same location ppo | ppo compatible rfe includes herd external rf (optimization),unknown,unknown,medium,False, +chunk_337f2737,src/unpriv/mm-formal.adoc,350,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > Formal Axiomatic Specification in Herd","(* Walk over all linear extensions of gmo0 *) with gmo from linearizations(M\IW,gmo0)",unknown,unknown,medium,False, +chunk_3b85cab6,src/unpriv/mm-formal.adoc,353,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > Formal Axiomatic Specification in Herd",(* Add initial writes upfront -- convenient for computing rfGMO *) let gmo = gmo | loc & IW * (M\IW),unknown,unknown,medium,False, +chunk_30e7ddcd,src/unpriv/mm-formal.adoc,360,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > Formal Axiomatic Specification in Herd","(* Compute rf according to the load value axiom, aka rfGMO *) let WR = loc & ([W];(gmo|po);[R]) let rfGMO = WR \ (loc&([W];gmo);WR)",unknown,unknown,medium,False, +chunk_8014b1f4,src/unpriv/mm-formal.adoc,364,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > Formal Axiomatic Specification in Herd",(* Check equality of herd rf and of rfGMO *) empty (rf\rfGMO)|(rfGMO\rf) as RfCons,unknown,unknown,medium,False, +chunk_62dff2b5,src/unpriv/mm-formal.adoc,386,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > Formal Axiomatic Specification in Herd","(* Compute coherence relation *) include ""cos-opt.cat""",unknown,unknown,medium,False, +chunk_aa316717,src/unpriv/mm-formal.adoc,393,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > Formal Axiomatic Specification in Herd",(* Sc per location *) acyclic co|rf|fr|po-loc as Coherence,unknown,unknown,medium,False, +chunk_e725010e,src/unpriv/mm-formal.adoc,396,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > Formal Axiomatic Specification in Herd",(* Main model axiom *) acyclic co|rfe|fr|ppo as Model,unknown,unknown,medium,False, +chunk_1e4ea52c,src/unpriv/mm-formal.adoc,406,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model",This is an alternative presentation of the RVWMO memory model in operational style.,unknown,unknown,medium,False, +chunk_97e7f3cc,src/unpriv/mm-formal.adoc,406,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model","It aims to admit exactly the same extensional behavior as the axiomatic presentation: for any given program, admitting an execution if and only if the axiomatic presentation allows it.",unknown,unknown,high,False, +chunk_e3e448ba,src/unpriv/mm-formal.adoc,411,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model",The axiomatic presentation is defined as a predicate on complete candidate executions.,unknown,unknown,medium,False, +chunk_31870c17,src/unpriv/mm-formal.adoc,411,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model","In contrast, this operational presentation has an abstract microarchitectural flavor: it is expressed as a state machine, with states that are an abstract representation of hardware machine states, and with explicit out-of-order and speculative execution (but abstracting from more implementation-specific microarchitectural details such as register renaming, store buffers, cache hierarchies, cache protocols, etc.).",non_CSR_parameter,unknown,medium,False, +chunk_83ba8998,src/unpriv/mm-formal.adoc,411,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model","It can also construct executions incrementally, making it possible to interactively and randomly explore the behavior of larger examples, while the axiomatic model requires complete candidate executions over which the axioms can be checked.",non_CSR_parameter,unknown,medium,False, +chunk_ee15c13c,src/unpriv/mm-formal.adoc,424,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model","The operational presentation covers mixed-size execution, with potentially overlapping memory accesses of different power-of-two byte sizes.",unknown,unknown,medium,False, +chunk_c7b5237b,src/unpriv/mm-formal.adoc,428,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model","In `rmem`, the ISA semantics is expressed explicitly in Sail (see https://github.com/rems-project/sail for the Sail language, and https://github.com/rems-project/sail-riscv for the RISC-V ISA model), and the concurrency semantics is expressed in Lem (see https://github.com/rems-project/lem for the Lem language).",unknown,unknown,medium,False, +chunk_6d9c1010,src/unpriv/mm-formal.adoc,439,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model",`rmem` has a command-line interface and a web-interface.,unknown,unknown,medium,False, +chunk_3f350b56,src/unpriv/mm-formal.adoc,439,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model","The web-interface runs entirely on the client side, and is provided online together with a library of litmus tests: http://www.cl.cam.ac.uk/.",unknown,unknown,medium,False, +chunk_299d0526,src/unpriv/mm-formal.adoc,439,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model","The command-line interface is faster than the web-interface, specially in exhaustive mode.",unknown,unknown,medium,False, +chunk_e9dd54ab,src/unpriv/mm-formal.adoc,448,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model","Terminology: In contrast to the axiomatic presentation, here every memory operation is either a load or a store.",unknown,enum,medium,False, +chunk_3dd82b5d,src/unpriv/mm-formal.adoc,448,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model","Hence, AMOs give rise to two distinct memory operations, a load and a store.",unknown,unknown,medium,False, +chunk_1207ee15,src/unpriv/mm-formal.adoc,448,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model","When used in conjunction with `instruction`, the terms `load` and `store` refer to instructions that give rise to such memory operations.",unknown,unknown,high,False, +chunk_c95fe718,src/unpriv/mm-formal.adoc,448,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model",The term `acquire` refers to an instruction (or its memory operation) with the acquire-RCpc or acquire-RCsc annotation.,unknown,unknown,medium,False, +chunk_efba5840,src/unpriv/mm-formal.adoc,448,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model",The term `release` refers to an instruction (or its memory operation) with the release-RCpc or release-RCsc annotation.,unknown,unknown,medium,False, +chunk_0e8184c4,src/unpriv/mm-formal.adoc,460,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model",Model states: A model state consists of a shared memory and a tuple of hart states.,unknown,unknown,medium,False, +chunk_add0eaa5,src/unpriv/mm-formal.adoc,473,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model","The shared memory state records all the memory store operations that have propagated so far, in the order they propagated (this can be made more efficient, but for simplicity of the presentation we keep it this way).",unknown,unknown,medium,False, +chunk_ee5c4c91,src/unpriv/mm-formal.adoc,478,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model","Each hart state consists principally of a tree of instruction instances, some of which have been finished, and some of which have not.",unknown,unknown,medium,False, +chunk_9a8c1fcd,src/unpriv/mm-formal.adoc,484,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model",Conditional branch and indirect jump instructions may have multiple successors in the instruction tree.,non_CSR_parameter,enum,medium,False, +chunk_c797fa78,src/unpriv/mm-formal.adoc,488,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model",Each instruction instance in the instruction tree has a state that includes an execution state of the intra-instruction semantics (the ISA pseudocode for this instruction).,unknown,unknown,medium,False, +chunk_f31fa55d,src/unpriv/mm-formal.adoc,488,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model","One can think of the execution state of an instruction as a representation of the pseudocode control state, pseudocode call stack, and local variable values.",unknown,unknown,medium,False, +chunk_4f882a65,src/unpriv/mm-formal.adoc,488,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model","An instruction instance state also includes information about the instance's memory and register footprints, its register reads and writes, its memory operations, whether it is finished, etc.",unknown,unknown,medium,False, +chunk_3d06102d,src/unpriv/mm-formal.adoc,500,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model","The model defines, for any model state, the set of allowed transitions, each of which is a single atomic step to a new abstract machine state.",unknown,unknown,medium,False, +chunk_753cffb7,src/unpriv/mm-formal.adoc,500,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model","Each transition arises from a single instruction instance; it will change the state of that instance, and it may depend on or change the rest of its hart state and the shared memory state, but it does not depend on other hart states, and it will not change them.",non_CSR_parameter,enum,medium,False, +chunk_62ffd597,src/unpriv/mm-formal.adoc,500,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model","The transitions are introduced below and defined in , with a precondition and a construction of the post-transition model state for each.",unknown,unknown,medium,False, +chunk_18b0b77d,src/unpriv/mm-formal.adoc,514,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model",": This transition represents a fetch and decode of a new instruction instance, as a program order successor of a previously fetched instruction instance (or the initial fetch address).",unknown,unknown,medium,False, +chunk_32a42b42,src/unpriv/mm-formal.adoc,517,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model",The model assumes the instruction memory is fixed; it does not describe the behavior of self-modifying code.,unknown,unknown,medium,False, +chunk_5151a39a,src/unpriv/mm-formal.adoc,517,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model","In particular, the transition does not generate memory load operations, and the shared memory is not involved in the transition.",unknown,unknown,medium,False, +chunk_38f9490c,src/unpriv/mm-formal.adoc,517,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model","Instead, the model depends on an external oracle that provides an opcode when given a memory location.",non_CSR_parameter,unknown,high,False, +chunk_076d0a30,src/unpriv/mm-formal.adoc,526,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model",: This is a read of a register value from the most recent program-order-predecessor instruction instance that writes to that register.,unknown,unknown,medium,False, +chunk_27354d72,src/unpriv/mm-formal.adoc,530,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model",": This covers pseudocode internal computation: arithmetic, function calls, etc.",unknown,unknown,medium,False, +chunk_f6d7bf96,src/unpriv/mm-formal.adoc,533,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model",": At this point the instruction pseudocode is done, the instruction cannot be restarted, memory accesses cannot be discarded, and all memory effects have taken place.",unknown,unknown,medium,False, +chunk_4ab04611,src/unpriv/mm-formal.adoc,533,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model","For conditional branch and indirect jump instructions, any program order successors that were fetched from an address that is not the one that was written to the pc register are discarded, together with the sub-tree of instruction instances below them.",unknown,unknown,medium,False, +chunk_c76f56b4,src/unpriv/mm-formal.adoc,542,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model",[circle] * : At this point the memory footprint of the load instruction is provisionally known (it could change if earlier instructions are restarted) and its individual memory load operations can start being satisfied.,unknown,unknown,high,False, +chunk_5e99cd00,src/unpriv/mm-formal.adoc,548,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model","[disc] * : This partially or entirely satisfies a single memory load operation by forwarding, from program-order-previous memory store operations.",unknown,unknown,medium,False, +chunk_1049a7fe,src/unpriv/mm-formal.adoc,551,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model",": This entirely satisfies the outstanding slices of a single memory load operation, from memory.",unknown,unknown,medium,False, +chunk_7e774973,src/unpriv/mm-formal.adoc,554,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model",[circle] * : At this point all the memory load operations of the instruction have been entirely satisfied and the instruction pseudocode can continue executing. A load instruction can be subject to being restarted until the transition.,unknown,unknown,medium,False, +chunk_b3118161,src/unpriv/mm-formal.adoc,563,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model",[circle] * : At this point the memory footprint of the store is provisionally known.,unknown,unknown,medium,False, +chunk_d946f40f,src/unpriv/mm-formal.adoc,567,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model",: At this point the memory store operations have their values and program-order-successor memory load operations can be satisfied by forwarding from them.,unknown,unknown,medium,False, +chunk_011742cf,src/unpriv/mm-formal.adoc,571,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model",": At this point the store operations are guaranteed to happen (the instruction can no longer be restarted or discarded), and they can start being propagated to memory.",unknown,unknown,medium,False, +chunk_fc1f3677,src/unpriv/mm-formal.adoc,575,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model",[disc] * : This propagates a single memory store operation to memory.,unknown,unknown,medium,False, +chunk_f25ddaad,src/unpriv/mm-formal.adoc,578,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model","[circle] * : At this point all the memory store operations of the instruction have been propagated to memory, and the instruction pseudocode can continue executing.",unknown,unknown,medium,False, +chunk_ac10304f,src/unpriv/mm-formal.adoc,591,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model",": This is an atomic execution of the transitions and , it is enabled only if the stores from which the `lr` read from have not been overwritten.",unknown,binary,high,False, +chunk_b54865e7,src/unpriv/mm-formal.adoc,600,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model","[disc] * : This is an atomic execution of all the transitions needed to satisfy the load operation, do the required arithmetic, and propagate the store operation.",unknown,unknown,medium,False, +chunk_5e952d45,src/unpriv/mm-formal.adoc,610,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model","The transitions labeled {circ} can always be taken eagerly, as soon as their precondition is satisfied, without excluding other behavior; the {bullet} cannot.",unknown,unknown,medium,False, +chunk_d1d4b77e,src/unpriv/mm-formal.adoc,632,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model",This concludes the informal description of the operational model.,unknown,unknown,medium,False, +chunk_1e9175c1,src/unpriv/mm-formal.adoc,632,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model",The following sections describe the formal operational model.,unknown,unknown,medium,False, +chunk_8c11ee5b,src/unpriv/mm-formal.adoc,639,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Intra-instruction Pseudocode Execution","The intra-instruction semantics for each instruction instance is expressed as a state machine, essentially running the instruction pseudocode.",unknown,unknown,medium,False, +chunk_93db2f5b,src/unpriv/mm-formal.adoc,639,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Intra-instruction Pseudocode Execution","Given a pseudocode execution state, it computes the next state.",unknown,unknown,medium,False, +chunk_e0195a75,src/unpriv/mm-formal.adoc,639,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Intra-instruction Pseudocode Execution","Most states identify a pending memory or register operation, requested by the pseudocode, which the memory model has to do.",unknown,unknown,medium,False, +chunk_69cf75a1,src/unpriv/mm-formal.adoc,646,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Intra-instruction Pseudocode Execution","[cols=""<,<"",grid=""none""] | |Loadmem(kind, address, size, loadcontinuation) |- memory load operation",unknown,unknown,medium,False, +chunk_cbea74c6,src/unpriv/mm-formal.adoc,651,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Intra-instruction Pseudocode Execution",|Earlyscfail(rescontinuation) |- allow `sc` to fail early,unknown,unknown,medium,False, +chunk_c64732ea,src/unpriv/mm-formal.adoc,653,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Intra-instruction Pseudocode Execution","|Storeea(kind, address, size, nextstate) |- memory store effective address",unknown,unknown,medium,False, +chunk_446591f2,src/unpriv/mm-formal.adoc,674,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Intra-instruction Pseudocode Execution","for load/store, kind identifies whether it is `lr/sc`, acquire-RCpc/release-RCpc, acquire-RCsc/release-RCsc, acquire-release-RCsc; * for fence, kind identifies whether it is a normal or TSO, and (for normal fences) the predecessor and successor ordering bits; * regname identifies a register and a slice thereof (start and end bit indices); and the continuations describe how the instruction instance will continue for each value that might be provided by the surrounding memory model (the loadcontinuation and readcontinuation take the value loaded from memory and read from the previous register write, the storecontinuation takes false for an `sc` that failed and true in all other cases, and rescontinuation takes false if the `sc` fails and true otherwise).",SW_rule,unknown,high,False, +chunk_047a7a8f,src/unpriv/mm-formal.adoc,674,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Intra-instruction Pseudocode Execution","Notice that writing to memory is split into two steps, Storeea and Storememv: the first one makes the memory footprint of the store provisionally known, and the second one adds the value to be stored.",unknown,unknown,medium,False, +chunk_f41140ee,src/unpriv/mm-formal.adoc,674,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Intra-instruction Pseudocode Execution","We ensure these are paired in the pseudocode (Storeea followed by Storememv), but there may be other steps between them.",non_CSR_parameter,enum,medium,False, +chunk_0e838eb5,src/unpriv/mm-formal.adoc,674,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Intra-instruction Pseudocode Execution","The pseudocode of each instruction performs at most one store or one load, except for AMOs that perform exactly one load and one store.",unknown,range,medium,False, +chunk_8ddfb9bb,src/unpriv/mm-formal.adoc,674,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Intra-instruction Pseudocode Execution",Those memory accesses are then split apart into the architecturally atomic units by the hart semantics (see and below).,unknown,unknown,medium,False, +chunk_f03700c5,src/unpriv/mm-formal.adoc,697,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Intra-instruction Pseudocode Execution","Informally, each bit of a register read should be satisfied from a register write by the most recent (in program order) instruction instance that can write that bit (or from the hart’s initial register state if there is no such write).",non_CSR_parameter,enum,high,False, +chunk_2a03b49b,src/unpriv/mm-formal.adoc,697,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Intra-instruction Pseudocode Execution","We ensure in the pseudocode that each instruction does at most one register write to each register bit, and also that it does not try to read a register value it just wrote.",unknown,range,medium,False, +chunk_b408e4e1,src/unpriv/mm-formal.adoc,707,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Intra-instruction Pseudocode Execution",Data-flow dependencies (address and data) in the model emerge from the fact that each register read has to wait for the appropriate register write to be executed (as described above).,unknown,unknown,medium,False, +chunk_71f6a960,src/unpriv/mm-formal.adoc,714,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Instruction Instance State",Each instruction instance i has a state comprising:,unknown,unknown,medium,False, +chunk_83766a01,src/unpriv/mm-formal.adoc,730,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Instruction Instance State","[cols=""<,<"",grid=""none""] | |Plain(isastate) |- ready to make a pseudocode transition",unknown,unknown,medium,False, +chunk_d96dbb62,src/unpriv/mm-formal.adoc,737,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Instruction Instance State","|Pendingmemstores(storecontinuation) |- requesting memory store operation(s) | * regreads, the register reads the instance has performed, including, for each one, the register write slices it read from; * regwrites, the register writes the instance has performed; * memloads, a set of memory load operations, and for each one the as-yet-unsatisfied slices (the byte indices that have not been satisfied yet), and, for the satisfied slices, the store slices (each consisting of a memory store operation and subset of its byte indices) that satisfied it. * memstores, a set of memory store operations, and for each one a flag that indicates whether it has been propagated (passed to the shared memory) or not. * information recording whether the instance is committed, finished, etc.",unknown,unknown,medium,False, +chunk_e8d569da,src/unpriv/mm-formal.adoc,754,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Instruction Instance State",Each memory load operation includes a memory footprint (address and size).,unknown,unknown,medium,False, +chunk_c018fe6e,src/unpriv/mm-formal.adoc,754,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Instruction Instance State","Each memory store operations includes a memory footprint, and, when available, a value.",unknown,unknown,high,False, +chunk_1824b40a,src/unpriv/mm-formal.adoc,762,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Instruction Instance State","Similarly, it is said to have a fully determined memory footprint if the load (and `sc`) instructions feeding its memory operation address register are finished.",unknown,unknown,high,False, +chunk_d62eaaa3,src/unpriv/mm-formal.adoc,762,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Instruction Instance State","Formally, we first define the notion of fully determined register write: a register write w from regwrites of instruction instance i is said to be fully determined if one of the following conditions hold:",unknown,enum,high,False, +chunk_e4f85dda,src/unpriv/mm-formal.adoc,780,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Instruction Instance State","Now, an instruction instance i is said to have fully determined data if for every register read r from regreads, the register writes that r reads from are fully determined.",unknown,unknown,high,False, +chunk_5a61afcf,src/unpriv/mm-formal.adoc,780,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Instruction Instance State","An instruction instance i is said to have a fully determined memory footprint if for every register read r from regreads that feeds into i’s memory operation address, the register writes that r reads from are fully determined.",unknown,unknown,high,False, +chunk_d02118f6,src/unpriv/mm-formal.adoc,791,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Hart State",The model state of a single hart comprises:,unknown,unknown,medium,False, +chunk_5fd12c29,src/unpriv/mm-formal.adoc,793,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Hart State","hartid, a unique identifier of the hart; * initialregisterstate, the initial register value for each register; * initialfetchaddress, the initial instruction fetch address; * instructiontree, a tree of the instruction instances that have been fetched (and not discarded), in program order.",unknown,unknown,medium,False, +chunk_72a4793b,src/unpriv/mm-formal.adoc,802,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Shared Memory State","The model state of the shared memory comprises a list of memory store operations, in the order they propagated to the shared memory.",unknown,unknown,medium,False, +chunk_6381b3fc,src/unpriv/mm-formal.adoc,805,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Shared Memory State",When a store operation is propagated to the shared memory it is simply added to the end of the list.,unknown,unknown,high,False, +chunk_cc1ecbd0,src/unpriv/mm-formal.adoc,805,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Shared Memory State","When a load operation is satisfied from memory, for each byte of the load operation, the most recent corresponding store slice is returned.",unknown,unknown,high,False, +chunk_5b25d999,src/unpriv/mm-formal.adoc,812,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions",The description starts with a condition over the current system state.,unknown,unknown,medium,False, +chunk_5b534fb3,src/unpriv/mm-formal.adoc,812,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions",The transition can be taken in the current state only if the condition is satisfied.,unknown,unknown,high,False, +chunk_8103ecdf,src/unpriv/mm-formal.adoc,812,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions","The condition is followed by an action that is applied to that state when the transition is taken, in order to generate the new system state.",unknown,unknown,high,False, +chunk_f0a909ba,src/unpriv/mm-formal.adoc,822,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Fetch instruction",A possible program-order-successor of instruction instance i can be fetched from address loc if:,unknown,unknown,medium,False, +chunk_b0536a89,src/unpriv/mm-formal.adoc,836,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Fetch instruction","Action: construct a freshly initialized instruction instance i' for the instruction in the program memory at loc, with state Plain(isastate), computed from the instruction pseudocode, including the static information available from the pseudocode such as its instructionkind, srcregs, and dstregs, and add i' to the hart’s instructiontree as a successor of i.",unknown,unknown,medium,False, +chunk_667b7744,src/unpriv/mm-formal.adoc,844,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Fetch instruction",For most instructions these addresses are easily obtained from the instruction pseudocode.,unknown,unknown,medium,False, +chunk_28b84575,src/unpriv/mm-formal.adoc,844,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Fetch instruction",In principle the mathematical model should allow speculation to arbitrary addresses here.,non_CSR_parameter,enum,high,False, +chunk_53266906,src/unpriv/mm-formal.adoc,844,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Fetch instruction",The exhaustive search in the `rmem` tool handles this by running the exhaustive search multiple times with a growing set of possible next fetch addresses for each indirect jump.,unknown,unknown,medium,False, +chunk_1e522679,src/unpriv/mm-formal.adoc,844,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Fetch instruction","The initial search uses empty sets, hence there is no fetch after indirect jump instruction until the pseudocode of the instruction writes to pc, and then we use that value for fetching the next instruction.",unknown,unknown,medium,False, +chunk_1e9e1f74,src/unpriv/mm-formal.adoc,844,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Fetch instruction","Before starting the next iteration of exhaustive search, we collect for each indirect jump (grouped by code location) the set of values it wrote to pc in all the executions in the previous search iteration, and use that as possible next fetch addresses of the instruction.",unknown,unknown,medium,False, +chunk_ecaeafb1,src/unpriv/mm-formal.adoc,867,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Initiate memory load operations","An instruction instance i in state Plain(Loadmem(kind, address, size, loadcontinuation)) can always initiate the corresponding memory load operations.",unknown,unknown,medium,False, +chunk_05ee3e6b,src/unpriv/mm-formal.adoc,883,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Satisfy memory load operation by forwarding from unpropagated stores","For a non-AMO load instruction instance i in state Pendingmemloads(loadcontinuation), and a memory load operation mlo in i.memloads that has unsatisfied slices, the memory load operation can be partially or entirely satisfied by forwarding from unpropagated memory store operations by store instruction instances that are program-order-before i if:",unknown,unknown,medium,False, +chunk_a640bb59,src/unpriv/mm-formal.adoc,909,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Satisfy memory load operation by forwarding from unpropagated stores","Let msoss be the set of all unpropagated memory store operation slices from non-`sc` store instruction instances that are program-order-before i and have already calculated the value to be stored, that overlap with the unsatisfied slices of mlo, and which are not superseded by intervening store operations or store operations that are read from by an intervening load.",unknown,unknown,medium,False, +chunk_cee88834,src/unpriv/mm-formal.adoc,909,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Satisfy memory load operation by forwarding from unpropagated stores","The last condition requires, for each memory store operation slice msos in msoss from instruction i':",non_CSR_parameter,unknown,medium,False, +chunk_6bb184c2,src/unpriv/mm-formal.adoc,919,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Satisfy memory load operation by forwarding from unpropagated stores",that there is no store instruction program-order-between i and i' with a memory store operation overlapping msos; and * that there is no load instruction program-order-between i and i' that was satisfied from an overlapping memory store operation slice from a different hart.,unknown,unknown,medium,False, +chunk_4ec499fc,src/unpriv/mm-formal.adoc,943,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Satisfy memory load operation by forwarding from unpropagated stores","program-order-successors of j that have data-flow dependency on a register write of j; * program-order-successors of j that have a memory load operation that reads from a memory store operation of j (by forwarding); * if j is a load-acquire, all the program-order-successors of j; * if j is a load, for every `fence`, f, with `.sr` and `.pr` set, and `.pw` not set, that is a program-order-successor of j, all the load instructions that are program-order-successors of f; * if j is a load, for every `fence.tso`, f, that is a program-order-successor of j, all the load instructions that are program-order-successors of f; and * (recursively) all the restart-dependents of all the instruction instances above.",SW_rule,unknown,high,False, +chunk_2faf5104,src/unpriv/mm-formal.adoc,962,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Satisfy memory load operation from memory","For an instruction instance i of a non-AMO load instruction or an AMO instruction in the context of the transition, any memory load operation mlo in i.memloads that has unsatisfied slices, can be satisfied from memory if all the conditions of > are satisfied.",unknown,unknown,high,False, +chunk_7fd6a2e4,src/unpriv/mm-formal.adoc,962,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Satisfy memory load operation from memory","Action: let msoss be the memory store operation slices from memory covering the unsatisfied slices of mlo, and apply the action of .",unknown,unknown,medium,False, +chunk_c26ac4d3,src/unpriv/mm-formal.adoc,973,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Complete load operations","Action: update the state of i to Plain(loadcontinuation(memvalue)), where memvalue is assembled from all the memory store operation slices that satisfied i.memloads.",unknown,unknown,medium,False, +chunk_972a4716,src/unpriv/mm-formal.adoc,985,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Early `sc` fail",An `sc` instruction instance i in state Plain(Earlyscfail(rescontinuation)) can always be made to fail.,unknown,unknown,medium,False, +chunk_22ac1409,src/unpriv/mm-formal.adoc,985,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Early `sc` fail",Action: update the state of i to Plain(rescontinuation(false)).,unknown,unknown,medium,False, +chunk_5f7b5313,src/unpriv/mm-formal.adoc,993,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Paired `sc`",An `sc` instruction instance i in state Plain(Earlyscfail(rescontinuation)) can continue its (potentially successful) execution if i is paired with an `lr`.,unknown,unknown,high,False, +chunk_3a4c5e9e,src/unpriv/mm-formal.adoc,993,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Paired `sc`",Action: update the state of i to Plain(rescontinuation(true)).,unknown,unknown,medium,False, +chunk_5c9d9b55,src/unpriv/mm-formal.adoc,1001,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Initiate memory store operation footprints","An instruction instance i in state Plain(Storeea(kind, address, size, nextstate)) can always announce its pending memory store operation footprint.",unknown,unknown,medium,False, +chunk_6c12220b,src/unpriv/mm-formal.adoc,1017,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Instantiate memory store operation values","An instruction instance i in state Plain(Storememv(memvalue, storecontinuation)) can always instantiate the values of the memory store operations i.memstores.",unknown,unknown,medium,False, +chunk_6abdc165,src/unpriv/mm-formal.adoc,1030,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Commit store instruction","An uncommitted instruction instance i of a non-`sc` store instruction or an `sc` instruction in the context of the transition, in state Pendingmemstores(storecontinuation), can be committed (not to be confused with propagated) if:",unknown,unknown,medium,False, +chunk_e4ab3146,src/unpriv/mm-formal.adoc,1053,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Commit store instruction",Action: record that i is committed.,unknown,unknown,medium,False, +chunk_28deb88b,src/unpriv/mm-formal.adoc,1057,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Propagate store operation","For a committed instruction instance i in state Pendingmemstores(storecontinuation), and an unpropagated memory store operation mso in i.memstores, mso can be propagated if:",unknown,unknown,medium,False, +chunk_b968b1a1,src/unpriv/mm-formal.adoc,1105,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Commit and propagate store operation of an `sc`","An uncommitted `sc` instruction instance i, from hart h, in state Pendingmemstores(storecontinuation), with a paired `lr` i' that has been satisfied by some store slices msoss, can be committed and propagated at the same time if:",unknown,unknown,medium,False, +chunk_8fa66658,src/unpriv/mm-formal.adoc,1130,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Late `sc` fail","An `sc` instruction instance i in state Pendingmemstores(storecontinuation), that has not propagated its memory store operation, can always be made to fail.",unknown,unknown,medium,False, +chunk_782f03af,src/unpriv/mm-formal.adoc,1140,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Complete store operations","A store instruction instance i in state Pendingmemstores(storecontinuation), for which all the memory store operations in i.memstores have been propagated, can always be completed (not to be confused with finished).",unknown,unknown,medium,False, +chunk_fe8e0253,src/unpriv/mm-formal.adoc,1140,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Complete store operations",Action: update the state of i to Plain(storecontinuation(true)).,unknown,unknown,medium,False, +chunk_8d6cae47,src/unpriv/mm-formal.adoc,1150,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Satisfy, commit and propagate operations of an AMO",An AMO instruction instance i in state Pendingmemloads(loadcontinuation) can perform its memory access if it is possible to perform the following sequence of transitions with no intervening transitions:,unknown,unknown,high,False, +chunk_f580db65,src/unpriv/mm-formal.adoc,1163,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Satisfy, commit and propagate operations of an AMO","and in addition, the condition of , with the exception of not requiring i to be in state Plain(Done), holds after those transitions.",unknown,unknown,high,False, +chunk_87ba038a,src/unpriv/mm-formal.adoc,1163,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Satisfy, commit and propagate operations of an AMO","Action: perform the above sequence of transitions (this does not include ), one after the other, with no intervening transitions.",unknown,unknown,medium,False, +chunk_a29af968,src/unpriv/mm-formal.adoc,1171,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Commit fence","A fence instruction instance i in state Plain(Fence(kind, nextstate)) can be committed if:",SW_rule,unknown,medium,False, +chunk_474d9742,src/unpriv/mm-formal.adoc,1189,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Register read","An instruction instance i in state Plain(Readreg(regname, readcont)) can do a register read of regname if every instruction instance that it needs to read from has already performed the expected regname register write.",unknown,unknown,high,False, +chunk_df044385,src/unpriv/mm-formal.adoc,1194,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Register read","Let readsources include, for each bit of regname, the write to that bit by the most recent (in program order) instruction instance that can write to that bit, if any.",unknown,unknown,high,False, +chunk_38aa5961,src/unpriv/mm-formal.adoc,1194,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Register read","If there is no such instruction, the source is the initial register value from initialregisterstate.",unknown,unknown,high,False, +chunk_8c84d2cb,src/unpriv/mm-formal.adoc,1194,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Register read",Let regvalue be the value assembled from readsources.,unknown,unknown,high,False, +chunk_5ce7ef6c,src/unpriv/mm-formal.adoc,1215,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Register write","where deps is a pair of the set of all readsources from i.regreads, and a flag that is true iff i is a load instruction instance that has already been entirely satisfied.",unknown,unknown,high,False, +chunk_1504e0ec,src/unpriv/mm-formal.adoc,1223,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Pseudocode internal step",An instruction instance i in state Plain(Internal(nextstate)) can always do that pseudocode-internal step.,unknown,unknown,medium,False, +chunk_f8e98720,src/unpriv/mm-formal.adoc,1280,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Limitations",The model covers user-level RV64I and RV64A.,unknown,unknown,medium,False, +chunk_d90dd08c,src/unpriv/mm-formal.adoc,1280,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Limitations","In particular, it does not support the misaligned atomicity granule PMA or the total store ordering extension ""Ztso"".",unknown,unknown,medium,False, +chunk_e5a0ab97,src/unpriv/mm-formal.adoc,1280,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Limitations","This will involve, mostly, writing Sail code for the instructions, with minimal, if any, changes to the concurrency model. * The model covers only normal memory accesses (it does not handle I/O accesses). * The model does not cover TLB-related effects. * The model assumes the instruction memory is fixed.",unknown,unknown,high,False, +chunk_780250bc,src/unpriv/mm-formal.adoc,1280,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Limitations","In particular, the transition does not generate memory load operations, and the shared memory is not involved in the transition.",unknown,unknown,medium,False, +chunk_a8823504,src/unpriv/mm-formal.adoc,1280,"Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Limitations","Instead, the model depends on an external oracle that provides an opcode when given a memory location. * The model does not cover exceptions, traps and interrupts.",non_CSR_parameter,unknown,high,False, +chunk_0a569f46,src/unpriv/preface.adoc,443,Preamble > Preface,"However, it remains the only standard instruction-fetch coherence mechanism. * Removed prohibitions on using RV32E with other extensions. * Removed platform-specific mandates that certain encodings produce illegal-instruction exceptions in RV32E and RV64I chapters. * Counter/timer instructions are now not considered part of the mandatory base ISA, and so CSR instructions were moved into separate chapter and marked as version 2.0, with the unprivileged counters moved into another separate chapter.",CSR_controlled,enum,high,False, +chunk_604e7a05,src/unpriv/preface.adoc,443,Preamble > Preface,"The counters are not ready for ratification as there are outstanding issues, including counter inaccuracies. * A CSR-access ordering model has been added. * Explicitly defined the 16-bit half-precision floating-point format for floating-point instructions in the 2-bit fmt field. * Defined the signed-zero behavior of FMIN.fmt and FMAX.fmt, and changed their behavior on signaling-NaN inputs to conform to the `minimumNumber` and `maximumNumber` operations in the proposed IEEE 754-201x specification. * The memory consistency model, RVWMO, has been defined. * The ""Zam"" extension, which permits misaligned AMOs and specifies their semantics, has been defined. * The ""Ztso"" extension, which enforces a stricter memory consistency model than RVWMO, has been defined. * Improvements to the description and commentary. * Defined the term `IALIGN` as shorthand to describe the instruction-address alignment constraint. * Removed text of `P` extension chapter as now superseded by active task group documents. * Removed text of `V` extension chapter as now superseded by separate vector extension draft document.",CSR_controlled,range,high,False, +chunk_e5172c01,src/unpriv/preface.adoc,580,Preamble > Preface,"Numerous additions and improvements to the commentary sections. * Separate version numbers for each chapter. * Modification to long instruction encodings >64 bits to avoid moving the rd specifier in very long instruction formats. * CSR instructions are now described in the base integer format where the counter registers are introduced, as opposed to only being introduced later in the floating-point section (and the companion privileged architecture manual). * The SCALL and SBREAK instructions have been renamed to `ECALL` and `EBREAK`, respectively.",CSR_controlled,range,high,False, +chunk_6f88d834,src/unpriv/preface.adoc,610,Preamble > Preface,"The ISA has been divided into an integer base with several standard extensions. * The instruction formats have been rearranged to make immediate encoding more efficient. * The base ISA has been defined to have a little-endian memory system, with big-endian or bi-endian as non-standard variants. * Load-Reserved/Store-Conditional (`LR/SC`) instructions have been added in the atomic instruction extension. * `AMOs` and `LR/SC` can support the release consistency model. * The `FENCE` instruction provides finer-grain memory and I/O orderings. * An `AMO` for fetch-and-`XOR` (`AMOXOR`) has been added, and the encoding for `AMOSWAP` has been changed to make room. * The `AUIPC` instruction, which adds a 20-bit upper immediate to the `PC`, replaces the `RDNPC` instruction, which only read the current `PC` value.",SW_rule,range,medium,False, +chunk_1864b5b7,src/unpriv/preface.adoc,610,Preamble > Preface,"This change simplifies datapath design. * `FCLASS.S` and `FCLASS.D` floating-point classify instructions have been added. * A simpler NaN generation and propagation scheme has been adopted. * For `RV32I`, the system performance counters have been extended to 64-bits wide, with separate read access to the upper and lower 32 bits. * Canonical `NOP` and `MV` encodings have been defined. * Standard instruction-length encodings have been defined for 48-bit, 64-bit, and >64-bit instructions. * Description of a 128-bit address space variant, `RV128`, has been added. * Major opcodes in the 32-bit base instruction format have been allocated for user-defined custom extensions. * A typographical error that suggested that stores source their data from rd has been corrected to refer to rs2.",non_CSR_parameter,range,high,False, +chunk_5519f459,src/unpriv/q-st-ext.adoc,16,"Preamble > ""Q"" Extension for Quad-Precision Floating-Point, Version 2.2 > Quad-Precision Load and Store Instructions","New 128-bit variants of LOAD-FP and STORE-FP instructions are added, encoded with a new value for the funct3 width field.",non_CSR_parameter,range,high,False, +chunk_e86a31c5,src/unpriv/q-st-ext.adoc,24,"Preamble > ""Q"" Extension for Quad-Precision Floating-Point, Version 2.2 > Quad-Precision Load and Store Instructions",FLQ and FSQ are only guaranteed to execute atomically if the effective address is naturally aligned and XLEN=128.,unknown,unknown,high,False, +chunk_ada16a4c,src/unpriv/q-st-ext.adoc,34,"Preamble > ""Q"" Extension for Quad-Precision Floating-Point, Version 2.2 > Quad-Precision Load and Store Instructions > Quad-Precision Computational Instructions","A new supported format is added to the format field of most instructions, as shown in",unknown,enum,high,False, +chunk_fbe9ffb6,src/unpriv/q-st-ext.adoc,59,"Preamble > ""Q"" Extension for Quad-Precision Floating-Point, Version 2.2 > Quad-Precision Load and Store Instructions > Quad-Precision Convert and Move Instructions","These instructions are defined analogously to the double-precision-to-integer and integer-to-double-precision conversion instructions. FCVT.W.Q or FCVT.L.Q converts a quad-precision floating-point number to a signed 32-bit or 64-bit integer, respectively. FCVT.Q.W or FCVT.Q.L converts a 32-bit or 64-bit signed integer, respectively, into a quad-precision floating-point number. FCVT.WU.Q, FCVT.LU.Q, FCVT.Q.WU, and FCVT.Q.LU variants convert to or from unsigned integer values. FCVT.L[U].Q and FCVT.Q.L[U] are RV64-only instructions.",non_CSR_parameter,range,high,False, +chunk_01b06710,src/unpriv/q-st-ext.adoc,95,"Preamble > ""Q"" Extension for Quad-Precision Floating-Point, Version 2.2 > Quad-Precision Load and Store Instructions > Quad-Precision Convert and Move Instructions","FMV.X.Q and FMV.Q.X instructions are not provided in RV32 or RV64, so quad-precision bit patterns must be moved to the integer registers via memory.",non_CSR_parameter,enum,very_high,False, +chunk_78b10a24,src/unpriv/rationale.adoc,16,"Preamble > Historical Rationale for Extensions > ""Zihintpause"" Extension for Pause Hint",The PAUSE instruction hints to a hart that it should temporarily reduce its rate of execution.,non_CSR_parameter,enum,medium,False, +chunk_836d2946,src/unpriv/rationale.adoc,21,"Preamble > Historical Rationale for Extensions > ""Zihintpause"" Extension for Pause Hint",Much of the debate surrounding this extension centered on whether a facility similar to x86's MONITOR/MWAIT should instead be provided.,non_CSR_parameter,enum,medium,False, +chunk_b08329c6,src/unpriv/rationale.adoc,58,"Preamble > Historical Rationale for Extensions > ""Zicond"" Extension for Integer Conditional Operations","Two conditional-zero instructions are included: one that writes zero if the comparand is zero, and one that does so if the comparand is nonzero.",unknown,unknown,high,False, +chunk_235ff1dc,src/unpriv/rationale.adoc,65,"Preamble > Historical Rationale for Extensions > ""Zacas"" Extension for Atomic Compare-and-Swap (CAS) Instructions","While compare-and-swap for XLEN wide data may be accomplished using LR/SC, the CAS atomic instructions scale better to highly parallel systems than LR/SC.",non_CSR_parameter,enum,medium,False, +chunk_44100064,src/unpriv/rationale.adoc,65,"Preamble > Historical Rationale for Extensions > ""Zacas"" Extension for Atomic Compare-and-Swap (CAS) Instructions","Many lock-free algorithms, such as a lock-free queue, require manipulation of pointer variables. A simple CAS operation may not be sufficient to guard against what is commonly referred to as the ABA problem in such algorithms that manipulate pointer variables.",non_CSR_parameter,enum,medium,False, +chunk_13377cb9,src/unpriv/rationale.adoc,94,"Preamble > Historical Rationale for Extensions > ""Zabha"" Extension for Byte and Halfword Atomic Memory Operations, Version 1.0",Emulation of narrower AMOs through wider AMO* instructions on non-idempotent IO memory regions may result in unintended side effects.,non_CSR_parameter,enum,medium,False, +chunk_c314bd1f,src/unpriv/rationale.adoc,114,"Preamble > Historical Rationale for Extensions > ""Zfbfmin"" Extension for Scalar BFloat16 Operations","When FP16 (officially called binary16) was first introduced by IEEE 754-2008, it was just an interchange format.",unknown,unknown,high,False, +chunk_5195fae5,src/unpriv/rationale.adoc,132,"Preamble > Historical Rationale for Extensions > ""Zfbfmin"" Extension for Scalar BFloat16 Operations","However, they also found that intermediate values were much better when accumulated into a higher precision.",unknown,unknown,high,False, +chunk_0ea19875,src/unpriv/rationale.adoc,132,"Preamble > Historical Rationale for Extensions > ""Zfbfmin"" Extension for Scalar BFloat16 Operations",There was the added benefit that smaller multiplication blocks could be created for the FP16's smaller number of significant bits.,unknown,unknown,high,False, +chunk_4f394264,src/unpriv/rationale.adoc,132,"Preamble > Historical Rationale for Extensions > ""Zfbfmin"" Extension for Scalar BFloat16 Operations","Also, more complicated dot product instructions started to show up including those that packed two FP16 numbers in a 32-bit register, multiplied these by another pair of FP16 numbers in another register, added these two products to an FP32 accumulate value in a 3rd register and returned an FP32 result.",non_CSR_parameter,range,medium,False, +chunk_2fe988cf,src/unpriv/rationale.adoc,146,"Preamble > Historical Rationale for Extensions > ""Zfbfmin"" Extension for Scalar BFloat16 Operations","Experts working in machine learning at Google who continued to work with FP32 values noted that the least significant 16 bits of their mantissas were not always needed for good results, even in training.",non_CSR_parameter,range,high,False, +chunk_27f3ac82,src/unpriv/rationale.adoc,146,"Preamble > Historical Rationale for Extensions > ""Zfbfmin"" Extension for Scalar BFloat16 Operations","They proposed a truncated version of FP32, which was the 16 most significant bits of the FP32 encoding.",unknown,enum,high,False, +chunk_8c52a393,src/unpriv/rationale.adoc,146,"Preamble > Historical Rationale for Extensions > ""Zfbfmin"" Extension for Scalar BFloat16 Operations","Not only did they find that the number of significant bits in BF16 tended to be sufficient for their work (despite being fewer than in FP16), but it was very easy for them to reuse their existing data; FP32 numbers could be readily rounded to BF16 with a minimal amount of work.",unknown,unknown,high,False, +chunk_cf9d7b18,src/unpriv/rationale.adoc,146,"Preamble > Historical Rationale for Extensions > ""Zfbfmin"" Extension for Scalar BFloat16 Operations","Furthermore, the even smaller number of the BF16 significant bits enabled even smaller multiplication blocks to be built.",unknown,binary,high,False, +chunk_857b01d9,src/unpriv/rv-32-64g.adoc,4,Preamble > RV32/64G Instruction Set Listings,"For this purpose, we define a combination of a base ISA (RV32I or RV64I) plus selected standard extensions (IMAFD, Zicsr, Zifencei) as a ""general-purpose"" ISA, and we use the abbreviation G for the IMAFDZicsrZifencei combination of instruction-set extensions.",CSR_controlled,enum,high,False, +chunk_b8fd51b4,src/unpriv/rv-32-64g.adoc,24,Preamble > RV32/64G Instruction Set Listings,Opcodes marked as reserved should be avoided for custom instruction-set extensions as they might be used by future standard extensions.,non_CSR_parameter,enum,medium,False, +chunk_bef23743,src/unpriv/rv-32-64g.adoc,24,Preamble > RV32/64G Instruction Set Listings,Major opcodes marked as custom-0 through custom-3 will be avoided by future standard extensions and are recommended for use by custom instruction-set extensions within the base 32-bit instruction format.,non_CSR_parameter,range,medium,False, +chunk_710bb04f,src/unpriv/rv-32-64g.adoc,141,Preamble > RV32/64G Instruction Set Listings,| 15+^|*RV32/RV64 Zicsr Standard Extension* 6+^|csr 2+^|rs1 2+^|001 2+^|rd 2+^|1110011 <|CSRRW 6+^|csr 2+^|rs1 2+^|010 2+^|rd 2+^|1110011 <|CSRRS 6+^|csr 2+^|rs1 2+^|011 2+^|rd 2+^|1110011 <|CSRRC 6+^|csr 2+^|uimm 2+^|101 2+^|rd 2+^|1110011 <|CSRRWI 6+^|csr 2+^|uimm 2+^|110 2+^|rd 2+^|1110011 <|CSRRSI 6+^|csr 2+^|uimm 2+^|111 2+^|rd 2+^|1110011 <|CSRRCI |,CSR_controlled,enum,high,False, +chunk_2ab5c1f5,src/unpriv/rv-32-64g.adoc,440,Preamble > RV32/64G Instruction Set Listings,lists the CSRs that have currently been allocated CSR addresses.,CSR_controlled,enum,high,False, +chunk_ff91fe55,src/unpriv/rv-32-64g.adoc,440,Preamble > RV32/64G Instruction Set Listings,"The timers, counters, and floating-point CSRs are the only CSRs defined in this specification.",CSR_controlled,enum,high,False, +chunk_e1e9daab,src/unpriv/rvwmo.adoc,12,"Preamble > RVWMO Memory Consistency Model, Version 2.0","Under RVWMO, code running on a single hart appears to execute in order from the perspective of other memory instructions in the same hart, but memory instructions from another hart may observe the memory instructions from the first hart being executed in a different order.",non_CSR_parameter,enum,medium,False, +chunk_6f3f6606,src/unpriv/rvwmo.adoc,12,"Preamble > RVWMO Memory Consistency Model, Version 2.0","Therefore, multithreaded code may require explicit synchronization to guarantee ordering between memory instructions from different harts.",non_CSR_parameter,enum,medium,False, +chunk_5dc56f14,src/unpriv/rvwmo.adoc,61,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives","Each aligned memory instruction that accesses XLEN or fewer bits gives rise to exactly one memory operation, unless specified otherwise.",unknown,unknown,high,False, +chunk_784a1731,src/unpriv/rvwmo.adoc,66,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives",A misaligned load or store instruction may be decomposed into a set of component memory operations of any granularity. A floating-point load or store of more than XLEN bits may also be decomposed into a set of component memory operations of any granularity.,non_CSR_parameter,range,high,False, +chunk_fdd7c4e4,src/unpriv/rvwmo.adoc,66,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives","However, if misaligned atomics are supported via the misaligned atomicity granule PMA, then AMOs within an atomicity granule are not decomposed, nor are loads and stores defined in the base ISAs, nor are loads and stores of no more than XLEN bits defined in the F, D, and Q extensions.",unknown,range,high,False, +chunk_b31d964e,src/unpriv/rvwmo.adoc,82,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives","An LR instruction and an SC instruction are said to be paired if the LR precedes the SC in program order and if there are no other LR or SC instructions in between; the corresponding memory operations are said to be paired as well (except in case of a failed SC, where no store operation is generated).",unknown,unknown,high,False, +chunk_b7d10a09,src/unpriv/rvwmo.adoc,82,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives","The complete list of conditions determining whether an SC must succeed, may succeed, or must fail is defined in .",non_CSR_parameter,enum,very_high,False, +chunk_b2c41f08,src/unpriv/rvwmo.adoc,90,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives","Load and store operations may also carry one or more ordering annotations from the following set: ""acquire-RCpc"", ""acquire-RCsc"", ""release-RCpc"", and ""release-RCsc"".",non_CSR_parameter,enum,medium,False, +chunk_d93d82e0,src/unpriv/rvwmo.adoc,112,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives > Syntactic Dependencies","In the context of defining dependencies, a register refers either to an entire general-purpose register, some portion of a CSR, or an entire CSR.",CSR_controlled,enum,high,False, +chunk_f15b72fa,src/unpriv/rvwmo.adoc,112,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives > Syntactic Dependencies",The granularity at which dependencies are tracked through CSRs is specific to each CSR and is defined in .,CSR_controlled,enum,high,False, +chunk_1ada0fd0,src/unpriv/rvwmo.adoc,129,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives > Syntactic Dependencies","In the opcode of i, rs1, rs2, or rs3 is set to r * i is a CSR instruction, and in the opcode of i, csr is set to r, unless i is CSRRW or CSRRWI and rd is set to `x0` * r is a CSR and an implicit source register for i, as defined in * r is a CSR that aliases with another source register for i",CSR_controlled,enum,high,False, +chunk_16373aa0,src/unpriv/rvwmo.adoc,146,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives > Syntactic Dependencies","In the opcode of i, rd is set to r * i is a CSR instruction, and in the opcode of i, csr is set to r, unless i is CSRRS or CSRRC and rs1 is set to `x0` or i is CSRRSI or CSRRCI and uimm[4:0] is set to zero. * r is a CSR and an implicit destination register for i, as defined in * r is a CSR that aliases with another destination register for i",CSR_controlled,binary,high,False, +chunk_be1f6a58,src/unpriv/rvwmo.adoc,160,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives > Syntactic Dependencies",Instruction j has a syntactic dependency on instruction i via destination register s of i and source register r of j if either of the following hold:,unknown,enum,high,False, +chunk_db9ecc3c,src/unpriv/rvwmo.adoc,182,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives > Syntactic Dependencies",b has a syntactic address dependency on a if r is an address source register for j and j has a syntactic dependency on i via source register r,unknown,unknown,high,False, +chunk_cf6fb098,src/unpriv/rvwmo.adoc,187,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives > Syntactic Dependencies","b has a syntactic data dependency on a if b is a store operation, r is a data source register for j, and j has a syntactic dependency on i via source register r",unknown,unknown,high,False, +chunk_6a261dea,src/unpriv/rvwmo.adoc,192,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives > Syntactic Dependencies",b has a syntactic control dependency on a if there is an instruction m program-ordered between i and j such that m is a branch or indirect jump and m has a syntactic dependency on i.,unknown,unknown,high,False, +chunk_3162a1b3,src/unpriv/rvwmo.adoc,200,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives > Preserved Program Order",The subset of program order that must be respected by the global memory order is known as preserved program order.,non_CSR_parameter,enum,very_high,False, +chunk_532077c9,src/unpriv/rvwmo.adoc,244,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives > Memory Model Axioms","An execution of a RISC-V program obeys the RVWMO memory consistency model only if there exists a global memory order conforming to preserved program order and satisfying the load value axiom, the atomicity axiom, and the progress axiom.",unknown,unknown,high,False, +chunk_a0e2af4f,src/unpriv/rvwmo.adoc,267,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives > Memory Model Axioms > Atomicity Axiom","If r and w are paired load and store operations generated by aligned LR and SC instructions in a hart h, s is a store to byte x, and r returns a value written by s, then s must precede w in the global memory order, and there can be no store from a hart other than h to byte x following s and preceding w in the global memory order.",non_CSR_parameter,binary,very_high,False, +chunk_64452d3c,src/unpriv/rvwmo.adoc,279,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives > Memory Model Axioms > Progress Axiom",No memory operation may be preceded in the global memory order by an infinite sequence of other memory operations.,non_CSR_parameter,enum,medium,False, +chunk_3a68286d,src/unpriv/rvwmo.adoc,301,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings",This section provides a concrete listing of the source and destination registers for each instruction.,unknown,unknown,high,False, +chunk_02a1679a,src/unpriv/rvwmo.adoc,301,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings",These listings are used in the definition of syntactic dependencies in .,unknown,unknown,high,False, +chunk_bd985468,src/unpriv/rvwmo.adoc,306,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings","The term ""accumulating CSR"" is used to describe a CSR that is both a source and a destination register, but which carries a dependency only from itself to itself.",CSR_controlled,enum,high,False, +chunk_94c569c7,src/unpriv/rvwmo.adoc,310,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings","Instructions carry a dependency from each source register in the ""Source Registers"" column to each destination register in the ""Destination Registers"" column, from each source register in the ""Source Registers"" column to each CSR in the ""Accumulating CSRs"" column, and from each CSR in the ""Accumulating CSRs"" column to itself, except where annotated otherwise.",CSR_controlled,enum,high,False, +chunk_eb508f38,src/unpriv/rvwmo.adoc,323,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings",† The instruction does not carry a dependency from any source register to any destination register,unknown,unknown,high,False, +chunk_09e4ddfb,src/unpriv/rvwmo.adoc,326,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings",‡ The instruction carries dependencies from source register(s) to destination register(s) as specified,unknown,unknown,high,False, +chunk_0c1f40f9,src/unpriv/rvwmo.adoc,364,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings","|SB |rs1 ^A^, rs2 ^D^ | ||",unknown,unknown,high,False, +chunk_f73a2887,src/unpriv/rvwmo.adoc,366,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings","|SH |rs1 ^A^, rs2 ^D^ | ||",unknown,unknown,high,False, +chunk_260bfd13,src/unpriv/rvwmo.adoc,368,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings","|SW |rs1 ^A^, rs2 ^D^ | ||",unknown,unknown,high,False, +chunk_4c6482ae,src/unpriv/rvwmo.adoc,416,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings","|CSRRW‡ |rs1, csr^*^ | rd, csr | |^*^unless rd=`x0`",CSR_controlled,enum,high,False, +chunk_e7fedf34,src/unpriv/rvwmo.adoc,418,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings",5+| ‡ carries a dependency from rs1 to csr and from csr to rd,CSR_controlled,enum,high,False, +chunk_d2694b71,src/unpriv/rvwmo.adoc,420,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings","|CSRRS‡ |rs1, csr |rd, csr^*^ | |^*^unless rs1=`x0`",CSR_controlled,enum,high,False, +chunk_ec44493a,src/unpriv/rvwmo.adoc,422,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings","|CSRRC‡ |rs1, csr |rd, csr^*^ | |^*^unless rs1=`x0`",CSR_controlled,enum,high,False, +chunk_808134f7,src/unpriv/rvwmo.adoc,424,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings",5+| ‡ carries a dependency from csr and rs1 to csr and from csr to rd,CSR_controlled,enum,high,False, +chunk_912b1614,src/unpriv/rvwmo.adoc,426,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings","|CSRRWI ‡ |csr ^*^ |rd, csr | |^*^unless rd=x0",CSR_controlled,enum,high,False, +chunk_47e30892,src/unpriv/rvwmo.adoc,428,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings",5+| ‡ carries a dependency from csr to rd,CSR_controlled,enum,high,False, +chunk_30cea04f,src/unpriv/rvwmo.adoc,430,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings","|CSRRSI ‡ |csr |rd, csr^*^ | |^*^unless uimm[4:0]=0",CSR_controlled,enum,high,False, +chunk_71e35c9f,src/unpriv/rvwmo.adoc,432,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings","|CSRRCI ‡ |csr |rd, csr^*^ | |^*^unless uimm[4:0]=0",CSR_controlled,enum,high,False, +chunk_8363fc78,src/unpriv/rvwmo.adoc,434,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings",5+| ‡ carries a dependency from csr to rd and csr |,CSR_controlled,enum,high,False, +chunk_8c70a0f0,src/unpriv/rvwmo.adoc,446,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings","|SD |rs1 ^A^, rs2 ^D^ | | |",unknown,unknown,high,False, +chunk_7b663cbd,src/unpriv/rvwmo.adoc,518,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings","|SC.W† | rs1 ^A^, rs2 ^D^ | rd ^*^ | | ^*^ if successful",unknown,unknown,high,False, +chunk_11c25b5d,src/unpriv/rvwmo.adoc,520,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings","|AMOSWAP.W† |rs1 ^A^, rs2 ^D^ |rd | |",unknown,unknown,high,False, +chunk_eaa0499a,src/unpriv/rvwmo.adoc,522,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings","|AMOADD.W† |rs1 ^A^, rs2 ^D^ |rd | |",unknown,unknown,high,False, +chunk_4e95c968,src/unpriv/rvwmo.adoc,524,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings","|AMOXOR.W† |rs1 ^A^, rs2 ^D^ |rd | |",unknown,unknown,high,False, +chunk_79424408,src/unpriv/rvwmo.adoc,526,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings","|AMOAND.W† |rs1 ^A^, rs2 ^D^ |rd | |",unknown,unknown,high,False, +chunk_3ee2089c,src/unpriv/rvwmo.adoc,528,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings","|AMOOR.W† |rs1 ^A^, rs2^D^ |rd | |",unknown,unknown,high,False, +chunk_941e3e19,src/unpriv/rvwmo.adoc,530,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings","|AMOMIN.W† |rs1 ^A^, rs2 ^D^ |rd | |",unknown,unknown,high,False, +chunk_c29eceb4,src/unpriv/rvwmo.adoc,532,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings","|AMOMAX.W† |rs1 ^A^, rs2 ^D^ |rd | |",unknown,unknown,high,False, +chunk_35051788,src/unpriv/rvwmo.adoc,534,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings","|AMOMINU.W† |rs1 ^A^, rs2 ^D^ |rd | |",unknown,unknown,high,False, +chunk_d73d8ffd,src/unpriv/rvwmo.adoc,536,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings","|AMOMAXU.W† |rs1 ^A^, rs2 ^D^ |rd | |",unknown,unknown,high,False, +chunk_3592c98a,src/unpriv/rvwmo.adoc,544,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings",| |Source Registers |Destination Registers |Accumulating CSRs|,CSR_controlled,enum,high,False, +chunk_21abad7e,src/unpriv/rvwmo.adoc,548,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings","|SC.D† |rs1 ^A^, rs2 ^D^ |rd ^*^ | |^*^if successful",unknown,unknown,high,False, +chunk_115bb9ed,src/unpriv/rvwmo.adoc,550,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings","|AMOSWAP.D† |rs1 ^A^, rs2 ^D^ |rd | |",unknown,unknown,high,False, +chunk_6d869cbd,src/unpriv/rvwmo.adoc,552,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings","|AMOADD.D† |rs1 ^A^, rs2 ^D^ |rd | |",unknown,unknown,high,False, +chunk_0c1ecf64,src/unpriv/rvwmo.adoc,554,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings","|AMOXOR.D† |rs1 ^A^, rs2 ^D^ |rd | |",unknown,unknown,high,False, +chunk_23001182,src/unpriv/rvwmo.adoc,556,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings","|AMOAND.D† |rs1 ^A^, rs2^D^ |rd | |",unknown,unknown,high,False, +chunk_36d6fdae,src/unpriv/rvwmo.adoc,558,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings","|AMOOR.D† |rs1 ^A^, rs2^D^ |rd | |",unknown,unknown,high,False, +chunk_68c267d6,src/unpriv/rvwmo.adoc,560,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings","|AMOMIN.D† |rs1 ^A^, rs2^D^ |rd | |",unknown,unknown,high,False, +chunk_76f5def4,src/unpriv/rvwmo.adoc,562,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings","|AMOMAX.D† |rs1 ^A^, rs2^D^ |rd | |",unknown,unknown,high,False, +chunk_416480ee,src/unpriv/rvwmo.adoc,564,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings","|AMOMINU.D† |rs1 ^A^, rs2^D^ |rd | |",unknown,unknown,high,False, +chunk_d8764f68,src/unpriv/rvwmo.adoc,566,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings","|AMOMAXU.D† |rs1 ^A^, rs2^D^ |rd | |",unknown,unknown,high,False, +chunk_b99486ff,src/unpriv/rvwmo.adoc,574,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings",| |Source Registers |Destination Registers |Accumulating CSRs |,CSR_controlled,enum,high,False, +chunk_edbda2b0,src/unpriv/rvwmo.adoc,578,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings","|FSW |rs1 ^A^, rs2^D^ | | |",unknown,unknown,high,False, +chunk_5b9c96dc,src/unpriv/rvwmo.adoc,580,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings","|FMADD.S |rs1, rs2, rs3, frm^*^ |rd |NV, OF, UF, NX |^*^if rm=111",CSR_controlled,enum,high,False, +chunk_fbe8ff47,src/unpriv/rvwmo.adoc,582,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings","|FMSUB.S |rs1, rs2, rs3, frm^*^ |rd |NV, OF, UF, NX |^*^if rm=111",CSR_controlled,enum,high,False, +chunk_e4920414,src/unpriv/rvwmo.adoc,584,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings","|FNMSUB.S |rs1, rs2, rs3, frm^*^ |rd |NV, OF, UF, NX |^*^if rm=111",CSR_controlled,enum,high,False, +chunk_6f2b4126,src/unpriv/rvwmo.adoc,586,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings","|FNMADD.S |rs1, rs2, rs3, frm^*^ |rd |NV, OF, UF, NX |^*^if rm=111",CSR_controlled,enum,high,False, +chunk_79ea3ec5,src/unpriv/rvwmo.adoc,588,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings","|FADD.S |rs1, rs2, frm^*^ |rd |NV, OF, NX |^*^if rm=111",CSR_controlled,enum,high,False, +chunk_e671e6f7,src/unpriv/rvwmo.adoc,590,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings","|FSUB.S |rs1, rs2, frm^*^ |rd |NV, OF, NX |^*^if rm=111",CSR_controlled,enum,high,False, +chunk_afbfc9cd,src/unpriv/rvwmo.adoc,592,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings","|FMUL.S |rs1, rs2, frm^*^ |rd |NV, OF, UF, NX |^*^if rm=111",CSR_controlled,enum,high,False, +chunk_2d7d8425,src/unpriv/rvwmo.adoc,594,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings","|FDIV.S |rs1, rs2, frm^*^ |rd |NV, DZ, OF, UF, NX |^*^if rm=111",CSR_controlled,enum,high,False, +chunk_2c13306d,src/unpriv/rvwmo.adoc,596,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings","|FSQRT.S |rs1, frm^*^ |rd |NV, NX |^*^if rm=111",CSR_controlled,enum,high,False, +chunk_6682f234,src/unpriv/rvwmo.adoc,608,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings","|FCVT.W.S |rs1, frm^*^ |rd |NV, NX |^*^if rm=111",CSR_controlled,enum,high,False, +chunk_3e268352,src/unpriv/rvwmo.adoc,610,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings","|FCVT.WU.S |rs1, frm^*^ |rd |NV, NX |^*^if rm=111",CSR_controlled,enum,high,False, +chunk_a5a34544,src/unpriv/rvwmo.adoc,622,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings","|FCVT.S.W |rs1, frm^*^ |rd |NX |^*^if rm=111",CSR_controlled,enum,high,False, +chunk_072586d2,src/unpriv/rvwmo.adoc,624,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings","|FCVT.S.WU |rs1, frm^*^ |rd |NX |^*^if rm=111",CSR_controlled,enum,high,False, +chunk_c37888b0,src/unpriv/rvwmo.adoc,635,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings","|FCVT.L.S |rs1, frm^*^ |rd |NV, NX |^*^if rm=111",CSR_controlled,enum,high,False, +chunk_9ab888b8,src/unpriv/rvwmo.adoc,637,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings","|FCVT.LU.S |rs1, frm^*^ |rd |NV, NX |^*^if rm=111",CSR_controlled,enum,high,False, +chunk_afe1342f,src/unpriv/rvwmo.adoc,639,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings","|FCVT.S.L |rs1, frm^*^ |rd |NX |^*^if rm=111",CSR_controlled,enum,high,False, +chunk_6b88806d,src/unpriv/rvwmo.adoc,641,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings","|FCVT.S.LU |rs1, frm^*^ |rd |NX |^*^if rm=111",CSR_controlled,enum,high,False, +chunk_a66eb6c0,src/unpriv/rvwmo.adoc,649,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings",| |Source Registers|Destination Registers |Accumulating CSRs |,CSR_controlled,enum,high,False, +chunk_a4a50509,src/unpriv/rvwmo.adoc,653,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings","|FSD |rs1 ^A^, rs2^D^ | | |",unknown,unknown,high,False, +chunk_705d3b96,src/unpriv/rvwmo.adoc,655,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings","|FMADD.D |rs1, rs2, rs3, frm^*^ |rd |NV, OF, UF, NX |^*^if rm=111",CSR_controlled,enum,high,False, +chunk_56b9d465,src/unpriv/rvwmo.adoc,657,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings","|FMSUB.D |rs1, rs2, rs3, frm^*^ |rd |NV, OF, UF, NX |^*^if rm=111",CSR_controlled,enum,high,False, +chunk_fac89de9,src/unpriv/rvwmo.adoc,659,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings","|FNMSUB.D |rs1, rs2, rs3, frm^*^ |rd |NV, OF, UF, NX |^*^if rm=111",CSR_controlled,enum,high,False, +chunk_ed337e7e,src/unpriv/rvwmo.adoc,661,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings","|FNMADD.D |rs1, rs2, rs3, frm^*^ |rd |NV, OF, UF, NX |^*^if rm=111",CSR_controlled,enum,high,False, +chunk_1d2989a9,src/unpriv/rvwmo.adoc,663,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings","|FADD.D |rs1, rs2, frm^*^ |rd |NV, OF, NX |^*^if rm=111",CSR_controlled,enum,high,False, +chunk_f094ea7f,src/unpriv/rvwmo.adoc,665,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings","|FSUB.D |rs1, rs2, frm^*^ |rd |NV, OF, NX |^*^if rm=111",CSR_controlled,enum,high,False, +chunk_19adc169,src/unpriv/rvwmo.adoc,667,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings","|FMUL.D |rs1, rs2, frm^*^ |rd |NV, OF, UF, NX |^*^if rm=111",CSR_controlled,enum,high,False, +chunk_c3aff269,src/unpriv/rvwmo.adoc,669,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings","|FDIV.D |rs1, rs2, frm^*^ |rd |NV, DZ, OF, UF, NX |^*^if rm=111",CSR_controlled,enum,high,False, +chunk_edbf9995,src/unpriv/rvwmo.adoc,671,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings","|FSQRT.D |rs1, frm^*^ |rd |NV, NX |^*^if rm=111",CSR_controlled,enum,high,False, +chunk_a4e7a7f8,src/unpriv/rvwmo.adoc,683,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings","|FCVT.S.D |rs1, frm^*^ |rd |NV, OF, UF, NX |^*^if rm=111",CSR_controlled,enum,high,False, +chunk_f00b9ccb,src/unpriv/rvwmo.adoc,695,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings","|FCVT.W.D |rs1, frm^*^ |rd |NV, NX |^*^if rm=111",CSR_controlled,enum,high,False, +chunk_e3489cdd,src/unpriv/rvwmo.adoc,697,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings","|FCVT.WU.D |rs1, frm^*^ |rd |NV, NX |^*^if rm=111",CSR_controlled,enum,high,False, +chunk_caa62920,src/unpriv/rvwmo.adoc,709,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings",| |Source Registers |Destination Registers |Accumulating CSRs |,CSR_controlled,enum,high,False, +chunk_5cba4c09,src/unpriv/rvwmo.adoc,711,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings","|FCVT.L.D |rs1, frm^*^ |rd |NV, NX |^*^if rm=111",CSR_controlled,enum,high,False, +chunk_5b6ba479,src/unpriv/rvwmo.adoc,713,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings","|FCVT.LU.D |rs1, frm^*^ |rd |NV, NX |^*^if rm=111",CSR_controlled,enum,high,False, +chunk_4cbb1b04,src/unpriv/rvwmo.adoc,717,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings","|FCVT.D.L |rs1, frm^*^ |rd |NX |^*^if rm=111",CSR_controlled,enum,high,False, +chunk_95a1cbdd,src/unpriv/rvwmo.adoc,719,"Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings","|FCVT.D.LU |rs1, frm^*^ |rd |NX |^*^if rm=111",CSR_controlled,enum,high,False, +chunk_cea6364f,src/unpriv/vector-examples.adoc,13,Preamble > Vector Assembly Code Examples > Vector-vector add example > Example with mixed-width mask and compute.,"---- Code using one width for predicate and different width for masked compute. int8t a[]; int32t b[], c[]; for (i=0; i Vector Assembly Code Examples > Vector-vector add example > Example with mixed-width mask and compute.,"vsetvli x0, a0, e32, m4, ta, mu Vector of 32-bit values. sub a0, a0, a4 Decrement count vmv.v.i v4, 1 Splat immediate to destination vle32.v v4, (a3), v0.t Load requested elements of C, others undisturbed sll t1, a4, 2 add a3, a3, t1 Bump pointer. vse32.v v4, (a2) Store b[i]. add a2, a2, t1 Bump pointer. bnez a0, loop Any more? ----",CSR_controlled,range,high,False, +chunk_aa783c15,src/unpriv/vector-examples.adoc,49,Preamble > Vector Assembly Code Examples > Vector-vector add example > Conditional example,"loop: vsetvli t0, a0, e8, m1, ta, ma Use 8b elements. vle8.v v0, (a1) Get x[i] sub a0, a0, t0 Decrement element count add a1, a1, t0 x[i] Bump pointer vmslt.vi v0, v0, 5 Set mask in v0 vsetvli x0, x0, e16, m2, ta, mu Use 16b elements. slli t0, t0, 1 Multiply by 2 bytes vle16.v v2, (a2), v0.t z[i] = a[i] case vmnot.m v0, v0 Invert v0 add a2, a2, t0 a[i] bump pointer vle16.v v2, (a3), v0.t z[i] = b[i] case add a3, a3, t0 b[i] bump pointer vse16.v v2, (a4) Store z add a4, a4, t0 z[i] bump pointer bnez a0, loop ----",CSR_controlled,range,high,False, +chunk_745c57da,src/unpriv/vector-examples.adoc,80,Preamble > Vector Assembly Code Examples > Vector-vector add example > Division approximation example,---- v1 = v1 / v2 to almost 23 bits of precision.,non_CSR_parameter,range,medium,False, +chunk_8a9760cd,src/unpriv/vector-examples.adoc,96,Preamble > Vector Assembly Code Examples > Vector-vector add example > Square root approximation example,---- v1 = sqrt(v1) to more than 23 bits of precision.,non_CSR_parameter,range,medium,False, +chunk_9bece716,src/unpriv/vector-examples.adoc,99,Preamble > Vector Assembly Code Examples > Vector-vector add example > Square root approximation example,"fmv.w.x ft0, x0 Mask off zero inputs vmfne.vf v0, v1, ft0 to avoid DZ exception vfrsqrt7.v v2, v1, v0.t Estimate r ~= 1/sqrt(v1) vmfne.vf v0, v2, ft0, v0.t Mask off +inf to avoid NV li t0, 0x3f800000 fli.s ft0, 0.5 vmv.v.x v5, t0 Splat 1.0 vfmul.vv v3, v1, v2, v0.t t = v1 r vfmul.vf v4, v2, ft0, v0.t 0.5 r vfmsub.vv v3, v2, v5, v0.t t r - 1 vfnmsac.vv v2, v3, v4, v0.t r - (0.5 r) (t r - 1) Better estimate of 1/sqrt(v1) vfmul.vv v1, v1, v2, v0.t t = v1 r vfmsub.vv v2, v1, v5, v0.t t r - 1 vfmul.vf v3, v1, ft0, v0.t 0.5 t vfnmsac.vv v1, v2, v3, v0.t t - (0.5 t) (t r - 1) ~ sqrt(v1) to about 23.3 bits ----",non_CSR_parameter,range,high,False, +chunk_1847da71,src/unpriv/vector-examples.adoc,152,Preamble > Vector Assembly Code Examples > Vector-vector add example > Fractional LMUL example,The compiler realizes there are two datatypes within the loop: an 8-bit 'char' and a 64-bit 'long *'.,non_CSR_parameter,range,medium,False, +chunk_4a871b13,src/unpriv/vector-examples.adoc,152,Preamble > Vector Assembly Code Examples > Vector-vector add example > Fractional LMUL example,"Without fractional LMUL, the compiler would be forced to use LMUL=1 for the 8-bit computation and LMUL=8 for the 64-bit computation(s), to have equal number of elements on all computations within the same loop iteration.",non_CSR_parameter,range,medium,False, +chunk_a4519941,src/unpriv/vector-examples.adoc,152,Preamble > Vector Assembly Code Examples > Vector-vector add example > Fractional LMUL example,"Given the large number of 64-bit variables and temporaries required in this loop, the compiler ends up generating a lot of spill code.",non_CSR_parameter,range,medium,False, +chunk_fabb674b,src/unpriv/vector-examples.adoc,162,Preamble > Vector Assembly Code Examples > Vector-vector add example > Fractional LMUL example,"---- .LBB04: %vector.body =>This Inner Loop Header: Depth=1 add s9, a2, s6 vsetvli s1, zero, e8,m1,ta,mu vle8.v v25, (s9) add s1, a3, s6 vle8.v v26, (s1) vadd.vv v25, v26, v25 add s1, a1, s6 vse8.v v25, (s1) add s9, a5, s10 vsetvli s1, zero, e64,m8,ta,mu vle64.v v8, (s9) add s1, a6, s10 vle64.v v16, (s1) add s1, a7, s10 vle64.v v24, (s1) add s1, s3, s10 vle64.v v0, (s1) sd a0, -112(s0) ld a0, -128(s0) vs8r.v v0, (a0) Spill LMUL=8 add s9, t6, s10 add s11, t5, s10 add ra, t2, s10 add s1, t3, s10 vle64.v v0, (s9) ld s9, -136(s0) vs8r.v v0, (s9) Spill LMUL=8 vle64.v v0, (s11) ld s9, -144(s0) vs8r.v v0, (s9) Spill LMUL=8 vle64.v v0, (ra) ld s9, -160(s0) vs8r.v v0, (s9) Spill LMUL=8 vle64.v v0, (s1) ld s1, -152(s0) vs8r.v v0, (s1) Spill LMUL=8 vadd.vv v16, v16, v8 ld s1, -128(s0) vl8r.v v8, (s1) Reload LMUL=8 vadd.vv v8, v8, v24 ld s1, -136(s0) vl8r.v v24, (s1) Reload LMUL=8 ld s1, -144(s0) vl8r.v v0, (s1) Reload LMUL=8 vadd.vv v24, v0, v24 ld s1, -128(s0) vs8r.v v24, (s1) Spill LMUL=8 ld s1, -152(s0) vl8r.v v0, (s1) Reload LMUL=8 ld s1, -160(s0) vl8r.v v24, (s1) Reload LMUL=8 vadd.vv v0, v0, v24 add s1, a4, s10 vse64.v v16, (s1) add s1, s2, s10 vse64.v v8, (s1) vadd.vv v8, v8, v16 add s1, t4, s10 ld s9, -128(s0) vl8r.v v16, (s9) Reload LMUL=8 vse64.v v16, (s1) add s9, t0, s10 vadd.vv v8, v8, v16 vle64.v v16, (s9) add s1, t1, s10 vse64.v v0, (s1) vadd.vv v8, v8, v0 vsll.vi v16, v16, 1 vadd.vv v8, v8, v16 vse64.v v8, (s9) add s6, s6, s7 add s10, s10, s8 bne s6, s4, .LBB04 ----",CSR_controlled,enum,high,False, +chunk_39ed75db,src/unpriv/vector-examples.adoc,247,Preamble > Vector Assembly Code Examples > Vector-vector add example > Fractional LMUL example,"---- .LBB04: %vector.body =>This Inner Loop Header: Depth=1 add s9, a2, s6 vsetvli s1, zero, e8,mf2,ta,mu // LMUL=1/2 ! vle8.v v25, (s9) add s1, a3, s6 vle8.v v26, (s1) vadd.vv v25, v26, v25 add s1, a1, s6 vse8.v v25, (s1) add s9, a5, s10 vsetvli s1, zero, e64,m4,ta,mu // LMUL=4 vle64.v v28, (s9) add s1, a6, s10 vle64.v v8, (s1) vadd.vv v28, v8, v28 add s1, a7, s10 vle64.v v8, (s1) add s1, s3, s10 vle64.v v12, (s1) add s1, t6, s10 vle64.v v16, (s1) add s1, t5, s10 vle64.v v20, (s1) add s1, a4, s10 vse64.v v28, (s1) vadd.vv v8, v12, v8 vadd.vv v12, v20, v16 add s1, t2, s10 vle64.v v16, (s1) add s1, t3, s10 vle64.v v20, (s1) add s1, s2, s10 vse64.v v8, (s1) add s9, t4, s10 vadd.vv v16, v20, v16 add s11, t0, s10 vle64.v v20, (s11) vse64.v v12, (s9) add s1, t1, s10 vse64.v v16, (s1) vsll.vi v20, v20, 1 vadd.vv v28, v8, v28 vadd.vv v28, v28, v12 vadd.vv v28, v28, v16 vadd.vv v28, v28, v20 vse64.v v28, (s11) add s6, s6, s7 add s10, s10, s8 bne s6, s4, .LBB04 ----",CSR_controlled,enum,high,False, +chunk_c6ab809e,src/unpriv/za.adoc,28,Preamble > Atomic Instructions > Specifying Ordering of Atomic Instructions,"No ordering constraint is implied to accesses to the other domain, and a FENCE instruction should be used to order across both domains.",SW_rule,enum,medium,False, +chunk_82d7022b,src/unpriv/za.adoc,36,Preamble > Atomic Instructions > Specifying Ordering of Atomic Instructions,"If both bits are clear, no additional ordering constraints are imposed on the atomic memory operation.",unknown,unknown,high,False, +chunk_13a4f9a4,src/unpriv/za.adoc,36,Preamble > Atomic Instructions > Specifying Ordering of Atomic Instructions,"If both the aq and rl bits are set, the atomic memory operation is sequentially consistent and cannot be observed to happen before any earlier memory operations or after any later memory operations in the same RISC-V hart and to the same address domain.",unknown,unknown,high,False, +chunk_3119cc81,src/unpriv/zaamo.adoc,5,"Preamble > ""Zaamo"" Extension for Atomic Memory Operations",The atomic memory operation (AMO) instructions perform read-modify-write operations for multiprocessor synchronization and are encoded with an R-type instruction format.,unknown,enum,high,False, +chunk_ae2d334e,src/unpriv/zaamo.adoc,5,"Preamble > ""Zaamo"" Extension for Atomic Memory Operations","For RV64, 32-bit AMOs always sign-extend the value placed in rd, and ignore the upper 32 bits of the original value of rs2.",non_CSR_parameter,range,high,False, +chunk_b7f66826,src/unpriv/zaamo.adoc,15,"Preamble > ""Zaamo"" Extension for Atomic Memory Operations","If the address is not naturally aligned, an address-misaligned exception or an access-fault exception will be generated.",unknown,unknown,high,False, +chunk_79c3920a,src/unpriv/zaamo.adoc,15,"Preamble > ""Zaamo"" Extension for Atomic Memory Operations","The access-fault exception can be generated for a memory access that would otherwise be able to complete except for the misalignment, if the misaligned access should not be emulated.",non_CSR_parameter,enum,high,False, +chunk_cd713f83,src/unpriv/zaamo.adoc,24,"Preamble > ""Zaamo"" Extension for Atomic Memory Operations","If present, the misaligned atomicity granule PMA specifies the size of a misaligned atomicity granule, a power-of-two number of bytes.",unknown,unknown,high,False, +chunk_313d65cf,src/unpriv/zaamo.adoc,36,"Preamble > ""Zaamo"" Extension for Atomic Memory Operations","The operations supported are swap, integer add, bitwise AND, bitwise OR, bitwise XOR, and signed and unsigned integer maximum and minimum.",unknown,range,high,False, +chunk_585bd9cb,src/unpriv/zaamo.adoc,42,"Preamble > ""Zaamo"" Extension for Atomic Memory Operations","If the aq bit is set, then no later memory operations in this RISC-V hart can be observed to take place before the AMO.",unknown,unknown,high,False, +chunk_f76d65e9,src/unpriv/zaamo.adoc,42,"Preamble > ""Zaamo"" Extension for Atomic Memory Operations","Conversely, if the rl bit is set, then other RISC-V harts will not observe the AMO before memory accesses preceding the AMO in this RISC-V hart.",unknown,unknown,high,False, +chunk_fd5b5a05,src/unpriv/zabha.adoc,16,"Preamble > ""Zabha"" Extension for Byte and Halfword Atomic Memory Operations, Version 1.0",Emulation of narrower AMOs through wider AMO* instructions on non-idempotent IO memory regions may result in unintended side effects.,non_CSR_parameter,enum,medium,False, +chunk_22ee40f0,src/unpriv/zabha.adoc,33,"Preamble > ""Zabha"" Extension for Byte and Halfword Atomic Memory Operations, Version 1.0 > Byte and Halfword Atomic Memory Operation Instructions","If Zacas extension is also implemented, Zabha further provides the `AMOCAS.[B|H]` instructions.",unknown,unknown,high,False, +chunk_c8dcd629,src/unpriv/zabha.adoc,56,"Preamble > ""Zabha"" Extension for Byte and Halfword Atomic Memory Operations, Version 1.0 > Byte and Halfword Atomic Memory Operation Instructions","Similar to the AMOs specified in the A extension, the Zabha extension mandates that the address contained in the `rs1` register must be naturally aligned to the size of the operand.",non_CSR_parameter,enum,very_high,False, +chunk_33521a87,src/unpriv/zabha.adoc,56,"Preamble > ""Zabha"" Extension for Byte and Halfword Atomic Memory Operations, Version 1.0 > Byte and Halfword Atomic Memory Operation Instructions",The same exception options as specified in the A extension are applicable in cases where the address is not naturally aligned.,unknown,unknown,high,False, +chunk_03c75dd7,src/unpriv/zacas.adoc,3,"Preamble > ""Zacas"" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0","This extension defines CAS instructions to operate on 32-bit, 64-bit, and 128-bit (RV64 only) data values.",non_CSR_parameter,range,medium,False, +chunk_26dbebc1,src/unpriv/zacas.adoc,25,"Preamble > ""Zacas"" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 > Word/Doubleword/Quadword CAS (AMOCAS.W/D/Q) Instructions","For RV32, `AMOCAS.W` atomically loads a 32-bit data value from address in `rs1`, compares the loaded value to the 32-bit value held in `rd`, and if the comparison is bitwise equal, then stores the 32-bit value held in `rs2` to the original address in `rs1`.",non_CSR_parameter,range,high,False, +chunk_8ed7eeeb,src/unpriv/zacas.adoc,31,"Preamble > ""Zacas"" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 > Word/Doubleword/Quadword CAS (AMOCAS.W/D/Q) Instructions",[listing] ---- temp = mem[X(rs1)] if ( temp X(rd) ) mem[X(rs1)] = X(rs2) X(rd) = temp ----,unknown,unknown,high,False, +chunk_7526b198,src/unpriv/zacas.adoc,39,"Preamble > ""Zacas"" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 > Word/Doubleword/Quadword CAS (AMOCAS.W/D/Q) Instructions",`AMOCAS.D` is similar to `AMOCAS.W` but operates on 64-bit data values.,non_CSR_parameter,range,medium,False, +chunk_8281b82c,src/unpriv/zacas.adoc,41,"Preamble > ""Zacas"" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 > Word/Doubleword/Quadword CAS (AMOCAS.W/D/Q) Instructions","When the first register of a source register pair is `x0`, then both halves of the pair read as zero.",unknown,unknown,high,False, +chunk_433d4ab0,src/unpriv/zacas.adoc,41,"Preamble > ""Zacas"" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 > Word/Doubleword/Quadword CAS (AMOCAS.W/D/Q) Instructions","When the first register of a destination register pair is `x0`, then the entire register result is discarded and neither destination register is written.",unknown,enum,high,False, +chunk_5aa38207,src/unpriv/zacas.adoc,56,"Preamble > ""Zacas"" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 > Word/Doubleword/Quadword CAS (AMOCAS.W/D/Q) Instructions",[listing] temp0 = mem[X(rs1)+0] temp1 = mem[X(rs1)+4] comp0 = (rd x0) ? 0 : X(rd) comp1 = (rd x0) ? 0 : X(rd+1) swap0 = (rs2 x0) ? 0 : X(rs2) swap1 = (rs2 x0) ? 0 : X(rs2+1) if ( temp0 comp0 ) && ( temp1 comp1 ) mem[X(rs1)+0] = swap0 mem[X(rs1)+4] = swap1 endif if ( rd != x0 ) X(rd) = temp0 X(rd+1) = temp1 endif,unknown,unknown,high,False, +chunk_32959945,src/unpriv/zacas.adoc,72,"Preamble > ""Zacas"" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 > Word/Doubleword/Quadword CAS (AMOCAS.W/D/Q) Instructions","For RV64, `AMOCAS.W` atomically loads a 32-bit data value from address in `rs1`, compares the loaded value to the lower 32 bits of the value held in `rd`, and if the comparison is bitwise equal, then stores the lower 32 bits of the value held in `rs2` to the original address in `rs1`.",non_CSR_parameter,range,high,False, +chunk_c538c32b,src/unpriv/zacas.adoc,72,"Preamble > ""Zacas"" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 > Word/Doubleword/Quadword CAS (AMOCAS.W/D/Q) Instructions",The 32-bit value loaded from memory is sign-extended and is placed into register `rd`.,non_CSR_parameter,range,high,False, +chunk_bc2892e6,src/unpriv/zacas.adoc,79,"Preamble > ""Zacas"" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 > Word/Doubleword/Quadword CAS (AMOCAS.W/D/Q) Instructions",[listing] temp[31:0] = mem[X(rs1)] if ( temp[31:0] X(rd)[31:0] ) mem[X(rs1)] = X(rs2)[31:0] X(rd) = SignExtend(temp[31:0]),unknown,unknown,high,False, +chunk_2e5194bc,src/unpriv/zacas.adoc,85,"Preamble > ""Zacas"" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 > Word/Doubleword/Quadword CAS (AMOCAS.W/D/Q) Instructions","For RV64, `AMOCAS.D` atomically loads 64-bits of a data value from address in `rs1`, compares the loaded value to a 64-bit value held in `rd`, and if the comparison is bitwise equal, then stores the 64-bit value held in `rs2` to the original address in `rs1`.",non_CSR_parameter,range,high,False, +chunk_8cfea027,src/unpriv/zacas.adoc,85,"Preamble > ""Zacas"" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 > Word/Doubleword/Quadword CAS (AMOCAS.W/D/Q) Instructions",The operation performed by `AMOCAS.D` for RV64 is as follows: [listing] temp = mem[X(rs1)] if ( temp X(rd) ) mem[X(rs1)] = X(rs2) X(rd) = temp,unknown,unknown,high,False, +chunk_c1f0e826,src/unpriv/zacas.adoc,96,"Preamble > ""Zacas"" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 > Word/Doubleword/Quadword CAS (AMOCAS.W/D/Q) Instructions","When the first register of a source register pair is `x0`, then both halves of the pair read as zero.",unknown,unknown,high,False, +chunk_bf618e59,src/unpriv/zacas.adoc,96,"Preamble > ""Zacas"" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 > Word/Doubleword/Quadword CAS (AMOCAS.W/D/Q) Instructions","When the first register of a destination register pair is `x0`, then the entire register result is discarded and neither destination register is written.",unknown,enum,high,False, +chunk_6d473f6f,src/unpriv/zacas.adoc,111,"Preamble > ""Zacas"" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 > Word/Doubleword/Quadword CAS (AMOCAS.W/D/Q) Instructions",[listing] temp0 = mem[X(rs1)+0] temp1 = mem[X(rs1)+8] comp0 = (rd x0) ? 0 : X(rd) comp1 = (rd x0) ? 0 : X(rd+1) swap0 = (rs2 x0) ? 0 : X(rs2) swap1 = (rs2 x0) ? 0 : X(rs2+1) if ( temp0 comp0 ) && ( temp1 comp1 ) mem[X(rs1)+0] = swap0 mem[X(rs1)+8] = swap1 endif if ( rd != x0 ) X(rd) = temp0 X(rd+1) = temp1 endif,unknown,unknown,high,False, +chunk_4fb09933,src/unpriv/zacas.adoc,127,"Preamble > ""Zacas"" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 > Word/Doubleword/Quadword CAS (AMOCAS.W/D/Q) Instructions",And the same exception options apply if the address is not naturally aligned.,unknown,unknown,high,False, +chunk_8fcaf242,src/unpriv/zacas.adoc,133,"Preamble > ""Zacas"" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 > Word/Doubleword/Quadword CAS (AMOCAS.W/D/Q) Instructions","The memory operation performed by an `AMOCAS.W/D/Q`, when successful, has acquire semantics if `aq` bit is 1 and has release semantics if `rl` bit is 1.",unknown,unknown,high,False, +chunk_116f9aba,src/unpriv/zacas.adoc,133,"Preamble > ""Zacas"" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 > Word/Doubleword/Quadword CAS (AMOCAS.W/D/Q) Instructions","The memory operation performed by an `AMOCAS.W/D/Q`, when not successful, has acquire semantics if `aq` bit is 1 but does not have release semantics, regardless of `rl`.",unknown,unknown,high,False, +chunk_334c5c8b,src/unpriv/zacas.adoc,141,"Preamble > ""Zacas"" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 > Word/Doubleword/Quadword CAS (AMOCAS.W/D/Q) Instructions","A FENCE instruction may be used to order the memory read access and, if produced, the memory write access by an `AMOCAS.W/D/Q` instruction.",SW_rule,enum,high,False, +chunk_0ec3bc4e,src/unpriv/zalasr.adoc,20,"Preamble > ""Zalasr"" Atomic Load-Acquire and Store-Release Instructions, Version 1.0 > Load-Acquire and Store-Release Instructions",The Zalasr instructions always sign-extend the value placed in rd and ignore the upper bits of the value of rs2.,unknown,enum,high,False, +chunk_b948c696,src/unpriv/zalasr.adoc,20,"Preamble > ""Zalasr"" Atomic Load-Acquire and Store-Release Instructions, Version 1.0 > Load-Acquire and Store-Release Instructions","If the address is not naturally aligned, an address-misaligned exception or an access-fault exception will be generated.",unknown,unknown,high,False, +chunk_c1db1c03,src/unpriv/zalasr.adoc,20,"Preamble > ""Zalasr"" Atomic Load-Acquire and Store-Release Instructions, Version 1.0 > Load-Acquire and Store-Release Instructions","The access-fault exception can be generated for a memory access that would otherwise be able to complete except for the misalignment, if the misaligned access should not be emulated.",non_CSR_parameter,enum,high,False, +chunk_be48df91,src/unpriv/zalasr.adoc,64,"Preamble > ""Zalasr"" Atomic Load-Acquire and Store-Release Instructions, Version 1.0 > Load-Acquire and Store-Release Instructions > Load Acquire",This load must have the ordering annotation aq and may have ordering annotation rl encoded in the instruction.,non_CSR_parameter,enum,very_high,False, +chunk_811aa6cb,src/unpriv/zalasr.adoc,64,"Preamble > ""Zalasr"" Atomic Load-Acquire and Store-Release Instructions, Version 1.0 > Load-Acquire and Store-Release Instructions > Load Acquire","The instruction always has an ""acquire-RCsc"" annotation, and if the bit rl is set the instruction has a ""release-RCsc"" annotation. + The versions without the aq bit set are RESERVED. LD.{AQ, AQRL} is RV64-only.",unknown,unknown,high,False, +chunk_17b7aee1,src/unpriv/zalasr.adoc,110,"Preamble > ""Zalasr"" Atomic Load-Acquire and Store-Release Instructions, Version 1.0 > Load-Acquire and Store-Release Instructions > Store Release",This store must have ordering annotation rl and may have ordering annotation aq encoded in the instruction.,non_CSR_parameter,enum,very_high,False, +chunk_cef22543,src/unpriv/zalasr.adoc,110,"Preamble > ""Zalasr"" Atomic Load-Acquire and Store-Release Instructions, Version 1.0 > Load-Acquire and Store-Release Instructions > Store Release","The instruction always has an ""release-RCsc"" annotation, and if the bit aq is set the instruction has a ""acquire-RCsc"" annotation. + The versions without the rl bit set are RESERVED. SD.{RL, AQRL} is RV64-only.",unknown,unknown,high,False, +chunk_0867a8c1,src/unpriv/zalrsc.adoc,5,"Preamble > ""Zalrsc"" Extension for Load-Reserved/Store-Conditional Instructions","Complex atomic memory operations on a single memory word or doubleword are performed with the load-reserved (LR) and store-conditional (SC) instructions. LR.W loads a word from the address in rs1, places the sign-extended value in rd, and registers a reservation set—a set of bytes that subsumes the bytes in the addressed word. SC.W conditionally writes a word in rs2 to the address in rs1: the SC.W succeeds only if the reservation is still valid and the reservation set contains the bytes being written.",unknown,enum,high,False, +chunk_fdca9cc1,src/unpriv/zalrsc.adoc,5,"Preamble > ""Zalrsc"" Extension for Load-Reserved/Store-Conditional Instructions","If the SC.W succeeds, the instruction writes the word in rs2 to memory, and it writes zero to rd.",unknown,unknown,high,False, +chunk_2b6efded,src/unpriv/zalrsc.adoc,5,"Preamble > ""Zalrsc"" Extension for Load-Reserved/Store-Conditional Instructions","If the SC.W fails, the instruction does not write to memory, and it writes a nonzero value to rd.",unknown,unknown,high,False, +chunk_4481135b,src/unpriv/zalrsc.adoc,5,"Preamble > ""Zalrsc"" Extension for Load-Reserved/Store-Conditional Instructions","No SC.W instruction shall retire unless it passes memory permission checks, but it is UNSPECIFIED whether any side effects of implicit address translation and protection memory accesses (such as setting a page-table entry D bit) occur on a failed SC.W.",non_CSR_parameter,binary,very_high,False, +chunk_441cd4d5,src/unpriv/zalrsc.adoc,5,"Preamble > ""Zalrsc"" Extension for Load-Reserved/Store-Conditional Instructions","For the purposes of memory protection, a failed SC.W may be treated like a store.",non_CSR_parameter,enum,medium,False, +chunk_1434282b,src/unpriv/zalrsc.adoc,27,"Preamble > ""Zalrsc"" Extension for Load-Reserved/Store-Conditional Instructions",Portable software should only assume the failure code will be non-zero.,SW_rule,enum,medium,False, +chunk_0b8622dd,src/unpriv/zalrsc.adoc,31,"Preamble > ""Zalrsc"" Extension for Load-Reserved/Store-Conditional Instructions","If the address is not naturally aligned, an address-misaligned exception or an access-fault exception will be generated.",unknown,unknown,high,False, +chunk_63fb69e8,src/unpriv/zalrsc.adoc,31,"Preamble > ""Zalrsc"" Extension for Load-Reserved/Store-Conditional Instructions","The access-fault exception can be generated for a memory access that would otherwise be able to complete except for the misalignment, if the misaligned access should not be emulated.",non_CSR_parameter,enum,high,False, +chunk_2bfa263e,src/unpriv/zalrsc.adoc,31,"Preamble > ""Zalrsc"" Extension for Load-Reserved/Store-Conditional Instructions","An SC may succeed only if no store from another hart to the reservation set can be observed to have occurred between the LR and the SC, and if there is no other SC between the LR and itself in program order.",non_CSR_parameter,enum,high,False, +chunk_540c678d,src/unpriv/zalrsc.adoc,31,"Preamble > ""Zalrsc"" Extension for Load-Reserved/Store-Conditional Instructions",An SC may succeed only if no write from a device other than a hart to the bytes accessed by the LR instruction can be observed to have occurred between the LR and SC.,non_CSR_parameter,enum,high,False, +chunk_f5eaf65f,src/unpriv/zalrsc.adoc,51,"Preamble > ""Zalrsc"" Extension for Load-Reserved/Store-Conditional Instructions",The SC must fail if the address is not within the reservation set of the most recent LR in program order.,non_CSR_parameter,binary,very_high,False, +chunk_f5e22b0e,src/unpriv/zalrsc.adoc,51,"Preamble > ""Zalrsc"" Extension for Load-Reserved/Store-Conditional Instructions",The SC must fail if a store to the reservation set from another hart can be observed to occur between the LR and SC.,non_CSR_parameter,binary,very_high,False, +chunk_9d0b2a89,src/unpriv/zalrsc.adoc,51,"Preamble > ""Zalrsc"" Extension for Load-Reserved/Store-Conditional Instructions",The SC must fail if a write from some other device to the bytes accessed by the LR can be observed to occur between the LR and SC. (,non_CSR_parameter,binary,very_high,False, +chunk_63eb6051,src/unpriv/zalrsc.adoc,51,"Preamble > ""Zalrsc"" Extension for Load-Reserved/Store-Conditional Instructions","If such a device writes the reservation set but does not write the bytes accessed by the LR, the SC may or may not fail.) An SC must fail if there is another SC (to any address) between the LR and the SC in program order.",non_CSR_parameter,binary,very_high,False, +chunk_8bc79d34,src/unpriv/zalrsc.adoc,66,"Preamble > ""Zalrsc"" Extension for Load-Reserved/Store-Conditional Instructions","Software should not set the rl bit on an LR instruction unless the aq bit is also set, nor should software set the aq bit on an SC instruction unless the rl bit is also set. LR.rl and SC.aq instructions are not guaranteed to provide any stronger ordering than those with both bits clear, but may result in lower performance.",SW_rule,enum,high,False, +chunk_61d2b5da,src/unpriv/zalrsc.adoc,78,"Preamble > ""Zalrsc"" Extension for Load-Reserved/Store-Conditional Instructions > Eventual Success of Store-Conditional Instructions","The loop comprises only an LR/SC sequence and code to retry the sequence in the case of failure, and must comprise at most 16 instructions placed sequentially in memory. * An LR/SC sequence begins with an LR instruction and ends with an SC instruction.",non_CSR_parameter,range,very_high,False, +chunk_c74d91c7,src/unpriv/zalrsc.adoc,78,"Preamble > ""Zalrsc"" Extension for Load-Reserved/Store-Conditional Instructions > Eventual Success of Store-Conditional Instructions","Compressed forms of the aforementioned ''I'' instructions in the C (hence Zca) and Zcb extensions are also permitted. * The code to retry a failing LR/SC sequence can contain backwards jumps and/or branches to repeat the LR/SC sequence, but otherwise has the same constraint as the code between the LR and SC. * The LR and SC addresses must lie within a memory region with the LR/SC eventuality property.",non_CSR_parameter,enum,very_high,False, +chunk_80abc89b,src/unpriv/zalrsc.adoc,78,"Preamble > ""Zalrsc"" Extension for Load-Reserved/Store-Conditional Instructions > Eventual Success of Store-Conditional Instructions",The execution environment is responsible for communicating which regions have this property. * The SC must be to the same effective address and of the same data size as the latest LR executed by the same hart.,SW_rule,enum,very_high,False, +chunk_297259b9,src/unpriv/zalrsc.adoc,102,"Preamble > ""Zalrsc"" Extension for Load-Reserved/Store-Conditional Instructions > Eventual Success of Store-Conditional Instructions","If a hart H enters a constrained LR/SC loop, the execution environment must guarantee that one of the following events eventually occurs:",SW_rule,enum,very_high,False, +chunk_616fff44,src/unpriv/zalrsc.adoc,105,"Preamble > ""Zalrsc"" Extension for Load-Reserved/Store-Conditional Instructions > Eventual Success of Store-Conditional Instructions","H or some other hart executes a successful SC to the reservation set of the LR instruction in H's constrained LR/SC loops. * Some other hart executes an unconditional store or AMO instruction to the reservation set of the LR instruction in H's constrained LR/SC loop, or some other device in the system writes to that reservation set. * H executes a branch or jump that exits the constrained LR/SC loop. * H traps.",unknown,unknown,high,False, +chunk_6bd45ee2,src/unpriv/zama.adoc,3,"Preamble > Zama16b Extension for 16-byte Misaligned Atomicity, Version 1.0","If the Zama16b extension is implemented, then the in main memory regions with both the cacheability and coherence PMAs is 16 bytes.",SW_rule,range,high,False, +chunk_3ee34466,src/unpriv/zama.adoc,3,"Preamble > Zama16b Extension for 16-byte Misaligned Atomicity, Version 1.0","Misaligned loads, stores, and AMOs to main memory regions that do not cross a naturally aligned 16-byte boundary are atomic.",non_CSR_parameter,range,medium,False, +chunk_2d18870e,src/unpriv/zars.adoc,3,"Preamble > Za128rs Extension for Reservation-Set Size, Version 1.0","The Za128rs extension requires that the reservation sets used by the instructions in the Zalrsc extension be contiguous, naturally aligned, and at most 128 bytes in size.",non_CSR_parameter,range,medium,False, +chunk_36b588c9,src/unpriv/zars.adoc,10,"Preamble > Za128rs Extension for Reservation-Set Size, Version 1.0 > Za64rs Extension for Reservation-Set Size, Version 1.0","The Za64rs extension requires that the reservation sets used by the instructions in the Zalrsc extension be contiguous, naturally aligned, and at most 64 bytes in size.",non_CSR_parameter,range,medium,False, +chunk_10ba508f,src/unpriv/zawrs.adoc,10,"Preamble > ""Zawrs"" Extension for Wait-on-Reservation-Set instructions, Version 1.01","The producer may be code executing on a RISC-V hart, an accelerator device, an external I/O agent.",non_CSR_parameter,enum,medium,False, +chunk_37177c9c,src/unpriv/zawrs.adoc,19,"Preamble > ""Zawrs"" Extension for Wait-on-Reservation-Set instructions, Version 1.01",Then a subsequent `WRS.NTO` instruction would cause the hart to temporarily stall execution in a low-power state until a store occurs to the reservation set or an interrupt is observed.,unknown,unknown,high,False, +chunk_a9c6a859,src/unpriv/zawrs.adoc,28,"Preamble > ""Zawrs"" Extension for Wait-on-Reservation-Set instructions, Version 1.01",Sometimes the program waiting on a memory update may also need to carry out a task at a future time or otherwise place an upper bound on the wait.,non_CSR_parameter,enum,medium,False, +chunk_c0e90a23,src/unpriv/zawrs.adoc,28,"Preamble > ""Zawrs"" Extension for Wait-on-Reservation-Set instructions, Version 1.01",To support such use cases a second instruction `WRS.STO` (WRS-with-short-timeout) is provided that works like `WRS.NTO` but bounds the stall duration to an implementation-define short timeout such that the stall is terminated on the timeout if no other conditions have occurred to terminate the stall.,unknown,unknown,high,False, +chunk_ba3a3671,src/unpriv/zawrs.adoc,28,"Preamble > ""Zawrs"" Extension for Wait-on-Reservation-Set instructions, Version 1.01",The program using this instruction may then determine if its deadline has been reached.,non_CSR_parameter,enum,high,False, +chunk_64af53f2,src/unpriv/zawrs.adoc,40,"Preamble > ""Zawrs"" Extension for Wait-on-Reservation-Set instructions, Version 1.01 > Wait-on-Reservation-Set Instructions","The `WRS.NTO` and `WRS.STO` instructions cause the hart to temporarily stall execution in a low-power state as long as the reservation set is valid and no pending interrupts, even if disabled, are observed.",unknown,binary,high,False, +chunk_a934267f,src/unpriv/zawrs.adoc,59,"Preamble > ""Zawrs"" Extension for Wait-on-Reservation-Set instructions, Version 1.01 > Wait-on-Reservation-Set Instructions",Hart execution may be stalled while the following conditions are all satisfied: [loweralpha] .,non_CSR_parameter,enum,medium,False, +chunk_c07c51b9,src/unpriv/zawrs.adoc,59,"Preamble > ""Zawrs"" Extension for Wait-on-Reservation-Set instructions, Version 1.01 > Wait-on-Reservation-Set Instructions","If `WRS.STO`, a ""short"" duration since start of stall has not elapsed .",unknown,unknown,high,False, +chunk_fd414941,src/unpriv/zawrs.adoc,59,"Preamble > ""Zawrs"" Extension for Wait-on-Reservation-Set instructions, Version 1.01 > Wait-on-Reservation-Set Instructions",No pending interrupt is observed (see the rules below),unknown,unknown,high,False, +chunk_4d5a2864,src/unpriv/zawrs.adoc,68,"Preamble > ""Zawrs"" Extension for Wait-on-Reservation-Set instructions, Version 1.01 > Wait-on-Reservation-Set Instructions",`WRS.NTO` and `WRS.STO` instructions follow the rules of the `WFI` instruction for resuming execution on a pending interrupt.,unknown,unknown,high,False, +chunk_7c2258e6,src/unpriv/zawrs.adoc,71,"Preamble > ""Zawrs"" Extension for Wait-on-Reservation-Set instructions, Version 1.01 > Wait-on-Reservation-Set Instructions","When the `TW` (Timeout Wait) bit in `mstatus` is set and `WRS.NTO` is executed in any privilege mode other than M mode, and it does not complete within an implementation-specific bounded time limit, the `WRS.NTO` instruction will cause an illegal-instruction exception.",CSR_controlled,enum,high,False, +chunk_ffe620a3,src/unpriv/zawrs.adoc,76,"Preamble > ""Zawrs"" Extension for Wait-on-Reservation-Set instructions, Version 1.01 > Wait-on-Reservation-Set Instructions","When executing in VS or VU mode, if the `VTW` bit is set in `hstatus`, the `TW` bit in `mstatus` is clear, and the `WRS.NTO` does not complete within an implementation-specific bounded time limit, the `WRS.NTO` instruction will cause a virtual-instruction exception.",CSR_controlled,enum,high,False, +chunk_4848b96d,src/unpriv/zc.adoc,3,Preamble > Compressed Instructions,"This chapter describes the RISC-V compressed instruction-set extensions, which reduce static and dynamic code size by adding short 16-bit instruction encodings for common operations.",non_CSR_parameter,range,medium,False, +chunk_58ea6b72,src/unpriv/zc.adoc,9,Preamble > Compressed Instructions,"The extlink:c[] extension combines ext:zca[], ext:zcf[] if XLEN=32 and the F extension is present, and ext:zcd[] if the D extension is present.",unknown,unknown,high,False, +chunk_b175a898,src/unpriv/zca.adoc,3,Preamble > ext:zca[] Integer Compressed Instructions Extension,The compressed extensions use a simple compression scheme that offers shorter 16-bit versions of common 32-bit RISC-V instructions when:,non_CSR_parameter,range,medium,False, +chunk_01312075,src/unpriv/zca.adoc,12,Preamble > ext:zca[] Integer Compressed Instructions Extension,"With the addition of the ext:zca[] extension, no instructions can raise instruction-address-misaligned exceptions.",non_CSR_parameter,unknown,high,False, +chunk_ca9336cf,src/unpriv/zca.adoc,19,Preamble > ext:zca[] Integer Compressed Instructions Extension,"If the C extension is implemented, the appropriate compressed floating-point load and store instructions must be provided whenever the relevant standard floating-point extension (F and/or D) is also implemented.",non_CSR_parameter,binary,very_high,False, +chunk_bf632ac0,src/unpriv/zca.adoc,34,Preamble > ext:zca[] Integer Compressed Instructions Extension,ext:zca[] was designed under the constraint that each ext:zca[] instruction expands into a single 32-bit instruction in the base ISA.,non_CSR_parameter,range,high,False, +chunk_a2a75af3,src/unpriv/zca.adoc,64,Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats,"When the full 5-bit destination register specifier is present, it is in the same place as in the 32-bit RISC-V encoding.",non_CSR_parameter,range,high,False, +chunk_38253dfb,src/unpriv/zca.adoc,64,Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats,"Where immediates are sign-extended, the sign extension is always from bit 12.",unknown,enum,high,False, +chunk_7a256ba7,src/unpriv/zca.adoc,64,Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats,"Immediate fields have been scrambled, as in the base specification, to reduce the number of immediate multiplexers required.",unknown,enum,high,False, +chunk_7643332e,src/unpriv/zca.adoc,64,Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats,"For many ext:zca[] instructions, zero-valued immediates are disallowed and `x0` is not a valid 5-bit register specifier.",non_CSR_parameter,range,high,False, +chunk_9c7a2d59,src/unpriv/zca.adoc,138,Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Load and Store Instructions,"To increase the reach of 16-bit instructions, data-transfer instructions use zero-extended immediates that are scaled by the size of the data in bytes: ×4 for words, ×8 for doublewords, and ×16 for quadwords.",non_CSR_parameter,range,high,False, +chunk_1083dca1,src/unpriv/zca.adoc,155,Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Load and Store Instructions > Stack-Pointer-Based Loads and Stores,C.LWSP loads a 32-bit value from memory into register rd.,non_CSR_parameter,range,medium,False, +chunk_a57e7c35,src/unpriv/zca.adoc,155,Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Load and Store Instructions > Stack-Pointer-Based Loads and Stores,"It computes an effective address by adding the zero-extended offset, scaled by 4, to the stack pointer, `x2`.",unknown,enum,high,False, +chunk_82114342,src/unpriv/zca.adoc,161,Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Load and Store Instructions > Stack-Pointer-Based Loads and Stores,C.LDSP is an XLEN=64-only instruction that loads a 64-bit value from memory into register rd.,non_CSR_parameter,range,medium,False, +chunk_ccef4248,src/unpriv/zca.adoc,161,Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Load and Store Instructions > Stack-Pointer-Based Loads and Stores,"It computes its effective address by adding the zero-extended offset, scaled by 8, to the stack pointer, `x2`.",unknown,enum,high,False, +chunk_cacc9a62,src/unpriv/zca.adoc,175,Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Load and Store Instructions > Stack-Pointer-Based Loads and Stores,C.SWSP stores a 32-bit value in register rs2 to memory.,non_CSR_parameter,range,medium,False, +chunk_098481d1,src/unpriv/zca.adoc,175,Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Load and Store Instructions > Stack-Pointer-Based Loads and Stores,"It computes an effective address by adding the zero-extended offset, scaled by 4, to the stack pointer, `x2`.",unknown,enum,high,False, +chunk_2819f935,src/unpriv/zca.adoc,179,Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Load and Store Instructions > Stack-Pointer-Based Loads and Stores,C.SDSP is an XLEN=64-only instruction that stores a 64-bit value in register rs2 to memory.,non_CSR_parameter,range,medium,False, +chunk_f3922a4e,src/unpriv/zca.adoc,179,Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Load and Store Instructions > Stack-Pointer-Based Loads and Stores,"It computes an effective address by adding the zero-extended offset, scaled by 8, to the stack pointer, `x2`.",unknown,enum,high,False, +chunk_f38fe9f7,src/unpriv/zca.adoc,186,Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Load and Store Instructions > Register-Based Loads and Stores,These instructions use the CL format.,unknown,unknown,high,False, +chunk_a6381f09,src/unpriv/zca.adoc,192,Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Load and Store Instructions > Register-Based Loads and Stores,C.LW loads a 32-bit value from memory into register `rd′`.,non_CSR_parameter,range,high,False, +chunk_9ce59e41,src/unpriv/zca.adoc,192,Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Load and Store Instructions > Register-Based Loads and Stores,"It computes an effective address by adding the zero-extended offset, scaled by 4, to the base address in register `rs1′`.",unknown,enum,high,False, +chunk_64b9baaf,src/unpriv/zca.adoc,197,Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Load and Store Instructions > Register-Based Loads and Stores,C.LD is an XLEN=64-only instruction that loads a 64-bit value from memory into register `rd′`.,non_CSR_parameter,range,high,False, +chunk_ac6e9320,src/unpriv/zca.adoc,197,Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Load and Store Instructions > Register-Based Loads and Stores,"It computes an effective address by adding the zero-extended offset, scaled by 8, to the base address in register `rs1′`.",unknown,enum,high,False, +chunk_787b99b9,src/unpriv/zca.adoc,208,Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Load and Store Instructions > Register-Based Loads and Stores,These instructions use the CS format.,unknown,unknown,high,False, +chunk_3ad5982e,src/unpriv/zca.adoc,210,Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Load and Store Instructions > Register-Based Loads and Stores,C.SW stores a 32-bit value in register `rs2′` to memory.,non_CSR_parameter,range,high,False, +chunk_69f9e371,src/unpriv/zca.adoc,210,Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Load and Store Instructions > Register-Based Loads and Stores,"It computes an effective address by adding the zero-extended offset, scaled by 4, to the base address in register `rs1′`.",unknown,enum,high,False, +chunk_28ae0e02,src/unpriv/zca.adoc,215,Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Load and Store Instructions > Register-Based Loads and Stores,C.SD is an XLEN=64-only instruction that stores a 64-bit value in register `rs2′` to memory.,non_CSR_parameter,range,high,False, +chunk_98780eb9,src/unpriv/zca.adoc,215,Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Load and Store Instructions > Register-Based Loads and Stores,"It computes an effective address by adding the zero-extended offset, scaled by 8, to the base address in register `rs1′`.",unknown,enum,high,False, +chunk_0224cf39,src/unpriv/zca.adoc,223,Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Control Transfer Instructions,"As with base RVI instructions, the offsets of all ext:zca[] control transfer instructions are in multiples of 2 bytes.",non_CSR_parameter,range,medium,False, +chunk_cb6ee97d,src/unpriv/zca.adoc,273,Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Control Transfer Instructions,The offset is sign-extended and added to the `pc` to form the branch target address.,unknown,enum,high,False, +chunk_976fc7ba,src/unpriv/zca.adoc,273,Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Control Transfer Instructions,It can therefore target a {pm}256 B range. C.BEQZ takes the branch if the value in register rs1′ is zero.,unknown,unknown,high,False, +chunk_9aad6ca1,src/unpriv/zca.adoc,279,Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Control Transfer Instructions,"C.BNEZ is defined analogously, but it takes the branch if rs1′ contains a nonzero value.",unknown,unknown,high,False, +chunk_ba5a195b,src/unpriv/zca.adoc,298,Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Constant-Generation Instructions,"C.LI loads the sign-extended 6-bit immediate, imm, into register rd. C.LI expands into `addi rd, x0, imm`.",non_CSR_parameter,range,high,False, +chunk_10509d59,src/unpriv/zca.adoc,302,Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Constant-Generation Instructions,"C.LUI loads the non-zero 6-bit immediate field into bits 17–12 of the destination register, clears the bottom 12 bits, and sign-extends bit 17 into all higher bits of the destination. C.LUI expands into `lui rd, imm`. C.LUI is valid only when rd!=`x2`, and when the immediate is not equal to zero.",non_CSR_parameter,range,high,False, +chunk_c81364d0,src/unpriv/zca.adoc,317,Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Immediate Operations,These integer register-immediate operations are encoded in the CI format and perform operations on an integer register and a 6-bit immediate.,non_CSR_parameter,range,high,False, +chunk_c12004bc,src/unpriv/zca.adoc,325,Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Immediate Operations,"C.ADDI adds the non-zero sign-extended 6-bit immediate to the value in register rd then writes the result to rd. C.ADDI expands into `addi rd, rd, imm`.",non_CSR_parameter,range,high,False, +chunk_e69f637e,src/unpriv/zca.adoc,325,Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Immediate Operations,The code points with rd!=0 and imm=0 are HINTs.,unknown,unknown,high,False, +chunk_d62bca7f,src/unpriv/zca.adoc,325,Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Immediate Operations,"The code points with rd=`x0` encode the C.NOP instruction, of which the code points with imm!=0 are HINTs.",unknown,unknown,high,False, +chunk_f7d8810b,src/unpriv/zca.adoc,332,Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Immediate Operations,"C.ADDIW is an XLEN=64-only instruction that performs the same computation but produces a 32-bit result, then sign-extends result to 64 bits. C.ADDIW expands into `addiw rd, rd, imm`.",non_CSR_parameter,range,high,False, +chunk_689af43a,src/unpriv/zca.adoc,332,Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Immediate Operations,"The immediate can be zero for C.ADDIW, where this corresponds to `sext.w rd`. C.ADDIW is valid only when rd!=`x0`; the code points with rd=`x0` are reserved.",unknown,unknown,high,False, +chunk_25315327,src/unpriv/zca.adoc,340,Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Immediate Operations,"C.ADDI16SP (add immediate to stack pointer) shares the opcode with C.LUI, but has a destination field of `x2`. C.ADDI16SP adds the non-zero sign-extended 6-bit immediate to the value in the stack pointer (`sp=x2`), where the immediate is scaled to represent multiples of 16 in the range [-512, 496]. C.ADDI16SP is used to adjust the stack pointer in procedure prologues and epilogues.",non_CSR_parameter,range,high,False, +chunk_4afe7147,src/unpriv/zca.adoc,340,Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Immediate Operations,"It expands into `addi x2, x2, nzimm[9:4]`. C.ADDI16SP is valid only when nzimm!=0; the code point with nzimm=0 is reserved.",unknown,unknown,high,False, +chunk_c7e35661,src/unpriv/zca.adoc,369,Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Immediate Operations,C.SLLI is a CI-format instruction that performs a logical left shift of the value in register rd then writes the result to rd.,unknown,unknown,high,False, +chunk_03bc4049,src/unpriv/zca.adoc,369,Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Immediate Operations,"The shift amount is encoded in the shamt field. C.SLLI expands into `slli rd, rd, shamt[5:0]`.",unknown,enum,high,False, +chunk_80b6a509,src/unpriv/zca.adoc,374,Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Immediate Operations,The C.SLLI code points with shamt=0 or with rd=`x0` are HINTs.,unknown,unknown,high,False, +chunk_9d4d17cb,src/unpriv/zca.adoc,376,Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Immediate Operations,"For XLEN=32, shamt[5] must be zero; the code points with shamt[5]=1 are designated for custom extensions.",non_CSR_parameter,enum,very_high,False, +chunk_477b7141,src/unpriv/zca.adoc,385,Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Immediate Operations,C.SRLI is a CB-format instruction that performs a logical right shift of the value in register rd′ then writes the result to rd′.,unknown,unknown,high,False, +chunk_fca60568,src/unpriv/zca.adoc,385,Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Immediate Operations,"The shift amount is encoded in the shamt field. C.SRLI expands into `srli rd′, rd′, shamt`.",unknown,enum,high,False, +chunk_00a520b6,src/unpriv/zca.adoc,390,Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Immediate Operations,The C.SRLI code points with shamt=0 are HINTs.,unknown,unknown,high,False, +chunk_f987c107,src/unpriv/zca.adoc,392,Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Immediate Operations,"For XLEN=32, shamt[5] must be zero; the code points with shamt[5]=1 are designated for custom extensions.",non_CSR_parameter,enum,very_high,False, +chunk_2a841775,src/unpriv/zca.adoc,418,Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Register Operations,"C.MV copies the value in register rs2 into register rd. C.MV expands into `add rd, x0, rs2`. C.MV is valid only when rs2!=`x0`; the code points with rs2=`x0` correspond to the C.JR instruction.",unknown,unknown,high,False, +chunk_dc485e6e,src/unpriv/zca.adoc,418,Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Register Operations,The code points with rs2!=`x0` and rd=`x0` are HINTs.,unknown,unknown,high,False, +chunk_7e484ec7,src/unpriv/zca.adoc,424,Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Register Operations,"C.ADD adds the values in registers rd and rs2 and writes the result to register rd. C.ADD expands into `add rd, rd, rs2`. C.ADD is only valid when rs2!=`x0`; the code points with rs2=`x0` correspond to the C.JALR and C.EBREAK instructions.",unknown,unknown,high,False, +chunk_ce062bb0,src/unpriv/zca.adoc,424,Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Register Operations,The code points with rs2!=`x0` and rd=`x0` are HINTs.,unknown,unknown,high,False, +chunk_3ea09b36,src/unpriv/zca.adoc,436,Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Register Operations,These instructions use the CA format.,unknown,unknown,high,False, +chunk_f68161c9,src/unpriv/zca.adoc,438,Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Register Operations,"`C.AND` computes the bitwise `AND` of the values in registers rd′ and rs2′, then writes the result to register rd′. `C.AND` expands into `and rd′, rd′, rs2′`.",unknown,unknown,high,False, +chunk_01747956,src/unpriv/zca.adoc,443,Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Register Operations,"`C.OR` computes the bitwise `OR` of the values in registers rd′ and rs2′, then writes the result to register rd′. `C.OR` expands into `or rd′, rd′, rs2′`.",unknown,unknown,high,False, +chunk_aa2086f2,src/unpriv/zca.adoc,448,Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Register Operations,"`C.XOR` computes the bitwise `XOR` of the values in registers rd′ and rs2′, then writes the result to register rd′. `C.XOR` expands into `xor rd′, rd′, rs2′`.",unknown,unknown,high,False, +chunk_87cafca2,src/unpriv/zca.adoc,453,Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Register Operations,"`C.SUB` subtracts the value in register rs2′ from the value in register rd′, then writes the result to register rd′. `C.SUB` expands into `sub rd′, rd′, rs2′`.",unknown,unknown,high,False, +chunk_a3324971,src/unpriv/zca.adoc,458,Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Register Operations,"`C.ADDW` is an XLEN=64-only instruction that adds the values in registers rd′ and rs2′, then sign-extends the lower 32 bits of the sum before writing the result to register rd′. `C.ADDW` expands into `addw rd′, rd′, rs2′`.",non_CSR_parameter,range,high,False, +chunk_ef4e9811,src/unpriv/zca.adoc,464,Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Register Operations,"`C.SUBW` is an XLEN=64-only instruction that subtracts the value in register rs2′ from the value in register rd′, then sign-extends the lower 32 bits of the difference before writing the result to register rd′. `C.SUBW` expands into `subw rd′, rd′, rs2′`.",non_CSR_parameter,range,high,False, +chunk_993070b0,src/unpriv/zca.adoc,476,Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Defined Illegal Instruction,A 16-bit instruction with all bits zero is permanently reserved as an illegal instruction.,non_CSR_parameter,range,high,False, +chunk_7e44809f,src/unpriv/zca.adoc,561,Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > ext:zca[] Instruction Set Listings,"The last quadrant, which has the two least-significant bits set, corresponds to instructions wider than 16 bits, including those in the base ISAs.",non_CSR_parameter,range,high,False, +chunk_ec2339ed,src/unpriv/zca.adoc,561,Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > ext:zca[] Instruction Set Listings,"Several instructions are only valid for certain operands; when invalid, they are marked either RES to indicate that the opcode is reserved for future standard extensions;",unknown,enum,high,False, +chunk_5263eecb,src/unpriv/zcb.adoc,3,Preamble > ext:zcb[] Extension for Additional Compressed Instructions,"The ext:zcb[] extension adds several compressed instructions which, like those in the extlink:zca[] extension, expand into a single 32-bit instruction.",non_CSR_parameter,range,medium,False, +chunk_adeec0bd,src/unpriv/zcb.adoc,118,Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu,The resulting byte is zero extended to XLEN bits and is written to rd'.,unknown,range,high,False, +chunk_cfb059c1,src/unpriv/zcb.adoc,173,Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.lhu,The resulting halfword is zero extended to XLEN bits and is written to rd'.,unknown,range,high,False, +chunk_f137fe17,src/unpriv/zcb.adoc,229,Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.lh,The resulting halfword is sign extended to XLEN bits and is written to rd'.,unknown,range,high,False, +chunk_0289468d,src/unpriv/zcb.adoc,284,Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.sb,This instruction stores the least significant byte of rs2' to the memory address formed by adding rs1' to the zero extended immediate uimm.,unknown,enum,high,False, +chunk_0f5d4f3d,src/unpriv/zcb.adoc,341,Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.sh,This instruction stores the least significant halfword of rs2' to the memory address formed by adding rs1' to the zero extended immediate uimm.,unknown,enum,high,False, +chunk_d91c998f,src/unpriv/zcb.adoc,387,Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.zext.b,It zero-extends the least-significant byte of the operand to XLEN bits by inserting zeros into all of the bits more significant than 7.,unknown,range,high,False, +chunk_e19a2bf7,src/unpriv/zcb.adoc,443,Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.sext.b,Zbb is also required. // //32-bit equivalent: // // from Zbb,non_CSR_parameter,range,medium,False, +chunk_0c8b7ec9,src/unpriv/zcb.adoc,488,Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.zext.h,It zero-extends the least-significant halfword of the operand to XLEN bits by inserting zeros into all of the bits more significant than 15.,unknown,range,high,False, +chunk_503b5bcd,src/unpriv/zcb.adoc,494,Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.zext.h,Zbb is also required. // //32-bit equivalent: // // from Zbb,non_CSR_parameter,range,medium,False, +chunk_620596b7,src/unpriv/zcb.adoc,541,Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.sext.h,Zbb is also required. // //32-bit equivalent: // // from Zbb,non_CSR_parameter,range,medium,False, +chunk_76d7d6d5,src/unpriv/zcb.adoc,582,Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.zext.w,It zero-extends the least-significant word of the operand to XLEN bits by inserting zeros into all of the bits more significant than 31.,unknown,range,high,False, +chunk_10648681,src/unpriv/zcb.adoc,684,Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.mul,M or Zmmul must be configured. // //32-bit equivalent: // //,non_CSR_parameter,range,very_high,False, +chunk_3bc84a13,src/unpriv/zcd.adoc,8,Preamble > ext:zcd[] Double-Precision Floating-Point Compressed Instructions Extension > Stack-Pointer-Based Loads and Stores,"It computes its effective address by adding the zero-extended offset, scaled by 8, to the stack pointer, `x2`.",unknown,enum,high,False, +chunk_17b32b64,src/unpriv/zcd.adoc,14,Preamble > ext:zcd[] Double-Precision Floating-Point Compressed Instructions Extension > Stack-Pointer-Based Loads and Stores,"It computes an effective address by adding the zero-extended offset, scaled by 8, to the stack pointer, `x2`.",unknown,enum,high,False, +chunk_4785730c,src/unpriv/zcd.adoc,22,Preamble > ext:zcd[] Double-Precision Floating-Point Compressed Instructions Extension > Stack-Pointer-Based Loads and Stores > Register-Based Loads and Stores,These instructions encode their data source or destination as described in .,unknown,unknown,high,False, +chunk_32d3a092,src/unpriv/zcd.adoc,25,Preamble > ext:zcd[] Double-Precision Floating-Point Compressed Instructions Extension > Stack-Pointer-Based Loads and Stores > Register-Based Loads and Stores,C.FLD is an RV32DC/RV64DC-only instruction that loads a double-precision floating-point value from memory into floating-point register `rd′`.,unknown,unknown,high,False, +chunk_d45f296c,src/unpriv/zcd.adoc,25,Preamble > ext:zcd[] Double-Precision Floating-Point Compressed Instructions Extension > Stack-Pointer-Based Loads and Stores > Register-Based Loads and Stores,"It computes an effective address by adding the zero-extended offset, scaled by 8, to the base address in register `rs1′`.",unknown,enum,high,False, +chunk_882384cf,src/unpriv/zcd.adoc,32,Preamble > ext:zcd[] Double-Precision Floating-Point Compressed Instructions Extension > Stack-Pointer-Based Loads and Stores > Register-Based Loads and Stores,C.FSD is an RV32DC/RV64DC-only instruction that stores a double-precision floating-point value in floating-point register `rs2′` to memory.,unknown,unknown,high,False, +chunk_b48956e2,src/unpriv/zcd.adoc,32,Preamble > ext:zcd[] Double-Precision Floating-Point Compressed Instructions Extension > Stack-Pointer-Based Loads and Stores > Register-Based Loads and Stores,"It computes an effective address by adding the zero-extended offset, scaled by 8, to the base address in register `rs1′`.",unknown,enum,high,False, +chunk_bd54237f,src/unpriv/zce.adoc,11,Preamble > ext:zce[] Extension for Enhanced Instruction Compression,"If XLEN=32 and the F extension is present, the ext:zce[] extension additionally depends upon the extlink:zcf[] extension.",unknown,unknown,high,False, +chunk_4b2bbfed,src/unpriv/zcf.adoc,9,Preamble > ext:zcf[] Single-Precision Floating-Point Compressed Instructions Extension > Stack-Pointer-Based Loads and Stores,"It computes its effective address by adding the zero-extended offset, scaled by 4, to the stack pointer, `x2`.",unknown,enum,high,False, +chunk_f54a3799,src/unpriv/zcf.adoc,16,Preamble > ext:zcf[] Single-Precision Floating-Point Compressed Instructions Extension > Stack-Pointer-Based Loads and Stores,"It computes an effective address by adding the zero-extended offset, scaled by 4, to the stack pointer, `x2`.",unknown,enum,high,False, +chunk_cccfef8f,src/unpriv/zcf.adoc,24,Preamble > ext:zcf[] Single-Precision Floating-Point Compressed Instructions Extension > Stack-Pointer-Based Loads and Stores > Register-Based Loads and Stores,These instructions encode their data source or destination as described in the following table.,unknown,unknown,high,False, +chunk_8e028dcf,src/unpriv/zcf.adoc,41,Preamble > ext:zcf[] Single-Precision Floating-Point Compressed Instructions Extension > Stack-Pointer-Based Loads and Stores > Register-Based Loads and Stores,! !`000` !`001` !`010` !`011` !`100` !`101` !`110` !`111` !`f8` !`f9` !`f10` !`f11` !`f12` !`f13`!`f14` !`f15` !`fs0` !`fs1` !`fa0` !`fa1` !`fa2`!`fa3` !`fa4` !`fa5` ! |,unknown,unknown,high,False, +chunk_8e5f6bb3,src/unpriv/zcf.adoc,49,Preamble > ext:zcf[] Single-Precision Floating-Point Compressed Instructions Extension > Stack-Pointer-Based Loads and Stores > Register-Based Loads and Stores,C.FLW is an RV32FC-only instruction that loads a single-precision floating-point value from memory into floating-point register `rd′`.,unknown,unknown,high,False, +chunk_c846447d,src/unpriv/zcf.adoc,49,Preamble > ext:zcf[] Single-Precision Floating-Point Compressed Instructions Extension > Stack-Pointer-Based Loads and Stores > Register-Based Loads and Stores,"It computes an effective address by adding the zero-extended offset, scaled by 4, to the base address in register `rs1′`.",unknown,enum,high,False, +chunk_8931f154,src/unpriv/zcf.adoc,56,Preamble > ext:zcf[] Single-Precision Floating-Point Compressed Instructions Extension > Stack-Pointer-Based Loads and Stores > Register-Based Loads and Stores,C.FSW is an RV32FC-only instruction that stores a single-precision floating-point value in floating-point register `rs2′` to memory.,unknown,unknown,high,False, +chunk_9e99f103,src/unpriv/zcf.adoc,56,Preamble > ext:zcf[] Single-Precision Floating-Point Compressed Instructions Extension > Stack-Pointer-Based Loads and Stores > Register-Based Loads and Stores,"It computes an effective address by adding the zero-extended offset, scaled by 4, to the base address in register `rs1′`.",unknown,enum,high,False, +chunk_5be97811,src/unpriv/zclsd.adoc,18,Preamble > ext:zclsd[] Extension for Compressed Load/Store Pair Instructions > Use of `x0` as operand > Exception Handling,"For the purposes of RVWMO and exception handling, C.LD[SP] and C.SD[SP] instructions are considered to be misaligned loads and stores, with one additional constraint: a C.LD[SP] or C.SD[SP] instruction whose effective address is a multiple of 4 gives rise to two 4-byte memory operations.",non_CSR_parameter,range,high,False, +chunk_3d8c64db,src/unpriv/zclsd.adoc,56,Preamble > ext:zclsd[] Extension for Compressed Load/Store Pair Instructions > Use of `x0` as operand > Exception Handling,"[insns-cldsp,reftext=""Stack-pointer based load doubleword to register pair, 16-bit encoding""]",non_CSR_parameter,range,medium,False, +chunk_89080859,src/unpriv/zclsd.adoc,77,Preamble > ext:zclsd[] Extension for Compressed Load/Store Pair Instructions > Use of `x0` as operand > Exception Handling > c.ldsp,"It computes its effective address by adding the zero-extended offset, scaled by 8, to the stack pointer, `x2`.",unknown,enum,high,False, +chunk_7abbc5ea,src/unpriv/zclsd.adoc,85,Preamble > ext:zclsd[] Extension for Compressed Load/Store Pair Instructions > Use of `x0` as operand > Exception Handling > c.ldsp,"[insns-csdsp,reftext=""Stack-pointer based store doubleword from register pair, 16-bit encoding""]",non_CSR_parameter,range,medium,False, +chunk_148711ae,src/unpriv/zclsd.adoc,105,Preamble > ext:zclsd[] Extension for Compressed Load/Store Pair Instructions > Use of `x0` as operand > Exception Handling > c.sdsp,"It computes an effective address by adding the zero-extended offset, scaled by 8, to the stack pointer, `x2`.",unknown,enum,high,False, +chunk_fa65403f,src/unpriv/zclsd.adoc,113,Preamble > ext:zclsd[] Extension for Compressed Load/Store Pair Instructions > Use of `x0` as operand > Exception Handling > c.sdsp,"[insns-cld,reftext=""Load doubleword to register pair, 16-bit encoding""]",non_CSR_parameter,range,medium,False, +chunk_35041d65,src/unpriv/zclsd.adoc,135,Preamble > ext:zclsd[] Extension for Compressed Load/Store Pair Instructions > Use of `x0` as operand > Exception Handling > c.ld,"It computes an effective address by adding the zero-extended offset, scaled by 8, to the base address in register rs1'.",unknown,enum,high,False, +chunk_f822abb1,src/unpriv/zclsd.adoc,144,Preamble > ext:zclsd[] Extension for Compressed Load/Store Pair Instructions > Use of `x0` as operand > Exception Handling > c.ld,"[insns-csd,reftext=""Store doubleword from register pair, 16-bit encoding""]",non_CSR_parameter,range,medium,False, +chunk_54a1dde2,src/unpriv/zclsd.adoc,166,Preamble > ext:zclsd[] Extension for Compressed Load/Store Pair Instructions > Use of `x0` as operand > Exception Handling > c.sd,"It computes an effective address by adding the zero-extended offset, scaled by 8, to the base address in register rs1'.",unknown,enum,high,False, +chunk_9b06a903,src/unpriv/zcmop.adoc,3,Preamble > ext:zcmop[] Compressed May-Be-Operations Extension,"This section defines the ext:zcmop[] extension, which defines eight 16-bit MOP instructions named C.MOP.n, where n is an odd integer between 1 and 15, inclusive. C.MOP.n is encoded in the reserved encoding space corresponding to C.LUI xn, 0, as shown in .",non_CSR_parameter,range,high,False, +chunk_bda13cc3,src/unpriv/zcmp.adoc,109,Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Example usage,As well as reducing the code-size PUSH and POPRET eliminate the branches from calling the millicode save/restore routines and so may also perform better.,non_CSR_parameter,enum,medium,False, +chunk_2e331ed9,src/unpriv/zcmp.adoc,118,Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Example usage > Stack pointer adjustment handling,Additionally the spimm field in the encoding allows the stack pointer to be adjusted in additional increments of 16-bytes.,unknown,enum,high,False, +chunk_883f34a4,src/unpriv/zcmp.adoc,124,Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Example usage > Register list handling,"There is no support for the \{ra, s0-s10} register list without also adding s11.",unknown,unknown,high,False, +chunk_8eaa350b,src/unpriv/zcmp.adoc,124,Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Example usage > Register list handling,"Therefore the \{ra, s0-s11} register list must be used in this case.",non_CSR_parameter,enum,very_high,False, +chunk_b8cdaabd,src/unpriv/zcmp.adoc,129,Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > PUSH/POP Fault handling,"Correct execution requires that sp refers to idempotent memory (also see ), because the core must be able to handle traps detected during the sequence.",non_CSR_parameter,binary,very_high,False, +chunk_8a42edb9,src/unpriv/zcmp.adoc,129,Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > PUSH/POP Fault handling,"The entire PUSH/POP sequence is re-executed after returning from the trap handler, and multiple traps are possible during the sequence.",unknown,unknown,high,False, +chunk_bf90f828,src/unpriv/zcmp.adoc,134,Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > PUSH/POP Fault handling,"If a trap occurs during the sequence then xEPC is updated with the PC of the instruction, xTVAL (if not read-only-zero) updated with the bad address if it was an access fault and xCAUSE updated with the type of trap.",unknown,unknown,high,False, +chunk_22a94933,src/unpriv/zcmp.adoc,146,Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Software view of execution > Software view of the PUSH sequence,A sequence of stores writing the bytes required by the pseudocode ** The bytes may be written in any order. ** The bytes may be grouped into larger accesses. ** Any of the bytes may be written multiple times. * A stack pointer adjustment,non_CSR_parameter,enum,medium,False, +chunk_5b2dd590,src/unpriv/zcmp.adoc,152,Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Software view of execution > Software view of the PUSH sequence,The stack pointer adjustment must only be committed only when it is certain that the entire PUSH instruction will commit.,non_CSR_parameter,binary,very_high,False, +chunk_244a5921,src/unpriv/zcmp.adoc,154,Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Software view of execution > Software view of the PUSH sequence,Stores may also return imprecise faults from the bus.,non_CSR_parameter,enum,high,False, +chunk_dfe1aa70,src/unpriv/zcmp.adoc,170,Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Software view of execution > Software view of the PUSH sequence,"[source,asm] ---- any bytes from sp-1 to sp-28 may be written multiple times before the instruction completes therefore these updates may be visible in the interrupt/exception handler below the stack pointer sw s5, -4(sp) sw s4, -8(sp) sw s3,-12(sp) sw s2,-16(sp) sw s1,-20(sp) sw s0,-24(sp) sw ra,-28(sp)",non_CSR_parameter,enum,high,False, +chunk_bcda8ac5,src/unpriv/zcmp.adoc,183,Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Software view of execution > Software view of the PUSH sequence,"this must only execute once, and will only execute after all stores completed without any precise faults, therefore this update is only visible in the interrupt/exception handler if cm.push has completed addi sp, sp, -64 ----",non_CSR_parameter,binary,very_high,False, +chunk_7696c9eb,src/unpriv/zcmp.adoc,193,Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Software view of execution > Software view of the POP/POPRET sequence,"A sequence of loads reading the bytes required by the pseudocode. ** The bytes may be loaded in any order. ** The bytes may be grouped into larger accesses. ** Any of the bytes may be loaded multiple times. * A stack pointer adjustment * An optional `li a0, 0` * An optional `ret`",non_CSR_parameter,enum,medium,False, +chunk_13f1a7d5,src/unpriv/zcmp.adoc,201,Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Software view of execution > Software view of the POP/POPRET sequence,"If a trap occurs during the sequence, then any loads which were executed before the trap may update architectural state.",non_CSR_parameter,enum,high,False, +chunk_0ae836bd,src/unpriv/zcmp.adoc,201,Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Software view of execution > Software view of the POP/POPRET sequence,"The loads will be re-executed once the trap handler completes, so the values will be overwritten.",unknown,unknown,high,False, +chunk_a89de1bd,src/unpriv/zcmp.adoc,201,Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Software view of execution > Software view of the POP/POPRET sequence,Therefore it is permitted for an implementation to update some of the destination registers before taking a fault.,unknown,unknown,high,False, +chunk_c0b97b01,src/unpriv/zcmp.adoc,205,Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Software view of execution > Software view of the POP/POPRET sequence,"The optional `li a0, 0`, stack pointer adjustment and optional `ret` must only be committed only when it is certain that the entire POP/POPRET instruction will commit.",non_CSR_parameter,binary,very_high,False, +chunk_4e1f005e,src/unpriv/zcmp.adoc,207,Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Software view of execution > Software view of the POP/POPRET sequence,For POPRET once the stack pointer adjustment has been committed the `ret` must execute.,non_CSR_parameter,enum,very_high,False, +chunk_a15a4c11,src/unpriv/zcmp.adoc,219,Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Software view of execution > Software view of the POP/POPRET sequence,"[source,asm] ---- any or all of these load instructions may execute multiple times therefore these updates may be visible in the interrupt/exception handler lw s3, 28(sp) lw s2, 24(sp) lw s1, 20(sp) lw s0, 16(sp) lw ra, 12(sp)",non_CSR_parameter,enum,high,False, +chunk_0941a2fa,src/unpriv/zcmp.adoc,229,Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Software view of execution > Software view of the POP/POPRET sequence,"these must only execute once, will only execute after all loads complete successfully all instructions must execute atomically therefore these updates are not visible in the interrupt/exception handler li a0, 0 addi sp, sp, 32 ret ----",non_CSR_parameter,binary,very_high,False, +chunk_f214c8f2,src/unpriv/zcmp.adoc,240,Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Non-idempotent memory handling,An implementation may have a requirement to issue a PUSH/POP instruction to non-idempotent memory.,non_CSR_parameter,enum,medium,False, +chunk_7b1c311f,src/unpriv/zcmp.adoc,242,Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Non-idempotent memory handling,"If the core implementation does not support PUSH/POP to non-idempotent memories, the core may use an idempotency PMA to detect it and take a load (POP/POPRET) or store (PUSH) access-fault exception in order to avoid unpredictable results.",non_CSR_parameter,enum,high,False, +chunk_4830fc54,src/unpriv/zcmp.adoc,245,Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Non-idempotent memory handling,Software should only use these instructions on non-idempotent memory regions when software can tolerate the required memory accesses being issued repeatedly in the case that they cause exceptions.,SW_rule,enum,high,False, +chunk_39381afb,src/unpriv/zcmp.adoc,381,Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.push,"switch (rlist){ case 4: \{reglist=""ra""; xreglist=""x1"";} case 5: \{reglist=""ra, s0""; xreglist=""x1, x8"";} case 6: \{reglist=""ra, s0-s1""; xreglist=""x1, x8-x9"";} default: reserved(); } stackadj = stackadjbase + spimm * 16; ----",unknown,unknown,high,False, +chunk_dfc47a5a,src/unpriv/zcmp.adoc,390,Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.push,"[source,sail] ---- RV32I, RV64: switch (rlist){ case 4: \{reglist=""ra""; xreglist=""x1"";} case 5: \{reglist=""ra, s0""; xreglist=""x1, x8"";} case 6: \{reglist=""ra, s0-s1""; xreglist=""x1, x8-x9"";} case 7: \{reglist=""ra, s0-s2""; xreglist=""x1, x8-x9, x18"";} case 8: \{reglist=""ra, s0-s3""; xreglist=""x1, x8-x9, x18-x19"";} case 9: \{reglist=""ra, s0-s4""; xreglist=""x1, x8-x9, x18-x20"";} case 10: \{reglist=""ra, s0-s5""; xreglist=""x1, x8-x9, x18-x21"";} case 11: \{reglist=""ra, s0-s6""; xreglist=""x1, x8-x9, x18-x22"";} case 12: \{reglist=""ra, s0-s7""; xreglist=""x1, x8-x9, x18-x23"";} case 13: \{reglist=""ra, s0-s8""; xreglist=""x1, x8-x9, x18-x24"";} case 14: \{reglist=""ra, s0-s9""; xreglist=""x1, x8-x9, x18-x25"";} //note - to include s10, s11 must also be included case 15: \{reglist=""ra, s0-s11""; xreglist=""x1, x8-x9, x18-x27"";} default: reserved(); } stackadj = stackadjbase + spimm * 16; ----",non_CSR_parameter,binary,very_high,False, +chunk_938f399a,src/unpriv/zcmp.adoc,470,Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.push,"This instruction pushes (stores) the registers in reglist to the memory below the stack pointer, and then creates the stack frame by decrementing the stack pointer by stackadj, including any additional stack space requested by the value of spimm.",unknown,enum,high,False, +chunk_59adbc22,src/unpriv/zcmp.adoc,478,Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.push,"stackadjbase is the minimum number of bytes, in multiples of 16-byte address increments, required to cover the registers in the list.",non_CSR_parameter,range,medium,False, +chunk_f1ef55ea,src/unpriv/zcmp.adoc,480,Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.push,spimm is the number of additional 16-byte address increments allocated for the stack frame.,non_CSR_parameter,range,medium,False, +chunk_1239efe6,src/unpriv/zcmp.adoc,495,Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.push,The first section of pseudocode may be executed multiple times before the instruction successfully completes.,non_CSR_parameter,enum,medium,False, +chunk_e8834e78,src/unpriv/zcmp.adoc,503,Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.push,"addr=sp-bytes; for(i in 27,26,25,24,23,22,21,20,19,18,9,8,1) { //if register i is in xreglist if (xreglist[i]) { switch(bytes) { 4: asm(""sw x[i], 0(addr)""); 8: asm(""sd x[i], 0(addr)""); } addr-=bytes; } } ----",unknown,unknown,high,False, +chunk_c3233798,src/unpriv/zcmp.adoc,516,Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.push,"The final section of pseudocode executes atomically, and only executes if the section above completes without any exceptions or interrupts.",unknown,unknown,high,False, +chunk_8068740c,src/unpriv/zcmp.adoc,561,Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.pop,"[source,sail] ---- RV32E: switch (rlist){ case 4: \{reglist=""ra""; xreglist=""x1"";} case 5: \{reglist=""ra, s0""; xreglist=""x1, x8"";} case 6: \{reglist=""ra, s0-s1""; xreglist=""x1, x8-x9"";} default: reserved(); } stackadj = stackadjbase + spimm * 16; ----",unknown,unknown,high,False, +chunk_3622230c,src/unpriv/zcmp.adoc,573,Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.pop,"[source,sail] ---- RV32I, RV64: switch (rlist){ case 4: \{reglist=""ra""; xreglist=""x1"";} case 5: \{reglist=""ra, s0""; xreglist=""x1, x8"";} case 6: \{reglist=""ra, s0-s1""; xreglist=""x1, x8-x9"";} case 7: \{reglist=""ra, s0-s2""; xreglist=""x1, x8-x9, x18"";} case 8: \{reglist=""ra, s0-s3""; xreglist=""x1, x8-x9, x18-x19"";} case 9: \{reglist=""ra, s0-s4""; xreglist=""x1, x8-x9, x18-x20"";} case 10: \{reglist=""ra, s0-s5""; xreglist=""x1, x8-x9, x18-x21"";} case 11: \{reglist=""ra, s0-s6""; xreglist=""x1, x8-x9, x18-x22"";} case 12: \{reglist=""ra, s0-s7""; xreglist=""x1, x8-x9, x18-x23"";} case 13: \{reglist=""ra, s0-s8""; xreglist=""x1, x8-x9, x18-x24"";} case 14: \{reglist=""ra, s0-s9""; xreglist=""x1, x8-x9, x18-x25"";} //note - to include s10, s11 must also be included case 15: \{reglist=""ra, s0-s11""; xreglist=""x1, x8-x9, x18-x27"";} default: reserved(); } stackadj = stackadjbase + spimm * 16; ----",non_CSR_parameter,binary,very_high,False, +chunk_6757022f,src/unpriv/zcmp.adoc,661,Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.pop,"stackadjbase is the minimum number of bytes, in multiples of 16-byte address increments, required to cover the registers in the list.",non_CSR_parameter,range,medium,False, +chunk_475ffe07,src/unpriv/zcmp.adoc,663,Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.pop,spimm is the number of additional 16-byte address increments allocated for the stack frame.,non_CSR_parameter,range,medium,False, +chunk_e6a70a49,src/unpriv/zcmp.adoc,678,Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.pop,The first section of pseudocode may be executed multiple times before the instruction successfully completes.,non_CSR_parameter,enum,medium,False, +chunk_0badcf9b,src/unpriv/zcmp.adoc,699,Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.pop,"The final section of pseudocode executes atomically, and only executes if the section above completes without any exceptions or interrupts.",unknown,unknown,high,False, +chunk_dae7b925,src/unpriv/zcmp.adoc,741,Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popretz,"[source,sail] ---- RV32E: switch (rlist){ case 4: \{reglist=""ra""; xreglist=""x1"";} case 5: \{reglist=""ra, s0""; xreglist=""x1, x8"";} case 6: \{reglist=""ra, s0-s1""; xreglist=""x1, x8-x9"";} default: reserved(); } stackadj = stackadjbase + spimm * 16; ----",unknown,unknown,high,False, +chunk_2367d297,src/unpriv/zcmp.adoc,757,Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popretz,"switch (rlist){ case 4: \{reglist=""ra""; xreglist=""x1"";} case 5: \{reglist=""ra, s0""; xreglist=""x1, x8"";} case 6: \{reglist=""ra, s0-s1""; xreglist=""x1, x8-x9"";} case 7: \{reglist=""ra, s0-s2""; xreglist=""x1, x8-x9, x18"";} case 8: \{reglist=""ra, s0-s3""; xreglist=""x1, x8-x9, x18-x19"";} case 9: \{reglist=""ra, s0-s4""; xreglist=""x1, x8-x9, x18-x20"";} case 10: \{reglist=""ra, s0-s5""; xreglist=""x1, x8-x9, x18-x21"";} case 11: \{reglist=""ra, s0-s6""; xreglist=""x1, x8-x9, x18-x22"";} case 12: \{reglist=""ra, s0-s7""; xreglist=""x1, x8-x9, x18-x23"";} case 13: \{reglist=""ra, s0-s8""; xreglist=""x1, x8-x9, x18-x24"";} case 14: \{reglist=""ra, s0-s9""; xreglist=""x1, x8-x9, x18-x25"";} //note - to include s10, s11 must also be included case 15: \{reglist=""ra, s0-s11""; xreglist=""x1, x8-x9, x18-x27"";} default: reserved(); } stackadj = stackadjbase + spimm * 16; ----",non_CSR_parameter,binary,very_high,False, +chunk_7d323770,src/unpriv/zcmp.adoc,841,Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popretz,"stackadjbase is the minimum number of bytes, in multiples of 16-byte address increments, required to cover the registers in the list.",non_CSR_parameter,range,medium,False, +chunk_38118f2c,src/unpriv/zcmp.adoc,843,Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popretz,spimm is the number of additional 16-byte address increments allocated for the stack frame.,non_CSR_parameter,range,medium,False, +chunk_cc3decbc,src/unpriv/zcmp.adoc,857,Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popretz,The first section of pseudocode may be executed multiple times before the instruction successfully completes.,non_CSR_parameter,enum,medium,False, +chunk_8f043a94,src/unpriv/zcmp.adoc,878,Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popretz,"The final section of pseudocode executes atomically, and only executes if the section above completes without any exceptions or interrupts.",unknown,unknown,high,False, +chunk_7b0a8f3d,src/unpriv/zcmp.adoc,929,Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popret,"switch (rlist){ case 4: \{reglist=""ra""; xreglist=""x1"";} case 5: \{reglist=""ra, s0""; xreglist=""x1, x8"";} case 6: \{reglist=""ra, s0-s1""; xreglist=""x1, x8-x9"";} default: reserved(); } stackadj = stackadjbase + spimm * 16; ----",unknown,unknown,high,False, +chunk_a23d07f7,src/unpriv/zcmp.adoc,942,Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popret,"switch (rlist){ case 4: \{reglist=""ra""; xreglist=""x1"";} case 5: \{reglist=""ra, s0""; xreglist=""x1, x8"";} case 6: \{reglist=""ra, s0-s1""; xreglist=""x1, x8-x9"";} case 7: \{reglist=""ra, s0-s2""; xreglist=""x1, x8-x9, x18"";} case 8: \{reglist=""ra, s0-s3""; xreglist=""x1, x8-x9, x18-x19"";} case 9: \{reglist=""ra, s0-s4""; xreglist=""x1, x8-x9, x18-x20"";} case 10: \{reglist=""ra, s0-s5""; xreglist=""x1, x8-x9, x18-x21"";} case 11: \{reglist=""ra, s0-s6""; xreglist=""x1, x8-x9, x18-x22"";} case 12: \{reglist=""ra, s0-s7""; xreglist=""x1, x8-x9, x18-x23"";} case 13: \{reglist=""ra, s0-s8""; xreglist=""x1, x8-x9, x18-x24"";} case 14: \{reglist=""ra, s0-s9""; xreglist=""x1, x8-x9, x18-x25"";} //note - to include s10, s11 must also be included case 15: \{reglist=""ra, s0-s11""; xreglist=""x1, x8-x9, x18-x27"";} default: reserved(); } stackadj = stackadjbase + spimm * 16; ----",non_CSR_parameter,binary,very_high,False, +chunk_c00f1f05,src/unpriv/zcmp.adoc,1026,Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popret,"stackadjbase is the minimum number of bytes, in multiples of 16-byte address increments, required to cover the registers in the list.",non_CSR_parameter,range,medium,False, +chunk_94439e00,src/unpriv/zcmp.adoc,1028,Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popret,spimm is the number of additional 16-byte address increments allocated for the stack frame.,non_CSR_parameter,range,medium,False, +chunk_68eb1534,src/unpriv/zcmp.adoc,1042,Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popret,The first section of pseudocode may be executed multiple times before the instruction successfully completes.,non_CSR_parameter,enum,medium,False, +chunk_03028360,src/unpriv/zcmp.adoc,1063,Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popret,"The final section of pseudocode executes atomically, and only executes if the section above completes without any exceptions or interrupts.",unknown,unknown,high,False, +chunk_b46a388d,src/unpriv/zcmp.adoc,1124,Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.mvsa01,"The SAIL hasn't been written yet. if (RV32E && (r1sc>1 || r2sc>1)) { reserved(); } xreg1 = {r1sc[2:1]>0,r1sc[2:1]0,r1sc[2:0]}; xreg2 = {r2sc[2:1]>0,r2sc[2:1]0,r2sc[2:0]}; X[xreg1] = X[10]; X[xreg2] = X[11]; ----",unknown,unknown,high,False, +chunk_4649270e,src/unpriv/zcmp.adoc,1187,Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.mva01s,"The SAIL hasn't been written yet. if (RV32E && (r1sc>1 || r2sc>1)) { reserved(); } xreg1 = {r1sc[2:1]>0,r1sc[2:1]0,r1sc[2:0]}; xreg2 = {r2sc[2:1]>0,r2sc[2:1]0,r2sc[2:0]}; X[10] = X[xreg1]; X[11] = X[xreg2]; ----",unknown,unknown,high,False, +chunk_6735a2ba,src/unpriv/zcmt.adoc,3,Preamble > ext:zcmt[] Extension for Compressed Table Jumps,"The ext:zcmt[] extension adds table-jump instructions, which improve code density when procedures have many call sites.",unknown,unknown,high,False, +chunk_9aed215a,src/unpriv/zcmt.adoc,3,Preamble > ext:zcmt[] Extension for Compressed Table Jumps,It also adds the csr:jvt[] CSR.,CSR_controlled,enum,high,False, +chunk_106f0851,src/unpriv/zcmt.adoc,3,Preamble > ext:zcmt[] Extension for Compressed Table Jumps,The csr:jvt[] CSR requires a state enable if Smstateen is implemented.,CSR_controlled,enum,high,False, +chunk_499c4a72,src/unpriv/zcmt.adoc,14,Preamble > ext:zcmt[] Extension for Compressed Table Jumps,The ext:zcmt[] extension depends on the extlink:zca[] and extlink:zicsr[] extensions.,CSR_controlled,enum,high,False, +chunk_f1809f62,src/unpriv/zcmt.adoc,40,Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview,The table must be a minimum of 64-byte aligned.,non_CSR_parameter,range,very_high,False, +chunk_cfc49892,src/unpriv/zcmt.adoc,57,Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview,"If a return address stack is implemented, then as cm.jalt is equivalent to jal ra, it pushes to the stack.",unknown,unknown,high,False, +chunk_096c9552,src/unpriv/zcmt.adoc,63,Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > jvt,If the same function is called with and without linking then it must have two entries in the table.,non_CSR_parameter,binary,very_high,False, +chunk_6bf5c16d,src/unpriv/zcmt.adoc,76,Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > Table Jump Fault handling,Multiple contexts may have different jump vector tables. JVT may be switched between them without an instruction barrier if the tables have not been updated in memory since the last fence.i.,SW_rule,enum,high,False, +chunk_2bcf64e2,src/unpriv/zcmt.adoc,79,Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > Table Jump Fault handling,"If an exception occurs on either instruction fetch, xEPC is set to the PC of the table jump instruction, xCAUSE is set as expected for the type of fault and xTVAL (if not set to zero) contains the fetch address which caused the fault.",unknown,binary,high,False, +chunk_bb9adf0d,src/unpriv/zcmt.adoc,81,Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > Table Jump Fault handling,"<<< [csrs-jvt,reftext=""jvt CSR, table jump base vector and control register""]",CSR_controlled,enum,high,False, +chunk_e28fd435,src/unpriv/zcmt.adoc,87,Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > jvt CSR,Table jump base vector and control register,unknown,unknown,high,False, +chunk_fb019f48,src/unpriv/zcmt.adoc,119,Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > jvt CSR,"The jvt register is an XLEN-bit *WARL* read/write register that holds the jump table configuration, consisting of the jump table base address (BASE) and the jump table mode (MODE).",CSR_controlled,range,very_high,False, +chunk_cda16098,src/unpriv/zcmt.adoc,121,Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > jvt CSR,"If ext:zcmt[] is implemented then jvt must also be implemented, but can contain a read-only value.",non_CSR_parameter,binary,very_high,False, +chunk_2f351e84,src/unpriv/zcmt.adoc,121,Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > jvt CSR,"If jvt is writable, the set of values the register may hold can vary by implementation.",non_CSR_parameter,enum,high,False, +chunk_6b510430,src/unpriv/zcmt.adoc,121,Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > jvt CSR,The value in the BASE field must always be aligned on a 64-byte boundary.,non_CSR_parameter,range,very_high,False, +chunk_9c947ab6,src/unpriv/zcmt.adoc,121,Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > jvt CSR,"When computing jump-table accesses, the lower six bits of base are filled with zeroes to obtain an XLEN-bit jump-table base address jvt.base that is always aligned on a 64-byte boundary.",non_CSR_parameter,range,high,False, +chunk_1bd419cf,src/unpriv/zcmt.adoc,124,Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > jvt CSR,"jvt.base is a virtual address, whenever virtual memory is enabled.",unknown,binary,high,False, +chunk_290c2b3d,src/unpriv/zcmt.adoc,126,Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > jvt CSR,"The memory pointed to by jvt.base is treated as instruction memory for the purpose of executing table jump instructions, implying execute access permission.",unknown,unknown,high,False, +chunk_28456f50,src/unpriv/zcmt.adoc,128,Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > jvt CSR,"[JVT-config-table] .jvt.mode definition [width=""60%"",options=header] | | jvt.mode | Comment | 000000 | Jump table mode | others | *reserved for future standard use* |",unknown,unknown,high,False, +chunk_e24417c7,src/unpriv/zcmt.adoc,137,Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > jvt CSR,"jvt.mode is a *WARL* field, so can only be programmed to modes which are implemented.",CSR_controlled,enum,very_high,False, +chunk_dcf77a12,src/unpriv/zcmt.adoc,137,Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > jvt CSR,Therefore the discovery mechanism is to attempt to program different modes and read back the values to see which are available.,unknown,unknown,high,False, +chunk_e466a733,src/unpriv/zcmt.adoc,137,Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > jvt CSR,Jump table mode must be implemented.,non_CSR_parameter,enum,very_high,False, +chunk_75f4f4e9,src/unpriv/zcmt.adoc,142,Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > jvt CSR,"jvt CSR adds architectural state to the system software context (such as an OS process), therefore must be saved/restored on context switches. <<< [insns-cmjt,reftext=""Jump via table""]",CSR_controlled,enum,very_high,False, +chunk_189c8c9e,src/unpriv/zfa.adoc,14,"Preamble > ""Zfa"" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions","The FLI.S instruction loads one of 32 single-precision floating-point constants, encoded in the rs1 field, into floating-point register rd.",unknown,enum,high,False, +chunk_32869777,src/unpriv/zfa.adoc,14,"Preamble > ""Zfa"" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions","The correspondence of rs1 field values and single-precision floating-point values is shown in . FLI.S is encoded like FMV.W.X, but with rs2=1.",unknown,enum,high,False, +chunk_d5ccbd86,src/unpriv/zfa.adoc,60,"Preamble > ""Zfa"" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions","If the D extension is implemented, FLI.D performs the analogous operation, but loads a double-precision value into floating-point register rd.",unknown,unknown,high,False, +chunk_b30cd70a,src/unpriv/zfa.adoc,68,"Preamble > ""Zfa"" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions","If the Q extension is implemented, FLI.Q performs the analogous operation, but loads a quad-precision value into floating-point register rd.",unknown,unknown,high,False, +chunk_3d9edbd1,src/unpriv/zfa.adoc,75,"Preamble > ""Zfa"" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions","If the Zfh or Zvfh extension is implemented, FLI.H performs the analogous operation, but loads a half-precision floating-point value into register rd.",unknown,unknown,high,False, +chunk_47f24a88,src/unpriv/zfa.adoc,75,"Preamble > ""Zfa"" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions",The FLI.fmt instructions never set any floating-point exception flags.,unknown,unknown,high,False, +chunk_6a907d49,src/unpriv/zfa.adoc,93,"Preamble > ""Zfa"" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Minimum and Maximum Instructions","If the D extension is implemented, FMINM.D and FMAXM.D instructions are analogously defined to operate on double-precision numbers.",unknown,unknown,high,False, +chunk_0415e4c0,src/unpriv/zfa.adoc,97,"Preamble > ""Zfa"" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Minimum and Maximum Instructions","If the Zfh extension is implemented, FMINM.H and FMAXM.H instructions are analogously defined to operate on half-precision numbers.",unknown,unknown,high,False, +chunk_ba239815,src/unpriv/zfa.adoc,101,"Preamble > ""Zfa"" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Minimum and Maximum Instructions","If the Q extension is implemented, FMINM.Q and FMAXM.Q instructions are analogously defined to operate on quad-precision numbers.",unknown,unknown,high,False, +chunk_77a5c549,src/unpriv/zfa.adoc,105,"Preamble > ""Zfa"" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Minimum and Maximum Instructions","These instructions are encoded like their FMIN and FMAX counterparts, but with instruction bit 13 set to 1.",unknown,binary,high,False, +chunk_a99ed609,src/unpriv/zfa.adoc,109,"Preamble > ""Zfa"" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Round-to-Integer Instructions","The FROUND.S instruction rounds the single-precision floating-point number in floating-point register rs1 to an integer, according to the rounding mode specified in the instruction's rm field.",unknown,enum,high,False, +chunk_b86fedb4,src/unpriv/zfa.adoc,109,"Preamble > ""Zfa"" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Round-to-Integer Instructions","Signaling NaN inputs cause the invalid operation exception flag to be set; no other exception flags are set. FROUND.S is encoded like FCVT.S.D, but with rs2=4.",unknown,enum,high,False, +chunk_70da0eb0,src/unpriv/zfa.adoc,118,"Preamble > ""Zfa"" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Round-to-Integer Instructions","The FROUNDNX.S instruction is defined similarly, but it also sets the inexact exception flag if the input differs from the rounded result and is not NaN. FROUNDNX.S is encoded like FCVT.S.D, but with rs2=5.",unknown,enum,high,False, +chunk_4a20b922,src/unpriv/zfa.adoc,123,"Preamble > ""Zfa"" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Round-to-Integer Instructions","If the D extension is implemented, FROUND.D and FROUNDNX.D instructions are analogously defined to operate on double-precision numbers.",unknown,unknown,high,False, +chunk_9d67c274,src/unpriv/zfa.adoc,123,"Preamble > ""Zfa"" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Round-to-Integer Instructions","They are encoded like FCVT.D.S, but with rs2=4 and 5, respectively,",unknown,enum,high,False, +chunk_1a226253,src/unpriv/zfa.adoc,128,"Preamble > ""Zfa"" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Round-to-Integer Instructions","If the Zfh extension is implemented, FROUND.H and FROUNDNX.H instructions are analogously defined to operate on half-precision numbers.",unknown,unknown,high,False, +chunk_0820a252,src/unpriv/zfa.adoc,128,"Preamble > ""Zfa"" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Round-to-Integer Instructions","They are encoded like FCVT.H.S, but with rs2=4 and 5, respectively,",unknown,enum,high,False, +chunk_9c917bad,src/unpriv/zfa.adoc,134,"Preamble > ""Zfa"" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Round-to-Integer Instructions","If the Q extension is implemented, FROUND.Q and FROUNDNX.Q instructions are analogously defined to operate on quad-precision numbers.",unknown,unknown,high,False, +chunk_96c215b1,src/unpriv/zfa.adoc,134,"Preamble > ""Zfa"" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Round-to-Integer Instructions","They are encoded like FCVT.Q.S, but with rs2=4 and 5, respectively,",unknown,enum,high,False, +chunk_5d83c8af,src/unpriv/zfa.adoc,140,"Preamble > ""Zfa"" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Modular Convert-to-Integer Instruction","Bits 31:0 are taken from the rounded, unbounded two's complement result, then sign-extended to XLEN bits and written to integer register rd. ±{inf} and NaN are converted to zero.",unknown,range,high,False, +chunk_789e6ece,src/unpriv/zfa.adoc,148,"Preamble > ""Zfa"" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Modular Convert-to-Integer Instruction",Floating-point exception flags are raised the same as they would be for FCVT.W.D with the same input operand.,non_CSR_parameter,unknown,high,False, +chunk_cc9e723a,src/unpriv/zfa.adoc,152,"Preamble > ""Zfa"" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Modular Convert-to-Integer Instruction",This instruction is only provided if the D extension is implemented.,unknown,unknown,high,False, +chunk_4c21b2d1,src/unpriv/zfa.adoc,152,"Preamble > ""Zfa"" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Modular Convert-to-Integer Instruction","It is encoded like FCVT.W.D, but with the rs2 field set to 8 and the rm field set to 1 (RTZ).",unknown,binary,high,False, +chunk_bd063bf2,src/unpriv/zfa.adoc,157,"Preamble > ""Zfa"" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Move Instructions","For RV32 only, if the D extension is implemented, the FMVH.X.D instruction moves bits 63:32 of floating-point register rs1 into integer register rd.",unknown,unknown,high,False, +chunk_7da7a4fa,src/unpriv/zfa.adoc,157,"Preamble > ""Zfa"" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Move Instructions","It is encoded in the OP-FP major opcode with funct3=0, rs2=1, and funct7=1110001.",unknown,enum,high,False, +chunk_4ab9ea14,src/unpriv/zfa.adoc,157,"Preamble > ""Zfa"" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Move Instructions","For RV32 only, if the D extension is implemented, the FMVP.D.X instruction moves a double-precision number from a pair of integer registers into a floating-point register.",unknown,unknown,high,False, +chunk_280451f6,src/unpriv/zfa.adoc,170,"Preamble > ""Zfa"" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Move Instructions","For RV64 only, if the Q extension is implemented, the FMVH.X.Q instruction moves bits 127:64 of floating-point register rs1 into integer register rd.",unknown,unknown,high,False, +chunk_4e4549a2,src/unpriv/zfa.adoc,170,"Preamble > ""Zfa"" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Move Instructions","It is encoded in the OP-FP major opcode with funct3=0, rs2=1, and funct7=1110011.",unknown,enum,high,False, +chunk_a1bf2a22,src/unpriv/zfa.adoc,170,"Preamble > ""Zfa"" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Move Instructions","For RV64 only, if the Q extension is implemented, the FMVP.Q.X instruction moves a double-precision number from a pair of integer registers into a floating-point register.",unknown,unknown,high,False, +chunk_33b26964,src/unpriv/zfa.adoc,185,"Preamble > ""Zfa"" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Comparison Instructions","The FLEQ.S and FLTQ.S instructions are defined like the FLE.S and FLT.S instructions, except that quiet NaN inputs do not cause the invalid operation exception flag to be set.",unknown,unknown,high,False, +chunk_69d6a512,src/unpriv/zfa.adoc,190,"Preamble > ""Zfa"" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Comparison Instructions","If the D extension is implemented, FLEQ.D and FLTQ.D instructions are analogously defined to operate on double-precision numbers.",unknown,unknown,high,False, +chunk_5ebd38b0,src/unpriv/zfa.adoc,194,"Preamble > ""Zfa"" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Comparison Instructions","If the Zfh extension is implemented, FLEQ.H and FLTQ.H instructions are analogously defined to operate on half-precision numbers.",unknown,unknown,high,False, +chunk_6dd6158a,src/unpriv/zfa.adoc,198,"Preamble > ""Zfa"" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Comparison Instructions","If the Q extension is implemented, FLEQ.Q and FLTQ.Q instructions are analogously defined to operate on quad-precision numbers.",unknown,unknown,high,False, +chunk_311b4175,src/unpriv/zfa.adoc,202,"Preamble > ""Zfa"" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Comparison Instructions","These instructions are encoded like their FLE and FLT counterparts, but with instruction bit 14 set to 1.",unknown,binary,high,False, +chunk_465554a9,src/unpriv/zfbfmin.adoc,30,Preamble > `Zfbfmin` Extension for Scalar BFloat16 Conversions > BF16 Number Format,"BF16 computational instructions defined in this chapter support all IEEE 754-2008 features, including all rounding modes, subnormal inputs and outputs, overflow and underflow, and default exception handling.",unknown,unknown,high,False, +chunk_cb2c536c,src/unpriv/zfbfmin.adoc,38,Preamble > `Zfbfmin` Extension for Scalar BFloat16 Conversions > BF16 Number Format,"BF16 values are NaN-boxed when held in `f` registers, as described in .",unknown,unknown,high,False, +chunk_2eb3bd2e,src/unpriv/zfbfmin.adoc,62,Preamble > `Zfbfmin` Extension for Scalar BFloat16 Conversions > BF16 Number Format > fcvt.bf16.s,Round according to the RM field.,unknown,enum,high,False, +chunk_e619a18c,src/unpriv/zfh.adoc,3,Preamble > `Zfh` Extension for Half-Precision Floating-Point,The NaN-boxing scheme described in is extended to allow a half-precision value to be NaN-boxed inside a single-precision value (which may be recursively NaN-boxed inside a double- or quad-precision value when the D or Q extension is present).,non_CSR_parameter,enum,high,False, +chunk_226b1613,src/unpriv/zfh.adoc,13,Preamble > `Zfh` Extension for Half-Precision Floating-Point > Half-Precision Load and Store Instructions,"New 16-bit variants of LOAD-FP and STORE-FP instructions are added, encoded with a new value for the funct3 width field.",non_CSR_parameter,range,high,False, +chunk_e98cc70a,src/unpriv/zfh.adoc,21,Preamble > `Zfh` Extension for Half-Precision Floating-Point > Half-Precision Load and Store Instructions,FLH and FSH are only guaranteed to execute atomically if the effective address is naturally aligned.,unknown,unknown,high,False, +chunk_5fc0d0c2,src/unpriv/zfh.adoc,25,Preamble > `Zfh` Extension for Half-Precision Floating-Point > Half-Precision Load and Store Instructions,"FLH and FSH do not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved. FLH NaN-boxes the result written to rd, whereas FSH ignores all but the lower 16 bits in rs2.",non_CSR_parameter,range,medium,False, +chunk_fc637e5d,src/unpriv/zfh.adoc,32,Preamble > `Zfh` Extension for Half-Precision Floating-Point > Half-Precision Load and Store Instructions > Half-Precision Computational Instructions,"A new supported format is added to the format field of most instructions, as shown in .",unknown,enum,high,False, +chunk_02f65601,src/unpriv/zfh.adoc,57,Preamble > `Zfh` Extension for Half-Precision Floating-Point > Half-Precision Load and Store Instructions > Half-Precision Conversion and Move Instructions,"These instructions are defined analogously to the single-precision-to-integer and integer-to-single-precision conversion instructions. FCVT.W.H or FCVT.L.H converts a half-precision floating-point number to a signed 32-bit or 64-bit integer, respectively. FCVT.H.W or FCVT.H.L converts a 32-bit or 64-bit signed integer, respectively, into a half-precision floating-point number. FCVT.WU.H, FCVT.LU.H, FCVT.H.WU, and FCVT.H.LU variants convert to or from unsigned integer values. FCVT.L[U].H and FCVT.H.L[U] are RV64-only instructions.",non_CSR_parameter,range,high,False, +chunk_f4b30396,src/unpriv/zfh.adoc,71,Preamble > `Zfh` Extension for Half-Precision Floating-Point > Half-Precision Load and Store Instructions > Half-Precision Conversion and Move Instructions,"If the D extension is present, FCVT.D.H or FCVT.H.D converts a half-precision floating-point number to a double-precision floating-point number, or vice-versa, respectively.",unknown,unknown,high,False, +chunk_3526cc83,src/unpriv/zfh.adoc,71,Preamble > `Zfh` Extension for Half-Precision Floating-Point > Half-Precision Load and Store Instructions > Half-Precision Conversion and Move Instructions,"If the Q extension is present, FCVT.Q.H or FCVT.H.Q converts a half-precision floating-point number to a quad-precision floating-point number, or vice-versa, respectively.",unknown,unknown,high,False, +chunk_0511159c,src/unpriv/zfh.adoc,94,Preamble > `Zfh` Extension for Half-Precision Floating-Point > Half-Precision Load and Store Instructions > Half-Precision Conversion and Move Instructions,"Instructions are provided to move bit patterns between the floating-point and integer registers. FMV.X.H moves the half-precision value in floating-point register rs1 to a representation in the IEEE 754-2008 encoding in integer register rd, filling the upper XLEN-16 bits with copies of the floating-point number's sign bit.",non_CSR_parameter,range,high,False, +chunk_ee726b52,src/unpriv/zfh.adoc,101,Preamble > `Zfh` Extension for Half-Precision Floating-Point > Half-Precision Load and Store Instructions > Half-Precision Conversion and Move Instructions,"FMV.H.X moves the half-precision value encoded in the IEEE 754-2008 encoding from the lower 16 bits of integer register rs1 to the floating-point register rd, NaN-boxing the result.",non_CSR_parameter,range,high,False, +chunk_132f54af,src/unpriv/zfhmin.adoc,3,Preamble > ext:zfhmin[] Extension for Minimal Half-Precision Floating-Point,"This section describes the Zfhmin standard extension, which provides minimal support for 16-bit half-precision binary floating-point instructions.",non_CSR_parameter,range,medium,False, +chunk_b89ce9f3,src/unpriv/zfhmin.adoc,12,Preamble > ext:zfhmin[] Extension for Minimal Half-Precision Floating-Point,"If the D extension is present, the FCVT.D.H and FCVT.H.D instructions are also included.",unknown,unknown,high,False, +chunk_4eacfc81,src/unpriv/zfhmin.adoc,12,Preamble > ext:zfhmin[] Extension for Minimal Half-Precision Floating-Point,"If the Q extension is present, the FCVT.Q.H and FCVT.H.Q instructions are additionally included.",unknown,unknown,high,False, +chunk_09884646,src/unpriv/zfinx.adoc,3,"Preamble > ""Zfinx"", ""Zdinx"", ""Zhinx"", ""Zhinxmin"" Extensions for Floating-Point in Integer Registers, Version 1.0","This chapter defines the ""Zfinx"" extension (pronounced ""z-f-in-x"") that provides instructions similar to those in the standard floating-point F extension for single-precision floating-point instructions but which operate on the `x` registers instead of the `f` registers.",unknown,unknown,high,False, +chunk_49710c2f,src/unpriv/zfinx.adoc,3,"Preamble > ""Zfinx"", ""Zdinx"", ""Zhinx"", ""Zhinxmin"" Extensions for Floating-Point in Integer Registers, Version 1.0","This chapter also defines the ""Zdinx"", ""Zhinx"", and ""Zhinxmin"" extensions that provide similar instructions for other floating-point precisions.",unknown,unknown,high,False, +chunk_9bda02a6,src/unpriv/zfinx.adoc,11,"Preamble > ""Zfinx"", ""Zdinx"", ""Zhinx"", ""Zhinxmin"" Extensions for Floating-Point in Integer Registers, Version 1.0","The Zfinx extension adds all of the instructions that the F extension adds, except for the transfer instructions FLW, FSW, FMV.W.X, FMV.X.W, C.FLW[SP], and C.FSW[SP].",unknown,unknown,high,False, +chunk_9be62281,src/unpriv/zfinx.adoc,16,"Preamble > ""Zfinx"", ""Zdinx"", ""Zhinx"", ""Zhinxmin"" Extensions for Floating-Point in Integer Registers, Version 1.0","The Zfinx variants of these F-extension instructions have the same semantics, except that whenever such an instruction would have accessed an `f` register, it instead accesses the `x` register with the same number.",unknown,unknown,high,False, +chunk_3c7e9006,src/unpriv/zfinx.adoc,22,"Preamble > ""Zfinx"", ""Zdinx"", ""Zhinx"", ""Zhinxmin"" Extensions for Floating-Point in Integer Registers, Version 1.0","The Zfinx extension depends on the ""Zicsr"" extension for control and status register access.",CSR_controlled,enum,high,False, +chunk_23088c1f,src/unpriv/zfinx.adoc,26,"Preamble > ""Zfinx"", ""Zdinx"", ""Zhinx"", ""Zhinxmin"" Extensions for Floating-Point in Integer Registers, Version 1.0 > Processing of Narrower Values",Floating-point operands of width w < XLEN bits occupy bits w-1:0 of an `x` register.,unknown,range,high,False, +chunk_23e363e3,src/unpriv/zfinx.adoc,26,"Preamble > ""Zfinx"", ""Zdinx"", ""Zhinx"", ""Zhinxmin"" Extensions for Floating-Point in Integer Registers, Version 1.0 > Processing of Narrower Values",Floating-point operations on w-bit operands ignore operand bits XLEN-1: w.,unknown,unknown,high,False, +chunk_f61810ad,src/unpriv/zfinx.adoc,31,"Preamble > ""Zfinx"", ""Zdinx"", ""Zhinx"", ""Zhinxmin"" Extensions for Floating-Point in Integer Registers, Version 1.0 > Processing of Narrower Values",Floating-point operations that produce w < XLEN-bit results fill bits XLEN-1: w with copies of bit w-1 (the sign bit).,unknown,range,high,False, +chunk_ceba460d,src/unpriv/zfinx.adoc,37,"Preamble > ""Zfinx"", ""Zdinx"", ""Zhinx"", ""Zhinxmin"" Extensions for Floating-Point in Integer Registers, Version 1.0 > Processing of Narrower Values > Zdinx",The Zdinx extension provides analogous double-precision floating-point instructions.,unknown,unknown,high,False, +chunk_a0040fcd,src/unpriv/zfinx.adoc,37,"Preamble > ""Zfinx"", ""Zdinx"", ""Zhinx"", ""Zhinxmin"" Extensions for Floating-Point in Integer Registers, Version 1.0 > Processing of Narrower Values > Zdinx",The Zdinx extension depends upon the Zfinx extension.,unknown,unknown,high,False, +chunk_68d1455c,src/unpriv/zfinx.adoc,40,"Preamble > ""Zfinx"", ""Zdinx"", ""Zhinx"", ""Zhinxmin"" Extensions for Floating-Point in Integer Registers, Version 1.0 > Processing of Narrower Values > Zdinx","The Zdinx extension adds all of the instructions that the D extension adds, except for the transfer instructions FLD, FSD, FMV.D.X, FMV.X.D, C.FLD[SP], and C.FSD[SP].",unknown,unknown,high,False, +chunk_1b7e1fd7,src/unpriv/zfinx.adoc,45,"Preamble > ""Zfinx"", ""Zdinx"", ""Zhinx"", ""Zhinxmin"" Extensions for Floating-Point in Integer Registers, Version 1.0 > Processing of Narrower Values > Zdinx","The Zdinx variants of these D-extension instructions have the same semantics, except that whenever such an instruction would have accessed an `f` register, it instead accesses the `x` register with the same number.",unknown,unknown,high,False, +chunk_93feb562,src/unpriv/zfinx.adoc,53,"Preamble > ""Zfinx"", ""Zdinx"", ""Zhinx"", ""Zhinxmin"" Extensions for Floating-Point in Integer Registers, Version 1.0 > Processing of Narrower Values > Processing of Wider Values","Double-precision operands in RV32Zdinx are held in aligned `x`-register pairs, i.e., register numbers must be even.",non_CSR_parameter,enum,very_high,False, +chunk_4dca5e84,src/unpriv/zfinx.adoc,53,"Preamble > ""Zfinx"", ""Zdinx"", ""Zhinx"", ""Zhinxmin"" Extensions for Floating-Point in Integer Registers, Version 1.0 > Processing of Narrower Values > Processing of Wider Values",Use of misaligned (odd-numbered) registers for double-width floating-point operands is reserved.,unknown,unknown,high,False, +chunk_0f200b97,src/unpriv/zfinx.adoc,77,"Preamble > ""Zfinx"", ""Zdinx"", ""Zhinx"", ""Zhinxmin"" Extensions for Floating-Point in Integer Registers, Version 1.0 > Processing of Narrower Values > Zhinx",The Zhinx extension provides analogous half-precision floating-point instructions.,unknown,unknown,high,False, +chunk_eac83960,src/unpriv/zfinx.adoc,77,"Preamble > ""Zfinx"", ""Zdinx"", ""Zhinx"", ""Zhinxmin"" Extensions for Floating-Point in Integer Registers, Version 1.0 > Processing of Narrower Values > Zhinx",The Zhinx extension depends upon the Zfinx extension.,unknown,unknown,high,False, +chunk_6df97b08,src/unpriv/zfinx.adoc,80,"Preamble > ""Zfinx"", ""Zdinx"", ""Zhinx"", ""Zhinxmin"" Extensions for Floating-Point in Integer Registers, Version 1.0 > Processing of Narrower Values > Zhinx","The Zhinx extension adds all of the instructions that the Zfh extension adds, except for the transfer instructions FLH, FSH, FMV.H.X, and FMV.X.H.",unknown,unknown,high,False, +chunk_4dd6daf3,src/unpriv/zfinx.adoc,85,"Preamble > ""Zfinx"", ""Zdinx"", ""Zhinx"", ""Zhinxmin"" Extensions for Floating-Point in Integer Registers, Version 1.0 > Processing of Narrower Values > Zhinx","The Zhinx variants of these Zfh-extension instructions have the same semantics, except that whenever such an instruction would have accessed an `f` register, it instead accesses the `x` register with the same number.",unknown,unknown,high,False, +chunk_582f03d4,src/unpriv/zfinx.adoc,93,"Preamble > ""Zfinx"", ""Zdinx"", ""Zhinx"", ""Zhinxmin"" Extensions for Floating-Point in Integer Registers, Version 1.0 > Processing of Narrower Values > Zhinxmin",The Zhinxmin extension provides minimal support for 16-bit half-precision floating-point instructions that operate on the `x` registers.,non_CSR_parameter,range,high,False, +chunk_4e6d87b6,src/unpriv/zfinx.adoc,93,"Preamble > ""Zfinx"", ""Zdinx"", ""Zhinx"", ""Zhinxmin"" Extensions for Floating-Point in Integer Registers, Version 1.0 > Processing of Narrower Values > Zhinxmin",The Zhinxmin extension depends upon the Zfinx extension.,unknown,unknown,high,False, +chunk_4823d6b3,src/unpriv/zfinx.adoc,97,"Preamble > ""Zfinx"", ""Zdinx"", ""Zhinx"", ""Zhinxmin"" Extensions for Floating-Point in Integer Registers, Version 1.0 > Processing of Narrower Values > Zhinxmin",The Zhinxmin extension includes the following instructions from the Zhinx extension: FCVT.S.H and FCVT.H.S.,unknown,unknown,high,False, +chunk_fe0759c9,src/unpriv/zfinx.adoc,97,"Preamble > ""Zfinx"", ""Zdinx"", ""Zhinx"", ""Zhinxmin"" Extensions for Floating-Point in Integer Registers, Version 1.0 > Processing of Narrower Values > Zhinxmin","If the Zdinx extension is present, the FCVT.D.H and FCVT.H.D instructions are also included.",unknown,unknown,high,False, +chunk_7323e61e,src/unpriv/zfinx.adoc,103,"Preamble > ""Zfinx"", ""Zdinx"", ""Zhinx"", ""Zhinxmin"" Extensions for Floating-Point in Integer Registers, Version 1.0 > Processing of Narrower Values > Privileged Architecture Implications","As described in , the `mstatus` field FS is hardwired to 0 if the Zfinx extension is implemented, and FS no longer affects the trapping behavior of floating-point instructions or `fcsr` accesses.",CSR_controlled,enum,high,False, +chunk_2f2a0fc2,src/unpriv/zfinx.adoc,109,"Preamble > ""Zfinx"", ""Zdinx"", ""Zhinx"", ""Zhinxmin"" Extensions for Floating-Point in Integer Registers, Version 1.0 > Processing of Narrower Values > Privileged Architecture Implications","The `misa` bits F, D, and Q are hardwired to 0 when the Zfinx extension is implemented.",unknown,unknown,high,False, +chunk_2350c40d,src/unpriv/zi.adoc,6,Preamble > Scalar Integer Extensions,"Most of these extensions are accordingly named with the prefix ""Zi"", with the exception of the integer multiplication and division extensions, which are named ""M"" or prefixed with ""Zm"".",unknown,unknown,high,False, +chunk_844e38f9,src/unpriv/zic64b.adoc,3,"Preamble > Zic64b Extension for 64-byte Cache Blocks, Version 1.0","If the Zic64b extension is implemented, then cache blocks must be 64 bytes in size, naturally aligned in the address space.",non_CSR_parameter,range,very_high,False, +chunk_873e17a8,src/unpriv/ziccamoa.adoc,3,"Preamble > Ziccamoa Extension for Main Memory Atomics, Version 1.0","If the Ziccamoa extension is implemented, then main memory regions with both the cacheability and coherence PMAs must support all atomics in the Zaamo extension.",SW_rule,binary,very_high,False, +chunk_a1df76c9,src/unpriv/ziccamoc.adoc,3,"Preamble > Ziccamoc Extension for Main Memory Compare-and-Swap, Version 1.0","If the Ziccamoc extension is implemented, then main memory regions with both the cacheability and coherence PMAs must provide ``AMOCASQ``-level PMA support.",SW_rule,binary,very_high,False, +chunk_fac5a4e4,src/unpriv/ziccif.adoc,7,"Preamble > Ziccif Extension for Instruction-Fetch Atomicity, Version 1.0","If the Ziccif extension is implemented, main memory regions with both the cacheability and coherence PMAs must support instruction fetch, and any instruction fetches of naturally aligned power-of-2 sizes of at most `min(ILEN,XLEN)` bits are atomic.",SW_rule,range,very_high,False, +chunk_bdeb387b,src/unpriv/ziccif.adoc,12,"Preamble > Ziccif Extension for Instruction-Fetch Atomicity, Version 1.0",An implementation with the Ziccif extension fetches instructions in a manner equivalent to the following state machine.,unknown,unknown,high,False, +chunk_89eaef06,src/unpriv/ziccif.adoc,20,"Preamble > Ziccif Extension for Instruction-Fetch Atomicity, Version 1.0","If the `T` bytes fetched begin with a complete instruction of length `L` {le} `T`, then execute that instruction, discard the remaining `T` - `L` bytes fetched, and go back to step 1, using the updated `pc`.",unknown,unknown,high,False, +chunk_79748322,src/unpriv/zicclsm.adoc,3,"Preamble > Zicclsm Extension for Main Memory Misaligned Accesses, Version 1.0","If the Zicclsm extension is implemented, then misaligned loads and stores to main memory regions with both the cacheability and coherence PMAs must be supported.",SW_rule,binary,very_high,False, +chunk_463acae0,src/unpriv/zicclsm.adoc,10,"Preamble > Zicclsm Extension for Main Memory Misaligned Accesses, Version 1.0","Standard software distributions should assume their existence only for correctness, not for performance.",SW_rule,enum,medium,False, +chunk_a63db0e0,src/unpriv/ziccrse.adoc,3,"Preamble > Ziccrse Extension for Main Memory Reservability, Version 1.0","If the Ziccrse extension is implemented, then main memory regions with both the cacheability and coherence PMAs must support the RsrvEventual PMA.",SW_rule,binary,very_high,False, +chunk_479e1cd1,src/unpriv/zicntr.adoc,3,"Preamble > ""Zicntr"" Extension for Base Counters and Timers","RISC-V ISAs provide a set of up to thirty-two 64-bit performance counters and timers that are accessible via unprivileged XLEN-bit read-only CSR registers `0xC00`–`0xC1F` (when XLEN=32, the upper 32 bits are accessed via CSR registers `0xC80`–`0xC9F`).",CSR_controlled,range,high,False, +chunk_c408604e,src/unpriv/zicntr.adoc,9,"Preamble > ""Zicntr"" Extension for Base Counters and Timers",The Zicntr extension depends on the Zicsr extension.,CSR_controlled,enum,high,False, +chunk_288606bf,src/unpriv/zicntr.adoc,16,"Preamble > ""Zicntr"" Extension for Base Counters and Timers","For base ISAs with XLEN{ge}64, CSR instructions can access the full 64-bit CSRs directly.",CSR_controlled,range,high,False, +chunk_73778658,src/unpriv/zicntr.adoc,16,"Preamble > ""Zicntr"" Extension for Base Counters and Timers","In particular, the RDCYCLE, RDTIME, and RDINSTRET pseudoinstructions read the full 64 bits of the `cycle`, `time`, and `instret` counters.",non_CSR_parameter,range,medium,False, +chunk_ea4b7db1,src/unpriv/zicntr.adoc,21,"Preamble > ""Zicntr"" Extension for Base Counters and Timers","For base ISAs with XLEN=32, the Zicntr extension enables the three 64-bit read-only counters to be accessed in 32-bit pieces.",CSR_controlled,range,high,False, +chunk_fb251695,src/unpriv/zicntr.adoc,21,"Preamble > ""Zicntr"" Extension for Base Counters and Timers","The RDCYCLE, RDTIME, and RDINSTRET pseudoinstructions provide the lower 32 bits, and the RDCYCLEH, RDTIMEH, and RDINSTRETH pseudoinstructions provide the upper 32 bits of the respective counters.",non_CSR_parameter,range,medium,False, +chunk_9db69357,src/unpriv/zicntr.adoc,21,"Preamble > ""Zicntr"" Extension for Base Counters and Timers",The RDCYCLE pseudoinstruction reads the low XLEN bits of the `cycle` CSR which holds a count of the number of clock cycles executed by the processor core on which the hart is running from an arbitrary start time in the past. RDCYCLEH is only present when XLEN=32 and reads bits 63-32 of the same cycle counter.,CSR_controlled,range,high,False, +chunk_a477e9fd,src/unpriv/zicntr.adoc,21,"Preamble > ""Zicntr"" Extension for Base Counters and Timers",The execution environment should provide a means to determine the current rate (cycles/second) at which the cycle counter is incrementing.,SW_rule,enum,medium,False, +chunk_93dcfd5e,src/unpriv/zicntr.adoc,21,"Preamble > ""Zicntr"" Extension for Base Counters and Timers","The RDTIME pseudoinstruction reads the low XLEN bits of the ""time"" CSR, which counts wall-clock real time that has passed from an arbitrary start time in the past. RDTIMEH is only present when XLEN=32 and reads bits 63-32 of the same real-time counter.",CSR_controlled,range,high,False, +chunk_7e76bafb,src/unpriv/zicntr.adoc,21,"Preamble > ""Zicntr"" Extension for Base Counters and Timers",The execution environment should provide a means of determining the period of a counter tick (seconds/tick).,SW_rule,enum,medium,False, +chunk_6c022daa,src/unpriv/zicntr.adoc,21,"Preamble > ""Zicntr"" Extension for Base Counters and Timers",The period should be constant within a small error bound.,non_CSR_parameter,enum,medium,False, +chunk_d078367c,src/unpriv/zicntr.adoc,21,"Preamble > ""Zicntr"" Extension for Base Counters and Timers",The real-time clocks of all harts must be synchronized to within one tick of the real-time clock.,non_CSR_parameter,enum,very_high,False, +chunk_dd32d15f,src/unpriv/zicntr.adoc,21,"Preamble > ""Zicntr"" Extension for Base Counters and Timers","The RDINSTRET pseudoinstruction reads the low XLEN bits of the `instret` CSR, which counts the number of instructions retired by this hart from some arbitrary start point in the past. RDINSTRETH is only present when XLEN=32 and reads bits 63-32 of the same instruction counter.",CSR_controlled,range,high,False, +chunk_68f2c698,src/unpriv/zicntr.adoc,21,"Preamble > ""Zicntr"" Extension for Base Counters and Timers","The following code sequence will read a valid 64-bit cycle counter value into `x3:x2`, even if the counter overflows its lower half between reading its upper and lower halves.",non_CSR_parameter,range,high,False, +chunk_12ddb6a0,src/unpriv/zicntr.adoc,59,"Preamble > ""Zicntr"" Extension for Base Counters and Timers","[source,asm.] .Sample code for reading the 64-bit cycle counter when XLEN=32. again: rdcycleh x3 rdcycle x2 rdcycleh x4 bne x3, x4, again",non_CSR_parameter,range,high,False, +chunk_a1214c6d,src/unpriv/zicond.adoc,27,"Preamble > ""Zicond"" Extension for Integer Conditional Operations, Version 1.0.0 > Instructions (in alphabetical order)","[insns-czero-eqz,reftext=""Conditional zero, if condition is equal to zero""]",unknown,range,high,False, +chunk_86864e34,src/unpriv/zicond.adoc,49,"Preamble > ""Zicond"" Extension for Integer Conditional Operations, Version 1.0.0 > Instructions (in alphabetical order) > czero.eqz","If rs2 contains the value zero, this instruction writes the value zero to rd.",unknown,unknown,high,False, +chunk_05762067,src/unpriv/zicond.adoc,53,"Preamble > ""Zicond"" Extension for Integer Conditional Operations, Version 1.0.0 > Instructions (in alphabetical order) > czero.eqz","Furthermore, if the Zkt extension is implemented, this instruction's timing is independent of the data values in rs1 and rs2.",unknown,unknown,high,False, +chunk_52ed35c9,src/unpriv/zicond.adoc,90,"Preamble > ""Zicond"" Extension for Integer Conditional Operations, Version 1.0.0 > Instructions (in alphabetical order) > czero.eqz > czero.nez","If rs2 contains a nonzero value, this instruction writes the value zero to rd.",unknown,unknown,high,False, +chunk_b666cd86,src/unpriv/zicond.adoc,94,"Preamble > ""Zicond"" Extension for Integer Conditional Operations, Version 1.0.0 > Instructions (in alphabetical order) > czero.eqz > czero.nez","Furthermore, if the Zkt extension is implemented, this instruction's timing is independent of the data values in rs1 and rs2.",unknown,unknown,high,False, +chunk_1331da3c,src/unpriv/zicond.adoc,119,"Preamble > ""Zicond"" Extension for Integer Conditional Operations, Version 1.0.0 > Instructions (in alphabetical order) > Usage examples > Instruction sequences","|*Conditional add, if zero* + `rd = (rc 0) ? (rs1 + rs2) : rs1` |czero.nez rd, rs2, rc add rd, rs1, rd .8+.^|2 insns",unknown,unknown,high,False, +chunk_3f9ac21d,src/unpriv/zicond.adoc,125,"Preamble > ""Zicond"" Extension for Integer Conditional Operations, Version 1.0.0 > Instructions (in alphabetical order) > Usage examples > Instruction sequences","|*Conditional add, if non-zero* + `rd = (rc != 0) ? (rs1 + rs2) : rs1` |czero.eqz rd, rs2, rc add rd, rs1, rd",unknown,unknown,high,False, +chunk_f0cc4d6d,src/unpriv/zicond.adoc,130,"Preamble > ""Zicond"" Extension for Integer Conditional Operations, Version 1.0.0 > Instructions (in alphabetical order) > Usage examples > Instruction sequences","|*Conditional subtract, if zero* + `rd = (rc 0) ? (rs1 - rs2) : rs1` |czero.nez rd, rs2, rc sub rd, rs1, rd",unknown,unknown,high,False, +chunk_0d764e52,src/unpriv/zicond.adoc,135,"Preamble > ""Zicond"" Extension for Integer Conditional Operations, Version 1.0.0 > Instructions (in alphabetical order) > Usage examples > Instruction sequences","|*Conditional subtract, if non-zero* + `rd = (rc != 0) ? (rs1 - rs2) : rs1` |czero.eqz rd, rs2, rc sub rd, rs1, rd",unknown,unknown,high,False, +chunk_03c75558,src/unpriv/zicond.adoc,140,"Preamble > ""Zicond"" Extension for Integer Conditional Operations, Version 1.0.0 > Instructions (in alphabetical order) > Usage examples > Instruction sequences","|*Conditional bitwise-or, if zero* + `rd = (rc 0) ? (rs1 \| rs2) : rs1` |czero.nez rd, rs2, rc or rd, rs1, rd",unknown,unknown,high,False, +chunk_10c1a422,src/unpriv/zicond.adoc,145,"Preamble > ""Zicond"" Extension for Integer Conditional Operations, Version 1.0.0 > Instructions (in alphabetical order) > Usage examples > Instruction sequences","|*Conditional bitwise-or, if non-zero* + `rd = (rc != 0) ? (rs1 \| rs2) : rs1` |czero.eqz rd, rs2, rc or rd, rs1, rd",unknown,unknown,high,False, +chunk_f5f24e63,src/unpriv/zicond.adoc,150,"Preamble > ""Zicond"" Extension for Integer Conditional Operations, Version 1.0.0 > Instructions (in alphabetical order) > Usage examples > Instruction sequences","|*Conditional bitwise-xor, if zero* + `rd = (rc 0) ? (rs1 ^ rs2) : rs1` |czero.nez rd, rs2, rc xor rd, rs1, rd",unknown,unknown,high,False, +chunk_a97d94a3,src/unpriv/zicond.adoc,155,"Preamble > ""Zicond"" Extension for Integer Conditional Operations, Version 1.0.0 > Instructions (in alphabetical order) > Usage examples > Instruction sequences","|*Conditional bitwise-xor, if non-zero* + `rd = (rc != 0) ? (rs1 ^ rs2) : rs1` |czero.eqz rd, rs2, rc xor rd, rs1, rd",unknown,unknown,high,False, +chunk_79abb737,src/unpriv/zicond.adoc,160,"Preamble > ""Zicond"" Extension for Integer Conditional Operations, Version 1.0.0 > Instructions (in alphabetical order) > Usage examples > Instruction sequences","|*Conditional bitwise-and, if zero* + `rd = (rc 0) ? (rs1 & rs2) : rs1` |and rd, rs1, rs2 czero.eqz rtmp, rs1, rc or rd, rd, rtmp .4+.^|3 insns + (requires 1 temporary)",non_CSR_parameter,unknown,high,False, +chunk_ea489e42,src/unpriv/zicond.adoc,168,"Preamble > ""Zicond"" Extension for Integer Conditional Operations, Version 1.0.0 > Instructions (in alphabetical order) > Usage examples > Instruction sequences","|*Conditional bitwise-and, if non-zero* + `rd = (rc != 0) ? (rs1 & rs2) : rs1` |and rd, rs1, rs2 czero.nez rtmp, rs1, rc or rd, rd, rtmp",unknown,unknown,high,False, +chunk_967ee658,src/unpriv/zicond.adoc,174,"Preamble > ""Zicond"" Extension for Integer Conditional Operations, Version 1.0.0 > Instructions (in alphabetical order) > Usage examples > Instruction sequences","|*Conditional select, if zero* + `rd = (rc 0) ? rs1 : rs2` |czero.nez rd, rs1, rc czero.eqz rtmp, rs2, rc add rd, rd, rtmp",unknown,enum,high,False, +chunk_b4b0da7d,src/unpriv/zicond.adoc,180,"Preamble > ""Zicond"" Extension for Integer Conditional Operations, Version 1.0.0 > Instructions (in alphabetical order) > Usage examples > Instruction sequences","|*Conditional select, if non-zero* + `rd = (rc != 0) ? rs1 : rs2` |czero.eqz rd, rs1, rc czero.nez rtmp, rs2, rc add rd, rd, rtmp",unknown,enum,high,False, +chunk_e287c5a3,src/unpriv/zicsr.adoc,3,"Preamble > ""Zicsr"" Extension for Control and Status Register (CSR) Instructions, Version 2.0",RISC-V defines a separate address space of 4096 Control and Status registers associated with each hart.,unknown,unknown,high,False, +chunk_1c9fc825,src/unpriv/zicsr.adoc,3,"Preamble > ""Zicsr"" Extension for Control and Status Register (CSR) Instructions, Version 2.0",This chapter defines the full set of CSR instructions that operate on these CSRs.,CSR_controlled,enum,high,False, +chunk_431e8b3d,src/unpriv/zicsr.adoc,9,"Preamble > ""Zicsr"" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions","All CSR instructions atomically read-modify-write a single CSR, whose CSR specifier is encoded in the 12-bit csr field of the instruction held in bits 31-20.",CSR_controlled,range,high,False, +chunk_8ecdb3f5,src/unpriv/zicsr.adoc,9,"Preamble > ""Zicsr"" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions",The immediate forms use a 5-bit zero-extended immediate encoded in the rs1 field.,non_CSR_parameter,range,high,False, +chunk_3910d2e2,src/unpriv/zicsr.adoc,16,"Preamble > ""Zicsr"" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions","The CSRRW (Atomic Read/Write CSR) instruction atomically swaps values in the CSRs and integer registers. CSRRW reads the old value of the CSR, zero-extends the value to XLEN bits, then writes it to integer register rd.",CSR_controlled,range,high,False, +chunk_4b27f85d,src/unpriv/zicsr.adoc,16,"Preamble > ""Zicsr"" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions",The initial value in rs1 is written to the CSR.,CSR_controlled,enum,high,False, +chunk_5e969665,src/unpriv/zicsr.adoc,16,"Preamble > ""Zicsr"" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions","If rd=`x0`, then the instruction shall not read the CSR and shall not cause any of the side effects that might occur on a CSR read.",CSR_controlled,enum,very_high,False, +chunk_ba728b9c,src/unpriv/zicsr.adoc,24,"Preamble > ""Zicsr"" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions","The CSRRS (Atomic Read and Set Bits in CSR) instruction reads the value of the CSR, zero-extends the value to XLEN bits, and writes it to integer register rd.",CSR_controlled,range,high,False, +chunk_fa62ab4c,src/unpriv/zicsr.adoc,24,"Preamble > ""Zicsr"" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions",The initial value in integer register rs1 is treated as a bit mask that specifies bit positions to be set in the CSR.,CSR_controlled,enum,high,False, +chunk_c1b61849,src/unpriv/zicsr.adoc,24,"Preamble > ""Zicsr"" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions","Any bit that is high in rs1 will cause the corresponding bit to be set in the CSR, if that CSR bit is writable.",CSR_controlled,enum,high,False, +chunk_03fe1b1e,src/unpriv/zicsr.adoc,32,"Preamble > ""Zicsr"" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions","The CSRRC (Atomic Read and Clear Bits in CSR) instruction reads the value of the CSR, zero-extends the value to XLEN bits, and writes it to integer register rd.",CSR_controlled,range,high,False, +chunk_b3c0c19b,src/unpriv/zicsr.adoc,32,"Preamble > ""Zicsr"" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions",The initial value in integer register rs1 is treated as a bit mask that specifies bit positions to be cleared in the CSR.,CSR_controlled,enum,high,False, +chunk_bd9a4a8f,src/unpriv/zicsr.adoc,32,"Preamble > ""Zicsr"" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions","Any bit that is high in rs1 will cause the corresponding bit to be cleared in the CSR, if that CSR bit is writable.",CSR_controlled,enum,high,False, +chunk_96304ce4,src/unpriv/zicsr.adoc,40,"Preamble > ""Zicsr"" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions","For both CSRRS and CSRRC, if rs1=`x0`, then the instruction will not write to the CSR at all, and so shall not cause any of the side effects that might otherwise occur on a CSR write, nor raise illegal-instruction exceptions on accesses to read-only CSRs.",CSR_controlled,enum,very_high,False, +chunk_d10c0607,src/unpriv/zicsr.adoc,40,"Preamble > ""Zicsr"" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions",Both CSRRS and CSRRC always read the addressed CSR and cause any read side effects regardless of rs1 and rd fields.,CSR_controlled,enum,high,False, +chunk_7fb7d76c,src/unpriv/zicsr.adoc,52,"Preamble > ""Zicsr"" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions",A CSRRW with rs1=`x0` will attempt to write zero to the destination CSR.,CSR_controlled,enum,high,False, +chunk_9db88041,src/unpriv/zicsr.adoc,55,"Preamble > ""Zicsr"" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions","The CSRRWI, CSRRSI, and CSRRCI variants are similar to CSRRW, CSRRS, and CSRRC respectively, except they update the CSR using an XLEN-bit value obtained by zero-extending a 5-bit unsigned immediate (uimm[4:0]) field encoded in the rs1 field instead of a value from an integer register.",CSR_controlled,range,high,False, +chunk_a1a3ca17,src/unpriv/zicsr.adoc,55,"Preamble > ""Zicsr"" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions","For CSRRSI and CSRRCI, if the uimm[4:0] field is zero, then these instructions will not write to the CSR, and shall not cause any of the side effects that might otherwise occur on a CSR write, nor raise illegal-instruction exceptions on accesses to read-only CSRs.",CSR_controlled,enum,very_high,False, +chunk_135e68b2,src/unpriv/zicsr.adoc,55,"Preamble > ""Zicsr"" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions","For CSRRWI, if rd=`x0`, then the instruction shall not read the CSR and shall not cause any of the side effects that might occur on a CSR read.",CSR_controlled,enum,very_high,False, +chunk_f3ce8ea7,src/unpriv/zicsr.adoc,55,"Preamble > ""Zicsr"" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions",Both CSRRSI and CSRRCI will always read the CSR and cause any read side effects regardless of rd and rs1 fields.,CSR_controlled,enum,high,False, +chunk_d06ade09,src/unpriv/zicsr.adoc,86,"Preamble > ""Zicsr"" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions",|Instruction |rd is `x0` |uimm=0 |Reads CSR |Writes CSR,CSR_controlled,enum,high,False, +chunk_fc511527,src/unpriv/zicsr.adoc,98,"Preamble > ""Zicsr"" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions",summarizes the behavior of the CSR instructions with respect to whether they read and/or write the CSR.,CSR_controlled,enum,high,False, +chunk_f195af57,src/unpriv/zicsr.adoc,102,"Preamble > ""Zicsr"" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions","In addition to side effects that occur as a consequence of reading or writing a CSR, individual fields within a CSR might have side effects when written.",CSR_controlled,enum,high,False, +chunk_64046f4d,src/unpriv/zicsr.adoc,102,"Preamble > ""Zicsr"" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions",The CSRRW[I] instructions action side effects for all such fields within the written CSR.,CSR_controlled,enum,high,False, +chunk_4de2104c,src/unpriv/zicsr.adoc,102,"Preamble > ""Zicsr"" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions",The CSRRS[I] and CSRRC[I] instructions only action side effects for fields for which the rs1 or uimm argument has at least one bit set corresponding to that field.,CSR_controlled,range,high,False, +chunk_eaef22cc,src/unpriv/zicsr.adoc,102,"Preamble > ""Zicsr"" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions","For any event or consequence that occurs due to a CSR having a particular value, if a write to the CSR gives it that value, the resulting event or consequence is said to be an indirect effect of the write.",CSR_controlled,enum,high,False, +chunk_98b81793,src/unpriv/zicsr.adoc,102,"Preamble > ""Zicsr"" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions",Indirect effects of a CSR write are not considered by the RISC-V ISA to be side effects of that write.,CSR_controlled,enum,high,False, +chunk_27c169ed,src/unpriv/zicsr.adoc,102,"Preamble > ""Zicsr"" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions","Some CSRs, such as the instructions-retired counter, `instret`, may be modified as side effects of instruction execution.",CSR_controlled,enum,high,False, +chunk_f75a76ad,src/unpriv/zicsr.adoc,102,"Preamble > ""Zicsr"" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions","In these cases, if a CSR access instruction reads a CSR, it reads the value prior to the execution of the instruction.",CSR_controlled,enum,high,False, +chunk_9c3e461a,src/unpriv/zicsr.adoc,102,"Preamble > ""Zicsr"" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions","If a CSR access instruction writes such a CSR, the explicit write is done instead of the update from the side effect.",CSR_controlled,enum,high,False, +chunk_11629f63,src/unpriv/zicsr.adoc,102,"Preamble > ""Zicsr"" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions","In particular, a value written to `instret` by one instruction will be the value read by the following instruction.",unknown,unknown,high,False, +chunk_d4bd6e00,src/unpriv/zicsr.adoc,122,"Preamble > ""Zicsr"" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions","The assembler pseudoinstruction to read a CSR, CSRR rd, csr, is encoded as CSRRS rd, csr, x0.",CSR_controlled,enum,high,False, +chunk_8185f9c5,src/unpriv/zicsr.adoc,122,"Preamble > ""Zicsr"" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions","The assembler pseudoinstruction to write a CSR, CSRW csr, rs1, is encoded as CSRRW x0, csr, rs1, while CSRWI csr, uimm, is encoded as CSRRWI x0, csr, uimm.",CSR_controlled,enum,high,False, +chunk_cb7068f8,src/unpriv/zicsr.adoc,127,"Preamble > ""Zicsr"" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions","Further assembler pseudoinstructions are defined to set and clear bits in the CSR when the old value is not required: CSRS/CSRC csr, rs1; CSRSI/CSRCI csr, uimm.",CSR_controlled,enum,high,False, +chunk_ae0b8d38,src/unpriv/zicsr.adoc,133,"Preamble > ""Zicsr"" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions > CSR Access Ordering","Each RISC-V hart normally observes its own CSR accesses, including its implicit CSR accesses, as performed in program order.",CSR_controlled,enum,high,False, +chunk_dd4964c0,src/unpriv/zicsr.adoc,133,"Preamble > ""Zicsr"" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions > CSR Access Ordering","Furthermore, an explicit CSR read returns the CSR state before the execution of the instruction, while an explicit CSR write suppresses and overrides any implicit writes or modifications to the same CSR by the same instruction.",CSR_controlled,enum,high,False, +chunk_26c36073,src/unpriv/zicsr.adoc,144,"Preamble > ""Zicsr"" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions > CSR Access Ordering","Likewise, any side effects from an explicit CSR access are normally observed to occur synchronously in program order.",CSR_controlled,enum,high,False, +chunk_4272daf5,src/unpriv/zicsr.adoc,144,"Preamble > ""Zicsr"" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions > CSR Access Ordering","Unless specified otherwise, the full consequences of any such side effects are observable by the very next instruction, and no consequences may be observed out-of-order by preceding instructions. (Note the distinction made earlier between side effects and indirect effects of CSR writes.)",CSR_controlled,enum,high,False, +chunk_21bad2c7,src/unpriv/zicsr.adoc,151,"Preamble > ""Zicsr"" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions > CSR Access Ordering","For the RVWMO memory consistency model (), CSR accesses are weakly ordered by default, so other harts or devices may observe CSR accesses in an order different from program order.",CSR_controlled,enum,high,False, +chunk_f1e14775,src/unpriv/zicsr.adoc,151,"Preamble > ""Zicsr"" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions > CSR Access Ordering","In addition, CSR accesses are not ordered with respect to explicit memory accesses, unless a CSR access modifies the execution behavior of the instruction that performs the explicit memory access or unless a CSR access and an explicit memory access are ordered by either the syntactic dependencies defined by the memory model or the ordering requirements defined in .",CSR_controlled,enum,high,False, +chunk_85b3dc5c,src/unpriv/zicsr.adoc,151,"Preamble > ""Zicsr"" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions > CSR Access Ordering","To enforce ordering in all other cases, software should execute a FENCE instruction between the relevant accesses.",SW_rule,enum,high,False, +chunk_ebd4feaa,src/unpriv/zicsr.adoc,151,"Preamble > ""Zicsr"" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions > CSR Access Ordering","For the purposes of the FENCE instruction, CSR read accesses are classified as device input (I), and CSR write accesses are classified as device output (O).",CSR_controlled,enum,high,False, +chunk_6769351e,src/unpriv/zicsr.adoc,151,"Preamble > ""Zicsr"" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions > CSR Access Ordering","The hardware platform may define that accesses to certain CSRs are strongly ordered, Accesses to strongly ordered CSRs have stronger ordering constraints with respect to accesses to both weakly ordered CSRs and accesses to memory-mapped I/O regions.",CSR_controlled,enum,high,False, +chunk_e8f13d4d,src/unpriv/zifencei.adoc,37,"Preamble > ""Zifencei"" Extension for Instruction-Fetch Fence, Version 2.0","The unused fields in the FENCE.I instruction, funct12, rs1, and rd, are reserved for finer-grain fences in future extensions.",SW_rule,enum,high,False, +chunk_c4d46b13,src/unpriv/zifencei.adoc,37,"Preamble > ""Zifencei"" Extension for Instruction-Fetch Fence, Version 2.0","For forward compatibility, base implementations shall ignore these fields, and standard software shall zero these fields.",SW_rule,enum,very_high,False, +chunk_dba267ff,src/unpriv/zihintntl.adoc,10,"Preamble > ""Zihintntl"" Extension for Non-Temporal Locality Hints, Version 1.0","The NTL.P1 instruction indicates that the target instruction does not exhibit temporal locality within the capacity of the innermost level of private cache in the memory hierarchy. NTL.P1 is encoded as ADD x0, x0, x2.",unknown,enum,high,False, +chunk_bac7f0dd,src/unpriv/zihintntl.adoc,15,"Preamble > ""Zihintntl"" Extension for Non-Temporal Locality Hints, Version 1.0","The NTL.PALL instruction indicates that the target instruction does not exhibit temporal locality within the capacity of any level of private cache in the memory hierarchy. NTL.PALL is encoded as ADD x0, x0, x3.",unknown,enum,high,False, +chunk_841c2ff4,src/unpriv/zihintntl.adoc,19,"Preamble > ""Zihintntl"" Extension for Non-Temporal Locality Hints, Version 1.0","The NTL.S1 instruction indicates that the target instruction does not exhibit temporal locality within the capacity of the innermost level of shared cache in the memory hierarchy. NTL.S1 is encoded as ADD x0, x0, x4.",unknown,enum,high,False, +chunk_14e12045,src/unpriv/zihintntl.adoc,24,"Preamble > ""Zihintntl"" Extension for Non-Temporal Locality Hints, Version 1.0","The NTL.ALL instruction indicates that the target instruction does not exhibit temporal locality within the capacity of any level of cache in the memory hierarchy. NTL.ALL is encoded as ADD x0, x0, x5.",unknown,enum,high,False, +chunk_47069481,src/unpriv/zihintntl.adoc,42,"Preamble > ""Zihintntl"" Extension for Non-Temporal Locality Hints, Version 1.0",The table also recommends which NTL variant that implementation-tuned software should use to avoid allocating in a particular cache level.,SW_rule,enum,medium,False, +chunk_51184e82,src/unpriv/zihintntl.adoc,42,"Preamble > ""Zihintntl"" Extension for Non-Temporal Locality Hints, Version 1.0","Furthermore, software tuned for such a system should use NTL.P1 to indicate a lack of temporal locality exploitable by the L1, or should use NTL.ALL indicate a lack of temporal locality exploitable by the L2.",SW_rule,enum,medium,False, +chunk_ad9a22b3,src/unpriv/zihintntl.adoc,54,"Preamble > ""Zihintntl"" Extension for Non-Temporal Locality Hints, Version 1.0","If the C or Zca extension is provided, compressed variants of these HINTs are also provided: C.NTL.P1 is encoded as C.ADD x0, x2; C.NTL.PALL is encoded as C.ADD x0, x3; C.NTL.S1 is encoded as C.ADD x0, x4; and C.NTL.ALL is encoded as C.ADD x0, x5.",unknown,enum,high,False, +chunk_8e3b2dc2,src/unpriv/zihintntl.adoc,89,"Preamble > ""Zihintntl"" Extension for Non-Temporal Locality Hints, Version 1.0","When an NTL instruction is applied to a prefetch hint in the Zicbop extension, it indicates that a cache line should be prefetched into a cache that is outer from the level specified by the NTL.",non_CSR_parameter,enum,high,False, +chunk_6cc183d2,src/unpriv/zihintntl.adoc,98,"Preamble > ""Zihintntl"" Extension for Non-Temporal Locality Hints, Version 1.0","In the event that a trap is taken on the target instruction, implementations are discouraged from applying the NTL to the first instruction in the trap handler.",unknown,unknown,high,False, +chunk_a96dd875,src/unpriv/zihintpause.adoc,3,"Preamble > ""Zihintpause"" Extension for Pause Hint, Version 2.0",The PAUSE instruction is a HINT that indicates the current hart's rate of instruction retirement should be temporarily reduced or paused.,non_CSR_parameter,enum,medium,False, +chunk_0de4ca53,src/unpriv/zihintpause.adoc,3,"Preamble > ""Zihintpause"" Extension for Pause Hint, Version 2.0",The duration of its effect must be bounded and may be zero.,non_CSR_parameter,enum,very_high,False, +chunk_6a6a0b8c,src/unpriv/zihintpause.adoc,9,"Preamble > ""Zihintpause"" Extension for Pause Hint, Version 2.0","PAUSE is encoded as a FENCE instruction with pred=`W`, succ=`0`, fm=`0`, rd=`x0`, and rs1=`x0`.",SW_rule,enum,high,False, +chunk_6abf98ab,src/unpriv/zihpm.adoc,3,"Preamble > ""Zihpm"" Extension for Hardware Performance Counters","The Zihpm extension comprises up to 29 additional unprivileged 64-bit hardware performance counters, `hpmcounter3-hpmcounter31`.",non_CSR_parameter,range,medium,False, +chunk_a67989e0,src/unpriv/zihpm.adoc,3,"Preamble > ""Zihpm"" Extension for Hardware Performance Counters","When XLEN=32, the upper 32 bits of these performance counters are accessible via additional CSRs `hpmcounter3h- hpmcounter31h`.",CSR_controlled,range,high,False, +chunk_df54db05,src/unpriv/zihpm.adoc,3,"Preamble > ""Zihpm"" Extension for Hardware Performance Counters",The Zihpm extension depends on the Zicsr extension.,CSR_controlled,enum,high,False, +chunk_dc32f4bd,src/unpriv/zihpm.adoc,3,"Preamble > ""Zihpm"" Extension for Hardware Performance Counters",Accessing an unimplemented counter may cause an illegal-instruction exception or may return a constant value.,non_CSR_parameter,enum,high,False, +chunk_67e109b9,src/unpriv/zihpm.adoc,3,"Preamble > ""Zihpm"" Extension for Hardware Performance Counters","If the configuration used to select the events counted by a counter is misconfigured, the counter may return a constant value.",non_CSR_parameter,enum,high,False, +chunk_7e664c43,src/unpriv/zihpm.adoc,15,"Preamble > ""Zihpm"" Extension for Hardware Performance Counters","The execution environment should provide a means to determine the number and width of the implemented counters, and an interface to configure the events to be counted by each counter.",SW_rule,enum,medium,False, +chunk_c54d4c93,src/unpriv/zilsd.adoc,5,Preamble > ext:zilsd[] Extension for Load/Store Pair Instructions,"Operands containing `src` for store instructions and `dest` for load instructions are held in aligned `x`-register pairs, i.e., register numbers must be even.",non_CSR_parameter,enum,very_high,False, +chunk_4f66a74a,src/unpriv/zilsd.adoc,32,Preamble > ext:zilsd[] Extension for Load/Store Pair Instructions,"As the access size is 64-bit, accesses are only considered naturally aligned for effective addresses that are a multiple of 8.",non_CSR_parameter,range,medium,False, +chunk_5c555bb3,src/unpriv/zilsd.adoc,32,Preamble > ext:zilsd[] Extension for Load/Store Pair Instructions,"In this case, these instructions are guaranteed to not raise an address-misaligned exception.",non_CSR_parameter,unknown,high,False, +chunk_a0448686,src/unpriv/zilsd.adoc,32,Preamble > ext:zilsd[] Extension for Load/Store Pair Instructions,"Even if naturally aligned, the memory access might not be performed atomically.",unknown,unknown,high,False, +chunk_16355b0a,src/unpriv/zilsd.adoc,36,Preamble > ext:zilsd[] Extension for Load/Store Pair Instructions,"If the effective address is a multiple of 4, then each word access is required to be performed atomically.",unknown,unknown,high,False, +chunk_a5483d4e,src/unpriv/zilsd.adoc,40,Preamble > ext:zilsd[] Extension for Load/Store Pair Instructions,| |Alignment |Word accesses guaranteed atomic? |Can cause misaligned trap? |8{nbsp}B |yes |no |4{nbsp}B not 8{nbsp}B |yes |yes |else |no | yes |,unknown,unknown,high,False, +chunk_eaecca12,src/unpriv/zilsd.adoc,48,Preamble > ext:zilsd[] Extension for Load/Store Pair Instructions,"To ensure resumable trap handling is possible for the load instructions, the base register must have its original value if a trap is taken.",non_CSR_parameter,binary,very_high,False, +chunk_bc6a0930,src/unpriv/zilsd.adoc,62,Preamble > ext:zilsd[] Extension for Load/Store Pair Instructions > Use of x0 as operand > Exception Handling,"For the purposes of RVWMO and exception handling, LD and SD instructions are considered to be misaligned loads and stores, with one additional constraint: an LD or SD instruction whose effective address is a multiple of 4 gives rise to two 4-byte memory operations.",non_CSR_parameter,range,high,False, +chunk_6ec83172,src/unpriv/zilsd.adoc,67,Preamble > ext:zilsd[] Extension for Load/Store Pair Instructions > Use of x0 as operand > Exception Handling,"If instructions with 4-byte-aligned effective address are decomposed into two 32b operations, there is no constraint on the order in which the operations are performed and each operation is guaranteed to be atomic.",non_CSR_parameter,range,high,False, +chunk_9323d676,src/unpriv/zilsd.adoc,67,Preamble > ext:zilsd[] Extension for Load/Store Pair Instructions > Use of x0 as operand > Exception Handling,These decomposed sequences are interruptible.,unknown,unknown,high,False, +chunk_5f6a3ba5,src/unpriv/zilsd.adoc,67,Preamble > ext:zilsd[] Extension for Load/Store Pair Instructions > Use of x0 as operand > Exception Handling,"Exceptions might occur on subsequent operations, making the effects of previous operations within the same instruction visible.",unknown,unknown,high,False, +chunk_2f70ffe3,src/unpriv/zilsd.adoc,86,Preamble > ext:zilsd[] Extension for Load/Store Pair Instructions > Use of x0 as operand > Instructions,"[insns-ld,reftext=""Load doubleword to register pair, 32-bit encoding""]",non_CSR_parameter,range,medium,False, +chunk_e399cd38,src/unpriv/zilsd.adoc,106,Preamble > ext:zilsd[] Extension for Load/Store Pair Instructions > Use of x0 as operand > Instructions > ld,The effective address is obtained by adding register rs1 to the sign-extended 12-bit offset.,non_CSR_parameter,range,high,False, +chunk_c6ec822a,src/unpriv/zilsd.adoc,116,Preamble > ext:zilsd[] Extension for Load/Store Pair Instructions > Use of x0 as operand > Instructions > ld,"[insns-sd,reftext=""Store doubleword from register pair, 32-bit encoding""]",non_CSR_parameter,range,medium,False, +chunk_00d22761,src/unpriv/zilsd.adoc,138,Preamble > ext:zilsd[] Extension for Load/Store Pair Instructions > Use of x0 as operand > Instructions > sd,The effective address is obtained by adding register rs1 to the sign-extended 12-bit offset.,non_CSR_parameter,range,high,False, +chunk_22eb57ca,src/unpriv/zimop.adoc,9,Preamble > ext:zimop[] Extension for May-Be-Operations,"Unless redefined by another extension, these instructions simply write 0 to `x[rd]`.",unknown,unknown,high,False, +chunk_53a21fab,src/unpriv/zimop.adoc,19,Preamble > ext:zimop[] Extension for May-Be-Operations,"Unless redefined by another extension, these instructions simply write 0 to `x[rd]`.",unknown,unknown,high,False, +chunk_36ad14da,src/unpriv/zimop.adoc,29,Preamble > ext:zimop[] Extension for May-Be-Operations,The extension that redefines a MOP may define an alternate assembly mnemonic.,non_CSR_parameter,enum,medium,False, +chunk_a2981048,src/unpriv/zimop.adoc,41,Preamble > ext:zimop[] Extension for May-Be-Operations,"The MOPs defined in the ext:zimop[] extension do not carry a syntactic dependency from `x[rs1]` or `x[rs2]` to `x[rd]`, though an extension that redefines the MOP may impose such a requirement.",non_CSR_parameter,enum,medium,False, +chunk_c49a56c7,src/unpriv/ztso.adoc,9,"Preamble > ""Ztso"" Extension for Total Store Ordering, Version 1.0",All load operations behave as if they have an acquire-RCpc annotation * All store operations behave as if they have a release-RCpc annotation. * All AMOs behave as if they have both acquire-RCsc and release-RCsc annotations.,unknown,unknown,high,False, +chunk_56ece718,src/unpriv/ztso.adoc,14,"Preamble > ""Ztso"" Extension for Total Store Ordering, Version 1.0","Additionally, if the Ztso extension is implemented, then vector memory instructions in the V extension and Zve family of extensions follow RVTSO at the instruction level.",unknown,unknown,high,False, +chunk_55f6fbc1,src/unpriv/ztso.adoc,20,"Preamble > ""Ztso"" Extension for Total Store Ordering, Version 1.0","Binaries compiled to run only under Ztso should indicate as such via a flag in the binary, so that platforms which do not implement Ztso can simply refuse to run them.",non_CSR_parameter,enum,medium,False, +chunk_a779dcd6,src/unpriv/zvfbfmin.adoc,49,Preamble > `Zvfbfmin` Extension for Vector BF16 Conversions > vfncvtbf16.f.f.w,Round according to the frm register.,CSR_controlled,enum,high,False, +chunk_d8280420,src/unpriv/zvfbfwma.adoc,66,Preamble > `Zvfbfwma` Extension for Vector BF16 Widening Multiply-Accumulation > vfwmaccbf16,The sum is rounded according to the frm register.,CSR_controlled,enum,high,False, +chunk_56023d0e,src/v-st-ext.adoc,13,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Implementation-defined Constant Parameters","The maximum size in bits of a vector element that any operation can produce or consume, ELEN {ge} 8, which must be a power of 2. .",non_CSR_parameter,range,very_high,False, +chunk_66980178,src/v-st-ext.adoc,13,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Implementation-defined Constant Parameters","The number of bits in a single vector register, VLEN {ge} ELEN, which must be a power of 2, and must be no greater than 2^16^.",CSR_controlled,range,very_high,False, +chunk_78fba37e,src/v-st-ext.adoc,17,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Implementation-defined Constant Parameters",Standard vector extensions () and architecture profiles may set further constraints on ELEN and VLEN.,CSR_controlled,enum,high,False, +chunk_32671622,src/v-st-ext.adoc,31,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Implementation-defined Constant Parameters","The vector extension supports writing binary code that under certain constraints will execute portably on harts with different values for the VLEN parameter, provided the harts support the required element types and instructions.",CSR_controlled,enum,high,False, +chunk_b2098700,src/v-st-ext.adoc,45,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model","The vector extension adds 32 vector registers, and seven unprivileged CSRs (`vstart`, `vxsat`, `vxrm`, `vcsr`, `vtype`, `vl`, `vlenb`) to a base scalar RISC-V ISA.",CSR_controlled,enum,high,False, +chunk_c8ebffe9,src/v-st-ext.adoc,55,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model",| 0x008 | URW | vstart | Vector start element index | 0x009 | URW | vxsat | Fixed-Point Saturate Flag | 0x00A | URW | vxrm | Fixed-Point Rounding Mode | 0x00F | URW | vcsr | Vector control and status register | 0xC20 | URO | vl | Vector length | 0xC21 | URO | vtype | Vector data type register | 0xC22 | URO | vlenb | VLEN/8 (vector register length in bytes) |,CSR_controlled,enum,high,False, +chunk_3855def4,src/v-st-ext.adoc,69,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Registers","The vector extension adds 32 architectural vector registers, `v0`-`v31` to the base scalar RISC-V ISA.",unknown,unknown,high,False, +chunk_9cf236cc,src/v-st-ext.adoc,73,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Registers",Each vector register has a fixed VLEN bits of state.,CSR_controlled,enum,high,False, +chunk_7d1c368f,src/v-st-ext.adoc,77,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Context Status in `mstatus`","A vector context status field, `VS`, is added to `mstatus[10:9]` and shadowed in `sstatus[10:9]`.",CSR_controlled,enum,high,False, +chunk_fc6d2e32,src/v-st-ext.adoc,77,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Context Status in `mstatus`","It is defined analogously to the floating-point context status field, `FS`.",unknown,enum,high,False, +chunk_c0c0139f,src/v-st-ext.adoc,82,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Context Status in `mstatus`","Attempts to execute any vector instruction, or to access the vector CSRs, raise an illegal-instruction exception when `mstatus.VS` is set to Off.",CSR_controlled,enum,high,False, +chunk_fccdaa45,src/v-st-ext.adoc,87,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Context Status in `mstatus`","When `mstatus.VS` is set to Initial or Clean, executing any instruction that changes vector state, including the vector CSRs, will change `mstatus.VS` to Dirty.",CSR_controlled,enum,high,False, +chunk_19a758db,src/v-st-ext.adoc,87,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Context Status in `mstatus`","Implementations may also change `mstatus.VS` from Initial or Clean to Dirty at any time, even when there is no change in vector state.",CSR_controlled,enum,high,False, +chunk_c68436d4,src/v-st-ext.adoc,97,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Context Status in `mstatus`","If `mstatus.VS` is Dirty, `mstatus.SD` is 1; otherwise, `mstatus.SD` is set in accordance with existing specifications.",CSR_controlled,enum,high,False, +chunk_b544d7cd,src/v-st-ext.adoc,101,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Context Status in `mstatus`",Implementations may have a writable `misa.V` field.,CSR_controlled,enum,high,False, +chunk_9a0af34c,src/v-st-ext.adoc,101,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Context Status in `mstatus`","Analogous to the way in which the floating-point unit is handled, the `mstatus.VS` field may exist even if `misa.V` is clear.",CSR_controlled,enum,high,False, +chunk_016445ef,src/v-st-ext.adoc,111,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Context Status in `vsstatus`","When the hypervisor extension is present, a vector context status field, `VS`, is added to `vsstatus[10:9]`.",CSR_controlled,enum,high,False, +chunk_4f9b96af,src/v-st-ext.adoc,111,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Context Status in `vsstatus`","It is defined analogously to the floating-point context status field, `FS`.",unknown,enum,high,False, +chunk_c7a05af6,src/v-st-ext.adoc,116,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Context Status in `vsstatus`","When V=1, both `vsstatus.VS` and `mstatus.VS` are in effect: attempts to execute any vector instruction, or to access the vector CSRs, raise an illegal-instruction exception when either field is set to Off.",CSR_controlled,enum,high,False, +chunk_4f912182,src/v-st-ext.adoc,121,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Context Status in `vsstatus`","When V=1 and neither `vsstatus.VS` nor `mstatus.VS` is set to Off, executing any instruction that changes vector state, including the vector CSRs, will change both `mstatus.VS` and `vsstatus.VS` to Dirty.",CSR_controlled,enum,high,False, +chunk_1e6d5f75,src/v-st-ext.adoc,121,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Context Status in `vsstatus`","Implementations may also change `mstatus.VS` or `vsstatus.VS` from Initial or Clean to Dirty at any time, even when there is no change in vector state.",CSR_controlled,enum,high,False, +chunk_19745b2d,src/v-st-ext.adoc,127,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Context Status in `vsstatus`","If `vsstatus.VS` is Dirty, `vsstatus.SD` is 1; otherwise, `vsstatus.SD` is set in accordance with existing specifications.",CSR_controlled,enum,high,False, +chunk_5dcf34fc,src/v-st-ext.adoc,131,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Context Status in `vsstatus`","If `mstatus.VS` is Dirty, `mstatus.SD` is 1; otherwise, `mstatus.SD` is set in accordance with existing specifications.",CSR_controlled,enum,high,False, +chunk_5e7facac,src/v-st-ext.adoc,135,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Context Status in `vsstatus`","For implementations with a writable `misa.V` field, the `vsstatus.VS` field may exist even if `misa.V` is clear.",CSR_controlled,enum,high,False, +chunk_f5c34059,src/v-st-ext.adoc,141,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register","The read-only XLEN-wide vector type CSR, `vtype` provides the default type used to interpret the contents of the vector register file, and can only be updated by `vset{i}vl{i}` instructions.",CSR_controlled,enum,high,False, +chunk_13a1efbf,src/v-st-ext.adoc,141,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register","The vector type determines the organization of elements in each vector register, and how multiple vector registers are grouped.",unknown,unknown,high,False, +chunk_b75676f5,src/v-st-ext.adoc,141,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register",The `vtype` register also indicates how masked-off elements and elements past the current vector length in a vector result are handled.,CSR_controlled,enum,high,False, +chunk_14951828,src/v-st-ext.adoc,152,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register","The `vtype` register has five fields, `vill`, `vma`, `vta`, `vsew[2:0]`, and `vlmul[2:0]`.",CSR_controlled,enum,high,False, +chunk_2bb9a0dd,src/v-st-ext.adoc,152,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register","Bits `vtype[XLEN-2:8]` should be written with zero, and non-zero values in this field are reserved.",CSR_controlled,enum,high,False, +chunk_c35b9616,src/v-st-ext.adoc,159,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register",The illegal value represented by `vill` can be internally encoded using the illegal 64-bit combination in `vsew[1:0]` without requiring an additional storage bit to hold `vill`.,non_CSR_parameter,range,high,False, +chunk_be0ffe7c,src/v-st-ext.adoc,165,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register","In many cases, the `vl` and `vtype` values can be reused across multiple instructions, reducing the static and dynamic instruction overhead from the `vset{i}vl{i}` instructions.",CSR_controlled,enum,high,False, +chunk_f6b6c9b2,src/v-st-ext.adoc,165,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register",It is anticipated that a future extended 64-bit instruction encoding would allow these fields to be specified statically in the instruction encoding.,non_CSR_parameter,range,high,False, +chunk_92e7b5fb,src/v-st-ext.adoc,180,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Selected Element Width (`vsew[2:0]`)",The value in `vsew` sets the dynamic selected element width (SEW).,unknown,enum,high,False, +chunk_ab5aa1c4,src/v-st-ext.adoc,180,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Selected Element Width (`vsew[2:0]`)","By default, a vector register is viewed as being divided into VLEN/SEW elements.",CSR_controlled,enum,high,False, +chunk_159d2358,src/v-st-ext.adoc,191,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Selected Element Width (`vsew[2:0]`)",| 0 | 0 | 0 | 8 | 0 | 0 | 1 | 16 | 0 | 1 | 0 | 32 | 0 | 1 | 1 | 64 | 1 | X | X | Reserved |,unknown,unknown,high,False, +chunk_9ba76760,src/v-st-ext.adoc,208,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Selected Element Width (`vsew[2:0]`)",| 64 | 2 | 32 | 4 | 16 | 8 | 8 | 16 |,unknown,unknown,high,False, +chunk_1a98b1dd,src/v-st-ext.adoc,214,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Selected Element Width (`vsew[2:0]`)",The supported element width may vary with LMUL.,non_CSR_parameter,enum,high,False, +chunk_5054779e,src/v-st-ext.adoc,216,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Selected Element Width (`vsew[2:0]`)",Some future extensions may support larger SEWs only when bits from multiple vector registers are combined using LMUL.,non_CSR_parameter,enum,high,False, +chunk_4bcb757d,src/v-st-ext.adoc,216,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Selected Element Width (`vsew[2:0]`)","In this case, software that relies on large SEW should attempt to use the largest LMUL, and hence the fewest vector register groups, to increase the number of implementations on which the code will run.",SW_rule,enum,high,False, +chunk_2525e083,src/v-st-ext.adoc,216,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Selected Element Width (`vsew[2:0]`)","The `vill` bit in `vtype` should be checked after setting `vtype` to see if the configuration is supported, and an alternate code path should be provided if it is not.",CSR_controlled,enum,high,False, +chunk_22b8bce5,src/v-st-ext.adoc,216,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Selected Element Width (`vsew[2:0]`)","Alternatively, a profile can mandate the minimum SEW at each LMUL setting.",unknown,range,high,False, +chunk_0c2bdd51,src/v-st-ext.adoc,229,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)","Multiple vector registers can be grouped together, so that a single vector instruction can operate on multiple vector registers.",unknown,unknown,high,False, +chunk_5a59f768,src/v-st-ext.adoc,229,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)",The term vector register group is used herein to refer to one or more vector registers used as a single operand to a vector instruction.,unknown,unknown,high,False, +chunk_d568baa3,src/v-st-ext.adoc,229,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)","The vector length multiplier, LMUL, when greater than 1, represents the default number of vector registers that are combined to form a vector register group.",unknown,range,high,False, +chunk_8ab701ed,src/v-st-ext.adoc,229,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)","Implementations must support LMUL integer values of 1, 2, 4, and 8.",non_CSR_parameter,enum,very_high,False, +chunk_6e0b521b,src/v-st-ext.adoc,242,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)",The effective LMUL (EMUL) of each vector operand is determined by the number of registers required to hold the elements.,non_CSR_parameter,unknown,high,False, +chunk_336dbdb3,src/v-st-ext.adoc,250,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)","LMUL can also be a fractional value, reducing the number of bits used in a single vector register.",unknown,unknown,high,False, +chunk_dccc5503,src/v-st-ext.adoc,250,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)",Fractional LMUL is used to increase the number of effective usable vector register groups when operating on mixed-width values.,unknown,unknown,high,False, +chunk_69d66bf2,src/v-st-ext.adoc,255,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)",This can limit the number of vector register groups available.,unknown,unknown,high,False, +chunk_49f4fd38,src/v-st-ext.adoc,255,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)","With fractional LMUL, the widest values need occupy only a single vector register while narrower values can occupy a fraction of a single vector register, allowing all 32 architectural vector register names to be used for different values in a vector loop even when handling mixed-width values.",unknown,unknown,high,False, +chunk_c2993deb,src/v-st-ext.adoc,255,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)","Fractional LMUL implies portions of vector registers are unused, but in some cases, having more shorter register-resident vectors improves efficiency relative to fewer longer register-resident vectors.",unknown,unknown,high,False, +chunk_f82746f4,src/v-st-ext.adoc,269,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)",Implementations must provide fractional LMUL settings that allow the narrowest supported type to occupy a fraction of a vector register corresponding to the ratio of the narrowest supported type's width to that of the largest supported type's width.,non_CSR_parameter,enum,very_high,False, +chunk_85c7cba7,src/v-st-ext.adoc,269,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)","In the standard extensions, SEW~MIN~=8.",unknown,unknown,high,False, +chunk_13e8418d,src/v-st-ext.adoc,269,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)","For standard vector extensions with ELEN=32, fractional LMULs of 1/2 and 1/4 must be supported.",non_CSR_parameter,enum,very_high,False, +chunk_52ccf9d2,src/v-st-ext.adoc,269,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)","For standard vector extensions with ELEN=64, fractional LMULs of 1/2, 1/4, and 1/8 must be supported.",non_CSR_parameter,enum,very_high,False, +chunk_e7f18d7c,src/v-st-ext.adoc,281,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)","When LMUL < SEW~MIN~/ELEN, there is no guarantee an implementation would have enough bits in the fractional vector register to store at least one element, as VLEN=ELEN is a valid implementation choice.",CSR_controlled,range,high,False, +chunk_50421d62,src/v-st-ext.adoc,288,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)","For a given supported fractional LMUL setting, implementations must support SEW settings between SEW~MIN~ and LMUL * ELEN, inclusive.",non_CSR_parameter,enum,very_high,False, +chunk_abf96fb1,src/v-st-ext.adoc,292,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)","The use of `vtype` encodings with LMUL < SEW~MIN~/ELEN is reserved, but implementations can set `vill` if they do not support these configurations.",CSR_controlled,enum,high,False, +chunk_2c7941b0,src/v-st-ext.adoc,309,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)",The derived value VLMAX = LMUL*VLEN/SEW represents the maximum number of elements that can be operated on with a single vector instruction given the current SEW and LMUL settings as shown in the table below.,CSR_controlled,range,high,False, +chunk_2e07878e,src/v-st-ext.adoc,329,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)",Instructions specifying an LMUL=2 vector register group with an odd-numbered vector register are reserved.,unknown,unknown,high,False, +chunk_059a9151,src/v-st-ext.adoc,334,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)","When LMUL=4, the vector register group contains four vector registers, and instructions specifying an LMUL=4 vector register group using vector register numbers that are not multiples of four are reserved.",unknown,unknown,high,False, +chunk_cab34478,src/v-st-ext.adoc,338,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)","When LMUL=8, the vector register group contains eight vector registers, and instructions specifying an LMUL=8 vector register group using register numbers that are not multiples of eight are reserved.",unknown,unknown,high,False, +chunk_e478d910,src/v-st-ext.adoc,342,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)","Mask registers are always contained in a single vector register, regardless of LMUL.",unknown,unknown,high,False, +chunk_4bd30b70,src/v-st-ext.adoc,350,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma`",These two bits modify the behavior of destination tail elements and destination inactive masked-off elements respectively during the execution of vector instructions.,unknown,unknown,high,False, +chunk_52063155,src/v-st-ext.adoc,350,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma`","The tail and inactive sets contain element positions that are not receiving new results during a vector operation,",unknown,unknown,high,False, +chunk_62203d67,src/v-st-ext.adoc,357,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma`",All systems must support all four options:,non_CSR_parameter,enum,very_high,False, +chunk_cf2d4fda,src/v-st-ext.adoc,360,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma`","[cols=""1,1,3,3""] | | `vta` | `vma` | Tail Elements | Inactive Elements",unknown,unknown,high,False, +chunk_9d5641cd,src/v-st-ext.adoc,365,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma`",| 0 | 0 | undisturbed | undisturbed | 0 | 1 | undisturbed | agnostic | 1 | 0 | agnostic | undisturbed | 1 | 1 | agnostic | agnostic |,unknown,unknown,high,False, +chunk_6e40ff6c,src/v-st-ext.adoc,371,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma`","Mask destination tail elements are always treated as tail-agnostic, regardless of the setting of `vta`.",unknown,unknown,high,False, +chunk_e647f308,src/v-st-ext.adoc,375,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma`","When a set is marked undisturbed, the corresponding set of destination elements in a vector register group retain the value they previously held.",unknown,unknown,high,False, +chunk_c676cdc4,src/v-st-ext.adoc,380,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma`","When a set is marked agnostic, the corresponding set of destination elements in any vector destination operand can either retain the value they previously held, or are overwritten with 1s.",unknown,enum,high,False, +chunk_a901278d,src/v-st-ext.adoc,380,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma`","Within a single vector instruction, each destination element can be either left undisturbed or overwritten with 1s, in any combination, and the pattern of undisturbed or overwritten with 1s is not required to be deterministic when the instruction is executed with the same inputs.",non_CSR_parameter,enum,high,False, +chunk_d4bc9d75,src/v-st-ext.adoc,389,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma`","With an undisturbed policy, all elements would have to be read from the old physical destination vector register to be copied into the new physical destination vector register.",unknown,unknown,high,False, +chunk_f7248ab1,src/v-st-ext.adoc,389,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma`",This causes an inefficiency when these inactive or tail values are not required for subsequent calculations.,unknown,unknown,high,False, +chunk_6d0aa5ef,src/v-st-ext.adoc,400,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma`",The `vta` and `vma` state bits must still be provided in `vtype` for compatibility and to support thread migration.,CSR_controlled,enum,very_high,False, +chunk_382f7cbc,src/v-st-ext.adoc,409,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma`","As it might be necessary to restart in the middle, we allow arbitrary mixing of agnostic policies within a single vector instruction.",unknown,unknown,high,False, +chunk_0f653bae,src/v-st-ext.adoc,421,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma`","In addition, except for mask load instructions, any element in the tail of a mask result can also be written with the value the mask-producing operation would have calculated with `vl`=VLMAX.",CSR_controlled,enum,high,False, +chunk_e201e0d2,src/v-st-ext.adoc,431,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma`",There appears to be little software need to support tail-undisturbed for mask register values.,SW_rule,unknown,high,False, +chunk_0c7925a1,src/v-st-ext.adoc,431,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma`","Allowing mask-generating instructions to write back the result of the instruction avoids the need for logic to mask out the tail, except mask loads cannot write memory values to destination mask tails as this would imply accessing memory past software intent.",SW_rule,unknown,high,False, +chunk_ab050261,src/v-st-ext.adoc,440,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma`",The assembly syntax adds two mandatory flags to the `vsetvli` instruction:,CSR_controlled,enum,high,False, +chunk_fe22b9c1,src/v-st-ext.adoc,442,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma`",---- ta Tail agnostic tu Tail undisturbed ma Mask agnostic mu Mask undisturbed,unknown,unknown,high,False, +chunk_3294b759,src/v-st-ext.adoc,448,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma`","vsetvli t0, a0, e32, m4, ta, ma Tail agnostic, mask agnostic vsetvli t0, a0, e32, m4, tu, ma Tail undisturbed, mask agnostic vsetvli t0, a0, e32, m4, ta, mu Tail agnostic, mask undisturbed vsetvli t0, a0, e32, m4, tu, mu Tail undisturbed, mask undisturbed ----",CSR_controlled,enum,high,False, +chunk_380b9eb2,src/v-st-ext.adoc,454,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma`","The use of `vsetvli` without these flags is deprecated, however, and specifying a flag setting is now mandatory.",CSR_controlled,enum,high,False, +chunk_ca56a477,src/v-st-ext.adoc,454,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma`","The default should perhaps be tail-agnostic/mask-agnostic, so software has to specify when it cares about the non-participating elements, but given the historical meaning of the instruction prior to introduction of these flags, it was decided to always require them in future assembly code.",SW_rule,enum,high,False, +chunk_e2f6f4fa,src/v-st-ext.adoc,465,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Type Illegal (`vill`)",The `vill` bit is used to encode that a previous `vset{i}vl{i}` instruction attempted to write an unsupported value to `vtype`.,CSR_controlled,enum,high,False, +chunk_3f095a40,src/v-st-ext.adoc,471,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Type Illegal (`vill`)","If the `vill` bit is set, then any attempt to execute a vector instruction that depends upon `vtype` will raise an illegal-instruction exception.",CSR_controlled,enum,high,False, +chunk_e8852c78,src/v-st-ext.adoc,478,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Type Illegal (`vill`)","When the `vill` bit is set, the other XLEN-1 bits in `vtype` shall be zero.",CSR_controlled,range,very_high,False, +chunk_ed4676a7,src/v-st-ext.adoc,483,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Length (`vl`) Register","The XLEN-bit-wide read-only `vl` CSR can only be updated by the `vset{i}vl{i}` instructions, and the fault-only-first vector load instruction variants.",CSR_controlled,range,high,False, +chunk_80d9c7fe,src/v-st-ext.adoc,488,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Length (`vl`) Register","The `vl` register holds an unsigned integer specifying the number of elements to be updated with results from a vector instruction, as further detailed in .",CSR_controlled,enum,high,False, +chunk_0830e388,src/v-st-ext.adoc,493,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Length (`vl`) Register","The smallest vector implementation with VLEN=32 and supporting SEW=8 would need at least six bits in `vl` to hold the values 0-32 (VLEN=32, with LMUL=8 and SEW=8, yields VLMAX=32).",CSR_controlled,range,high,False, +chunk_96b18efb,src/v-st-ext.adoc,514,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Start Index (`vstart`) Register","The XLEN-bit-wide read-write `vstart` CSR specifies the index of the first element to be executed by a vector instruction, as described in .",CSR_controlled,range,high,False, +chunk_49e0d509,src/v-st-ext.adoc,519,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Start Index (`vstart`) Register","Normally, `vstart` is only written by hardware on a trap on a vector instruction, with the `vstart` value representing the element on which the trap was taken (either a synchronous exception or an asynchronous interrupt), and at which execution should resume after a resumable trap is handled.",CSR_controlled,enum,high,False, +chunk_874ef282,src/v-st-ext.adoc,525,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Start Index (`vstart`) Register","All vector instructions are defined to begin execution with the element number given in the `vstart` CSR, leaving earlier elements in the destination vector undisturbed, and to reset the `vstart` CSR to zero at the end of execution.",CSR_controlled,enum,high,False, +chunk_11535194,src/v-st-ext.adoc,533,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Start Index (`vstart`) Register",`vstart` is not modified by vector instructions that raise illegal-instruction exceptions.,CSR_controlled,enum,high,False, +chunk_f186a2d8,src/v-st-ext.adoc,537,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Start Index (`vstart`) Register",The `vstart` CSR is defined to have only enough writable bits to hold the largest element index (one less than the maximum VLMAX).,CSR_controlled,range,high,False, +chunk_6c161904,src/v-st-ext.adoc,545,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Start Index (`vstart`) Register",The use of `vstart` values greater than the largest element index for the current `vtype` setting is reserved.,CSR_controlled,range,high,False, +chunk_fd9b2c24,src/v-st-ext.adoc,549,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Start Index (`vstart`) Register","It is not required to trap, as a possible future use of upper `vstart` bits is to store imprecise trap information.",CSR_controlled,enum,high,False, +chunk_e6535f14,src/v-st-ext.adoc,553,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Start Index (`vstart`) Register","The `vstart` CSR is writable by unprivileged code, but non-zero `vstart` values may cause vector instructions to run substantially slower on some implementations, so `vstart` should not be used by application programmers. A few vector instructions cannot be executed with a non-zero `vstart` value and will raise an illegal-instruction exception as defined below.",CSR_controlled,enum,high,False, +chunk_54ca22af,src/v-st-ext.adoc,563,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Start Index (`vstart`) Register",Implementations are permitted to raise illegal-instruction exceptions when attempting to execute a vector instruction with a value of `vstart` that the implementation can never produce when executing that same instruction with the same `vtype` setting.,CSR_controlled,enum,high,False, +chunk_b7bfd38e,src/v-st-ext.adoc,569,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Start Index (`vstart`) Register",Such implementations are permitted to raise an illegal-instruction exception when attempting to execute a vector arithmetic instruction when `vstart` is nonzero.,CSR_controlled,enum,high,False, +chunk_46f5cca6,src/v-st-ext.adoc,575,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Start Index (`vstart`) Register","When migrating a software thread between two harts with different microarchitectures, the `vstart` value might not be supported by the new hart microarchitecture.",CSR_controlled,enum,high,False, +chunk_e612aca8,src/v-st-ext.adoc,575,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Start Index (`vstart`) Register",The runtime on the receiving hart might then have to emulate instruction execution up to the next supported `vstart` element position.,CSR_controlled,enum,high,False, +chunk_40a29758,src/v-st-ext.adoc,575,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Start Index (`vstart`) Register","Alternatively, migration events can be constrained to only occur at mutually supported `vstart` locations.",CSR_controlled,enum,high,False, +chunk_20f1c61e,src/v-st-ext.adoc,584,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Fixed-Point Rounding Mode (`vxrm`) Register","The upper bits, `vxrm[XLEN-1:2]`, should be written as zeros.",CSR_controlled,enum,high,False, +chunk_61649f19,src/v-st-ext.adoc,590,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Fixed-Point Rounding Mode (`vxrm`) Register","The vector fixed-point rounding-mode is given a separate CSR address to allow independent access, but is also reflected as a field in `vcsr`.",CSR_controlled,enum,high,False, +chunk_f4447951,src/v-st-ext.adoc,598,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Fixed-Point Rounding Mode (`vxrm`) Register",The fixed-point rounding algorithm is specified as follows.,unknown,unknown,high,False, +chunk_9d18a174,src/v-st-ext.adoc,598,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Fixed-Point Rounding Mode (`vxrm`) Register","Suppose the pre-rounding result is `v`, and `d` bits of that result are to be rounded off.",unknown,unknown,high,False, +chunk_d08a2eeb,src/v-st-ext.adoc,598,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Fixed-Point Rounding Mode (`vxrm`) Register","Then the rounded result is `(v >> d) + r`, where `r` depends on the rounding mode as specified in the following table.",non_CSR_parameter,unknown,high,False, +chunk_387d4e3e,src/v-st-ext.adoc,617,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Fixed-Point Rounding Mode (`vxrm`) Register","The rounding functions: ---- roundoffunsigned(v, d) = (unsigned(v) >> d) + r roundoffsigned(v, d) = (signed(v) >> d) + r ---- are used to represent this operation in the instruction descriptions below.",unknown,unknown,high,False, +chunk_48bae0cc,src/v-st-ext.adoc,626,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Fixed-Point Saturation Flag (`vxsat`)",The `vxsat` CSR has a single read-write least-significant bit (`vxsat[0]`) that indicates if a fixed-point instruction has had to saturate an output value to fit into a destination format.,CSR_controlled,enum,high,False, +chunk_2ae89361,src/v-st-ext.adoc,626,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Fixed-Point Saturation Flag (`vxsat`)",Bits `vxsat[XLEN-1:1]` should be written as zeros.,CSR_controlled,enum,high,False, +chunk_c5769816,src/v-st-ext.adoc,632,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Fixed-Point Saturation Flag (`vxsat`)",The `vxsat` bit is mirrored in `vcsr`.,CSR_controlled,enum,high,False, +chunk_e05c2c3e,src/v-st-ext.adoc,637,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Control and Status (`vcsr`) Register","The `vxrm` and `vxsat` separate CSRs can also be accessed via fields in the XLEN-bit-wide vector control and status CSR, `vcsr`.",CSR_controlled,range,high,False, +chunk_b3802007,src/v-st-ext.adoc,647,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Control and Status (`vcsr`) Register",| XLEN-1:3 | | Reserved | 2:1 | vxrm[1:0] | Fixed-point rounding mode | 0 | vxsat | Fixed-point accrued saturation flag |,CSR_controlled,enum,high,False, +chunk_5af03e29,src/v-st-ext.adoc,654,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > State of Vector Extension at Reset",The vector extension must have a consistent state at reset.,non_CSR_parameter,enum,very_high,False, +chunk_73e87195,src/v-st-ext.adoc,654,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > State of Vector Extension at Reset","In particular, `vtype` and `vl` must have values that can be read and then restored with a single `vsetvl` instruction.",CSR_controlled,enum,very_high,False, +chunk_8d61799d,src/v-st-ext.adoc,661,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > State of Vector Extension at Reset","The `vstart`, `vxrm`, `vxsat` CSRs can have arbitrary values at reset.",CSR_controlled,enum,high,False, +chunk_36882137,src/v-st-ext.adoc,663,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > State of Vector Extension at Reset",The `vxrm` and `vxsat` fields should be reset explicitly in software before use.,CSR_controlled,enum,high,False, +chunk_e481ceb3,src/v-st-ext.adoc,671,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State","The following diagrams illustrate how different width elements are packed into the bytes of a vector register depending on the current SEW and LMUL settings, as well as implementation VLEN.",CSR_controlled,enum,high,False, +chunk_1aa12ceb,src/v-st-ext.adoc,671,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State",Elements are packed into each vector register with the least-significant byte in the lowest-numbered bits.,unknown,unknown,high,False, +chunk_3cdaaf87,src/v-st-ext.adoc,677,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State","The mapping was chosen to provide the simplest and most portable model for software, but might appear to incur large wiring cost for wider vector datapaths on certain operations.",SW_rule,unknown,high,False, +chunk_da3cbc85,src/v-st-ext.adoc,691,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping for LMUL = 1","When LMUL=1, elements are simply packed in order from the least-significant to most-significant bits of the vector register.",unknown,unknown,high,False, +chunk_54d91bfc,src/v-st-ext.adoc,695,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping for LMUL = 1",Bits within an element are numbered in a little-endian format with increasing bit index from right to left corresponding to increasing magnitude.,unknown,unknown,high,False, +chunk_b40e4e1f,src/v-st-ext.adoc,704,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping for LMUL = 1",The element index is given in hexadecimal and is shown placed at the least-significant byte of the stored element.,unknown,unknown,high,False, +chunk_2489fc21,src/v-st-ext.adoc,711,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping for LMUL = 1",SEW=8b 3 2 1 0 SEW=16b 1 0 SEW=32b 0,unknown,unknown,high,False, +chunk_5d1900d8,src/v-st-ext.adoc,719,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping for LMUL = 1",SEW=8b 7 6 5 4 3 2 1 0 SEW=16b 3 2 1 0 SEW=32b 1 0 SEW=64b 0,unknown,unknown,high,False, +chunk_d19d0ab7,src/v-st-ext.adoc,726,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping for LMUL = 1",Byte F E D C B A 9 8 7 6 5 4 3 2 1 0,unknown,unknown,high,False, +chunk_8e5330ce,src/v-st-ext.adoc,728,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping for LMUL = 1",SEW=8b F E D C B A 9 8 7 6 5 4 3 2 1 0 SEW=16b 7 6 5 4 3 2 1 0 SEW=32b 3 2 1 0 SEW=64b 1 0,unknown,unknown,high,False, +chunk_00705a24,src/v-st-ext.adoc,735,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping for LMUL = 1",Byte 1F1E1D1C1B1A19181716151413121110 F E D C B A 9 8 7 6 5 4 3 2 1 0,unknown,unknown,high,False, +chunk_47b6344f,src/v-st-ext.adoc,737,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping for LMUL = 1",SEW=8b 1F1E1D1C1B1A19181716151413121110 F E D C B A 9 8 7 6 5 4 3 2 1 0 SEW=16b F E D C B A 9 8 7 6 5 4 3 2 1 0 SEW=32b 7 6 5 4 3 2 1 0 SEW=64b 3 2 1 0 ----,unknown,unknown,high,False, +chunk_2c5a6859,src/v-st-ext.adoc,746,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping for LMUL < 1","When LMUL < 1, only the first LMUL*VLEN/SEW elements in the vector register are used.",CSR_controlled,enum,high,False, +chunk_b5cd7129,src/v-st-ext.adoc,746,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping for LMUL < 1","The remaining space in the vector register is treated as part of the tail, and hence must obey the vta setting.",non_CSR_parameter,enum,very_high,False, +chunk_2d95f4d5,src/v-st-ext.adoc,754,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping for LMUL < 1",Byte F E D C B A 9 8 7 6 5 4 3 2 1 0,unknown,unknown,high,False, +chunk_26be5177,src/v-st-ext.adoc,756,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping for LMUL < 1",SEW=8b - - - - - - - - - - - - 3 2 1 0 SEW=16b - - - - - - 1 0 SEW=32b - - - 0 ----,unknown,unknown,high,False, +chunk_642d8cf4,src/v-st-ext.adoc,763,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping for LMUL > 1","When vector registers are grouped, the elements of the vector register group are packed contiguously in element order beginning with the lowest-numbered vector register and moving to the next-highest-numbered vector register in the group once each vector register is filled.",unknown,unknown,high,False, +chunk_bc5eba89,src/v-st-ext.adoc,775,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping for LMUL > 1",Byte 3 2 1 0 v2*n 3 2 1 0 v2*n+1 7 6 5 4,unknown,unknown,high,False, +chunk_63f0b9b1,src/v-st-ext.adoc,781,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping for LMUL > 1",Byte 3 2 1 0 v2*n 1 0 v2*n+1 3 2,unknown,unknown,high,False, +chunk_95a9f49f,src/v-st-ext.adoc,787,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping for LMUL > 1",Byte 3 2 1 0 v4*n 1 0 v4*n+1 3 2 v4*n+2 5 4 v4*n+3 7 6,unknown,unknown,high,False, +chunk_d7599f7f,src/v-st-ext.adoc,795,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping for LMUL > 1",Byte 3 2 1 0 v4*n 0 v4*n+1 1 v4*n+2 2 v4*n+3 3,unknown,unknown,high,False, +chunk_b6642a6b,src/v-st-ext.adoc,803,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping for LMUL > 1",Byte 7 6 5 4 3 2 1 0 v2*n 1 0 v2*n+1 3 2,unknown,unknown,high,False, +chunk_03846ff1,src/v-st-ext.adoc,809,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping for LMUL > 1",Byte 7 6 5 4 3 2 1 0 v4*n 1 0 v4*n+1 3 2 v4*n+2 5 4 v4*n+3 7 6,unknown,unknown,high,False, +chunk_75a6490e,src/v-st-ext.adoc,817,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping for LMUL > 1",Byte F E D C B A 9 8 7 6 5 4 3 2 1 0 v2*n 3 2 1 0 v2*n+1 7 6 5 4,unknown,unknown,high,False, +chunk_6eb0e4a2,src/v-st-ext.adoc,823,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping for LMUL > 1",Byte F E D C B A 9 8 7 6 5 4 3 2 1 0 v4*n 3 2 1 0 v4*n+1 7 6 5 4 v4*n+2 B A 9 8 v4*n+3 F E D C ----,unknown,unknown,high,False, +chunk_4bd6f882,src/v-st-ext.adoc,833,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping across Mixed-Width Operations",The recommended software strategy when operating on multiple vectors with different precision values is to modify `vtype` dynamically to keep SEW/LMUL constant (and hence VLMAX constant).,CSR_controlled,enum,high,False, +chunk_4273fab1,src/v-st-ext.adoc,839,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping across Mixed-Width Operations","The following example shows four different packed element widths (8b, 16b, 32b, 64b) in a VLEN=128b implementation.",CSR_controlled,enum,high,False, +chunk_2706a7b4,src/v-st-ext.adoc,839,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping across Mixed-Width Operations",The vector register grouping factor (LMUL) is increased by the relative element size such that each group can hold the same number of vector elements (VLMAX=8 in this example) to simplify strip-mining code.,CSR_controlled,enum,high,False, +chunk_23cd3004,src/v-st-ext.adoc,848,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping across Mixed-Width Operations","Byte F E D C B A 9 8 7 6 5 4 3 2 1 0 vn - - - - - - - - 7 6 5 4 3 2 1 0 SEW=8b, LMUL=1/2",unknown,unknown,high,False, +chunk_b13bf5c4,src/v-st-ext.adoc,851,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping across Mixed-Width Operations","vn 7 6 5 4 3 2 1 0 SEW=16b, LMUL=1",unknown,unknown,high,False, +chunk_4a696ffa,src/v-st-ext.adoc,853,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping across Mixed-Width Operations","v2*n 3 2 1 0 SEW=32b, LMUL=2 v2*n+1 7 6 5 4",unknown,unknown,high,False, +chunk_d242e6af,src/v-st-ext.adoc,856,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping across Mixed-Width Operations","v4*n 1 0 SEW=64b, LMUL=4 v4*n+1 3 2 v4*n+2 5 4 v4*n+3 7 6 ----",unknown,unknown,high,False, +chunk_62236b15,src/v-st-ext.adoc,862,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping across Mixed-Width Operations",The following table shows each possible constant SEW/LMUL operating point for loops with mixed-width operations.,unknown,unknown,high,False, +chunk_0949b082,src/v-st-ext.adoc,862,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping across Mixed-Width Operations",Each column represents a constant SEW/LMUL operating point.,unknown,unknown,high,False, +chunk_7b712bae,src/v-st-ext.adoc,862,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping across Mixed-Width Operations",Entries in table are the LMUL values that yield that column's SEW/LMUL value for the data width on that row.,unknown,unknown,high,False, +chunk_85d2a9b7,src/v-st-ext.adoc,862,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping across Mixed-Width Operations","In each column, an LMUL setting for a data width indicates that it can be aligned with the other data widths in the same column that also have an LMUL setting, such that all have the same VLMAX.",CSR_controlled,enum,high,False, +chunk_6aae7a5b,src/v-st-ext.adoc,870,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping across Mixed-Width Operations",| | 7+^| SEW/LMUL | | 1 | 2 | 4 | 8 | 16 | 32 | 64,unknown,unknown,high,False, +chunk_3e044c94,src/v-st-ext.adoc,874,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping across Mixed-Width Operations",| SEW= 8 | 8 | 4 | 2 | 1 | 1/2 | 1/4 | 1/8 | SEW= 16 | | 8 | 4 | 2 | 1 | 1/2 | 1/4 | SEW= 32 | | | 8 | 4 | 2 | 1 | 1/2 | SEW= 64 | | | | 8 | 4 | 2 | 1 |,unknown,unknown,high,False, +chunk_8f5f8d0b,src/v-st-ext.adoc,880,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping across Mixed-Width Operations",Larger LMUL settings can also used to simply increase vector length to reduce instruction fetch and dispatch overheads in cases where fewer vector register groups are needed.,unknown,unknown,high,False, +chunk_1dbb37f1,src/v-st-ext.adoc,887,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mask Register Layout",A vector mask occupies only one vector register regardless of SEW and LMUL.,unknown,unknown,high,False, +chunk_1bc4d072,src/v-st-ext.adoc,891,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mask Register Layout",Each element is allocated a single mask bit in a mask vector register.,unknown,unknown,high,False, +chunk_800e13ed,src/v-st-ext.adoc,891,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mask Register Layout","The mask bit for element i is located in bit i of the mask register, independent of SEW or LMUL.",unknown,unknown,high,False, +chunk_1c47f08c,src/v-st-ext.adoc,901,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats",Vector loads and stores are encoded within the scalar floating-point load and store major opcodes (LOAD-FP/STORE-FP).,unknown,enum,high,False, +chunk_4e824fcd,src/v-st-ext.adoc,948,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Vector Operands","By default, for most operands of most instructions, EEW=SEW and EMUL=LMUL.",unknown,unknown,high,False, +chunk_838f92a2,src/v-st-ext.adoc,963,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Vector Operands","Vector operands or results may occupy one or more vector registers depending on EMUL, but are always specified using the lowest-numbered vector register in the group.",non_CSR_parameter,enum,medium,False, +chunk_5bb645c0,src/v-st-ext.adoc,969,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Vector Operands","An encoding that would result in the same vector register being read with two or more different EEWs, including when the vector register appears at different positions within two or more vector register groups, is reserved.",unknown,enum,high,False, +chunk_e9a44fbe,src/v-st-ext.adoc,983,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Vector Operands",A destination vector register group can overlap a source vector register group only if one of the following holds:,unknown,enum,high,False, +chunk_ffeacabb,src/v-st-ext.adoc,1010,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Vector Operands","When source and destination registers overlap and have different EEW, the instruction is mask- and tail-agnostic, regardless of the setting of the `vta` and `vma` bits in `vtype`.",CSR_controlled,enum,high,False, +chunk_81aa6583,src/v-st-ext.adoc,1030,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Vector Masking",Element operations that are masked off (inactive) never generate exceptions.,unknown,unknown,high,False, +chunk_74460c10,src/v-st-ext.adoc,1030,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Vector Masking",The destination vector register elements corresponding to masked-off elements are handled with either a mask-undisturbed or mask-agnostic policy depending on the setting of the `vma` bit in `vtype` ().,CSR_controlled,enum,high,False, +chunk_bcb4bbe5,src/v-st-ext.adoc,1066,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Vector Masking > Mask Encoding","Where available, masking is encoded in a single-bit `vm` field in the instruction (`inst[25]`).",unknown,enum,high,False, +chunk_616a0657,src/v-st-ext.adoc,1078,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Vector Masking > Mask Encoding","Vector masking is represented in assembler code as another vector operand, with `.t` indicating that the operation occurs when `v0.mask[i]` is `1` (`t` for ""true"").",unknown,unknown,high,False, +chunk_c36221d3,src/v-st-ext.adoc,1078,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Vector Masking > Mask Encoding","If no masking operand is specified, unmasked vector execution (`vm=1`) is assumed.",unknown,unknown,high,False, +chunk_2fbc3961,src/v-st-ext.adoc,1105,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Prestart, Active, Inactive, Body, and Tail Element Definitions",The prestart elements are those whose element index is less than the initial value in the `vstart` register.,CSR_controlled,range,high,False, +chunk_8157fc43,src/v-st-ext.adoc,1105,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Prestart, Active, Inactive, Body, and Tail Element Definitions",The prestart elements do not raise exceptions and do not update the destination vector register.,non_CSR_parameter,unknown,high,False, +chunk_db16c30e,src/v-st-ext.adoc,1108,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Prestart, Active, Inactive, Body, and Tail Element Definitions","The body elements are those whose element index is greater than or equal to the initial value in the `vstart` register, and less than the current vector length setting in `vl`.",CSR_controlled,range,high,False, +chunk_03604f63,src/v-st-ext.adoc,1112,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Prestart, Active, Inactive, Body, and Tail Element Definitions",The active elements can raise exceptions and update the destination vector register group.,non_CSR_parameter,unknown,high,False, +chunk_e12a5ef7,src/v-st-ext.adoc,1116,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Prestart, Active, Inactive, Body, and Tail Element Definitions","The inactive elements do not raise exceptions and do not update any destination vector register group unless masked agnostic is specified (`vtype.vma`=1), in which case inactive elements may be overwritten with 1s.",CSR_controlled,enum,high,False, +chunk_8d8fc413,src/v-st-ext.adoc,1120,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Prestart, Active, Inactive, Body, and Tail Element Definitions",The tail elements during a vector instruction's execution are the elements past the current vector length setting specified in `vl`.,CSR_controlled,enum,high,False, +chunk_38e1c0ce,src/v-st-ext.adoc,1120,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Prestart, Active, Inactive, Body, and Tail Element Definitions","The tail elements do not raise exceptions, and do not update any destination vector register group unless tail agnostic is specified (`vtype.vta`=1), in which case tail elements may be overwritten with 1s, or with the result of the instruction in the case of mask-producing instructions except for mask loads.",CSR_controlled,enum,high,False, +chunk_7a8c3b86,src/v-st-ext.adoc,1120,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Prestart, Active, Inactive, Body, and Tail Element Definitions","When LMUL < 1, the tail includes the elements past VLMAX that are held in the same vector register.",CSR_controlled,enum,high,False, +chunk_cb85a7a1,src/v-st-ext.adoc,1124,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Prestart, Active, Inactive, Body, and Tail Element Definitions","---- for element index x prestart(x) = (0 <= x < vstart) body(x) = (vstart <= x < vl) tail(x) = (vl <= x < max(VLMAX,VLEN/SEW)) mask(x) = unmasked || v0.mask[x] 1 active(x) = body(x) && mask(x) inactive(x) = body(x) && !mask(x) ----",CSR_controlled,enum,high,False, +chunk_7abd1fbf,src/v-st-ext.adoc,1134,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Prestart, Active, Inactive, Body, and Tail Element Definitions","When `vstart` {ge} `vl`, there are no body elements, and no elements are updated in any destination vector register group, including that no tail elements are updated with agnostic values.",CSR_controlled,enum,high,False, +chunk_0646c622,src/v-st-ext.adoc,1143,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Prestart, Active, Inactive, Body, and Tail Element Definitions","Instructions that write an `x` register or `f` register do so even when `vstart` {ge} `vl`, including when `vl`=0.",CSR_controlled,enum,high,False, +chunk_6e31e5d5,src/v-st-ext.adoc,1147,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Prestart, Active, Inactive, Body, and Tail Element Definitions",The general policy is to return the value 0 when the index is greater than VLMAX in the source vector register group.,CSR_controlled,range,high,False, +chunk_a2daceee,src/v-st-ext.adoc,1155,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`)","The application specifies the total number of elements to be processed (the application vector length or AVL) as a candidate value for `vl`, and the hardware responds via a general-purpose register with the (frequently smaller) number of elements that the hardware will handle per iteration (stored in `vl`), based on the microarchitectural implementation and the `vtype` setting. A straightforward loop structure, shown in , depicts the ease with which the code keeps track of the remaining number of elements and the amount per iteration handled by hardware.",CSR_controlled,enum,high,False, +chunk_983fab24,src/v-st-ext.adoc,1168,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`)",A set of instructions is provided to allow rapid configuration of the values in `vl` and `vtype` to match application needs.,CSR_controlled,enum,high,False, +chunk_6b11e34b,src/v-st-ext.adoc,1168,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`)","The `vset{i}vl{i}` instructions set the `vtype` and `vl` CSRs based on their arguments, and write the new value of `vl` into `rd`.",CSR_controlled,enum,high,False, +chunk_d08063ef,src/v-st-ext.adoc,1173,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`)","---- vsetvli rd, rs1, vtypei rd = new vl, rs1 = AVL, vtypei = new vtype setting vsetivli rd, uimm, vtypei rd = new vl, uimm = AVL, vtypei = new vtype setting vsetvl rd, rs1, rs2 rd = new vl, rs1 = AVL, rs2 = new vtype value ----",CSR_controlled,enum,high,False, +chunk_cccadccc,src/v-st-ext.adoc,1185,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > `vtype` encoding","The new `vtype` value is encoded in the immediate fields of `vsetvli` and `vsetivli`, and in the `rs2` register for `vsetvl`.",CSR_controlled,enum,high,False, +chunk_f9421ee1,src/v-st-ext.adoc,1189,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > `vtype` encoding",---- Suggested assembler names used for vset{i}vli vtypei immediate,CSR_controlled,enum,high,False, +chunk_de3c6ab2,src/v-st-ext.adoc,1205,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > `vtype` encoding","Examples: vsetvli t0, a0, e8, m1, ta, ma SEW= 8, LMUL=1 vsetvli t0, a0, e8, m2, ta, ma SEW= 8, LMUL=2 vsetvli t0, a0, e32, mf2, ta, ma SEW=32, LMUL=1/2 ----",CSR_controlled,enum,high,False, +chunk_7a158acb,src/v-st-ext.adoc,1211,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > `vtype` encoding",The `vsetvl` variant operates similarly to `vsetvli` except that it takes a `vtype` value from `rs2` and can be used for context restore.,CSR_controlled,enum,high,False, +chunk_2153b69c,src/v-st-ext.adoc,1216,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > `vtype` encoding > Unsupported `vtype` Values","If the `vtype` value is not supported by the implementation, then the `vill` bit is set in `vtype`, the remaining bits in `vtype` are set to zero, and the `vl` register is also set to zero.",CSR_controlled,binary,high,False, +chunk_da8f6255,src/v-st-ext.adoc,1220,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > `vtype` encoding > Unsupported `vtype` Values","However, this would have added the first data-dependent trap on a CSR write to the ISA.",CSR_controlled,enum,high,False, +chunk_4f481530,src/v-st-ext.adoc,1220,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > `vtype` encoding > Unsupported `vtype` Values","Implementations could choose to trap when illegal values are written to `vtype` instead of setting `vill`, to allow emulation to support new configurations for forward-compatibility.",CSR_controlled,enum,high,False, +chunk_a123b49a,src/v-st-ext.adoc,1220,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > `vtype` encoding > Unsupported `vtype` Values",The current scheme supports light-weight runtime interrogation of the supported vector unit configurations by checking if `vill` is clear for a given setting.,unknown,unknown,high,False, +chunk_d5e40453,src/v-st-ext.adoc,1229,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > `vtype` encoding > Unsupported `vtype` Values",A `vtype` value with `vill` set is treated as an unsupported configuration.,CSR_controlled,enum,high,False, +chunk_a20bbe5a,src/v-st-ext.adoc,1233,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > `vtype` encoding > Unsupported `vtype` Values",Implementations must consider all bits of the `vtype` value to determine if the configuration is supported.,CSR_controlled,enum,very_high,False, +chunk_4dd0c839,src/v-st-ext.adoc,1233,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > `vtype` encoding > Unsupported `vtype` Values",An unsupported value in any location within the `vtype` value must result in `vill` being set.,CSR_controlled,enum,very_high,False, +chunk_9c10de18,src/v-st-ext.adoc,1238,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > `vtype` encoding > Unsupported `vtype` Values",Implementations cannot ignore fields they do not implement.,unknown,enum,high,False, +chunk_8efcbd73,src/v-st-ext.adoc,1238,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > `vtype` encoding > Unsupported `vtype` Values",All bits must be checked to ensure that new code assuming unsupported vector features in `vtype` traps instead of executing incorrectly on an older implementation.,CSR_controlled,enum,very_high,False, +chunk_5bdb9f2f,src/v-st-ext.adoc,1246,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > AVL encoding","The new vector length setting is based on AVL, which for `vsetvli` and `vsetvl` is encoded in the `rs1` and `rd` fields as follows:",CSR_controlled,enum,high,False, +chunk_55fae626,src/v-st-ext.adoc,1260,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > AVL encoding","When rs1 is not `x0`, the AVL is an unsigned integer held in the `x` register specified by rs1, and the new `vl` value is also written to the `x` register specified by rd.",CSR_controlled,enum,high,False, +chunk_4e93bbbd,src/v-st-ext.adoc,1265,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > AVL encoding","When rs1=`x0` but rd!=`x0`, the maximum unsigned integer value (`~0`) is used as the AVL, and the resulting VLMAX is written to `vl` and also to the `x` register specified by `rd`.",CSR_controlled,range,high,False, +chunk_fa0458ed,src/v-st-ext.adoc,1270,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > AVL encoding","When rs1=`x0` and rd=`x0`, the instructions operate as if the current vector length in `vl` is used as the AVL, and the resulting value is written to `vl`, but not to a destination register.",CSR_controlled,enum,high,False, +chunk_efce93a0,src/v-st-ext.adoc,1270,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > AVL encoding",This form can only be used when VLMAX and hence `vl` is not actually changed by the new SEW/LMUL ratio.,CSR_controlled,enum,high,False, +chunk_55ecc5ba,src/v-st-ext.adoc,1270,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > AVL encoding",Use of the instructions with a new SEW/LMUL ratio that would result in a change of VLMAX is reserved.,CSR_controlled,enum,high,False, +chunk_77c3e146,src/v-st-ext.adoc,1270,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > AVL encoding",Use of the instructions is also reserved if `vill` was 1 beforehand.,unknown,unknown,high,False, +chunk_7b4d904f,src/v-st-ext.adoc,1270,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > AVL encoding",Implementations may set `vill` in either case.,non_CSR_parameter,enum,medium,False, +chunk_39f219b2,src/v-st-ext.adoc,1272,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > AVL encoding",This design was chosen to ensure `vl` would always hold a legal value for current `vtype` setting.,CSR_controlled,enum,high,False, +chunk_67f004f2,src/v-st-ext.adoc,1272,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > AVL encoding",The current `vl` value can be read from the `vl` CSR.,CSR_controlled,enum,high,False, +chunk_621489a4,src/v-st-ext.adoc,1272,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > AVL encoding","The `vl` value could be reduced by these instructions if the new SEW/LMUL ratio causes VLMAX to shrink, and so this case has been reserved as it is not clear this is a generally useful operation, and implementations can otherwise assume `vl` is not changed by these instructions to optimize their microarchitecture.",CSR_controlled,enum,high,False, +chunk_4ae85374,src/v-st-ext.adoc,1282,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > AVL encoding","For the `vsetivli` instruction, the AVL is encoded as a 5-bit zero-extended immediate (0--31) in the `rs1` field.",CSR_controlled,range,high,False, +chunk_c9912437,src/v-st-ext.adoc,1296,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > Constraints on Setting `vl`","The `vset{i}vl{i}` instructions first set VLMAX according to their `vtype` argument, then set `vl` obeying the following constraints:",CSR_controlled,enum,high,False, +chunk_3004082d,src/v-st-ext.adoc,1300,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > Constraints on Setting `vl`",Deterministic on any given implementation for same input AVL and VLMAX values .,CSR_controlled,enum,high,False, +chunk_402dab50,src/v-st-ext.adoc,1300,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > Constraints on Setting `vl`","These specific properties follow from the prior rules: .. `vl = 0` if `AVL = 0` .. `vl > 0` if `AVL > 0` .. `vl {le} VLMAX` .. `vl {le} AVL` .. a value read from `vl` when used as the AVL argument to `vset{i}vl{i}` results in the same value in `vl`, provided the resultant VLMAX equals the value of VLMAX at the time that `vl` was read",CSR_controlled,enum,high,False, +chunk_aa2ac48b,src/v-st-ext.adoc,1320,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > Constraints on Setting `vl`","Requirement 2 ensures that the first strip-mine iteration of reduction loops uses the largest vector length of all iterations, even in the case of `AVL < 2*VLMAX`.",CSR_controlled,enum,high,False, +chunk_2180ca08,src/v-st-ext.adoc,1320,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > Constraints on Setting `vl`",Requirement 2 also allows an implementation to set vl to VLMAX for `VLMAX < AVL < 2*VLMAX` --,CSR_controlled,enum,high,False, +chunk_f59c03df,src/v-st-ext.adoc,1334,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > Example of strip mining and changes to SEW","The SEW and LMUL settings can be changed dynamically to provide high throughput on mixed-width operations in a single loop. ---- Example: Load 16-bit values, widen multiply to 32b, shift 32b result right by 3, store 32b values.",non_CSR_parameter,range,medium,False, +chunk_08b7e239,src/v-st-ext.adoc,1352,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > Example of strip mining and changes to SEW","vsetvli x0, x0, e32, m8, ta, ma Operate on 32b values vsrl.vi v8, v8, 3 vse32.v v8, (a2) Store vector of 32b elements slli t1, a3, 2 Multiply elements this iteration by 4 bytes/destination element add a2, a2, t1 Bump pointer sub a0, a0, a3 Decrement count by vl bnez a0, loop Any more? ----",CSR_controlled,range,high,False, +chunk_7410d06d,src/v-st-ext.adoc,1364,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores","Vector loads and stores can be masked, and they only access memory or raise exceptions for active elements.",non_CSR_parameter,unknown,high,False, +chunk_d7acb521,src/v-st-ext.adoc,1364,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores","Masked vector loads do not update inactive elements in the destination vector register group, unless masked agnostic is specified (`vtype.vma`=1).",CSR_controlled,enum,high,False, +chunk_153d329d,src/v-st-ext.adoc,1364,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores",All vector loads and stores may generate and accept a non-zero `vstart` value.,CSR_controlled,enum,high,False, +chunk_4d0b3fae,src/v-st-ext.adoc,1376,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Instruction Encoding",Vector loads and stores are encoded within the scalar floating-point load and store major opcodes (LOAD-FP/STORE-FP).,unknown,enum,high,False, +chunk_eedf5d77,src/v-st-ext.adoc,1389,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Instruction Encoding","See | mop[1:0] | specifies memory addressing mode | nf[2:0] | specifies the number of fields in each segment, for segment load/stores | lumop[4:0]/sumop[4:0] | are additional fields encoding variants of unit-stride instructions |",unknown,enum,high,False, +chunk_30622221,src/v-st-ext.adoc,1402,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Instruction Encoding",Vector memory unit-stride and constant-stride operations directly encode EEW of the data to be transferred statically in the instruction to reduce the number of `vtype` changes when accessing memory in a mixed-width routine.,CSR_controlled,enum,high,False, +chunk_793aeb7a,src/v-st-ext.adoc,1424,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Addressing Modes","The data vector register group has EEW=SEW, EMUL=LMUL, while the offset vector register group has EEW encoded in the instruction and EMUL=(EEW/SEW)*LMUL.",unknown,enum,high,False, +chunk_5bb0d930,src/v-st-ext.adoc,1443,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Addressing Modes","If the vector offset elements are narrower than XLEN, they are zero-extended to XLEN before adding to the base effective address.",unknown,enum,high,False, +chunk_d2da2701,src/v-st-ext.adoc,1443,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Addressing Modes","If the vector offset elements are wider than XLEN, the least-significant XLEN bits are used in the address calculation.",unknown,range,high,False, +chunk_000cf0e1,src/v-st-ext.adoc,1443,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Addressing Modes","If the implementation does not support the EEW of the offset elements, the instruction is reserved.",unknown,unknown,high,False, +chunk_8c1cbf96,src/v-st-ext.adoc,1455,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Addressing Modes",The vector addressing modes are encoded using the 2-bit `mop[1:0]` field.,non_CSR_parameter,range,high,False, +chunk_fac8ce9f,src/v-st-ext.adoc,1487,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Addressing Modes","If the accesses are to a strongly ordered IO region, the element accesses can be initiated in any order.",unknown,unknown,high,False, +chunk_9e116f85,src/v-st-ext.adoc,1495,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Addressing Modes","For implementations with precise vector traps, exceptions on indexed-unordered stores must also be precise.",non_CSR_parameter,binary,very_high,False, +chunk_9be7667f,src/v-st-ext.adoc,1499,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Addressing Modes",Additional unit-stride vector addressing modes are encoded using the 5-bit `lumop` and `sumop` fields in the unit-stride load and store instruction encodings respectively.,non_CSR_parameter,range,high,False, +chunk_003dc0bf,src/v-st-ext.adoc,1508,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Addressing Modes","| 0 | 0 | 0 | 0 | 0 | unit-stride load | 0 | 1 | 0 | 0 | 0 | unit-stride, whole register load | 0 | 1 | 0 | 1 | 1 | unit-stride, mask load, EEW=8 | 1 | 0 | 0 | 0 | 0 | unit-stride fault-only-first | x | x | x | x | x | other encodings reserved |",unknown,enum,high,False, +chunk_2f486243,src/v-st-ext.adoc,1526,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Addressing Modes",The `nf[2:0]` field encodes the number of fields in each segment.,unknown,enum,high,False, +chunk_d6d1e392,src/v-st-ext.adoc,1526,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Addressing Modes",Larger values in the `nf` field are used to access multiple contiguous fields within a segment as described below in .,unknown,enum,high,False, +chunk_6fb69d97,src/v-st-ext.adoc,1534,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Addressing Modes",The `nf[2:0]` field also encodes the number of whole vector registers to transfer for the whole vector register load/store instructions.,unknown,enum,high,False, +chunk_9bd72c15,src/v-st-ext.adoc,1541,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Width Encoding",Vector loads and stores have an EEW encoded directly in the instruction.,unknown,enum,high,False, +chunk_bbdba0c6,src/v-st-ext.adoc,1541,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Width Encoding","If the EMUL would be out of range (EMUL>8 or EMUL<1/8), the instruction encoding is reserved.",unknown,enum,high,False, +chunk_7a47c928,src/v-st-ext.adoc,1541,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Width Encoding","The vector register groups must have legal register specifiers for the selected EMUL, otherwise the instruction encoding is reserved.",non_CSR_parameter,enum,very_high,False, +chunk_ad86c660,src/v-st-ext.adoc,1548,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Width Encoding","Vector unit-stride and constant-stride use the EEW/EMUL encoded in the instruction for the data values, while vector indexed loads and stores use the EEW/EMUL encoded in the instruction for the index values and the SEW/LMUL encoded in `vtype` for the data values.",CSR_controlled,enum,high,False, +chunk_ad14d11d,src/v-st-ext.adoc,1554,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Width Encoding",Vector loads and stores are encoded using width values that are not claimed by the standard scalar floating-point loads and stores.,unknown,enum,high,False, +chunk_19264dca,src/v-st-ext.adoc,1557,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Width Encoding",Implementations must provide vector loads and stores with EEWs corresponding to all supported SEW settings.,non_CSR_parameter,enum,very_high,False, +chunk_0c6aee9a,src/v-st-ext.adoc,1564,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Width Encoding",| Standard scalar FP | x | 0 | 0 | 1 | 16| FLEN | - | FLH/FSH | Standard scalar FP | x | 0 | 1 | 0 | 32| FLEN | - | FLW/FSW | Standard scalar FP | x | 0 | 1 | 1 | 64| FLEN | - | FLD/FSD | Standard scalar FP | x | 1 | 0 | 0 | 128| FLEN | - | FLQ/FSQ | Vector 8b element | 0 | 0 | 0 | 0 | 8| 8 | - | VLxE8/VSxE8 | Vector 16b element | 0 | 1 | 0 | 1 | 16| 16 | - | VLxE16/VSxE16 | Vector 32b element | 0 | 1 | 1 | 0 | 32| 32 | - | VLxE32/VSxE32 | Vector 64b element | 0 | 1 | 1 | 1 | 64| 64 | - | VLxE64/VSxE64 | Vector 8b index | 0 | 0 | 0 | 0 | SEW | SEW | 8 | VLxEI8/VSxEI8 | Vector 16b index | 0 | 1 | 0 | 1 | SEW | SEW | 16 | VLxEI16/VSxEI16 | Vector 32b index | 0 | 1 | 1 | 0 | SEW | SEW | 32 | VLxEI32/VSxEI32 | Vector 64b index | 0 | 1 | 1 | 1 | SEW | SEW | 64 | VLxEI64/VSxEI64 | Reserved | 1 | X | X | X | - | - | - | |,CSR_controlled,enum,high,False, +chunk_06e83c95,src/v-st-ext.adoc,1616,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Unit-Stride Instructions","---- Vector unit-stride mask load vlm.v vd, (rs1) Load byte vector of length ceil(vl/8)",CSR_controlled,enum,high,False, +chunk_8f80ad27,src/v-st-ext.adoc,1620,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Unit-Stride Instructions","Vector unit-stride mask store vsm.v vs3, (rs1) Store byte vector of length ceil(vl/8) ----",CSR_controlled,enum,high,False, +chunk_9e77658f,src/v-st-ext.adoc,1624,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Unit-Stride Instructions","`vlm.v` and `vsm.v` are encoded with the same `width[2:0]`=0 encoding as `vle8.v` and `vse8.v`, but are distinguished by different `lumop` and `sumop` encodings.",CSR_controlled,enum,high,False, +chunk_21bf3e84,src/v-st-ext.adoc,1624,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Unit-Stride Instructions","Since `vlm.v` and `vsm.v` operate as byte loads and stores, `vstart` is in units of bytes for these instructions.",CSR_controlled,enum,high,False, +chunk_060180a5,src/v-st-ext.adoc,1637,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Unit-Stride Instructions","However, these instructions also provide a convenient mechanism to use packed bit vectors in memory as mask values, and also reduce the cost of mask spill/fill by reducing need to change `vl`.",CSR_controlled,enum,high,False, +chunk_c579ff8a,src/v-st-ext.adoc,1649,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Constant-Stride Instructions","vd destination, rs1 base address, rs2 byte constant-stride vlse8.v vd, (rs1), rs2, vm 8-bit constant-stride load vlse16.v vd, (rs1), rs2, vm 16-bit constant-stride load vlse32.v vd, (rs1), rs2, vm 32-bit constant-stride load vlse64.v vd, (rs1), rs2, vm 64-bit constant-stride load",CSR_controlled,range,high,False, +chunk_30eaf178,src/v-st-ext.adoc,1655,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Constant-Stride Instructions","vs3 store data, rs1 base address, rs2 byte constant-stride vsse8.v vs3, (rs1), rs2, vm 8-bit constant-stride store vsse16.v vs3, (rs1), rs2, vm 16-bit constant-stride store vsse32.v vs3, (rs1), rs2, vm 32-bit constant-stride store vsse64.v vs3, (rs1), rs2, vm 64-bit constant-stride store ----",non_CSR_parameter,range,medium,False, +chunk_9ca3cffa,src/v-st-ext.adoc,1669,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Constant-Stride Instructions","When `rs2`=`x0`, then an implementation is allowed, but not required, to perform fewer memory operations than the number of active elements, and may perform different numbers of memory operations across different dynamic executions of the same static instruction.",non_CSR_parameter,enum,high,False, +chunk_480de010,src/v-st-ext.adoc,1679,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Constant-Stride Instructions","When `rs2!=x0` and the value of `x[rs2]=0`, the implementation must perform one memory access for each active element (but these accesses will not be ordered).",non_CSR_parameter,enum,very_high,False, +chunk_92dc0b09,src/v-st-ext.adoc,1690,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Constant-Stride Instructions","When repeating ordered vector accesses to the same memory address are required, then an ordered indexed operation can be used.",unknown,unknown,high,False, +chunk_b3afcbd5,src/v-st-ext.adoc,1698,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Indexed Instructions","Vector indexed-unordered load instructions vd destination, rs1 base address, vs2 byte offsets vluxei8.v vd, (rs1), vs2, vm unordered 8-bit indexed load of SEW data vluxei16.v vd, (rs1), vs2, vm unordered 16-bit indexed load of SEW data vluxei32.v vd, (rs1), vs2, vm unordered 32-bit indexed load of SEW data vluxei64.v vd, (rs1), vs2, vm unordered 64-bit indexed load of SEW data",CSR_controlled,range,high,False, +chunk_434969dd,src/v-st-ext.adoc,1705,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Indexed Instructions","Vector indexed-ordered load instructions vd destination, rs1 base address, vs2 byte offsets vloxei8.v vd, (rs1), vs2, vm ordered 8-bit indexed load of SEW data vloxei16.v vd, (rs1), vs2, vm ordered 16-bit indexed load of SEW data vloxei32.v vd, (rs1), vs2, vm ordered 32-bit indexed load of SEW data vloxei64.v vd, (rs1), vs2, vm ordered 64-bit indexed load of SEW data",CSR_controlled,range,high,False, +chunk_5823302e,src/v-st-ext.adoc,1712,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Indexed Instructions","Vector indexed-unordered store instructions vs3 store data, rs1 base address, vs2 byte offsets vsuxei8.v vs3, (rs1), vs2, vm unordered 8-bit indexed store of SEW data vsuxei16.v vs3, (rs1), vs2, vm unordered 16-bit indexed store of SEW data vsuxei32.v vs3, (rs1), vs2, vm unordered 32-bit indexed store of SEW data vsuxei64.v vs3, (rs1), vs2, vm unordered 64-bit indexed store of SEW data",non_CSR_parameter,range,medium,False, +chunk_48b72283,src/v-st-ext.adoc,1719,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Indexed Instructions","Vector indexed-ordered store instructions vs3 store data, rs1 base address, vs2 byte offsets vsoxei8.v vs3, (rs1), vs2, vm ordered 8-bit indexed store of SEW data vsoxei16.v vs3, (rs1), vs2, vm ordered 16-bit indexed store of SEW data vsoxei32.v vs3, (rs1), vs2, vm ordered 32-bit indexed store of SEW data vsoxei64.v vs3, (rs1), vs2, vm ordered 64-bit indexed store of SEW data ----",non_CSR_parameter,range,medium,False, +chunk_a2007328,src/v-st-ext.adoc,1740,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Unit-stride Fault-Only-First Loads","The unit-stride fault-only-first load instructions are used to vectorize loops with data-dependent exit conditions (""while"" loops).",unknown,unknown,high,False, +chunk_1429c5af,src/v-st-ext.adoc,1740,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Unit-stride Fault-Only-First Loads",These instructions execute as a regular load except that they will only take a trap caused by a synchronous exception on element 0.,unknown,unknown,high,False, +chunk_ec1a1765,src/v-st-ext.adoc,1740,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Unit-stride Fault-Only-First Loads","If element 0 raises an exception, `vl` is not modified, and the trap is taken.",CSR_controlled,enum,high,False, +chunk_6ce0ce7d,src/v-st-ext.adoc,1740,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Unit-stride Fault-Only-First Loads","If an element > 0 raises an exception, the corresponding trap is not taken, and the vector length `vl` is reduced to the index of the element that would have raised an exception.",CSR_controlled,enum,high,False, +chunk_726d5217,src/v-st-ext.adoc,1745,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Unit-stride Fault-Only-First Loads",Load instructions may overwrite active destination vector register group elements past the element index at which the trap is reported.,non_CSR_parameter,enum,high,False, +chunk_12d536d4,src/v-st-ext.adoc,1745,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Unit-stride Fault-Only-First Loads","Similarly, fault-only-first load instructions may update active destination elements past the element that causes trimming of the vector length (but not past the original vector length).",non_CSR_parameter,enum,high,False, +chunk_09971494,src/v-st-ext.adoc,1745,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Unit-stride Fault-Only-First Loads",Non-idempotent memory locations can only be accessed when it is known the corresponding element load operation will not be restarted due to a trap or vector-length trimming.,unknown,unknown,high,False, +chunk_c29d5fa7,src/v-st-ext.adoc,1759,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Unit-stride Fault-Only-First Loads",---- strlen example using unit-stride fault-only-first instruction,unknown,unknown,high,False, +chunk_8bcbd080,src/v-st-ext.adoc,1765,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Unit-stride Fault-Only-First Loads","The unit-stride versions only allow probing a region immediately contiguous to a known region, and so reduce the security impact when used in unprivileged code.",unknown,unknown,high,False, +chunk_664faa8a,src/v-st-ext.adoc,1765,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Unit-stride Fault-Only-First Loads","Constant-stride and scatter/gather fault-only-first instructions are not provided due to lack of encoding space, but they can also represent a larger security hole, allowing even unprivileged software to easily check multiple random pages for accessibility without experiencing a trap.",SW_rule,enum,high,False, +chunk_c479a877,src/v-st-ext.adoc,1765,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Unit-stride Fault-Only-First Loads",This standard does not address possible security mitigations for fault-only-first instructions.,unknown,unknown,high,False, +chunk_b40b80b0,src/v-st-ext.adoc,1778,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Unit-stride Fault-Only-First Loads","Even when an exception is not raised, implementations are permitted to process fewer than `vl` elements and reduce `vl` accordingly, but if `vstart`=0 and `vl`>0, then at least one element must be processed.",CSR_controlled,range,very_high,False, +chunk_42cf6152,src/v-st-ext.adoc,1783,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Unit-stride Fault-Only-First Loads","When the fault-only-first instruction takes a trap due to an interrupt, implementations should not reduce `vl` and should instead set a `vstart` value.",CSR_controlled,enum,high,False, +chunk_666c4ff3,src/v-st-ext.adoc,1788,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Unit-stride Fault-Only-First Loads","When the fault-only-first instruction would trigger a debug data-watchpoint trap on an element after the first, implementations should not reduce `vl` but instead should trigger the debug trap as otherwise the event might be lost.",CSR_controlled,enum,high,False, +chunk_a03e8e70,src/v-st-ext.adoc,1796,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions",The vector load/store segment instructions move multiple contiguous fields in memory to and from consecutively numbered vector registers.,unknown,enum,high,False, +chunk_af1d1b2e,src/v-st-ext.adoc,1805,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions","The three-bit `nf` field in the vector instruction encoding is an unsigned integer that contains one less than the number of fields per segment, NFIELDS.",unknown,range,high,False, +chunk_a66def17,src/v-st-ext.adoc,1826,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions","The EMUL setting must be such that EMUL * NFIELDS {le} 8, otherwise the instruction encoding is reserved.",non_CSR_parameter,enum,very_high,False, +chunk_1c6aa97a,src/v-st-ext.adoc,1836,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions",Each field will be held in successively numbered vector register groups.,unknown,enum,high,False, +chunk_4ce717ba,src/v-st-ext.adoc,1836,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions","When EMUL>1, each field will occupy a vector register group held in multiple successively numbered vector registers, and the vector register group for each field must follow the usual vector register alignment constraints (e.g., when EMUL=2 and NFIELDS=4, each field's vector register group must start at an even vector register, but does not have to start at a multiple of 8 vector register number).",non_CSR_parameter,enum,very_high,False, +chunk_f418ea7f,src/v-st-ext.adoc,1845,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions","If the vector register numbers accessed by the segment load or store would increment past 31, then the instruction encoding is reserved.",unknown,enum,high,False, +chunk_17a94e21,src/v-st-ext.adoc,1853,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions","The `vl` register gives the number of segments to move, which is equal to the number of elements transferred to each vector register group.",CSR_controlled,range,high,False, +chunk_fd2bb749,src/v-st-ext.adoc,1858,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions","For segment loads and stores, the individual memory accesses used to access fields within each segment are unordered with respect to each other even for ordered indexed segment loads and stores.",unknown,enum,high,False, +chunk_5855aeff,src/v-st-ext.adoc,1863,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions",The `vstart` value is in units of whole segments.,CSR_controlled,enum,high,False, +chunk_c9b92996,src/v-st-ext.adoc,1863,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions","If a trap occurs during access to a segment, it is implementation-defined whether a subset of the faulting segment's accesses are performed before the trap is taken.",non_CSR_parameter,unknown,high,False, +chunk_b062fbc5,src/v-st-ext.adoc,1878,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions > Vector Unit-Stride Segment Loads and Stores",The assembler prefixes `vlseg`/`vsseg` are used for unit-stride segment loads and stores respectively.,CSR_controlled,enum,high,False, +chunk_35e54fdb,src/v-st-ext.adoc,1887,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions > Vector Unit-Stride Segment Loads and Stores","Examples vlseg8e8.v vd, (rs1), vm Load eight vector registers with eight byte fields.",CSR_controlled,enum,high,False, +chunk_f4be0851,src/v-st-ext.adoc,1890,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions > Vector Unit-Stride Segment Loads and Stores","vsseg3e32.v vs3, (rs1), vm Store packed vector of 3*4-byte segments from vs3,vs3+1,vs3+2 to memory ----",non_CSR_parameter,range,medium,False, +chunk_b0889704,src/v-st-ext.adoc,1893,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions > Vector Unit-Stride Segment Loads and Stores","For loads, the `vd` register will hold the first field loaded from the segment.",unknown,enum,high,False, +chunk_0a89af58,src/v-st-ext.adoc,1893,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions > Vector Unit-Stride Segment Loads and Stores","For stores, the `vs3` register is read to provide the first field to be stored to each segment.",unknown,enum,high,False, +chunk_f32d7842,src/v-st-ext.adoc,1898,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions > Vector Unit-Stride Segment Loads and Stores","---- Example 1 Memory structure holds packed RGB pixels (24-bit data structure, 8bpp) vsetvli a1, t0, e8, m1, ta, ma vlseg3e8.v v8, (a0), vm v8 holds the red pixels v9 holds the green pixels v10 holds the blue pixels",CSR_controlled,range,high,False, +chunk_1afd0b53,src/v-st-ext.adoc,1907,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions > Vector Unit-Stride Segment Loads and Stores","Example 2 Memory structure holds complex values, 32b for real and 32b for imaginary vsetvli a1, t0, e32, m1, ta, ma vlseg2e32.v v8, (a0), vm v8 holds real v9 holds imaginary ----",CSR_controlled,enum,high,False, +chunk_ed674a64,src/v-st-ext.adoc,1915,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions > Vector Unit-Stride Segment Loads and Stores",There are also fault-only-first versions of the unit-stride instructions.,unknown,unknown,high,False, +chunk_57081eb7,src/v-st-ext.adoc,1922,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions > Vector Unit-Stride Segment Loads and Stores","For fault-only-first segment loads, if an exception is detected partway through accessing the zeroth segment, the trap is taken.",unknown,unknown,high,False, +chunk_2df8a29a,src/v-st-ext.adoc,1922,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions > Vector Unit-Stride Segment Loads and Stores","If an exception is detected partway through accessing a subsequent segment, `vl` is reduced to the index of that segment.",CSR_controlled,enum,high,False, +chunk_b8a1275a,src/v-st-ext.adoc,1931,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions > Vector Unit-Stride Segment Loads and Stores",These instructions may overwrite destination vector register group elements past the point at which a trap is reported or past the point at which vector length is trimmed.,non_CSR_parameter,enum,high,False, +chunk_96b7541f,src/v-st-ext.adoc,1950,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions > Vector Constant-Stride Segment Loads and Stores","Examples vsetvli a1, t0, e8, m1, ta, ma vlsseg3e8.v v4, (x5), x6 Load bytes at addresses x5+i*x6 into v4[i], and bytes at addresses x5+i*x6+1 into v5[i], and bytes at addresses x5+i*x6+2 into v6[i].",CSR_controlled,enum,high,False, +chunk_c220a78e,src/v-st-ext.adoc,1956,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions > Vector Constant-Stride Segment Loads and Stores","Examples vsetvli a1, t0, e32, m1, ta, ma vssseg2e32.v v2, (x5), x6 Store words from v2[i] to address x5+i*x6 and words from v3[i] to address x5+i*x6+4 ----",CSR_controlled,enum,high,False, +chunk_d09e6f06,src/v-st-ext.adoc,1962,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions > Vector Constant-Stride Segment Loads and Stores","Accesses to the fields within each segment can occur in any order, including the case where the byte stride is such that segments overlap in memory.",unknown,enum,high,False, +chunk_8b2ee621,src/v-st-ext.adoc,1969,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions > Vector Indexed Segment Loads and Stores",Vector indexed segment loads and stores move contiguous segments where each segment is located at an address given by adding the scalar base address in the `rs1` field to byte offsets in vector register `vs2`.,unknown,enum,high,False, +chunk_a20753e3,src/v-st-ext.adoc,1969,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions > Vector Indexed Segment Loads and Stores","However, even for the ordered form, accesses to the fields within an individual segment are not ordered with respect to each other.",unknown,enum,high,False, +chunk_e47e99bf,src/v-st-ext.adoc,1971,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions > Vector Indexed Segment Loads and Stores","The data vector register group has EEW=SEW, EMUL=LMUL, while the index vector register group has EEW encoded in the instruction with EMUL=(EEW/SEW)*LMUL.",unknown,enum,high,False, +chunk_f2d896a8,src/v-st-ext.adoc,1971,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions > Vector Indexed Segment Loads and Stores",The EMUL * NFIELDS {le} 8 constraint applies to the data vector register group.,unknown,enum,high,False, +chunk_911fa1e4,src/v-st-ext.adoc,1985,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions > Vector Indexed Segment Loads and Stores","Examples vsetvli a1, t0, e8, m1, ta, ma vluxseg3ei8.v v4, (x5), v3 Load bytes at addresses x5+v3[i] into v4[i], and bytes at addresses x5+v3[i]+1 into v5[i], and bytes at addresses x5+v3[i]+2 into v6[i].",CSR_controlled,enum,high,False, +chunk_c069fe59,src/v-st-ext.adoc,1991,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions > Vector Indexed Segment Loads and Stores","Examples vsetvli a1, t0, e32, m1, ta, ma vsuxseg2ei32.v v2, (x5), v5 Store words from v2[i] to address x5+v5[i] and words from v3[i] to address x5+v5[i]+4 ----",CSR_controlled,enum,high,False, +chunk_b2152f5d,src/v-st-ext.adoc,2007,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions",Format for Vector Load Whole Register Instructions under LOAD-FP major opcode,unknown,unknown,high,False, +chunk_6c3cf57a,src/v-st-ext.adoc,2029,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions",Format for Vector Store Whole Register Instructions under STORE-FP major opcode,unknown,unknown,high,False, +chunk_56aa9e41,src/v-st-ext.adoc,2051,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions",These instructions load and store whole vector register groups.,unknown,unknown,high,False, +chunk_6e6fc620,src/v-st-ext.adoc,2053,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions","Examples include compiler register spills, vector function calls where values are passed in vector registers, interrupt handlers, and OS context switches.",unknown,unknown,high,False, +chunk_cc5fddea,src/v-st-ext.adoc,2053,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions",Software can determine the number of bytes transferred by reading the `vlenb` register.,CSR_controlled,enum,high,False, +chunk_92a8fcae,src/v-st-ext.adoc,2061,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions",The load instructions have an EEW encoded in the `mew` and `width` fields following the pattern of regular unit-stride loads.,unknown,enum,high,False, +chunk_7275e9f5,src/v-st-ext.adoc,2065,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions","Hence, it would have sufficed to provide only EEW=8 variants.",unknown,unknown,high,False, +chunk_f9ab3ac5,src/v-st-ext.adoc,2065,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions","The full set of EEW variants is provided so that the encoded EEW can be used as a hint to indicate the destination register group will next be accessed with this EEW, which aids implementations that rearrange data internally.",unknown,enum,high,False, +chunk_37ef2fdd,src/v-st-ext.adoc,2073,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions",The vector whole register store instructions are encoded similar to unmasked unit-stride store of elements with EEW=8.,unknown,enum,high,False, +chunk_5fa18b40,src/v-st-ext.adoc,2076,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions",The `nf` field encodes how many vector registers to load and store using the NFIELDS encoding (Figure ).,unknown,enum,high,False, +chunk_9543dc6e,src/v-st-ext.adoc,2076,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions","The encoded number of registers must be a power of 2 and the vector register numbers must be aligned as with a vector register group, otherwise the instruction encoding is reserved. NFIELDS indicates the number of vector registers to transfer, numbered successively after the base.",non_CSR_parameter,enum,very_high,False, +chunk_e143bcf6,src/v-st-ext.adoc,2076,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions","Only NFIELDS values of 1, 2, 4, 8 are supported, with other values reserved.",unknown,enum,high,False, +chunk_2dfc05c6,src/v-st-ext.adoc,2076,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions","When multiple registers are transferred, the lowest-numbered vector register is held in the lowest-numbered memory addresses and successive vector register numbers are placed contiguously in memory.",unknown,unknown,high,False, +chunk_b62cb4c2,src/v-st-ext.adoc,2087,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions","The instructions operate with an effective vector length, `evl`=NFIELDS*VLEN/EEW, regardless of current settings in `vtype` and `vl`.",CSR_controlled,enum,high,False, +chunk_1cd9fe2d,src/v-st-ext.adoc,2087,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions",The usual property that no elements are written if `vstart` {ge} `vl` does not apply to these instructions.,CSR_controlled,enum,high,False, +chunk_b71f8243,src/v-st-ext.adoc,2087,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions","Similarly, the property that the instructions are reserved if `vstart` exceeds the largest element index for the current `vtype` setting does not apply.",CSR_controlled,enum,high,False, +chunk_04b6214f,src/v-st-ext.adoc,2087,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions","Instead, the instructions are reserved if `vstart` {ge} `evl`.",CSR_controlled,enum,high,False, +chunk_230a10ee,src/v-st-ext.adoc,2097,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions","The instructions operate similarly to unmasked unit-stride load and store instructions, with the base address passed in the scalar `x` register specified by `rs1`.",unknown,unknown,high,False, +chunk_09018e24,src/v-st-ext.adoc,2101,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions",Implementations are allowed to raise a misaligned address exception on whole register loads and stores if the base address is not naturally aligned to the larger of the size of the encoded EEW in bytes (EEW/8) or the implementation's smallest supported SEW size in bytes (SEW~MIN~/8).,non_CSR_parameter,enum,high,False, +chunk_eee684ac,src/v-st-ext.adoc,2108,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions","Some subset implementations might not support smaller SEW widths, so are allowed to report misaligned exceptions for the smallest supported SEW even if larger than encoded EEW.",unknown,enum,high,False, +chunk_e7bd38ad,src/v-st-ext.adoc,2108,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions",Software environments can mandate the minimum alignment requirements to support an ABI.,SW_rule,range,high,False, +chunk_440ed0bc,src/v-st-ext.adoc,2117,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions","---- Format of whole register load and store instructions. vl1r.v v3, (a0) Pseudoinstruction equal to vl1re8.v",CSR_controlled,range,high,False, +chunk_b7106e30,src/v-st-ext.adoc,2121,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions","vl1re8.v v3, (a0) Load v3 with VLEN/8 bytes held at address in a0 vl1re16.v v3, (a0) Load v3 with VLEN/16 halfwords held at address in a0 vl1re32.v v3, (a0) Load v3 with VLEN/32 words held at address in a0 vl1re64.v v3, (a0) Load v3 with VLEN/64 doublewords held at address in a0",CSR_controlled,range,high,False, +chunk_d81d3b25,src/v-st-ext.adoc,2126,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions","vl2r.v v2, (a0) Pseudoinstruction equal to vl2re8.v",CSR_controlled,range,high,False, +chunk_3cc8ce31,src/v-st-ext.adoc,2128,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions","vl2re8.v v2, (a0) Load v2-v3 with 2*VLEN/8 bytes from address in a0 vl2re16.v v2, (a0) Load v2-v3 with 2*VLEN/16 halfwords held at address in a0 vl2re32.v v2, (a0) Load v2-v3 with 2*VLEN/32 words held at address in a0 vl2re64.v v2, (a0) Load v2-v3 with 2*VLEN/64 doublewords held at address in a0",CSR_controlled,range,high,False, +chunk_29f2b99d,src/v-st-ext.adoc,2133,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions","vl4r.v v4, (a0) Pseudoinstruction equal to vl4re8.v",CSR_controlled,range,high,False, +chunk_c7103d4e,src/v-st-ext.adoc,2135,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions","vl4re8.v v4, (a0) Load v4-v7 with 4*VLEN/8 bytes from address in a0 vl4re16.v v4, (a0) vl4re32.v v4, (a0) vl4re64.v v4, (a0)",CSR_controlled,range,high,False, +chunk_03a079dd,src/v-st-ext.adoc,2140,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions","vl8r.v v8, (a0) Pseudoinstruction equal to vl8re8.v",CSR_controlled,range,high,False, +chunk_50580c08,src/v-st-ext.adoc,2142,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions","vl8re8.v v8, (a0) Load v8-v15 with 8*VLEN/8 bytes from address in a0 vl8re16.v v8, (a0) vl8re32.v v8, (a0) vl8re64.v v8, (a0)",CSR_controlled,range,high,False, +chunk_f22ab8a6,src/v-st-ext.adoc,2147,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions","vs1r.v v3, (a1) Store v3 to address in a1 vs2r.v v2, (a1) Store v2-v3 to address in a1 vs4r.v v4, (a1) Store v4-v7 to address in a1 vs8r.v v8, (a1) Store v8-v15 to address in a1 ----",unknown,unknown,high,False, +chunk_bcca5b18,src/v-st-ext.adoc,2153,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions",The primary purpose would be to inform the microarchitecture that the data will be used as a mask.,unknown,unknown,high,False, +chunk_b8d988a3,src/v-st-ext.adoc,2153,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions","The same effect can be achieved with the following code sequence, whose cost is at most four instructions.",unknown,range,high,False, +chunk_74df8f5e,src/v-st-ext.adoc,2153,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions","Of these, the first could likely be removed as `vl` is often already in a scalar register, and the last might already be present if the following vector instruction needs a new SEW/LMUL.",CSR_controlled,enum,high,False, +chunk_0e13627a,src/v-st-ext.adoc,2173,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Memory Alignment Constraints","If an element accessed by a vector memory instruction is not naturally aligned to the size of the element, either the element is transferred successfully or an address-misaligned exception is raised on that element.",non_CSR_parameter,enum,high,False, +chunk_275416b5,src/v-st-ext.adoc,2198,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Memory Consistency Model","If the Ztso extension is implemented, vector memory instructions additionally follow RVTSO at the instruction level.",unknown,unknown,high,False, +chunk_f9a58a58,src/v-st-ext.adoc,2215,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Memory Consistency Model","Instructions affected by the vector length register `vl` have a control dependency on `vl`, rather than a data dependency.",CSR_controlled,enum,high,False, +chunk_15feb995,src/v-st-ext.adoc,2231,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats",The three-bit `funct3` field is used to define sub-categories of vector instructions.,unknown,enum,high,False, +chunk_a8f0b3e0,src/v-st-ext.adoc,2240,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Vector Arithmetic Instruction encoding",The `funct3` field encodes the operand type and source locations.,unknown,enum,high,False, +chunk_72d7eddd,src/v-st-ext.adoc,2263,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Vector Arithmetic Instruction encoding",All vector floating-point operations use the dynamic rounding mode in the `frm` register.,CSR_controlled,enum,high,False, +chunk_6ea15001,src/v-st-ext.adoc,2263,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Vector Arithmetic Instruction encoding","Use of the `frm` field when it contains an invalid rounding mode by any vector floating-point instruction--even those that do not depend on the rounding mode, or when `vl`=0, or when `vstart` {ge} `vl`--is reserved.",CSR_controlled,enum,high,False, +chunk_2da14e29,src/v-st-ext.adoc,2269,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Vector Arithmetic Instruction encoding",Implementations can make all vector FP instructions report exceptions when the rounding mode is invalid to simplify control logic.,unknown,unknown,high,False, +chunk_e9115c3b,src/v-st-ext.adoc,2282,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Vector Arithmetic Instruction encoding","For integer operations, the scalar can be a 5-bit immediate, `imm[4:0]`, encoded in the `rs1` field.",non_CSR_parameter,range,high,False, +chunk_c80e0890,src/v-st-ext.adoc,2282,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Vector Arithmetic Instruction encoding","The value is sign-extended to SEW bits, unless otherwise specified.",unknown,enum,high,False, +chunk_f048017a,src/v-st-ext.adoc,2285,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Vector Arithmetic Instruction encoding","If XLEN>SEW, the least-significant SEW bits of the `x` register are used, unless otherwise specified.",unknown,unknown,high,False, +chunk_e1765f80,src/v-st-ext.adoc,2285,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Vector Arithmetic Instruction encoding","If XLEN ""V"" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Vector Arithmetic Instruction encoding","If FLEN > SEW, the value in the `f` registers is checked for a valid NaN-boxed value, in which case the least-significant SEW bits of the `f` register are used, else the canonical NaN value is used.",unknown,unknown,high,False, +chunk_47551ea0,src/v-st-ext.adoc,2289,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Vector Arithmetic Instruction encoding",Vector instructions where any floating-point vector operand's EEW is not a supported floating-point type width (which includes when FLEN < SEW) are reserved.,unknown,unknown,high,False, +chunk_05ffec25,src/v-st-ext.adoc,2300,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Vector Arithmetic Instruction encoding","When adding a vector extension to the Zfinx/Zdinx/Zhinx extensions, floating-point scalar arguments are taken from the `x` registers.",unknown,unknown,high,False, +chunk_827ca6eb,src/v-st-ext.adoc,2306,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Vector Arithmetic Instruction encoding",Vector arithmetic instructions are masked under control of the `vm` field.,unknown,enum,high,False, +chunk_269534aa,src/v-st-ext.adoc,2321,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Vector Arithmetic Instruction encoding","This arrangement retains the existing encoding conventions that instructions that read only one scalar register, read it from `rs1`, and that 5-bit immediates are sourced from the `rs1` field.",non_CSR_parameter,range,high,False, +chunk_022ea3a4,src/v-st-ext.adoc,2384,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Widening Vector Arithmetic Instructions",Widening instruction encodings must follow the constraints in .,non_CSR_parameter,enum,very_high,False, +chunk_ae8bb168,src/v-st-ext.adoc,2397,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Narrowing Vector Arithmetic Instructions",The choice here is motivated by the belief the chosen approach will require fewer `vtype` changes.,CSR_controlled,enum,high,False, +chunk_1ccea559,src/v-st-ext.adoc,2419,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Narrowing Vector Arithmetic Instructions",Narrowing instruction encodings must follow the constraints in .,non_CSR_parameter,enum,very_high,False, +chunk_13267868,src/v-st-ext.adoc,2425,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions","Unless otherwise stated, integer operations wrap around on overflow.",unknown,unknown,high,False, +chunk_627da66f,src/v-st-ext.adoc,2454,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Widening Integer Add/Subtract","The widening add/subtract instructions are provided in both signed and unsigned variants, depending on whether the narrower source operands are first sign- or zero-extended before forming the double-width sum.",unknown,enum,high,False, +chunk_dfd0c833,src/v-st-ext.adoc,2506,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Extension","If the source EEW is not a supported width, or source EMUL would be below the minimum legal LMUL, the instruction encoding is reserved.",unknown,range,high,False, +chunk_93216de6,src/v-st-ext.adoc,2509,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Extension","To avoid having to provide the cross-product of the number of vector load instructions by the number of data types (byte, word, halfword, and also signed/unsigned variants), we instead add explicit extension instructions that can be used if an appropriate widening arithmetic instruction is not available.",unknown,unknown,high,False, +chunk_ae262851,src/v-st-ext.adoc,2521,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions","For each operation (add or subtract), two instructions are provided: one to provide the result (SEW width), and the second to generate the carry output (single bit encoded as a mask boolean).",unknown,enum,high,False, +chunk_827a9f43,src/v-st-ext.adoc,2527,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions","Due to encoding constraints, the carry input must come from the implicit `v0` register, but carry outputs can be written to any vector register that respects the source/destination overlap restrictions.",non_CSR_parameter,enum,very_high,False, +chunk_ece761f2,src/v-st-ext.adoc,2533,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions","These instructions are encoded as masked instructions (`vm=0`), but they operate on and write back all body elements.",unknown,enum,high,False, +chunk_1b1e3f78,src/v-st-ext.adoc,2539,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions","`vmadc` and `vmsbc` add or subtract the source operands, optionally add the carry-in or subtract the borrow-in if masked (`vm=0`), and write the resulting carry-out or borrow-out back to mask register `vd`.",unknown,unknown,high,False, +chunk_895a0ebc,src/v-st-ext.adoc,2539,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions","If unmasked (`vm=1`), there is no carry-in or borrow-in.",unknown,unknown,high,False, +chunk_25b97861,src/v-st-ext.adoc,2539,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions","These instructions operate on and write back all body elements, even if masked.",unknown,unknown,high,False, +chunk_fed93517,src/v-st-ext.adoc,2622,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions","For `vadc` and `vsbc`, the instruction encoding is reserved if the destination vector register is `v0`.",unknown,enum,high,False, +chunk_4a30edc6,src/v-st-ext.adoc,2652,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Single-Width Shift Instructions","The data to be shifted is in the vector register group specified by `vs2` and the shift amount value can come from a vector register group `vs1`, a scalar integer register `rs1`, or a zero-extended 5-bit immediate.",non_CSR_parameter,range,high,False, +chunk_a58b5b81,src/v-st-ext.adoc,2678,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Narrowing Integer Right Shift Instructions",The narrowing right shifts extract a smaller field from a wider operand and have both zero-extending (`srl`) and sign-extending (`sra`) forms.,unknown,enum,high,False, +chunk_f4b1ca64,src/v-st-ext.adoc,2678,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Narrowing Integer Right Shift Instructions","The shift amount can come from a vector register group, or a scalar `x` register, or a zero-extended 5-bit immediate.",non_CSR_parameter,range,high,False, +chunk_17dbd262,src/v-st-ext.adoc,2707,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Compare Instructions",The destination mask vector register may be the same as the source vector mask register (`v0`).,non_CSR_parameter,enum,medium,False, +chunk_49c7bae8,src/v-st-ext.adoc,2714,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Compare Instructions","---- Set if equal vmseq.vv vd, vs2, vs1, vm Vector-vector vmseq.vx vd, vs2, rs1, vm vector-scalar vmseq.vi vd, vs2, imm, vm vector-immediate",unknown,unknown,high,False, +chunk_a7f730f8,src/v-st-ext.adoc,2720,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Compare Instructions","Set if not equal vmsne.vv vd, vs2, vs1, vm Vector-vector vmsne.vx vd, vs2, rs1, vm vector-scalar vmsne.vi vd, vs2, imm, vm vector-immediate",unknown,range,high,False, +chunk_aa36e0e1,src/v-st-ext.adoc,2725,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Compare Instructions","Set if less than, unsigned vmsltu.vv vd, vs2, vs1, vm Vector-vector vmsltu.vx vd, vs2, rs1, vm Vector-scalar",unknown,range,high,False, +chunk_7dbbb399,src/v-st-ext.adoc,2729,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Compare Instructions","Set if less than, signed vmslt.vv vd, vs2, vs1, vm Vector-vector vmslt.vx vd, vs2, rs1, vm vector-scalar",unknown,range,high,False, +chunk_6d44b7bc,src/v-st-ext.adoc,2733,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Compare Instructions","Set if less than or equal, unsigned vmsleu.vv vd, vs2, vs1, vm Vector-vector vmsleu.vx vd, vs2, rs1, vm vector-scalar vmsleu.vi vd, vs2, imm, vm Vector-immediate",unknown,range,high,False, +chunk_fac29bdd,src/v-st-ext.adoc,2738,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Compare Instructions","Set if less than or equal, signed vmsle.vv vd, vs2, vs1, vm Vector-vector vmsle.vx vd, vs2, rs1, vm vector-scalar vmsle.vi vd, vs2, imm, vm vector-immediate",unknown,range,high,False, +chunk_b5e1e886,src/v-st-ext.adoc,2743,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Compare Instructions","Set if greater than, unsigned vmsgtu.vx vd, vs2, rs1, vm Vector-scalar vmsgtu.vi vd, vs2, imm, vm Vector-immediate",unknown,range,high,False, +chunk_c12a8c02,src/v-st-ext.adoc,2747,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Compare Instructions","Set if greater than, signed vmsgt.vx vd, vs2, rs1, vm Vector-scalar vmsgt.vi vd, vs2, imm, vm Vector-immediate",unknown,range,high,False, +chunk_79dce25b,src/v-st-ext.adoc,2751,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Compare Instructions","Following two instructions are not provided directly Set if greater than or equal, unsigned vmsgeu.vx vd, vs2, rs1, vm Vector-scalar Set if greater than or equal, signed vmsge.vx vd, vs2, rs1, vm Vector-scalar ----",unknown,range,high,False, +chunk_f4690bd1,src/v-st-ext.adoc,2823,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Compare Instructions","The `vmsge{u}.vx` operation can be synthesized by reducing the value of `x` by 1 and using the `vmsgt{u}.vx` instruction, when it is known that this will not underflow the representation in `x`.",unknown,enum,high,False, +chunk_be344f25,src/v-st-ext.adoc,2860,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Compare Instructions",The vt argument to the pseudoinstruction must name a temporary vector register that is not same as vd and which will be clobbered by the pseudoinstruction ----,non_CSR_parameter,enum,very_high,False, +chunk_191a80cd,src/v-st-ext.adoc,2866,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Compare Instructions","---- (a < b) && (b < c) in two instructions when mask-undisturbed vmslt.vv v0, va, vb All body elements written vmslt.vv v0, vb, vc, v0.t Only update at set mask ----",unknown,unknown,high,False, +chunk_a4b05703,src/v-st-ext.adoc,2907,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Single-Width Integer Multiply Instructions","---- Signed multiply, returning low bits of product vmul.vv vd, vs2, vs1, vm Vector-vector vmul.vx vd, vs2, rs1, vm vector-scalar",unknown,unknown,high,False, +chunk_1a1364b0,src/v-st-ext.adoc,2912,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Single-Width Integer Multiply Instructions","Signed multiply, returning high bits of product vmulh.vv vd, vs2, vs1, vm Vector-vector vmulh.vx vd, vs2, rs1, vm vector-scalar",unknown,unknown,high,False, +chunk_2c5d6465,src/v-st-ext.adoc,2916,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Single-Width Integer Multiply Instructions","Unsigned multiply, returning high bits of product vmulhu.vv vd, vs2, vs1, vm Vector-vector vmulhu.vx vd, vs2, rs1, vm vector-scalar",unknown,unknown,high,False, +chunk_96e754ef,src/v-st-ext.adoc,2920,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Single-Width Integer Multiply Instructions","Signed(vs2)-Unsigned multiply, returning high bits of product vmulhsu.vv vd, vs2, vs1, vm Vector-vector vmulhsu.vx vd, vs2, rs1, vm vector-scalar ----",unknown,unknown,high,False, +chunk_7e7bed85,src/v-st-ext.adoc,3051,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Merge Instructions",The `vmerge` instructions are encoded as masked instructions (`vm=0`).,unknown,enum,high,False, +chunk_c65f6dea,src/v-st-ext.adoc,3051,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Merge Instructions",The second operand is a vector register group specified by `vs1` or a scalar `x` register specified by `rs1` or a 5-bit sign-extended immediate.,non_CSR_parameter,range,high,False, +chunk_46b5e528,src/v-st-ext.adoc,3069,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Move Instructions",These instructions are encoded as unmasked instructions (`vm=1`).,unknown,enum,high,False, +chunk_fe2a2de3,src/v-st-ext.adoc,3069,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Move Instructions","The first operand specifier (`vs2`) must contain `v0`, and any other vector register number in `vs2` is reserved.",non_CSR_parameter,enum,very_high,False, +chunk_b46cf7d2,src/v-st-ext.adoc,3094,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Move Instructions",Implementations that do not internally reorganize data can dynamically elide this instruction (aside from resetting `vstart` to 0).,CSR_controlled,enum,high,False, +chunk_2c810be6,src/v-st-ext.adoc,3151,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions > Vector Single-Width Averaging Add and Subtract",The averaging add and subtract instructions right shift the result by one bit and round off the result according to the setting in `vxrm`.,CSR_controlled,enum,high,False, +chunk_eadefd5b,src/v-st-ext.adoc,3185,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions > Vector Single-Width Fractional Multiply with Rounding and Saturation","The signed fractional multiply instruction produces a 2*SEW product of the two SEW inputs, then shifts the result right by SEW-1 bits, rounding these bits according to `vxrm`, then saturates the result to fit into SEW bits.",CSR_controlled,range,high,False, +chunk_4527fab3,src/v-st-ext.adoc,3185,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions > Vector Single-Width Fractional Multiply with Rounding and Saturation","If the result causes saturation, the `vxsat` bit is set.",CSR_controlled,enum,high,False, +chunk_4b449aad,src/v-st-ext.adoc,3191,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions > Vector Single-Width Fractional Multiply with Rounding and Saturation","---- Signed saturating and rounding fractional multiply See vxrm description for rounding calculation vsmul.vv vd, vs2, vs1, vm vd[i] = clip(roundoffsigned(vs2[i]*vs1[i], SEW-1)) vsmul.vx vd, vs2, rs1, vm vd[i] = clip(roundoffsigned(vs2[i]*x[rs1], SEW-1)) ----",CSR_controlled,enum,high,False, +chunk_1e388db4,src/v-st-ext.adoc,3198,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions > Vector Single-Width Fractional Multiply with Rounding and Saturation","When multiplying two N-bit signed numbers, the largest magnitude is obtained for -2^N-1^ * -2^N-1^ producing a result +2^2N-2^, which has a single (zero) sign bit when held in 2N bits.",unknown,unknown,high,False, +chunk_15296079,src/v-st-ext.adoc,3198,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions > Vector Single-Width Fractional Multiply with Rounding and Saturation",All other products have two sign bits in 2N bits.,unknown,unknown,high,False, +chunk_e03e1964,src/v-st-ext.adoc,3214,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions > Vector Single-Width Scaling Shift Instructions","These instructions shift the input value right, and round off the shifted out bits according to `vxrm`.",CSR_controlled,enum,high,False, +chunk_94960edf,src/v-st-ext.adoc,3214,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions > Vector Single-Width Scaling Shift Instructions","The data to be shifted is in the vector register group specified by `vs2` and the shift amount value can come from a vector register group `vs1`, a scalar integer register `rs1`, or a zero-extended 5-bit immediate.",non_CSR_parameter,range,high,False, +chunk_aac2a72a,src/v-st-ext.adoc,3236,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions > Vector Narrowing Fixed-Point Clip Instructions","The scaling shift amount value can come from a vector register group `vs1`, a scalar integer register `rs1`, or a zero-extended 5-bit immediate.",non_CSR_parameter,range,high,False, +chunk_b3467f3c,src/v-st-ext.adoc,3258,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions > Vector Narrowing Fixed-Point Clip Instructions","For `vnclipu`/`vnclip`, the rounding mode is specified in the `vxrm` CSR.",CSR_controlled,enum,high,False, +chunk_e0a0cf16,src/v-st-ext.adoc,3258,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions > Vector Narrowing Fixed-Point Clip Instructions",Rounding occurs around the least-significant bit of the destination and before saturation.,unknown,unknown,high,False, +chunk_05595617,src/v-st-ext.adoc,3262,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions > Vector Narrowing Fixed-Point Clip Instructions","For `vnclipu`, the shifted rounded source value is treated as an unsigned integer and saturates if the result would overflow the destination viewed as an unsigned integer.",unknown,unknown,high,False, +chunk_df860a3b,src/v-st-ext.adoc,3274,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions > Vector Narrowing Fixed-Point Clip Instructions","For `vnclip`, the shifted rounded source value is treated as a signed integer and saturates if the result would overflow the destination viewed as a signed integer.",unknown,unknown,high,False, +chunk_e3f52391,src/v-st-ext.adoc,3278,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions > Vector Narrowing Fixed-Point Clip Instructions","If any destination element is saturated, the `vxsat` bit is set in the `vxsat` register.",CSR_controlled,enum,high,False, +chunk_769d3963,src/v-st-ext.adoc,3284,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions","If the EEW of a vector floating-point operand does not correspond to a supported IEEE floating-point type, the instruction encoding is reserved.",unknown,enum,high,False, +chunk_24ac14f4,src/v-st-ext.adoc,3289,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions",The current set of extensions include support for 32-bit and 64-bit floating-point values.,non_CSR_parameter,range,medium,False, +chunk_1f6d1e65,src/v-st-ext.adoc,3289,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions","When 16-bit and 128-bit element widths are added, they will be also be treated as IEEE 754-2008-compatible values.",non_CSR_parameter,range,high,False, +chunk_eb55f3bc,src/v-st-ext.adoc,3289,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions",Other floating-point formats may be supported in future extensions.,non_CSR_parameter,enum,medium,False, +chunk_61306eba,src/v-st-ext.adoc,3304,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions",If the floating-point unit status field `mstatus.FS` is `Off` then any attempt to execute a vector floating-point instruction will raise an illegal-instruction exception.,CSR_controlled,enum,high,False, +chunk_6d3a5562,src/v-st-ext.adoc,3304,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions","Any vector floating-point instruction that modifies any floating-point extension state (i.e., floating-point CSRs or `f` registers) must set `mstatus.FS` to `Dirty`.",CSR_controlled,enum,very_high,False, +chunk_905348a0,src/v-st-ext.adoc,3310,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions","If the hypervisor extension is implemented and V=1, the `vsstatus.FS` field is additionally in effect for vector floating-point instructions.",CSR_controlled,enum,high,False, +chunk_f4a00fe3,src/v-st-ext.adoc,3310,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions",If `vsstatus.FS` or `mstatus.FS` is `Off` then any attempt to execute a vector floating-point instruction will raise an illegal-instruction exception.,CSR_controlled,enum,high,False, +chunk_e6fa493c,src/v-st-ext.adoc,3310,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions","Any vector floating-point instruction that modifies any floating-point extension state (i.e., floating-point CSRs or `f` registers) must set both `mstatus.FS` and `vsstatus.FS` to `Dirty`.",CSR_controlled,enum,very_high,False, +chunk_d924facc,src/v-st-ext.adoc,3326,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Exception Flags",A vector floating-point exception at any active floating-point element sets the standard FP exception flags in the `fflags` register.,CSR_controlled,enum,high,False, +chunk_643ef9ef,src/v-st-ext.adoc,3326,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Exception Flags",Inactive elements do not set FP exception flags.,unknown,unknown,high,False, +chunk_9d7fc124,src/v-st-ext.adoc,3466,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Square-Root Estimate Instruction","---- Floating-point reciprocal square-root estimate to 7 bits. vfrsqrt7.v vd, vs2, vm ----",non_CSR_parameter,range,medium,False, +chunk_79d007c2,src/v-st-ext.adoc,3471,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Square-Root Estimate Instruction",This is a unary vector-vector instruction that returns an estimate of 1/sqrt(x) accurate to 7 bits.,non_CSR_parameter,range,medium,False, +chunk_0aac6040,src/v-st-ext.adoc,3482,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Square-Root Estimate Instruction","[cols=""1,1,1""] | | Input | Output | Exceptions raised",non_CSR_parameter,unknown,high,False, +chunk_8d4dc33a,src/v-st-ext.adoc,3500,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Square-Root Estimate Instruction","For the non-exceptional cases, the low bit of the exponent and the six high bits of significand (after the leading one) are concatenated and used to address the following table.",unknown,unknown,high,False, +chunk_553ab545,src/v-st-ext.adoc,3500,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Square-Root Estimate Instruction",The output of the table becomes the seven high bits of the result significand (after the leading one); the remainder of the result significand is zero.,unknown,unknown,high,False, +chunk_afbaa4d7,src/v-st-ext.adoc,3510,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Square-Root Estimate Instruction","Let the normalized input exponent be equal to the input exponent if the input is normal, or 0 minus the number of leading zeros in the significand otherwise.",unknown,range,high,False, +chunk_83cba425,src/v-st-ext.adoc,3510,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Square-Root Estimate Instruction","If the input is subnormal, the normalized input significand is given by shifting the input significand left by 1 minus the normalized input exponent, discarding the leading 1 bit.",non_CSR_parameter,range,high,False, +chunk_108509ab,src/v-st-ext.adoc,3520,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Square-Root Estimate Instruction",The following table gives the seven MSBs of the output significand as a function of the LSB of the normalized input exponent and the six MSBs of the normalized input significand; the other bits of the output significand are zero.,unknown,unknown,high,False, +chunk_24af5065,src/v-st-ext.adoc,3535,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Estimate Instruction","---- Floating-point reciprocal estimate to 7 bits. vfrec7.v vd, vs2, vm ----",non_CSR_parameter,range,medium,False, +chunk_a4e86fdb,src/v-st-ext.adoc,3545,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Estimate Instruction",This is a unary vector-vector instruction that returns an estimate of 1/x accurate to 7 bits.,non_CSR_parameter,range,medium,False, +chunk_de9bbbb6,src/v-st-ext.adoc,3551,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Estimate Instruction","[cols=""1,1,1,1""] | | Input (x) | Rounding Mode | Output (y {approx} 1/x) | Exceptions raised",non_CSR_parameter,unknown,high,False, +chunk_a0541d24,src/v-st-ext.adoc,3578,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Estimate Instruction",Normal inputs with magnitude at least 2^B-1^ produce subnormal outputs; other normal inputs produce normal outputs.,non_CSR_parameter,range,medium,False, +chunk_d159b4fa,src/v-st-ext.adoc,3586,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Estimate Instruction","For the non-exceptional cases, the seven high bits of significand (after the leading one) are used to address the following table.",unknown,unknown,high,False, +chunk_3c51b7e9,src/v-st-ext.adoc,3586,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Estimate Instruction",The output of the table becomes the seven high bits of the result significand (after the leading one); the remainder of the result significand is zero.,unknown,unknown,high,False, +chunk_a96ef144,src/v-st-ext.adoc,3595,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Estimate Instruction","Let the normalized input exponent be equal to the input exponent if the input is normal, or 0 minus the number of leading zeros in the significand otherwise.",unknown,range,high,False, +chunk_02fa3d4e,src/v-st-ext.adoc,3595,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Estimate Instruction","If the normalized output exponent is outside the range [-1, 2*B], the result corresponds to one of the exceptional cases in the table above.",unknown,enum,high,False, +chunk_e40d65c6,src/v-st-ext.adoc,3603,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Estimate Instruction","If the input is subnormal, the normalized input significand is given by shifting the input significand left by 1 minus the normalized input exponent, discarding the leading 1 bit.",non_CSR_parameter,range,high,False, +chunk_a55098cb,src/v-st-ext.adoc,3603,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Estimate Instruction",The following table gives the seven MSBs of the normalized output significand as a function of the seven MSBs of the normalized input significand; the other bits of the normalized output significand are zero.,unknown,unknown,high,False, +chunk_4ec5b218,src/v-st-ext.adoc,3647,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Sign-Injection Instructions",The result takes all bits except the sign bit from the vector `vs2` operands.,unknown,unknown,high,False, +chunk_b174182e,src/v-st-ext.adoc,3672,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Compare Instructions",The destination mask vector register may be the same as the source vector mask register (`v0`).,non_CSR_parameter,enum,medium,False, +chunk_04926b9a,src/v-st-ext.adoc,3733,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Compare Instructions","When the comparand is a non-NaN constant, the middle two instructions can be omitted.",unknown,unknown,high,False, +chunk_1e049c6e,src/v-st-ext.adoc,3761,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Classify Instruction",The 10-bit mask produced by this instruction is placed in the least-significant bits of the result elements.,non_CSR_parameter,range,high,False, +chunk_a71846e9,src/v-st-ext.adoc,3761,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Classify Instruction",The upper (SEW-10) bits of the result are filled with zeros.,unknown,unknown,high,False, +chunk_4b20124c,src/v-st-ext.adoc,3769,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Merge Instruction","A vector-scalar floating-point merge instruction is provided, which operates on all body elements from `vstart` up to the current vector length in `vl` regardless of mask value.",CSR_controlled,enum,high,False, +chunk_9bf11c90,src/v-st-ext.adoc,3773,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Merge Instruction",The `vfmerge.vfm` instruction is encoded as a masked instruction (`vm=0`).,unknown,enum,high,False, +chunk_5c64c8e1,src/v-st-ext.adoc,3784,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Move Instruction",This instruction is encoded as an unmasked instruction (`vm=1`).,unknown,enum,high,False, +chunk_cd9b11dc,src/v-st-ext.adoc,3784,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Move Instruction","The instruction must have the `vs2` field set to `v0`, with all other values for `vs2` reserved.",non_CSR_parameter,enum,very_high,False, +chunk_53a65f29,src/v-st-ext.adoc,3815,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Single-Width Floating-Point/Integer Type-Convert Instructions",The conversions follow the same rules on exceptional conditions as the scalar conversion instructions.,unknown,unknown,high,False, +chunk_2ba5461c,src/v-st-ext.adoc,3815,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Single-Width Floating-Point/Integer Type-Convert Instructions","The conversions use the dynamic rounding mode in `frm`, except for the `rtz` variants, which round towards zero.",CSR_controlled,enum,high,False, +chunk_70059d11,src/v-st-ext.adoc,3879,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Narrowing Floating-Point/Integer Type-Convert Instructions",Results are equivalently rounded and the same exception flags are raised if all but the last halving step use round-towards-odd (`vfncvt.rod.f.f.w`).,non_CSR_parameter,unknown,high,False, +chunk_7a7e77f3,src/v-st-ext.adoc,3879,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Narrowing Floating-Point/Integer Type-Convert Instructions",Only the final step should use the desired rounding mode.,non_CSR_parameter,enum,medium,False, +chunk_cb9088b2,src/v-st-ext.adoc,3912,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations",The other elements in the destination vector register ( 0 < index < VLEN/SEW) are considered the tail and are managed with the current tail agnostic/undisturbed policy.,CSR_controlled,enum,high,False, +chunk_691bc124,src/v-st-ext.adoc,3919,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations","For the uncommon case that the source and destination scalar operand are in different vector registers, this instruction will not copy the source into the destination when `vl`=0.",CSR_controlled,enum,high,False, +chunk_77bae2f3,src/v-st-ext.adoc,3919,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations","However, it is expected that in most of these cases it will be statically known that `vl` is not zero.",CSR_controlled,enum,high,False, +chunk_29701136,src/v-st-ext.adoc,3932,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations",Traps on vector reduction instructions are always reported with a `vstart` of 0.,CSR_controlled,enum,high,False, +chunk_22050f67,src/v-st-ext.adoc,3932,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations",Vector reduction operations raise an illegal-instruction exception if `vstart` is non-zero.,CSR_controlled,enum,high,False, +chunk_290197fb,src/v-st-ext.adoc,3994,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations > Vector Single-Width Floating-Point Reduction Instructions > Vector Ordered Single-Width Floating-Point Sum Reduction","The `vfredosum` instruction must sum the floating-point values in element order, starting with the scalar in `vs1[0]`--that is, it performs the computation:",non_CSR_parameter,enum,very_high,False, +chunk_07299328,src/v-st-ext.adoc,4008,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations > Vector Single-Width Floating-Point Reduction Instructions > Vector Ordered Single-Width Floating-Point Sum Reduction","When the operation is masked (`vm=0`), the masked-off elements do not affect the result or the exception flags.",unknown,unknown,high,False, +chunk_1cd74e7b,src/v-st-ext.adoc,4011,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations > Vector Single-Width Floating-Point Reduction Instructions > Vector Ordered Single-Width Floating-Point Sum Reduction","If no elements are active, no additions are performed, so the scalar in `vs1[0]` is simply copied to the destination register, without canonicalizing NaN values and without setting any exception flags.",unknown,unknown,high,False, +chunk_741ba3ad,src/v-st-ext.adoc,4011,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations > Vector Single-Width Floating-Point Reduction Instructions > Vector Ordered Single-Width Floating-Point Sum Reduction","This behavior preserves the handling of NaNs, exceptions, and rounding when auto-vectorizing a scalar summation loop.",unknown,unknown,high,False, +chunk_e42f3fa3,src/v-st-ext.adoc,4022,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations > Vector Single-Width Floating-Point Reduction Instructions > Vector Unordered Single-Width Floating-Point Sum Reduction","The implementation must produce a result equivalent to a reduction tree composed of binary operator nodes, with the inputs being elements from the source vector register group (`vs2`) and the source scalar value (`vs1[0]`).",non_CSR_parameter,enum,very_high,False, +chunk_81a246ff,src/v-st-ext.adoc,4022,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations > Vector Single-Width Floating-Point Reduction Instructions > Vector Unordered Single-Width Floating-Point Sum Reduction","Each operator first computes an exact sum as a RISC-V scalar floating-point addition with infinite exponent range and precision, then converts this exact sum to a floating-point format with range and precision each at least as great as the element floating-point format indicated by SEW, rounding using the currently active floating-point dynamic rounding mode and raising exception flags as necessary. A different floating-point range and precision may be chosen for the result of each operator. A node where one input is derived only from elements masked-off or beyond the active vector length may either treat that input as the additive identity of the appropriate EEW or simply copy the other input to its output.",non_CSR_parameter,range,high,False, +chunk_f71b5fc5,src/v-st-ext.adoc,4044,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations > Vector Single-Width Floating-Point Reduction Instructions > Vector Unordered Single-Width Floating-Point Sum Reduction",The additive identity is +0.0 when rounding down (towards -{inf}) or -0.0 for all other rounding modes.,unknown,unknown,high,False, +chunk_84b5f542,src/v-st-ext.adoc,4047,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations > Vector Single-Width Floating-Point Reduction Instructions > Vector Unordered Single-Width Floating-Point Sum Reduction",The reduction tree structure must be deterministic for a given value in `vtype` and `vl`.,CSR_controlled,enum,very_high,False, +chunk_b30184dc,src/v-st-ext.adoc,4050,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations > Vector Single-Width Floating-Point Reduction Instructions > Vector Unordered Single-Width Floating-Point Sum Reduction","In particular, if no elements are active and the scalar input is NaN, implementations are permitted to canonicalize the NaN and, if the NaN is signaling, set the invalid exception flag.",unknown,unknown,high,False, +chunk_ce0d4f21,src/v-st-ext.adoc,4050,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations > Vector Single-Width Floating-Point Reduction Instructions > Vector Unordered Single-Width Floating-Point Sum Reduction","Implementations are alternatively permitted to pass through the original NaN and set no exception flags, as with `vfredosum`.",unknown,unknown,high,False, +chunk_0d378927,src/v-st-ext.adoc,4071,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations > Vector Single-Width Floating-Point Reduction Instructions > Vector Single-Width Floating-Point Max and Min Reductions","If no elements are active, the scalar in `vs1[0]` is simply copied to the destination register, without canonicalizing NaN values and without setting any exception flags.",unknown,unknown,high,False, +chunk_a14b951e,src/v-st-ext.adoc,4078,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations > Vector Widening Floating-Point Reduction Instructions",Widening forms of the sum reductions are provided that read and write a double-width reduction result.,unknown,unknown,high,False, +chunk_7b272c87,src/v-st-ext.adoc,4105,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Mask-Register Logical Instructions",Vector mask-register logical operations operate on mask registers.,unknown,unknown,high,False, +chunk_9694aaed,src/v-st-ext.adoc,4105,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Mask-Register Logical Instructions","Each element in a mask register is a single bit, so these instructions all operate on single vector registers regardless of the setting of the `vlmul` field in `vtype`.",CSR_controlled,enum,high,False, +chunk_6bddb64b,src/v-st-ext.adoc,4105,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Mask-Register Logical Instructions",They do not change the value of `vlmul`.,CSR_controlled,enum,high,False, +chunk_2b1c792e,src/v-st-ext.adoc,4105,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Mask-Register Logical Instructions",The destination vector register may be the same as either source vector register.,non_CSR_parameter,enum,high,False, +chunk_17e270ca,src/v-st-ext.adoc,4112,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Mask-Register Logical Instructions","As with other vector instructions, the elements with indices less than `vstart` are unchanged, and `vstart` is reset to zero after execution.",CSR_controlled,binary,high,False, +chunk_22f53182,src/v-st-ext.adoc,4112,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Mask-Register Logical Instructions","Vector mask logical instructions are always unmasked, so there are no inactive elements, and the encodings with `vm=0` are reserved.",unknown,enum,high,False, +chunk_182130d3,src/v-st-ext.adoc,4112,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Mask-Register Logical Instructions","Mask elements past `vl`, the tail elements, are always updated with a tail-agnostic policy.",CSR_controlled,enum,high,False, +chunk_da4b8205,src/v-st-ext.adoc,4119,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Mask-Register Logical Instructions","---- vmand.mm vd, vs2, vs1 vd.mask[i] = vs2.mask[i] && vs1.mask[i] vmnand.mm vd, vs2, vs1 vd.mask[i] = !(vs2.mask[i] && vs1.mask[i]) vmandn.mm vd, vs2, vs1 vd.mask[i] = vs2.mask[i] && !vs1.mask[i] vmxor.mm vd, vs2, vs1 vd.mask[i] = vs2.mask[i] ^^ vs1.mask[i] vmor.mm vd, vs2, vs1 vd.mask[i] = vs2.mask[i] || vs1.mask[i] vmnor.mm vd, vs2, vs1 vd.mask[i] = !(vs2.mask[i] || vs1.mask[i]) vmorn.mm vd, vs2, vs1 vd.mask[i] = vs2.mask[i] || !vs1.mask[i] vmxnor.mm vd, vs2, vs1 vd.mask[i] = !(vs2.mask[i] ^^ vs1.mask[i]) ----",unknown,unknown,high,False, +chunk_c4f5a9ef,src/v-st-ext.adoc,4131,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Mask-Register Logical Instructions",The old `vmandnot` and `vmornot` mnemonics can be retained as assembler aliases for compatibility.,unknown,unknown,high,False, +chunk_72e72db8,src/v-st-ext.adoc,4136,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Mask-Register Logical Instructions","Several assembler pseudoinstructions are defined as shorthand for common uses of mask logical operations: ---- vmmv.m vd, vs => vmand.mm vd, vs, vs Copy mask register vmclr.m vd => vmxor.mm vd, vd, vd Clear mask register vmset.m vd => vmxnor.mm vd, vd, vd Set mask register vmnot.m vd, vs => vmnand.mm vd, vs, vs Invert bits ----",unknown,unknown,high,False, +chunk_43432ade,src/v-st-ext.adoc,4145,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Mask-Register Logical Instructions",The `vmcpy.m` assembler pseudoinstruction can be retained for compatibility.,unknown,unknown,high,False, +chunk_7111b863,src/v-st-ext.adoc,4145,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Mask-Register Logical Instructions","For implementations that internally rearrange bits according to EEW, a `vmmv.m` instruction with same source and destination can be used as idiom to force an internal reformat into a mask vector.",unknown,unknown,high,False, +chunk_fc5f2a7f,src/v-st-ext.adoc,4153,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Mask-Register Logical Instructions",The set of eight mask logical instructions can generate any of the 16 possibly binary logical functions of the two input masks:,unknown,unknown,high,False, +chunk_b1bcac2f,src/v-st-ext.adoc,4160,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Mask-Register Logical Instructions",| 0 | 0 | 1 | 1 | src1 | 0 | 1 | 0 | 1 | src2 |,unknown,unknown,high,False, +chunk_141503eb,src/v-st-ext.adoc,4164,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Mask-Register Logical Instructions","[cols=""1,1,1,1,6,6""] | 4+| output | instruction | pseudoinstruction",unknown,unknown,high,False, +chunk_b33c25b1,src/v-st-ext.adoc,4168,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Mask-Register Logical Instructions","| 0 | 0 | 0 | 0 | vmxor.mm vd, vd, vd | vmclr.m vd | 1 | 0 | 0 | 0 | vmnor.mm vd, src1, src2 | | 0 | 1 | 0 | 0 | vmandn.mm vd, src2, src1 | | 1 | 1 | 0 | 0 | vmnand.mm vd, src1, src1 | vmnot.m vd, src1 | 0 | 0 | 1 | 0 | vmandn.mm vd, src1, src2 | | 1 | 0 | 1 | 0 | vmnand.mm vd, src2, src2 | vmnot.m vd, src2 | 0 | 1 | 1 | 0 | vmxor.mm vd, src1, src2 | | 1 | 1 | 1 | 0 | vmnand.mm vd, src1, src2 | | 0 | 0 | 0 | 1 | vmand.mm vd, src1, src2 | | 1 | 0 | 0 | 1 | vmxnor.mm vd, src1, src2 | | 0 | 1 | 0 | 1 | vmand.mm vd, src2, src2 | vmmv.m vd, src2 | 1 | 1 | 0 | 1 | vmorn.mm vd, src2, src1 | | 0 | 0 | 1 | 1 | vmand.mm vd, src1, src1 | vmmv.m vd, src1 | 1 | 0 | 1 | 1 | vmorn.mm vd, src1, src2 | | 0 | 1 | 1 | 1 | vmor.mm vd, src1, src2 | | 1 | 1 | 1 | 1 | vmxnor.mm vd, vd, vd | vmset.m vd |",unknown,unknown,high,False, +chunk_588bb847,src/v-st-ext.adoc,4217,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector count population in mask `vcpop.m`","The `vcpop.m` instruction writes `x[rd]` even if `vl`=0 (with the value 0, since no mask elements are active).",CSR_controlled,enum,high,False, +chunk_ee999c5d,src/v-st-ext.adoc,4220,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector count population in mask `vcpop.m`",Traps on `vcpop.m` are always reported with a `vstart` of 0.,CSR_controlled,enum,high,False, +chunk_1cd9d0f2,src/v-st-ext.adoc,4220,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector count population in mask `vcpop.m`",The `vcpop.m` instruction will raise an illegal-instruction exception if `vstart` is non-zero.,CSR_controlled,enum,high,False, +chunk_6977a624,src/v-st-ext.adoc,4230,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > `vfirst` find-first-set mask bit","If no active element has the value 1, -1 is written to the GPR.",unknown,unknown,high,False, +chunk_48003e61,src/v-st-ext.adoc,4239,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > `vfirst` find-first-set mask bit","The `vfirst.m` instruction writes `x[rd]` even if `vl`=0 (with the value -1, since no mask elements are active).",CSR_controlled,enum,high,False, +chunk_abab55e1,src/v-st-ext.adoc,4242,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > `vfirst` find-first-set mask bit",Traps on `vfirst` are always reported with a `vstart` of 0.,CSR_controlled,enum,high,False, +chunk_b1d916b3,src/v-st-ext.adoc,4242,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > `vfirst` find-first-set mask bit",The `vfirst` instruction will raise an illegal-instruction exception if `vstart` is non-zero.,CSR_controlled,enum,high,False, +chunk_e4d11974,src/v-st-ext.adoc,4273,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > `vmsbf.m` set-before-first mask bit","If there is no set bit in the active elements of the source vector, then all active elements in the destination are written with a 1.",unknown,unknown,high,False, +chunk_5370701a,src/v-st-ext.adoc,4283,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > `vmsbf.m` set-before-first mask bit",Traps on `vmsbf.m` are always reported with a `vstart` of 0.,CSR_controlled,enum,high,False, +chunk_62ba7498,src/v-st-ext.adoc,4283,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > `vmsbf.m` set-before-first mask bit",The `vmsbf` instruction will raise an illegal-instruction exception if `vstart` is non-zero.,CSR_controlled,enum,high,False, +chunk_523dacea,src/v-st-ext.adoc,4287,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > `vmsbf.m` set-before-first mask bit","The destination register cannot overlap the source register and, if masked, cannot overlap the mask register (`v0`).",unknown,unknown,high,False, +chunk_e871eff9,src/v-st-ext.adoc,4319,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > `vmsif.m` set-including-first mask bit",Traps on `vmsif.m` are always reported with a `vstart` of 0.,CSR_controlled,enum,high,False, +chunk_e61d2738,src/v-st-ext.adoc,4319,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > `vmsif.m` set-including-first mask bit",The `vmsif` instruction will raise an illegal-instruction exception if `vstart` is non-zero.,CSR_controlled,enum,high,False, +chunk_33ae605e,src/v-st-ext.adoc,4323,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > `vmsif.m` set-including-first mask bit","The destination register cannot overlap the source register and, if masked, cannot overlap the mask register (`v0`).",unknown,unknown,high,False, +chunk_75fcb78c,src/v-st-ext.adoc,4328,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > `vmsof.m` set-only-first mask bit","The vector mask set-only-first instruction is similar to set-before-first, except it only sets the first element with a bit set, if any.",unknown,unknown,high,False, +chunk_d7a8c05b,src/v-st-ext.adoc,4356,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > `vmsof.m` set-only-first mask bit",Traps on `vmsof.m` are always reported with a `vstart` of 0.,CSR_controlled,enum,high,False, +chunk_5b9c39f1,src/v-st-ext.adoc,4356,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > `vmsof.m` set-only-first mask bit",The `vmsof` instruction will raise an illegal-instruction exception if `vstart` is non-zero.,CSR_controlled,enum,high,False, +chunk_7774827c,src/v-st-ext.adoc,4360,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > `vmsof.m` set-only-first mask bit","The destination register cannot overlap the source register and, if masked, cannot overlap the mask register (`v0`).",unknown,unknown,high,False, +chunk_e97a5ac2,src/v-st-ext.adoc,4396,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Iota Instruction","1 1 1 0 1 0 1 1 v0 contents 1 0 0 1 0 0 0 1 v2 contents 2 3 4 5 6 7 8 9 v4 contents viota.m v4, v2, v0.t Masked, vtype.vma=0 1 1 1 5 1 7 1 0 v4 results ----",CSR_controlled,enum,high,False, +chunk_db760b2f,src/v-st-ext.adoc,4403,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Iota Instruction",The result value is zero-extended to fill the destination element if SEW is wider than the result.,unknown,enum,high,False, +chunk_22e45d2c,src/v-st-ext.adoc,4403,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Iota Instruction","If the result value would overflow the destination SEW, the least-significant SEW bits are retained.",unknown,unknown,high,False, +chunk_7baafd20,src/v-st-ext.adoc,4407,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Iota Instruction","Traps on `viota.m` are always reported with a `vstart` of 0, and execution is always restarted from the beginning when resuming after a trap handler.",CSR_controlled,enum,high,False, +chunk_7ff4a988,src/v-st-ext.adoc,4407,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Iota Instruction",An illegal-instruction exception is raised if `vstart` is non-zero.,CSR_controlled,enum,high,False, +chunk_a35efd59,src/v-st-ext.adoc,4412,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Iota Instruction","The destination register group cannot overlap the source register and, if masked, cannot overlap the mask register (`v0`).",unknown,unknown,high,False, +chunk_9eeeccdd,src/v-st-ext.adoc,4418,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Iota Instruction","---- Compact non-zero elements from input memory array to output memory array sizet compactnonzero(sizet n, const int* in, int* out) { sizet i; int *p = out; for (i=0; i ""V"" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Iota Instruction","compactnonzero: li a6, 0 Clear count of non-zero elements loop: vsetvli a5, a0, e32, m8, ta, ma 32-bit integers vle32.v v8, (a1) Load input vector sub a0, a0, a5 Decrement number done slli a5, a5, 2 Multiply by four bytes vmsne.vi v0, v8, 0 Locate non-zero values add a1, a1, a5 Bump input pointer vcpop.m a5, v0 Count number of elements set in v0 viota.m v16, v0 Get destination offsets of active elements add a6, a6, a5 Accumulate number of elements vsll.vi v16, v16, 2, v0.t Multiply offsets by four bytes slli a5, a5, 2 Multiply number of non-zero elements by four bytes vsuxei32.v v8, (a2), v16, v0.t Scatter using scaled viota results under mask add a2, a2, a5 Bump output pointer bnez a0, loop Any more?",CSR_controlled,range,high,False, +chunk_ca8888e5,src/v-st-ext.adoc,4464,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Element Index Instruction","The `vid.v` instruction writes each element's index to the destination vector register group, from 0 to `vl`-1.",CSR_controlled,enum,high,False, +chunk_a9e9a162,src/v-st-ext.adoc,4474,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Element Index Instruction","The `vs2` field of the instruction must be set to `v0`, otherwise the encoding is reserved.",non_CSR_parameter,enum,very_high,False, +chunk_75931988,src/v-st-ext.adoc,4477,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Element Index Instruction",The result value is zero-extended to fill the destination element if SEW is wider than the result.,unknown,enum,high,False, +chunk_ef2ed3f4,src/v-st-ext.adoc,4477,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Element Index Instruction","If the result value would overflow the destination SEW, the least-significant SEW bits are retained.",unknown,unknown,high,False, +chunk_a2870437,src/v-st-ext.adoc,4492,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Integer Scalar Move Instructions",The integer scalar read/write instructions transfer a single value between a scalar `x` register and element 0 of a vector register.,unknown,unknown,high,False, +chunk_1b11c757,src/v-st-ext.adoc,4501,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Integer Scalar Move Instructions","If SEW > XLEN, the least-significant XLEN bits are transferred and the upper SEW-XLEN bits are ignored.",unknown,range,high,False, +chunk_d4fac149,src/v-st-ext.adoc,4501,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Integer Scalar Move Instructions","If SEW < XLEN, the value is sign-extended to XLEN bits.",unknown,range,high,False, +chunk_1eff46e3,src/v-st-ext.adoc,4508,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Integer Scalar Move Instructions","If SEW < XLEN, the least-significant bits are copied and the upper XLEN-SEW bits are ignored.",unknown,unknown,high,False, +chunk_9d52996d,src/v-st-ext.adoc,4508,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Integer Scalar Move Instructions","If SEW > XLEN, the value is sign-extended to SEW bits.",unknown,enum,high,False, +chunk_36ecfd75,src/v-st-ext.adoc,4508,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Integer Scalar Move Instructions",The other elements in the destination vector register ( 0 < index < VLEN/SEW) are treated as tail elements using the current tail agnostic/undisturbed policy.,CSR_controlled,enum,high,False, +chunk_a5832245,src/v-st-ext.adoc,4524,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Floating-Point Scalar Move Instructions",The floating-point scalar read/write instructions transfer a single value between a scalar `f` register and element 0 of a vector register.,unknown,unknown,high,False, +chunk_7c96b96a,src/v-st-ext.adoc,4539,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Floating-Point Scalar Move Instructions",The other elements in the destination vector register ( 0 < index < VLEN/SEW) are treated as tail elements using the current tail agnostic/undisturbed policy.,CSR_controlled,enum,high,False, +chunk_58fb62d7,src/v-st-ext.adoc,4557,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions",Implementations may optimize certain OFFSET values for `vslideup` and `vslidedown`.,non_CSR_parameter,enum,medium,False, +chunk_e788e6ec,src/v-st-ext.adoc,4557,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions","In particular, power-of-2 offsets may operate substantially faster than other offsets.",non_CSR_parameter,enum,medium,False, +chunk_a06ce344,src/v-st-ext.adoc,4563,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions","For all of the `vslideup`, `vslidedown`, `v[f]slide1up`, and `v[f]slide1down` instructions, if `vstart` {ge} `vl`, the instruction performs no operation and leaves the destination vector register unchanged.",CSR_controlled,enum,high,False, +chunk_01230961,src/v-st-ext.adoc,4572,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions","The slide instructions may be masked, with mask element i controlling whether destination element i is written.",non_CSR_parameter,enum,medium,False, +chunk_f3d0d241,src/v-st-ext.adoc,4583,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-up Instructions","For `vslideup`, the value in `vl` specifies the maximum number of destination elements that are written.",CSR_controlled,range,high,False, +chunk_fc2831b4,src/v-st-ext.adoc,4583,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-up Instructions","The start index (OFFSET) for the destination can be either specified using an unsigned integer in the `x` register specified by `rs1`, or a 5-bit immediate, zero-extended to XLEN bits.",non_CSR_parameter,range,high,False, +chunk_fa60b433,src/v-st-ext.adoc,4583,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-up Instructions","If XLEN > SEW, OFFSET is not truncated to SEW bits.",unknown,unknown,high,False, +chunk_70f32fc3,src/v-st-ext.adoc,4583,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-up Instructions",Destination elements OFFSET through `vl`-1 are written if unmasked and if OFFSET < `vl`.,CSR_controlled,enum,high,False, +chunk_7b61bfd5,src/v-st-ext.adoc,4591,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-up Instructions",---- vslideup behavior for destination elements (vstart < vl),CSR_controlled,enum,high,False, +chunk_73ca926d,src/v-st-ext.adoc,4594,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-up Instructions","OFFSET is amount to slideup, either from x register or a 5-bit immediate",non_CSR_parameter,range,medium,False, +chunk_4a8f21f9,src/v-st-ext.adoc,4596,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-up Instructions","0 <= i < min(vl, max(vstart, OFFSET)) Unchanged max(vstart, OFFSET) <= i < vl vd[i] = vs2[i-OFFSET] if v0.mask[i] enabled vl <= i < VLMAX Follow tail policy ----",CSR_controlled,binary,high,False, +chunk_cc004563,src/v-st-ext.adoc,4616,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-down Instructions","For `vslidedown`, the value in `vl` specifies the maximum number of destination elements that are written.",CSR_controlled,range,high,False, +chunk_569cbb2b,src/v-st-ext.adoc,4616,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-down Instructions",The remaining elements past `vl` are handled according to the current tail policy ().,CSR_controlled,enum,high,False, +chunk_3b680b09,src/v-st-ext.adoc,4621,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-down Instructions","The start index (OFFSET) for the source can be either specified using an unsigned integer in the `x` register specified by `rs1`, or a 5-bit immediate, zero-extended to XLEN bits.",non_CSR_parameter,range,high,False, +chunk_c1a17417,src/v-st-ext.adoc,4621,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-down Instructions","If XLEN > SEW, OFFSET is not truncated to SEW bits.",unknown,unknown,high,False, +chunk_a0b329d0,src/v-st-ext.adoc,4626,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-down Instructions",---- vslidedown behavior for source elements for element i in slide (vstart < vl) 0 <= i+OFFSET < VLMAX src[i] = vs2[i+OFFSET] VLMAX <= i+OFFSET src[i] = 0,CSR_controlled,enum,high,False, +chunk_c2bd2a4e,src/v-st-ext.adoc,4631,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-down Instructions",vslidedown behavior for destination element i in slide (vstart < vl) 0 <= i < vstart Unchanged vstart <= i < vl vd[i] = src[i] if v0.mask[i] enabled vl <= i < VLMAX Follow tail policy ----,CSR_controlled,binary,high,False, +chunk_fd2a667f,src/v-st-ext.adoc,4639,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-1-up",Variants of slide are provided that only move by one element but which also allow a scalar integer value to be inserted at the vacated element position.,unknown,unknown,high,False, +chunk_97842578,src/v-st-ext.adoc,4647,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-1-up","The `vslide1up` instruction places the `x` register argument at location 0 of the destination vector register group, provided that element 0 is active, otherwise the destination element update follows the current mask agnostic/undisturbed policy.",unknown,unknown,high,False, +chunk_0812bdd1,src/v-st-ext.adoc,4647,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-1-up","If XLEN < SEW, the value is sign-extended to SEW bits.",unknown,enum,high,False, +chunk_0732b9c3,src/v-st-ext.adoc,4647,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-1-up","If XLEN > SEW, the least-significant bits are copied over and the high XLEN-SEW bits are ignored.",unknown,unknown,high,False, +chunk_6aefd1ad,src/v-st-ext.adoc,4658,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-1-up","The `vl` register specifies the maximum number of destination vector register elements updated with source values, and remaining elements past `vl` are handled according to the current tail policy ().",CSR_controlled,range,high,False, +chunk_2fd0b917,src/v-st-ext.adoc,4663,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-1-up",---- vslide1up behavior when vl > 0,CSR_controlled,enum,high,False, +chunk_12b3fc04,src/v-st-ext.adoc,4666,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-1-up","i < vstart unchanged 0 = i = vstart vd[i] = x[rs1] if v0.mask[i] enabled max(vstart, 1) <= i < vl vd[i] = vs2[i-1] if v0.mask[i] enabled vl <= i < VLMAX Follow tail policy ----",CSR_controlled,binary,high,False, +chunk_a4b9b4ae,src/v-st-ext.adoc,4693,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-1-down Instruction","The `vl` register specifies the maximum number of destination vector register elements written with source values, and remaining elements past `vl` are handled according to the current tail policy ().",CSR_controlled,range,high,False, +chunk_2c7c4241,src/v-st-ext.adoc,4698,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-1-down Instruction","---- vslide1down.vx vd, vs2, rs1, vm vd[i] = vs2[i+1], vd[vl-1]=x[rs1] ----",CSR_controlled,enum,high,False, +chunk_54edfb97,src/v-st-ext.adoc,4702,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-1-down Instruction","The `vslide1down` instruction places the `x` register argument at location `vl`-1 in the destination vector register, provided that element `vl-1` is active, otherwise the destination element update follows the current mask agnostic/undisturbed policy.",CSR_controlled,enum,high,False, +chunk_3ac62189,src/v-st-ext.adoc,4702,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-1-down Instruction","If XLEN < SEW, the value is sign-extended to SEW bits.",unknown,enum,high,False, +chunk_54b32d67,src/v-st-ext.adoc,4702,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-1-down Instruction","If XLEN > SEW, the least-significant bits are copied over and the high SEW-XLEN bits are ignored.",unknown,range,high,False, +chunk_7b415b1d,src/v-st-ext.adoc,4713,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-1-down Instruction",i < vstart unchanged vstart <= i < vl-1 vd[i] = vs2[i+1] if v0.mask[i] enabled vstart <= i = vl-1 vd[vl-1] = x[rs1] if v0.mask[i] enabled vl <= i < VLMAX Follow tail policy ----,CSR_controlled,binary,high,False, +chunk_1473405c,src/v-st-ext.adoc,4728,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Floating-Point Slide-1-down Instruction","---- vfslide1down.vf vd, vs2, rs1, vm vd[i] = vs2[i+1], vd[vl-1]=f[rs1] ----",CSR_controlled,enum,high,False, +chunk_0b5ab9c5,src/v-st-ext.adoc,4737,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Register Gather Instructions",The vector register gather instructions read elements from a first source vector register group at locations given by a second source vector register group.,unknown,unknown,high,False, +chunk_2ca45b80,src/v-st-ext.adoc,4737,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Register Gather Instructions",The index values in the second vector are treated as unsigned integers.,unknown,unknown,high,False, +chunk_cda645c7,src/v-st-ext.adoc,4737,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Register Gather Instructions",The source vector can be read at any index < VLMAX regardless of `vl`.,CSR_controlled,enum,high,False, +chunk_7b373d05,src/v-st-ext.adoc,4737,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Register Gather Instructions","The maximum number of elements to write to the destination register is given by `vl`, and the remaining elements past `vl` are handled according to the current tail policy ().",CSR_controlled,range,high,False, +chunk_bf7e8005,src/v-st-ext.adoc,4737,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Register Gather Instructions","The operation can be masked, and the mask undisturbed/agnostic policy is followed for inactive elements.",unknown,unknown,high,False, +chunk_39b3a901,src/v-st-ext.adoc,4747,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Register Gather Instructions","---- vrgather.vv vd, vs2, vs1, vm vd[i] = (vs1[i] >= VLMAX) ? 0 : vs2[vs1[i]]; vrgatherei16.vv vd, vs2, vs1, vm vd[i] = (vs1[i] >= VLMAX) ? 0 : vs2[vs1[i]]; ----",CSR_controlled,enum,high,False, +chunk_63535f93,src/v-st-ext.adoc,4753,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Register Gather Instructions",The `vrgather.vv` form uses SEW/LMUL for both the data and indices.,unknown,unknown,high,False, +chunk_38b48a5f,src/v-st-ext.adoc,4753,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Register Gather Instructions",The `vrgatherei16.vv` form uses SEW/LMUL for the data in `vs2` but EEW=16 and EMUL = (16/SEW)*LMUL for the indices in `vs1`.,unknown,unknown,high,False, +chunk_ee540469,src/v-st-ext.adoc,4757,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Register Gather Instructions","When SEW=8, `vrgather.vv` can only reference vector elements 0-255.",unknown,unknown,high,False, +chunk_611b9e0c,src/v-st-ext.adoc,4757,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Register Gather Instructions","The `vrgatherei16` form can index 64K elements, and can also be used to reduce the register capacity needed to hold indices when SEW > 16.",unknown,unknown,high,False, +chunk_8f637b17,src/v-st-ext.adoc,4762,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Register Gather Instructions",If an element index is out of range ( `vs1[i]` {ge} VLMAX ) then zero is returned for the element value.,CSR_controlled,enum,high,False, +chunk_5e09101b,src/v-st-ext.adoc,4765,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Register Gather Instructions",Vector-scalar and vector-immediate forms of the register gather are also provided.,unknown,unknown,high,False, +chunk_aae7d88d,src/v-st-ext.adoc,4765,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Register Gather Instructions","These read one element from the source vector at the given index, and write this value to the active elements of the destination vector register.",unknown,unknown,high,False, +chunk_07040439,src/v-st-ext.adoc,4765,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Register Gather Instructions","The index value in the scalar register and the immediate, zero-extended to XLEN bits, are treated as unsigned integers.",unknown,range,high,False, +chunk_7fd5cb29,src/v-st-ext.adoc,4765,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Register Gather Instructions","If XLEN > SEW, the index value is not truncated to SEW bits.",unknown,unknown,high,False, +chunk_7536e6bc,src/v-st-ext.adoc,4775,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Register Gather Instructions","---- vrgather.vx vd, vs2, rs1, vm vd[i] = (x[rs1] >= VLMAX) ? 0 : vs2[x[rs1]] vrgather.vi vd, vs2, uimm, vm vd[i] = (uimm >= VLMAX) ? 0 : vs2[uimm] ----",CSR_controlled,enum,high,False, +chunk_cddfc96e,src/v-st-ext.adoc,4780,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Register Gather Instructions","For any `vrgather` instruction, the destination vector register group cannot overlap with the source vector register groups, otherwise the instruction encoding is reserved.",unknown,enum,high,False, +chunk_30e5151c,src/v-st-ext.adoc,4795,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Compress Instruction",The vector mask register specified by `vs1` indicates which of the first `vl` elements of vector register group `vs2` should be extracted and packed into contiguous elements at the beginning of vector register `vd`.,CSR_controlled,enum,high,False, +chunk_79bd8b48,src/v-st-ext.adoc,4807,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Compress Instruction","1 1 0 1 0 0 1 0 1 v0 8 7 6 5 4 3 2 1 0 v1 1 2 3 4 5 6 7 8 9 v2 vsetivli t0, 9, e8, m1, tu, ma vcompress.vm v2, v1, v0 1 2 3 4 8 7 5 2 0 v2 ----",CSR_controlled,enum,high,False, +chunk_6170a268,src/v-st-ext.adoc,4815,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Compress Instruction",T`vcompress` is encoded as an unmasked instruction (`vm=1`).,unknown,enum,high,False, +chunk_eabb5799,src/v-st-ext.adoc,4822,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Compress Instruction",A trap on a `vcompress` instruction is always reported with a `vstart` of 0.,CSR_controlled,enum,high,False, +chunk_c2a73b4b,src/v-st-ext.adoc,4822,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Compress Instruction",Executing a `vcompress` instruction with a non-zero `vstart` raises an illegal-instruction exception.,CSR_controlled,enum,high,False, +chunk_60c2eecb,src/v-st-ext.adoc,4826,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Compress Instruction",This does mean elements in destination register after `vstart` will already have been updated.,CSR_controlled,enum,high,False, +chunk_17c36ae1,src/v-st-ext.adoc,4866,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Whole Vector Register Move","The `nr` value in the opcode is the number of individual vector registers, NREG, to copy.",unknown,unknown,high,False, +chunk_86d405e4,src/v-st-ext.adoc,4866,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Whole Vector Register Move","The instructions operate as if EEW=SEW, EMUL = NREG, effective length `evl`= EMUL * VLEN/SEW.",CSR_controlled,enum,high,False, +chunk_9a383ad3,src/v-st-ext.adoc,4875,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Whole Vector Register Move",The usual property that no elements are written if `vstart` {ge} `vl` does not apply to these instructions.,CSR_controlled,enum,high,False, +chunk_5867c880,src/v-st-ext.adoc,4875,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Whole Vector Register Move","Similarly, the property that the instructions are reserved if `vstart` exceeds the largest element index for the current `vtype` setting does not apply.",CSR_controlled,enum,high,False, +chunk_c360baeb,src/v-st-ext.adoc,4875,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Whole Vector Register Move","Instead, the instructions are reserved if `vstart` {ge} `evl`.",CSR_controlled,enum,high,False, +chunk_7e5462d8,src/v-st-ext.adoc,4882,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Whole Vector Register Move","If `vd` is equal to `vs2`, the instruction does not change any vector register state.",unknown,range,high,False, +chunk_4a963a93,src/v-st-ext.adoc,4882,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Whole Vector Register Move",Implementations that rearrange data internally can treat this instruction as a hint that the register group will next be accessed with an EEW equal to SEW.,unknown,range,high,False, +chunk_9e2df6bd,src/v-st-ext.adoc,4888,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Whole Vector Register Move",The instruction is encoded as an OPIVI instruction.,unknown,enum,high,False, +chunk_f6668414,src/v-st-ext.adoc,4893,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Whole Vector Register Move","The value of NREG must be 1, 2, 4, or 8, and values of `simm[4:0]` other than 0, 1, 3, and 7 are reserved.",non_CSR_parameter,enum,very_high,False, +chunk_6f08d54b,src/v-st-ext.adoc,4898,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Whole Vector Register Move","This encoding is chosen as it is close to the related `vmerge` encoding, and it is unlikely the `vsmul` instruction would benefit from an immediate form.",unknown,enum,high,False, +chunk_71960078,src/v-st-ext.adoc,4913,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Whole Vector Register Move","The source and destination vector register numbers must be aligned appropriately for the vector register group size, and encodings with other vector register numbers are reserved.",non_CSR_parameter,enum,very_high,False, +chunk_cc28174e,src/v-st-ext.adoc,4922,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Exception Handling","On a trap during a vector instruction (caused by either a synchronous exception or an asynchronous interrupt), the existing `*epc` CSR is written with a pointer to the trapping vector instruction, while the `vstart` CSR contains the element index on which the trap was taken.",CSR_controlled,enum,high,False, +chunk_e04db574,src/v-st-ext.adoc,4928,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Exception Handling","To ensure forward progress without the `vstart` CSR, implementations would have to guarantee an entire vector instruction can always complete atomically without generating a trap.",CSR_controlled,enum,high,False, +chunk_1841408f,src/v-st-ext.adoc,4950,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Exception Handling > Precise vector traps","We relax the last requirement to allow elements following `vstart` to have been updated at the time the trap is reported, provided that re-executing the instruction from the given `vstart` will correctly overwrite those elements.",CSR_controlled,enum,high,False, +chunk_407f951b,src/v-st-ext.adoc,4955,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Exception Handling > Precise vector traps","In idempotent memory regions, vector store instructions may have updated elements in memory past the element causing a synchronous trap.",non_CSR_parameter,enum,high,False, +chunk_a7889603,src/v-st-ext.adoc,4955,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Exception Handling > Precise vector traps",Non-idempotent memory regions must not have been updated for indices equal to or greater than the element that caused a synchronous trap during a vector store instruction.,non_CSR_parameter,range,very_high,False, +chunk_b8441f87,src/v-st-ext.adoc,4961,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Exception Handling > Precise vector traps","Except where noted above, vector instructions are allowed to overwrite their inputs, and so in most cases, the vector instruction restart must be from the `vstart` element index.",CSR_controlled,enum,very_high,False, +chunk_bd0d0892,src/v-st-ext.adoc,4968,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Exception Handling > Precise vector traps",Implementations must ensure forward progress can be eventually guaranteed for the element or segment reported by `vstart`.,CSR_controlled,enum,very_high,False, +chunk_cf29ffa9,src/v-st-ext.adoc,4973,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Exception Handling > Imprecise vector traps",Imprecise vector traps are traps that are not precise.,unknown,unknown,high,False, +chunk_dab23b82,src/v-st-ext.adoc,4973,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Exception Handling > Imprecise vector traps","In particular, instructions newer than `*epc` may have committed results, and instructions older than `*epc` may have not completed execution.",non_CSR_parameter,enum,medium,False, +chunk_6ca58132,src/v-st-ext.adoc,4980,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Exception Handling > Imprecise vector traps","We assume many embedded implementations will generate only imprecise traps for vector instructions on fatal errors, as they will not require resumable traps.",unknown,unknown,high,False, +chunk_a73dcb9d,src/v-st-ext.adoc,4985,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Exception Handling > Imprecise vector traps",Imprecise traps shall report the faulting element in `vstart` for traps caused by synchronous vector exceptions.,CSR_controlled,enum,very_high,False, +chunk_6d387ad0,src/v-st-ext.adoc,4988,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Exception Handling > Imprecise vector traps",There is no support for imprecise traps in the current standard extensions.,unknown,unknown,high,False, +chunk_2bd29a03,src/v-st-ext.adoc,4992,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Exception Handling > Selectable precise/imprecise traps",Some profiles may choose to provide a privileged mode bit to select between precise and imprecise vector traps.,non_CSR_parameter,enum,high,False, +chunk_ef08a509,src/v-st-ext.adoc,5003,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Exception Handling > Swappable traps","Another trap mode can support swappable state in the vector unit, where on a trap, special instructions can save and restore the vector unit microarchitectural state, to allow execution to continue correctly around imprecise traps.",unknown,unknown,high,False, +chunk_d1027985,src/v-st-ext.adoc,5030,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > Zvl*: Minimum Vector Length Extensions",All standard vector extensions have a minimum required VLEN as described below. A set of vector length extensions are provided to increase the minimum vector length of a vector extension.,CSR_controlled,range,high,False, +chunk_d21b8b44,src/v-st-ext.adoc,5044,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > Zvl*: Minimum Vector Length Extensions",| Zvl32b | 32 | Zvl64b | 64 | Zvl128b | 128 | Zvl256b | 256 | Zvl512b | 512 | Zvl1024b | 1024 |,CSR_controlled,enum,high,False, +chunk_ecee0605,src/v-st-ext.adoc,5064,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > Zve*: Vector Extensions for Embedded Processors",The table lists the minimum VLEN and supported EEWs for each extension as well as what floating-point types are supported.,CSR_controlled,range,high,False, +chunk_a9633243,src/v-st-ext.adoc,5088,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > Zve*: Vector Extensions for Embedded Processors",All Zve* extensions have precise traps.,unknown,unknown,high,False, +chunk_f4c175c4,src/v-st-ext.adoc,5099,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > Zve*: Vector Extensions for Embedded Processors","All Zve* extensions support all vector load and store instructions (), except Zve64* extensions do not support EEW=64 for index values when XLEN=32.",unknown,unknown,high,False, +chunk_d358b70b,src/v-st-ext.adoc,5131,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > Zve*: Vector Extensions for Embedded Processors",The Zve32x extension depends on the Zicsr extension.,CSR_controlled,enum,high,False, +chunk_e8c152c0,src/v-st-ext.adoc,5155,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > V: Vector Extension for Application Processors",The V vector extension has precise traps.,unknown,unknown,high,False, +chunk_e33c1a69,src/v-st-ext.adoc,5157,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > V: Vector Extension for Application Processors",The V vector extension depends upon the Zvl128b and Zve64d extensions.,CSR_controlled,enum,high,False, +chunk_fb4daf3a,src/v-st-ext.adoc,5159,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > V: Vector Extension for Application Processors","Providing a larger VLEN allows strip-mining code to be elided in some cases for short vectors, but also increases the size of the minimum implementation.",CSR_controlled,range,high,False, +chunk_c3744897,src/v-st-ext.adoc,5173,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > V: Vector Extension for Application Processors","The V extension supports all vector load and store instructions (), except the V extension does not support EEW=64 for index values when XLEN=32.",unknown,unknown,high,False, +chunk_9d1e0c1c,src/v-st-ext.adoc,5204,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > Zvfhmin: Vector Extension for Minimal Half-Precision Floating-Point","When the Zvfhmin extension is implemented, the `vfwcvt.f.f.v` and `vfncvt.f.f.w` instructions become defined when SEW=16.",unknown,unknown,high,False, +chunk_b84dc252,src/v-st-ext.adoc,5216,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > Zvfh: Vector Extension for Half-Precision Floating-Point","When the Zvfh extension is implemented, all instructions in , , , , , and become defined when SEW=16.",unknown,unknown,high,False, +chunk_748bada1,src/v-st-ext.adoc,5226,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > Zvfh: Vector Extension for Half-Precision Floating-Point","Additionally, conversions between 8-bit integers and binary16 values are provided.",non_CSR_parameter,range,medium,False, +chunk_b806deb9,src/v-st-ext.adoc,5226,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > Zvfh: Vector Extension for Half-Precision Floating-Point",The floating-point-to-integer narrowing conversions (`vfncvt[.rtz].x[u].f.w`) and integer-to-floating-point widening conversions (`vfwcvt.f.x[u].v`) become defined when SEW=8.,unknown,unknown,high,False, +chunk_968b68c9,src/v-st-ext.adoc,5242,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Element Groups","As another example, the SHA-256 cryptographic instructions in the Zvknha extension operate on 128-bit values represented as a 4-element group of 32-bit elements.",non_CSR_parameter,range,medium,False, +chunk_8eecc1f7,src/v-st-ext.adoc,5256,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Element Groups > Element Group Size","The element group size (EGS) is the number of elements in one group, and must be a power-of-two (POT).",non_CSR_parameter,enum,very_high,False, +chunk_989808cd,src/v-st-ext.adoc,5259,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Element Groups > Element Group Size",Error checking for `vl` is a little more difficult.,CSR_controlled,enum,high,False, +chunk_6674c7ed,src/v-st-ext.adoc,5259,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Element Groups > Element Group Size","Non-POT EGS can also cause large increases in the lowest-common-multiple of element group sizes, which adds constraints to `vl` setting in order to avoid splitting an element group across strip-mine iterations in vector-length-agnostic code.",CSR_controlled,enum,high,False, +chunk_201b2057,src/v-st-ext.adoc,5268,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Element Groups > Element Group Size","The element group size is statically encoded in the instruction, often implicitly as part of the opcode.",unknown,enum,high,False, +chunk_ba9b0b66,src/v-st-ext.adoc,5271,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Element Groups > Element Group Size",Vector instructions with EGS > VLMAX are reserved.,CSR_controlled,enum,high,False, +chunk_34252ccb,src/v-st-ext.adoc,5283,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Element Groups > Setting `vl`","When an operand is a vector of element groups, the `vl` setting must correspond to an integer multiple of the element group size, with other values of `vl` reserved.",CSR_controlled,enum,very_high,False, +chunk_c5e85f62,src/v-st-ext.adoc,5292,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Element Groups > Setting `vl`","When element group instructions are present, an additional constraint is placed on the setting of `vl` based on an AVL value (augmenting ). EGSMAX is the largest EGS supported by the implementation.",CSR_controlled,enum,high,False, +chunk_01343bc4,src/v-st-ext.adoc,5292,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Element Groups > Setting `vl`","When AVL > VLMAX, the value of `vl` must be set to either VLMAX or a positive integer multiple of EGSMAX.",CSR_controlled,enum,very_high,False, +chunk_4a6faa2e,src/v-st-ext.adoc,5307,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Element Groups > Setting `vl`","If EEW is encoded statically in the instruction, or if an instruction has multiple operands containing vectors of element groups with different EEW, an appropriate SEW must be chosen for `vsetvl` instructions.",CSR_controlled,enum,very_high,False, +chunk_3b50ed53,src/v-st-ext.adoc,5323,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Element Groups > Determining EEW","Alternatively, the opcode might encode EEW of all operands statically and ignore the value of SEW when the operation only makes sense for a single size on each operand.",unknown,enum,high,False, +chunk_a883f232,src/v-st-ext.adoc,5346,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Element Groups > Determining EMUL","Each source and destination operand to a vector instruction may have a different element group size, different EMUL, and/or different EEW.",non_CSR_parameter,enum,medium,False, +chunk_3556f2e3,src/v-st-ext.adoc,5351,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Element Groups > Element Group Width",It is possible to use LMUL to concatenate multiple vector registers together to support larger EGW>VLEN.,CSR_controlled,enum,high,False, +chunk_db3172a7,src/v-st-ext.adoc,5358,"Preamble > ""V"" Extension for Vector Operations, Version 1.0 > Vector Element Groups > Element Group Width",Profiles can set minimum VLEN requirements to inform authors of such software.,CSR_controlled,range,high,False, +chunk_dcf68539,src/vector-crypto.adoc,19,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Intended Audience","Where possible, we have written this specification to be understandable by all, though we recognize that the motivations and references to algorithms or other specifications and standards may be unfamiliar to those who are not domain experts.",non_CSR_parameter,enum,medium,False, +chunk_325872c6,src/vector-crypto.adoc,26,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Intended Audience","We hope this aids people's understanding of which aspects of the specification are particularly relevant to them, and which they may (safely!) ignore or pass to a colleague.",non_CSR_parameter,enum,medium,False, +chunk_c5eae6f5,src/vector-crypto.adoc,35,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Intended Audience","They should understand the motivations for the instructions we include, and be familiar with most of the algorithms and outside standards to which we refer.",non_CSR_parameter,enum,medium,False, +chunk_370f9e33,src/vector-crypto.adoc,49,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Intended Audience","In particular, they should be aware of the literature around efficiently implementing AES and SM4 SBoxes in hardware.",non_CSR_parameter,enum,medium,False, +chunk_1eaa4ab0,src/vector-crypto.adoc,140,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Policies",The standard will not try to anticipate new useful low-level operations which may be useful as building blocks for future cryptographic constructs.,non_CSR_parameter,enum,medium,False, +chunk_7adc298c,src/vector-crypto.adoc,148,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Policies","Regarding side-channel countermeasures: Where relevant, proposed instructions must aim to remove the possibility of any timing side-channels.",non_CSR_parameter,enum,very_high,False, +chunk_c5ef14fa,src/vector-crypto.adoc,148,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Policies",All instructions shall be implemented with data-independent timing.,non_CSR_parameter,enum,very_high,False, +chunk_853aecc6,src/vector-crypto.adoc,148,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Policies","That is, the latency of the execution of these instructions shall not vary with different input values.",non_CSR_parameter,enum,very_high,False, +chunk_5d06aa19,src/vector-crypto.adoc,157,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Element Groups",Many vector crypto instructions operate on operands that are wider than elements (which are currently limited to 64 bits wide).,non_CSR_parameter,range,medium,False, +chunk_b66ad81b,src/vector-crypto.adoc,195,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Element Groups","As with all vector instructions, the number of elements processed is specified by the vector length `vl`.",CSR_controlled,enum,high,False, +chunk_de8729ff,src/vector-crypto.adoc,195,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Element Groups",The number of element groups operated upon is then `vl`/`EGS`.,CSR_controlled,enum,high,False, +chunk_d2bd3ffd,src/vector-crypto.adoc,195,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Element Groups",Likewise the starting element group is `vstart`/`EGS`.,CSR_controlled,enum,high,False, +chunk_cd2c84cc,src/vector-crypto.adoc,195,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Element Groups",See for limitations on `vl` and `vstart` for vector crypto instructions.,CSR_controlled,enum,high,False, +chunk_6fc87476,src/vector-crypto.adoc,219,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Instruction Constraints",Instructions that violate the `vl` or `vstart` requirements are reserved.,CSR_controlled,enum,high,False, +chunk_a8c17d39,src/vector-crypto.adoc,235,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Instruction Constraints","LMUL constraints:: For element-group instructions, `LMUL`*`VLEN` must always be at least as large as `EGW`, otherwise an illegal-instruction exception is raised, even if `vl`=0.",CSR_controlled,range,very_high,False, +chunk_356861ac,src/vector-crypto.adoc,275,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Instruction Constraints",The *Scalar Element Group* operand has `EMUL = ceil(EGW / VLEN)`.,CSR_controlled,enum,high,False, +chunk_ed9fc12d,src/vector-crypto.adoc,278,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Instruction Constraints","In the case of the `.vs` instructions defined in this specification, `vs2` holds a 128-bit scalar element group.",non_CSR_parameter,range,high,False, +chunk_72f4ea11,src/vector-crypto.adoc,278,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Instruction Constraints","For implementations with `VLEN` ≥ 128, `vs2` refers to a single register.",CSR_controlled,enum,high,False, +chunk_5b9da8d8,src/vector-crypto.adoc,278,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Instruction Constraints","Thus, the `vd` register group must not overlap the `vs2` register.",non_CSR_parameter,enum,very_high,False, +chunk_1ab1961e,src/vector-crypto.adoc,278,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Instruction Constraints","However, in implementations where `VLEN` < 128, `vs2` refers to a register group comprised of the number of registers needed to hold the 128-bit scalar element group.",CSR_controlled,range,high,False, +chunk_6b9467f4,src/vector-crypto.adoc,278,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Instruction Constraints","In this case, the `vd` register group must not overlap this `vs2` register group.",non_CSR_parameter,enum,very_high,False, +chunk_eb8c5660,src/vector-crypto.adoc,348,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Software Portability",The following contains some guidelines that enable the portability of vector-crypto-based code to implementations with different values for `VLEN`,CSR_controlled,enum,high,False, +chunk_e447ceef,src/vector-crypto.adoc,351,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Software Portability",Application Processors:: Application processors are expected to follow the V-extension and will therefore have `VLEN` {ge} 128.,CSR_controlled,enum,high,False, +chunk_bae02ff2,src/vector-crypto.adoc,359,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Software Portability","Implementations with `VLEN` = 128, require that `LMUL` is doubled for these instructions in order to create 256-bit elements across a pair of registers.",CSR_controlled,range,high,False, +chunk_dd6c9a77,src/vector-crypto.adoc,359,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Software Portability","Therefore, we recommend that libraries that implement SHA-512 and SM3 employ this doubling of `LMUL` to ensure that the software can run on all implementation with `VLEN` {ge} 128.",CSR_controlled,enum,high,False, +chunk_5aa7c4e2,src/vector-crypto.adoc,366,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Software Portability","While the doubling of `LMUL` for these instructions is safe for implementations with `VLEN` {ge} 256, it may be less optimal as it will result in unnecessary register pressure and might exact a performance penalty in some microarchitectures.",CSR_controlled,enum,high,False, +chunk_ff2c9b2a,src/vector-crypto.adoc,366,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Software Portability","Therefore, we suggest that in addition to providing portable code for SHA-512 and SM3, libraries should also include more optimal code for these instructions when `VLEN` {ge} 256. //",CSR_controlled,enum,high,False, +chunk_ffca5398,src/vector-crypto.adoc,372,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Software Portability",| | Algorithm | Instructions | VLEN | LMUL,CSR_controlled,enum,high,False, +chunk_c35595a7,src/vector-crypto.adoc,380,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Software Portability",| SHA-512 | vsha2* | 64 | vl/2 | SM3 | vsm3* | 32 | vl/4 |,CSR_controlled,enum,high,False, +chunk_f7e14b9d,src/vector-crypto.adoc,396,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Software Portability","On implementations with `VLEN` < 128, these scalar element groups will necessarily be formed across registers.",CSR_controlled,enum,high,False, +chunk_684726a3,src/vector-crypto.adoc,422,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview","If `Zve32x` is supported then `Zvkb` or `Zvbb` provide support for EEW of 8, 16, and 32.",unknown,unknown,high,False, +chunk_75a26ddf,src/vector-crypto.adoc,422,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview",If `Zve64x` is supported then `Zvkb` or `Zvbb` also add support for EEW 64.,unknown,unknown,high,False, +chunk_bb27d2de,src/vector-crypto.adoc,427,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview","All cryptography-specific instructions defined in this Vector Crypto specification (i.e., those in , , , and but not ,, or ) shall be executed with data-independent execution latency as defined in the .",non_CSR_parameter,enum,very_high,False, +chunk_fe57b73f,src/vector-crypto.adoc,434,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview","This specification includes a extension that, when implemented, requires certain vector instructions (including , , and ) to be executed with data-independent execution latency.",non_CSR_parameter,unknown,high,False, +chunk_ccc37ee9,src/vector-crypto.adoc,521,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvkg` - Vector GCM/GMAC",All of these instructions work on 128-bit element groups comprised of four 32-bit elements.,non_CSR_parameter,range,medium,False, +chunk_c1e1f6a7,src/vector-crypto.adoc,523,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvkg` - Vector GCM/GMAC","GHASH~H~ is defined in the // link:https://csrc.nist.gov/publications/detail/sp/800-38d/final[NIST Special Publication 800-38D] ""Recommendation for Block Cipher Modes of Operation: Galois/Counter Mode (GCM) and GMAC"" cite:[nist:gcm] (NIST Specification).",CSR_controlled,enum,high,False, +chunk_d533d724,src/vector-crypto.adoc,529,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvkg` - Vector GCM/GMAC","To help avoid side-channel timing attacks, these instructions shall be implemented with data-independent timing.",non_CSR_parameter,enum,very_high,False, +chunk_27440d37,src/vector-crypto.adoc,531,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvkg` - Vector GCM/GMAC","The number of element groups to be processed is `vl`/`EGS`. `vl` must be set to the number of `SEW=32` elements to be processed and therefore must be a multiple of `EGS=4`. + Likewise, `vstart` must be a multiple of `EGS=4`.",CSR_controlled,enum,very_high,False, +chunk_a241af1e,src/vector-crypto.adoc,560,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvkned` - NIST Suite: Vector AES Block Cipher",All of these instructions work on 128-bit element groups comprised of four 32-bit elements.,non_CSR_parameter,range,medium,False, +chunk_b910ad34,src/vector-crypto.adoc,563,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvkned` - NIST Suite: Vector AES Block Cipher","On systems with `VLEN`<128, element groups may be formed by concatenating 32-bit elements from two or four registers by using an LMUL =2 and LMUL=4 respectively.",CSR_controlled,range,high,False, +chunk_c4c3216d,src/vector-crypto.adoc,571,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvkned` - NIST Suite: Vector AES Block Cipher","To help avoid side-channel timing attacks, these instructions shall be implemented with data-independent timing.",non_CSR_parameter,enum,very_high,False, +chunk_391c8fd1,src/vector-crypto.adoc,573,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvkned` - NIST Suite: Vector AES Block Cipher","The number of element groups to be processed is `vl`/`EGS`. `vl` must be set to the number of `SEW=32` elements to be processed and therefore must be a multiple of `EGS=4`. + Likewise, `vstart` must be a multiple of `EGS=4`.",CSR_controlled,enum,very_high,False, +chunk_767310fa,src/vector-crypto.adoc,605,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvknh[ab]` - NIST Suite: Vector SHA-2 Secure Hash",SHA-256: these instructions work on 128-bit element groups comprised of four 32-bit elements. - SHA-512: these instructions work on 256-bit element groups comprised of four 64-bit elements.,non_CSR_parameter,range,medium,False, +chunk_516c21f1,src/vector-crypto.adoc,640,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvknh[ab]` - NIST Suite: Vector SHA-2 Secure Hash","To help avoid side-channel timing attacks, these instructions shall be implemented with data-independent timing.",non_CSR_parameter,enum,very_high,False, +chunk_e32644aa,src/vector-crypto.adoc,650,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvknh[ab]` - NIST Suite: Vector SHA-2 Secure Hash","The number of element groups to be processed is `vl`/`EGS`. `vl` must be set to the number of `SEW` elements to be processed and therefore must be a multiple of `EGS=4`. + Likewise, `vstart` must be a multiple of `EGS=4`.",CSR_controlled,enum,very_high,False, +chunk_fa1dcc0b,src/vector-crypto.adoc,687,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvksed` - ShangMi Suite: SM4 Block Cipher",All of these instructions work on 128-bit element groups comprised of four 32-bit elements.,non_CSR_parameter,range,medium,False, +chunk_441c4256,src/vector-crypto.adoc,694,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvksed` - ShangMi Suite: SM4 Block Cipher","To help avoid side-channel timing attacks, these instructions shall be implemented with data-independent timing.",non_CSR_parameter,enum,very_high,False, +chunk_1d39c544,src/vector-crypto.adoc,696,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvksed` - ShangMi Suite: SM4 Block Cipher","The number of element groups to be processed is `vl`/`EGS`. `vl` must be set to the number of `SEW=32` elements to be processed and therefore must be a multiple of `EGS=4`. + Likewise, `vstart` must be a multiple of `EGS=4`.",CSR_controlled,enum,very_high,False, +chunk_f8ef407b,src/vector-crypto.adoc,731,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvksh` - ShangMi Suite: SM3 Secure Hash",All of these instructions work on 256-bit element groups comprised of eight 32-bit elements.,non_CSR_parameter,range,medium,False, +chunk_81fcf466,src/vector-crypto.adoc,746,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvksh` - ShangMi Suite: SM3 Secure Hash","To help avoid side-channel timing attacks, these instructions shall be implemented with data-independent timing.",non_CSR_parameter,enum,very_high,False, +chunk_2715a8e8,src/vector-crypto.adoc,748,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvksh` - ShangMi Suite: SM3 Secure Hash","The number of element groups to be processed is `vl`/`EGS`. `vl` must be set to the number of `SEW=32` elements to be processed and therefore must be a multiple of `EGS=8`. + Likewise, `vstart` must be a multiple of `EGS=8`.",CSR_controlled,enum,very_high,False, +chunk_ccd0d1b5,src/vector-crypto.adoc,890,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvkt` - Vector Data-Independent Execution Latency","However, DIEL does not apply to other values such as vl, vtype, and the mask (when used to control execution of a masked vector instruction).",CSR_controlled,enum,high,False, +chunk_b1e1d28d,src/vector-crypto.adoc,1067,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesdf.[vv,vs]",This instruction must always be implemented such that its execution latency does not depend on the data being operated upon.,non_CSR_parameter,enum,very_high,False, +chunk_54cab962,src/vector-crypto.adoc,1072,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesdf.[vv,vs]","Operation:: [source,sail] -- function clause execute (VAESDF(vs2, vd, suffix)) = { if(LMUL*VLEN < EGW) then { handleillegal(); // illegal-instruction exception RETIREFAIL } else {",CSR_controlled,enum,high,False, +chunk_77c26fc3,src/vector-crypto.adoc,1084,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesdf.[vv,vs]","foreach (i from egstart to eglen-1) { let keyelem = if suffix ""vv"" then i else 0; let state : bits(128) = getvelem(vd, EGW=128, i); let rkey : bits(128) = getvelem(vs2, EGW=128, keyelem); let sr : bits(128) = aesshiftrowsinv(state); let sb : bits(128) = aessubbytesinv(sr); let ark : bits(128) = sb ^ rkey; setvelem(vd, EGW=128, i, ark); } RETIRESUCCESS } } --",unknown,unknown,high,False, +chunk_b0bd5069,src/vector-crypto.adoc,1169,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesdm.[vv,vs]","This instruction must always be implemented such that its execution latency does not depend on the data being operated upon. // // The number of element groups to be processed is `vl`/`EGS`. // `vl` must be set to the number of `SEW=32` elements to be processed and // therefore must be a multiple of `EGS=4`. + // Likewise, `vstart` must be a multiple of `EGS=4`.",CSR_controlled,enum,very_high,False, +chunk_c0f4cdd4,src/vector-crypto.adoc,1177,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesdm.[vv,vs]","Operation:: [source,sail] -- function clause execute (VAESDM(vs2, vd, suffix)) = { if(LMUL*VLEN < EGW) then { handleillegal(); // illegal-instruction exception RETIREFAIL } else {",CSR_controlled,enum,high,False, +chunk_e2fbb825,src/vector-crypto.adoc,1189,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesdm.[vv,vs]","foreach (i from egstart to eglen-1) { let keyelem = if suffix ""vv"" then i else 0; let state : bits(128) = getvelem(vd, EGW=128, i); let rkey : bits(128) = getvelem(vs2, EGW=128, keyelem); let sr : bits(128) = aesshiftrowsinv(state); let sb : bits(128) = aessubbytesinv(sr); let ark : bits(128) = sb ^ rkey; let mix : bits(128) = aesmixcolumnsinv(ark); setvelem(vd, EGW=128, i, mix); } RETIRESUCCESS } } --",unknown,unknown,high,False, +chunk_698591a0,src/vector-crypto.adoc,1274,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesef.[vv,vs]","This instruction must always be implemented such that its execution latency does not depend on the data being operated upon. // // The number of element groups to be processed is `vl`/`EGS`. // `vl` must be set to the number of `SEW=32` elements to be processed and // therefore must be a multiple of `EGS=4`. + // Likewise, `vstart` must be a multiple of `EGS=4`.",CSR_controlled,enum,very_high,False, +chunk_07a088e2,src/vector-crypto.adoc,1282,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesef.[vv,vs]","Operation:: [source,sail] -- function clause execute (VAESEF(vs2, vd, suffix) = { if(LMUL*VLEN < EGW) then { handleillegal(); // illegal-instruction exception RETIREFAIL } else {",CSR_controlled,enum,high,False, +chunk_d8eba26e,src/vector-crypto.adoc,1294,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesef.[vv,vs]","foreach (i from egstart to eglen-1) { let keyelem = if suffix ""vv"" then i else 0; let state : bits(128) = getvelem(vd, EGW=128, i); let rkey : bits(128) = getvelem(vs2, EGW=128, keyelem); let sb : bits(128) = aessubbytesfwd(state); let sr : bits(128) = aesshiftrowsfwd(sb); let ark : bits(128) = sr ^ rkey; setvelem(vd, EGW=128, i, ark); } RETIRESUCCESS } } --",unknown,unknown,high,False, +chunk_2fc0ff0c,src/vector-crypto.adoc,1379,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesem.[vv,vs]","This instruction must always be implemented such that its execution latency does not depend on the data being operated upon. // // The number of element groups to be processed is `vl`/`EGS`. // `vl` must be set to the number of `SEW=32` elements to be processed and // therefore must be a multiple of `EGS=4`. + // Likewise, `vstart` must be a multiple of `EGS=4`.",CSR_controlled,enum,very_high,False, +chunk_242ff693,src/vector-crypto.adoc,1387,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesem.[vv,vs]","Operation:: [source,sail] -- function clause execute (VAESEM(vs2, vd, suffix)) = { if(LMUL*VLEN < EGW) then { handleillegal(); // illegal-instruction exception RETIREFAIL } else {",CSR_controlled,enum,high,False, +chunk_d5b261d1,src/vector-crypto.adoc,1399,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesem.[vv,vs]","foreach (i from egstart to eglen-1) { let keyelem = if suffix ""vv"" then i else 0; let state : bits(128) = getvelem(vd, EGW=128, i); let rkey : bits(128) = getvelem(vs2, EGW=128, keyelem); let sb : bits(128) = aessubbytesfwd(state); let sr : bits(128) = aesshiftrowsfwd(sb); let mix : bits(128) = aesmixcolumnsfwd(sr); let ark : bits(128) = mix ^ rkey; setvelem(vd, EGW=128, i, ark); } RETIRESUCCESS } } --",unknown,unknown,high,False, +chunk_f5ec64b6,src/vector-crypto.adoc,1479,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaeskf1.vi",This instruction must always be implemented such that its execution latency does not depend on the data being operated upon.,non_CSR_parameter,enum,very_high,False, +chunk_3778f1de,src/vector-crypto.adoc,1491,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaeskf1.vi","Operation:: [source,Sail] -- function clause execute (VAESKF1(rnd, vd, vs2)) = { if(LMUL*VLEN < EGW) then { handleillegal(); // illegal-instruction exception RETIREFAIL } else {",CSR_controlled,enum,high,False, +chunk_d4bb108c,src/vector-crypto.adoc,1589,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaeskf2.vi",This instruction must always be implemented such that its execution latency does not depend on the data being operated upon.,non_CSR_parameter,enum,very_high,False, +chunk_fbc5a5e2,src/vector-crypto.adoc,1599,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaeskf2.vi","Operation:: [source,Sail] -- function clause execute (VAESKF2(rnd, vd, vs2)) = { if(LMUL*VLEN < EGW) then { handleillegal(); // illegal-instruction exception RETIREFAIL } else {",CSR_controlled,enum,high,False, +chunk_81b48b9a,src/vector-crypto.adoc,1690,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesz.vs",This instruction must always be implemented such that its execution latency does not depend on the data being operated upon.,non_CSR_parameter,enum,very_high,False, +chunk_639eb033,src/vector-crypto.adoc,1699,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesz.vs","Operation:: [source,sail] -- function clause execute (VAESZ(vs2, vd) = { if(((vstart%EGS)<>0) | (LMUL*VLEN < EGW)) then { handleillegal(); // illegal-instruction exception RETIREFAIL } else {",CSR_controlled,enum,high,False, +chunk_3b7e5c6a,src/vector-crypto.adoc,1796,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vandn.[vv,vx]","In the vector-scalar version, `Op1` is the sign-extended or truncated value in scalar register `rs1`.",unknown,enum,high,False, +chunk_ea6fad60,src/vector-crypto.adoc,1812,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vandn.[vv,vx]","Operation:: [source,sail] -- function clause execute (VANDN(vs2, vs1, vd, suffix)) = { foreach (i from vstart to vl-1) { let op1 = match suffix { ""vv"" => getvelem(vs1, SEW, i), ""vx"" => sextortruncatetosew(X(vs1)) }; let op2 = getvelem(vs2, SEW, i); setvelem(vd, EEW=SEW, i, ~op1 & op2); } RETIRESUCCESS }",CSR_controlled,enum,high,False, +chunk_858684d8,src/vector-crypto.adoc,2016,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vclmul.[vv,vx]","Each 64-bit element in the `vs2` vector register is carry-less multiplied by either each 64-bit element in `vs1` (vector-vector), or the 64-bit value from integer register `rs1` (vector-scalar).",non_CSR_parameter,range,medium,False, +chunk_f11d9371,src/vector-crypto.adoc,2027,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vclmul.[vv,vx]","foreach (i from vstart to vl-1) { let op1 : bits (64) = if suffix ""vv"" then getvelem(vs1,i) else zextortruncatetosew(X(vs1)); let op2 : bits (64) = getvelem(vs2,i); let product : bits (64) = clmul(op1,op2,SEW); setvelem(vd, i, product); } RETIRESUCCESS }",CSR_controlled,enum,high,False, +chunk_2d8ad53a,src/vector-crypto.adoc,2109,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vclmulh.[vv,vx]","Each 64-bit element in the `vs2` vector register is carry-less multiplied by either each 64-bit element in `vs1` (vector-vector), or the 64-bit value from integer register `rs1` (vector-scalar).",non_CSR_parameter,range,medium,False, +chunk_58fedcc1,src/vector-crypto.adoc,2122,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vclmulh.[vv,vx]","foreach (i from vstart to vl-1) { let op1 : bits (64) = if suffix ""vv"" then getvelem(vs1,i) else zextortruncatetosew(X(vs1)); let op2 : bits (64) = getvelem(vs2, i); let product : bits (64) = clmulh(op1, op2, SEW); setvelem(vd, i, product); } RETIRESUCCESS }",CSR_controlled,enum,high,False, +chunk_0d45ecd1,src/vector-crypto.adoc,2179,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vclz.v",| Vs2 | input | Input elements | Vd | output | Count of leading zero bits |,unknown,unknown,high,False, +chunk_932db4e6,src/vector-crypto.adoc,2193,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vclz.v","foreach (i from vstart to vl-1) { let input = getvelem(vs2, SEW, i); for (j = (SEW - 1); j >= 0; j--) if [input[j]] 0b1 then break; setvelem(vd, SEW, i, SEW - 1 - j) } RETIRESUCCESS } --",CSR_controlled,enum,high,False, +chunk_c998a2a3,src/vector-crypto.adoc,2296,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vctz.v",| Vs2 | input | Input elements | Vd | output | Count of trailing zero bits |,unknown,unknown,high,False, +chunk_28ae0776,src/vector-crypto.adoc,2310,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vctz.v","foreach (i from vstart to vl-1) { let input = getvelem(vs2, SEW, i); for (j = 0; j < SEW; j++) if [input[j]] 0b1 then break; setvelem(vd, SEW, i, j) } RETIRESUCCESS } --",CSR_controlled,enum,high,False, +chunk_822e0943,src/vector-crypto.adoc,2371,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vghsh.vv",This instruction treats all of the inputs and outputs as 128-bit polynomials and performs operations over GF[2].,non_CSR_parameter,range,medium,False, +chunk_06125fe7,src/vector-crypto.adoc,2377,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vghsh.vv",The multiplication over GF(2^128^) is a carry-less multiply of two 128-bit polynomials modulo GHASH's irreducible polynomial (x^128^ + x^7^ + x^2^ + x + 1).,non_CSR_parameter,range,medium,False, +chunk_3ca24c25,src/vector-crypto.adoc,2391,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vghsh.vv",This instruction must always be implemented such that its execution latency does not depend on the data being operated upon.,non_CSR_parameter,enum,very_high,False, +chunk_4ed2f790,src/vector-crypto.adoc,2416,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vghsh.vv",for (int bit = 0; bit < 128; bit++) { if bittobool(S[bit]) Z ^= H,unknown,unknown,high,False, +chunk_9de0270b,src/vector-crypto.adoc,2420,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vghsh.vv",bool reduce = bittobool(H[127]); H = H << 1; // left shift H by 1 if (reduce) H ^= 0x87; // Reduce using x^7 + x^2 + x^1 + 1 polynomial },unknown,unknown,high,False, +chunk_9dc6eb59,src/vector-crypto.adoc,2484,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vgmul.vv",This instruction treats all of the inputs and outputs as 128-bit polynomials and performs operations over GF[2].,non_CSR_parameter,range,medium,False, +chunk_a0947dcb,src/vector-crypto.adoc,2484,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vgmul.vv",It produces the product over GF(2^128^) of the two 128-bit inputs.,non_CSR_parameter,range,medium,False, +chunk_4b8602f0,src/vector-crypto.adoc,2488,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vgmul.vv",The multiplication over GF(2^128^) is a carry-less multiply of two 128-bit polynomials modulo GHASH's irreducible polynomial (x^128^ + x^7^ + x^2^ + x + 1).,non_CSR_parameter,range,medium,False, +chunk_ff885a1c,src/vector-crypto.adoc,2498,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vgmul.vv",This instruction must always be implemented such that its execution latency does not depend on the data being operated upon.,non_CSR_parameter,enum,very_high,False, +chunk_3782b992,src/vector-crypto.adoc,2519,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vgmul.vv",for (int bit = 0; bit < 128; bit++) { if bittobool(Y[bit]) Z ^= H,unknown,unknown,high,False, +chunk_82803ec7,src/vector-crypto.adoc,2523,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vgmul.vv",bool reduce = bittobool(H[127]); H = H << 1; // left shift H by 1 if (reduce) H ^= 0x87; // Reduce using x^7 + x^2 + x^1 + 1 polynomial },unknown,unknown,high,False, +chunk_2a537f4c,src/vector-crypto.adoc,2585,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vrev8.v","Operation:: [source,sail] -- function clause execute (VREV8(vs2)) = { foreach (i from vstart to vl-1) { input = getvelem(vs2, SEW, i); let output : SEW = 0; let j = SEW - 1; foreach (k from 0 to (SEW - 8) by 8) { output[k..(k + 7)] = input[(j - 7)..j]; j = j - 8; setvelem(vd, SEW, i, output) } RETIRESUCCESS } --",CSR_controlled,enum,high,False, +chunk_4c28def4,src/vector-crypto.adoc,2686,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vrol.[vv,vx]","Operation:: [source,sail] -- function clause execute (VROLVV(vs2, vs1, vd)) = { foreach (i from vstart to vl - 1) { setvelem(vd, EEW=SEW, i, getvelem(vs2, i) <<< (getvelem(vs1, i) & (SEW-1)) ) } RETIRESUCCESS }",CSR_controlled,enum,high,False, +chunk_1a7d2a0d,src/vector-crypto.adoc,2698,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vrol.[vv,vx]","function clause execute (VROLVX(vs2, rs1, vd)) = { foreach (i from vstart to vl - 1) { setvelem(vd, EEW=SEW, i, getvelem(vs2, i) <<< (X(rs1) & (SEW-1)) ) } RETIRESUCCESS }",CSR_controlled,enum,high,False, +chunk_f5f6efb4,src/vector-crypto.adoc,2809,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vror.[vv,vx,vi]","Operation:: [source,sail] -- function clause execute (VRORVV(vs2, vs1, vd)) = { foreach (i from vstart to vl - 1) { setvelem(vd, EEW=SEW, i, getvelem(vs2, i) >>> (getvelem(vs1, i) & (SEW-1)) ) } RETIRESUCCESS }",CSR_controlled,enum,high,False, +chunk_52fd3c99,src/vector-crypto.adoc,2821,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vror.[vv,vx,vi]","function clause execute (VRORVX(vs2, rs1, vd)) = { foreach (i from vstart to vl - 1) { setvelem(vd, EEW=SEW, i, getvelem(vs2, i) >>> (X(rs1) & (SEW-1)) ) } RETIRESUCCESS }",CSR_controlled,enum,high,False, +chunk_e59bc2cf,src/vector-crypto.adoc,2830,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vror.[vv,vx,vi]","function clause execute (VRORVI(vs2, uimm[5:0], vd)) = { foreach (i from vstart to vl - 1) { setvelem(vd, EEW=SEW, i, getvelem(vs2, i) >>> (uimm[5:0] & (SEW-1)) ) } RETIRESUCCESS } --",CSR_controlled,enum,high,False, +chunk_3a7f24b8,src/vector-crypto.adoc,2911,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsha2c[hl].vv",Two words of `vs1` are processed with the 8 words of current state held in `vd` and `vs2` to perform two rounds of hash computation producing four words of the next state.,non_CSR_parameter,range,medium,False, +chunk_8a14d441,src/vector-crypto.adoc,2965,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsha2c[hl].vv","Operation:: [source,sail] -- function clause execute (VSHA2c(vs2, vs1, vd)) = { if(LMUL*VLEN < EGW) then { handleillegal(); // illegal-instruction exception RETIREFAIL } else {",CSR_controlled,enum,high,False, +chunk_d8a05b31,src/vector-crypto.adoc,3165,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsha2ms.vv","Operation:: [source,sail] -- function clause execute (VSHA2ms(vs2, vs1, vd)) = { // SEW32 = SHA-256 // SEW64 = SHA-512 if(LMUL*VLEN < EGW) then { handleillegal(); // illegal-instruction exception RETIREFAIL } else {",CSR_controlled,enum,high,False, +chunk_fb584b00,src/vector-crypto.adoc,3266,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm3c.vi",The current state of eight 32-bit words is read in as an element group from `vd`.,non_CSR_parameter,range,medium,False, +chunk_13a309c8,src/vector-crypto.adoc,3266,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm3c.vi","Eight 32-bit message words are read in as an element group from `vs2`, although only four of them are used.",non_CSR_parameter,range,medium,False, +chunk_ad5dc774,src/vector-crypto.adoc,3266,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm3c.vi",All of the 32-bit input words are byte-swapped from big endian to little endian.,non_CSR_parameter,range,medium,False, +chunk_e96e140e,src/vector-crypto.adoc,3266,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm3c.vi","These inputs are processed somewhat differently based on the round group (as specified in rnds), and the next state is generated as an element group of eight 32-bit words.",non_CSR_parameter,range,medium,False, +chunk_d06fa038,src/vector-crypto.adoc,3266,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm3c.vi","The next state of eight 32-bit words are generated, swapped from little endian to big endian, and are returned in an eight-element group.",non_CSR_parameter,range,medium,False, +chunk_46e1371f,src/vector-crypto.adoc,3275,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm3c.vi",The round number is provided by the 5-bit `rnds` unsigned immediate.,non_CSR_parameter,range,high,False, +chunk_21e22715,src/vector-crypto.adoc,3297,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm3c.vi","Operation:: [source,sail] -- function clause execute (VSM3C(rnds, vs2, vd)) = { if(LMUL*VLEN < EGW) then { handleillegal(); // illegal-instruction exception RETIREFAIL } else {",CSR_controlled,enum,high,False, +chunk_9d1208b0,src/vector-crypto.adoc,3439,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm3me.vv",The sixteen most recent 32-bit message words are read in as two eight-element groups from `vs1` and `vs2`.,non_CSR_parameter,range,medium,False, +chunk_d0a40012,src/vector-crypto.adoc,3439,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm3me.vv","The next eight 32-bit message words are generated, swapped from little endian to big endian, and are returned in an eight-element group.",non_CSR_parameter,range,medium,False, +chunk_14b808ca,src/vector-crypto.adoc,3458,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm3me.vv","Operation:: [source,sail] -- function clause execute (VSM3ME(vs2, vs1)) = { if(LMUL*VLEN < EGW) then { handleillegal(); // illegal-instruction exception RETIREFAIL } else {",CSR_controlled,enum,high,False, +chunk_6a9ee2b1,src/vector-crypto.adoc,3661,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm4k.vi","function clause execute (vsm4k(uimm, vs2)) = { if(LMUL*VLEN < EGW) then { handleillegal(); // illegal-instruction exception RETIREFAIL } else {",CSR_controlled,enum,high,False, +chunk_be5fae05,src/vector-crypto.adoc,3807,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm4r.[vv,vs]","Operation:: [source,pseudocode] -- function clause execute (VSM4R(vd, vs2)) = { if(LMUL*VLEN < EGW) then { handleillegal(); // illegal-instruction exception RETIREFAIL } else {",CSR_controlled,enum,high,False, +chunk_f7f97d23,src/vector-crypto.adoc,3836,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm4r.[vv,vs]","foreach (i from egstart to eglen-1) { keyelem = if suffix ""vv"" then i else 0; {rk3 @ rk2 @ rk1 @ rk0} : bits(128) = getvelem(vs2, EGW=128, keyelem); {x3 @ x2 @ x1 @ x0} : bits(128) = getvelem(vd, EGW=128, i);",unknown,unknown,high,False, +chunk_e4b62a77,src/vector-crypto.adoc,3960,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vwsll.[vv,vx,vi]","The elements in `vs2` are zero-extended to 2*`SEW` bits, then shifted left by the shift amount specified by either the corresponding elements of `vs1` (vector-vector), integer register `rs1` (vector-scalar), or an immediate value (vector-immediate).",unknown,enum,high,False, +chunk_4611802a,src/vector-crypto.adoc,3967,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vwsll.[vv,vx,vi]","Operation:: [source,sail] -- function clause execute (VWSLLVV(vs2, vs1, vd)) = { foreach (i from vstart to vl - 1) { setvelem(vd, EEW=2*SEW, i, getvelem(vs2, i) << (getvelem(vs1, i) & ((2*SEW)-1)) ) } RETIRESUCCESS }",CSR_controlled,enum,high,False, +chunk_074c75bf,src/vector-crypto.adoc,3979,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vwsll.[vv,vx,vi]","function clause execute (VWSLLVX(vs2, rs1, vd)) = { foreach (i from vstart to vl - 1) { setvelem(vd, EEW=2*SEW, i, getvelem(vs2, i) << (X(rs1) & ((2*SEW)-1)) ) } RETIRESUCCESS }",CSR_controlled,enum,high,False, +chunk_2ec7e2d8,src/vector-crypto.adoc,3988,"Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vwsll.[vv,vx,vi]","function clause execute (VWSLLVI(vs2, uimm[4:0], vd)) = { foreach (i from vstart to vl - 1) { setvelem(vd, EEW=2*SEW, i, getvelem(vs2, i) << (uimm[4:0] & ((2*SEW)-1)) ) } RETIRESUCCESS } --",CSR_controlled,enum,high,False, diff --git a/tools/llm-extraction/data/output/raw_chunks/src__b-st-ext.json b/tools/llm-extraction/data/output/raw_chunks/src__b-st-ext.json new file mode 100644 index 0000000000..5e29237f4d --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__b-st-ext.json @@ -0,0 +1,4734 @@ +{ + "source_file": "src/b-st-ext.adoc", + "total": 591, + "sentences": [ + { + "text": "The bit-manipulation (bitmanip) extension collection is comprised of several component extensions to the base RISC-V architecture that are intended to provide some combination of code-size reduction, performance improvement, and energy reduction.", + "section": "Preamble > Bit Manipulation Extensions", + "line_range": [ + 3, + 5 + ] + }, + { + "text": "While the instructions are intended for general use, some instructions are more useful in certain domains than in others.", + "section": "Preamble > Bit Manipulation Extensions", + "line_range": [ + 3, + 5 + ] + }, + { + "text": "Hence, several smaller bitmanip extensions are provided.", + "section": "Preamble > Bit Manipulation Extensions", + "line_range": [ + 3, + 5 + ] + }, + { + "text": "Each of these smaller extensions is grouped by common function and use case, and each has its own Zb*-extension name.", + "section": "Preamble > Bit Manipulation Extensions", + "line_range": [ + 3, + 5 + ] + }, + { + "text": "Each bitmanip extension includes a group of several bitmanip instructions that have similar purposes and can often share the same logic.", + "section": "Preamble > Bit Manipulation Extensions", + "line_range": [ + 7, + 9 + ] + }, + { + "text": "Some instructions are available in only one extension, while others are available in several.", + "section": "Preamble > Bit Manipulation Extensions", + "line_range": [ + 7, + 9 + ] + }, + { + "text": "The instructions have mnemonics and encodings that are independent of the extensions in which they appear.", + "section": "Preamble > Bit Manipulation Extensions", + "line_range": [ + 7, + 9 + ] + }, + { + "text": "Thus, when implementing extensions with overlapping instructions, there is no redundancy in logic or encoding.", + "section": "Preamble > Bit Manipulation Extensions", + "line_range": [ + 7, + 9 + ] + }, + { + "text": "The bitmanip extensions are defined for RV32 and RV64.", + "section": "Preamble > Bit Manipulation Extensions", + "line_range": [ + 11, + 11 + ] + }, + { + "text": "The bitmanip extension follows the convention in RV64 that w-suffixed instructions (without a dot before the w) ignore the upper 32 bits of their inputs, operate on the least-significant 32 bits as signed values, and produce a 32-bit signed result that is sign-extended to XLEN.", + "section": "Preamble > Bit Manipulation Extensions", + "line_range": [ + 13, + 13 + ] + }, + { + "text": "Bitmanip instructions with the suffix .uw have one operand that is an unsigned 32-bit value that is extracted from the least-significant 32 bits of the specified register.", + "section": "Preamble > Bit Manipulation Extensions", + "line_range": [ + 15, + 15 + ] + }, + { + "text": "Other than that, these perform full-XLEN operations.", + "section": "Preamble > Bit Manipulation Extensions", + "line_range": [ + 15, + 15 + ] + }, + { + "text": "Bitmanip instructions with the suffixes .b, .h, and .w only look at the least-significant 8 bits, 16 bits, and 32 bits of the input (respectively) and produce an XLEN-wide result that is sign-extended or zero-extended, based on the specific instruction.", + "section": "Preamble > Bit Manipulation Extensions", + "line_range": [ + 17, + 17 + ] + }, + { + "text": "The bit-manipulation instructions comprise the following extensions:", + "section": "Preamble > Bit Manipulation Extensions", + "line_range": [ + 19, + 19 + ] + }, + { + "text": "Zba: * Zbb: ext:zbb[] * Zbs: * Zbc: * Zbkb: * Zbkc: * Zbkx:", + "section": "Preamble > Bit Manipulation Extensions", + "line_range": [ + 21, + 27 + ] + }, + { + "text": "Below is a list of all of the instructions that are included in these extensions, along with their specific mapping:", + "section": "Preamble > Bit Manipulation Extensions", + "line_range": [ + 29, + 30 + ] + }, + { + "text": "| |RV32 |RV64 |Mnemonic |Instruction |Zbb |Zbkb |Zbc |Zbkc |{check}|{check}|andn rd, rs1, rs2 | |{check}|{check}| | |{check}|{check}|brev8 rd, rs | | |{check}| | |{check}|{check}|clmul rd, rs1, rs2 | | | |{check}|{check} |{check}|{check}|clmulh rd, rs1, rs2 | | | |{check}|{check} |{check}|{check}|clmulr rd, rs1, rs2 | | | |{check}| |{check}|{check}|clz rd, rs | |{check}| | | | |{check}|clzw rd, rs | |{check}| | | |{check}|{check}|cpop rd, rs | |{check}| | | | |{check}|cpopw rd, rs | |{check}| | | |{check}|{check}|ctz rd, rs | |{check}| | | | |{check}|ctzw rd, rs | |{check}| | | |{check}|{check}|max rd, rs1, rs2 | |{check}| | | |{check}|{check}|maxu rd, rs1, rs2 | |{check}| | | |{check}|{check}|min rd, rs1, rs2 | |{check}| | | |{check}|{check}|minu rd, rs1, rs2 | |{check}| | | |{check}|{check}|orc.b rd, rs | |{check}| | | |{check}|{check}|orn rd, rs1, rs2 | |{check}|{check}| | |{check}|{check}|pack rd, rs1, rs2 | | |{check}| | |{check}|{check}|packh rd, rs1, rs2 | | |{check}| | | |{check}|packw rd, rs1, rs2 | | |{check}| | |{check}|{check}|rev8 rd, rs | |{check}|{check}| | |{check}|{check}|rol rd, rs1, rs2 | |{check}|{check}| | | |{check}|rolw rd, rs1, rs2 | |{check}|{check}| | |{check}|{check}|ror rd, rs1, rs2 | |{check}|{check}| | |{check}|{check}|rori rd, rs1, shamt | |{check}|{check}| | | |{check}|roriw rd, rs1, shamt| |{check}|{check}| | | |{check}|rorw rd, rs1, rs2 | |{check}|{check}| | |{check}|{check}|sext.b rd, rs | |{check}| | | |{check}|{check}|sext.h rd, rs | |{check}| | | |{check}| |unzip rd, rs | | |{check}| | |{check}|{check}|xnor rd, rs1, rs2 | |{check}|{check}| | |{check}|{check}|zext.h rd, rs | |{check}| | | |{check}| |zip rd, rs | | |{check}| | |", + "section": "Preamble > Bit Manipulation Extensions", + "line_range": [ + 32, + 68 + ] + }, + { + "text": "| |RV32 |RV64 |Mnemonic |Instruction |Zba |Zbs | |{check}|add.uw rd, rs1, rs2 | |{check}| |{check}|{check}|bclr rd, rs1, rs2 | | |{check} |{check}|{check}|bclri rd, rs1, imm | | |{check} |{check}|{check}|bext rd, rs1, rs2 | | |{check} |{check}|{check}|bexti rd, rs1, imm | | |{check} |{check}|{check}|binv rd, rs1, rs2 | | |{check} |{check}|{check}|binvi rd, rs1, imm | | |{check} |{check}|{check}|bset rd, rs1, rs2 | | |{check} |{check}|{check}|bseti rd, rs1, imm | | |{check} |{check}|{check}|sh1add rd, rs1, rs2 | |{check}| | |{check}|sh1add.uw rd, rs1, rs2||{check}| |{check}|{check}|sh2add rd, rs1, rs2 | |{check}| | |{check}|sh2add.uw rd, rs1, rs2||{check}| |{check}|{check}|sh3add rd, rs1, rs2 | |{check}| | |{check}|sh3add.uw rd, rs1, rs2||{check}| | |{check}|slli.uw rd, rs1, imm | |{check}| |", + "section": "Preamble > Bit Manipulation Extensions", + "line_range": [ + 70, + 89 + ] + }, + { + "text": "The B standard extension comprises instructions provided by the Zba, Zbb, and Zbs extensions.", + "section": "Preamble > Bit Manipulation Extensions > \"B\" Extension for Bit Manipulation, Version 1.0.0", + "line_range": [ + 93, + 94 + ] + }, + { + "text": "[zba,reftext=Address generation instructions]", + "section": "Preamble > Bit Manipulation Extensions > \"B\" Extension for Bit Manipulation, Version 1.0.0", + "line_range": [ + 96, + 96 + ] + }, + { + "text": "The Zba instructions can be used to accelerate the generation of addresses that index into arrays of basic types (halfword, word, doubleword) using both unsigned word-sized and XLEN-sized indices: a shifted index is added to a base address.", + "section": "Preamble > Bit Manipulation Extensions > Zba: Extension for Address generation, Version 1.0.0", + "line_range": [ + 98, + 98 + ] + }, + { + "text": "The shift and add instructions do a left shift of 1, 2, or 3 because these are commonly found in real-world code and because they can be implemented with a minimal amount of additional hardware beyond that of the simple adder.", + "section": "Preamble > Bit Manipulation Extensions > Zba: Extension for Address generation, Version 1.0.0", + "line_range": [ + 100, + 100 + ] + }, + { + "text": "This avoids lengthening the critical path in implementations.", + "section": "Preamble > Bit Manipulation Extensions > Zba: Extension for Address generation, Version 1.0.0", + "line_range": [ + 100, + 100 + ] + }, + { + "text": "While the shift and add instructions are limited to a maximum left shift of 3, the slli instruction (from the base ISA) can be used to perform similar shifts for indexing into arrays of wider elements.", + "section": "Preamble > Bit Manipulation Extensions > Zba: Extension for Address generation, Version 1.0.0", + "line_range": [ + 102, + 102 + ] + }, + { + "text": "The slli.uw -- added in this extension -- can be used when the index is to be interpreted as an unsigned word.", + "section": "Preamble > Bit Manipulation Extensions > Zba: Extension for Address generation, Version 1.0.0", + "line_range": [ + 102, + 102 + ] + }, + { + "text": "The following instructions comprise the Zba extension:", + "section": "Preamble > Bit Manipulation Extensions > Zba: Extension for Address generation, Version 1.0.0", + "line_range": [ + 104, + 104 + ] + }, + { + "text": "| |RV32 |RV64 |Mnemonic |Instruction", + "section": "Preamble > Bit Manipulation Extensions > Zba: Extension for Address generation, Version 1.0.0", + "line_range": [ + 106, + 111 + ] + }, + { + "text": "| |{check} |add.uw rd, rs1, rs2 |", + "section": "Preamble > Bit Manipulation Extensions > Zba: Extension for Address generation, Version 1.0.0", + "line_range": [ + 113, + 116 + ] + }, + { + "text": "|{check} |{check} |sh1add rd, rs1, rs2 |", + "section": "Preamble > Bit Manipulation Extensions > Zba: Extension for Address generation, Version 1.0.0", + "line_range": [ + 118, + 121 + ] + }, + { + "text": "| |{check} |sh1add.uw rd, rs1, rs2 |", + "section": "Preamble > Bit Manipulation Extensions > Zba: Extension for Address generation, Version 1.0.0", + "line_range": [ + 123, + 126 + ] + }, + { + "text": "|{check} |{check} |sh2add rd, rs1, rs2 |", + "section": "Preamble > Bit Manipulation Extensions > Zba: Extension for Address generation, Version 1.0.0", + "line_range": [ + 128, + 131 + ] + }, + { + "text": "| |{check} |sh2add.uw rd, rs1, rs2 |", + "section": "Preamble > Bit Manipulation Extensions > Zba: Extension for Address generation, Version 1.0.0", + "line_range": [ + 133, + 136 + ] + }, + { + "text": "|{check} |{check} |sh3add rd, rs1, rs2 |", + "section": "Preamble > Bit Manipulation Extensions > Zba: Extension for Address generation, Version 1.0.0", + "line_range": [ + 138, + 141 + ] + }, + { + "text": "| |{check} |sh3add.uw rd, rs1, rs2 |", + "section": "Preamble > Bit Manipulation Extensions > Zba: Extension for Address generation, Version 1.0.0", + "line_range": [ + 143, + 146 + ] + }, + { + "text": "| |{check} |slli.uw rd, rs1, imm |", + "section": "Preamble > Bit Manipulation Extensions > Zba: Extension for Address generation, Version 1.0.0", + "line_range": [ + 148, + 151 + ] + }, + { + "text": "| |RV32 |RV64 |Mnemonic |Instruction", + "section": "Preamble > Bit Manipulation Extensions > ext:zbb[] Extension for Basic bit-manipulation, Version 1.0.0 > Logical with negate", + "line_range": [ + 160, + 165 + ] + }, + { + "text": "|{check} |{check} |andn rd, rs1, rs2 |", + "section": "Preamble > Bit Manipulation Extensions > ext:zbb[] Extension for Basic bit-manipulation, Version 1.0.0 > Logical with negate", + "line_range": [ + 167, + 170 + ] + }, + { + "text": "|{check} |{check} |orn rd, rs1, rs2 |", + "section": "Preamble > Bit Manipulation Extensions > ext:zbb[] Extension for Basic bit-manipulation, Version 1.0.0 > Logical with negate", + "line_range": [ + 172, + 175 + ] + }, + { + "text": "|{check} |{check} |xnor rd, rs1, rs2 | |", + "section": "Preamble > Bit Manipulation Extensions > ext:zbb[] Extension for Basic bit-manipulation, Version 1.0.0 > Logical with negate", + "line_range": [ + 177, + 181 + ] + }, + { + "text": ".Implementation Hint [NOTE, caption=\"Imp\" ] The Logical with Negate instructions can be implemented by inverting the rs2 inputs to the base-required AND, OR, and XOR logic instructions.", + "section": "Preamble > Bit Manipulation Extensions > ext:zbb[] Extension for Basic bit-manipulation, Version 1.0.0 > Logical with negate", + "line_range": [ + 183, + 188 + ] + }, + { + "text": "In some implementations, the inverter on rs2 used for subtraction can be reused for this purpose.", + "section": "Preamble > Bit Manipulation Extensions > ext:zbb[] Extension for Basic bit-manipulation, Version 1.0.0 > Logical with negate", + "line_range": [ + 183, + 188 + ] + }, + { + "text": "| |RV32 |RV64 |Mnemonic |Instruction", + "section": "Preamble > Bit Manipulation Extensions > ext:zbb[] Extension for Basic bit-manipulation, Version 1.0.0 > Count leading/trailing zero bits", + "line_range": [ + 192, + 197 + ] + }, + { + "text": "|{check} |{check} |clz rd, rs |", + "section": "Preamble > Bit Manipulation Extensions > ext:zbb[] Extension for Basic bit-manipulation, Version 1.0.0 > Count leading/trailing zero bits", + "line_range": [ + 199, + 202 + ] + }, + { + "text": "|{check} |{check} |ctz rd, rs |", + "section": "Preamble > Bit Manipulation Extensions > ext:zbb[] Extension for Basic bit-manipulation, Version 1.0.0 > Count leading/trailing zero bits", + "line_range": [ + 209, + 212 + ] + }, + { + "text": "| |{check} |ctzw rd, rs | |", + "section": "Preamble > Bit Manipulation Extensions > ext:zbb[] Extension for Basic bit-manipulation, Version 1.0.0 > Count leading/trailing zero bits", + "line_range": [ + 214, + 218 + ] + }, + { + "text": "These instructions count the number of set bits (1-bits).", + "section": "Preamble > Bit Manipulation Extensions > ext:zbb[] Extension for Basic bit-manipulation, Version 1.0.0 > Count population", + "line_range": [ + 222, + 223 + ] + }, + { + "text": "This is also commonly referred to as population count.", + "section": "Preamble > Bit Manipulation Extensions > ext:zbb[] Extension for Basic bit-manipulation, Version 1.0.0 > Count population", + "line_range": [ + 222, + 223 + ] + }, + { + "text": "| |RV32 |RV64 |Mnemonic |Instruction", + "section": "Preamble > Bit Manipulation Extensions > ext:zbb[] Extension for Basic bit-manipulation, Version 1.0.0 > Count population", + "line_range": [ + 225, + 230 + ] + }, + { + "text": "|{check} |{check} |cpop rd, rs |", + "section": "Preamble > Bit Manipulation Extensions > ext:zbb[] Extension for Basic bit-manipulation, Version 1.0.0 > Count population", + "line_range": [ + 232, + 235 + ] + }, + { + "text": "| |{check} |cpopw rd, rs | |", + "section": "Preamble > Bit Manipulation Extensions > ext:zbb[] Extension for Basic bit-manipulation, Version 1.0.0 > Count population", + "line_range": [ + 237, + 241 + ] + }, + { + "text": "The integer minimum/maximum instructions are arithmetic R-type instructions that return the smaller/larger of two operands.", + "section": "Preamble > Bit Manipulation Extensions > ext:zbb[] Extension for Basic bit-manipulation, Version 1.0.0 > Integer minimum/maximum", + "line_range": [ + 245, + 246 + ] + }, + { + "text": "| |RV32 |RV64 |Mnemonic |Instruction", + "section": "Preamble > Bit Manipulation Extensions > ext:zbb[] Extension for Basic bit-manipulation, Version 1.0.0 > Integer minimum/maximum", + "line_range": [ + 248, + 253 + ] + }, + { + "text": "|{check} |{check} |max rd, rs1, rs2 |", + "section": "Preamble > Bit Manipulation Extensions > ext:zbb[] Extension for Basic bit-manipulation, Version 1.0.0 > Integer minimum/maximum", + "line_range": [ + 255, + 258 + ] + }, + { + "text": "|{check} |{check} |maxu rd, rs1, rs2 |", + "section": "Preamble > Bit Manipulation Extensions > ext:zbb[] Extension for Basic bit-manipulation, Version 1.0.0 > Integer minimum/maximum", + "line_range": [ + 260, + 263 + ] + }, + { + "text": "|{check} |{check} |min rd, rs1, rs2 |", + "section": "Preamble > Bit Manipulation Extensions > ext:zbb[] Extension for Basic bit-manipulation, Version 1.0.0 > Integer minimum/maximum", + "line_range": [ + 265, + 268 + ] + }, + { + "text": "|{check} |{check} |minu rd, rs1, rs2 | |", + "section": "Preamble > Bit Manipulation Extensions > ext:zbb[] Extension for Basic bit-manipulation, Version 1.0.0 > Integer minimum/maximum", + "line_range": [ + 270, + 274 + ] + }, + { + "text": "These instructions perform the sign extension or zero extension of the least-significant 8 bits or 16 bits of the source register.", + "section": "Preamble > Bit Manipulation Extensions > ext:zbb[] Extension for Basic bit-manipulation, Version 1.0.0 > Sign extension and zero extension", + "line_range": [ + 278, + 278 + ] + }, + { + "text": "These instructions replace the generalized idioms `slli rd,rs,(XLEN-) + srai` (for sign extension of 8-bit and 16-bit quantities) and `slli + srli` (for zero extension of 16-bit quantities).", + "section": "Preamble > Bit Manipulation Extensions > ext:zbb[] Extension for Basic bit-manipulation, Version 1.0.0 > Sign extension and zero extension", + "line_range": [ + 280, + 280 + ] + }, + { + "text": "| |RV32 |RV64 |Mnemonic |Instruction", + "section": "Preamble > Bit Manipulation Extensions > ext:zbb[] Extension for Basic bit-manipulation, Version 1.0.0 > Sign extension and zero extension", + "line_range": [ + 282, + 287 + ] + }, + { + "text": "|{check} |{check} |sext.b rd, rs |", + "section": "Preamble > Bit Manipulation Extensions > ext:zbb[] Extension for Basic bit-manipulation, Version 1.0.0 > Sign extension and zero extension", + "line_range": [ + 289, + 292 + ] + }, + { + "text": "|{check} |{check} |sext.h rd, rs |", + "section": "Preamble > Bit Manipulation Extensions > ext:zbb[] Extension for Basic bit-manipulation, Version 1.0.0 > Sign extension and zero extension", + "line_range": [ + 294, + 297 + ] + }, + { + "text": "|{check} |{check} |zext.h rd, rs | |", + "section": "Preamble > Bit Manipulation Extensions > ext:zbb[] Extension for Basic bit-manipulation, Version 1.0.0 > Sign extension and zero extension", + "line_range": [ + 299, + 303 + ] + }, + { + "text": "Bitwise rotation instructions are similar to the shift-logical operations from the base spec.", + "section": "Preamble > Bit Manipulation Extensions > ext:zbb[] Extension for Basic bit-manipulation, Version 1.0.0 > Bitwise rotation", + "line_range": [ + 307, + 309 + ] + }, + { + "text": "However, where the shift-logical instructions shift in zeros, the rotate instructions shift in the bits that were shifted out of the other side of the value.", + "section": "Preamble > Bit Manipulation Extensions > ext:zbb[] Extension for Basic bit-manipulation, Version 1.0.0 > Bitwise rotation", + "line_range": [ + 307, + 309 + ] + }, + { + "text": "Such operations are also referred to as ‘circular shifts’.", + "section": "Preamble > Bit Manipulation Extensions > ext:zbb[] Extension for Basic bit-manipulation, Version 1.0.0 > Bitwise rotation", + "line_range": [ + 307, + 309 + ] + }, + { + "text": "| |RV32 |RV64 |Mnemonic |Instruction", + "section": "Preamble > Bit Manipulation Extensions > ext:zbb[] Extension for Basic bit-manipulation, Version 1.0.0 > Bitwise rotation", + "line_range": [ + 311, + 316 + ] + }, + { + "text": "|{check} |{check} |rol rd, rs1, rs2 |", + "section": "Preamble > Bit Manipulation Extensions > ext:zbb[] Extension for Basic bit-manipulation, Version 1.0.0 > Bitwise rotation", + "line_range": [ + 318, + 321 + ] + }, + { + "text": "| |{check} |rolw rd, rs1, rs2 |", + "section": "Preamble > Bit Manipulation Extensions > ext:zbb[] Extension for Basic bit-manipulation, Version 1.0.0 > Bitwise rotation", + "line_range": [ + 323, + 326 + ] + }, + { + "text": "|{check} |{check} |ror rd, rs1, rs2 |", + "section": "Preamble > Bit Manipulation Extensions > ext:zbb[] Extension for Basic bit-manipulation, Version 1.0.0 > Bitwise rotation", + "line_range": [ + 328, + 331 + ] + }, + { + "text": "|{check} |{check} |rori rd, rs1, shamt |", + "section": "Preamble > Bit Manipulation Extensions > ext:zbb[] Extension for Basic bit-manipulation, Version 1.0.0 > Bitwise rotation", + "line_range": [ + 333, + 336 + ] + }, + { + "text": "| |{check} |roriw rd, rs1, shamt |", + "section": "Preamble > Bit Manipulation Extensions > ext:zbb[] Extension for Basic bit-manipulation, Version 1.0.0 > Bitwise rotation", + "line_range": [ + 338, + 341 + ] + }, + { + "text": "| |{check} |rorw rd, rs1, rs2 | |", + "section": "Preamble > Bit Manipulation Extensions > ext:zbb[] Extension for Basic bit-manipulation, Version 1.0.0 > Bitwise rotation", + "line_range": [ + 343, + 347 + ] + }, + { + "text": ".Architecture Explanation [NOTE, caption=\"AE\" ] The rotate instructions were included to replace a common four-instruction sequence to achieve the same effect (neg; sll/srl; srl/sll; or)", + "section": "Preamble > Bit Manipulation Extensions > ext:zbb[] Extension for Basic bit-manipulation, Version 1.0.0 > Bitwise rotation", + "line_range": [ + 349, + 354 + ] + }, + { + "text": "*orc.b* sets the bits of each byte in the result rd to all zeros if no bit within the respective byte of rs is set, or to all ones if any bit within the respective byte of rs is set.", + "section": "Preamble > Bit Manipulation Extensions > ext:zbb[] Extension for Basic bit-manipulation, Version 1.0.0 > OR Combine", + "line_range": [ + 360, + 360 + ] + }, + { + "text": "One use-case is string-processing functions, such as *strlen* and *strcpy*, which can use *orc.b* to test for the terminating zero byte by counting the set bits in leading non-zero bytes in a word.", + "section": "Preamble > Bit Manipulation Extensions > ext:zbb[] Extension for Basic bit-manipulation, Version 1.0.0 > OR Combine", + "line_range": [ + 362, + 362 + ] + }, + { + "text": "| |RV32 |RV64 |Mnemonic |Instruction", + "section": "Preamble > Bit Manipulation Extensions > ext:zbb[] Extension for Basic bit-manipulation, Version 1.0.0 > OR Combine", + "line_range": [ + 364, + 369 + ] + }, + { + "text": "|{check} |{check} |orc.b rd, rs | |", + "section": "Preamble > Bit Manipulation Extensions > ext:zbb[] Extension for Basic bit-manipulation, Version 1.0.0 > OR Combine", + "line_range": [ + 371, + 375 + ] + }, + { + "text": "*rev8* reverses the byte-ordering of rs.", + "section": "Preamble > Bit Manipulation Extensions > ext:zbb[] Extension for Basic bit-manipulation, Version 1.0.0 > Byte-reverse", + "line_range": [ + 379, + 379 + ] + }, + { + "text": "| |RV32 |RV64 |Mnemonic |Instruction", + "section": "Preamble > Bit Manipulation Extensions > ext:zbb[] Extension for Basic bit-manipulation, Version 1.0.0 > Byte-reverse", + "line_range": [ + 381, + 386 + ] + }, + { + "text": "|{check} |{check} |rev8 rd, rs |", + "section": "Preamble > Bit Manipulation Extensions > ext:zbb[] Extension for Basic bit-manipulation, Version 1.0.0 > Byte-reverse", + "line_range": [ + 388, + 391 + ] + }, + { + "text": "[zbc,reftext=\"Carry-less multiplication\"]", + "section": "Preamble > Bit Manipulation Extensions > ext:zbb[] Extension for Basic bit-manipulation, Version 1.0.0 > Byte-reverse", + "line_range": [ + 395, + 395 + ] + }, + { + "text": "Carry-less multiplication is the multiplication in the polynomial ring over GF(2).", + "section": "Preamble > Bit Manipulation Extensions > Zbc: Extension for Carry-less multiplication, Version 1.0.0", + "line_range": [ + 398, + 398 + ] + }, + { + "text": "*clmul* produces the lower half of the carry-less product and *clmulh* produces the upper half of the 2{times}XLEN carry-less product.", + "section": "Preamble > Bit Manipulation Extensions > Zbc: Extension for Carry-less multiplication, Version 1.0.0", + "line_range": [ + 400, + 400 + ] + }, + { + "text": "*clmulr* produces bits 2{times}XLEN−2:XLEN-1 of the 2{times}XLEN carry-less product.", + "section": "Preamble > Bit Manipulation Extensions > Zbc: Extension for Carry-less multiplication, Version 1.0.0", + "line_range": [ + 402, + 402 + ] + }, + { + "text": "| |RV32 |RV64 |Mnemonic |Instruction", + "section": "Preamble > Bit Manipulation Extensions > Zbc: Extension for Carry-less multiplication, Version 1.0.0", + "line_range": [ + 404, + 409 + ] + }, + { + "text": "|{check} |{check} |clmul rd, rs1, rs2 |", + "section": "Preamble > Bit Manipulation Extensions > Zbc: Extension for Carry-less multiplication, Version 1.0.0", + "line_range": [ + 411, + 414 + ] + }, + { + "text": "|{check} |{check} |clmulh rd, rs1, rs2 |", + "section": "Preamble > Bit Manipulation Extensions > Zbc: Extension for Carry-less multiplication, Version 1.0.0", + "line_range": [ + 416, + 419 + ] + }, + { + "text": "|{check} |{check} |clmulr rd, rs1, rs2 |", + "section": "Preamble > Bit Manipulation Extensions > Zbc: Extension for Carry-less multiplication, Version 1.0.0", + "line_range": [ + 421, + 424 + ] + }, + { + "text": "[zbs,reftext=\"Single-bit instructions\"]", + "section": "Preamble > Bit Manipulation Extensions > Zbc: Extension for Carry-less multiplication, Version 1.0.0", + "line_range": [ + 428, + 428 + ] + }, + { + "text": "The single-bit instructions provide a mechanism to set, clear, invert, or extract a single bit in a register.", + "section": "Preamble > Bit Manipulation Extensions > Zbs: Extension for Single-bit instructions, Version 1.0.0", + "line_range": [ + 431, + 432 + ] + }, + { + "text": "The bit is specified by its index.", + "section": "Preamble > Bit Manipulation Extensions > Zbs: Extension for Single-bit instructions, Version 1.0.0", + "line_range": [ + 431, + 432 + ] + }, + { + "text": "| |RV32 |RV64 |Mnemonic |Instruction", + "section": "Preamble > Bit Manipulation Extensions > Zbs: Extension for Single-bit instructions, Version 1.0.0", + "line_range": [ + 434, + 439 + ] + }, + { + "text": "|{check} |{check} |bclr rd, rs1, rs2 |", + "section": "Preamble > Bit Manipulation Extensions > Zbs: Extension for Single-bit instructions, Version 1.0.0", + "line_range": [ + 441, + 444 + ] + }, + { + "text": "|{check} |{check} |bclri rd, rs1, imm |", + "section": "Preamble > Bit Manipulation Extensions > Zbs: Extension for Single-bit instructions, Version 1.0.0", + "line_range": [ + 446, + 449 + ] + }, + { + "text": "|{check} |{check} |bext rd, rs1, rs2 |", + "section": "Preamble > Bit Manipulation Extensions > Zbs: Extension for Single-bit instructions, Version 1.0.0", + "line_range": [ + 451, + 454 + ] + }, + { + "text": "|{check} |{check} |bexti rd, rs1, imm |", + "section": "Preamble > Bit Manipulation Extensions > Zbs: Extension for Single-bit instructions, Version 1.0.0", + "line_range": [ + 456, + 459 + ] + }, + { + "text": "|{check} |{check} |binv rd, rs1, rs2 |", + "section": "Preamble > Bit Manipulation Extensions > Zbs: Extension for Single-bit instructions, Version 1.0.0", + "line_range": [ + 461, + 464 + ] + }, + { + "text": "|{check} |{check} |binvi rd, rs1, imm |", + "section": "Preamble > Bit Manipulation Extensions > Zbs: Extension for Single-bit instructions, Version 1.0.0", + "line_range": [ + 466, + 469 + ] + }, + { + "text": "|{check} |{check} |bset rd, rs1, rs2 |", + "section": "Preamble > Bit Manipulation Extensions > Zbs: Extension for Single-bit instructions, Version 1.0.0", + "line_range": [ + 471, + 474 + ] + }, + { + "text": "|{check} |{check} |bseti rd, rs1, imm |", + "section": "Preamble > Bit Manipulation Extensions > Zbs: Extension for Single-bit instructions, Version 1.0.0", + "line_range": [ + 476, + 479 + ] + }, + { + "text": "This extension contains instructions essential for implementing common operations in cryptographic workloads.", + "section": "Preamble > Bit Manipulation Extensions > Zbkb: Extension for Bit-manipulation for Cryptography, Version 1.0.0", + "line_range": [ + 486, + 487 + ] + }, + { + "text": "| |RV32 |RV64 |Mnemonic |Instruction", + "section": "Preamble > Bit Manipulation Extensions > Zbkb: Extension for Bit-manipulation for Cryptography, Version 1.0.0", + "line_range": [ + 489, + 494 + ] + }, + { + "text": "| {check} | {check} | rol |", + "section": "Preamble > Bit Manipulation Extensions > Zbkb: Extension for Bit-manipulation for Cryptography, Version 1.0.0", + "line_range": [ + 496, + 499 + ] + }, + { + "text": "| {check} | {check} | ror |", + "section": "Preamble > Bit Manipulation Extensions > Zbkb: Extension for Bit-manipulation for Cryptography, Version 1.0.0", + "line_range": [ + 506, + 509 + ] + }, + { + "text": "| {check} | {check} | rori |", + "section": "Preamble > Bit Manipulation Extensions > Zbkb: Extension for Bit-manipulation for Cryptography, Version 1.0.0", + "line_range": [ + 511, + 514 + ] + }, + { + "text": "| {check} | {check} | andn |", + "section": "Preamble > Bit Manipulation Extensions > Zbkb: Extension for Bit-manipulation for Cryptography, Version 1.0.0", + "line_range": [ + 526, + 529 + ] + }, + { + "text": "| {check} | {check} | orn |", + "section": "Preamble > Bit Manipulation Extensions > Zbkb: Extension for Bit-manipulation for Cryptography, Version 1.0.0", + "line_range": [ + 531, + 534 + ] + }, + { + "text": "| {check} | {check} | xnor |", + "section": "Preamble > Bit Manipulation Extensions > Zbkb: Extension for Bit-manipulation for Cryptography, Version 1.0.0", + "line_range": [ + 536, + 539 + ] + }, + { + "text": "| {check} | {check} | pack |", + "section": "Preamble > Bit Manipulation Extensions > Zbkb: Extension for Bit-manipulation for Cryptography, Version 1.0.0", + "line_range": [ + 541, + 544 + ] + }, + { + "text": "| {check} | {check} | packh |", + "section": "Preamble > Bit Manipulation Extensions > Zbkb: Extension for Bit-manipulation for Cryptography, Version 1.0.0", + "line_range": [ + 546, + 549 + ] + }, + { + "text": "| {check} | {check} | brev8 |", + "section": "Preamble > Bit Manipulation Extensions > Zbkb: Extension for Bit-manipulation for Cryptography, Version 1.0.0", + "line_range": [ + 556, + 559 + ] + }, + { + "text": "| {check} | {check} | rev8 |", + "section": "Preamble > Bit Manipulation Extensions > Zbkb: Extension for Bit-manipulation for Cryptography, Version 1.0.0", + "line_range": [ + 561, + 564 + ] + }, + { + "text": "Carry-less multiplication is the multiplication in the polynomial ring over GF(2).", + "section": "Preamble > Bit Manipulation Extensions > Zbkc: Extension for Carry-less multiplication for Cryptography, Version 1.0.0", + "line_range": [ + 582, + 587 + ] + }, + { + "text": "This extension is a subset of the Zbc extension, and only provides `clmul` and `clmulh`.", + "section": "Preamble > Bit Manipulation Extensions > Zbkc: Extension for Carry-less multiplication for Cryptography, Version 1.0.0", + "line_range": [ + 582, + 587 + ] + }, + { + "text": "These are the crucial instructions needed to efficiently implement the GHASH operation, a critical operation in some cryptographic workloads such as the AES-GCM authenticated encryption scheme.", + "section": "Preamble > Bit Manipulation Extensions > Zbkc: Extension for Carry-less multiplication for Cryptography, Version 1.0.0", + "line_range": [ + 582, + 587 + ] + }, + { + "text": "See Zbc for further instruction details for these two instructions.", + "section": "Preamble > Bit Manipulation Extensions > Zbkc: Extension for Carry-less multiplication for Cryptography, Version 1.0.0", + "line_range": [ + 582, + 587 + ] + }, + { + "text": "These instructions implement a \"lookup table\" for 4 and 8 bit elements inside the general purpose registers. rs1 is used as a vector of N-bit words, and rs2 as a vector of N-bit indices into rs1.", + "section": "Preamble > Bit Manipulation Extensions > Zbkx: Extension for Crossbar permutations, Version 1.0.0", + "line_range": [ + 593, + 598 + ] + }, + { + "text": "Elements in rs1 are replaced by the indexed element in rs2, or zero if the index into rs2 is out of bounds.", + "section": "Preamble > Bit Manipulation Extensions > Zbkx: Extension for Crossbar permutations, Version 1.0.0", + "line_range": [ + 593, + 598 + ] + }, + { + "text": "These instructions are useful for expressing N-bit to N-bit boolean operations, and implementing cryptographic code with secret dependent memory accesses (particularly SBoxes) such that the execution latency does not depend on the (secret) data being operated on.", + "section": "Preamble > Bit Manipulation Extensions > Zbkx: Extension for Crossbar permutations, Version 1.0.0", + "line_range": [ + 600, + 603 + ] + }, + { + "text": "| |RV32 |RV64 |Mnemonic |Instruction", + "section": "Preamble > Bit Manipulation Extensions > Zbkx: Extension for Crossbar permutations, Version 1.0.0", + "line_range": [ + 605, + 610 + ] + }, + { + "text": "|{check} |{check} |xperm4 rd, rs1, rs2 |", + "section": "Preamble > Bit Manipulation Extensions > Zbkx: Extension for Crossbar permutations, Version 1.0.0", + "line_range": [ + 612, + 615 + ] + }, + { + "text": "|{check} |{check} |xperm8 rd, rs1, rs2 |", + "section": "Preamble > Bit Manipulation Extensions > Zbkx: Extension for Crossbar permutations, Version 1.0.0", + "line_range": [ + 617, + 620 + ] + }, + { + "text": "[insns-b,reftext=\"Instructions (in alphabetical order)\"]", + "section": "Preamble > Bit Manipulation Extensions > Zbkx: Extension for Crossbar permutations, Version 1.0.0", + "line_range": [ + 626, + 626 + ] + }, + { + "text": "The semantics of each instruction is expressed in a SAIL-like syntax.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order)", + "line_range": [ + 629, + 629 + ] + }, + { + "text": "[insns-adduw,reftext=Add unsigned word]", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order)", + "line_range": [ + 631, + 631 + ] + }, + { + "text": "Synopsis:: Add unsigned word", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > add.uw", + "line_range": [ + 634, + 635 + ] + }, + { + "text": "Mnemonic:: add.uw rd, rs1, rs2", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > add.uw", + "line_range": [ + 637, + 638 + ] + }, + { + "text": "Pseudoinstructions:: zext.w rd, rs1 {rightarrow} add.uw rd, rs1, zero", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > add.uw", + "line_range": [ + 640, + 641 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0x3b, attr: ['OP-32'] }, { bits: 5, name: 'rd' }, { bits: 3, name: 0x0, attr: ['ADD.UW'] }, { bits: 5, name: 'rs1' }, { bits: 5, name: 'rs2' }, { bits: 7, name: 0x04, attr: ['ADD.UW'] }, ]} ....", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > add.uw", + "line_range": [ + 643, + 655 + ] + }, + { + "text": "Description:: This instruction performs an XLEN-wide addition between rs2 and the zero-extended least-significant word of rs1.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > add.uw", + "line_range": [ + 657, + 658 + ] + }, + { + "text": "Operation:: [source,sail] -- let base = X(rs2); let index = EXTZ(X(rs1)[31..0]);", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > add.uw", + "line_range": [ + 660, + 665 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > add.uw", + "line_range": [ + 670, + 675 + ] + }, + { + "text": "<<< [insns-andn,reftext=\"AND with inverted operand\"]", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > add.uw", + "line_range": [ + 682, + 683 + ] + }, + { + "text": "Synopsis:: AND with inverted operand", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > andn", + "line_range": [ + 687, + 688 + ] + }, + { + "text": "Mnemonic:: andn rd, rs1, rs2", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > andn", + "line_range": [ + 690, + 691 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0x33, attr: ['OP'] }, { bits: 5, name: 'rd' }, { bits: 3, name: 0x7, attr: ['ANDN']}, { bits: 5, name: 'rs1' }, { bits: 5, name: 'rs2' }, { bits: 7, name: 0x20, attr: ['ANDN'] }, ]} ....", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > andn", + "line_range": [ + 693, + 705 + ] + }, + { + "text": "Description:: This instruction performs the bitwise logical AND operation between rs1 and the bitwise inversion of rs2.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > andn", + "line_range": [ + 707, + 708 + ] + }, + { + "text": "Operation:: [source,sail] -- X(rd) = X(rs1) & ~X(rs2); --", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > andn", + "line_range": [ + 710, + 715 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > andn", + "line_range": [ + 717, + 722 + ] + }, + { + "text": "|Zbb (ext:zbb[]) |v1.0 |Ratified", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > andn", + "line_range": [ + 724, + 726 + ] + }, + { + "text": "|Zbkb () |v1.0 |Ratified |", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > andn", + "line_range": [ + 728, + 731 + ] + }, + { + "text": "<<< [insns-bclr,reftext=\"Single-Bit Clear (Register)\"]", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > andn", + "line_range": [ + 733, + 734 + ] + }, + { + "text": "Synopsis:: Single-Bit Clear (Register)", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > bclr", + "line_range": [ + 737, + 738 + ] + }, + { + "text": "Mnemonic:: bclr rd, rs1, rs2", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > bclr", + "line_range": [ + 740, + 741 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0x33, attr: ['OP'] }, { bits: 5, name: 'rd' }, { bits: 3, name: 0x1, attr: ['BCLR'] }, { bits: 5, name: 'rs1' }, { bits: 5, name: 'rs2' }, { bits: 7, name: 0x24, attr: ['BCLR/BEXT'] }, ]} ....", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > bclr", + "line_range": [ + 743, + 755 + ] + }, + { + "text": "Description:: This instruction returns rs1 with a single bit cleared at the index specified in rs2.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > bclr", + "line_range": [ + 757, + 759 + ] + }, + { + "text": "The index is read from the lower log2(XLEN) bits of rs2.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > bclr", + "line_range": [ + 757, + 759 + ] + }, + { + "text": "Operation:: [source,sail] -- let index = X(rs2) & (XLEN - 1); X(rd) = X(rs1) & ~(1 << index) --", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > bclr", + "line_range": [ + 761, + 767 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > bclr", + "line_range": [ + 769, + 774 + ] + }, + { + "text": "<<< [insns-bclri,reftext=\"Single-Bit Clear (Immediate)\"]", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > bclr", + "line_range": [ + 781, + 782 + ] + }, + { + "text": "Synopsis:: Single-Bit Clear (Immediate)", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > bclri", + "line_range": [ + 785, + 786 + ] + }, + { + "text": "Mnemonic:: bclri rd, rs1, shamt", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > bclri", + "line_range": [ + 788, + 789 + ] + }, + { + "text": "Encoding (RV32):: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0x13, attr: ['OP-IMM'] }, { bits: 5, name: 'rd' }, { bits: 3, name: 0x1, attr: ['BCLRI'] }, { bits: 5, name: 'rs1' }, { bits: 5, name: 'shamt' }, { bits: 7, name: 0x24, attr: ['BCLRI'] }, ]} ....", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > bclri", + "line_range": [ + 791, + 803 + ] + }, + { + "text": "Encoding (RV64):: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0x13, attr: ['OP-IMM'] }, { bits: 5, name: 'rd' }, { bits: 3, name: 0x1, attr: ['BCLRI'] }, { bits: 5, name: 'rs1' }, { bits: 6, name: 'shamt' }, { bits: 6, name: 0x12, attr: ['BCLRI'] }, ]} ....", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > bclri", + "line_range": [ + 805, + 817 + ] + }, + { + "text": "Description:: This instruction returns rs1 with a single bit cleared at the index specified in shamt.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > bclri", + "line_range": [ + 819, + 822 + ] + }, + { + "text": "The index is read from the lower log2(XLEN) bits of shamt.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > bclri", + "line_range": [ + 819, + 822 + ] + }, + { + "text": "For RV32, the encodings corresponding to shamt[5]=1 are reserved.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > bclri", + "line_range": [ + 819, + 822 + ] + }, + { + "text": "Operation:: [source,sail] -- let index = shamt & (XLEN - 1); X(rd) = X(rs1) & ~(1 << index) --", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > bclri", + "line_range": [ + 824, + 830 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > bclri", + "line_range": [ + 832, + 837 + ] + }, + { + "text": "<<< [insns-bext,reftext=\"Single-Bit Extract (Register)\"]", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > bclri", + "line_range": [ + 844, + 845 + ] + }, + { + "text": "Synopsis:: Single-Bit Extract (Register) // Should we describe this as a Set-if-bit-is-set?", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > bext", + "line_range": [ + 848, + 850 + ] + }, + { + "text": "Mnemonic:: bext rd, rs1, rs2", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > bext", + "line_range": [ + 852, + 853 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0x33, attr: ['OP'] }, { bits: 5, name: 'rd' }, { bits: 3, name: 0x5, attr: ['BEXT'] }, { bits: 5, name: 'rs1' }, { bits: 5, name: 'rs2' }, { bits: 7, name: 0x24, attr: ['BCLR/BEXT'] }, ]} ....", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > bext", + "line_range": [ + 855, + 867 + ] + }, + { + "text": "Description:: This instruction returns a single bit extracted from rs1 at the index specified in rs2.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > bext", + "line_range": [ + 869, + 871 + ] + }, + { + "text": "The index is read from the lower log2(XLEN) bits of rs2.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > bext", + "line_range": [ + 869, + 871 + ] + }, + { + "text": "Operation:: [source,sail] -- let index = X(rs2) & (XLEN - 1); X(rd) = (X(rs1) >> index) & 1; --", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > bext", + "line_range": [ + 873, + 879 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > bext", + "line_range": [ + 881, + 886 + ] + }, + { + "text": "<<< [insns-bexti,reftext=\"Single-Bit Extract (Immediate)\"]", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > bext", + "line_range": [ + 893, + 894 + ] + }, + { + "text": "Synopsis:: Single-Bit Extract (Immediate)", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > bexti", + "line_range": [ + 897, + 898 + ] + }, + { + "text": "Mnemonic:: bexti rd, rs1, shamt", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > bexti", + "line_range": [ + 900, + 901 + ] + }, + { + "text": "Encoding (RV32):: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0x13, attr: ['OP-IMM'] }, { bits: 5, name: 'rd' }, { bits: 3, name: 0x5, attr: ['BEXTI'] }, { bits: 5, name: 'rs1' }, { bits: 5, name: 'shamt' }, { bits: 7, name: 0x24, attr: ['BEXTI/BCLRI'] }, ]} ....", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > bexti", + "line_range": [ + 903, + 915 + ] + }, + { + "text": "Encoding (RV64):: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0x13, attr: ['OP-IMM'] }, { bits: 5, name: 'rd' }, { bits: 3, name: 0x5, attr: ['BEXTI'] }, { bits: 5, name: 'rs1' }, { bits: 6, name: 'shamt' }, { bits: 6, name: 0x12, attr: ['BEXTI/BCLRI'] }, ]} ....", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > bexti", + "line_range": [ + 917, + 929 + ] + }, + { + "text": "Description:: This instruction returns a single bit extracted from rs1 at the index specified in shamt.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > bexti", + "line_range": [ + 931, + 934 + ] + }, + { + "text": "The index is read from the lower log2(XLEN) bits of shamt.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > bexti", + "line_range": [ + 931, + 934 + ] + }, + { + "text": "For RV32, the encodings corresponding to shamt[5]=1 are reserved.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > bexti", + "line_range": [ + 931, + 934 + ] + }, + { + "text": "Operation:: [source,sail] -- let index = shamt & (XLEN - 1); X(rd) = (X(rs1) >> index) & 1; --", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > bexti", + "line_range": [ + 936, + 942 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > bexti", + "line_range": [ + 944, + 949 + ] + }, + { + "text": "<<< [insns-binv,reftext=\"Single-Bit Invert (Register)\"]", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > bexti", + "line_range": [ + 956, + 957 + ] + }, + { + "text": "Synopsis:: Single-Bit Invert (Register)", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > binv", + "line_range": [ + 960, + 961 + ] + }, + { + "text": "Mnemonic:: binv rd, rs1, rs2", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > binv", + "line_range": [ + 963, + 964 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0x33, attr: ['OP'] }, { bits: 5, name: 'rd' }, { bits: 3, name: 0x1, attr: ['BINV'] }, { bits: 5, name: 'rs1' }, { bits: 5, name: 'rs2' }, { bits: 7, name: 0x34, attr: ['BINV'] }, ]} ....", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > binv", + "line_range": [ + 966, + 978 + ] + }, + { + "text": "Description:: This instruction returns rs1 with a single bit inverted at the index specified in rs2.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > binv", + "line_range": [ + 980, + 982 + ] + }, + { + "text": "The index is read from the lower log2(XLEN) bits of rs2.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > binv", + "line_range": [ + 980, + 982 + ] + }, + { + "text": "Operation:: [source,sail] -- let index = X(rs2) & (XLEN - 1); X(rd) = X(rs1) ^ (1 << index) --", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > binv", + "line_range": [ + 984, + 990 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > binv", + "line_range": [ + 992, + 997 + ] + }, + { + "text": "<<< [insns-binvi,reftext=\"Single-Bit Invert (Immediate)\"]", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > binv", + "line_range": [ + 1004, + 1005 + ] + }, + { + "text": "Synopsis:: Single-Bit Invert (Immediate)", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > binvi", + "line_range": [ + 1008, + 1009 + ] + }, + { + "text": "Mnemonic:: binvi rd, rs1, shamt", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > binvi", + "line_range": [ + 1011, + 1012 + ] + }, + { + "text": "Encoding (RV32):: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0x13, attr: ['OP-IMM'] }, { bits: 5, name: 'rd' }, { bits: 3, name: 0x1, attr: ['BINV'] }, { bits: 5, name: 'rs1' }, { bits: 5, name: 'shamt' }, { bits: 7, name: 0x34, attr: ['BINVI'] }, ]} ....", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > binvi", + "line_range": [ + 1014, + 1026 + ] + }, + { + "text": "Encoding (RV64):: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0x13, attr: ['OP-IMM'] }, { bits: 5, name: 'rd' }, { bits: 3, name: 0x1, attr: ['BINV'] }, { bits: 5, name: 'rs1' }, { bits: 6, name: 'shamt' }, { bits: 6, name: 0x1a, attr: ['BINVI'] }, ]} ....", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > binvi", + "line_range": [ + 1028, + 1040 + ] + }, + { + "text": "Description:: This instruction returns rs1 with a single bit inverted at the index specified in shamt.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > binvi", + "line_range": [ + 1042, + 1045 + ] + }, + { + "text": "The index is read from the lower log2(XLEN) bits of shamt.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > binvi", + "line_range": [ + 1042, + 1045 + ] + }, + { + "text": "For RV32, the encodings corresponding to shamt[5]=1 are reserved.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > binvi", + "line_range": [ + 1042, + 1045 + ] + }, + { + "text": "Operation:: [source,sail] -- let index = shamt & (XLEN - 1); X(rd) = X(rs1) ^ (1 << index) --", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > binvi", + "line_range": [ + 1047, + 1053 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > binvi", + "line_range": [ + 1055, + 1060 + ] + }, + { + "text": "<<< [insns-bset,reftext=\"Single-Bit Set (Register)\"]", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > binvi", + "line_range": [ + 1067, + 1068 + ] + }, + { + "text": "Synopsis:: Single-Bit Set (Register)", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > bset", + "line_range": [ + 1071, + 1072 + ] + }, + { + "text": "Mnemonic:: bset rd, rs1,rs2", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > bset", + "line_range": [ + 1074, + 1075 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0x33, attr: ['OP'] }, { bits: 5, name: 'rd' }, { bits: 3, name: 0x1, attr: ['BSET'] }, { bits: 5, name: 'rs1' }, { bits: 5, name: 'rs2' }, { bits: 7, name: 0x14, attr: ['BSET'] }, ]} ....", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > bset", + "line_range": [ + 1077, + 1089 + ] + }, + { + "text": "Description:: This instruction returns rs1 with a single bit set at the index specified in rs2.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > bset", + "line_range": [ + 1091, + 1093 + ] + }, + { + "text": "The index is read from the lower log2(XLEN) bits of rs2.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > bset", + "line_range": [ + 1091, + 1093 + ] + }, + { + "text": "Operation:: [source,sail] -- let index = X(rs2) & (XLEN - 1); X(rd) = X(rs1) | (1 << index) --", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > bset", + "line_range": [ + 1095, + 1101 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > bset", + "line_range": [ + 1103, + 1108 + ] + }, + { + "text": "<<< [insns-bseti,reftext=\"Single-Bit Set (Immediate)\"]", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > bset", + "line_range": [ + 1115, + 1116 + ] + }, + { + "text": "Synopsis:: Single-Bit Set (Immediate)", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > bseti", + "line_range": [ + 1119, + 1120 + ] + }, + { + "text": "Mnemonic:: bseti rd, rs1,shamt", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > bseti", + "line_range": [ + 1122, + 1123 + ] + }, + { + "text": "Encoding (RV32):: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0x13, attr: ['OP-IMM'] }, { bits: 5, name: 'rd' }, { bits: 3, name: 0x1, attr: ['BSETI'] }, { bits: 5, name: 'rs1' }, { bits: 5, name: 'shamt' }, { bits: 7, name: 0x14, attr: ['BSETI'] }, ]} ....", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > bseti", + "line_range": [ + 1125, + 1137 + ] + }, + { + "text": "Encoding (RV64):: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0x13, attr: ['OP-IMM'] }, { bits: 5, name: 'rd' }, { bits: 3, name: 0x1, attr: ['BSETI'] }, { bits: 5, name: 'rs1' }, { bits: 6, name: 'shamt' }, { bits: 6, name: 0x0a, attr: ['BSETI'] }, ]} ....", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > bseti", + "line_range": [ + 1139, + 1151 + ] + }, + { + "text": "Description:: This instruction returns rs1 with a single bit set at the index specified in shamt.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > bseti", + "line_range": [ + 1153, + 1156 + ] + }, + { + "text": "The index is read from the lower log2(XLEN) bits of shamt.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > bseti", + "line_range": [ + 1153, + 1156 + ] + }, + { + "text": "For RV32, the encodings corresponding to shamt[5]=1 are reserved.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > bseti", + "line_range": [ + 1153, + 1156 + ] + }, + { + "text": "Operation:: [source,sail] -- let index = shamt & (XLEN - 1); X(rd) = X(rs1) | (1 << index) --", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > bseti", + "line_range": [ + 1158, + 1164 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > bseti", + "line_range": [ + 1166, + 1171 + ] + }, + { + "text": "<<< [insns-clmul,reftext=\"Carry-less multiply (low-part)\"]", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > bseti", + "line_range": [ + 1178, + 1179 + ] + }, + { + "text": "Synopsis:: Carry-less multiply (low-part)", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > clmul", + "line_range": [ + 1182, + 1183 + ] + }, + { + "text": "Mnemonic:: clmul rd, rs1, rs2", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > clmul", + "line_range": [ + 1185, + 1186 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0x33, attr: ['OP'] }, { bits: 5, name: 'rd' }, { bits: 3, name: 0x1, attr: ['CLMUL'] }, { bits: 5, name: 'rs1' }, { bits: 5, name: 'rs2' }, { bits: 7, name: 0x5, attr: ['MINMAX/CLMUL'] }, ]} ....", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > clmul", + "line_range": [ + 1188, + 1200 + ] + }, + { + "text": "Description:: clmul produces the lower half of the 2·XLEN carry-less product.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > clmul", + "line_range": [ + 1202, + 1203 + ] + }, + { + "text": "Operation:: [source,sail] -- let rs1val = X(rs1); let rs2val = X(rs2); let output : xlenbits = 0;", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > clmul", + "line_range": [ + 1205, + 1211 + ] + }, + { + "text": "foreach (i from 0 to (xlen - 1) by 1) { output = if ((rs2val >> i) & 1) then output ^ (rs1val << i); else output; }", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > clmul", + "line_range": [ + 1213, + 1217 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > clmul", + "line_range": [ + 1222, + 1227 + ] + }, + { + "text": "|Zbkc () |v1.0 |Ratified |", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > clmul", + "line_range": [ + 1233, + 1236 + ] + }, + { + "text": "<<< [insns-clmulh,reftext=\"Carry-less multiply (high-part)\"]", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > clmul", + "line_range": [ + 1238, + 1239 + ] + }, + { + "text": "Synopsis:: Carry-less multiply (high-part)", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > clmulh", + "line_range": [ + 1242, + 1243 + ] + }, + { + "text": "Mnemonic:: clmulh rd, rs1, rs2", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > clmulh", + "line_range": [ + 1245, + 1246 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0x33, attr: ['OP'] }, { bits: 5, name: 'rd' }, { bits: 3, name: 0x3, attr: ['CLMULH'] }, { bits: 5, name: 'rs1' }, { bits: 5, name: 'rs2' }, { bits: 7, name: 0x5, attr: ['MINMAX/CLMUL'] }, ]} ....", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > clmulh", + "line_range": [ + 1248, + 1260 + ] + }, + { + "text": "Description:: clmulh produces the upper half of the 2·XLEN carry-less product.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > clmulh", + "line_range": [ + 1262, + 1263 + ] + }, + { + "text": "Operation:: [source,sail] -- let rs1val = X(rs1); let rs2val = X(rs2); let output : xlenbits = 0;", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > clmulh", + "line_range": [ + 1265, + 1271 + ] + }, + { + "text": "foreach (i from 1 to xlen by 1) { output = if ((rs2val >> i) & 1) then output ^ (rs1val >> (xlen - i)); else output; }", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > clmulh", + "line_range": [ + 1273, + 1277 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > clmulh", + "line_range": [ + 1282, + 1287 + ] + }, + { + "text": "|Zbkc () |v1.0 |Ratified |", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > clmulh", + "line_range": [ + 1293, + 1296 + ] + }, + { + "text": "<<< [insns-clmulr,reftext=\"Carry-less multiply (reversed)\"]", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > clmulh", + "line_range": [ + 1298, + 1299 + ] + }, + { + "text": "Synopsis:: Carry-less multiply (reversed)", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > clmulr", + "line_range": [ + 1303, + 1304 + ] + }, + { + "text": "Mnemonic:: clmulr rd, rs1, rs2", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > clmulr", + "line_range": [ + 1306, + 1307 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0x33, attr: ['OP'] }, { bits: 5, name: 'rd' }, { bits: 3, name: 0x2, attr: ['CLMULR'] }, { bits: 5, name: 'rs1' }, { bits: 5, name: 'rs2' }, { bits: 7, name: 0x5, attr: ['MINMAX/CLMUL'] }, ]} ....", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > clmulr", + "line_range": [ + 1309, + 1321 + ] + }, + { + "text": "Description:: *clmulr* produces bits 2·XLEN−2:XLEN-1 of the 2·XLEN carry-less product.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > clmulr", + "line_range": [ + 1323, + 1325 + ] + }, + { + "text": "Operation:: [source,sail] -- let rs1val = X(rs1); let rs2val = X(rs2); let output : xlenbits = 0;", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > clmulr", + "line_range": [ + 1327, + 1333 + ] + }, + { + "text": "foreach (i from 0 to (xlen - 1) by 1) { output = if ((rs2val >> i) & 1) then output ^ (rs1val >> (xlen - i - 1)); else output; }", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > clmulr", + "line_range": [ + 1335, + 1339 + ] + }, + { + "text": ".Note [NOTE, caption=\"A\" ] The *clmulr* instruction is used to accelerate CRC calculations.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > clmulr", + "line_range": [ + 1344, + 1351 + ] + }, + { + "text": "The *r* in the instruction's mnemonic stands for reversed, as the instruction is equivalent to bit-reversing the inputs, performing a *clmul*, then bit-reversing the output.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > clmulr", + "line_range": [ + 1344, + 1351 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > clmulr", + "line_range": [ + 1353, + 1358 + ] + }, + { + "text": "<<< [insns-clz,reftext=\"Count leading zero bits\"]", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > clmulr", + "line_range": [ + 1365, + 1366 + ] + }, + { + "text": "Synopsis:: Count leading zero bits", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > clz", + "line_range": [ + 1369, + 1370 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0x13, attr: ['OP-IMM'] }, { bits: 5, name: 'rd' }, { bits: 3, name: 0x1, attr: ['CLZ'] }, { bits: 5, name: 'rs1' }, { bits: 5, name: 0x0, attr: ['CLZ'] }, { bits: 7, name: 0x30, attr: ['CLZ'] }, ]} ....", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > clz", + "line_range": [ + 1375, + 1387 + ] + }, + { + "text": "Description:: This instruction counts the number of 0's before the first 1, starting at the most-significant bit (i.e., XLEN-1) and progressing to bit 0.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > clz", + "line_range": [ + 1389, + 1390 + ] + }, + { + "text": "Accordingly, if the input is 0, the output is XLEN, and if the most-significant bit of the input is a 1, the output is 0.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > clz", + "line_range": [ + 1389, + 1390 + ] + }, + { + "text": "Operation:: [source,sail] -- val HighestSetBit : forall ('N : Int), 'N >= 0. bits('N) -> int", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > clz", + "line_range": [ + 1392, + 1396 + ] + }, + { + "text": "function HighestSetBit x = { foreach (i from (xlen - 1) to 0 by 1 in dec) if [x[i]] 0b1 then return(i) else (); return -1; }", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > clz", + "line_range": [ + 1398, + 1402 + ] + }, + { + "text": "let rs = X(rs); X[rd] = (xlen - 1) - HighestSetBit(rs); --", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > clz", + "line_range": [ + 1404, + 1406 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > clz", + "line_range": [ + 1408, + 1413 + ] + }, + { + "text": "|Zbb (ext:zbb[]) |v1.0 |Ratified |", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > clz", + "line_range": [ + 1415, + 1418 + ] + }, + { + "text": "<<< [insns-clzw,reftext=\"Count leading zero bits in word\"]", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > clz", + "line_range": [ + 1420, + 1421 + ] + }, + { + "text": "Synopsis:: Count leading zero bits in word", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > clzw", + "line_range": [ + 1424, + 1425 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0x1b, attr: ['OP-IMM-32'] }, { bits: 5, name: 'rd' }, { bits: 3, name: 0x1, attr: ['CLZW'] }, { bits: 5, name: 'rs1' }, { bits: 5, name: 0x0, attr: ['CLZW'] }, { bits: 7, name: 0x30, attr: ['CLZW'] }, ]} ....", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > clzw", + "line_range": [ + 1430, + 1442 + ] + }, + { + "text": "Description:: This instruction counts the number of 0's before the first 1 starting at bit 31 and progressing to bit 0.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > clzw", + "line_range": [ + 1444, + 1446 + ] + }, + { + "text": "Accordingly, if the least-significant word is 0, the output is 32, and if the most-significant bit of the word (i.e., bit 31) is a 1, the output is 0.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > clzw", + "line_range": [ + 1444, + 1446 + ] + }, + { + "text": "Operation:: [source,sail] -- val HighestSetBit32 : forall ('N : Int), 'N >= 0. bits('N) -> int", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > clzw", + "line_range": [ + 1448, + 1452 + ] + }, + { + "text": "function HighestSetBit32 x = { foreach (i from 31 to 0 by 1 in dec) if [x[i]] 0b1 then return(i) else (); return -1; }", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > clzw", + "line_range": [ + 1454, + 1458 + ] + }, + { + "text": "let rs = X(rs); X[rd] = 31 - HighestSetBit(rs); --", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > clzw", + "line_range": [ + 1460, + 1462 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > clzw", + "line_range": [ + 1464, + 1469 + ] + }, + { + "text": "|Zbb (ext:zbb[]) |v1.0 |Ratified |", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > clzw", + "line_range": [ + 1471, + 1474 + ] + }, + { + "text": "<<< [insns-cpop,reftext=\"Count set bits\"]", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > clzw", + "line_range": [ + 1476, + 1477 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0x13, attr: ['OP-IMM'] }, { bits: 5, name: 'rd' }, { bits: 3, name: 0x1, attr: ['CPOP'] }, { bits: 5, name: 'rs1' }, { bits: 5, name: 0x2, attr: ['CPOP'] }, { bits: 7, name: 0x30, attr: ['CPOP'] }, ]} ....", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > cpop", + "line_range": [ + 1486, + 1500 + ] + }, + { + "text": "Description:: This instructions counts the number of 1's (i.e., set bits) in the source register.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > cpop", + "line_range": [ + 1486, + 1500 + ] + }, + { + "text": "Operation:: [source,sail] -- let bitcount = 0; let rs = X(rs);", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > cpop", + "line_range": [ + 1502, + 1507 + ] + }, + { + "text": "foreach (i from 0 to (xlen - 1) in inc) if rs[i] 0b1 then bitcount = bitcount + 1 else ();", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > cpop", + "line_range": [ + 1509, + 1510 + ] + }, + { + "text": ".Software Hint [NOTE, caption=\"SH\" ] This operation is known as population count, popcount, sideways sum, bit summation, or Hamming weight.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > cpop", + "line_range": [ + 1515, + 1518 + ] + }, + { + "text": "The GCC builtin function `+builtinpopcount (unsigned int x)+` is implemented by cpop on RV32 and by *cpopw* on RV64.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > cpop", + "line_range": [ + 1520, + 1522 + ] + }, + { + "text": "The GCC builtin function `+builtinpopcountl (unsigned long x)+` for LP64 is implemented by *cpop* on RV64.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > cpop", + "line_range": [ + 1520, + 1522 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > cpop", + "line_range": [ + 1524, + 1529 + ] + }, + { + "text": "|Zbb (ext:zbb[]) |v1.0 |Ratified |", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > cpop", + "line_range": [ + 1531, + 1534 + ] + }, + { + "text": "<<< [insns-cpopw,reftext=\"Count set bits in word\"]", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > cpop", + "line_range": [ + 1536, + 1537 + ] + }, + { + "text": "Synopsis:: Count set bits in word", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > cpopw", + "line_range": [ + 1540, + 1541 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0x1b, attr: ['OP-IMM-32'] }, { bits: 5, name: 'rd' }, { bits: 3, name: 0x1, attr: ['CPOPW'] }, { bits: 5, name: 'rs' }, { bits: 5, name: 0x2, attr: ['CPOPW'] }, { bits: 7, name: 0x30, attr: ['CPOPW'] }, ]} ....", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > cpopw", + "line_range": [ + 1546, + 1560 + ] + }, + { + "text": "Description:: This instructions counts the number of 1's (i.e., set bits) in the least-significant word of the source register.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > cpopw", + "line_range": [ + 1546, + 1560 + ] + }, + { + "text": "Operation:: [source,sail] -- let bitcount = 0; let val = X(rs);", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > cpopw", + "line_range": [ + 1562, + 1567 + ] + }, + { + "text": "foreach (i from 0 to 31 in inc) if val[i] 0b1 then bitcount = bitcount + 1 else ();", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > cpopw", + "line_range": [ + 1569, + 1570 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > cpopw", + "line_range": [ + 1575, + 1580 + ] + }, + { + "text": "|Zbb (ext:zbb[]) |v1.0 |Ratified |", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > cpopw", + "line_range": [ + 1582, + 1585 + ] + }, + { + "text": "<<< [insns-ctz,reftext=\"Count trailing zero bits\"]", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > cpopw", + "line_range": [ + 1587, + 1588 + ] + }, + { + "text": "Synopsis:: Count trailing zeros", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > ctz", + "line_range": [ + 1591, + 1592 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0x13, attr: ['OP-IMM'] }, { bits: 5, name: 'rd' }, { bits: 3, name: 0x1, attr: ['CTZ/CTZW'] }, { bits: 5, name: 'rs1' }, { bits: 5, name: 0x1, attr: ['CTZ/CTZW'] }, { bits: 7, name: 0x30, attr: ['CTZ/CTZW'] }, ]} ....", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > ctz", + "line_range": [ + 1597, + 1609 + ] + }, + { + "text": "Description:: This instruction counts the number of 0's before the first 1, starting at the least-significant bit (i.e., 0) and progressing to the most-significant bit (i.e., XLEN-1).", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > ctz", + "line_range": [ + 1611, + 1613 + ] + }, + { + "text": "Accordingly, if the input is 0, the output is XLEN, and if the least-significant bit of the input is a 1, the output is 0.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > ctz", + "line_range": [ + 1611, + 1613 + ] + }, + { + "text": "Operation:: [source,sail] -- val LowestSetBit : forall ('N : Int), 'N >= 0. bits('N) -> int", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > ctz", + "line_range": [ + 1615, + 1619 + ] + }, + { + "text": "function LowestSetBit x = { foreach (i from 0 to (xlen - 1) by 1 in dec) if [x[i]] 0b1 then return(i) else (); return xlen; }", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > ctz", + "line_range": [ + 1621, + 1625 + ] + }, + { + "text": "let rs = X(rs); X[rd] = LowestSetBit(rs); --", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > ctz", + "line_range": [ + 1627, + 1629 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > ctz", + "line_range": [ + 1631, + 1636 + ] + }, + { + "text": "|Zbb (ext:zbb[]) |v1.0 |Ratified |", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > ctz", + "line_range": [ + 1638, + 1641 + ] + }, + { + "text": "<<< [insns-ctzw,reftext=\"Count trailing zero bits in word\"]", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > ctz", + "line_range": [ + 1643, + 1644 + ] + }, + { + "text": "Synopsis:: Count trailing zero bits in word", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > ctzw", + "line_range": [ + 1647, + 1648 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0x1b, attr: ['OP-IMM-32'] }, { bits: 5, name: 'rd' }, { bits: 3, name: 0x1, attr: ['CTZ/CTZW'] }, { bits: 5, name: 'rs1' }, { bits: 5, name: 0x1, attr: ['CTZ/CTZW'] }, { bits: 7, name: 0x30, attr: ['CTZ/CTZW'] }, ]} ....", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > ctzw", + "line_range": [ + 1653, + 1665 + ] + }, + { + "text": "Description:: This instruction counts the number of 0's before the first 1, starting at the least-significant bit (i.e., 0) and progressing to the most-significant bit of the least-significant word (i.e., 31).", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > ctzw", + "line_range": [ + 1667, + 1668 + ] + }, + { + "text": "Accordingly, if the least-significant word is 0, the output is 32, and if the least-significant bit of the input is a 1, the output is 0.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > ctzw", + "line_range": [ + 1667, + 1668 + ] + }, + { + "text": "Operation:: [source,sail] -- val LowestSetBit32 : forall ('N : Int), 'N >= 0. bits('N) -> int", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > ctzw", + "line_range": [ + 1670, + 1674 + ] + }, + { + "text": "function LowestSetBit32 x = { foreach (i from 0 to 31 by 1 in dec) if [x[i]] 0b1 then return(i) else (); return 32; }", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > ctzw", + "line_range": [ + 1676, + 1680 + ] + }, + { + "text": "let rs = X(rs); X[rd] = LowestSetBit32(rs); --", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > ctzw", + "line_range": [ + 1682, + 1684 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > ctzw", + "line_range": [ + 1686, + 1691 + ] + }, + { + "text": "|Zbb (ext:zbb[]) |v1.0 |Ratified |", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > ctzw", + "line_range": [ + 1693, + 1696 + ] + }, + { + "text": "<<< [insns-max,reftext=\"Maximum\"]", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > ctzw", + "line_range": [ + 1698, + 1699 + ] + }, + { + "text": "Mnemonic:: max rd, rs1, rs2", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > max", + "line_range": [ + 1705, + 1706 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0x33, attr: ['OP'] }, { bits: 5, name: 'rd' }, { bits: 3, name: 0x6, attr: ['MAX']}, { bits: 5, name: 'rs1' }, { bits: 5, name: 'rs2' }, { bits: 7, name: 0x05, attr: ['MINMAX/CLMUL'] }, ]} ....", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > max", + "line_range": [ + 1708, + 1720 + ] + }, + { + "text": "Description:: This instruction returns the larger of two signed integers.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > max", + "line_range": [ + 1722, + 1723 + ] + }, + { + "text": "Operation:: [source,sail] -- let rs1val = X(rs1); let rs2val = X(rs2);", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > max", + "line_range": [ + 1725, + 1730 + ] + }, + { + "text": "let result = if rs1val Bit Manipulation Extensions > Instructions (in alphabetical order) > max", + "line_range": [ + 1732, + 1734 + ] + }, + { + "text": ".Software Hint [NOTE, caption=\"SW\"] Calculating the absolute value of a signed integer can be performed using the following sequence: *neg rD,rS* followed by *max rD,rS,rD*.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > max", + "line_range": [ + 1739, + 1747 + ] + }, + { + "text": "When using this common sequence, it is suggested that they are scheduled with no intervening instructions so that implementations that are so optimized can fuse them together.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > max", + "line_range": [ + 1739, + 1747 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > max", + "line_range": [ + 1749, + 1754 + ] + }, + { + "text": "|Zbb (ext:zbb[]) |v1.0 |Ratified |", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > max", + "line_range": [ + 1756, + 1759 + ] + }, + { + "text": "<<< [insns-maxu,reftext=\"Unsigned maximum\"]", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > max", + "line_range": [ + 1761, + 1762 + ] + }, + { + "text": "Synopsis:: Unsigned maximum", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > maxu", + "line_range": [ + 1765, + 1766 + ] + }, + { + "text": "Mnemonic:: maxu rd, rs1, rs2", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > maxu", + "line_range": [ + 1768, + 1769 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0x33, attr: ['OP'] }, { bits: 5, name: 'rd' }, { bits: 3, name: 0x7, attr: ['MAXU']}, { bits: 5, name: 'rs1' }, { bits: 5, name: 'rs2' }, { bits: 7, name: 0x05, attr: ['MINMAX/CLMUL'] }, ]} ....", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > maxu", + "line_range": [ + 1771, + 1783 + ] + }, + { + "text": "Description:: This instruction returns the larger of two unsigned integers.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > maxu", + "line_range": [ + 1785, + 1786 + ] + }, + { + "text": "Operation:: [source,sail] -- let rs1val = X(rs1); let rs2val = X(rs2);", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > maxu", + "line_range": [ + 1788, + 1793 + ] + }, + { + "text": "let result = if rs1val Bit Manipulation Extensions > Instructions (in alphabetical order) > maxu", + "line_range": [ + 1795, + 1797 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > maxu", + "line_range": [ + 1802, + 1807 + ] + }, + { + "text": "|Zbb (ext:zbb[]) |v1.0 |Ratified |", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > maxu", + "line_range": [ + 1809, + 1812 + ] + }, + { + "text": "<<< [insns-min,reftext=\"Minimum\"]", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > maxu", + "line_range": [ + 1814, + 1815 + ] + }, + { + "text": "Mnemonic:: min rd, rs1, rs2", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > min", + "line_range": [ + 1821, + 1822 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0x33, attr: ['OP'] }, { bits: 5, name: 'rd' }, { bits: 3, name: 0x4, attr: ['MIN']}, { bits: 5, name: 'rs1' }, { bits: 5, name: 'rs2' }, { bits: 7, name: 0x05, attr: ['MINMAX/CLMUL'] }, ]} ....", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > min", + "line_range": [ + 1824, + 1836 + ] + }, + { + "text": "Description:: This instruction returns the smaller of two signed integers.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > min", + "line_range": [ + 1838, + 1839 + ] + }, + { + "text": "Operation:: [source,sail] -- let rs1val = X(rs1); let rs2val = X(rs2);", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > min", + "line_range": [ + 1841, + 1846 + ] + }, + { + "text": "let result = if rs1val Bit Manipulation Extensions > Instructions (in alphabetical order) > min", + "line_range": [ + 1848, + 1850 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > min", + "line_range": [ + 1855, + 1860 + ] + }, + { + "text": "|Zbb (ext:zbb[]) |v1.0 |Ratified |", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > min", + "line_range": [ + 1862, + 1865 + ] + }, + { + "text": "<<< [insns-minu,reftext=\"Unsigned minimum\"]", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > min", + "line_range": [ + 1867, + 1868 + ] + }, + { + "text": "Synopsis:: Unsigned minimum", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > minu", + "line_range": [ + 1871, + 1872 + ] + }, + { + "text": "Mnemonic:: minu rd, rs1, rs2", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > minu", + "line_range": [ + 1874, + 1875 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0x33, attr: ['OP'] }, { bits: 5, name: 'rd' }, { bits: 3, name: 0x5, attr: ['MINU']}, { bits: 5, name: 'rs1' }, { bits: 5, name: 'rs2' }, { bits: 7, name: 0x05, attr: ['MINMAX/CLMUL'] }, ]} ....", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > minu", + "line_range": [ + 1877, + 1889 + ] + }, + { + "text": "Description:: This instruction returns the smaller of two unsigned integers.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > minu", + "line_range": [ + 1891, + 1892 + ] + }, + { + "text": "Operation:: [source,sail] -- let rs1val = X(rs1); let rs2val = X(rs2);", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > minu", + "line_range": [ + 1894, + 1899 + ] + }, + { + "text": "let result = if rs1val Bit Manipulation Extensions > Instructions (in alphabetical order) > minu", + "line_range": [ + 1901, + 1903 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > minu", + "line_range": [ + 1908, + 1913 + ] + }, + { + "text": "|Zbb (ext:zbb[]) |v1.0 |Ratified |", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > minu", + "line_range": [ + 1915, + 1918 + ] + }, + { + "text": "<<< [insns-orcb,reftext=\"Bitwise OR-Combine, byte granule\"]", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > minu", + "line_range": [ + 1920, + 1921 + ] + }, + { + "text": "Synopsis:: Bitwise OR-Combine, byte granule", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > orc.b", + "line_range": [ + 1924, + 1925 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0x13, attr: ['OP-IMM'] }, { bits: 5, name: 'rd' }, { bits: 3, name: 0x5 }, { bits: 5, name: 'rs' }, { bits: 12, name: 0x287 } ]} ....", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > orc.b", + "line_range": [ + 1930, + 1941 + ] + }, + { + "text": "Description:: Combines the bits within each byte using bitwise logical OR.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > orc.b", + "line_range": [ + 1943, + 1945 + ] + }, + { + "text": "This sets the bits of each byte in the result rd to all zeros if no bit within the respective byte of rs is set, or to all ones if any bit within the respective byte of rs is set.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > orc.b", + "line_range": [ + 1943, + 1945 + ] + }, + { + "text": "Operation:: [source,sail] -- let input = X(rs); let output : xlenbits = 0;", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > orc.b", + "line_range": [ + 1947, + 1952 + ] + }, + { + "text": "foreach (i from 0 to (xlen - 8) by 8) { output[(i + 7)..i] = if input[(i + 7)..i] 0 then 0b00000000 else 0b11111111; }", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > orc.b", + "line_range": [ + 1954, + 1958 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > orc.b", + "line_range": [ + 1963, + 1968 + ] + }, + { + "text": "|Zbb (ext:zbb[]) |v1.0 |Ratified |", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > orc.b", + "line_range": [ + 1970, + 1973 + ] + }, + { + "text": "<<< [insns-orn,reftext=\"OR with inverted operand\"]", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > orc.b", + "line_range": [ + 1975, + 1976 + ] + }, + { + "text": "Synopsis:: OR with inverted operand", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > orn", + "line_range": [ + 1979, + 1980 + ] + }, + { + "text": "Mnemonic:: orn rd, rs1, rs2", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > orn", + "line_range": [ + 1982, + 1983 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0x33, attr: ['OP'] }, { bits: 5, name: 'rd' }, { bits: 3, name: 0x6, attr: ['ORN']}, { bits: 5, name: 'rs1' }, { bits: 5, name: 'rs2' }, { bits: 7, name: 0x20, attr: ['ORN'] }, ]} ....", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > orn", + "line_range": [ + 1985, + 1997 + ] + }, + { + "text": "Description:: This instruction performs the bitwise logical OR operation between rs1 and the bitwise inversion of rs2.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > orn", + "line_range": [ + 1999, + 2000 + ] + }, + { + "text": "Operation:: [source,sail] -- X(rd) = X(rs1) | ~X(rs2); --", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > orn", + "line_range": [ + 2002, + 2007 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > orn", + "line_range": [ + 2009, + 2014 + ] + }, + { + "text": "|Zbb (ext:zbb[]) |v1.0 |Ratified", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > orn", + "line_range": [ + 2016, + 2018 + ] + }, + { + "text": "|Zbkb () |v1.0 |Ratified |", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > orn", + "line_range": [ + 2020, + 2023 + ] + }, + { + "text": "<<< [insns-pack,reftext=\"Pack low halves of registers\"]", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > orn", + "line_range": [ + 2025, + 2026 + ] + }, + { + "text": "Synopsis:: Pack the low halves of rs1 and rs2 into rd.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > pack", + "line_range": [ + 2029, + 2030 + ] + }, + { + "text": "Mnemonic:: pack rd, rs1, rs2", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > pack", + "line_range": [ + 2032, + 2033 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 0x33, attr: ['OP'] }, {bits: 5, name: 'rd'}, {bits: 3, name: 0x4, attr:['PACK']}, {bits: 5, name: 'rs1'}, {bits: 5, name: 'rs2'}, {bits: 7, name: 0x4, attr:['PACK']}, ]} ....", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > pack", + "line_range": [ + 2035, + 2047 + ] + }, + { + "text": "Description:: The pack instruction packs the XLEN/2-bit lower halves of rs1 and rs2 into rd, with rs1 in the lower half and rs2 in the upper half.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > pack", + "line_range": [ + 2049, + 2051 + ] + }, + { + "text": "Operation:: [source,sail] -- let lohalf : bits(xlen/2) = X(rs1)[xlen/2-1..0]; let hihalf : bits(xlen/2) = X(rs2)[xlen/2-1..0]; X(rd) = EXTZ(hihalf @ lohalf); --", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > pack", + "line_range": [ + 2053, + 2060 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > pack", + "line_range": [ + 2062, + 2067 + ] + }, + { + "text": "|Zbkb () |v1.0 |Ratified |", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > pack", + "line_range": [ + 2069, + 2072 + ] + }, + { + "text": "NOTE: For RV32, the `pack` instruction with rs2=`x0` is the `zext.h` instruction.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > pack", + "line_range": [ + 2074, + 2079 + ] + }, + { + "text": "Hence, for RV32, any extension that contains the `pack` instruction also contains the `zext.h` instruction (but not necessarily the `c.zext.h` instruction, which is only guaranteed to exist if both the Zcb and Zbb extensions are implemented).", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > pack", + "line_range": [ + 2074, + 2079 + ] + }, + { + "text": "<<< [insns-packh,reftext=\"Pack low bytes of registers\"]", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > pack", + "line_range": [ + 2081, + 2082 + ] + }, + { + "text": "Synopsis:: Pack the low bytes of rs1 and rs2 into rd.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > packh", + "line_range": [ + 2085, + 2086 + ] + }, + { + "text": "Mnemonic:: packh rd, rs1, rs2", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > packh", + "line_range": [ + 2088, + 2089 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 0x33, attr: ['OP'] }, {bits: 5, name: 'rd'}, {bits: 3, name: 0x7, attr: ['PACKH']}, {bits: 5, name: 'rs1'}, {bits: 5, name: 'rs2'}, {bits: 7, name: 0x4, attr: ['PACKH']}, ]} ....", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > packh", + "line_range": [ + 2091, + 2103 + ] + }, + { + "text": "Description:: The packh instruction packs the least-significant bytes of rs1 and rs2 into the 16 least-significant bits of rd, zero extending the rest of rd.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > packh", + "line_range": [ + 2105, + 2108 + ] + }, + { + "text": "Operation:: [source,sail] -- let lohalf : bits(8) = X(rs1)[7..0]; let hihalf : bits(8) = X(rs2)[7..0]; X(rd) = EXTZ(hihalf @ lohalf); --", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > packh", + "line_range": [ + 2110, + 2117 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > packh", + "line_range": [ + 2119, + 2124 + ] + }, + { + "text": "|Zbkb () |v1.0 |Ratified |", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > packh", + "line_range": [ + 2126, + 2129 + ] + }, + { + "text": "<<< [insns-packw,reftext=\"Pack low 16-bits of registers (RV64)\"]", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > packh", + "line_range": [ + 2131, + 2132 + ] + }, + { + "text": "Synopsis:: Pack the low 16-bits of rs1 and rs2 into rd on RV64.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > packw", + "line_range": [ + 2135, + 2136 + ] + }, + { + "text": "Mnemonic:: packw rd, rs1, rs2", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > packw", + "line_range": [ + 2138, + 2139 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 0x3b, attr: ['OP-32']}, {bits: 5, name: 'rd'}, {bits: 3, name: 0x4}, {bits: 5, name: 'rs1'}, {bits: 5, name: 'rs2'}, {bits: 7, name: 0x4}, ]} ....", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > packw", + "line_range": [ + 2141, + 2153 + ] + }, + { + "text": "Description:: This instruction packs the low 16 bits of rs1 and rs2 into the 32 least-significant bits of rd, sign extending the 32-bit result to the rest of rd.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > packw", + "line_range": [ + 2155, + 2159 + ] + }, + { + "text": "This instruction only exists on RV64 based systems.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > packw", + "line_range": [ + 2155, + 2159 + ] + }, + { + "text": "Operation:: [source,sail] -- let lohalf : bits(16) = X(rs1)[15..0]; let hihalf : bits(16) = X(rs2)[15..0]; X(rd) = EXTS(hihalf @ lohalf); --", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > packw", + "line_range": [ + 2161, + 2168 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > packw", + "line_range": [ + 2170, + 2175 + ] + }, + { + "text": "|Zbkb () |v1.0 |Ratified |", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > packw", + "line_range": [ + 2177, + 2180 + ] + }, + { + "text": "NOTE: For RV64, the `packw` instruction with rs2=`x0` is the `zext.h` instruction.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > packw", + "line_range": [ + 2182, + 2187 + ] + }, + { + "text": "Hence, for RV64, any extension that contains the `packw` instruction also contains the `zext.h` instruction (but not necessarily the `c.zext.h` instruction, which is only guaranteed to exist if both the Zcb and Zbb extensions are implemented).", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > packw", + "line_range": [ + 2182, + 2187 + ] + }, + { + "text": "<<< [insns-rev8,reftext=\"Byte-reverse register\"]", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > packw", + "line_range": [ + 2189, + 2190 + ] + }, + { + "text": "Synopsis:: Byte-reverse register", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > rev8", + "line_range": [ + 2193, + 2194 + ] + }, + { + "text": "Encoding (RV32):: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0x13, attr: ['OP-IMM'] }, { bits: 5, name: 'rd' }, { bits: 3, name: 0x5 }, { bits: 5, name: 'rs' }, { bits: 12, name: 0x698 } ]} ....", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > rev8", + "line_range": [ + 2199, + 2210 + ] + }, + { + "text": "Encoding (RV64):: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0x13, attr: ['OP-IMM'] }, { bits: 5, name: 'rd' }, { bits: 3, name: 0x5 }, { bits: 5, name: 'rs' }, { bits: 12, name: 0x6b8 } ]} ....", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > rev8", + "line_range": [ + 2212, + 2223 + ] + }, + { + "text": "Description:: This instruction reverses the order of the bytes in rs.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > rev8", + "line_range": [ + 2225, + 2226 + ] + }, + { + "text": "Operation:: [source,sail] -- let input = X(rs); let output : xlenbits = 0; let j = xlen - 1;", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > rev8", + "line_range": [ + 2228, + 2234 + ] + }, + { + "text": "foreach (i from 0 to (xlen - 8) by 8) { output[i..(i + 7)] = input[(j - 7)..j]; j = j - 8; }", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > rev8", + "line_range": [ + 2236, + 2239 + ] + }, + { + "text": ".Note [NOTE, caption=\"A\" ] The *rev8* mnemonic corresponds to different instruction encodings in RV32 and RV64.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > rev8", + "line_range": [ + 2244, + 2248 + ] + }, + { + "text": ".Software Hint [NOTE, caption=\"SH\" ] The byte-reverse operation is only available for the full register width.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > rev8", + "line_range": [ + 2250, + 2257 + ] + }, + { + "text": "To emulate word-sized and halfword-sized byte-reversal, perform a `rev8 rd,rs` followed by a `srai rd,rd,K`, where K is XLEN-32 and XLEN-16, respectively.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > rev8", + "line_range": [ + 2250, + 2257 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > rev8", + "line_range": [ + 2259, + 2264 + ] + }, + { + "text": "|Zbb (ext:zbb[]) |v1.0 |Ratified", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > rev8", + "line_range": [ + 2266, + 2268 + ] + }, + { + "text": "|Zbkb () |v1.0 |Ratified |", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > rev8", + "line_range": [ + 2270, + 2273 + ] + }, + { + "text": "<<< [insns-brev8,reftext=\"Reverse bits in bytes\"]", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > rev8", + "line_range": [ + 2275, + 2276 + ] + }, + { + "text": "Synopsis:: Reverse the bits in each byte of a source register.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > brev8", + "line_range": [ + 2279, + 2280 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0x13, attr: ['OP-IMM'] }, { bits: 5, name: 'rd' }, { bits: 3, name: 0x5 }, { bits: 5, name: 'rs' }, { bits: 12, name: 0x687 } ]} ....", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > brev8", + "line_range": [ + 2285, + 2296 + ] + }, + { + "text": "Description:: This instruction reverses the order of the bits in every byte of a register.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > brev8", + "line_range": [ + 2298, + 2299 + ] + }, + { + "text": "Operation:: [source,sail] -- result : xlenbits = EXTZ(0b0); foreach (i from 0 to sizeof(xlen) by 8) { result[i+7..i] = reversebitsinbyte(X(rs1)[i+7..i]); }; X(rd) = result; --", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > brev8", + "line_range": [ + 2301, + 2310 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > brev8", + "line_range": [ + 2312, + 2317 + ] + }, + { + "text": "|Zbkb () |v1.0 |Ratified |", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > brev8", + "line_range": [ + 2319, + 2322 + ] + }, + { + "text": "<<< [insns-rol,reftext=\"Rotate left (Register)\"]", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > brev8", + "line_range": [ + 2324, + 2325 + ] + }, + { + "text": "Synopsis:: Rotate Left (Register)", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > rol", + "line_range": [ + 2328, + 2329 + ] + }, + { + "text": "Mnemonic:: rol rd, rs1, rs2", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > rol", + "line_range": [ + 2331, + 2332 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0x33, attr: ['OP'] }, { bits: 5, name: 'rd' }, { bits: 3, name: 0x1, attr: ['ROL']}, { bits: 5, name: 'rs1' }, { bits: 5, name: 'rs2' }, { bits: 7, name: 0x30, attr: ['ROL'] }, ]} ....", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > rol", + "line_range": [ + 2334, + 2346 + ] + }, + { + "text": "Description:: This instruction performs a rotate left of rs1 by the amount in least-significant log2(XLEN) bits of rs2.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > rol", + "line_range": [ + 2348, + 2349 + ] + }, + { + "text": "Operation:: [source,sail] -- let shamt = if xlen 32 then X(rs2)[4..0] else X(rs2)[5..0]; let result = (X(rs1) (xlen - shamt));", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > rol", + "line_range": [ + 2351, + 2358 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > rol", + "line_range": [ + 2363, + 2368 + ] + }, + { + "text": "|Zbb (ext:zbb[]) |0.93 |Ratified", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > rol", + "line_range": [ + 2370, + 2372 + ] + }, + { + "text": "|Zbkb () |v1.0 |Ratified |", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > rol", + "line_range": [ + 2374, + 2377 + ] + }, + { + "text": "<<< [insns-rolw,reftext=\"Rotate Left Word (Register)\"]", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > rol", + "line_range": [ + 2379, + 2380 + ] + }, + { + "text": "Synopsis:: Rotate Left Word (Register)", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > rolw", + "line_range": [ + 2383, + 2384 + ] + }, + { + "text": "Mnemonic:: rolw rd, rs1, rs2", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > rolw", + "line_range": [ + 2386, + 2387 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0x3b, attr: ['OP-32'] }, { bits: 5, name: 'rd' }, { bits: 3, name: 0x1, attr: ['ROLW']}, { bits: 5, name: 'rs1' }, { bits: 5, name: 'rs2' }, { bits: 7, name: 0x30, attr: ['ROLW'] }, ]} ....", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > rolw", + "line_range": [ + 2389, + 2401 + ] + }, + { + "text": "Description:: This instruction performs a rotate left on the least-significant word of rs1 by the amount in least-significant 5 bits of rs2.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > rolw", + "line_range": [ + 2403, + 2405 + ] + }, + { + "text": "The resulting word value is sign-extended by copying bit 31 to all of the more-significant bits.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > rolw", + "line_range": [ + 2403, + 2405 + ] + }, + { + "text": "Operation:: [source,sail] -- let rs1 = EXTZ(X(rs1)[31..0]) let shamt = X(rs2)[4..0]; let result = (rs1 (32 - shamt)); X(rd) = EXTS(result[31..0]); --", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > rolw", + "line_range": [ + 2407, + 2415 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > rolw", + "line_range": [ + 2417, + 2422 + ] + }, + { + "text": "|Zbb (ext:zbb[]) |0.93 |Ratified", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > rolw", + "line_range": [ + 2424, + 2426 + ] + }, + { + "text": "|Zbkb () |v1.0 |Ratified |", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > rolw", + "line_range": [ + 2428, + 2431 + ] + }, + { + "text": "<<< [insns-ror,reftext=\"Rotate right (Register)\"]", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > rolw", + "line_range": [ + 2433, + 2434 + ] + }, + { + "text": "Mnemonic:: ror rd, rs1, rs2", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > ror", + "line_range": [ + 2440, + 2441 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0x33, attr: ['OP'] }, { bits: 5, name: 'rd' }, { bits: 3, name: 0x5, attr: ['ROR']}, { bits: 5, name: 'rs1' }, { bits: 5, name: 'rs2' }, { bits: 7, name: 0x30, attr: ['ROR'] }, ]} ....", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > ror", + "line_range": [ + 2443, + 2455 + ] + }, + { + "text": "Description:: This instruction performs a rotate right of rs1 by the amount in least-significant log2(XLEN) bits of rs2.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > ror", + "line_range": [ + 2457, + 2458 + ] + }, + { + "text": "Operation:: [source,sail] -- let shamt = if xlen 32 then X(rs2)[4..0] else X(rs2)[5..0]; let result = (X(rs1) >> shamt) | (X(rs1) << (xlen - shamt));", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > ror", + "line_range": [ + 2460, + 2467 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > ror", + "line_range": [ + 2472, + 2477 + ] + }, + { + "text": "|Zbb (ext:zbb[]) |0.93 |Ratified", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > ror", + "line_range": [ + 2479, + 2481 + ] + }, + { + "text": "|Zbkb () |v1.0 |Ratified |", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > ror", + "line_range": [ + 2483, + 2486 + ] + }, + { + "text": "<<< [insns-rori,reftext=\"Rotate right (Immediate)\"]", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > ror", + "line_range": [ + 2488, + 2489 + ] + }, + { + "text": "Synopsis:: Rotate Right (Immediate)", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > rori", + "line_range": [ + 2492, + 2493 + ] + }, + { + "text": "Mnemonic:: rori rd, rs1, shamt", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > rori", + "line_range": [ + 2495, + 2496 + ] + }, + { + "text": "Encoding (RV32):: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0x13, attr: ['OP-IMM'] }, { bits: 5, name: 'rd' }, { bits: 3, name: 0x5, attr: ['RORI']}, { bits: 5, name: 'rs1' }, { bits: 5, name: 'shamt' }, { bits: 7, name: 0x30, attr: ['RORI'] }, ]} ....", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > rori", + "line_range": [ + 2498, + 2510 + ] + }, + { + "text": "Encoding (RV64):: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0x13, attr: ['OP-IMM'] }, { bits: 5, name: 'rd' }, { bits: 3, name: 0x5, attr: ['RORI']}, { bits: 5, name: 'rs1' }, { bits: 6, name: 'shamt' }, { bits: 6, name: 0x18, attr: ['RORI'] }, ]} ....", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > rori", + "line_range": [ + 2512, + 2524 + ] + }, + { + "text": "Description:: This instruction performs a rotate right of rs1 by the amount in the least-significant log2(XLEN) bits of shamt.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > rori", + "line_range": [ + 2526, + 2528 + ] + }, + { + "text": "For RV32, the encodings corresponding to shamt[5]=1 are reserved.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > rori", + "line_range": [ + 2526, + 2528 + ] + }, + { + "text": "Operation:: [source,sail] -- let shamt = if xlen 32 then shamt[4..0] else shamt[5..0]; let result = (X(rs1) >> shamt) | (X(rs1) << (xlen - shamt));", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > rori", + "line_range": [ + 2530, + 2537 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > rori", + "line_range": [ + 2542, + 2547 + ] + }, + { + "text": "|Zbb (ext:zbb[]) |0.93 |Ratified", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > rori", + "line_range": [ + 2549, + 2551 + ] + }, + { + "text": "|Zbkb () |v1.0 |Ratified |", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > rori", + "line_range": [ + 2553, + 2556 + ] + }, + { + "text": "<<< [insns-roriw,reftext=\"Rotate right Word (Immediate)\"]", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > rori", + "line_range": [ + 2558, + 2559 + ] + }, + { + "text": "Synopsis:: Rotate Right Word by Immediate", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > roriw", + "line_range": [ + 2562, + 2563 + ] + }, + { + "text": "Mnemonic:: roriw rd, rs1, shamt", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > roriw", + "line_range": [ + 2565, + 2566 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0x1b, attr: ['OP-IMM-32'] }, { bits: 5, name: 'rd' }, { bits: 3, name: 0x5, attr: ['RORIW']}, { bits: 5, name: 'rs1' }, { bits: 5, name: 'shamt' }, { bits: 7, name: 0x30, attr: ['RORIW'] }, ]} ....", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > roriw", + "line_range": [ + 2568, + 2580 + ] + }, + { + "text": "Description:: This instruction performs a rotate right on the least-significant word of rs1 by the amount in the least-significant log2(XLEN) bits of shamt.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > roriw", + "line_range": [ + 2582, + 2587 + ] + }, + { + "text": "The resulting word value is sign-extended by copying bit 31 to all of the more-significant bits.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > roriw", + "line_range": [ + 2582, + 2587 + ] + }, + { + "text": "Operation:: [source,sail] -- let rs1data = EXTZ(X(rs1)[31..0]; let result = (rs1data >> shamt) | (rs1data << (32 - shamt)); X(rd) = EXTS(result[31..0]); --", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > roriw", + "line_range": [ + 2589, + 2596 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > roriw", + "line_range": [ + 2598, + 2603 + ] + }, + { + "text": "|Zbb (ext:zbb[]) |0.93 |Ratified", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > roriw", + "line_range": [ + 2605, + 2607 + ] + }, + { + "text": "|Zbkb () |v1.0 |Ratified |", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > roriw", + "line_range": [ + 2609, + 2612 + ] + }, + { + "text": "<<< [insns-rorw,reftext=\"Rotate right Word (Register)\"]", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > roriw", + "line_range": [ + 2614, + 2615 + ] + }, + { + "text": "Synopsis:: Rotate Right Word (Register)", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > rorw", + "line_range": [ + 2619, + 2620 + ] + }, + { + "text": "Mnemonic:: rorw rd, rs1, rs2", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > rorw", + "line_range": [ + 2622, + 2623 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0x3b, attr: ['OP-32'] }, { bits: 5, name: 'rd' }, { bits: 3, name: 0x5, attr: ['RORW']}, { bits: 5, name: 'rs1' }, { bits: 5, name: 'rs2' }, { bits: 7, name: 0x30, attr: ['RORW'] }, ]} ....", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > rorw", + "line_range": [ + 2625, + 2637 + ] + }, + { + "text": "Description:: This instruction performs a rotate right on the least-significant word of rs1 by the amount in least-significant 5 bits of rs2.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > rorw", + "line_range": [ + 2639, + 2641 + ] + }, + { + "text": "The resultant word is sign-extended by copying bit 31 to all of the more-significant bits.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > rorw", + "line_range": [ + 2639, + 2641 + ] + }, + { + "text": "Operation:: [source,sail] -- let rs1 = EXTZ(X(rs1)[31..0]) let shamt = X(rs2)[4..0]; let result = (rs1 >> shamt) | (rs1 << (32 - shamt)); X(rd) = EXTS(result); --", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > rorw", + "line_range": [ + 2643, + 2651 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > rorw", + "line_range": [ + 2653, + 2658 + ] + }, + { + "text": "|Zbb (ext:zbb[]) |0.93 |Ratified", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > rorw", + "line_range": [ + 2660, + 2662 + ] + }, + { + "text": "|Zbkb () |v1.0 |Ratified |", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > rorw", + "line_range": [ + 2664, + 2667 + ] + }, + { + "text": "<<< [insns-sextb,reftext=\"Sign-extend byte\"]", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > rorw", + "line_range": [ + 2669, + 2670 + ] + }, + { + "text": "Synopsis:: Sign-extend byte", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > sext.b", + "line_range": [ + 2673, + 2674 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0x13, attr: ['OP-IMM'] }, { bits: 5, name: 'rd' }, { bits: 3, name: 0x1, attr: ['SEXT.B/SEXT.H'] }, { bits: 5, name: 'rs1' }, { bits: 5, name: 0x04, attr: ['SEXT.B'] }, { bits: 7, name: 0x30 }, ]} ....", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > sext.b", + "line_range": [ + 2679, + 2691 + ] + }, + { + "text": "Description:: This instruction sign-extends the least-significant byte in the source to XLEN by copying the most-significant bit in the byte (i.e., bit 7) to all of the more-significant bits.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > sext.b", + "line_range": [ + 2693, + 2694 + ] + }, + { + "text": "Operation:: [source,sail] -- X(rd) = EXTS(X(rs)[7..0]); --", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > sext.b", + "line_range": [ + 2696, + 2701 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > sext.b", + "line_range": [ + 2703, + 2708 + ] + }, + { + "text": "|Zbb (ext:zbb[]) |0.93 |Ratified |", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > sext.b", + "line_range": [ + 2710, + 2713 + ] + }, + { + "text": "<<< [insns-sexth,reftext=\"Sign-extend halfword\"]", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > sext.b", + "line_range": [ + 2715, + 2716 + ] + }, + { + "text": "Synopsis:: Sign-extend halfword", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > sext.h", + "line_range": [ + 2719, + 2720 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0x13, attr: ['OP-IMM'] }, { bits: 5, name: 'rd' }, { bits: 3, name: 0x1, attr: ['SEXT.B/SEXT.H'] }, { bits: 5, name: 'rs1' }, { bits: 5, name: 0x05, attr: ['SEXT.H'] }, { bits: 7, name: 0x30 }, ]} ....", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > sext.h", + "line_range": [ + 2725, + 2737 + ] + }, + { + "text": "Description:: This instruction sign-extends the least-significant halfword in rs to XLEN by copying the most-significant bit in the halfword (i.e., bit 15) to all of the more-significant bits.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > sext.h", + "line_range": [ + 2739, + 2740 + ] + }, + { + "text": "Operation:: [source,sail] -- X(rd) = EXTS(X(rs)[15..0]); --", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > sext.h", + "line_range": [ + 2742, + 2747 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > sext.h", + "line_range": [ + 2749, + 2754 + ] + }, + { + "text": "|Zbb (ext:zbb[]) |0.93 |Ratified |", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > sext.h", + "line_range": [ + 2756, + 2759 + ] + }, + { + "text": "<<< [insns-sh1add,reftext=Shift left by 1 and add]", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > sext.h", + "line_range": [ + 2761, + 2762 + ] + }, + { + "text": "Synopsis:: Shift left by 1 and add", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > sh1add", + "line_range": [ + 2766, + 2767 + ] + }, + { + "text": "Mnemonic:: sh1add rd, rs1, rs2", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > sh1add", + "line_range": [ + 2769, + 2770 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0x33, attr: ['OP'] }, { bits: 5, name: 'rd' }, { bits: 3, name: 0x2, attr: ['SH1ADD'] }, { bits: 5, name: 'rs1' }, { bits: 5, name: 'rs2' }, { bits: 7, name: 0x10, attr: ['SH1ADD'] }, ]} ....", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > sh1add", + "line_range": [ + 2772, + 2784 + ] + }, + { + "text": "Description:: This instruction shifts rs1 to the left by 1 bit and adds it to rs2.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > sh1add", + "line_range": [ + 2786, + 2787 + ] + }, + { + "text": "Operation:: [source,sail] -- X(rd) = X(rs2) + (X(rs1) << 1); --", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > sh1add", + "line_range": [ + 2789, + 2794 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > sh1add", + "line_range": [ + 2796, + 2801 + ] + }, + { + "text": "<<< [insns-sh1adduw,reftext=Shift unsigned word left by 1 and add]", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > sh1add", + "line_range": [ + 2811, + 2812 + ] + }, + { + "text": "Synopsis:: Shift unsigned word left by 1 and add", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > sh1add.uw", + "line_range": [ + 2815, + 2816 + ] + }, + { + "text": "Mnemonic:: sh1add.uw rd, rs1, rs2", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > sh1add.uw", + "line_range": [ + 2818, + 2819 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0x3b, attr: ['OP-32'] }, { bits: 5, name: 'rd' }, { bits: 3, name: 0x2, attr: ['SH1ADD.UW'] }, { bits: 5, name: 'rs1' }, { bits: 5, name: 'rs2' }, { bits: 7, name: 0x10, attr: ['SH1ADD.UW'] }, ]} ....", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > sh1add.uw", + "line_range": [ + 2821, + 2833 + ] + }, + { + "text": "Description:: This instruction performs an XLEN-wide addition of two addends.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > sh1add.uw", + "line_range": [ + 2835, + 2837 + ] + }, + { + "text": "The second addend is the unsigned value formed by extracting the least-significant word of rs1 and shifting it left by 1 place.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > sh1add.uw", + "line_range": [ + 2835, + 2837 + ] + }, + { + "text": "Operation:: [source,sail] -- let base = X(rs2); let index = EXTZ(X(rs1)[31..0]);", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > sh1add.uw", + "line_range": [ + 2839, + 2844 + ] + }, + { + "text": "X(rd) = base + (index << 1); --", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > sh1add.uw", + "line_range": [ + 2846, + 2847 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > sh1add.uw", + "line_range": [ + 2849, + 2854 + ] + }, + { + "text": "<<< [insns-sh2add,reftext=Shift left by 2 and add]", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > sh1add.uw", + "line_range": [ + 2861, + 2862 + ] + }, + { + "text": "Synopsis:: Shift left by 2 and add", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > sh2add", + "line_range": [ + 2865, + 2866 + ] + }, + { + "text": "Mnemonic:: sh2add rd, rs1, rs2", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > sh2add", + "line_range": [ + 2868, + 2869 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0x33, attr: ['OP'] }, { bits: 5, name: 'rd' }, { bits: 3, name: 0x4, attr: ['SH2ADD'] }, { bits: 5, name: 'rs1' }, { bits: 5, name: 'rs2' }, { bits: 7, name: 0x10, attr: ['SH2ADD'] }, ]} ....", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > sh2add", + "line_range": [ + 2871, + 2883 + ] + }, + { + "text": "Description:: This instruction shifts rs1 to the left by 2 places and adds it to rs2.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > sh2add", + "line_range": [ + 2885, + 2886 + ] + }, + { + "text": "Operation:: [source,sail] -- X(rd) = X(rs2) + (X(rs1) << 2); --", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > sh2add", + "line_range": [ + 2888, + 2893 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > sh2add", + "line_range": [ + 2895, + 2900 + ] + }, + { + "text": "<<< [insns-sh2adduw,reftext=Shift unsigned word left by 2 and add]", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > sh2add", + "line_range": [ + 2907, + 2908 + ] + }, + { + "text": "Synopsis:: Shift unsigned word left by 2 and add", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > sh2add.uw", + "line_range": [ + 2911, + 2912 + ] + }, + { + "text": "Mnemonic:: sh2add.uw rd, rs1, rs2", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > sh2add.uw", + "line_range": [ + 2914, + 2915 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0x3b, attr: ['OP-32'] }, { bits: 5, name: 'rd' }, { bits: 3, name: 0x4, attr: ['SH2ADD.UW'] }, { bits: 5, name: 'rs1' }, { bits: 5, name: 'rs2' }, { bits: 7, name: 0x10, attr: ['SH2ADD.UW'] }, ]} ....", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > sh2add.uw", + "line_range": [ + 2917, + 2929 + ] + }, + { + "text": "Description:: This instruction performs an XLEN-wide addition of two addends.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > sh2add.uw", + "line_range": [ + 2931, + 2934 + ] + }, + { + "text": "The second addend is the unsigned value formed by extracting the least-significant word of rs1 and shifting it left by 2 places.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > sh2add.uw", + "line_range": [ + 2931, + 2934 + ] + }, + { + "text": "Operation:: [source,sail] -- let base = X(rs2); let index = EXTZ(X(rs1)[31..0]);", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > sh2add.uw", + "line_range": [ + 2936, + 2941 + ] + }, + { + "text": "X(rd) = base + (index << 2); --", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > sh2add.uw", + "line_range": [ + 2943, + 2944 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > sh2add.uw", + "line_range": [ + 2946, + 2951 + ] + }, + { + "text": "<<< [insns-sh3add,reftext=Shift left by 3 and add]", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > sh2add.uw", + "line_range": [ + 2958, + 2959 + ] + }, + { + "text": "Synopsis:: Shift left by 3 and add", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > sh3add", + "line_range": [ + 2962, + 2963 + ] + }, + { + "text": "Mnemonic:: sh3add rd, rs1, rs2", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > sh3add", + "line_range": [ + 2965, + 2966 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0x33, attr: ['OP'] }, { bits: 5, name: 'rd' }, { bits: 3, name: 0x6, attr: ['SH3ADD'] }, { bits: 5, name: 'rs1' }, { bits: 5, name: 'rs2' }, { bits: 7, name: 0x10, attr: ['SH3ADD'] }, ]} ....", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > sh3add", + "line_range": [ + 2968, + 2980 + ] + }, + { + "text": "Description:: This instruction shifts rs1 to the left by 3 places and adds it to rs2.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > sh3add", + "line_range": [ + 2982, + 2983 + ] + }, + { + "text": "Operation:: [source,sail] -- X(rd) = X(rs2) + (X(rs1) << 3); --", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > sh3add", + "line_range": [ + 2985, + 2990 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > sh3add", + "line_range": [ + 2992, + 2997 + ] + }, + { + "text": "<<< [insns-sh3adduw,reftext=Shift unsigned word left by 3 and add]", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > sh3add", + "line_range": [ + 3004, + 3005 + ] + }, + { + "text": "Synopsis:: Shift unsigned word left by 3 and add", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > sh3add.uw", + "line_range": [ + 3008, + 3009 + ] + }, + { + "text": "Mnemonic:: sh3add.uw rd, rs1, rs2", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > sh3add.uw", + "line_range": [ + 3011, + 3012 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0x3b, attr: ['OP-32'] }, { bits: 5, name: 'rd' }, { bits: 3, name: 0x6, attr: ['SH3ADD.UW'] }, { bits: 5, name: 'rs1' }, { bits: 5, name: 'rs2' }, { bits: 7, name: 0x10, attr: ['SH3ADD.UW'] }, ]} ....", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > sh3add.uw", + "line_range": [ + 3014, + 3026 + ] + }, + { + "text": "Description:: This instruction performs an XLEN-wide addition of two addends.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > sh3add.uw", + "line_range": [ + 3028, + 3029 + ] + }, + { + "text": "The second addend is the unsigned value formed by extracting the least-significant word of rs1 and shifting it left by 3 places.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > sh3add.uw", + "line_range": [ + 3028, + 3029 + ] + }, + { + "text": "Operation:: [source,sail] -- let base = X(rs2); let index = EXTZ(X(rs1)[31..0]);", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > sh3add.uw", + "line_range": [ + 3031, + 3036 + ] + }, + { + "text": "X(rd) = base + (index << 3); --", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > sh3add.uw", + "line_range": [ + 3038, + 3039 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > sh3add.uw", + "line_range": [ + 3041, + 3046 + ] + }, + { + "text": "<<< [insns-slliuw,reftext=\"Shift-left unsigned word (Immediate)\"]", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > sh3add.uw", + "line_range": [ + 3053, + 3054 + ] + }, + { + "text": "Synopsis:: Shift-left unsigned word (Immediate)", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > slli.uw", + "line_range": [ + 3057, + 3058 + ] + }, + { + "text": "Mnemonic:: slli.uw rd, rs1, shamt", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > slli.uw", + "line_range": [ + 3060, + 3061 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0x1b, attr: ['OP-IMM-32'] }, { bits: 5, name: 'rd' }, { bits: 3, name: 0x1, attr: ['SLLI.UW'] }, { bits: 5, name: 'rs1' }, { bits: 6, name: 'shamt' }, { bits: 6, name: 0x02, attr: ['SLLI.UW'] }, ]} ....", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > slli.uw", + "line_range": [ + 3063, + 3075 + ] + }, + { + "text": "Description:: This instruction takes the least-significant word of rs1, zero-extends it, and shifts it left by the immediate.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > slli.uw", + "line_range": [ + 3077, + 3078 + ] + }, + { + "text": "Operation:: [source,sail] -- X(rd) = (EXTZ(X(rs)[31..0]) << shamt); --", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > slli.uw", + "line_range": [ + 3080, + 3085 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > slli.uw", + "line_range": [ + 3087, + 3092 + ] + }, + { + "text": ".Architecture Explanation [NOTE, caption=\"A\" ] This instruction is the same as *slli* with *zext.w* performed on rs1 before shifting.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > slli.uw", + "line_range": [ + 3099, + 3103 + ] + }, + { + "text": "<<< [insns-unzip,reftext=\"Bit deinterleave\"]", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > slli.uw", + "line_range": [ + 3105, + 3106 + ] + }, + { + "text": "Synopsis:: Place odd and even bits of the source register into upper and lower halves of the destination register, respectively.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > unzip", + "line_range": [ + 3109, + 3111 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 0x13, attr: ['OP-IMM']}, {bits: 5, name: 'rd'}, {bits: 3, name: 0x5}, {bits: 5, name: 'rs1'}, {bits: 5, name: 0xf}, {bits: 7, name: 0x4}, ]} ....", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > unzip", + "line_range": [ + 3116, + 3128 + ] + }, + { + "text": "Description:: This instruction scatters all of the odd and even bits of a source word into the high and low halves of a destination word.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > unzip", + "line_range": [ + 3130, + 3134 + ] + }, + { + "text": "It is the inverse of the instruction.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > unzip", + "line_range": [ + 3130, + 3134 + ] + }, + { + "text": "This instruction is available only on RV32.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > unzip", + "line_range": [ + 3130, + 3134 + ] + }, + { + "text": "Operation:: [source,sail] -- foreach (i from 0 to xlen/2-1) { X(rd)[i] = X(rs1)[2*i] X(rd)[i+xlen/2] = X(rs1)[2*i+1] } --", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > unzip", + "line_range": [ + 3136, + 3144 + ] + }, + { + "text": ".Software Hint [NOTE, caption=\"SH\" ] This instruction is useful for implementing the SHA3 cryptographic hash function on a 32-bit architecture, as it implements the bit-interleaving operation used to speed up the 64-bit rotations directly.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > unzip", + "line_range": [ + 3146, + 3153 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > unzip", + "line_range": [ + 3155, + 3160 + ] + }, + { + "text": "|Zbkb () (RV32) |v1.0 |Ratified |", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > unzip", + "line_range": [ + 3162, + 3165 + ] + }, + { + "text": "<<< [insns-xnor,reftext=\"Exclusive NOR\"]", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > unzip", + "line_range": [ + 3167, + 3168 + ] + }, + { + "text": "Mnemonic:: xnor rd, rs1, rs2", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > xnor", + "line_range": [ + 3174, + 3175 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0x33, attr: ['OP'] }, { bits: 5, name: 'rd' }, { bits: 3, name: 0x4, attr: ['XNOR']}, { bits: 5, name: 'rs1' }, { bits: 5, name: 'rs2' }, { bits: 7, name: 0x20, attr: ['XNOR'] }, ]} ....", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > xnor", + "line_range": [ + 3177, + 3189 + ] + }, + { + "text": "Description:: This instruction performs the bit-wise exclusive-NOR operation on rs1 and rs2.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > xnor", + "line_range": [ + 3191, + 3192 + ] + }, + { + "text": "Operation:: [source,sail] -- X(rd) = ~(X(rs1) ^ X(rs2)); --", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > xnor", + "line_range": [ + 3194, + 3199 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > xnor", + "line_range": [ + 3201, + 3206 + ] + }, + { + "text": "|Zbb (ext:zbb[]) |0.93 |Ratified", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > xnor", + "line_range": [ + 3208, + 3210 + ] + }, + { + "text": "|Zbkb () |v1.0 |Ratified |", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > xnor", + "line_range": [ + 3212, + 3215 + ] + }, + { + "text": "<<< [insns-xperm8,reftext=\"Crossbar permutation (bytes)\"]", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > xnor", + "line_range": [ + 3217, + 3218 + ] + }, + { + "text": "Synopsis:: Byte-wise lookup of indices into a vector in registers.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > xperm8", + "line_range": [ + 3221, + 3222 + ] + }, + { + "text": "Mnemonic:: xperm8 rd, rs1, rs2", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > xperm8", + "line_range": [ + 3224, + 3225 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 0x33, attr: ['OP'] }, {bits: 5, name: 'rd'}, {bits: 3, name: 0x4}, {bits: 5, name: 'rs1'}, {bits: 5, name: 'rs2'}, {bits: 7, name: 0x14}, ]} ....", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > xperm8", + "line_range": [ + 3227, + 3239 + ] + }, + { + "text": "Description:: The xperm8 instruction operates on bytes.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > xperm8", + "line_range": [ + 3241, + 3246 + ] + }, + { + "text": "The rs1 register contains a vector of XLEN/8 8-bit elements.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > xperm8", + "line_range": [ + 3241, + 3246 + ] + }, + { + "text": "The rs2 register contains a vector of XLEN/8 8-bit indexes.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > xperm8", + "line_range": [ + 3241, + 3246 + ] + }, + { + "text": "The result is each element in rs2 replaced by the indexed element in rs1, or zero if the index into rs2 is out of bounds.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > xperm8", + "line_range": [ + 3241, + 3246 + ] + }, + { + "text": "Operation:: [source,sail] -- val xperm8lookup : (bits(8), xlenbits) -> bits(8) function xperm8lookup (idx, lut) = { (lut >> (idx @ 0b000))[7..0] }", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > xperm8", + "line_range": [ + 3248, + 3255 + ] + }, + { + "text": "function clause execute ( XPERM8 (rs2,rs1,rd)) = { result : xlenbits = EXTZ(0b0); foreach(i from 0 to xlen by 8) { result[i+7..i] = xperm8lookup(X(rs2)[i+7..i], X(rs1)); }; X(rd) = result; RETIRESUCCESS } --", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > xperm8", + "line_range": [ + 3257, + 3265 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > xperm8", + "line_range": [ + 3267, + 3272 + ] + }, + { + "text": "|Zbkx () |v1.0 |Ratified |", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > xperm8", + "line_range": [ + 3274, + 3277 + ] + }, + { + "text": "<<< [insns-xperm4,reftext=\"Crossbar permutation (nibbles)\"]", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > xperm8", + "line_range": [ + 3279, + 3280 + ] + }, + { + "text": "Synopsis:: Nibble-wise lookup of indices into a vector.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > xperm4", + "line_range": [ + 3283, + 3284 + ] + }, + { + "text": "Mnemonic:: xperm4 rd, rs1, rs2", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > xperm4", + "line_range": [ + 3286, + 3287 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 0x33, attr: ['OP'] }, {bits: 5, name: 'rd'}, {bits: 3, name: 0x2}, {bits: 5, name: 'rs1'}, {bits: 5, name: 'rs2'}, {bits: 7, name: 0x14}, ]} ....", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > xperm4", + "line_range": [ + 3289, + 3301 + ] + }, + { + "text": "Description:: The xperm4 instruction operates on nibbles.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > xperm4", + "line_range": [ + 3303, + 3308 + ] + }, + { + "text": "The rs1 register contains a vector of XLEN/4 4-bit elements.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > xperm4", + "line_range": [ + 3303, + 3308 + ] + }, + { + "text": "The rs2 register contains a vector of XLEN/4 4-bit indexes.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > xperm4", + "line_range": [ + 3303, + 3308 + ] + }, + { + "text": "The result is each element in rs2 replaced by the indexed element in rs1, or zero if the index into rs2 is out of bounds.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > xperm4", + "line_range": [ + 3303, + 3308 + ] + }, + { + "text": "Operation:: [source,sail] -- val xperm4lookup : (bits(4), xlenbits) -> bits(4) function xperm4lookup (idx, lut) = { (lut >> (idx @ 0b00))[3..0] }", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > xperm4", + "line_range": [ + 3310, + 3317 + ] + }, + { + "text": "function clause execute ( XPERM4 (rs2,rs1,rd)) = { result : xlenbits = EXTZ(0b0); foreach(i from 0 to xlen by 4) { result[i+3..i] = xperm4lookup(X(rs2)[i+3..i], X(rs1)); }; X(rd) = result; RETIRESUCCESS } --", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > xperm4", + "line_range": [ + 3319, + 3327 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > xperm4", + "line_range": [ + 3329, + 3334 + ] + }, + { + "text": "|Zbkx () |v1.0 |Ratified |", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > xperm4", + "line_range": [ + 3336, + 3339 + ] + }, + { + "text": "<<< [insns-zexth,reftext=\"Zero-extend halfword\"]", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > xperm4", + "line_range": [ + 3341, + 3342 + ] + }, + { + "text": "Synopsis:: Zero-extend halfword", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > zext.h", + "line_range": [ + 3345, + 3346 + ] + }, + { + "text": "Encoding (RV32):: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0x33, attr: ['OP'] }, { bits: 5, name: 'rd' }, { bits: 3, name: 0x4, attr: ['ZEXT.H']}, { bits: 5, name: 'rs' }, { bits: 5, name: 0x00 }, { bits: 7, name: 0x04 }, ]} ....", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > zext.h", + "line_range": [ + 3351, + 3363 + ] + }, + { + "text": "Encoding (RV64):: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0x3b, attr: ['OP-32'] }, { bits: 5, name: 'rd' }, { bits: 3, name: 0x4, attr: ['ZEXT.H']}, { bits: 5, name: 'rs' }, { bits: 5, name: 0x00 }, { bits: 7, name: 0x04 }, ]} ....", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > zext.h", + "line_range": [ + 3365, + 3377 + ] + }, + { + "text": "Description:: This instruction zero-extends the least-significant halfword of the source to XLEN by inserting 0's into all of the bits more significant than 15.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > zext.h", + "line_range": [ + 3379, + 3380 + ] + }, + { + "text": "Operation:: [source,sail] -- X(rd) = EXTZ(X(rs)[15..0]); --", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > zext.h", + "line_range": [ + 3382, + 3387 + ] + }, + { + "text": ".Note [NOTE, caption=\"A\" ] The *zext.h* mnemonic corresponds to different instruction encodings in RV32 and RV64.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > zext.h", + "line_range": [ + 3389, + 3393 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > zext.h", + "line_range": [ + 3395, + 3400 + ] + }, + { + "text": "|Zbb (ext:zbb[]) |0.93 |Ratified |", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > zext.h", + "line_range": [ + 3402, + 3405 + ] + }, + { + "text": "<<< [insns-zip,reftext=\"Bit interleave\"]", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > zext.h", + "line_range": [ + 3407, + 3408 + ] + }, + { + "text": "Synopsis:: Interleave upper and lower halves of the source register into odd and even bits of the destination register, respectively.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > zip", + "line_range": [ + 3411, + 3413 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 0x13, attr: ['OP-IMM']}, {bits: 5, name: 'rd'}, {bits: 3, name: 0x1}, {bits: 5, name: 'rs1'}, {bits: 5, name: 0xf}, {bits: 7, name: 0x4}, ]} ....", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > zip", + "line_range": [ + 3418, + 3430 + ] + }, + { + "text": "Description:: This instruction gathers bits from the high and low halves of the source word into odd/even bit positions in the destination word.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > zip", + "line_range": [ + 3432, + 3436 + ] + }, + { + "text": "It is the inverse of the instruction.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > zip", + "line_range": [ + 3432, + 3436 + ] + }, + { + "text": "This instruction is available only on RV32.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > zip", + "line_range": [ + 3432, + 3436 + ] + }, + { + "text": "Operation:: [source,sail] -- foreach (i from 0 to xlen/2-1) { X(rd)[2*i] = X(rs1)[i] X(rd)[2*i+1] = X(rs1)[i+xlen/2] } --", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > zip", + "line_range": [ + 3438, + 3446 + ] + }, + { + "text": ".Software Hint [NOTE, caption=\"SH\" ] This instruction is useful for implementing the SHA3 cryptographic hash function on a 32-bit architecture, as it implements the bit-interleaving operation used to speed up the 64-bit rotations directly.", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > zip", + "line_range": [ + 3448, + 3455 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > zip", + "line_range": [ + 3457, + 3462 + ] + }, + { + "text": "|Zbkb () (RV32) |v1.0 |Ratified |", + "section": "Preamble > Bit Manipulation Extensions > Instructions (in alphabetical order) > zip", + "line_range": [ + 3464, + 3467 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__c-st-ext.json b/tools/llm-extraction/data/output/raw_chunks/src__c-st-ext.json new file mode 100644 index 0000000000..0e434b6adb --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__c-st-ext.json @@ -0,0 +1,1502 @@ +{ + "source_file": "src/c-st-ext.adoc", + "total": 187, + "sentences": [ + { + "text": "This chapter describes the RISC-V standard compressed instruction-set extension, named \"C\", which reduces static and dynamic code size by adding short 16-bit instruction encodings for common operations.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0", + "line_range": [ + 3, + 9 + ] + }, + { + "text": "The C extension can be added to any of the base ISAs (RV32I, RV32E, RV64I, RV64E), and we use the generic term \"RVC\" to cover any of these.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0", + "line_range": [ + 3, + 9 + ] + }, + { + "text": "Typically, 50%-60% of the RISC-V instructions in a program can be replaced with RVC instructions, resulting in a 25%-30% code-size reduction.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0", + "line_range": [ + 3, + 9 + ] + }, + { + "text": "RVC uses a simple compression scheme that offers shorter 16-bit versions of common 32-bit RISC-V instructions when:", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Overview", + "line_range": [ + 13, + 14 + ] + }, + { + "text": "the immediate or address offset is small, or * one of the registers is the zero register (`x0`), the ABI link register (`x1`), or the ABI stack pointer (`x2`), or * the destination register and the first source register are identical, or * the registers used are the 8 most popular ones.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Overview", + "line_range": [ + 16, + 20 + ] + }, + { + "text": "The C extension is compatible with all other standard instruction extensions.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Overview", + "line_range": [ + 22, + 27 + ] + }, + { + "text": "The C extension allows 16-bit instructions to be freely intermixed with 32-bit instructions, with the latter now able to start on any 16-bit boundary, i.e., IALIGN=16.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Overview", + "line_range": [ + 22, + 27 + ] + }, + { + "text": "With the addition of the C extension, no instructions can raise instruction-address-misaligned exceptions.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Overview", + "line_range": [ + 22, + 27 + ] + }, + { + "text": "The compressed instruction encodings are mostly common across RV32C and RV64C, but as shown in , a few opcodes are used for different purposes depending on base ISA.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Overview", + "line_range": [ + 29, + 41 + ] + }, + { + "text": "For example, the wider address-space RV64C variant requires additional opcodes to compress loads and stores of 64-bit integer values, while RV32C uses the same opcodes to compress loads and stores of single-precision floating-point values.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Overview", + "line_range": [ + 29, + 41 + ] + }, + { + "text": "If the C extension is implemented, the appropriate compressed floating-point load and store instructions must be provided whenever the relevant standard floating-point extension (F and/or D) is also implemented.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Overview", + "line_range": [ + 29, + 41 + ] + }, + { + "text": "In addition, RV32C includes a compressed jump and link instruction to compress short-range subroutine calls, where the same opcode is used to compress ADDIW for RV64C.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Overview", + "line_range": [ + 29, + 41 + ] + }, + { + "text": "RVC was designed under the constraint that each RVC instruction expands into a single 32-bit instruction in either the base ISA (RV32I/E or RV64I/E) or the F and D standard extensions where present.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Overview", + "line_range": [ + 43, + 46 + ] + }, + { + "text": "Adopting this constraint has two main benefits:", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Overview", + "line_range": [ + 43, + 46 + ] + }, + { + "text": "Hardware designs can simply expand RVC instructions during decode, simplifying verification and minimizing modifications to existing microarchitectures.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Overview", + "line_range": [ + 48, + 50 + ] + }, + { + "text": "Compilers can be unaware of the RVC extension and leave code compression to the assembler and linker, although a compression-aware compiler will generally be able to produce better results.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Overview", + "line_range": [ + 52, + 54 + ] + }, + { + "text": "It is important to note that the C extension is not designed to be a stand-alone ISA, and is meant to be used alongside a base ISA.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Overview", + "line_range": [ + 56, + 57 + ] + }, + { + "text": "shows the nine compressed instruction formats. CR, CI, and CSS can use any of the 32 RVI registers, but CIW, CL, CS, CA, and CB are limited to just 8 of them. lists these popular registers, which correspond to registers `x8` to `x15`.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Compressed Instruction Formats", + "line_range": [ + 63, + 72 + ] + }, + { + "text": "Note that there is a separate version of load and store instructions that use the stack pointer as the base address register, since saving to and restoring from the stack are so prevalent, and that they use the CI and CSS formats to allow access to all 32 data registers. CIW supplies an 8-bit immediate for the ADDI4SPN instruction.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Compressed Instruction Formats", + "line_range": [ + 63, + 72 + ] + }, + { + "text": "Compressed register-based floating-point loads and stores also use the CL and CS formats respectively, with the eight registers mapping to `f8` to `f15`. ) ) The formats were designed to keep bits for the two register source specifiers in the same place in all instructions, while the destination register field can move.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Compressed Instruction Formats", + "line_range": [ + 74, + 87 + ] + }, + { + "text": "When the full 5-bit destination register specifier is present, it is in the same place as in the 32-bit RISC-V encoding.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Compressed Instruction Formats", + "line_range": [ + 74, + 87 + ] + }, + { + "text": "Where immediates are sign-extended, the sign extension is always from bit 12.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Compressed Instruction Formats", + "line_range": [ + 74, + 87 + ] + }, + { + "text": "Immediate fields have been scrambled, as in the base specification, to reduce the number of immediate multiplexers required.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Compressed Instruction Formats", + "line_range": [ + 74, + 87 + ] + }, + { + "text": "For many RVC instructions, zero-valued immediates are disallowed and `x0` is not a valid 5-bit register specifier.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Compressed Instruction Formats", + "line_range": [ + 74, + 87 + ] + }, + { + "text": "These restrictions free up encoding space for other instructions requiring fewer operand bits.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Compressed Instruction Formats", + "line_range": [ + 74, + 87 + ] + }, + { + "text": ".Compressed 16-bit RVC instruction formats // [float=\"center\",align=\"center\",cols=\"1a, 2a\",frame=\"none\",grid=\"none\"] | | ! !Format ! Meaning !CR ! Register !CI ! Immediate !CSS ! Stack-relative Store !CIW ! Wide Immediate !CL ! Load !CS ! Store !CA ! Arithmetic !CB ! Branch/Arithmetic !CJ ! Jump ! | [float=\"left\",align=\"left\",cols=\"1,1,1,1,1,1,1\",options=\"noheader\"] ! ^!15 14 13 ^!12 ^!11 10 ^!9 8 7 ^!6 5 ^!4 3 2 ^!1 0 2+^!funct4 2+^!rd/rs1 2+^!rs2 ^! op ^!funct3 ^!imm 2+^!rd/rs1 2+^!imm ^! op ^!funct3 3+^!imm 2+^!rs2 ^! op ^!funct3 4+^!imm ^!rd{prime} ^! op ^!funct3 2+^!imm ^!rs1{prime} ^!imm ^!rd{prime} ^! op ^!funct3 2+^!imm ^!rs1{prime} ^! imm ^!rs2{prime} ^! op 3+^!funct6 ^!rd{prime}/rs1{prime} ^!funct2 ^!rs2{prime} ^! op ^!funct3 2+^!offset ^!rd{prime}/rs1{prime} 2+^!offset ^! op ^!funct3 5+^!jump target ^! op ! |", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Compressed Instruction Formats", + "line_range": [ + 94, + 127 + ] + }, + { + "text": ".Registers specified by the three-bit rs1{prime}, rs2{prime}, and rd{prime} fields of the CIW, CL, CS, CA, and CB formats. //[cols=\"20%,10%,10%,10%,10%,10%,10%,10%,10%\"] [float=\"center\",align=\"center\",cols=\"1a, 1a\",frame=\"none\",grid=\"none\"] | | ! !RVC Register Number !Integer Register Number !Integer Register ABI Name !Floating-Point Register Number !Floating-Point Register ABI Name ! |", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Compressed Instruction Formats", + "line_range": [ + 129, + 143 + ] + }, + { + "text": "! !`000` !`001` !`010` !`011` !`100` !`101` !`110` !`111` !`x8` !`x9` !`x10` !`x11` !`x12` !`x13` !`x14`!`x15` !`s0` !`s1` !`a0` !`a1` !`a2` !`a3` !`a4`!`a5` !`f8` !`f9` !`f10` !`f11` !`f12` !`f13`!`f14` !`f15` !`fs0` !`fs1` !`fa0` !`fa1` !`fa2`!`fa3` !`fa4` !`fa5` ! |", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Compressed Instruction Formats", + "line_range": [ + 145, + 153 + ] + }, + { + "text": "To increase the reach of 16-bit instructions, data-transfer instructions use zero-extended immediates that are scaled by the size of the data in bytes: ×4 for words, ×8 for double words, and ×16 for quad words.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Load and Store Instructions", + "line_range": [ + 157, + 160 + ] + }, + { + "text": "RVC provides two variants of loads and stores.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Load and Store Instructions", + "line_range": [ + 162, + 165 + ] + }, + { + "text": "One uses the ABI stack pointer, `x2`, as the base address and can target any data register.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Load and Store Instructions", + "line_range": [ + 162, + 165 + ] + }, + { + "text": "The other can reference one of 8 base address registers and one of 8 data registers.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Load and Store Instructions", + "line_range": [ + 162, + 165 + ] + }, + { + "text": "These instructions use the CI format.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Load and Store Instructions > Stack-Pointer-Based Loads and Stores", + "line_range": [ + 173, + 173 + ] + }, + { + "text": "C.LWSP loads a 32-bit value from memory into register rd.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Load and Store Instructions > Stack-Pointer-Based Loads and Stores", + "line_range": [ + 175, + 179 + ] + }, + { + "text": "It computes an effective address by adding the zero-extended offset, scaled by 4, to the stack pointer, `x2`.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Load and Store Instructions > Stack-Pointer-Based Loads and Stores", + "line_range": [ + 175, + 179 + ] + }, + { + "text": "It expands to `lw rd, offset(x2)`. C.LWSP is valid only when rd!=`x0`; the code points with rd=`x0` are reserved.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Load and Store Instructions > Stack-Pointer-Based Loads and Stores", + "line_range": [ + 175, + 179 + ] + }, + { + "text": "C.LDSP is an RV64C-only instruction that loads a 64-bit value from memory into register rd.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Load and Store Instructions > Stack-Pointer-Based Loads and Stores", + "line_range": [ + 181, + 187 + ] + }, + { + "text": "It computes its effective address by adding the zero-extended offset, scaled by 8, to the stack pointer, `x2`.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Load and Store Instructions > Stack-Pointer-Based Loads and Stores", + "line_range": [ + 181, + 187 + ] + }, + { + "text": "It expands to `ld rd, offset(x2)`. C.LDSP is valid only when rd!=`x0`; the code points with rd=`x0` are reserved.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Load and Store Instructions > Stack-Pointer-Based Loads and Stores", + "line_range": [ + 181, + 187 + ] + }, + { + "text": "C.FLWSP is an RV32FC-only instruction that loads a single-precision floating-point value from memory into floating-point register rd.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Load and Store Instructions > Stack-Pointer-Based Loads and Stores", + "line_range": [ + 189, + 193 + ] + }, + { + "text": "It computes its effective address by adding the zero-extended offset, scaled by 4, to the stack pointer, `x2`.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Load and Store Instructions > Stack-Pointer-Based Loads and Stores", + "line_range": [ + 189, + 193 + ] + }, + { + "text": "It expands to `flw rd, offset(x2)`.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Load and Store Instructions > Stack-Pointer-Based Loads and Stores", + "line_range": [ + 189, + 193 + ] + }, + { + "text": "C.FLDSP is an RV32DC/RV64DC-only instruction that loads a double-precision floating-point value from memory into floating-point register rd.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Load and Store Instructions > Stack-Pointer-Based Loads and Stores", + "line_range": [ + 195, + 199 + ] + }, + { + "text": "It computes its effective address by adding the zero-extended offset, scaled by 8, to the stack pointer, `x2`.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Load and Store Instructions > Stack-Pointer-Based Loads and Stores", + "line_range": [ + 195, + 199 + ] + }, + { + "text": "It expands to `fld rd, offset(x2)`.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Load and Store Instructions > Stack-Pointer-Based Loads and Stores", + "line_range": [ + 195, + 199 + ] + }, + { + "text": "These instructions use the CSS format.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Load and Store Instructions > Stack-Pointer-Based Loads and Stores", + "line_range": [ + 205, + 205 + ] + }, + { + "text": "C.SWSP stores a 32-bit value in register rs2 to memory.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Load and Store Instructions > Stack-Pointer-Based Loads and Stores", + "line_range": [ + 207, + 209 + ] + }, + { + "text": "It computes an effective address by adding the zero-extended offset, scaled by 4, to the stack pointer, `x2`.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Load and Store Instructions > Stack-Pointer-Based Loads and Stores", + "line_range": [ + 207, + 209 + ] + }, + { + "text": "It expands to `sw rs2, offset(x2)`.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Load and Store Instructions > Stack-Pointer-Based Loads and Stores", + "line_range": [ + 207, + 209 + ] + }, + { + "text": "C.SDSP is an RV64C-only instruction that stores a 64-bit value in register rs2 to memory.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Load and Store Instructions > Stack-Pointer-Based Loads and Stores", + "line_range": [ + 211, + 214 + ] + }, + { + "text": "It computes an effective address by adding the zero-extended offset, scaled by 8, to the stack pointer, `x2`.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Load and Store Instructions > Stack-Pointer-Based Loads and Stores", + "line_range": [ + 211, + 214 + ] + }, + { + "text": "It expands to `sd rs2, offset(x2)`.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Load and Store Instructions > Stack-Pointer-Based Loads and Stores", + "line_range": [ + 211, + 214 + ] + }, + { + "text": "C.FSWSP is an RV32FC-only instruction that stores a single-precision floating-point value in floating-point register rs2 to memory.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Load and Store Instructions > Stack-Pointer-Based Loads and Stores", + "line_range": [ + 216, + 220 + ] + }, + { + "text": "It computes an effective address by adding the zero-extended offset, scaled by 4, to the stack pointer, `x2`.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Load and Store Instructions > Stack-Pointer-Based Loads and Stores", + "line_range": [ + 216, + 220 + ] + }, + { + "text": "It expands to `fsw rs2, offset(x2)`.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Load and Store Instructions > Stack-Pointer-Based Loads and Stores", + "line_range": [ + 216, + 220 + ] + }, + { + "text": "C.FSDSP is an RV32DC/RV64DC-only instruction that stores a double-precision floating-point value in floating-point register rs2 to memory.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Load and Store Instructions > Stack-Pointer-Based Loads and Stores", + "line_range": [ + 222, + 226 + ] + }, + { + "text": "It computes an effective address by adding the zero-extended offset, scaled by 8, to the stack pointer, `x2`.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Load and Store Instructions > Stack-Pointer-Based Loads and Stores", + "line_range": [ + 222, + 226 + ] + }, + { + "text": "It expands to `fsd rs2, offset(x2)`.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Load and Store Instructions > Stack-Pointer-Based Loads and Stores", + "line_range": [ + 222, + 226 + ] + }, + { + "text": "include::images/wavedrom/reg-based-ldnstr.edn[] //.Compressed, register-based load and stores--these instructions use the CL format.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Load and Store Instructions > Register-Based Loads and Stores", + "line_range": [ + 230, + 234 + ] + }, + { + "text": "These instructions use the CL format.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Load and Store Instructions > Register-Based Loads and Stores", + "line_range": [ + 230, + 234 + ] + }, + { + "text": "C.LW loads a 32-bit value from memory into register `rd′`.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Load and Store Instructions > Register-Based Loads and Stores", + "line_range": [ + 236, + 239 + ] + }, + { + "text": "It computes an effective address by adding the zero-extended offset, scaled by 4, to the base address in register `rs1′`.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Load and Store Instructions > Register-Based Loads and Stores", + "line_range": [ + 236, + 239 + ] + }, + { + "text": "It expands to `lw rd′, offset(rs1′)`.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Load and Store Instructions > Register-Based Loads and Stores", + "line_range": [ + 236, + 239 + ] + }, + { + "text": "C.LD is an RV64C-only instruction that loads a 64-bit value from memory into register `rd′`.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Load and Store Instructions > Register-Based Loads and Stores", + "line_range": [ + 241, + 245 + ] + }, + { + "text": "It computes an effective address by adding the zero-extended offset, scaled by 8, to the base address in register `rs1′`.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Load and Store Instructions > Register-Based Loads and Stores", + "line_range": [ + 241, + 245 + ] + }, + { + "text": "It expands to `ld rd′, offset(rs1′)`.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Load and Store Instructions > Register-Based Loads and Stores", + "line_range": [ + 241, + 245 + ] + }, + { + "text": "C.FLW is an RV32FC-only instruction that loads a single-precision floating-point value from memory into floating-point register `rd′`.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Load and Store Instructions > Register-Based Loads and Stores", + "line_range": [ + 247, + 252 + ] + }, + { + "text": "It computes an effective address by adding the zero-extended offset, scaled by 4, to the base address in register `rs1′`.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Load and Store Instructions > Register-Based Loads and Stores", + "line_range": [ + 247, + 252 + ] + }, + { + "text": "It expands to `flw rd′, offset(rs1′)`.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Load and Store Instructions > Register-Based Loads and Stores", + "line_range": [ + 247, + 252 + ] + }, + { + "text": "C.FLD is an RV32DC/RV64DC-only instruction that loads a double-precision floating-point value from memory into floating-point register `rd′`.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Load and Store Instructions > Register-Based Loads and Stores", + "line_range": [ + 254, + 259 + ] + }, + { + "text": "It computes an effective address by adding the zero-extended offset, scaled by 8, to the base address in register `rs1′`.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Load and Store Instructions > Register-Based Loads and Stores", + "line_range": [ + 254, + 259 + ] + }, + { + "text": "It expands to `fld rd′, offset(rs1′)`.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Load and Store Instructions > Register-Based Loads and Stores", + "line_range": [ + 254, + 259 + ] + }, + { + "text": "include::images/wavedrom/c-cs-format-ls.edn[] //.Compressed, CS format load and store--these instructions use the CS format.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Load and Store Instructions > Register-Based Loads and Stores", + "line_range": [ + 261, + 264 + ] + }, + { + "text": "These instructions use the CS format.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Load and Store Instructions > Register-Based Loads and Stores", + "line_range": [ + 266, + 266 + ] + }, + { + "text": "C.SW stores a 32-bit value in register `rs2′` to memory.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Load and Store Instructions > Register-Based Loads and Stores", + "line_range": [ + 268, + 271 + ] + }, + { + "text": "It computes an effective address by adding the zero-extended offset, scaled by 4, to the base address in register `rs1′`.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Load and Store Instructions > Register-Based Loads and Stores", + "line_range": [ + 268, + 271 + ] + }, + { + "text": "It expands to `sw rs2′, offset(rs1′)`.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Load and Store Instructions > Register-Based Loads and Stores", + "line_range": [ + 268, + 271 + ] + }, + { + "text": "C.SD is an RV64C-only instruction that stores a 64-bit value in register `rs2′` to memory.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Load and Store Instructions > Register-Based Loads and Stores", + "line_range": [ + 273, + 277 + ] + }, + { + "text": "It computes an effective address by adding the zero-extended offset, scaled by 8, to the base address in register `rs1′`.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Load and Store Instructions > Register-Based Loads and Stores", + "line_range": [ + 273, + 277 + ] + }, + { + "text": "It expands to `sd rs2′, offset(rs1′)`.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Load and Store Instructions > Register-Based Loads and Stores", + "line_range": [ + 273, + 277 + ] + }, + { + "text": "C.FSW is an RV32FC-only instruction that stores a single-precision floating-point value in floating-point register `rs2′` to memory.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Load and Store Instructions > Register-Based Loads and Stores", + "line_range": [ + 279, + 284 + ] + }, + { + "text": "It computes an effective address by adding the zero-extended offset, scaled by 4, to the base address in register `rs1′`.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Load and Store Instructions > Register-Based Loads and Stores", + "line_range": [ + 279, + 284 + ] + }, + { + "text": "It expands to `fsw rs2′, offset(rs1′)`.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Load and Store Instructions > Register-Based Loads and Stores", + "line_range": [ + 279, + 284 + ] + }, + { + "text": "C.FSD is an RV32DC/RV64DC-only instruction that stores a double-precision floating-point value in floating-point register `rs2′` to memory.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Load and Store Instructions > Register-Based Loads and Stores", + "line_range": [ + 286, + 291 + ] + }, + { + "text": "It computes an effective address by adding the zero-extended offset, scaled by 8, to the base address in register `rs1′`.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Load and Store Instructions > Register-Based Loads and Stores", + "line_range": [ + 286, + 291 + ] + }, + { + "text": "It expands to `fsd rs2′, offset(rs1′)`.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Load and Store Instructions > Register-Based Loads and Stores", + "line_range": [ + 286, + 291 + ] + }, + { + "text": "RVC provides unconditional jump instructions and conditional branch instructions.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Control Transfer Instructions", + "line_range": [ + 295, + 297 + ] + }, + { + "text": "As with base RVI instructions, the offsets of all RVC control transfer instructions are in multiples of 2 bytes.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Control Transfer Instructions", + "line_range": [ + 295, + 297 + ] + }, + { + "text": "include::images/wavedrom/c-cj-format-ls.edn[] //.Compressed, CJ format load and store--these instructions use the CJ format.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Control Transfer Instructions", + "line_range": [ + 299, + 302 + ] + }, + { + "text": "These instructions use the CJ format.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Control Transfer Instructions", + "line_range": [ + 304, + 304 + ] + }, + { + "text": "C.J performs an unconditional control transfer.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Control Transfer Instructions", + "line_range": [ + 306, + 309 + ] + }, + { + "text": "The offset is sign-extended and added to the `pc` to form the jump target address. C.J can therefore target a {pm}2 KiB range. C.J expands to `jal x0, offset`.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Control Transfer Instructions", + "line_range": [ + 306, + 309 + ] + }, + { + "text": "C.JAL is an RV32C-only instruction that performs the same operation as C.J, but additionally writes the address of the instruction following the jump (`pc+2`) to the link register, `x1`. C.JAL expands to `jal x1, offset`.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Control Transfer Instructions", + "line_range": [ + 311, + 314 + ] + }, + { + "text": "include::images/wavedrom/c-cr-format-ls.edn[] //.Compressed, CR format load and store--these instructions use the CR format.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Control Transfer Instructions", + "line_range": [ + 316, + 319 + ] + }, + { + "text": "These instructions use the CR format.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Control Transfer Instructions", + "line_range": [ + 321, + 321 + ] + }, + { + "text": "C.JR (jump register) performs an unconditional control transfer to the address in register rs1. C.JR expands to `jalr x0, 0(rs1)`. C.JR is valid only when rs1!=`x0`; the code point with rs1=`x0` is reserved.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Control Transfer Instructions", + "line_range": [ + 323, + 327 + ] + }, + { + "text": "C.JALR (jump and link register) performs the same operation as C.JR, but additionally writes the address of the instruction following the jump (`pc`+2) to the link register, `x1`. C.JALR expands to `jalr x1, 0(rs1)`. C.JALR is valid only when rs1!=`x0`; the code point with rs1=`x0` corresponds to the C.EBREAK instruction.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Control Transfer Instructions", + "line_range": [ + 329, + 336 + ] + }, + { + "text": "include::images/wavedrom/c-cb-format-ls.edn[] //.Compressed, CB format load and store--these instructions use the CB format.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Control Transfer Instructions", + "line_range": [ + 338, + 341 + ] + }, + { + "text": "These instructions use the CB format.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Control Transfer Instructions", + "line_range": [ + 343, + 343 + ] + }, + { + "text": "C.BEQZ performs conditional control transfers.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Control Transfer Instructions", + "line_range": [ + 345, + 349 + ] + }, + { + "text": "The offset is sign-extended and added to the `pc` to form the branch target address.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Control Transfer Instructions", + "line_range": [ + 345, + 349 + ] + }, + { + "text": "It can therefore target a {pm}256 B range. C.BEQZ takes the branch if the value in register rs1′ is zero.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Control Transfer Instructions", + "line_range": [ + 345, + 349 + ] + }, + { + "text": "It expands to `beq rs1′, x0, offset`.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Control Transfer Instructions", + "line_range": [ + 345, + 349 + ] + }, + { + "text": "C.BNEZ is defined analogously, but it takes the branch if rs1′ contains a nonzero value.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Control Transfer Instructions", + "line_range": [ + 351, + 353 + ] + }, + { + "text": "It expands to `bne rs1′, x0, offset`.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Control Transfer Instructions", + "line_range": [ + 351, + 353 + ] + }, + { + "text": "RVC provides several instructions for integer arithmetic and constant generation.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Integer Computational Instructions", + "line_range": [ + 357, + 358 + ] + }, + { + "text": "The two constant-generation instructions both use the CI instruction format and can target any integer register.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Integer Computational Instructions > Integer Constant-Generation Instructions", + "line_range": [ + 362, + 363 + ] + }, + { + "text": "include::images/wavedrom/c-integer-const-gen.edn[] //.Integer constant generation format.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Integer Computational Instructions > Integer Constant-Generation Instructions", + "line_range": [ + 365, + 368 + ] + }, + { + "text": "C.LI loads the sign-extended 6-bit immediate, imm, into register rd. C.LI expands into `addi rd, x0, imm`.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Integer Computational Instructions > Integer Constant-Generation Instructions", + "line_range": [ + 370, + 372 + ] + }, + { + "text": "The C.LI code points with rd=`x0` are HINTs.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Integer Computational Instructions > Integer Constant-Generation Instructions", + "line_range": [ + 370, + 372 + ] + }, + { + "text": "C.LUI loads the non-zero 6-bit immediate field into bits 17–12 of the destination register, clears the bottom 12 bits, and sign-extends bit 17 into all higher bits of the destination. C.LUI expands into `lui rd, imm`. C.LUI is valid only when rd!=`x2`, and when the immediate is not equal to zero.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Integer Computational Instructions > Integer Constant-Generation Instructions", + "line_range": [ + 374, + 384 + ] + }, + { + "text": "The code points with imm=0 are reserved.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Integer Computational Instructions > Integer Constant-Generation Instructions", + "line_range": [ + 374, + 384 + ] + }, + { + "text": "The code points with rd=`x2` and imm!=0 correspond to the C.ADDI16SP instruction.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Integer Computational Instructions > Integer Constant-Generation Instructions", + "line_range": [ + 374, + 384 + ] + }, + { + "text": "The code points with rd=`x0` and imm!=0 are HINTs.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Integer Computational Instructions > Integer Constant-Generation Instructions", + "line_range": [ + 374, + 384 + ] + }, + { + "text": "These integer register-immediate operations are encoded in the CI format and perform operations on an integer register and a 6-bit immediate.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Integer Computational Instructions > Integer Register-Immediate Operations", + "line_range": [ + 389, + 390 + ] + }, + { + "text": "include::images/wavedrom/c-int-reg-immed.edn[] //.Integer register-immediate format.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Integer Computational Instructions > Integer Register-Immediate Operations", + "line_range": [ + 392, + 395 + ] + }, + { + "text": "C.ADDI adds the non-zero sign-extended 6-bit immediate to the value in register rd then writes the result to rd. C.ADDI expands into `addi rd, rd, imm`.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Integer Computational Instructions > Integer Register-Immediate Operations", + "line_range": [ + 397, + 402 + ] + }, + { + "text": "The code points with rd!=0 and imm=0 are HINTs.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Integer Computational Instructions > Integer Register-Immediate Operations", + "line_range": [ + 397, + 402 + ] + }, + { + "text": "The code points with rd=`x0` encode the C.NOP instruction, of which the code points with imm!=0 are HINTs.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Integer Computational Instructions > Integer Register-Immediate Operations", + "line_range": [ + 397, + 402 + ] + }, + { + "text": "C.ADDIW is an RV64C-only instruction that performs the same computation but produces a 32-bit result, then sign-extends result to 64 bits. C.ADDIW expands into `addiw rd, rd, imm`.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Integer Computational Instructions > Integer Register-Immediate Operations", + "line_range": [ + 404, + 410 + ] + }, + { + "text": "The immediate can be zero for C.ADDIW, where this corresponds to `sext.w rd`. C.ADDIW is valid only when rd!=`x0`; the code points with rd=`x0` are reserved.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Integer Computational Instructions > Integer Register-Immediate Operations", + "line_range": [ + 404, + 410 + ] + }, + { + "text": "C.ADDI16SP (add immediate to stack pointer) shares the opcode with C.LUI, but has a destination field of `x2`. C.ADDI16SP adds the non-zero sign-extended 6-bit immediate to the value in the stack pointer (`sp=x2`), where the immediate is scaled to represent multiples of 16 in the range [-512, 496]. C.ADDI16SP is used to adjust the stack pointer in procedure prologues and epilogues.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Integer Computational Instructions > Integer Register-Immediate Operations", + "line_range": [ + 412, + 420 + ] + }, + { + "text": "It expands into `addi x2, x2, nzimm[9:4]`. C.ADDI16SP is valid only when nzimm!=0; the code point with nzimm=0 is reserved.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Integer Computational Instructions > Integer Register-Immediate Operations", + "line_range": [ + 412, + 420 + ] + }, + { + "text": "include::images/wavedrom/c-ciw.edn[] //.CIW format. C.ADDI4SPN (add immediate to stack pointer, non-destructive) is a CIW-format instruction that adds a zero-extended non-zero immediate, scaled by 4, to the stack pointer, `x2`, and writes the result to `rd′`.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Integer Computational Instructions > Integer Register-Immediate Operations", + "line_range": [ + 422, + 434 + ] + }, + { + "text": "This instruction is used to generate pointers to stack-allocated variables, and expands to `addi rd′, x2, nzuimm[9:2]`. C.ADDI4SPN is valid only when nzuimm!=0; the code points with nzuimm=0 are reserved.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Integer Computational Instructions > Integer Register-Immediate Operations", + "line_range": [ + 422, + 434 + ] + }, + { + "text": "include::images/wavedrom/c-ci.edn[] //.CI format.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Integer Computational Instructions > Integer Register-Immediate Operations", + "line_range": [ + 436, + 439 + ] + }, + { + "text": "C.SLLI is a CI-format instruction that performs a logical left shift of the value in register rd then writes the result to rd.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Integer Computational Instructions > Integer Register-Immediate Operations", + "line_range": [ + 441, + 444 + ] + }, + { + "text": "The shift amount is encoded in the shamt field. C.SLLI expands into `slli rd, rd, shamt[5:0]`.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Integer Computational Instructions > Integer Register-Immediate Operations", + "line_range": [ + 441, + 444 + ] + }, + { + "text": "The C.SLLI code points with shamt=0 or with rd=`x0` are HINTs.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Integer Computational Instructions > Integer Register-Immediate Operations", + "line_range": [ + 446, + 446 + ] + }, + { + "text": "For RV32C, shamt[5] must be zero; the code points with shamt[5]=1 are designated for custom extensions.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Integer Computational Instructions > Integer Register-Immediate Operations", + "line_range": [ + 448, + 449 + ] + }, + { + "text": "C.SRLI is a CB-format instruction that performs a logical right shift of the value in register rd′ then writes the result to rd′.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Integer Computational Instructions > Integer Register-Immediate Operations", + "line_range": [ + 457, + 460 + ] + }, + { + "text": "The shift amount is encoded in the shamt field. C.SRLI expands into `srli rd′, rd′, shamt`.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Integer Computational Instructions > Integer Register-Immediate Operations", + "line_range": [ + 457, + 460 + ] + }, + { + "text": "The C.SRLI code points with shamt=0 are HINTs.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Integer Computational Instructions > Integer Register-Immediate Operations", + "line_range": [ + 462, + 462 + ] + }, + { + "text": "For RV32C, shamt[5] must be zero; the code points with shamt[5]=1 are designated for custom extensions.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Integer Computational Instructions > Integer Register-Immediate Operations", + "line_range": [ + 464, + 465 + ] + }, + { + "text": "C.SRAI is defined analogously to C.SRLI, but instead performs an arithmetic right shift. C.SRAI expands to `srai rd′, rd′, shamt`.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Integer Computational Instructions > Integer Register-Immediate Operations", + "line_range": [ + 467, + 469 + ] + }, + { + "text": "include::images/wavedrom/c-andi.edn[] //.C.ANDI format", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Integer Computational Instructions > Integer Register-Immediate Operations", + "line_range": [ + 471, + 474 + ] + }, + { + "text": "C.ANDI is a CB-format instruction that computes the bitwise AND of the value in register rd′ and the sign-extended 6-bit immediate, then writes the result to rd′. C.ANDI expands to `andi rd′, rd′, imm`.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Integer Computational Instructions > Integer Register-Immediate Operations", + "line_range": [ + 476, + 479 + ] + }, + { + "text": "include::images/wavedrom/c-int-reg-to-reg-cr-format.edn[] //C.CR format ) These instructions use the CR format.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Integer Computational Instructions > Integer Register-Register Operations", + "line_range": [ + 484, + 488 + ] + }, + { + "text": "C.MV copies the value in register rs2 into register rd. C.MV expands into `add rd, x0, rs2`. C.MV is valid only when rs2!=`x0`; the code points with rs2=`x0` correspond to the C.JR instruction.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Integer Computational Instructions > Integer Register-Register Operations", + "line_range": [ + 490, + 494 + ] + }, + { + "text": "The code points with rs2!=`x0` and rd=`x0` are HINTs.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Integer Computational Instructions > Integer Register-Register Operations", + "line_range": [ + 490, + 494 + ] + }, + { + "text": "C.ADD adds the values in registers rd and rs2 and writes the result to register rd. C.ADD expands into `add rd, rd, rs2`. C.ADD is only valid when rs2!=`x0`; the code points with rs2=`x0` correspond to the C.JALR and C.EBREAK instructions.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Integer Computational Instructions > Integer Register-Register Operations", + "line_range": [ + 496, + 501 + ] + }, + { + "text": "The code points with rs2!=`x0` and rd=`x0` are HINTs.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Integer Computational Instructions > Integer Register-Register Operations", + "line_range": [ + 496, + 501 + ] + }, + { + "text": "include::images/wavedrom/c-int-reg-to-reg-ca-format.edn[] //C.CA format )", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Integer Computational Instructions > Integer Register-Register Operations", + "line_range": [ + 503, + 506 + ] + }, + { + "text": "These instructions use the CA format.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Integer Computational Instructions > Integer Register-Register Operations", + "line_range": [ + 508, + 508 + ] + }, + { + "text": "`C.AND` computes the bitwise `AND` of the values in registers rd′ and rs2′, then writes the result to register rd′. `C.AND` expands into `and rd′, rd′, rs2′`.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Integer Computational Instructions > Integer Register-Register Operations", + "line_range": [ + 510, + 513 + ] + }, + { + "text": "`C.OR` computes the bitwise `OR` of the values in registers rd′ and rs2′, then writes the result to register rd′. `C.OR` expands into `or rd′, rd′, rs2′`.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Integer Computational Instructions > Integer Register-Register Operations", + "line_range": [ + 515, + 518 + ] + }, + { + "text": "`C.XOR` computes the bitwise `XOR` of the values in registers rd′ and rs2′, then writes the result to register rd′. `C.XOR` expands into `xor rd′, rd′, rs2′`.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Integer Computational Instructions > Integer Register-Register Operations", + "line_range": [ + 520, + 523 + ] + }, + { + "text": "`C.SUB` subtracts the value in register rs2′ from the value in register rd′, then writes the result to register rd′. `C.SUB` expands into `sub rd′, rd′, rs2′`.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Integer Computational Instructions > Integer Register-Register Operations", + "line_range": [ + 525, + 528 + ] + }, + { + "text": "`C.ADDW` is an RV64C-only instruction that adds the values in registers rd′ and rs2′, then sign-extends the lower 32 bits of the sum before writing the result to register rd′. `C.ADDW` expands into `addw rd′, rd′, rs2′`.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Integer Computational Instructions > Integer Register-Register Operations", + "line_range": [ + 530, + 534 + ] + }, + { + "text": "`C.SUBW` is an RV64C-only instruction that subtracts the value in register rs2′ from the value in register rd′, then sign-extends the lower 32 bits of the difference before writing the result to register rd′. `C.SUBW` expands into `subw rd′, rd′, rs2′`.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Integer Computational Instructions > Integer Register-Register Operations", + "line_range": [ + 536, + 540 + ] + }, + { + "text": "include::images/wavedrom/c-def-illegal-inst.edn[] )", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Integer Computational Instructions > Defined Illegal Instruction", + "line_range": [ + 544, + 546 + ] + }, + { + "text": "A 16-bit instruction with all bits zero is permanently reserved as an illegal instruction.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Integer Computational Instructions > Defined Illegal Instruction", + "line_range": [ + 548, + 549 + ] + }, + { + "text": "include::images/wavedrom/c-nop-instr.edn[] )", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Integer Computational Instructions > NOP Instruction", + "line_range": [ + 553, + 555 + ] + }, + { + "text": "`C.NOP` is a CI-format instruction that does not change any user-visible state, except for advancing the `pc` and incrementing any applicable performance counters. `C.NOP` expands to `nop`.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Integer Computational Instructions > NOP Instruction", + "line_range": [ + 557, + 561 + ] + }, + { + "text": "The `C.NOP` code points with imm!=0 encode HINTs.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Integer Computational Instructions > NOP Instruction", + "line_range": [ + 557, + 561 + ] + }, + { + "text": "include::images/wavedrom/c-breakpoint-instr.edn[] )", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Integer Computational Instructions > Breakpoint Instruction", + "line_range": [ + 565, + 567 + ] + }, + { + "text": "Debuggers can use the `C.EBREAK` instruction, which expands to `ebreak`, to cause control to be transferred back to the debugging environment. `C.EBREAK` shares the opcode with the `C.ADD` instruction, but with rd and rs2 both zero, thus can also use the `CR` format.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Integer Computational Instructions > Breakpoint Instruction", + "line_range": [ + 569, + 572 + ] + }, + { + "text": "On implementations that support the C extension, compressed forms of the I instructions permitted inside constrained LR/SC sequences, as described in , are also permitted inside constrained LR/SC sequences.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > Usage of C Instructions in LR/SC Sequences", + "line_range": [ + 576, + 579 + ] + }, + { + "text": "A portion of the RVC encoding space is reserved for microarchitectural HINTs.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > HINT Instructions", + "line_range": [ + 584, + 589 + ] + }, + { + "text": "Like the HINTs in the RV32I base ISA (see ), these instructions do not modify any architectural state, except for advancing the `pc` and any applicable performance counters. HINTs are executed as no-ops on implementations that ignore them.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > HINT Instructions", + "line_range": [ + 584, + 589 + ] + }, + { + "text": "RVC HINTs are encoded as computational instructions that do not modify the architectural state, either because rd=`x0` (e.g. `C.ADD x0, t0`), or because rd is overwritten with a copy of itself (e.g. `C.ADDI t0, 0`).", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > HINT Instructions", + "line_range": [ + 591, + 594 + ] + }, + { + "text": "RVC HINTs do not necessarily expand to their RVI HINT counterparts.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > HINT Instructions", + "line_range": [ + 596, + 598 + ] + }, + { + "text": "For example, `C.ADD` x0, a0 might not encode the same HINT as `ADD` x0, x0, a0.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > HINT Instructions", + "line_range": [ + 596, + 598 + ] + }, + { + "text": "lists all RVC HINT code points.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > HINT Instructions", + "line_range": [ + 600, + 602 + ] + }, + { + "text": "For RV32C, 78% of the HINT space is reserved for standard HINTs.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > HINT Instructions", + "line_range": [ + 600, + 602 + ] + }, + { + "text": "The remainder of the HINT space is designated for custom HINTs; no standard HINTs will ever be defined in this subspace.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > HINT Instructions", + "line_range": [ + 600, + 602 + ] + }, + { + "text": ".RVC HINT instructions. [cols=\"<,<,>,<\",options=\"header\",] | |Instruction |Constraints |Code Points |Purpose", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > HINT Instructions", + "line_range": [ + 604, + 608 + ] + }, + { + "text": "|C.NOP |imm!=0 |63 .6+.^|Designated for future standard use", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > HINT Instructions", + "line_range": [ + 610, + 610 + ] + }, + { + "text": "|C.ADDI | rd!=`x0`, imm=0 |31", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > HINT Instructions", + "line_range": [ + 612, + 612 + ] + }, + { + "text": "|C.LUI | rd=`x0`, imm!=0 |63", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > HINT Instructions", + "line_range": [ + 616, + 616 + ] + }, + { + "text": "|C.MV | rd=`x0`, rs2!=`x0` |31", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > HINT Instructions", + "line_range": [ + 618, + 618 + ] + }, + { + "text": "|C.ADD | rd=`x0`, rs2!=`x0`, rs2!=`x2-x5` | 27", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > HINT Instructions", + "line_range": [ + 620, + 620 + ] + }, + { + "text": "|C.ADD | rd=`x0`, rs2=`x2-x5` |4|(rs2=x2) C.NTL.P1 (rs2=x3) C.NTL.PALL (rs2=x4) C.NTL.S1 (rs2=x5) C.NTL.ALL", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > HINT Instructions", + "line_range": [ + 622, + 622 + ] + }, + { + "text": "|C.SLLI |rd=`x0` or imm=0 |63 (RV32), 95 (RV64) .3+.^|Designated for custom use", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > HINT Instructions", + "line_range": [ + 624, + 624 + ] + }, + { + "text": "shows a map of the major opcodes for RVC.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > RVC Instruction Set Listings", + "line_range": [ + 633, + 642 + ] + }, + { + "text": "Each row of the table corresponds to one quadrant of the encoding space.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > RVC Instruction Set Listings", + "line_range": [ + 633, + 642 + ] + }, + { + "text": "The last quadrant, which has the two least-significant bits set, corresponds to instructions wider than 16 bits, including those in the base ISAs.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > RVC Instruction Set Listings", + "line_range": [ + 633, + 642 + ] + }, + { + "text": "Several instructions are only valid for certain operands; when invalid, they are marked either RES to indicate that the opcode is reserved for future standard extensions;", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > RVC Instruction Set Listings", + "line_range": [ + 633, + 642 + ] + }, + { + "text": "Custom to indicate that the opcode is designated for custom extensions; or HINT to indicate that the opcode is reserved for microarchitectural hints (see ).", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > RVC Instruction Set Listings", + "line_range": [ + 633, + 642 + ] + }, + { + "text": ".RVC opcode map instructions. | 2+>|inst[15:13] + inst[1:0] ^.^s|000 ^.^s|001 ^.^s|010 ^.^s|011 ^.^s|100 ^.^s|101 ^.^s|110 ^.^s|111 |", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > RVC Instruction Set Listings", + "line_range": [ + 646, + 651 + ] + }, + { + "text": "2+>.^|00 .^|ADDI4SPN ^.^|FLD + FLD ^.^| LW ^.^| FLW + LD ^.^| Reserved ^.^| FSD + FSD ^.^| SW ^.^| FSW + SD ^.^| RV32 + RV64", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > RVC Instruction Set Listings", + "line_range": [ + 653, + 659 + ] + }, + { + "text": "2+>.^|01 ^.^|ADDI ^.^|JAL + ADDIW ^.^|LI ^.^|LUI/ADDI16SP ^.^|MISC-ALU ^.^|J ^.^|BEQZ ^.^|BNEZ ^.^|RV32 + RV64", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > RVC Instruction Set Listings", + "line_range": [ + 661, + 663 + ] + }, + { + "text": "2+>.^|10 ^.^|SLLI ^.^|FLDSP + FLDSP ^.^|LWSP ^.^|FLWSP + LDSP ^.^|J[AL]R/MV/ADD ^.^|FSDSP + FSDSP ^.^|SWSP ^.^|FSWSP + SDSP ^.^|RV32 + RV64", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > RVC Instruction Set Listings", + "line_range": [ + 665, + 670 + ] + }, + { + "text": ", , and list the RVC instructions.", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > RVC Instruction Set Listings", + "line_range": [ + 675, + 675 + ] + }, + { + "text": ".Instruction listing for RVC, Quadrant 0 include::images/bytefield/rvc-instr-quad0.edn[]", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > RVC Instruction Set Listings", + "line_range": [ + 677, + 679 + ] + }, + { + "text": ".Instruction listing for RVC, Quadrant 1 include::images/bytefield/rvc-instr-quad1.edn[]", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > RVC Instruction Set Listings", + "line_range": [ + 681, + 683 + ] + }, + { + "text": ".Instruction listing for RVC, Quadrant 2 include::images/bytefield/rvc-instr-quad2.edn[]", + "section": "Preamble > \"C\" Extension for Compressed Instructions, Version 2.0 > RVC Instruction Set Listings", + "line_range": [ + 685, + 687 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__images__graphviz__litmus_sample.json b/tools/llm-extraction/data/output/raw_chunks/src__images__graphviz__litmus_sample.json new file mode 100644 index 0000000000..126dd8e715 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__images__graphviz__litmus_sample.json @@ -0,0 +1,38 @@ +{ + "source_file": "src/images/graphviz/litmus_sample.adoc", + "total": 4, + "sentences": [ + { + "text": "[\"graphviz\", ,\"png\"] .... digraph G {", + "section": "Preamble", + "line_range": [ + 3, + 5 + ] + }, + { + "text": "splines=spline; pad=\"0.000000\";", + "section": "Preamble", + "line_range": [ + 7, + 8 + ] + }, + { + "text": "eiid0 [label=\"a: Wx=1\", shape=\"none\", fontsize=8, pos=\"1.000000,2.109375!\", fixedsize=\"false\", height=\"0.111111\", width=\"0.555556\"]; eiid1 [label=\"b: Wx=2\", shape=\"none\", fontsize=8, pos=\"1.000000,1.546875!\", fixedsize=\"false\", height=\"0.111111\", width=\"0.555556\"]; eiid2 [label=\"c: Rx=1\", shape=\"none\", fontsize=8, pos=\"1.000000,0.984375!\", fixedsize=\"false\", height=\"0.111111\", width=\"0.555556\"]; eiid3 [label=\"d: Wx=3\", shape=\"none\", fontsize=8, pos=\"1.000000,0.421875!\", fixedsize=\"false\", height=\"0.111111\", width=\"0.555556\"]; eiid4 [label=\"e: Wx=4\", shape=\"none\", fontsize=8, pos=\"1.850000,1.687500!\", fixedsize=\"false\", height=\"0.111111\", width=\"0.555556\"]; eiiid6 [label=\"\", shape=none, width=0.05, height=0.1, pos=\"1.0,1.85!\";] eiid5 [label=\"f: Wx=5\", shape=\"none\", fontsize=8, pos=\"1.850000,1.125000!\", fixedsize=\"false\", height=\"0.111111\", width=\"0.555556\"];", + "section": "Preamble", + "line_range": [ + 10, + 17 + ] + }, + { + "text": "eiid0 -> eiid1 [label=<co>, color=\"blue\", fontsize=11, penwidth=\"3.000000\", arrowsize=\"0.666700\"]; eiid0 -> eiid2 [label=<rf>, color=\"red\", fontsize=11, penwidth=\"3.000000\", arrowsize=\"0.666700\"]; eiid1 -> eiid0 [label=<co>, color=\"blue\", fontsize=11, penwidth=\"3.000000\", arrowsize=\"0.666700\"]; eiid1 -> eiid3 [label=<co>, color=\"blue\", fontsize=11, penwidth=\"3.000000\", arrowsize=\"0.666700\"]; eiid2 -> eiid0 [label=<fr>, color=\"ffa040\", fontsize=11, penwidth=\"3.000000\", arrowsize=\"0.666700\"]; eiid2 -> eiid1 [label=<fr>, color=\"ffa040\", fontsize=11, penwidth=\"3.000000\", arrowsize=\"0.666700\"]; eiid2 -> eiid3 [label=<fr>, color=\"ffa040\", fontsize=11, penwidth=\"3.000000\", arrowsize=\"0.666700\"]; eiiid6 [label=\"\", shape=none, width=0.05, height=0.1, pos=\"1.0,1.85!\";] eiid4 -> eiid5 [label=<co>, color=\"blue\", fontsize=11, penwidth=\"3.000000\", arrowsize=\"0.666700\"]; } ....", + "section": "Preamble", + "line_range": [ + 26, + 37 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__intro.json b/tools/llm-extraction/data/output/raw_chunks/src__intro.json new file mode 100644 index 0000000000..d95d1358ef --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__intro.json @@ -0,0 +1,1150 @@ +{ + "source_file": "src/intro.adoc", + "total": 143, + "sentences": [ + { + "text": "RISC-V (pronounced \"risk-five\") is a new instruction-set architecture (ISA) that was originally designed to support computer architecture research and education, but which we now hope will also become a standard free and open architecture for industry implementations.", + "section": "Preamble > Introduction", + "line_range": [ + 2, + 6 + ] + }, + { + "text": "Our goals in defining RISC-V include:", + "section": "Preamble > Introduction", + "line_range": [ + 2, + 6 + ] + }, + { + "text": "A completely open ISA that is freely available to academia and industry. * A real ISA suitable for direct native hardware implementation, not just simulation or binary translation. * An ISA that avoids \"over-architecting\" for a particular microarchitecture style (e.g., microcoded, in-order, decoupled, out-of-order) or implementation technology (e.g., full-custom, ASIC, FPGA), but which allows efficient implementation in any of these. * An ISA separated into a small base integer ISA, usable by itself as a base for customized accelerators or for educational purposes, and optional standard extensions, to support general-purpose software development. * Support for the IEEE 754-2008 cite:[ieee754-2008] floating-point arithmetic standard. * An ISA supporting extensive ISA extensions and specialized variants. * Both 32-bit and 64-bit address space variants for applications, operating system kernels, and hardware implementations. * An ISA with support for highly parallel multicore or manycore implementations, including heterogeneous multiprocessors. * Optional variable-length instructions to both expand available instruction encoding space and to support an optional dense instruction encoding for improved performance, static code size, and energy efficiency. * A fully virtualizable ISA to ease hypervisor development. * An ISA that simplifies experiments with new privileged architecture designs.", + "section": "Preamble > Introduction", + "line_range": [ + 8, + 33 + ] + }, + { + "text": "The RISC-V ISA is defined avoiding implementation details as much as possible (although commentary is included on implementation-driven decisions) and should be read as the software-visible interface to a wide variety of implementations rather than as the design of a particular hardware artifact.", + "section": "Preamble > Introduction", + "line_range": [ + 35, + 48 + ] + }, + { + "text": "The RISC-V manual is structured in two volumes.", + "section": "Preamble > Introduction", + "line_range": [ + 35, + 48 + ] + }, + { + "text": "This volume covers the design of the base unprivileged instructions, including optional unprivileged ISA extensions.", + "section": "Preamble > Introduction", + "line_range": [ + 35, + 48 + ] + }, + { + "text": "Unprivileged instructions are those that are generally usable in all privilege modes in all privileged architectures, though behavior might vary depending on privilege mode and privilege architecture.", + "section": "Preamble > Introduction", + "line_range": [ + 35, + 48 + ] + }, + { + "text": "The second volume provides the design of the first (\"classic\") privileged architecture.", + "section": "Preamble > Introduction", + "line_range": [ + 35, + 48 + ] + }, + { + "text": "The manuals use IEC 80000-13:2008 conventions, with a byte of 8 bits.", + "section": "Preamble > Introduction", + "line_range": [ + 35, + 48 + ] + }, + { + "text": "A RISC-V hardware platform can contain one or more RISC-V-compatible processing cores together with other non-RISC-V-compatible cores, fixed-function accelerators, various physical memory structures, I/O devices, and an interconnect structure to allow the components to communicate.", + "section": "Preamble > Introduction > RISC-V Hardware Platform Terminology", + "line_range": [ + 53, + 58 + ] + }, + { + "text": "A component is termed a core if it contains an independent instruction fetch unit. A RISC-V-compatible core might support multiple RISC-V-compatible hardware threads, or harts, through multithreading.", + "section": "Preamble > Introduction > RISC-V Hardware Platform Terminology", + "line_range": [ + 60, + 63 + ] + }, + { + "text": "A RISC-V core might have additional specialized instruction-set extensions or an added coprocessor.", + "section": "Preamble > Introduction > RISC-V Hardware Platform Terminology", + "line_range": [ + 65, + 70 + ] + }, + { + "text": "We use the term coprocessor to refer to a unit that is attached to a RISC-V core and is mostly sequenced by a RISC-V instruction stream, but which contains additional architectural state and instruction-set extensions, and possibly some limited autonomy relative to the primary RISC-V instruction stream.", + "section": "Preamble > Introduction > RISC-V Hardware Platform Terminology", + "line_range": [ + 65, + 70 + ] + }, + { + "text": "We use the term accelerator to refer to either a non-programmable fixed-function unit or a core that can operate autonomously but is specialized for certain tasks.", + "section": "Preamble > Introduction > RISC-V Hardware Platform Terminology", + "line_range": [ + 72, + 79 + ] + }, + { + "text": "In RISC-V systems, we expect many programmable accelerators will be RISC-V-based cores with specialized instruction-set extensions and/or customized coprocessors.", + "section": "Preamble > Introduction > RISC-V Hardware Platform Terminology", + "line_range": [ + 72, + 79 + ] + }, + { + "text": "An important class of RISC-V accelerators are I/O accelerators, which offload I/O processing tasks from the main application cores.", + "section": "Preamble > Introduction > RISC-V Hardware Platform Terminology", + "line_range": [ + 72, + 79 + ] + }, + { + "text": "The system-level organization of a RISC-V hardware platform can range from a single-core microcontroller to a many-thousand-node cluster of shared-memory manycore server nodes.", + "section": "Preamble > Introduction > RISC-V Hardware Platform Terminology", + "line_range": [ + 81, + 87 + ] + }, + { + "text": "Even small systems-on-a-chip might be structured as a hierarchy of multicomputers and/or multiprocessors to modularize development effort or to provide secure isolation between subsystems.", + "section": "Preamble > Introduction > RISC-V Hardware Platform Terminology", + "line_range": [ + 81, + 87 + ] + }, + { + "text": "The behavior of a RISC-V program depends on the execution environment in which it runs. A RISC-V execution environment interface (EEI) defines the initial state of the program, the number and type of harts in the environment including the privilege modes supported by the harts, the accessibility and attributes of memory and I/O regions, the behavior of all legal instructions executed on each hart (i.e., the ISA is one component of the EEI), and the handling of any interrupts or exceptions raised during execution including environment calls.", + "section": "Preamble > Introduction > RISC-V Software Execution Environments and Harts", + "line_range": [ + 92, + 105 + ] + }, + { + "text": "Examples of EEIs include the Linux application binary interface (ABI), or the RISC-V supervisor binary interface (SBI).", + "section": "Preamble > Introduction > RISC-V Software Execution Environments and Harts", + "line_range": [ + 92, + 105 + ] + }, + { + "text": "The implementation of a RISC-V execution environment can be pure hardware, pure software, or a combination of hardware and software.", + "section": "Preamble > Introduction > RISC-V Software Execution Environments and Harts", + "line_range": [ + 92, + 105 + ] + }, + { + "text": "For example, opcode traps and software emulation can be used to implement functionality not provided in hardware.", + "section": "Preamble > Introduction > RISC-V Software Execution Environments and Harts", + "line_range": [ + 92, + 105 + ] + }, + { + "text": "Examples of execution environment implementations include:", + "section": "Preamble > Introduction > RISC-V Software Execution Environments and Harts", + "line_range": [ + 92, + 105 + ] + }, + { + "text": "\"Bare metal\" hardware platforms where harts are directly implemented by physical processor threads and instructions have full access to the physical address space.", + "section": "Preamble > Introduction > RISC-V Software Execution Environments and Harts", + "line_range": [ + 107, + 119 + ] + }, + { + "text": "The hardware platform defines an execution environment that begins at power-on reset. * RISC-V operating systems that provide multiple user-level execution environments by multiplexing user-level harts onto available physical processor threads and by controlling access to memory via virtual memory. * RISC-V hypervisors that provide multiple supervisor-level execution environments for guest operating systems. * RISC-V emulators, such as Spike, QEMU or rv8, which emulate RISC-V harts on an underlying x86 system, and which can provide either a user-level or a supervisor-level execution environment.", + "section": "Preamble > Introduction > RISC-V Software Execution Environments and Harts", + "line_range": [ + 107, + 119 + ] + }, + { + "text": "From the perspective of software running in a given execution environment, a hart is a resource that autonomously fetches and executes RISC-V instructions within that execution environment.", + "section": "Preamble > Introduction > RISC-V Software Execution Environments and Harts", + "line_range": [ + 121, + 128 + ] + }, + { + "text": "In this respect, a hart behaves like a hardware thread resource even if time-multiplexed onto real hardware by the execution environment.", + "section": "Preamble > Introduction > RISC-V Software Execution Environments and Harts", + "line_range": [ + 121, + 128 + ] + }, + { + "text": "Some EEIs support the creation and destruction of additional harts, for example, via environment calls to fork new harts.", + "section": "Preamble > Introduction > RISC-V Software Execution Environments and Harts", + "line_range": [ + 121, + 128 + ] + }, + { + "text": "The execution environment is responsible for ensuring the eventual forward progress of each of its harts.", + "section": "Preamble > Introduction > RISC-V Software Execution Environments and Harts", + "line_range": [ + 130, + 136 + ] + }, + { + "text": "For a given hart, that responsibility is suspended while the hart is exercising a mechanism that explicitly waits for an event, such as the wait-for-interrupt instruction defined in ; and that responsibility ends if the hart is terminated.", + "section": "Preamble > Introduction > RISC-V Software Execution Environments and Harts", + "line_range": [ + 130, + 136 + ] + }, + { + "text": "The following events constitute forward progress:", + "section": "Preamble > Introduction > RISC-V Software Execution Environments and Harts", + "line_range": [ + 130, + 136 + ] + }, + { + "text": "The retirement of an instruction. * A trap, * Any other event defined by an extension to constitute forward progress.", + "section": "Preamble > Introduction > RISC-V Software Execution Environments and Harts", + "line_range": [ + 138, + 141 + ] + }, + { + "text": "A RISC-V ISA is defined as a base integer ISA, which must be present in any implementation, plus optional extensions to the base ISA.", + "section": "Preamble > Introduction > RISC-V ISA Overview", + "line_range": [ + 146, + 155 + ] + }, + { + "text": "The base integer ISAs are very similar to that of the early RISC processors except with no branch delay slots and with support for optional variable-length instruction encodings. A base is carefully restricted to a minimal set of instructions sufficient to provide a reasonable target for compilers, assemblers, linkers, and operating systems (with additional privileged operations), and so provides a convenient ISA and software toolchain \"skeleton\" around which more customized processor ISAs can be built.", + "section": "Preamble > Introduction > RISC-V ISA Overview", + "line_range": [ + 146, + 155 + ] + }, + { + "text": "Although it is convenient to speak of the RISC-V ISA, RISC-V is actually a family of related ISAs, of which there are currently four base ISAs.", + "section": "Preamble > Introduction > RISC-V ISA Overview", + "line_range": [ + 157, + 170 + ] + }, + { + "text": "Each base integer instruction set is characterized by the width of the integer registers and the corresponding size of the address space and by the number of integer registers.", + "section": "Preamble > Introduction > RISC-V ISA Overview", + "line_range": [ + 157, + 170 + ] + }, + { + "text": "There are two primary base integer variants, RV32I and RV64I, described in and , which provide 32-bit or 64-bit address spaces respectively.", + "section": "Preamble > Introduction > RISC-V ISA Overview", + "line_range": [ + 157, + 170 + ] + }, + { + "text": "We use the term XLEN to refer to the width of an integer register in bits (either 32 or 64). describes the RV32E and RV64E subset variants of the RV32I or RV64I base instruction sets respectively, which have been added to support small microcontrollers, and which have half the number of integer registers.", + "section": "Preamble > Introduction > RISC-V ISA Overview", + "line_range": [ + 157, + 170 + ] + }, + { + "text": "The base integer instruction sets use a two's-complement representation for signed integer values.", + "section": "Preamble > Introduction > RISC-V ISA Overview", + "line_range": [ + 157, + 170 + ] + }, + { + "text": "RISC-V has been designed to support extensive customization and specialization.", + "section": "Preamble > Introduction > RISC-V ISA Overview", + "line_range": [ + 172, + 192 + ] + }, + { + "text": "Each base integer ISA can be extended with one or more optional instruction-set extensions.", + "section": "Preamble > Introduction > RISC-V ISA Overview", + "line_range": [ + 172, + 192 + ] + }, + { + "text": "An extension may be categorized as either standard, custom, or non-conforming.", + "section": "Preamble > Introduction > RISC-V ISA Overview", + "line_range": [ + 172, + 192 + ] + }, + { + "text": "For this purpose, we divide each RISC-V instruction-set encoding space (and related encoding spaces such as the CSRs) into three disjoint categories: standard, reserved, and custom.", + "section": "Preamble > Introduction > RISC-V ISA Overview", + "line_range": [ + 172, + 192 + ] + }, + { + "text": "Standard extensions and encodings are defined by RISC-V International; any extensions not defined by RISC-V International are non-standard.", + "section": "Preamble > Introduction > RISC-V ISA Overview", + "line_range": [ + 172, + 192 + ] + }, + { + "text": "Each base ISA and its standard extensions use only standard encodings.", + "section": "Preamble > Introduction > RISC-V ISA Overview", + "line_range": [ + 172, + 192 + ] + }, + { + "text": "Reserved encodings are currently not defined but are saved for future standard extensions; once thus used, they become standard encodings.", + "section": "Preamble > Introduction > RISC-V ISA Overview", + "line_range": [ + 172, + 192 + ] + }, + { + "text": "Custom encodings shall never be used for standard extensions and are made available for vendor-specific non-standard extensions.", + "section": "Preamble > Introduction > RISC-V ISA Overview", + "line_range": [ + 172, + 192 + ] + }, + { + "text": "Non-standard extensions are either custom extensions, that use only custom encodings, or non-conforming extensions, that use any standard or reserved encoding.", + "section": "Preamble > Introduction > RISC-V ISA Overview", + "line_range": [ + 172, + 192 + ] + }, + { + "text": "Instruction-set extensions are generally shared but may provide slightly different functionality depending on the base ISA.", + "section": "Preamble > Introduction > RISC-V ISA Overview", + "line_range": [ + 172, + 192 + ] + }, + { + "text": "We have also developed a naming convention for RISC-V base instructions and instruction-set extensions, described in detail in .", + "section": "Preamble > Introduction > RISC-V ISA Overview", + "line_range": [ + 172, + 192 + ] + }, + { + "text": "To support more general software development, a set of standard extensions are defined to provide integer multiply/divide, atomic operations, and single and double-precision floating-point arithmetic.", + "section": "Preamble > Introduction > RISC-V ISA Overview", + "line_range": [ + 194, + 211 + ] + }, + { + "text": "The base integer ISA is named \"I\" (prefixed by RV32 or RV64 depending on integer register width), and contains integer computational instructions, integer loads, integer stores, and control-flow instructions.", + "section": "Preamble > Introduction > RISC-V ISA Overview", + "line_range": [ + 194, + 211 + ] + }, + { + "text": "The standard integer multiplication and division extension is named \"M\", and adds instructions to multiply and divide values held in the integer registers.", + "section": "Preamble > Introduction > RISC-V ISA Overview", + "line_range": [ + 194, + 211 + ] + }, + { + "text": "The standard atomic instruction extension, denoted by \"A\", adds instructions that atomically read, modify, and write memory for inter-processor synchronization.", + "section": "Preamble > Introduction > RISC-V ISA Overview", + "line_range": [ + 194, + 211 + ] + }, + { + "text": "The standard single-precision floating-point extension, denoted by \"F\", adds floating-point registers, single-precision computational instructions, and single-precision loads and stores.", + "section": "Preamble > Introduction > RISC-V ISA Overview", + "line_range": [ + 194, + 211 + ] + }, + { + "text": "The standard double-precision floating-point extension, denoted by \"D\", expands the floating-point registers, and adds double-precision computational instructions, loads, and stores.", + "section": "Preamble > Introduction > RISC-V ISA Overview", + "line_range": [ + 194, + 211 + ] + }, + { + "text": "The standard \"C\" compressed instruction extension provides narrower 16-bit forms of common instructions.", + "section": "Preamble > Introduction > RISC-V ISA Overview", + "line_range": [ + 194, + 211 + ] + }, + { + "text": "Beyond the base integer ISA and these standard extensions, we believe it is rare that a new instruction will provide a significant benefit for all applications, although it may be very beneficial for a certain domain.", + "section": "Preamble > Introduction > RISC-V ISA Overview", + "line_range": [ + 213, + 224 + ] + }, + { + "text": "As energy efficiency concerns are forcing greater specialization, we believe it is important to simplify the required portion of an ISA specification.", + "section": "Preamble > Introduction > RISC-V ISA Overview", + "line_range": [ + 213, + 224 + ] + }, + { + "text": "Whereas other architectures usually treat their ISA as a single entity, which changes to a new version as instructions are added over time, RISC-V will endeavor to keep the base and each standard extension constant over time, and instead layer new instructions as further optional extensions.", + "section": "Preamble > Introduction > RISC-V ISA Overview", + "line_range": [ + 213, + 224 + ] + }, + { + "text": "For example, the base integer ISAs will continue as fully supported standalone ISAs, regardless of any subsequent extensions.", + "section": "Preamble > Introduction > RISC-V ISA Overview", + "line_range": [ + 213, + 224 + ] + }, + { + "text": "A RISC-V hart has a single byte-addressable address space of 2^XLEN^ bytes for all memory accesses. A word of memory is defined as 32{nbsp}bits (4{nbsp}bytes).", + "section": "Preamble > Introduction > Memory", + "line_range": [ + 231, + 238 + ] + }, + { + "text": "Correspondingly, a halfword is 16{nbsp}bits (2{nbsp}bytes), a doubleword is 64{nbsp}bits (8{nbsp}bytes), and a quadword is 128{nbsp}bits (16{nbsp}bytes).", + "section": "Preamble > Introduction > Memory", + "line_range": [ + 231, + 238 + ] + }, + { + "text": "The memory address space is circular, so that the byte at address 2^XLEN^−1 is adjacent to the byte at address zero.", + "section": "Preamble > Introduction > Memory", + "line_range": [ + 231, + 238 + ] + }, + { + "text": "Accordingly, memory address computations done by the hardware ignore overflow and instead wrap around modulo 2^XLEN^.", + "section": "Preamble > Introduction > Memory", + "line_range": [ + 231, + 238 + ] + }, + { + "text": "The execution environment determines the mapping of hardware resources into a hart's address space.", + "section": "Preamble > Introduction > Memory", + "line_range": [ + 240, + 249 + ] + }, + { + "text": "Different address ranges of a hart's address space may (1) contain main memory, or (2) contain one or more I/O devices.", + "section": "Preamble > Introduction > Memory", + "line_range": [ + 240, + 249 + ] + }, + { + "text": "Reads and writes of I/O devices may have visible side effects, but accesses to main memory cannot.", + "section": "Preamble > Introduction > Memory", + "line_range": [ + 240, + 249 + ] + }, + { + "text": "Vacant address ranges are not a separate category but can be represented as either main memory or I/O regions that are not accessible.", + "section": "Preamble > Introduction > Memory", + "line_range": [ + 240, + 249 + ] + }, + { + "text": "Although it is possible for the execution environment to call everything in a hart's address space an I/O device, it is usually expected that some portion will be specified as main memory.", + "section": "Preamble > Introduction > Memory", + "line_range": [ + 240, + 249 + ] + }, + { + "text": "When a RISC-V platform has multiple harts, the address spaces of any two harts may be entirely the same, or entirely different, or may be partly different but sharing some subset of resources, mapped into the same or different address ranges.", + "section": "Preamble > Introduction > Memory", + "line_range": [ + 251, + 254 + ] + }, + { + "text": "Executing each RISC-V machine instruction entails one or more memory accesses, subdivided into implicit and explicit accesses.", + "section": "Preamble > Introduction > Memory", + "line_range": [ + 258, + 267 + ] + }, + { + "text": "For each instruction executed, an implicit memory read (instruction fetch) is done to obtain the encoded instruction to execute.", + "section": "Preamble > Introduction > Memory", + "line_range": [ + 258, + 267 + ] + }, + { + "text": "Many RISC-V instructions perform no further memory accesses beyond instruction fetch.", + "section": "Preamble > Introduction > Memory", + "line_range": [ + 258, + 267 + ] + }, + { + "text": "Specific load and store instructions perform an explicit read or write of memory at an address determined by the instruction.", + "section": "Preamble > Introduction > Memory", + "line_range": [ + 258, + 267 + ] + }, + { + "text": "The execution environment may dictate that instruction execution performs other implicit memory accesses (such as to implement address translation) beyond those documented for the unprivileged ISA.", + "section": "Preamble > Introduction > Memory", + "line_range": [ + 258, + 267 + ] + }, + { + "text": "The execution environment determines what portions of the address space are accessible for each kind of memory access.", + "section": "Preamble > Introduction > Memory", + "line_range": [ + 269, + 277 + ] + }, + { + "text": "For example, the set of locations that can be implicitly read for instruction fetch may or may not have any overlap with the set of locations that can be explicitly read by a load instruction; and the set of locations that can be explicitly written by a store instruction may be only a subset of locations that can be read.", + "section": "Preamble > Introduction > Memory", + "line_range": [ + 269, + 277 + ] + }, + { + "text": "Ordinarily, if an instruction attempts to access memory at an inaccessible address, an exception is raised for the instruction.", + "section": "Preamble > Introduction > Memory", + "line_range": [ + 269, + 277 + ] + }, + { + "text": "Except when specified otherwise, implicit reads that do not raise an exception and that have no side effects may occur arbitrarily early and speculatively, even before the machine could possibly prove that the read will be needed.", + "section": "Preamble > Introduction > Memory", + "line_range": [ + 279, + 290 + ] + }, + { + "text": "For instance, a valid implementation could attempt to read all of main memory at the earliest opportunity, cache as many fetchable (executable) bytes as possible for later instruction fetches, and avoid reading main memory for instruction fetches ever again.", + "section": "Preamble > Introduction > Memory", + "line_range": [ + 279, + 290 + ] + }, + { + "text": "To ensure that certain implicit reads are ordered only after writes to the same memory locations, software must execute specific fence or cache-control instructions defined for this purpose (such as the FENCE.I instruction defined in ).", + "section": "Preamble > Introduction > Memory", + "line_range": [ + 279, + 290 + ] + }, + { + "text": "The memory accesses (implicit or explicit) made by a hart may appear to occur in a different order as perceived by another hart or by any other agent that can access the same memory.", + "section": "Preamble > Introduction > Memory", + "line_range": [ + 292, + 308 + ] + }, + { + "text": "This perceived reordering of memory accesses is always constrained, however, by the applicable memory consistency model.", + "section": "Preamble > Introduction > Memory", + "line_range": [ + 292, + 308 + ] + }, + { + "text": "The default memory consistency model for RISC-V is the RISC-V Weak Memory Ordering (RVWMO), defined in and in appendices.", + "section": "Preamble > Introduction > Memory", + "line_range": [ + 292, + 308 + ] + }, + { + "text": "Optionally, an implementation may adopt the stronger model of Total Store Ordering, The execution environment may also add constraints that further limit the perceived reordering of memory accesses.", + "section": "Preamble > Introduction > Memory", + "line_range": [ + 292, + 308 + ] + }, + { + "text": "Since the RVWMO model is the weakest model allowed for any RISC-V implementation, software written for this model is compatible with the actual memory consistency rules of all RISC-V implementations.", + "section": "Preamble > Introduction > Memory", + "line_range": [ + 292, + 308 + ] + }, + { + "text": "As with implicit reads, software must execute fence or cache-control instructions to ensure specific ordering of memory accesses beyond the requirements of the assumed memory consistency model and execution environment.", + "section": "Preamble > Introduction > Memory", + "line_range": [ + 292, + 308 + ] + }, + { + "text": "The base RISC-V ISA has fixed-length 32-bit instructions that must be naturally aligned on 32-bit boundaries.", + "section": "Preamble > Introduction > Base Instruction-Length Encoding", + "line_range": [ + 313, + 322 + ] + }, + { + "text": "However, the standard RISC-V encoding scheme is designed to support ISA extensions with variable-length instructions, where each instruction can be any number of 16-bit instruction parcels in length and parcels are naturally aligned on 16-bit boundaries.", + "section": "Preamble > Introduction > Base Instruction-Length Encoding", + "line_range": [ + 313, + 322 + ] + }, + { + "text": "The reduces code size by providing compressed 16-bit instructions and relaxes the alignment constraints to allow all instructions (16 bit and 32 bit) to be aligned on any 16-bit boundary to improve code density.", + "section": "Preamble > Introduction > Base Instruction-Length Encoding", + "line_range": [ + 313, + 322 + ] + }, + { + "text": "We use the term IALIGN (measured in bits) to refer to the instruction-address alignment constraint the implementation enforces. IALIGN is 32 bits in the base ISA, but some ISA extensions, including the compressed ISA extension, relax IALIGN to 16 bits. IALIGN may not take on any value other than 16 or 32.", + "section": "Preamble > Introduction > Base Instruction-Length Encoding", + "line_range": [ + 324, + 329 + ] + }, + { + "text": "We use the term ILEN (measured in bits) to refer to the maximum instruction length supported by an implementation, and which is always a multiple of IALIGN.", + "section": "Preamble > Introduction > Base Instruction-Length Encoding", + "line_range": [ + 331, + 335 + ] + }, + { + "text": "For implementations supporting only a base instruction set, ILEN is 32 bits.", + "section": "Preamble > Introduction > Base Instruction-Length Encoding", + "line_range": [ + 331, + 335 + ] + }, + { + "text": "Implementations supporting longer instructions have larger values of ILEN.", + "section": "Preamble > Introduction > Base Instruction-Length Encoding", + "line_range": [ + 331, + 335 + ] + }, + { + "text": "All the 32-bit instructions in the base ISA have their lowest two bits set to `11`.", + "section": "Preamble > Introduction > Base Instruction-Length Encoding", + "line_range": [ + 337, + 340 + ] + }, + { + "text": "The optional compressed 16-bit instruction-set extensions have their lowest two bits equal to `00`, `01`, or `10`.", + "section": "Preamble > Introduction > Base Instruction-Length Encoding", + "line_range": [ + 337, + 340 + ] + }, + { + "text": "Encodings with bits [15:0] all zeros are defined as illegal instructions.", + "section": "Preamble > Introduction > Base Instruction-Length Encoding", + "line_range": [ + 342, + 346 + ] + }, + { + "text": "These instructions are considered to be of minimal length: 16 bits if any 16-bit instruction-set extension is present, otherwise 32 bits.", + "section": "Preamble > Introduction > Base Instruction-Length Encoding", + "line_range": [ + 342, + 346 + ] + }, + { + "text": "The encoding with bits [ILEN-1:0] all ones is also illegal; this instruction is considered to be ILEN bits long.", + "section": "Preamble > Introduction > Base Instruction-Length Encoding", + "line_range": [ + 342, + 346 + ] + }, + { + "text": "RISC-V base ISAs have either little-endian or big-endian memory systems, with the privileged architecture further defining bi-endian operation.", + "section": "Preamble > Introduction > Base Instruction-Length Encoding", + "line_range": [ + 348, + 357 + ] + }, + { + "text": "Instructions are stored in memory as a sequence of 16-bit little-endian parcels, regardless of memory system endianness.", + "section": "Preamble > Introduction > Base Instruction-Length Encoding", + "line_range": [ + 348, + 357 + ] + }, + { + "text": "Parcels forming one instruction are stored at increasing halfword addresses, with the lowest-addressed parcel holding the lowest-numbered bits in the instruction specification.", + "section": "Preamble > Introduction > Base Instruction-Length Encoding", + "line_range": [ + 348, + 357 + ] + }, + { + "text": "We use the term exception to refer to an unusual condition occurring at run time associated with an instruction in the current RISC-V hart.", + "section": "Preamble > Introduction > Exceptions, Traps, and Interrupts", + "line_range": [ + 362, + 370 + ] + }, + { + "text": "We use the term interrupt to refer to an external asynchronous event that may cause a RISC-V hart to experience an unexpected transfer of control.", + "section": "Preamble > Introduction > Exceptions, Traps, and Interrupts", + "line_range": [ + 362, + 370 + ] + }, + { + "text": "We use the term trap to refer to the transfer of control to a trap handler caused by either an exception or an interrupt.", + "section": "Preamble > Introduction > Exceptions, Traps, and Interrupts", + "line_range": [ + 362, + 370 + ] + }, + { + "text": "The instruction descriptions in following chapters describe conditions that can raise an exception during execution.", + "section": "Preamble > Introduction > Exceptions, Traps, and Interrupts", + "line_range": [ + 372, + 378 + ] + }, + { + "text": "The general behavior of most RISC-V EEIs is that a trap to some handler occurs when an exception is signaled on an instruction (except for floating-point exceptions, which, in the standard floating-point extensions, do not cause traps).", + "section": "Preamble > Introduction > Exceptions, Traps, and Interrupts", + "line_range": [ + 372, + 378 + ] + }, + { + "text": "The manner in which interrupts are generated, routed to, and enabled by a hart depends on the EEI.", + "section": "Preamble > Introduction > Exceptions, Traps, and Interrupts", + "line_range": [ + 372, + 378 + ] + }, + { + "text": "How traps are handled and made visible to software running on the hart depends on the enclosing execution environment.", + "section": "Preamble > Introduction > Exceptions, Traps, and Interrupts", + "line_range": [ + 380, + 383 + ] + }, + { + "text": "From the perspective of software running inside an execution environment, traps encountered by a hart at runtime can have four different effects:", + "section": "Preamble > Introduction > Exceptions, Traps, and Interrupts", + "line_range": [ + 380, + 383 + ] + }, + { + "text": "Contained Trap::: The trap is visible to, and handled by, software running inside the execution environment.", + "section": "Preamble > Introduction > Exceptions, Traps, and Interrupts", + "line_range": [ + 385, + 414 + ] + }, + { + "text": "For example, in an EEI providing both supervisor and user mode on harts, an ECALL by a user-mode hart will generally result in a transfer of control to a supervisor-mode handler running on the same hart.", + "section": "Preamble > Introduction > Exceptions, Traps, and Interrupts", + "line_range": [ + 385, + 414 + ] + }, + { + "text": "Similarly, in the same environment, when a hart is interrupted, an interrupt handler will be run in supervisor mode on the hart.", + "section": "Preamble > Introduction > Exceptions, Traps, and Interrupts", + "line_range": [ + 385, + 414 + ] + }, + { + "text": "Requested Trap::: The trap is a synchronous exception that is an explicit call to the execution environment requesting an action on behalf of software inside the execution environment.", + "section": "Preamble > Introduction > Exceptions, Traps, and Interrupts", + "line_range": [ + 385, + 414 + ] + }, + { + "text": "An example is a system call.", + "section": "Preamble > Introduction > Exceptions, Traps, and Interrupts", + "line_range": [ + 385, + 414 + ] + }, + { + "text": "In this case, execution may or may not resume on the hart after the requested action is taken by the execution environment.", + "section": "Preamble > Introduction > Exceptions, Traps, and Interrupts", + "line_range": [ + 385, + 414 + ] + }, + { + "text": "For example, a system call could remove the hart or cause an orderly termination of the entire execution environment.", + "section": "Preamble > Introduction > Exceptions, Traps, and Interrupts", + "line_range": [ + 385, + 414 + ] + }, + { + "text": "Invisible Trap::: The trap is handled transparently by the execution environment and execution resumes normally after the trap is handled.", + "section": "Preamble > Introduction > Exceptions, Traps, and Interrupts", + "line_range": [ + 385, + 414 + ] + }, + { + "text": "Examples include emulating missing instructions, handling non-resident page faults in a demand-paged virtual-memory system, or handling device interrupts for a different job in a multiprogrammed machine.", + "section": "Preamble > Introduction > Exceptions, Traps, and Interrupts", + "line_range": [ + 385, + 414 + ] + }, + { + "text": "In these cases, the software running inside the execution environment is not aware of the trap (we ignore timing effects in these definitions).", + "section": "Preamble > Introduction > Exceptions, Traps, and Interrupts", + "line_range": [ + 385, + 414 + ] + }, + { + "text": "Fatal Trap::: The trap represents a fatal failure and causes the execution environment to terminate execution.", + "section": "Preamble > Introduction > Exceptions, Traps, and Interrupts", + "line_range": [ + 385, + 414 + ] + }, + { + "text": "Examples include failing a virtual-memory page-protection check or allowing a watchdog timer to expire.", + "section": "Preamble > Introduction > Exceptions, Traps, and Interrupts", + "line_range": [ + 385, + 414 + ] + }, + { + "text": "Each EEI should define how execution is terminated and reported to an external environment.", + "section": "Preamble > Introduction > Exceptions, Traps, and Interrupts", + "line_range": [ + 385, + 414 + ] + }, + { + "text": "shows the characteristics of each kind of trap.", + "section": "Preamble > Introduction > Exceptions, Traps, and Interrupts", + "line_range": [ + 416, + 416 + ] + }, + { + "text": ".Characteristics of traps | | |Contained |Requested |Invisible |Fatal |Execution terminates |No |No^1^|No |Yes |Software is oblivious |No |No |Yes |Yes^2^|Handled by environment |No |Yes |Yes |Yes |", + "section": "Preamble > Introduction > Exceptions, Traps, and Interrupts", + "line_range": [ + 418, + 425 + ] + }, + { + "text": "^1^ Termination may be requested + ^2^ Imprecise fatal traps might be observable by software", + "section": "Preamble > Introduction > Exceptions, Traps, and Interrupts", + "line_range": [ + 427, + 428 + ] + }, + { + "text": "The EEI defines for each trap whether it is handled precisely, though the recommendation is to maintain preciseness where possible.", + "section": "Preamble > Introduction > Exceptions, Traps, and Interrupts", + "line_range": [ + 430, + 437 + ] + }, + { + "text": "Contained and requested traps can be observed to be imprecise by software inside the execution environment.", + "section": "Preamble > Introduction > Exceptions, Traps, and Interrupts", + "line_range": [ + 430, + 437 + ] + }, + { + "text": "Invisible traps, by definition, cannot be observed to be precise or imprecise by software running inside the execution environment.", + "section": "Preamble > Introduction > Exceptions, Traps, and Interrupts", + "line_range": [ + 430, + 437 + ] + }, + { + "text": "Fatal traps can be observed to be imprecise by software running inside the execution environment, if known-errorful instructions do not cause immediate termination.", + "section": "Preamble > Introduction > Exceptions, Traps, and Interrupts", + "line_range": [ + 430, + 437 + ] + }, + { + "text": "Because this volume describes unprivileged instructions, traps are rarely mentioned.", + "section": "Preamble > Introduction > Exceptions, Traps, and Interrupts", + "line_range": [ + 439, + 446 + ] + }, + { + "text": "Architectural means to handle contained traps are defined in the privileged architecture manual, along with other features to support richer EEIs.", + "section": "Preamble > Introduction > Exceptions, Traps, and Interrupts", + "line_range": [ + 439, + 446 + ] + }, + { + "text": "Unprivileged instructions that are defined solely to cause requested traps are documented here.", + "section": "Preamble > Introduction > Exceptions, Traps, and Interrupts", + "line_range": [ + 439, + 446 + ] + }, + { + "text": "Invisible traps are, by their nature, out of scope for the unprivileged architecture.", + "section": "Preamble > Introduction > Exceptions, Traps, and Interrupts", + "line_range": [ + 439, + 446 + ] + }, + { + "text": "Instruction encodings that are not defined here and not defined by some other means may cause a fatal trap.", + "section": "Preamble > Introduction > Exceptions, Traps, and Interrupts", + "line_range": [ + 439, + 446 + ] + }, + { + "text": "The architecture fully describes what implementations must do and any constraints on what they may do.", + "section": "Preamble > Introduction > UNSPECIFIED Behaviors and Values", + "line_range": [ + 450, + 455 + ] + }, + { + "text": "In cases where the architecture intentionally does not constrain implementations, the term UNSPECIFIED is explicitly used.", + "section": "Preamble > Introduction > UNSPECIFIED Behaviors and Values", + "line_range": [ + 450, + 455 + ] + }, + { + "text": "The term UNSPECIFIED refers to a behavior or value that is intentionally unconstrained.", + "section": "Preamble > Introduction > UNSPECIFIED Behaviors and Values", + "line_range": [ + 457, + 461 + ] + }, + { + "text": "The definition of these behaviors or values is open to extensions, platform standards, or implementations.", + "section": "Preamble > Introduction > UNSPECIFIED Behaviors and Values", + "line_range": [ + 457, + 461 + ] + }, + { + "text": "Extensions, platform standards, or implementation documentation may provide normative content to further constrain cases that the base architecture defines as UNSPECIFIED.", + "section": "Preamble > Introduction > UNSPECIFIED Behaviors and Values", + "line_range": [ + 457, + 461 + ] + }, + { + "text": "Like the base architecture, extensions should fully describe allowable behavior and values and use the term UNSPECIFIED for cases that are intentionally unconstrained.", + "section": "Preamble > Introduction > UNSPECIFIED Behaviors and Values", + "line_range": [ + 463, + 466 + ] + }, + { + "text": "These cases may be constrained or defined by other extensions, platform standards, or implementations.", + "section": "Preamble > Introduction > UNSPECIFIED Behaviors and Values", + "line_range": [ + 463, + 466 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__naming.json b/tools/llm-extraction/data/output/raw_chunks/src__naming.json new file mode 100644 index 0000000000..617e425281 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__naming.json @@ -0,0 +1,662 @@ +{ + "source_file": "src/naming.adoc", + "total": 82, + "sentences": [ + { + "text": "This chapter describes the RISC-V ISA extension naming scheme that is used to concisely describe the set of instructions present in a hardware implementation, or the set of instructions used by an application binary interface (ABI).", + "section": "Preamble > ISA Extension Naming Conventions", + "line_range": [ + 3, + 6 + ] + }, + { + "text": "The ISA naming strings are case insensitive.", + "section": "Preamble > ISA Extension Naming Conventions > Case Sensitivity", + "line_range": [ + 9, + 9 + ] + }, + { + "text": "RISC-V ISA strings begin with either RV32I, RV32E, RV64I, or RV64E, indicating the supported address space size in bits for the base integer ISA.", + "section": "Preamble > ISA Extension Naming Conventions > Base Integer ISA", + "line_range": [ + 13, + 15 + ] + }, + { + "text": "Standard ISA extensions are given a name consisting of a single letter.", + "section": "Preamble > ISA Extension Naming Conventions > Instruction-Set Extension Names", + "line_range": [ + 19, + 26 + ] + }, + { + "text": "For example, the first four standard extensions to the integer bases are: \"M\" for integer multiplication and division, \"A\" for atomic memory instructions, \"F\" for single-precision floating-point instructions, and \"D\" for double-precision floating-point instructions.", + "section": "Preamble > ISA Extension Naming Conventions > Instruction-Set Extension Names", + "line_range": [ + 19, + 26 + ] + }, + { + "text": "Any RISC-V instruction-set variant can be succinctly described by concatenating the base integer prefix with the names of the included extensions, e.g., \"RV64IMAFD\".", + "section": "Preamble > ISA Extension Naming Conventions > Instruction-Set Extension Names", + "line_range": [ + 19, + 26 + ] + }, + { + "text": "We have also defined an abbreviation \"G\" to represent the \"IMAFDZicsrZifencei\" base and extensions, as this is intended to represent our standard general-purpose ISA.", + "section": "Preamble > ISA Extension Naming Conventions > Instruction-Set Extension Names", + "line_range": [ + 28, + 30 + ] + }, + { + "text": "Standard extensions to the RISC-V ISA are given other reserved letters, e.g., \"Q\" for quad-precision floating-point, or \"C\" for the 16-bit compressed instruction format.", + "section": "Preamble > ISA Extension Naming Conventions > Instruction-Set Extension Names", + "line_range": [ + 32, + 34 + ] + }, + { + "text": "Some ISA extensions depend on the presence of other extensions, e.g., \"D\" depends on \"F\" and \"F\" depends on \"Zicsr\".", + "section": "Preamble > ISA Extension Naming Conventions > Instruction-Set Extension Names", + "line_range": [ + 36, + 39 + ] + }, + { + "text": "These dependencies may be implicit in the ISA name: for example, RV32IF is equivalent to RV32IFZicsr, and RV32ID is equivalent to RV32IFD and RV32IFDZicsr.", + "section": "Preamble > ISA Extension Naming Conventions > Instruction-Set Extension Names", + "line_range": [ + 36, + 39 + ] + }, + { + "text": "Underscores \"\" may be used to separate ISA extensions to improve readability and to provide disambiguation, e.g., \"RV32I2M2A2\".", + "section": "Preamble > ISA Extension Naming Conventions > Underscores", + "line_range": [ + 43, + 44 + ] + }, + { + "text": "Standard unprivileged extensions can also be named by using a single \"Z\" followed by an alphanumeric name.", + "section": "Preamble > ISA Extension Naming Conventions > Additional Standard Unprivileged Extension Names", + "line_range": [ + 48, + 52 + ] + }, + { + "text": "The name must end with an alphabetical character.", + "section": "Preamble > ISA Extension Naming Conventions > Additional Standard Unprivileged Extension Names", + "line_range": [ + 48, + 52 + ] + }, + { + "text": "The second letter from the end cannot be numeric if the last letter is \"p\".", + "section": "Preamble > ISA Extension Naming Conventions > Additional Standard Unprivileged Extension Names", + "line_range": [ + 48, + 52 + ] + }, + { + "text": "For example, \"Zifencei\" names the instruction-fetch fence extension described in .", + "section": "Preamble > ISA Extension Naming Conventions > Additional Standard Unprivileged Extension Names", + "line_range": [ + 48, + 52 + ] + }, + { + "text": "The first letter following the \"Z\" conventionally indicates the most closely related alphabetical extension category, IMAFDQLCBKJTPVH.", + "section": "Preamble > ISA Extension Naming Conventions > Additional Standard Unprivileged Extension Names", + "line_range": [ + 54, + 57 + ] + }, + { + "text": "For the \"Zfa\" extension for additional floating-point instructions, for example, the letter \"f\" indicates the extension is related to the \"F\" standard extension.", + "section": "Preamble > ISA Extension Naming Conventions > Additional Standard Unprivileged Extension Names", + "line_range": [ + 54, + 57 + ] + }, + { + "text": "NOTE: The Zhinx extension is an exception to this rule, as the extension is not related to the H extension but the Zfh extension.", + "section": "Preamble > ISA Extension Naming Conventions > Additional Standard Unprivileged Extension Names", + "line_range": [ + 59, + 60 + ] + }, + { + "text": "If multiple \"Z\" extensions are named, they should be ordered first by category, then alphabetically within a category—for example, \"ZicsrZifenceiZtso\".", + "section": "Preamble > ISA Extension Naming Conventions > Additional Standard Unprivileged Extension Names", + "line_range": [ + 62, + 63 + ] + }, + { + "text": "All multi-letter extensions, including those with the \"Z\" prefix, must be separated from other multi-letter extensions by an underscore, e.g., \"RV32IMACZicsrZifencei\".", + "section": "Preamble > ISA Extension Naming Conventions > Additional Standard Unprivileged Extension Names", + "line_range": [ + 65, + 67 + ] + }, + { + "text": "Standard extensions that extend the user-level architecture are prefixed with the letters \"Su\".", + "section": "Preamble > ISA Extension Naming Conventions > User-Level Instruction-Set Extension Names", + "line_range": [ + 71, + 72 + ] + }, + { + "text": "Standard user-level extensions should be listed after standard unprivileged extensions, and like other multi-letter extensions, must be separated from other multi-letter extensions by an underscore.", + "section": "Preamble > ISA Extension Naming Conventions > User-Level Instruction-Set Extension Names", + "line_range": [ + 74, + 77 + ] + }, + { + "text": "If multiple user-level extensions are listed, they should be ordered alphabetically.", + "section": "Preamble > ISA Extension Naming Conventions > User-Level Instruction-Set Extension Names", + "line_range": [ + 74, + 77 + ] + }, + { + "text": "Standard extensions that extend the supervisor-level virtual-memory architecture are prefixed with the letters \"Sv\", followed by an alphanumeric name.", + "section": "Preamble > ISA Extension Naming Conventions > Supervisor-Level Instruction-Set Extension Names", + "line_range": [ + 81, + 87 + ] + }, + { + "text": "Other standard extensions that extend the supervisor-level architecture are prefixed with the letters \"Ss\", followed by an alphanumeric name.", + "section": "Preamble > ISA Extension Naming Conventions > Supervisor-Level Instruction-Set Extension Names", + "line_range": [ + 81, + 87 + ] + }, + { + "text": "The name must end with an alphabetical character.", + "section": "Preamble > ISA Extension Naming Conventions > Supervisor-Level Instruction-Set Extension Names", + "line_range": [ + 81, + 87 + ] + }, + { + "text": "The second letter from the end cannot be numeric if the last letter is \"p\".", + "section": "Preamble > ISA Extension Naming Conventions > Supervisor-Level Instruction-Set Extension Names", + "line_range": [ + 81, + 87 + ] + }, + { + "text": "These extensions are further defined in Volume II.", + "section": "Preamble > ISA Extension Naming Conventions > Supervisor-Level Instruction-Set Extension Names", + "line_range": [ + 81, + 87 + ] + }, + { + "text": "The extensions \"sv32\", \"sv39\", \"sv48\", and \"sv59\" were defined before the rule against extension names ending in numbers was established.", + "section": "Preamble > ISA Extension Naming Conventions > Supervisor-Level Instruction-Set Extension Names", + "line_range": [ + 89, + 90 + ] + }, + { + "text": "Standard supervisor-level extensions should be listed after standard unprivileged and user-level extensions, and like other multi-letter extensions, must be separated from other multi-letter extensions by an underscore.", + "section": "Preamble > ISA Extension Naming Conventions > Supervisor-Level Instruction-Set Extension Names", + "line_range": [ + 92, + 96 + ] + }, + { + "text": "If multiple supervisor-level extensions are listed, they should be ordered alphabetically.", + "section": "Preamble > ISA Extension Naming Conventions > Supervisor-Level Instruction-Set Extension Names", + "line_range": [ + 92, + 96 + ] + }, + { + "text": "Standard extensions that extend the hypervisor-level architecture are prefixed with the letters \"Sh\".", + "section": "Preamble > ISA Extension Naming Conventions > Hypervisor-Level Instruction-Set Extension Names", + "line_range": [ + 100, + 101 + ] + }, + { + "text": "Standard hypervisor-level extensions should be listed after standard unprivileged, user-level and supervisor-level extensions, and like other multi-letter extensions, must be separated from other multi-letter extensions by an underscore.", + "section": "Preamble > ISA Extension Naming Conventions > Hypervisor-Level Instruction-Set Extension Names", + "line_range": [ + 103, + 107 + ] + }, + { + "text": "If multiple hypervisor-level extensions are listed, they should be ordered alphabetically.", + "section": "Preamble > ISA Extension Naming Conventions > Hypervisor-Level Instruction-Set Extension Names", + "line_range": [ + 103, + 107 + ] + }, + { + "text": "NOTE: Many augmentations to the hypervisor-level architecture are more naturally defined as supervisor-level extensions, following the scheme described in the previous section.", + "section": "Preamble > ISA Extension Naming Conventions > Hypervisor-Level Instruction-Set Extension Names", + "line_range": [ + 109, + 113 + ] + }, + { + "text": "The \"Sh\" prefix is used by the few hypervisor-level extensions that have no supervisor-visible effects.", + "section": "Preamble > ISA Extension Naming Conventions > Hypervisor-Level Instruction-Set Extension Names", + "line_range": [ + 109, + 113 + ] + }, + { + "text": "Standard machine-level instruction-set extensions are prefixed with the letters \"Sm\".", + "section": "Preamble > ISA Extension Naming Conventions > Machine-Level Instruction-Set Extension Names", + "line_range": [ + 117, + 118 + ] + }, + { + "text": "Standard machine-level extensions should be listed after standard lesser-privileged extensions, and like other multi-letter extensions, must be separated from other multi-letter extensions by an underscore.", + "section": "Preamble > ISA Extension Naming Conventions > Machine-Level Instruction-Set Extension Names", + "line_range": [ + 120, + 123 + ] + }, + { + "text": "If multiple machine-level extensions are listed, they should be ordered alphabetically.", + "section": "Preamble > ISA Extension Naming Conventions > Machine-Level Instruction-Set Extension Names", + "line_range": [ + 120, + 123 + ] + }, + { + "text": "Non-standard extensions are named by using a single \"X\" followed by the alphanumeric name.", + "section": "Preamble > ISA Extension Naming Conventions > Non-Standard Extension Names", + "line_range": [ + 127, + 130 + ] + }, + { + "text": "The name must end with an alphabetic character.", + "section": "Preamble > ISA Extension Naming Conventions > Non-Standard Extension Names", + "line_range": [ + 127, + 130 + ] + }, + { + "text": "The second letter from the end cannot be numeric if the last letter is \"p\".", + "section": "Preamble > ISA Extension Naming Conventions > Non-Standard Extension Names", + "line_range": [ + 127, + 130 + ] + }, + { + "text": "For example, \"Xhwacha\" names the Hwacha vector-fetch ISA extension cite:[hwacha-esscirc2014].", + "section": "Preamble > ISA Extension Naming Conventions > Non-Standard Extension Names", + "line_range": [ + 127, + 130 + ] + }, + { + "text": "Non-standard extensions must be listed after all standard extensions, and, like other multi-letter extensions, must be separated from other multi-letter extensions by an underscore.", + "section": "Preamble > ISA Extension Naming Conventions > Non-Standard Extension Names", + "line_range": [ + 132, + 135 + ] + }, + { + "text": "If multiple non-standard extensions are listed, they should be ordered alphabetically.", + "section": "Preamble > ISA Extension Naming Conventions > Non-Standard Extension Names", + "line_range": [ + 132, + 135 + ] + }, + { + "text": "For example, an ISA with non-standard extensions Argle and Bargle may be named \"RV64IZifenceiXargleXbargle\".", + "section": "Preamble > ISA Extension Naming Conventions > Non-Standard Extension Names", + "line_range": [ + 137, + 138 + ] + }, + { + "text": "Recognizing that instruction sets may expand or alter over time, we encode extension version numbers following the extension name.", + "section": "Preamble > ISA Extension Naming Conventions > Version Numbers", + "line_range": [ + 142, + 147 + ] + }, + { + "text": "Version numbers are divided into major and minor version numbers, separated by a \"p\".", + "section": "Preamble > ISA Extension Naming Conventions > Version Numbers", + "line_range": [ + 142, + 147 + ] + }, + { + "text": "If the minor version is \"0\", then \"p0\" can be omitted from the version string.", + "section": "Preamble > ISA Extension Naming Conventions > Version Numbers", + "line_range": [ + 142, + 147 + ] + }, + { + "text": "To avoid ambiguity, no extension name may end with a number or a \"p\" preceded by a number.", + "section": "Preamble > ISA Extension Naming Conventions > Version Numbers", + "line_range": [ + 142, + 147 + ] + }, + { + "text": "Because the \"P\" extension for Packed SIMD can be confused for the decimal point in a version number, it must be preceded by an underscore if it follows another extension with a version number.", + "section": "Preamble > ISA Extension Naming Conventions > Version Numbers", + "line_range": [ + 149, + 153 + ] + }, + { + "text": "For example, \"rv32i2p2\" means version 2.2 of RV32I, whereas \"rv32i2p2\" means version 2.0 of RV32I with version 2.0 of the P extension.", + "section": "Preamble > ISA Extension Naming Conventions > Version Numbers", + "line_range": [ + 149, + 153 + ] + }, + { + "text": "Changes in major version numbers imply a loss of backwards compatibility, whereas changes in only the minor version number must be backwards-compatible.", + "section": "Preamble > ISA Extension Naming Conventions > Version Numbers", + "line_range": [ + 155, + 160 + ] + }, + { + "text": "For example, the original 64-bit standard ISA defined in release 1.0 of this manual can be written in full as \"RV64I1p0M1p0A1p0F1p0D1p0\", more concisely as \"RV64I1M1A1F1D1\".", + "section": "Preamble > ISA Extension Naming Conventions > Version Numbers", + "line_range": [ + 155, + 160 + ] + }, + { + "text": "We define the default version of ratified standard extensions as follows:", + "section": "Preamble > ISA Extension Naming Conventions > Version Numbers", + "line_range": [ + 162, + 162 + ] + }, + { + "text": "Version 2 if the extension is one of the following extensions: I, E, M, A, F, D, Q, C, Zicntr, Zicsr, Zifencei, Zihintpause, Zihpm. - Version 1 otherwise.", + "section": "Preamble > ISA Extension Naming Conventions > Version Numbers", + "line_range": [ + 164, + 166 + ] + }, + { + "text": "For instance, \"RV32IV\" is equivalent to \"RV32I2V1\".", + "section": "Preamble > ISA Extension Naming Conventions > Version Numbers", + "line_range": [ + 168, + 168 + ] + }, + { + "text": "In canonical ISA name strings, components appear in the following order:", + "section": "Preamble > ISA Extension Naming Conventions > Canonical Order", + "line_range": [ + 172, + 172 + ] + }, + { + "text": "One-letter extensions, MAFDQCBPVH, in this order . Z-prefixed extensions .", + "section": "Preamble > ISA Extension Naming Conventions > Canonical Order", + "line_range": [ + 174, + 182 + ] + }, + { + "text": "Sm-prefixed extensions . X-prefixed extensions", + "section": "Preamble > ISA Extension Naming Conventions > Canonical Order", + "line_range": [ + 174, + 182 + ] + }, + { + "text": "For instance, RV32IMACV is canonical, whereas RV32IMAVC is not.", + "section": "Preamble > ISA Extension Naming Conventions > Canonical Order", + "line_range": [ + 184, + 184 + ] + }, + { + "text": "summarizes the standardized extension names.", + "section": "Preamble > ISA Extension Naming Conventions > Summary", + "line_range": [ + 188, + 188 + ] + }, + { + "text": ".Standard ISA extension names. | |Subset |Name |Implies", + "section": "Preamble > ISA Extension Naming Conventions > Summary", + "line_range": [ + 190, + 194 + ] + }, + { + "text": "3+^|*Standard Unprivileged Extensions*", + "section": "Preamble > ISA Extension Naming Conventions > Summary", + "line_range": [ + 202, + 202 + ] + }, + { + "text": "|Integer Multiplication and Division |M |Zmmul", + "section": "Preamble > ISA Extension Naming Conventions > Summary", + "line_range": [ + 204, + 204 + ] + }, + { + "text": "|Single-Precision Floating-Point |F |Zicsr", + "section": "Preamble > ISA Extension Naming Conventions > Summary", + "line_range": [ + 208, + 208 + ] + }, + { + "text": "|Double-Precision Floating-Point |D |F", + "section": "Preamble > ISA Extension Naming Conventions > Summary", + "line_range": [ + 210, + 210 + ] + }, + { + "text": "|General |G |IMAFDZicsrZifencei", + "section": "Preamble > ISA Extension Naming Conventions > Summary", + "line_range": [ + 212, + 212 + ] + }, + { + "text": "|Quad-Precision Floating-Point |Q |D", + "section": "Preamble > ISA Extension Naming Conventions > Summary", + "line_range": [ + 214, + 214 + ] + }, + { + "text": "|16-bit Compressed Instructions |C |", + "section": "Preamble > ISA Extension Naming Conventions > Summary", + "line_range": [ + 216, + 216 + ] + }, + { + "text": "3+^|*Additional Standard Unprivileged Extensions*", + "section": "Preamble > ISA Extension Naming Conventions > Summary", + "line_range": [ + 224, + 224 + ] + }, + { + "text": "|Unprivileged extension \"abc\" |Zabc |", + "section": "Preamble > ISA Extension Naming Conventions > Summary", + "line_range": [ + 226, + 226 + ] + }, + { + "text": "3+^|*Standard User-Level Extensions*", + "section": "Preamble > ISA Extension Naming Conventions > Summary", + "line_range": [ + 228, + 228 + ] + }, + { + "text": "|User-level extension \"def\" |Sudef |", + "section": "Preamble > ISA Extension Naming Conventions > Summary", + "line_range": [ + 230, + 230 + ] + }, + { + "text": "3+^|*Standard Supervisor-Level Extensions*", + "section": "Preamble > ISA Extension Naming Conventions > Summary", + "line_range": [ + 232, + 232 + ] + }, + { + "text": "|Supervisor-level extension \"ghi\" |Ssghi | |Supervisor-level virtual-memory extension \"jkl\" |Svjkl |", + "section": "Preamble > ISA Extension Naming Conventions > Summary", + "line_range": [ + 236, + 237 + ] + }, + { + "text": "3+^|*Standard Hypervisor-Level Extensions*", + "section": "Preamble > ISA Extension Naming Conventions > Summary", + "line_range": [ + 239, + 239 + ] + }, + { + "text": "|Hypervisor-level extension \"mno\" |Shmno |", + "section": "Preamble > ISA Extension Naming Conventions > Summary", + "line_range": [ + 241, + 241 + ] + }, + { + "text": "3+^|*Standard Machine-Level Extensions*", + "section": "Preamble > ISA Extension Naming Conventions > Summary", + "line_range": [ + 243, + 243 + ] + }, + { + "text": "|Machine-level extension \"pqr\" |Smpqr |", + "section": "Preamble > ISA Extension Naming Conventions > Summary", + "line_range": [ + 245, + 245 + ] + }, + { + "text": "3+^|*Non-Standard Extensions*", + "section": "Preamble > ISA Extension Naming Conventions > Summary", + "line_range": [ + 247, + 247 + ] + }, + { + "text": "|Non-standard extension \"stu\" |Xstu | |", + "section": "Preamble > ISA Extension Naming Conventions > Summary", + "line_range": [ + 249, + 250 + ] + } + ] +} \ No newline at end of file diff --git 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|*1.0* |*Za64rs* |*1.0* |*Zic64b* |*1.0* |*Ziccamoa* |*1.0* |*Ziccamoc* |*1.0* |*Ziccif* |*1.0* |*Zicclsm* |*1.0* |*Ziccrse* |*1.0* |", + "section": "Preamble > Preface", + "line_range": [ + 24, + 124 + ] + }, + { + "text": "The changes in this version of the document include:", + "section": "Preamble > Preface", + "line_range": [ + 126, + 126 + ] + }, + { + "text": "Addition of extensions that have already been ratified as part of the profile specifications. * Numerous non-normative descriptive improvements.", + "section": "Preamble > Preface", + "line_range": [ + 128, + 130 + ] + }, + { + "text": "[.big]*Preface to Document Version 20260120*", + "section": "Preamble > Preface", + "line_range": [ + 132, + 132 + ] + }, + { + "text": "This document describes the RISC-V unprivileged architecture.", + "section": "Preamble > Preface", + "line_range": [ + 134, + 136 + ] + }, + { + "text": "It contains the following versions of the RISC-V ISA modules, all of which have been ratified:", + "section": "Preamble > Preface", + "line_range": [ + 134, + 136 + ] + }, + { + "text": "| |Base |Version |Status |*RV32I* |*2.1* |*Ratified* |*RV32E* |*2.0* |*Ratified* |*RV64E* |*2.0* |*Ratified* |*RV64I* |*2.1* |*Ratified*", + "section": "Preamble > Preface", + "line_range": [ + 138, + 144 + ] + }, + { + "text": "h|Extension h|Version h|Status", + "section": "Preamble > Preface", + "line_range": [ + 146, + 146 + ] + }, + { + "text": "|*Zifencei* |*2.0* |*Ratified* |*Zicsr* |*2.0* |*Ratified* |*Zicntr* |*2.0* |*Ratified* |*Zihpm* | *2.0* | *Ratified* |*Zihintntl* |*1.0* |*Ratified* |*Zihintpause* |*2.0* |*Ratified* |*Zimop* | *1.0* | *Ratified* |*Zicond* | *1.0* |*Ratified* |*Zilsd* | *1.0* |*Ratified* |*M* |*2.0* |*Ratified* |*Zmmul* |*1.0* |*Ratified* |*A* |*2.1* |*Ratified* |*Zalrsc* |*1.0* | *Ratified* |*Zaamo* |*1.0* | *Ratified* |*Zawrs* |*1.0* |*Ratified* |*Zacas* |*1.0* |*Ratified* |*Zabha* |*1.0* |*Ratified* |*Zalasr* |*1.0* |*Ratified* |*RVWMO* |*2.0* |*Ratified* |*Ztso* |*1.0* |*Ratified* |*CMO* |*1.0* |*Ratified* |*F* |*2.2* |*Ratified* |*D* |*2.2* |*Ratified* |*Q* |*2.2* |*Ratified* |*Zfh* |*1.0* |*Ratified* |*Zfhmin* |*1.0* |*Ratified* |*BF16* |*1.0* |*Ratified* |*Zfa* |*1.0* |*Ratified* |*Zfinx* |*1.0* |*Ratified* |*Zdinx* |*1.0* |*Ratified* |*Zhinx* |*1.0* |*Ratified* |*Zhinxmin* |*1.0* |*Ratified* |*C* |*2.0* |*Ratified* |*Zce* |*1.0* |*Ratified* |*Zclsd* |*1.0* |*Ratified* |*B* |*1.0* |*Ratified* |*V* |*1.0* |*Ratified* |*Zbkb* |*1.0* |*Ratified* |*Zbkc* |*1.0* |*Ratified* |*Zbkx* |*1.0* |*Ratified* |*Zk* |*1.0* |*Ratified* |*Zks* |*1.0* |*Ratified* |*Zvbb* |*1.0* |*Ratified* |*Zvbc* |*1.0* |*Ratified* |*Zvkg* |*1.0* |*Ratified* |*Zvkned* |*1.0* |*Ratified* |*Zvknhb* |*1.0* |*Ratified* |*Zvksed* |*1.0* |*Ratified* |*Zvksh* |*1.0* |*Ratified* |*Zvkt* |*1.0* |*Ratified* |*Zicfiss* |*1.0* |*Ratified* |*Zicfilp* |*1.0* |*Ratified* |", + "section": "Preamble > Preface", + "line_range": [ + 148, + 200 + ] + }, + { + "text": "The changes in this version of the document include:", + "section": "Preamble > Preface", + "line_range": [ + 202, + 202 + ] + }, + { + "text": "Addition of the Zalasr extension for Load-Acquire/Store-Release operations.", + "section": "Preamble > Preface", + "line_range": [ + 204, + 204 + ] + }, + { + "text": "[.big]*Preface to Document Version 20250508*", + "section": "Preamble > Preface", + "line_range": [ + 206, + 206 + ] + }, + { + "text": "This document describes the RISC-V unprivileged architecture.", + "section": "Preamble > Preface", + "line_range": [ + 208, + 210 + ] + }, + { + "text": "It contains the following versions of the RISC-V ISA modules, all of which have been ratified:", + "section": "Preamble > Preface", + "line_range": [ + 208, + 210 + ] + }, + { + "text": "| |Base |Version |Status |*RV32I* |*2.1* |*Ratified* |*RV32E* |*2.0* |*Ratified* |*RV64E* |*2.0* |*Ratified* |*RV64I* |*2.1* |*Ratified*", + "section": "Preamble > Preface", + "line_range": [ + 212, + 218 + ] + }, + { + "text": "h|Extension h|Version h|Status", + "section": "Preamble > Preface", + "line_range": [ + 220, + 220 + ] + }, + { + "text": "|*Zifencei* |*2.0* |*Ratified* |*Zicsr* |*2.0* |*Ratified* |*Zicntr* |*2.0* |*Ratified* |*Zihintntl* |*1.0* |*Ratified* |*Zihintpause* |*2.0* |*Ratified* |*Zimop* | *1.0* | *Ratified* |*Zicond* | *1.0* |*Ratified* |*Zilsd* | *1.0* |*Ratified* |*M* |*2.0* |*Ratified* |*Zmmul* |*1.0* |*Ratified* |*A* |*2.1* |*Ratified* |*Zalrsc* |*1.0* | *Ratified* |*Zaamo* |*1.0* | *Ratified* |*Zawrs* |*1.0* |*Ratified* |*Zacas* |*1.0* |*Ratified* |*Zabha* |*1.0* |*Ratified* |*RVWMO* |*2.0* |*Ratified* |*Ztso* |*1.0* |*Ratified* |*CMO* |*1.0* |*Ratified* |*F* |*2.2* |*Ratified* |*D* |*2.2* |*Ratified* |*Q* |*2.2* |*Ratified* |*Zfh* |*1.0* |*Ratified* |*Zfhmin* |*1.0* |*Ratified* |*BF16* |*1.0* |*Ratified* |*Zfa* |*1.0* |*Ratified* |*Zfinx* |*1.0* |*Ratified* |*Zdinx* |*1.0* |*Ratified* |*Zhinx* |*1.0* |*Ratified* |*Zhinxmin* |*1.0* |*Ratified* |*C* |*2.0* |*Ratified* |*Zce* |*1.0* |*Ratified* |*Zclsd* |*1.0* |*Ratified* |*B* |*1.0* |*Ratified* |*V* |*1.0* |*Ratified* |*Zbkb* |*1.0* |*Ratified* |*Zbkc* |*1.0* |*Ratified* |*Zbkx* |*1.0* |*Ratified* |*Zk* |*1.0* |*Ratified* |*Zks* |*1.0* |*Ratified* |*Zvbb* |*1.0* |*Ratified* |*Zvbc* |*1.0* |*Ratified* |*Zvkg* |*1.0* |*Ratified* |*Zvkned* |*1.0* |*Ratified* |*Zvknhb* |*1.0* |*Ratified* |*Zvksed* |*1.0* |*Ratified* |*Zvksh* |*1.0* |*Ratified* |*Zvkt* |*1.0* |*Ratified* |*Zicfiss* |*1.0* |*Ratified* |*Zicfilp* |*1.0* |*Ratified* |", + "section": "Preamble > Preface", + "line_range": [ + 222, + 272 + ] + }, + { + "text": "The changes in this version of the document include:", + "section": "Preamble > Preface", + "line_range": [ + 274, + 274 + ] + }, + { + "text": "The inclusion of all ratified extensions through May 2025. * Removal of all unratified material. * Addition of the BFloat16-precision Floating Point extension. * Addition of the Zabha extension for Byte and Halfword Atomic Memory Operations.", + "section": "Preamble > Preface", + "line_range": [ + 276, + 279 + ] + }, + { + "text": "[.big]*Preface to Document Version 20240411*", + "section": "Preamble > Preface", + "line_range": [ + 281, + 281 + ] + }, + { + "text": "This document describes the RISC-V unprivileged architecture.", + "section": "Preamble > Preface", + "line_range": [ + 283, + 284 + ] + }, + { + "text": "It contains the following versions of the RISC-V ISA modules:", + "section": "Preamble > Preface", + "line_range": [ + 283, + 284 + ] + }, + { + "text": "| |Base |Version |Status |*RV32I* |*2.1* |*Ratified* |*RV32E* |*2.0* |*Ratified* |*RV64E* |*2.0* |*Ratified* |*RV64I* |*2.1* |*Ratified*", + "section": "Preamble > Preface", + "line_range": [ + 286, + 292 + ] + }, + { + "text": "h|Extension h|Version h|Status", + "section": "Preamble > Preface", + "line_range": [ + 294, + 294 + ] + }, + { + "text": "|*Zifencei* |*2.0* |*Ratified* |*Zicsr* |*2.0* |*Ratified* |*Zicntr* |*2.0* |*Ratified* |*Zihintntl* |*1.0* |*Ratified* |*Zihintpause* |*2.0* |*Ratified* |*Zimop* | *1.0* | *Ratified* |*Zicond* | *1.0* |*Ratified* |*Zilsd* | *1.0* |*Ratified* |*M* |*2.0* |*Ratified* |*Zmmul* |*1.0* |*Ratified* |*A* |*2.1* |*Ratified* |*Zalrsc* |*1.0* | *Ratified* |*Zaamo* |*1.0* | *Ratified* |*Zawrs* |*1.0* |*Ratified* |*Zacas* |*1.0* |*Ratified* |*Zabha* |*1.0* |*Ratified* |*RVWMO* |*2.0* |*Ratified* |*Ztso* |*1.0* |*Ratified* |*CMO* |*1.0* |*Ratified* |*F* |*2.2* |*Ratified* |*D* |*2.2* |*Ratified* |*Q* |*2.2* |*Ratified* |*Zfh* |*1.0* |*Ratified* |*Zfhmin* |*1.0* |*Ratified* |*Zfa* |*1.0* |*Ratified* |*Zfinx* |*1.0* |*Ratified* |*Zdinx* |*1.0* |*Ratified* |*Zhinx* |*1.0* |*Ratified* |*Zhinxmin* |*1.0* |*Ratified* |*C* |*2.0* |*Ratified* |*Zce* |*1.0* |*Ratified* |*Zclsd* |*1.0* |*Ratified* |*B* |*1.0* |*Ratified* |*V* |*1.0* |*Ratified* |*Zbkb* |*1.0* |*Ratified* |*Zbkc* |*1.0* |*Ratified* |*Zbkx* |*1.0* |*Ratified* |*Zk* |*1.0* |*Ratified* |*Zks* |*1.0* |*Ratified* |*Zvbb* |*1.0* |*Ratified* |*Zvbc* |*1.0* |*Ratified* |*Zvkg* |*1.0* |*Ratified* |*Zvkned* |*1.0* |*Ratified* |*Zvknhb* |*1.0* |*Ratified* |*Zvksed* |*1.0* |*Ratified* |*Zvksh* |*1.0* |*Ratified* |*Zvkt* |*1.0* |*Ratified* |*Zicfiss* |*1.0* |*Ratified* |*Zicfilp* |*1.0* |*Ratified* |", + "section": "Preamble > Preface", + "line_range": [ + 296, + 345 + ] + }, + { + "text": "The changes in this version of the document include:", + "section": "Preamble > Preface", + "line_range": [ + 347, + 347 + ] + }, + { + "text": "The inclusion of all ratified extensions through February 2025. * The draft Zam extension has been removed, in favor of the definition of a misaligned atomicity granule PMA. * The concept of vacant memory regions has been superseded by inaccessible memory or I/O regions. * The removal of unratified content, including the sketch of the RV128I base ISA.", + "section": "Preamble > Preface", + "line_range": [ + 349, + 352 + ] + }, + { + "text": "[.big]*Preface to Document Version 20191213-Base-Ratified*", + "section": "Preamble > Preface", + "line_range": [ + 354, + 354 + ] + }, + { + "text": "This document describes the RISC-V unprivileged architecture.", + "section": "Preamble > Preface", + "line_range": [ + 356, + 356 + ] + }, + { + "text": "The ISA modules marked *Ratified* have been ratified at this time.", + "section": "Preamble > Preface", + "line_range": [ + 358, + 361 + ] + }, + { + "text": "The modules marked Frozen are not expected to change significantly before being put up for ratification.", + "section": "Preamble > Preface", + "line_range": [ + 358, + 361 + ] + }, + { + "text": "The modules marked Draft are expected to change before ratification.", + "section": "Preamble > Preface", + "line_range": [ + 358, + 361 + ] + }, + { + "text": "The document contains the following versions of the RISC-V ISA modules:", + "section": "Preamble > Preface", + "line_range": [ + 363, + 363 + ] + }, + { + "text": "| |Base |Version |Status |RVWMO |2.0 |*Ratified* |*RV32I* |*2.1* |*Ratified* |*RV64I* |*2.1* |*Ratified* |RV32E |1.9 |Draft |RV128I |1.7 |Draft h|Extension h|Version h|Status |*M* |*2.0* |*Ratified* |*A* |*2.1* |*Ratified* |*F* |*2.2* |*Ratified* |*D* |*2.2* |*Ratified* |*Q* |*2.2* |*Ratified* |*C* |*2.0* |*Ratified* |Counters |2.0 |Draft |L |0.0 |Draft |B |0.0 |Draft |J |0.0 |Draft |T |0.0 |Draft |P |0.2 |Draft |V |0.7 |Draft |*Zicsr* |*2.0* |*Ratified* |*Zifencei* |*2.0* |*Ratified* |Zam |0.1 |Draft |Ztso |0.1 |Frozen |", + "section": "Preamble > Preface", + "line_range": [ + 365, + 391 + ] + }, + { + "text": "The changes in this version of the document include:", + "section": "Preamble > Preface", + "line_range": [ + 393, + 393 + ] + }, + { + "text": "The A extension, now version 2.1, was ratified by the board in December 2019. * Defined big-endian ISA variant. * Moved N extension for user-mode interrupts into Volume II. * Defined PAUSE hint instruction.", + "section": "Preamble > Preface", + "line_range": [ + 395, + 399 + ] + }, + { + "text": "[.big]*Preface to Document Version 20190608-Base-Ratified*", + "section": "Preamble > Preface", + "line_range": [ + 401, + 401 + ] + }, + { + "text": "This document describes the RISC-V unprivileged architecture.", + "section": "Preamble > Preface", + "line_range": [ + 403, + 403 + ] + }, + { + "text": "The RVWMO memory model has been ratified at this time.", + "section": "Preamble > Preface", + "line_range": [ + 405, + 409 + ] + }, + { + "text": "The ISA modules marked *Ratified*, have been ratified at this time.", + "section": "Preamble > Preface", + "line_range": [ + 405, + 409 + ] + }, + { + "text": "The modules marked Frozen are not expected to change significantly before being put up for ratification.", + "section": "Preamble > Preface", + "line_range": [ + 405, + 409 + ] + }, + { + "text": "The modules marked Draft are expected to change before ratification.", + "section": "Preamble > Preface", + "line_range": [ + 405, + 409 + ] + }, + { + "text": "The document contains the following versions of the RISC-V ISA modules:", + "section": "Preamble > Preface", + "line_range": [ + 411, + 411 + ] + }, + { + "text": "| |Base |Version |Status |RVWMO |2.0 |*Ratified* |*RV32I* |*2.1* |*Ratified* |*RV64I* |*2.1* |*Ratified* |RV32E |1.9 |Draft |RV128I |1.7 |Draft h|Extension h|Version h|Status |*Zifencei* |*2.0* |*Ratified* |*Zicsr* |*2.0* |*Ratified* |*M* |*2.0* |*Ratified* |A |2.0 |Frozen |*F* |*2.2* |*Ratified* |*D* |*2.2* |*Ratified* |*Q* |*2.2* |*Ratified* |*C* |*2.0* |*Ratified* |Ztso |0.1 |Frozen |Counters |2.0 |Draft |L |0.0 |Draft |B |0.0 |Draft |J |0.0 |Draft |T |0.0 |Draft |P |0.2 |Draft |V |0.7 |Draft |Zam |0.1 |Draft |", + "section": "Preamble > Preface", + "line_range": [ + 413, + 439 + ] + }, + { + "text": "The changes in this version of the document include:", + "section": "Preamble > Preface", + "line_range": [ + 441, + 441 + ] + }, + { + "text": "Moved description to *Ratified* for the ISA modules ratified by the board in early 2019. * Removed the A extension from ratification. * Changed document version scheme to avoid confusion with versions of the ISA modules. * Incremented the version numbers of the base integer ISA to 2.1, reflecting the presence of the ratified RVWMO memory model and exclusion of FENCE.I, counters, and CSR instructions that were in previous base ISA. * Incremented the version numbers of the F and D extensions to 2.2, reflecting that version 2.1 changed the canonical NaN, and version 2.2 defined the NaN-boxing scheme and changed the definition of the FMIN and FMAX instructions. * Changed name of document to refer to \"unprivileged\" instructions as part of move to separate ISA specifications from platform profile mandates. * Added clearer and more precise definitions of execution environments, harts, traps, and memory accesses. * Defined instruction-set categories: standard, reserved, custom, non-standard, and non-conforming. * Removed text implying operation under alternate endianness, as alternate-endianness operation has not yet been defined for RISC-V. * Changed description of misaligned load and store behavior.", + "section": "Preamble > Preface", + "line_range": [ + 443, + 503 + ] + }, + { + "text": "The specification now allows visible misaligned address traps in execution environment interfaces, rather than just mandating invisible handling of misaligned loads and stores in user mode.", + "section": "Preamble > Preface", + "line_range": [ + 443, + 503 + ] + }, + { + "text": "Also, now allows access-fault exceptions to be reported for misaligned accesses (including atomics) that should not be emulated. * Moved FENCE.I out of the mandatory base and into a separate extension, with Zifencei ISA name. FENCE.I was removed from the Linux user ABI and is problematic in implementations with large incoherent instruction and data caches.", + "section": "Preamble > Preface", + "line_range": [ + 443, + 503 + ] + }, + { + "text": "However, it remains the only standard instruction-fetch coherence mechanism. * Removed prohibitions on using RV32E with other extensions. * Removed platform-specific mandates that certain encodings produce illegal-instruction exceptions in RV32E and RV64I chapters. * Counter/timer instructions are now not considered part of the mandatory base ISA, and so CSR instructions were moved into separate chapter and marked as version 2.0, with the unprivileged counters moved into another separate chapter.", + "section": "Preamble > Preface", + "line_range": [ + 443, + 503 + ] + }, + { + "text": "The counters are not ready for ratification as there are outstanding issues, including counter inaccuracies. * A CSR-access ordering model has been added. * Explicitly defined the 16-bit half-precision floating-point format for floating-point instructions in the 2-bit fmt field. * Defined the signed-zero behavior of FMIN.fmt and FMAX.fmt, and changed their behavior on signaling-NaN inputs to conform to the `minimumNumber` and `maximumNumber` operations in the proposed IEEE 754-201x specification. * The memory consistency model, RVWMO, has been defined. * The \"Zam\" extension, which permits misaligned AMOs and specifies their semantics, has been defined. * The \"Ztso\" extension, which enforces a stricter memory consistency model than RVWMO, has been defined. * Improvements to the description and commentary. * Defined the term `IALIGN` as shorthand to describe the instruction-address alignment constraint. * Removed text of `P` extension chapter as now superseded by active task group documents. * Removed text of `V` extension chapter as now superseded by separate vector extension draft document.", + "section": "Preamble > Preface", + "line_range": [ + 443, + 503 + ] + }, + { + "text": "[.big]*Preface to Document Version 2.2*", + "section": "Preamble > Preface", + "line_range": [ + 505, + 505 + ] + }, + { + "text": "This is version 2.2 of the document describing the RISC-V user-level architecture.", + "section": "Preamble > Preface", + "line_range": [ + 507, + 509 + ] + }, + { + "text": "The document contains the following versions of the RISC-V ISA modules:", + "section": "Preamble > Preface", + "line_range": [ + 507, + 509 + ] + }, + { + "text": "| h|Base h|Version h|Draft Frozen? |RV32I |2.0 |Y |RV32E |1.9 |N |RV64I |2.0 |Y |RV128I |1.7 |N h|Extension h|Version h|Frozen? |M |2.0 |Y |A |2.0 |Y |F |2.0 |Y |D |2.0 |Y |Q |2.0 |Y |L |0.0 |N |C |2.0 |Y |B |0.0 |N |J |0.0 |N |T |0.0 |N |P |0.1 |N |V |0.7 |N |N |1.1 |N |", + "section": "Preamble > Preface", + "line_range": [ + 511, + 532 + ] + }, + { + "text": "To date, no parts of the standard have been officially ratified by the RISC-V Foundation, but the components labeled \"frozen\" above are not expected to change during the ratification process beyond resolving ambiguities and holes in the specification.", + "section": "Preamble > Preface", + "line_range": [ + 534, + 537 + ] + }, + { + "text": "The major changes in this version of the document include:", + "section": "Preamble > Preface", + "line_range": [ + 539, + 539 + ] + }, + { + "text": "The previous version of this document was released under a Creative Commons Attribution 4.0 International License by the original authors, and this and future versions of this document will be released under the same license. * Rearranged chapters to put all extensions first in canonical order. * Improvements to the description and commentary. * Modified implicit hinting suggestion on `JALR` to support more efficient macro-op fusion of `LUI/JALR` and `AUIPC/JALR` pairs. * Clarification of constraints on load-reserved/store-conditional sequences. * A new table of control and status register (CSR) mappings. * Clarified purpose and behavior of high-order bits of `fcsr`. * Corrected the description of the `FNMADD`.fmt and `FNMSUB`.fmt instructions, which had suggested the incorrect sign of a zero result. * Instructions `FMV.S.X` and `FMV.X.S` were renamed to `FMV.W.X` and `FMV.X.W` respectively to be more consistent with their semantics, which did not change.", + "section": "Preamble > Preface", + "line_range": [ + 541, + 569 + ] + }, + { + "text": "The old names will continue to be supported in the tools. * Specified behavior of narrower ( Preface", + "line_range": [ + 541, + 569 + ] + }, + { + "text": "[.big]*Preface to Document Version 2.1*", + "section": "Preamble > Preface", + "line_range": [ + 571, + 571 + ] + }, + { + "text": "This is version 2.1 of the document describing the RISC-V user-level architecture.", + "section": "Preamble > Preface", + "line_range": [ + 573, + 578 + ] + }, + { + "text": "Note the frozen user-level ISA base and extensions `IMAFDQ` version 2.0 have not changed from the previous version of this document cite:[riscvtr2], but some specification holes have been fixed and the documentation has been improved.", + "section": "Preamble > Preface", + "line_range": [ + 573, + 578 + ] + }, + { + "text": "Some changes have been made to the software conventions.", + "section": "Preamble > Preface", + "line_range": [ + 573, + 578 + ] + }, + { + "text": "Numerous additions and improvements to the commentary sections. * Separate version numbers for each chapter. * Modification to long instruction encodings >64 bits to avoid moving the rd specifier in very long instruction formats. * CSR instructions are now described in the base integer format where the counter registers are introduced, as opposed to only being introduced later in the floating-point section (and the companion privileged architecture manual). * The SCALL and SBREAK instructions have been renamed to `ECALL` and `EBREAK`, respectively.", + "section": "Preamble > Preface", + "line_range": [ + 580, + 601 + ] + }, + { + "text": "Their encoding and functionality are unchanged. * Clarification of floating-point NaN handling, and a new canonical NaN value. * Clarification of values returned by floating-point to integer conversions that overflow. * Clarification of `LR/SC` allowed successes and required failures, including use of compressed instructions in the sequence. * A new `RV32E` base ISA proposal for reduced integer register counts, supports `MAC` extensions. * A revised calling convention. * Relaxed stack alignment for soft-float calling convention, and description of the RV32E calling convention. * A revised proposal for the `C` compressed extension, version 1.9 .", + "section": "Preamble > Preface", + "line_range": [ + 580, + 601 + ] + }, + { + "text": "[.big]*Preface to Version 2.0*", + "section": "Preamble > Preface", + "line_range": [ + 603, + 603 + ] + }, + { + "text": "This is the second release of the user ISA specification, and we intend the specification of the base user ISA plus general extensions (i.e., IMAFD) to remain fixed for future development.", + "section": "Preamble > Preface", + "line_range": [ + 605, + 608 + ] + }, + { + "text": "The following changes have been made since Version 1.0 cite:[riscvtr] of this ISA specification.", + "section": "Preamble > Preface", + "line_range": [ + 605, + 608 + ] + }, + { + "text": "The ISA has been divided into an integer base with several standard extensions. * The instruction formats have been rearranged to make immediate encoding more efficient. * The base ISA has been defined to have a little-endian memory system, with big-endian or bi-endian as non-standard variants. * Load-Reserved/Store-Conditional (`LR/SC`) instructions have been added in the atomic instruction extension. * `AMOs` and `LR/SC` can support the release consistency model. * The `FENCE` instruction provides finer-grain memory and I/O orderings. * An `AMO` for fetch-and-`XOR` (`AMOXOR`) has been added, and the encoding for `AMOSWAP` has been changed to make room. * The `AUIPC` instruction, which adds a 20-bit upper immediate to the `PC`, replaces the `RDNPC` instruction, which only read the current `PC` value.", + "section": "Preamble > Preface", + "line_range": [ + 610, + 658 + ] + }, + { + "text": "This results in significant savings for position-independent code. * The `JAL` instruction has now moved to the `U-Type` format with an explicit destination register, and the `J` instruction has been dropped being replaced by `JAL` with rd=`x0`.", + "section": "Preamble > Preface", + "line_range": [ + 610, + 658 + ] + }, + { + "text": "This removes the only instruction with an implicit destination register and removes the `J-Type` instruction format from the base ISA.", + "section": "Preamble > Preface", + "line_range": [ + 610, + 658 + ] + }, + { + "text": "There is an accompanying reduction in `JAL` reach, but a significant reduction in base ISA complexity. * The static hints on the `JALR` instruction have been dropped.", + "section": "Preamble > Preface", + "line_range": [ + 610, + 658 + ] + }, + { + "text": "The hints are redundant with the rd and rs1 register specifiers for code compliant with the standard calling convention. * The `JALR` instruction now clears the lowest bit of the calculated target address, to simplify hardware and to allow auxiliary information to be stored in function pointers. * The `MFTX.S` and `MFTX.D` instructions have been renamed to `FMV.X.S` and `FMV.X.D`, respectively.", + "section": "Preamble > Preface", + "line_range": [ + 610, + 658 + ] + }, + { + "text": "Similarly, `MXTF.S` and `MXTF.D` instructions have been renamed to `FMV.S.X` and `FMV.D.X`, respectively. * The `MFFSR` and `MTFSR` instructions have been renamed to `FRCSR` and `FSCSR`, respectively. `FRRM`, `FSRM`, `FRFLAGS`, and `FSFLAGS` instructions have been added to individually access the rounding mode and exception flags subfields of the `fcsr`. * The `FMV.X.S` and `FMV.X.D` instructions now source their operands from rs1, instead of rs2.", + "section": "Preamble > Preface", + "line_range": [ + 610, + 658 + ] + }, + { + "text": "This change simplifies datapath design. * `FCLASS.S` and `FCLASS.D` floating-point classify instructions have been added. * A simpler NaN generation and propagation scheme has been adopted. * For `RV32I`, the system performance counters have been extended to 64-bits wide, with separate read access to the upper and lower 32 bits. * Canonical `NOP` and `MV` encodings have been defined. * Standard instruction-length encodings have been defined for 48-bit, 64-bit, and >64-bit instructions. * Description of a 128-bit address space variant, `RV128`, has been added. * Major opcodes in the 32-bit base instruction format have been allocated for user-defined custom extensions. * A typographical error that suggested that stores source their data from rd has been corrected to refer to rs2.", + "section": "Preamble > Preface", + "line_range": [ + 610, + 658 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__priv__cfi.json b/tools/llm-extraction/data/output/raw_chunks/src__priv__cfi.json new file mode 100644 index 0000000000..ce6ffd8c32 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__priv__cfi.json @@ -0,0 +1,558 @@ +{ + "source_file": "src/priv/cfi.adoc", + "total": 69, + "sentences": [ + { + "text": "Control-flow Integrity (CFI) capabilities help defend against Return-Oriented Programming (ROP) and Call/Jump-Oriented Programming (COP/JOP) style control-flow subversion attacks.", + "section": "Preamble > Control-flow Integrity (CFI)", + "line_range": [ + 3, + 8 + ] + }, + { + "text": "The Zicfiss and Zicfilp extensions provide backward-edge and forward-edge control flow integrity respectively.", + "section": "Preamble > Control-flow Integrity (CFI)", + "line_range": [ + 3, + 8 + ] + }, + { + "text": "Please see the Control-flow Integrity chapter of the Unprivileged ISA specification for further details on these CFI capabilities and the associated Unprivileged ISA.", + "section": "Preamble > Control-flow Integrity (CFI)", + "line_range": [ + 3, + 8 + ] + }, + { + "text": "This section specifies the Privileged ISA for the Zicfilp extension.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp)", + "line_range": [ + 13, + 13 + ] + }, + { + "text": "The term `xLPE` is used to determine if forward-edge CFI using landing pads provided by the Zicfilp extension is enabled at a privilege mode.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing-Pad-Enabled (LPE) State", + "line_range": [ + 18, + 19 + ] + }, + { + "text": "When S-mode is implemented, it is determined as follows:", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing-Pad-Enabled (LPE) State", + "line_range": [ + 21, + 21 + ] + }, + { + "text": ".`xLPE` determination when S-mode is implemented [width=100%] | |Privilege Mode| xLPE | M | `mseccfg.MLPE` | S or HS | `menvcfg.LPE` | VS | `henvcfg.LPE` | U or VU | `senvcfg.LPE` |", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing-Pad-Enabled (LPE) State", + "line_range": [ + 23, + 32 + ] + }, + { + "text": "When S-mode is not implemented, it is determined as follows:", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing-Pad-Enabled (LPE) State", + "line_range": [ + 34, + 34 + ] + }, + { + "text": ".`xLPE` determination when S-mode is not implemented [width=100%] | |Privilege Mode| xLPE | M | `mseccfg.MLPE` | U | `menvcfg.LPE` |", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing-Pad-Enabled (LPE) State", + "line_range": [ + 36, + 43 + ] + }, + { + "text": "A trap may need to be delivered to the same or to a higher privilege mode upon completion of `JALR`/`C.JALR`/`C.JR`, but before the instruction at the target of indirect call/jump was decoded, due to:", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing-Pad-Enabled (LPE) State > Preserving Expected Landing Pad State on Traps", + "line_range": [ + 50, + 52 + ] + }, + { + "text": "Asynchronous interrupts. * Synchronous exceptions with priority higher than that of a software-check exception with `xtval` set to \"landing pad fault (code=2)\" (See of Privileged Specification).", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing-Pad-Enabled (LPE) State > Preserving Expected Landing Pad State on Traps", + "line_range": [ + 54, + 57 + ] + }, + { + "text": "The software-check exception caused by Zicfilp has higher priority than an illegal-instruction exception but lower priority than instruction access-fault.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing-Pad-Enabled (LPE) State > Preserving Expected Landing Pad State on Traps", + "line_range": [ + 59, + 61 + ] + }, + { + "text": "The software-check exception due to the instruction not being an `LPAD` instruction when `ELP` is `LPEXPECTED` or a software-check exception caused by the `LPAD` instruction itself leads to a trap being delivered to the same or to a higher privilege mode.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing-Pad-Enabled (LPE) State > Preserving Expected Landing Pad State on Traps", + "line_range": [ + 63, + 67 + ] + }, + { + "text": "In such cases, the `ELP` prior to the trap, the previous `ELP`, must be preserved by the trap delivery such that it can be restored on a return from the trap.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing-Pad-Enabled (LPE) State > Preserving Expected Landing Pad State on Traps", + "line_range": [ + 69, + 77 + ] + }, + { + "text": "To store the previous `ELP` state on trap delivery to M-mode, an `MPELP` bit is provided in the `mstatus` CSR.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing-Pad-Enabled (LPE) State > Preserving Expected Landing Pad State on Traps", + "line_range": [ + 69, + 77 + ] + }, + { + "text": "To store the previous `ELP` state on trap delivery to S/HS-mode, an `SPELP` bit is provided in the `mstatus` CSR.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing-Pad-Enabled (LPE) State > Preserving Expected Landing Pad State on Traps", + "line_range": [ + 69, + 77 + ] + }, + { + "text": "The `SPELP` bit in `mstatus` can be accessed through the `sstatus` CSR.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing-Pad-Enabled (LPE) State > Preserving Expected Landing Pad State on Traps", + "line_range": [ + 69, + 77 + ] + }, + { + "text": "To store the previous `ELP` state on traps to VS-mode, a `SPELP` bit is defined in the `vsstatus` (VS-modes version of `sstatus`).", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing-Pad-Enabled (LPE) State > Preserving Expected Landing Pad State on Traps", + "line_range": [ + 69, + 77 + ] + }, + { + "text": "To store the previous `ELP` state on transition to Debug Mode, a `pelp` bit is defined in the `dcsr` register.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing-Pad-Enabled (LPE) State > Preserving Expected Landing Pad State on Traps", + "line_range": [ + 69, + 77 + ] + }, + { + "text": "When a trap is taken into privilege mode `x`, the `xPELP` is set to `ELP` and `ELP` is set to `NOLPEXPECTED`.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing-Pad-Enabled (LPE) State > Preserving Expected Landing Pad State on Traps", + "line_range": [ + 79, + 81 + ] + }, + { + "text": "An `MRET` or `SRET` instruction is used to return from a trap in M-mode or S-mode, respectively.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing-Pad-Enabled (LPE) State > Preserving Expected Landing Pad State on Traps", + "line_range": [ + 83, + 88 + ] + }, + { + "text": "When executing an `xRET` instruction, if the new privilege mode is `y`, then `ELP` is set to the value of `xPELP` if `yLPE` (see ) is 1; otherwise, it is set to `NOLPEXPECTED`; `xPELP` is set to `NOLPEXPECTED`.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing-Pad-Enabled (LPE) State > Preserving Expected Landing Pad State on Traps", + "line_range": [ + 83, + 88 + ] + }, + { + "text": "Upon entry into Debug Mode, the `pelp` bit in `dcsr` is updated with the `ELP` at the privilege level the hart was previously in, and the `ELP` is set to `NOLPEXPECTED`.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing-Pad-Enabled (LPE) State > Preserving Expected Landing Pad State on Traps", + "line_range": [ + 90, + 95 + ] + }, + { + "text": "When a hart resumes from Debug Mode, if the new privilege mode is `y`, then `ELP` is set to the value of `pelp` if `yLPE` (see ) is 1; otherwise, it is set to `NOLPEXPECTED`.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing-Pad-Enabled (LPE) State > Preserving Expected Landing Pad State on Traps", + "line_range": [ + 90, + 95 + ] + }, + { + "text": "See also for semantics added to the RNMI trap and the MNRET instruction when this extension is implemented.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing-Pad-Enabled (LPE) State > Preserving Expected Landing Pad State on Traps", + "line_range": [ + 97, + 98 + ] + }, + { + "text": "This section specifies the Privileged ISA for the Zicfiss extension.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss)", + "line_range": [ + 105, + 105 + ] + }, + { + "text": "Attempts to access the `ssp` CSR may result in either an illegal-instruction exception or a virtual-instruction exception, contingent upon the state of the *x*`envcfg.SSE` fields.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Pointer (`ssp`) CSR access control", + "line_range": [ + 109, + 112 + ] + }, + { + "text": "The conditions are specified as follows:", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Pointer (`ssp`) CSR access control", + "line_range": [ + 109, + 112 + ] + }, + { + "text": "If the privilege mode is less than M and `menvcfg.SSE` is 0, an illegal-instruction exception is raised. *", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Pointer (`ssp`) CSR access control", + "line_range": [ + 114, + 122 + ] + }, + { + "text": "Otherwise, if in U-mode and `senvcfg.SSE` is 0, an illegal-instruction exception is raised. *", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Pointer (`ssp`) CSR access control", + "line_range": [ + 114, + 122 + ] + }, + { + "text": "Otherwise, if in VS-mode and `henvcfg.SSE` is 0, a virtual-instruction exception is raised. *", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Pointer (`ssp`) CSR access control", + "line_range": [ + 114, + 122 + ] + }, + { + "text": "Otherwise, if in VU-mode and either `henvcfg.SSE` or `senvcfg.SSE` is 0, a virtual-instruction exception is raised. *", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Pointer (`ssp`) CSR access control", + "line_range": [ + 114, + 122 + ] + }, + { + "text": "Otherwise, the access is allowed.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Pointer (`ssp`) CSR access control", + "line_range": [ + 114, + 122 + ] + }, + { + "text": "The term `xSSE` is used to determine if backward-edge CFI using shadow stacks provided by the Zicfiss extension is enabled at a privilege mode.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow-Stack-Enabled (SSE) State", + "line_range": [ + 126, + 127 + ] + }, + { + "text": "When S-mode is implemented, it is determined as follows:", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow-Stack-Enabled (SSE) State", + "line_range": [ + 129, + 129 + ] + }, + { + "text": ".`xSSE` determination when S-mode is implemented [width=100%] | |Privilege Mode| `xSSE` | M | `0` | S or HS | `menvcfg.SSE` | VS | `henvcfg.SSE` | U or VU | `senvcfg.SSE` |", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow-Stack-Enabled (SSE) State", + "line_range": [ + 131, + 140 + ] + }, + { + "text": "When S-mode is not implemented, then `xSSE` is 0 at both M and U privilege modes.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow-Stack-Enabled (SSE) State", + "line_range": [ + 142, + 143 + ] + }, + { + "text": "NOTE: Changes to `xSSE` take effect immediately; address-translation caches need not be synchronized with SFENCE.VMA, HFENCE.GVMA, or HFENCE.VVMA instructions.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow-Stack-Enabled (SSE) State", + "line_range": [ + 145, + 147 + ] + }, + { + "text": "To protect shadow stack memory, the memory is associated with a new page type – the Shadow Stack (SS) page – in the single-stage and VS-stage page tables.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Memory Protection", + "line_range": [ + 153, + 157 + ] + }, + { + "text": "The encoding `R=0`, `W=1`, and `X=0`, is defined to represent an SS page.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Memory Protection", + "line_range": [ + 153, + 157 + ] + }, + { + "text": "When `menvcfg.SSE=0`, this encoding remains reserved.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Memory Protection", + "line_range": [ + 153, + 157 + ] + }, + { + "text": "Similarly, when `V=1` and `henvcfg.SSE=0`, this encoding remains reserved at `VS` and `VU` levels.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Memory Protection", + "line_range": [ + 153, + 157 + ] + }, + { + "text": "If `satp.MODE` (or `vsatp.MODE` when `V=1`) is set to `Bare` and the effective privilege mode is less than M, shadow stack instructions raise a store/AMO access-fault exception.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Memory Protection", + "line_range": [ + 159, + 162 + ] + }, + { + "text": "When the effective privilege mode is M, memory access by an `SSAMOSWAP.W/D` instruction results in a store/AMO access-fault exception.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Memory Protection", + "line_range": [ + 159, + 162 + ] + }, + { + "text": "Memory mapped as an SS page cannot be written to by instructions other than `SSAMOSWAP.W/D`, `SSPUSH`, and `C.SSPUSH`.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Memory Protection", + "line_range": [ + 164, + 171 + ] + }, + { + "text": "Attempts will raise a store/AMO access-fault exception.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Memory Protection", + "line_range": [ + 164, + 171 + ] + }, + { + "text": "Access to a SS page using cache-block operation (`CBO.*`) instructions is not permitted.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Memory Protection", + "line_range": [ + 164, + 171 + ] + }, + { + "text": "Such accesses will raise a store/AMO access-fault exception.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Memory Protection", + "line_range": [ + 164, + 171 + ] + }, + { + "text": "Implicit accesses, including instruction fetches to an SS page, are not permitted.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Memory Protection", + "line_range": [ + 164, + 171 + ] + }, + { + "text": "Such accesses will raise an access-fault exception appropriate to the access type.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Memory Protection", + "line_range": [ + 164, + 171 + ] + }, + { + "text": "However, the shadow stack is readable by all instructions that only load from memory.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Memory Protection", + "line_range": [ + 164, + 171 + ] + }, + { + "text": "If a shadow stack (SS) instruction raises an access-fault, page-fault, or guest-page-fault exception that is supposed to indicate the original instruction type (load or store/AMO), then the reported exception cause is respectively a store/AMO access fault (code 7), a store/AMO page fault (code 15), or a store/AMO guest-page fault (code 23).", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Memory Protection", + "line_range": [ + 173, + 180 + ] + }, + { + "text": "For shadow stack instructions, the reported instruction type is always as though it were a store or AMO, even for instructions `SSPOPCHK` and `C.SSPOPCHK` that only read from memory and do not write to it.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Memory Protection", + "line_range": [ + 173, + 180 + ] + }, + { + "text": "Shadow stack instructions are restricted to accessing shadow stack (`pte.xwr=010b`) pages.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Memory Protection", + "line_range": [ + 182, + 187 + ] + }, + { + "text": "Should a shadow stack instruction access a page that is not designated as a shadow stack page and is not marked as read-only (`pte.xwr=001`), a store/AMO access-fault exception will be invoked.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Memory Protection", + "line_range": [ + 182, + 187 + ] + }, + { + "text": "Conversely, if the page being accessed by a shadow stack instruction is a read-only page, a store/AMO page-fault exception will be triggered.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Memory Protection", + "line_range": [ + 182, + 187 + ] + }, + { + "text": "If the virtual address in `ssp` is not `XLEN` aligned, then the `SSPUSH`/ `C.SSPUSH`/`SSPOPCHK`/`C.SSPOPCHK` instructions cause a store/AMO access-fault exception.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Memory Protection", + "line_range": [ + 191, + 194 + ] + }, + { + "text": "Correct execution of shadow stack instructions that access memory requires the the accessed memory to be idempotent.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Memory Protection", + "line_range": [ + 196, + 199 + ] + }, + { + "text": "If the memory referenced by `SSPUSH`/`C.SSPUSH`/`SSPOPCHK`/`C.SSPOPCHK`/`SSAMOSWAP.W/D` instructions is not idempotent, then the instructions cause a store/AMO access-fault exception.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Memory Protection", + "line_range": [ + 196, + 199 + ] + }, + { + "text": "The `U` and `SUM` bit enforcement is performed normally for shadow stack instruction initiated memory accesses.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Memory Protection", + "line_range": [ + 201, + 204 + ] + }, + { + "text": "The state of the `MXR` bit does not affect read access to a shadow stack page as the shadow stack page is always readable by all instructions that load from memory.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Memory Protection", + "line_range": [ + 201, + 204 + ] + }, + { + "text": "The G-stage address translation and protections remain unaffected by the Zicfiss extension.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Memory Protection", + "line_range": [ + 206, + 210 + ] + }, + { + "text": "The `xwr 010b` encoding in the G-stage PTE remains reserved.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Memory Protection", + "line_range": [ + 206, + 210 + ] + }, + { + "text": "When G-stage page tables are active, the shadow stack instructions that access memory require the G-stage page table to have read-write permission for the accessed memory; else a store/AMO guest-page-fault exception is raised.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Memory Protection", + "line_range": [ + 206, + 210 + ] + }, + { + "text": "Svpbmt and Svnapot extensions are supported for shadow stack pages.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Memory Protection", + "line_range": [ + 212, + 212 + ] + }, + { + "text": "The PMA checks are extended to require memory referenced by shadow stack instructions to be idempotent.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Memory Protection", + "line_range": [ + 214, + 218 + ] + }, + { + "text": "The PMP checks are extended to require read-write permission for memory accessed by shadow stack instructions.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Memory Protection", + "line_range": [ + 214, + 218 + ] + }, + { + "text": "If the PMP does not provide read-write permissions or if the accessed memory is not idempotent then a store/AMO access-fault exception is raised.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Memory Protection", + "line_range": [ + 214, + 218 + ] + }, + { + "text": "The `SSAMOSWAP.W/D` instructions require the PMA of the accessed memory range to provide AMOSwap level support.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Memory Protection", + "line_range": [ + 220, + 221 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__priv__csrs.json b/tools/llm-extraction/data/output/raw_chunks/src__priv__csrs.json new file mode 100644 index 0000000000..99c5f791d9 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__priv__csrs.json @@ -0,0 +1,1014 @@ +{ + "source_file": "src/priv/csrs.adoc", + "total": 126, + "sentences": [ + { + "text": "The SYSTEM major opcode is used to encode all privileged instructions in the RISC-V ISA.", + "section": "Preamble > Control and Status Registers (CSRs)", + "line_range": [ + 3, + 9 + ] + }, + { + "text": "These can be divided into two main classes: those that atomically read-modify-write control and status registers (CSRs), which are defined in the Zicsr extension, and all other privileged instructions.", + "section": "Preamble > Control and Status Registers (CSRs)", + "line_range": [ + 3, + 9 + ] + }, + { + "text": "The privileged architecture requires the Zicsr extension; which other privileged instructions are required depends on the privileged-architecture feature set.", + "section": "Preamble > Control and Status Registers (CSRs)", + "line_range": [ + 3, + 9 + ] + }, + { + "text": "In addition to the unprivileged state described in Volume I of this manual, an implementation may contain additional CSRs, accessible by some subset of the privilege levels using the CSR instructions described in .", + "section": "Preamble > Control and Status Registers (CSRs)", + "line_range": [ + 11, + 19 + ] + }, + { + "text": "In this chapter, we map out the CSR address space.", + "section": "Preamble > Control and Status Registers (CSRs)", + "line_range": [ + 11, + 19 + ] + }, + { + "text": "The following chapters describe the function of each of the CSRs according to privilege level, as well as the other privileged instructions which are generally closely associated with a particular privilege level.", + "section": "Preamble > Control and Status Registers (CSRs)", + "line_range": [ + 11, + 19 + ] + }, + { + "text": "Note that although CSRs and instructions are associated with one privilege level, they are also accessible at all higher privilege levels.", + "section": "Preamble > Control and Status Registers (CSRs)", + "line_range": [ + 11, + 19 + ] + }, + { + "text": "Standard CSRs do not have side effects on reads but may have side effects on writes.", + "section": "Preamble > Control and Status Registers (CSRs)", + "line_range": [ + 21, + 22 + ] + }, + { + "text": "The standard RISC-V ISA sets aside a 12-bit encoding space (csr[11:0]) for up to 4,096 CSRs.", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Address Mapping Conventions", + "line_range": [ + 26, + 30 + ] + }, + { + "text": "By convention, the upper 4 bits of the CSR address (csr[11:8]) are used to encode the read and write accessibility of the CSRs according to privilege level as shown in .", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Address Mapping Conventions", + "line_range": [ + 26, + 30 + ] + }, + { + "text": "The top two bits (csr[11:10]) indicate whether the register is read/write (`00`,`01`, or `10`) or read-only (`11`).", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Address Mapping Conventions", + "line_range": [ + 26, + 30 + ] + }, + { + "text": "The next two bits (csr[9:8]) encode the lowest privilege level that can access the CSR, with the pattern `10` representing hypervisor CSRs.", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Address Mapping Conventions", + "line_range": [ + 26, + 30 + ] + }, + { + "text": "Instructions that access a non-existent CSR are reserved.", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Address Mapping Conventions", + "line_range": [ + 32, + 38 + ] + }, + { + "text": "Attempts to access a CSR without appropriate privilege level raise illegal-instruction exceptions or, as described in , virtual-instruction exceptions.", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Address Mapping Conventions", + "line_range": [ + 32, + 38 + ] + }, + { + "text": "Attempts to write a read-only register raise illegal-instruction exceptions. A read/write register might also contain some bits that are read-only, in which case writes to the read-only bits are ignored.", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Address Mapping Conventions", + "line_range": [ + 32, + 38 + ] + }, + { + "text": "also indicates the convention to allocate CSR addresses between standard and custom uses.", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Address Mapping Conventions", + "line_range": [ + 40, + 43 + ] + }, + { + "text": "The CSR addresses designated for custom uses will not be redefined by future standard extensions.", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Address Mapping Conventions", + "line_range": [ + 40, + 43 + ] + }, + { + "text": "Machine-mode standard read-write CSRs `0x7A0`-`0x7BF` are reserved for use by the debug system.", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Address Mapping Conventions", + "line_range": [ + 45, + 50 + ] + }, + { + "text": "Of these CSRs, `0x7A0`-`0x7AF` are accessible to machine mode, whereas `0x7B0`-`0x7BF` are only visible to debug mode.", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Address Mapping Conventions", + "line_range": [ + 45, + 50 + ] + }, + { + "text": "Implementations should raise illegal-instruction exceptions on machine-mode access to the latter set of registers.", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Address Mapping Conventions", + "line_range": [ + 45, + 50 + ] + }, + { + "text": ".Allocation of RISC-V CSR address ranges. [.monofont] | 3+^|CSR Address 2.2+|Hex 3.2+|Use and Accessibility |[11:10] |[9:8] |[7:4] 8+|Unprivileged and User-Level CSRs m|00 m|00 m|XXXX 2+m| 0x000-0x0FF 3+|Standard read/write |`01` |`00` |`XXXX` 2+| `0x400-0x4FF` 3+|Standard read/write |`10` |`00` |`XXXX` 2+| `0x800-0x8FF` 3+|Custom read/write |`11` |`00` |`0XXX` 2+| `0xC00-0xC7F` 3+|Standard read-only |`11` |`00` |`10XX` 2+| `0xC80-0xCBF` 3+|Standard read-only |`11` |`00` |`11XX` 2+| `0xCC0-0xCFF` 3+|Custom read-only 8+|Supervisor-Level CSRs |`00` |`01` |`XXXX` 2+| `0x100-0x1FF` 3+|Standard read/write |`01` |`01` |`0XXX` 2+| `0x500-0x57F` 3+|Standard read/write |`01` |`01` |`10XX` 2+| `0x580-0x5BF` 3+|Standard read/write |`01` |`01` |`11XX` 2+| `0x5C0-0x5FF` 3+|Custom read/write |`10` |`01` |`0XXX` 2+| `0x900-0x97F` 3+|Standard read/write |`10` |`01` |`10XX` 2+| `0x980-0x9BF` 3+|Standard read/write |`10` |`01` |`11XX` 2+| `0x9C0-0x9FF` 3+|Custom read/write |`11` |`01` |`0XXX` 2+| `0xD00-0xD7F` 3+|Standard read-only |`11` |`01` |`10XX` 2+| `0xD80-0xDBF` 3+|Standard read-only |`11` |`01` |`11XX` 2+| `0xDC0-0xDFF` 3+|Custom read-only 8+|Hypervisor and VS CSRs |`00` |`10` |`XXXX` 2+| `0x200-0x2FF` 3+|Standard read/write |`01` |`10` |`0XXX` 2+| `0x600-0x67F` 3+|Standard read/write |`01` |`10` |`10XX` 2+| `0x680-0x6BF` 3+|Standard read/write |`01` |`10` |`11XX` 2+| `0x6C0-0x6FF` 3+|Custom read/write |`10` |`10` |`0XXX` 2+| `0xA00-0xA7F` 3+|Standard read/write |`10` |`10` |`10XX` 2+| `0xA80-0xABF` 3+|Standard read/write |`10` |`10` |`11XX` 2+| `0xAC0-0xAFF` 3+|Custom read/write |`11` |`10` |`0XXX` 2+| `0xE00-0xE7F` 3+|Standard read-only |`11` |`10` |`10XX` 2+| `0xE80-0xEBF` 3+|Standard read-only |`11` |`10` |`11XX` 2+| `0xEC0-0xEFF` 3+|Custom read-only 8+|Machine-Level CSRs |`00` |`11` |`XXXX` 2+|`0x300-0x3FF` 3+|Standard read/write |`01` |`11` |`0XXX` 2+|`0x700-0x77F` 3+|Standard read/write |`01` |`11` |`100X` 2+|`0x780-0x79F` 3+|Standard read/write |`01` |`11` |`1010` 2+|`0x7A0-0x7AF` 3+|Standard read/write debug CSRs |`01` |`11` |`1011` 2+|`0x7B0-0x7BF` 3+|Debug-mode-only CSRs |`01` |`11` |`11XX` 2+|`0x7C0-0x7FF` 3+|Custom read/write |`10` |`11` |`0XXX` 2+|`0xB00-0xB7F` 3+|Standard read/write |`10` |`11` |`10XX` 2+|`0xB80-0xBBF` 3+|Standard read/write |`10` |`11` |`11XX` 2+|`0xBC0-0xBFF` 3+|Custom read/write |`11` |`11` |`0XXX` 2+|`0xF00-0xF7F` 3+|Standard read-only |`11` |`11` |`10XX` 2+|`0xF80-0xFBF` 3+|Standard read-only |`11` |`11` |`11XX` 2+|`0xFC0-0xFFF` 3+|Custom read-only |", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Address Mapping Conventions", + "line_range": [ + 52, + 101 + ] + }, + { + "text": "list the CSRs that have currently been allocated CSR addresses.", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing", + "line_range": [ + 107, + 111 + ] + }, + { + "text": "The timers, counters, and floating-point CSRs are standard unprivileged CSRs.", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing", + "line_range": [ + 107, + 111 + ] + }, + { + "text": "The other registers are used by privileged code, as described in the following chapters.", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing", + "line_range": [ + 107, + 111 + ] + }, + { + "text": "Note that not all registers are required on all implementations.", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing", + "line_range": [ + 107, + 111 + ] + }, + { + "text": ".Currently allocated RISC-V unprivileged CSR addresses. [float=\"center\",align=\"center\",cols=\"<10%,<10%,<20%,<60%\",options=\"header\"] | |Number |Privilege |Name |Description 4+^|Unprivileged Floating-Point CSRs", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V unprivileged CSR addresses", + "line_range": [ + 115, + 120 + ] + }, + { + "text": "|`0x001` + `0x002` + `0x003` |URW + URW + URW |`fflags` + `frm` + `fcsr` |Floating-Point Accrued Exceptions. + Floating-Point Dynamic Rounding Mode. + Floating-Point Control and Status Register (`frm` +`fflags`).", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V unprivileged CSR addresses", + "line_range": [ + 122, + 133 + ] + }, + { + "text": "4+^|Unprivileged Vector CSRs", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V unprivileged CSR addresses", + "line_range": [ + 135, + 135 + ] + }, + { + "text": "|`0x008` + `0x009` + `0x00A` + `0x00F` + `0xC20` + `0xC21` + `0xC22` |URW + URW + URW + URW + URO + URO + URO |`vstart` + `vxsat` + `vxrm` + `vcsr` + `vl` + `vtype` + `vlenb` |Vector start position. + Fixed-point accrued saturation flag. + Fixed-point rounding mode. + Vector control and status register. + Vector length. + Vector data type register. + Vector register length in bytes.", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V unprivileged CSR addresses", + "line_range": [ + 137, + 164 + ] + }, + { + "text": "4+^|Unprivileged Zicfiss extension CSR |`0x011` + |URW + |`ssp` + |Shadow Stack Pointer. +", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V unprivileged CSR addresses", + "line_range": [ + 166, + 170 + ] + }, + { + "text": "4+^|Unprivileged Entropy Source Extension CSR |`0x015` + |URW + |`seed` + |Seed for cryptographic random bit generators. +", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V unprivileged CSR addresses", + "line_range": [ + 172, + 176 + ] + }, + { + "text": "4+^|Unprivileged Zcmt Extension CSR |`0x017` + |URW + |`jvt` + |Table jump base vector and control register. +", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V unprivileged CSR addresses", + "line_range": [ + 178, + 182 + ] + }, + { + "text": "4+^|Unprivileged Counter/Timers", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V unprivileged CSR addresses", + "line_range": [ + 184, + 184 + ] + }, + { + "text": "|`0xC00` + `0xC01` + `0xC02` + `0xC03` + `0xC04` + {nbsp} + `0xC1F` + `0xC80` + `0xC81` + `0xC82` + `0xC83` + `0xC84` + {nbsp} + `0xC9F` |URO + URO + URO + URO + URO + {nbsp} + URO + URO + URO + URO + URO + URO + {nbsp} + URO |`cycle` + `time` + `instret` + `hpmcounter3` + `hpmcounter4` + {vertical-ellipsis} + `hpmcounter31` + `cycleh` + `timeh` + `instreth` + `hpmcounter3h` + `hpmcounter4h` + {vertical-ellipsis} + `hpmcounter31h` |Cycle counter for RDCYCLE instruction. + Timer for RDTIME instruction. + Instructions-retired counter for RDINSTRET instruction. + Performance-monitoring counter. + Performance-monitoring counter. + {nbsp} + Performance-monitoring counter. + Upper 32 bits of `cycle`, RV32 only. + Upper 32 bits of `time`, RV32 only. + Upper 32 bits of `instret`, RV32 only. + Upper 32 bits of `hpmcounter3`, RV32 only. + Upper 32 bits of `hpmcounter4`, RV32 only. + {nbsp} + Upper 32 bits of `hpmcounter31`, RV32 only. |", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V unprivileged CSR addresses", + "line_range": [ + 186, + 242 + ] + }, + { + "text": ".Currently allocated RISC-V supervisor-level CSR addresses. | |Number |Privilege |Name |Description 4+^|Supervisor Trap Setup", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V supervisor-level CSR addresses", + "line_range": [ + 248, + 253 + ] + }, + { + "text": "|`0x100` + `0x104` + `0x105` + `0x106` |SRW + SRW + SRW + SRW |`sstatus` + `sie` + `stvec` + `scounteren` |Supervisor status register. + Supervisor interrupt-enable register. + Supervisor trap handler base address. + Supervisor counter enable.", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V supervisor-level CSR addresses", + "line_range": [ + 255, + 270 + ] + }, + { + "text": "4+^|Supervisor Configuration", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V supervisor-level CSR addresses", + "line_range": [ + 272, + 272 + ] + }, + { + "text": "|`0x10A` |SRW |`senvcfg` |Supervisor environment configuration register.", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V supervisor-level CSR addresses", + "line_range": [ + 274, + 274 + ] + }, + { + "text": "4+^|Supervisor Counter Setup", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V supervisor-level CSR addresses", + "line_range": [ + 276, + 276 + ] + }, + { + "text": "|`0x120` |SRW |`scountinhibit` |Supervisor counter-inhibit register.", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V supervisor-level CSR addresses", + "line_range": [ + 278, + 278 + ] + }, + { + "text": "4+^|Supervisor Trap Handling", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V supervisor-level CSR addresses", + "line_range": [ + 280, + 280 + ] + }, + { + "text": "|`0x140` + `0x141` + `0x142` + `0x143` + `0x144` + `0xDA0` |SRW + SRW + SRW + SRW + SRW + SRO |`sscratch` + `sepc` + `scause` + `stval` + `sip` + `scountovf` |Supervisor scratch register. + Supervisor exception program counter. + Supervisor trap cause. + Supervisor trap value. + Supervisor interrupt pending. + Supervisor count overflow.", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V supervisor-level CSR addresses", + "line_range": [ + 282, + 305 + ] + }, + { + "text": "|`0x150` + `0x151` + `0x152` + `0x153` + `0x155` + `0x156` + `0x157` |SRW + SRW + SRW + SRW + SRW + SRW + SRW |`siselect` + `sireg` + `sireg2` + `sireg3` + `sireg4` + `sireg5` + `sireg6` |Supervisor indirect register select. + Supervisor indirect register alias. + Supervisor indirect register alias 2. + Supervisor indirect register alias 3. + Supervisor indirect register alias 4. + Supervisor indirect register alias 5. + Supervisor indirect register alias 6.", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V supervisor-level CSR addresses", + "line_range": [ + 309, + 336 + ] + }, + { + "text": "4+^|Supervisor Protection and Translation", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V supervisor-level CSR addresses", + "line_range": [ + 338, + 338 + ] + }, + { + "text": "|`0x180` |SRW |`satp` |Supervisor address translation and protection.", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V supervisor-level CSR addresses", + "line_range": [ + 340, + 340 + ] + }, + { + "text": "4+^|Supervisor Timer Compare", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V supervisor-level CSR addresses", + "line_range": [ + 342, + 342 + ] + }, + { + "text": "|`0x14D` + `0x15D` |SRW + SRW |`stimecmp` + `stimecmph` |Supervisor timer compare. + Upper 32 bits of `stimecmp`, RV32 only.", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V supervisor-level CSR addresses", + "line_range": [ + 344, + 351 + ] + }, + { + "text": "|`0x5A8` |SRW |`scontext` |Supervisor-mode context register.", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V supervisor-level CSR addresses", + "line_range": [ + 355, + 355 + ] + }, + { + "text": "4+^|Supervisor Resource Management Configuration |`0x181` |SRW |`srmcfg` |Supervisor Resource Management Configuration.", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V supervisor-level CSR addresses", + "line_range": [ + 357, + 358 + ] + }, + { + "text": "4+^|Supervisor State Enable Registers |`0x10C` + `0x10D` + `0x10E` + `0x10F` |SRW + SRW + SRW + SRW |`sstateen0` + `sstateen1` + `sstateen2` + `sstateen3` |Supervisor State Enable 0 Register. + Supervisor State Enable 1 Register. + Supervisor State Enable 2 Register. + Supervisor State Enable 3 Register.", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V supervisor-level CSR addresses", + "line_range": [ + 360, + 376 + ] + }, + { + "text": "4+^|Supervisor Control Transfer Records Configuration |`0x14E` + `0x14F` + `0x15F` |SRW + SRW + SRW |`sctrctl` + `sctrstatus` + `sctrdepth` |Supervisor Control Transfer Records Control Register. + Supervisor Control Transfer Records Status Register. + Supervisor Control Transfer Records Depth Register.", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V supervisor-level CSR addresses", + "line_range": [ + 378, + 390 + ] + }, + { + "text": ".Currently allocated RISC-V hypervisor and VS CSR addresses. | |Number |Privilege |Name |Description 4+^|Hypervisor Trap Setup", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V hypervisor and VS CSR addresses", + "line_range": [ + 398, + 403 + ] + }, + { + "text": "|`0x600` + `0x602` + `0x603` + `0x604` + `0x606` + `0x607` + `0x612` |HRW + HRW + HRW + HRW + HRW + HRW + HRW |`hstatus` + `hedeleg` + `hideleg` + `hie` + `hcounteren` + `hgeie` + `hedelegh` |Hypervisor status register. + Hypervisor exception delegation register. + Hypervisor interrupt delegation register. + Hypervisor interrupt-enable register. + Hypervisor counter enable. + Hypervisor guest external interrupt-enable register. + Upper 32 bits of `hedeleg`, RV32 only.", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V hypervisor and VS CSR addresses", + "line_range": [ + 405, + 432 + ] + }, + { + "text": "4+^|Hypervisor Trap Handling", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V hypervisor and VS CSR addresses", + "line_range": [ + 434, + 434 + ] + }, + { + "text": "|`0x643` + `0x644` + `0x645` + `0x64A` + `0xE12` |HRW + HRW + HRW + HRW + HRO |`htval` + `hip` + `hvip` + `htinst` + `hgeip` |Hypervisor trap value. + Hypervisor interrupt pending. + Hypervisor virtual interrupt pending. + Hypervisor trap instruction (transformed). + Hypervisor guest external interrupt pending.", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V hypervisor and VS CSR addresses", + "line_range": [ + 436, + 455 + ] + }, + { + "text": "4+^|Hypervisor Configuration", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V hypervisor and VS CSR addresses", + "line_range": [ + 457, + 457 + ] + }, + { + "text": "|`0x60A` + `0x61A` |HRW + HRW |`henvcfg` + `henvcfgh` |Hypervisor environment configuration register. + Upper 32 bits of `henvcfg`, RV32 only.", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V hypervisor and VS CSR addresses", + "line_range": [ + 459, + 466 + ] + }, + { + "text": "4+^|Hypervisor Protection and Translation", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V hypervisor and VS CSR addresses", + "line_range": [ + 468, + 468 + ] + }, + { + "text": "|`0x680` |HRW |`hgatp` |Hypervisor guest address translation and protection.", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V hypervisor and VS CSR addresses", + "line_range": [ + 470, + 470 + ] + }, + { + "text": "|`0x6A8` |HRW |`hcontext` |Hypervisor-mode context register.", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V hypervisor and VS CSR addresses", + "line_range": [ + 474, + 474 + ] + }, + { + "text": "4+^|Hypervisor Counter/Timer Virtualization Registers", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V hypervisor and VS CSR addresses", + "line_range": [ + 476, + 476 + ] + }, + { + "text": "|`0x605` + `0x615` |HRW + HRW |`htimedelta` + `htimedeltah` |Delta for VS/VU-mode timer. + Upper 32 bits of `htimedelta`, RV32 only.", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V hypervisor and VS CSR addresses", + "line_range": [ + 478, + 485 + ] + }, + { + "text": "4+^|Hypervisor State Enable Registers |`0x60C` + `0x60D` + `0x60E` + `0x60F` + `0x61C` + `0x61D` + `0x61E` + `0x61F` |HRW + HRW + HRW + HRW + HRW + HRW + HRW + HRW |`hstateen0` + `hstateen1` + `hstateen2` + `hstateen3` + `hstateen0h` + `hstateen1h` + `hstateen2h` + `hstateen3h` |Hypervisor State Enable 0 Register. + Hypervisor State Enable 1 Register. + Hypervisor State Enable 2 Register. + Hypervisor State Enable 3 Register. + Upper 32 bits of Hypervisor State Enable 0 Register, RV32 only. + Upper 32 bits of Hypervisor State Enable 1 Register, RV32 only. + Upper 32 bits of Hypervisor State Enable 2 Register, RV32 only. + Upper 32 bits of Hypervisor State Enable 3 Register, RV32 only.", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V hypervisor and VS CSR addresses", + "line_range": [ + 487, + 519 + ] + }, + { + "text": "4+^|Virtual Supervisor Registers", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V hypervisor and VS CSR addresses", + "line_range": [ + 521, + 521 + ] + }, + { + "text": "|`0x200` + `0x204` + `0x205` + `0x240` + `0x241` + `0x242` + `0x243` + `0x244` + `0x280` |HRW + HRW + HRW + HRW + HRW + HRW + HRW + HRW + HRW |`vsstatus` + `vsie` + `vstvec` + `vsscratch` + `vsepc` + `vscause` + `vstval` + `vsip` + `vsatp` |Virtual supervisor status register. + Virtual supervisor interrupt-enable register. + Virtual supervisor trap handler base address. + Virtual supervisor scratch register. + Virtual supervisor exception program counter. + Virtual supervisor trap cause. + Virtual supervisor trap value. + Virtual supervisor interrupt pending. + Virtual supervisor address translation and protection.", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V hypervisor and VS CSR addresses", + "line_range": [ + 523, + 558 + ] + }, + { + "text": "4+^|Virtual Supervisor Indirect", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V hypervisor and VS CSR addresses", + "line_range": [ + 560, + 560 + ] + }, + { + "text": "|`0x250` + `0x251` + `0x252` + `0x253` + `0x255` + `0x256` + `0x257` |HRW + HRW + HRW + HRW + HRW + HRW + HRW |`vsiselect` + `vsireg` + `vsireg2` + `vsireg3` + `vsireg4` + `vsireg5` + `vsireg6` |Virtual supervisor indirect register select. + Virtual supervisor indirect register alias. + Virtual supervisor indirect register alias 2. + Virtual supervisor indirect register alias 3. + Virtual supervisor indirect register alias 4. + Virtual supervisor indirect register alias 5. + Virtual supervisor indirect register alias 6.", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V hypervisor and VS CSR addresses", + "line_range": [ + 562, + 589 + ] + }, + { + "text": "4+^|Virtual Supervisor Timer Compare", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V hypervisor and VS CSR addresses", + "line_range": [ + 591, + 591 + ] + }, + { + "text": "|`0x24D` + `0x25D` |HRW + HRW |`vstimecmp` + `vstimecmph` |Virtual supervisor timer compare. + Upper 32 bits of `vstimecmp`, RV32 only.", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V hypervisor and VS CSR addresses", + "line_range": [ + 593, + 600 + ] + }, + { + "text": "4+^|Virtual Supervisor Control Transfer Records Configuration |`0x24E` |HRW |`vsctrctl` |Virtual Supervisor Control Transfer Records Control Register.", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V hypervisor and VS CSR addresses", + "line_range": [ + 602, + 606 + ] + }, + { + "text": "[.monocell] .Currently allocated RISC-V machine-level CSR addresses. | |Number |Privilege |Name |Description 4+^|Machine Information Registers", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V machine-level CSR addresses", + "line_range": [ + 614, + 620 + ] + }, + { + "text": "|`0xF11` + `0xF12` + `0xF13` + `0xF14` + `0xF15` |MRO + MRO + MRO + MRO + MRO |`mvendorid` + `marchid` + `mimpid` + `mhartid` + `mconfigptr` |Vendor ID. + Architecture ID. + Implementation ID. + Hardware thread ID. + Pointer to configuration data structure.", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V machine-level CSR addresses", + "line_range": [ + 622, + 641 + ] + }, + { + "text": "|`0x300` + `0x301` + `0x302` + `0x303` + `0x304` + `0x305` + `0x306` + `0x310` + `0x312` |MRW + MRW + MRW + MRW + MRW + MRW + MRW + MRW + MRW |`mstatus` + `misa` + `medeleg` + `mideleg` + `mie` + `mtvec` + `mcounteren` + `mstatush` + `medelegh` |Machine status register. + ISA and extensions + Machine exception delegation register. + Machine interrupt delegation register. + Machine interrupt-enable register. + Machine trap-handler base address. + Machine counter enable. + Additional machine status register, RV32 only. + Upper 32 bits of `medeleg`, RV32 only.", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V machine-level CSR addresses", + "line_range": [ + 645, + 680 + ] + }, + { + "text": "|`0x340` + `0x341` + `0x342` + `0x343` + `0x344` + `0x34A` + `0x34B` |MRW + MRW + MRW + MRW + MRW + MRW + MRW |`mscratch` + `mepc` + `mcause` + `mtval` + `mip` + `mtinst` + `mtval2` |Machine scratch register. + Machine exception program counter. + Machine trap cause. + Machine trap value. + Machine interrupt pending. + Machine trap instruction (transformed). + Machine second trap value.", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V machine-level CSR addresses", + "line_range": [ + 684, + 711 + ] + }, + { + "text": "|`0x350` + `0x351` + `0x352` + `0x353` + `0x355` + `0x356` + `0x357` |MRW + MRW + MRW + MRW + MRW + MRW + MRW |`miselect` + `mireg` + `mireg2` + `mireg3` + `mireg4` + `mireg5` + `mireg6` |Machine indirect register select. + Machine indirect register alias. + Machine indirect register alias 2. + Machine indirect register alias 3. + Machine indirect register alias 4. + Machine indirect register alias 5. + Machine indirect register alias 6.", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V machine-level CSR addresses", + "line_range": [ + 715, + 742 + ] + }, + { + "text": "|`0x30A` + `0x31A` + `0x747` + `0x757` |MRW + MRW + MRW + MRW |`menvcfg` + `menvcfgh` + `mseccfg` + `mseccfgh` |Machine environment configuration register. + Upper 32 bits of `menvcfg`, RV32 only. + Machine security configuration register. + Upper 32 bits of `mseccfg`, RV32 only.", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V machine-level CSR addresses", + "line_range": [ + 746, + 761 + ] + }, + { + "text": "4+^|Machine Memory Protection", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V machine-level CSR addresses", + "line_range": [ + 763, + 763 + ] + }, + { + "text": "|`0x3A0` + `0x3A1` + `0x3A2` + `0x3A3` + {nbsp} + `0x3AE` + `0x3AF` + `0x3B0` + `0x3B1` + {nbsp} + `0x3EF` |MRW + MRW + MRW + MRW + {nbsp} + MRW + MRW + MRW + MRW + {nbsp} + MRW |`pmpcfg0` + `pmpcfg1` + `pmpcfg2` + `pmpcfg3` + {ellipsis} + `pmpcfg14` + `pmpcfg15` + `pmpaddr0` + `pmpaddr1` + {ellipsis} + `pmpaddr63` |Physical memory protection configuration. + Physical memory protection configuration, RV32 only. + Physical memory protection configuration. + Physical memory protection configuration, RV32 only. + {nbsp} + Physical memory protection configuration. + Physical memory protection configuration, RV32 only. + Physical memory protection address register. + Physical memory protection address register. + {nbsp} + Physical memory protection address register.", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V machine-level CSR addresses", + "line_range": [ + 765, + 808 + ] + }, + { + "text": "4+^|Machine State Enable Registers |`0x30C` + `0x30D` + `0x30E` + `0x30F` + `0x31C` + `0x31D` + `0x31E` + `0x31F` |MRW + MRW + MRW + MRW + MRW + MRW + MRW + MRW |`mstateen0` + `mstateen1` + `mstateen2` + `mstateen3` + `mstateen0h` + `mstateen1h` + `mstateen2h` + `mstateen3h` |Machine State Enable 0 Register. + Machine State Enable 1 Register. + Machine State Enable 2 Register. + Machine State Enable 3 Register. + Upper 32 bits of Machine State Enable 0 Register, RV32 only. + Upper 32 bits of Machine State Enable 1 Register, RV32 only. + Upper 32 bits of Machine State Enable 2 Register, RV32 only. + Upper 32 bits of Machine State Enable 3 Register, RV32 only.", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V machine-level CSR addresses", + "line_range": [ + 810, + 842 + ] + }, + { + "text": "4+^|Machine Non-Maskable Interrupt Handling", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V machine-level CSR addresses", + "line_range": [ + 844, + 844 + ] + }, + { + "text": "|`0x740` + `0x741` + `0x742` + `0x744` |MRW + MRW + MRW + MRW |`mnscratch` + `mnepc` + `mncause` + `mnstatus` |Resumable NMI scratch register. + Resumable NMI program counter. + Resumable NMI cause. + Resumable NMI status.", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V machine-level CSR addresses", + "line_range": [ + 846, + 861 + ] + }, + { + "text": "4+^|Machine Counter/Timers", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V machine-level CSR addresses", + "line_range": [ + 863, + 863 + ] + }, + { + "text": "|`0xB00` + `0xB02` + `0xB03` + `0xB04` + {nbsp} + `0xB1F` + `0xB80` + `0xB82` + `0xB83` + `0xB84` + {nbsp} + `0xB9F` |MRW + MRW + MRW + MRW + {nbsp} + MRW + MRW + MRW + MRW + MRW + {nbsp} + MRW + |`mcycle` + `minstret` + `mhpmcounter3` + `mhpmcounter4` + {vertical-ellipsis} + `mhpmcounter31` + `mcycleh` + `minstreth` + `mhpmcounter3h` + `mhpmcounter4h` + {vertical-ellipsis} + `mhpmcounter31h` |Machine cycle counter. + Machine instructions-retired counter. + Machine performance-monitoring counter. + Machine performance-monitoring counter. + {nbsp} + Machine performance-monitoring counter. + Upper 32 bits of `mcycle`, RV32 only. + Upper 32 bits of `minstret`, RV32 only. + Upper 32 bits of `mhpmcounter3`, RV32 only. + Upper 32 bits of `mhpmcounter4`, RV32 only. + {nbsp} + Upper 32 bits of `mhpmcounter31`, RV32 only.", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V machine-level CSR addresses", + "line_range": [ + 865, + 912 + ] + }, + { + "text": "|`0x320` + `0x321` + `0x322` + `0x323` + `0x324` + {nbsp} + `0x33F` + `0x721` + `0x722` + `0x723` + `0x724` + {nbsp} + `0x73F` |MRW + MRW + MRW + MRW + MRW + {nbsp} + MRW + MRW + MRW + MRW + MRW + {nbsp} + MRW |`mcountinhibit` + `mcyclecfg` + `minstretcfg` + `mhpmevent3` + `mhpmevent4` + {vertical-ellipsis} + `mhpmevent31` + `mcyclecfgh` + `minstretcfgh` + `mhpmevent3h` + `mhpmevent4h` + {vertical-ellipsis} + `mhpmevent31h` |Machine counter-inhibit register. + Machine cycle counter configuration register. + Machine instret counter configuration register. + Machine performance-monitoring event selector. + Machine performance-monitoring event selector. + {nbsp} + Machine performance-monitoring event selector. + Upper 32 bits of `mcyclecfg`, RV32 only. + Upper 32 bits of `minstretcfg`, RV32 only. + Upper 32 bits of `mhpmevent3`, RV32 only. + Upper 32 bits of `mhpmevent4`, RV32 only. + {nbsp} + Upper 32 bits of `mhpmevent31`, RV32 only.", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V machine-level CSR addresses", + "line_range": [ + 916, + 967 + ] + }, + { + "text": "4+^|Machine Control Transfer Records Configuration |`0x34E` |MRW |`mctrctl` |Machine Control Transfer Records Control Register.", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V machine-level CSR addresses", + "line_range": [ + 969, + 973 + ] + }, + { + "text": "4+^|Debug/Trace Registers (shared with Debug Mode)", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V machine-level CSR addresses", + "line_range": [ + 975, + 975 + ] + }, + { + "text": "|`0x7A0` + `0x7A1` + `0x7A2` + `0x7A3` + `0x7A4` + `0x7A5` + `0x7A8` |MRW + MRW + MRW + MRW + MRW + MRW + MRW |`tselect` + `tdata1` + `tdata2` + `tdata3` + `tinfo` + `tcontrol` + `mcontext`", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V machine-level CSR addresses", + "line_range": [ + 977, + 997 + ] + }, + { + "text": "|Debug/Trace trigger register select. + First Debug/Trace trigger data register. + Second Debug/Trace trigger data register. + Third Debug/Trace trigger data register. + Trigger info register. + Trigger control register. + Machine-mode context register.", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V machine-level CSR addresses", + "line_range": [ + 999, + 1005 + ] + }, + { + "text": "|`0x7B0` + `0x7B1` + `0x7B2` + `0x7B3` |DRW + DRW + DRW + DRW + |`dcsr` + `dpc` + `dscratch0` + `dscratch1` |Debug control and status register. + Debug program counter. + Debug scratch register 0. + Debug scratch register 1. |", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V machine-level CSR addresses", + "line_range": [ + 1009, + 1025 + ] + }, + { + "text": ".Currently allocated RISC-V indirect CSR (Smcsrind) mappings - M-mode [float=\"center\",align=\"center\",options=\"header\"] | | `miselect` | `mireg` | `mireg2` | `mireg3` | `mireg4` | `mireg5` | `mireg6` | 0x30 | `iprio0` | none | none | none | none | none | ... | ... | ... | ... | ... | ... | ... | 0x3F | `iprio15` | none | none | none | none | none | 0x70 | `eidelivery` | none | none | none | none | none | 0x71 | 0 | none | none | none | none | none | 0x72 | `eithreshold` | none | none | none | none | none | 0x73 | 0 | none | none | none | none | none | ... | ... | ... | ... | ... | ... | ... | 0x7F | 0 | none | none | none | none | none | 0x80 | `eip0` | none | none | none | none | none | ... | ... | ... | ... | ... | ... | ... | 0xBF | `eip63` | none | none | none | none | none | 0xC0 | `eie0` | none | none | none | none | none | ... | ... | ... | ... | ... | ... | ... | 0xFF | `eie63` | none | none | none | none | none |", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V indirect CSR (Smcsrind) mappings", + "line_range": [ + 1031, + 1051 + ] + }, + { + "text": ".Currently allocated RISC-V indirect CSR (Smcsrind/Sscsrind) mappings - S-mode [float=\"center\",align=\"center\",options=\"header\"] | | `siselect` | `sireg` | `sireg2` | `sireg3` | `sireg4` | `sireg5` | `sireg6` | 0x30 | `iprio0` | none | none | none | none | none | ... | ... | ... | ... | ... | ... | ... | 0x3F | `iprio15` | none | none | none | none | none | 0x40 | `cycle` | `cyclecfg` | none | `cycleh` | `cyclecfgh` | none | 0x41 | none | none | none | none | none | none | 0x42 | `instret` | `instretcfg` | none | `instreth` | `instretcfgh` | none | 0x43 | `hpmcounter3` | `hpmevent3` | none | `hpmcounter3h` | `hpmevent3h` | none | ... | ... | ... | ... | ... | ... | ... | 0x5F | `hpmcounter31` | `hpmevent31` | none | `hpmcounter31h` | `hpmevent31h` | none | 0x70 | `eidelivery` | none | none | none | none | none | 0x71 | 0 | none | none | none | none | none | 0x72 | `eithreshold` | none | none | none | none | none | 0x73 | 0 | none | none | none | none | none | ... | ... | ... | ... | ... | ... | ... | 0x7F | 0 | none | none | none | none | none | 0x80 | `eip0` | none | none | none | none | none | ... | ... | ... | ... | ... | ... | ... | 0xBF | `eip63` | none | none | none | none | none | 0xC0 | `eie0` | none | none | none | none | none | ... | ... | ... | ... | ... | ... | ... | 0xFF | `eie63` | none | none | none | none | none | 0x200 | `ctrsource0` | `ctrtarget0` | `ctrdata0` | 0 | 0 | 0 | ... | ... | ... | ... | ... | ... | ... | 0x2FF | `ctrsource255` | `ctrtarget255` | `ctrdata255` | 0 | 0 | 0 |", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V indirect CSR (Smcsrind) mappings", + "line_range": [ + 1053, + 1082 + ] + }, + { + "text": ".Currently allocated RISC-V indirect CSR (Smcsrind/Sscsrind) mappings - VS-mode [float=\"center\",align=\"center\",options=\"header\"] | | `vsiselect` | `vsireg` | `vsireg2` | `vsireg3` | `vsireg4` | `vsireg5` | `vsireg6` | 0x30 | `iprio0` | none | none | none | none | none | ... | ... | ... | ... | ... | ... | ... | 0x3F | `iprio15` | none | none | none | none | none | 0x70 | `eidelivery` | none | none | none | none | none | 0x71 | 0 | none | none | none | none | none | 0x72 | `eithreshold` | none | none | none | none | none | 0x73 | 0 | none | none | none | none | none | ... | ... | ... | ... | ... | ... | ... | 0x7F | 0 | none | none | none | none | none | 0x80 | `eip0` | none | none | none | none | none | ... | ... | ... | ... | ... | ... | ... | 0xBF | `eip63` | none | none | none | none | none | 0xC0 | `eie0` | none | none | none | none | none | ... | ... | ... | ... | ... | ... | ... | 0xFF | `eie63` | none | none | none | none | none | 0x200 | `ctrsource0` | `ctrtarget0` | `ctrdata0` | 0 | 0 | 0 | ... | ... | ... | ... | ... | ... | ... | 0x2FF | `ctrsource255` | `ctrtarget255` | `ctrdata255` | 0 | 0 | 0 |", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Listing > Currently allocated RISC-V indirect CSR (Smcsrind) mappings", + "line_range": [ + 1084, + 1107 + ] + }, + { + "text": "The following definitions and abbreviations are used in specifying the behavior of fields within the CSRs.", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Field Specifications", + "line_range": [ + 1111, + 1112 + ] + }, + { + "text": "Some whole read/write fields are reserved for future use.", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Field Specifications > Reserved Writes Preserve Values, Reads Ignore Values (WPRI)", + "line_range": [ + 1116, + 1121 + ] + }, + { + "text": "Software should ignore the values read from these fields, and should preserve the values held in these fields when writing values to other fields of the same register.", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Field Specifications > Reserved Writes Preserve Values, Reads Ignore Values (WPRI)", + "line_range": [ + 1116, + 1121 + ] + }, + { + "text": "For forward compatibility, implementations that do not furnish these fields must make them read-only zero.", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Field Specifications > Reserved Writes Preserve Values, Reads Ignore Values (WPRI)", + "line_range": [ + 1116, + 1121 + ] + }, + { + "text": "These fields are labeled *WPRI* in the register descriptions.", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Field Specifications > Reserved Writes Preserve Values, Reads Ignore Values (WPRI)", + "line_range": [ + 1116, + 1121 + ] + }, + { + "text": "Some read/write CSR fields specify behavior for only a subset of possible bit encodings, with other bit encodings reserved.", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Field Specifications > Write/Read Only Legal Values (WLRL)", + "line_range": [ + 1125, + 1132 + ] + }, + { + "text": "Software should not write anything other than legal values to such a field, and should not assume a read will return a legal value unless the last write was of a legal value, or the register has not been written since another operation (e.g., reset) set the register to a legal value.", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Field Specifications > Write/Read Only Legal Values (WLRL)", + "line_range": [ + 1125, + 1132 + ] + }, + { + "text": "These fields are labeled *WLRL* in the register descriptions.", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Field Specifications > Write/Read Only Legal Values (WLRL)", + "line_range": [ + 1125, + 1132 + ] + }, + { + "text": "Implementations are permitted but not required to raise an illegal-instruction exception if an instruction attempts to write a non-supported value to a *WLRL* field.", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Field Specifications > Write/Read Only Legal Values (WLRL)", + "line_range": [ + 1134, + 1140 + ] + }, + { + "text": "Implementations can return arbitrary bit patterns on the read of a *WLRL* field when the last write was of an illegal value, but the value returned should deterministically depend on the illegal written value and the value of the field prior to the write.", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Field Specifications > Write/Read Only Legal Values (WLRL)", + "line_range": [ + 1134, + 1140 + ] + }, + { + "text": "Some read/write CSR fields are only defined for a subset of bit encodings, but allow any value to be written while guaranteeing to return a legal value whenever read.", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Field Specifications > Write Any Values, Reads Legal Values (WARL)", + "line_range": [ + 1144, + 1149 + ] + }, + { + "text": "Assuming that writing the CSR has no other side effects, the range of supported values can be determined by attempting to write a desired setting then reading to see if the value was retained.", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Field Specifications > Write Any Values, Reads Legal Values (WARL)", + "line_range": [ + 1144, + 1149 + ] + }, + { + "text": "These fields are labeled *WARL* in the register descriptions.", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Field Specifications > Write Any Values, Reads Legal Values (WARL)", + "line_range": [ + 1144, + 1149 + ] + }, + { + "text": "Implementations will not raise an exception on writes of unsupported values to a *WARL* field.", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Field Specifications > Write Any Values, Reads Legal Values (WARL)", + "line_range": [ + 1151, + 1155 + ] + }, + { + "text": "Implementations can return any legal value on the read of a *WARL* field when the last write was of an illegal value, but the legal value returned should deterministically depend on the illegal written value and the architectural state of the hart.", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Field Specifications > Write Any Values, Reads Legal Values (WARL)", + "line_range": [ + 1151, + 1155 + ] + }, + { + "text": "If a write to one CSR changes the set of legal values allowed for a field of a second CSR, then unless specified otherwise, the second CSR's field immediately gets an `UNSPECIFIED` value from among its new legal values.", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Field Modulation", + "line_range": [ + 1160, + 1165 + ] + }, + { + "text": "This is true even if the field's value before the write remains legal after the write; the value of the field may be changed in consequence of the write to the controlling CSR.", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Field Modulation", + "line_range": [ + 1160, + 1165 + ] + }, + { + "text": "A change to the value of a CSR for this reason is not a write to the affected CSR and thus does not trigger any side effects specified for that CSR.", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Field Modulation", + "line_range": [ + 1167, + 1169 + ] + }, + { + "text": "Implementations sometimes perform implicit reads of CSRs. (For example, all S-mode instruction fetches implicitly read the `satp` CSR.)", + "section": "Preamble > Control and Status Registers (CSRs) > Implicit Reads of CSRs", + "line_range": [ + 1173, + 1178 + ] + }, + { + "text": "Unless otherwise specified, the value returned by an implicit read of a CSR is the same value that would have been returned by an explicit read of the CSR, using a CSR-access instruction in a sufficient privilege mode.", + "section": "Preamble > Control and Status Registers (CSRs) > Implicit Reads of CSRs", + "line_range": [ + 1173, + 1178 + ] + }, + { + "text": "If the width of a CSR is changed (for example, by changing SXLEN or UXLEN, as described in ), the values of the writable fields and bits of the new-width CSR are, unless specified otherwise, determined from the previous-width CSR as though by this algorithm:", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Width Modulation", + "line_range": [ + 1183, + 1187 + ] + }, + { + "text": "The value of the previous-width CSR is copied to a temporary register of the same width. .", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Width Modulation", + "line_range": [ + 1189, + 1200 + ] + }, + { + "text": "For the read-only bits of the previous-width CSR, the bits at the same positions in the temporary register are set to zeros. .", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Width Modulation", + "line_range": [ + 1189, + 1200 + ] + }, + { + "text": "The width of the temporary register is changed to the new width.", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Width Modulation", + "line_range": [ + 1189, + 1200 + ] + }, + { + "text": "If the new width W is narrower than the previous width, the least-significant W bits of the temporary register are retained and the more-significant bits are discarded.", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Width Modulation", + "line_range": [ + 1189, + 1200 + ] + }, + { + "text": "If the new width is wider than the previous width, the temporary register is zero-extended to the wider width. .", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Width Modulation", + "line_range": [ + 1189, + 1200 + ] + }, + { + "text": "Each writable field of the new-width CSR takes the value of the bits at the same positions in the temporary register.", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Width Modulation", + "line_range": [ + 1189, + 1200 + ] + }, + { + "text": "Changing the width of a CSR is not a read or write of the CSR and thus does not trigger any side effects.", + "section": "Preamble > Control and Status Registers (CSRs) > CSR Width Modulation", + "line_range": [ + 1202, + 1203 + ] + }, + { + "text": "If a standard CSR is wider than XLEN bits, then an explicit read of the CSR returns the register's least-significant XLEN bits, and an explicit write to the CSR modifies only the register's least-significant XLEN bits, leaving the upper bits unchanged.", + "section": "Preamble > Control and Status Registers (CSRs) > Explicit Accesses to CSRs Wider than XLEN", + "line_range": [ + 1207, + 1210 + ] + }, + { + "text": "Some standard CSRs, such as the counter CSRs of extension Zicntr, are always 64 bits, even when XLEN=32 (RV32).", + "section": "Preamble > Control and Status Registers (CSRs) > Explicit Accesses to CSRs Wider than XLEN", + "line_range": [ + 1212, + 1219 + ] + }, + { + "text": "For each such 64-bit CSR (for example, counter `time`), a corresponding 32-bit high-half CSR is usually defined with the same name but with the letter '`h`' appended at the end (`timeh`).", + "section": "Preamble > Control and Status Registers (CSRs) > Explicit Accesses to CSRs Wider than XLEN", + "line_range": [ + 1212, + 1219 + ] + }, + { + "text": "The high-half CSR aliases bits 63:32 of its namesake 64-bit CSR, thus providing a way for RV32 software to read and modify the otherwise-unreachable 32 bits.", + "section": "Preamble > Control and Status Registers (CSRs) > Explicit Accesses to CSRs Wider than XLEN", + "line_range": [ + 1212, + 1219 + ] + }, + { + "text": "Standard high-half CSRs are accessible only when the base RISC-V instruction set is RV32 (XLEN=32).", + "section": "Preamble > Control and Status Registers (CSRs) > Explicit Accesses to CSRs Wider than XLEN", + "line_range": [ + 1221, + 1225 + ] + }, + { + "text": "For RV64 (when XLEN=64), the addresses of all standard high-half CSRs are reserved, so an attempt to access a high-half CSR typically raises an illegal-instruction exception.", + "section": "Preamble > Control and Status Registers (CSRs) > Explicit Accesses to CSRs Wider than XLEN", + "line_range": [ + 1221, + 1225 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__priv__hypervisor.json b/tools/llm-extraction/data/output/raw_chunks/src__priv__hypervisor.json new file mode 100644 index 0000000000..4c0ec0b172 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__priv__hypervisor.json @@ -0,0 +1,4686 @@ +{ + "source_file": "src/priv/hypervisor.adoc", + "total": 585, + "sentences": [ + { + "text": "This chapter describes the RISC-V hypervisor extension, which virtualizes the supervisor-level architecture to support the efficient hosting of guest operating systems atop a type-1 or type-2 hypervisor.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0", + "line_range": [ + 3, + 16 + ] + }, + { + "text": "The hypervisor extension changes supervisor mode into hypervisor-extended supervisor mode (HS-mode, or hypervisor mode for short), where a hypervisor or a hosting-capable operating system runs.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0", + "line_range": [ + 3, + 16 + ] + }, + { + "text": "The hypervisor extension also adds another stage of address translation, from guest physical addresses to supervisor physical addresses, to virtualize the memory and memory-mapped I/O subsystems for a guest operating system. HS-mode acts the same as S-mode, but with additional instructions and CSRs that control the new stage of address translation and support hosting a guest OS in virtual S-mode (VS-mode).", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0", + "line_range": [ + 3, + 16 + ] + }, + { + "text": "Regular S-mode operating systems can execute without modification either in HS-mode or as VS-mode guests.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0", + "line_range": [ + 3, + 16 + ] + }, + { + "text": "In HS-mode, an OS or hypervisor interacts with the machine through the same SBI as an OS normally does from S-mode.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0", + "line_range": [ + 18, + 20 + ] + }, + { + "text": "An HS-mode hypervisor is expected to implement the SBI for its VS-mode guest.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0", + "line_range": [ + 18, + 20 + ] + }, + { + "text": "The hypervisor extension depends on an \"I\" base integer ISA with 32 `x` registers (RV32I or RV64I), not RV32E or RV64E, which have only 16 `x` registers. CSR `mtval` must not be read-only zero, and standard page-based address translation must be supported, either Sv32 for RV32, or a minimum of Sv39 for RV64.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0", + "line_range": [ + 22, + 27 + ] + }, + { + "text": "The hypervisor extension is enabled by setting bit 7 in the `misa` CSR, which corresponds to the letter H. RISC-V harts that implement the hypervisor extension are encouraged not to hardwire `misa`[7], so that the extension may be disabled.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0", + "line_range": [ + 29, + 32 + ] + }, + { + "text": "The current virtualization mode, denoted V, indicates whether the hart is currently executing in a guest.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Privilege Modes", + "line_range": [ + 36, + 43 + ] + }, + { + "text": "When V=1, the hart is either in virtual S-mode (VS-mode), or in virtual U-mode (VU-mode) atop a guest OS running in VS-mode.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Privilege Modes", + "line_range": [ + 36, + 43 + ] + }, + { + "text": "When V=0, the hart is either in M-mode, in HS-mode, or in U-mode atop an OS running in HS-mode.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Privilege Modes", + "line_range": [ + 36, + 43 + ] + }, + { + "text": "The virtualization mode also indicates whether two-stage address translation is active (V=1) or inactive (V=0). lists the possible privilege modes of a RISC-V hart with the hypervisor extension.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Privilege Modes", + "line_range": [ + 36, + 43 + ] + }, + { + "text": ".Privilege modes with the hypervisor extension. [float=\"center\",align=\"center\",cols=\"~,~,~,~,~\"] | ^|Virtualization + Mode (V) ^|Nominal Privilege |Abbreviation |Name |Two-Stage Translation", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Privilege Modes", + "line_range": [ + 47, + 52 + ] + }, + { + "text": "^|0 + 0 + 0 ^| U + S + M |U-mode + HS-mode + M-mode |User mode + Hypervisor-extended supervisor mode + Machine mode |Off + Off + Off ^|1 + 1 ^|U + S |VU-mode + VS-mode |Virtual user mode + Virtual supervisor mode |On + On |", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Privilege Modes", + "line_range": [ + 54, + 79 + ] + }, + { + "text": "For privilege modes U and VU, the nominal privilege mode is U, and for privilege modes HS and VS, the nominal privilege mode is S.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Privilege Modes", + "line_range": [ + 81, + 82 + ] + }, + { + "text": "HS-mode is more privileged than VS-mode, and VS-mode is more privileged than VU-mode. VS-mode interrupts are globally disabled when executing in U-mode.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Privilege Modes", + "line_range": [ + 84, + 86 + ] + }, + { + "text": "An OS or hypervisor running in HS-mode uses the supervisor CSRs to interact with the exception, interrupt, and address-translation subsystems.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs", + "line_range": [ + 90, + 96 + ] + }, + { + "text": "Additional CSRs are provided to HS-mode, but not to VS-mode, to manage two-stage address translation and to control the behavior of a VS-mode guest: `hstatus`, `hedeleg`, `hideleg`, `hvip`, `hip`, `hie`, `hgeip`, `hgeie`, `henvcfg`, `henvcfgh`, `hcounteren`, `htimedelta`, `htimedeltah`, `htval`, `htinst`, and `hgatp`.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs", + "line_range": [ + 90, + 96 + ] + }, + { + "text": "Furthermore, several virtual supervisor CSRs (VS CSRs) are replicas of the normal supervisor CSRs.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs", + "line_range": [ + 98, + 100 + ] + }, + { + "text": "For example, `vsstatus` is the VS CSR that duplicates the usual `sstatus` CSR.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs", + "line_range": [ + 98, + 100 + ] + }, + { + "text": "When V=1, the VS CSRs substitute for the corresponding supervisor CSRs, taking over all functions of the usual supervisor CSRs except as specified otherwise.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs", + "line_range": [ + 102, + 112 + ] + }, + { + "text": "Instructions that normally read or modify a supervisor CSR shall instead access the corresponding VS CSR.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs", + "line_range": [ + 102, + 112 + ] + }, + { + "text": "When V=1, an attempt to read or write a VS CSR directly by its own separate CSR address causes a virtual-instruction exception. (Attempts from U-mode cause an illegal-instruction exception as usual.) The VS CSRs can be accessed as themselves only from M-mode or HS-mode.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs", + "line_range": [ + 102, + 112 + ] + }, + { + "text": "While V=1, the normal HS-level supervisor CSRs that are replaced by VS CSRs retain their values but do not affect the behavior of the machine unless specifically documented to do so.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs", + "line_range": [ + 114, + 119 + ] + }, + { + "text": "Conversely, when V=0, the VS CSRs do not ordinarily affect the behavior of the machine other than being readable and writable by CSR instructions.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs", + "line_range": [ + 114, + 119 + ] + }, + { + "text": "Some standard supervisor CSRs (`senvcfg`, `scounteren`, and `scontext`, possibly others) have no matching VS CSR.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs", + "line_range": [ + 121, + 127 + ] + }, + { + "text": "These supervisor CSRs continue to have their usual function and accessibility even when V=1, except with VS-mode and VU-mode substituting for HS-mode and U-mode.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs", + "line_range": [ + 121, + 127 + ] + }, + { + "text": "Hypervisor software is expected to manually swap the contents of these registers as needed.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs", + "line_range": [ + 121, + 127 + ] + }, + { + "text": "In this chapter, we use the term HSXLEN to refer to the effective XLEN when executing in HS-mode, and VSXLEN to refer to the effective XLEN when executing in VS-mode.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs", + "line_range": [ + 129, + 131 + ] + }, + { + "text": "The `hstatus` register is an HSXLEN-bit read/write register formatted as shown in when HSXLEN=32 and when HSXLEN=64.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register", + "line_range": [ + 136, + 141 + ] + }, + { + "text": "The `hstatus` register provides facilities analogous to the `mstatus` register for tracking and controlling the exception behavior of a VS-mode guest.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register", + "line_range": [ + 136, + 141 + ] + }, + { + "text": ".Hypervisor status register (`hstatus`) when HSXLEN=32 [wavedrom,, svg] .... {reg: [ {bits: 5, name: 'WPRI'}, {bits: 1, name: 'VSBE'}, {bits: 1, name: 'GVA'}, {bits: 1, name: 'SPV'}, {bits: 1, name: 'SPVP'}, {bits: 1, name: 'HU'}, {bits: 2, name: 'WPRI'}, {bits: 6, name: 'VGEIN'}, {bits: 2, name: 'WPRI'}, {bits: 1, name: 'VTVM'}, {bits: 1, name: 'VTW'}, {bits: 1, name: 'VTSR'}, {bits: 9, name: 'WPRI'}, ], config:{lanes: 2, hspace:1024}} ....", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register", + "line_range": [ + 143, + 162 + ] + }, + { + "text": ".Hypervisor status register (`hstatus`) when HSXLEN=64. [wavedrom,, svg] .... {reg: [ {bits: 5, name: 'WPRI'}, {bits: 1, name: 'VSBE'}, {bits: 1, name: 'GVA'}, {bits: 1, name: 'SPV'}, {bits: 1, name: 'SPVP'}, {bits: 1, name: 'HU'}, {bits: 2, name: 'WPRI'}, {bits: 6, name: 'VGEIN'}, {bits: 2, name: 'WPRI'}, {bits: 1, name: 'VTVM'}, {bits: 1, name: 'VTW'}, {bits: 1, name: 'VTSR'}, {bits: 9, name: 'WPRI'}, {bits: 2, name: 'VSXL'}, {bits: 14, name: 'WPRI'}, {bits: 2, name: 'HUPMM'}, {bits: 14, name: 'WPRI'}, ], config:{lanes: 4, hspace:1024}} ....", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register", + "line_range": [ + 164, + 187 + ] + }, + { + "text": "The VSXL field controls the effective XLEN for VS-mode (known as VSXLEN), which may differ from the XLEN for HS-mode (HSXLEN).", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register", + "line_range": [ + 189, + 195 + ] + }, + { + "text": "When HSXLEN=32, the VSXL field does not exist, and VSXLEN=32.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register", + "line_range": [ + 189, + 195 + ] + }, + { + "text": "When HSXLEN=64, VSXL is a *WARL* field that is encoded the same as the MXL field of `misa`, shown in .", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register", + "line_range": [ + 189, + 195 + ] + }, + { + "text": "In particular, an implementation may make VSXL be a read-only field whose value always ensures that VSXLEN=HSXLEN.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register", + "line_range": [ + 189, + 195 + ] + }, + { + "text": "If HSXLEN is changed from 32 to a wider width, and if field VSXL is not restricted to a single value, it gets the value corresponding to the widest supported width not wider than the new HSXLEN.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register", + "line_range": [ + 197, + 200 + ] + }, + { + "text": "The `hstatus` fields VTSR, VTW, and VTVM are defined analogously to the `mstatus` fields TSR, TW, and TVM, but affect execution only in VS-mode, and cause virtual-instruction exceptions instead of illegal-instruction exceptions.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register", + "line_range": [ + 202, + 217 + ] + }, + { + "text": "When VTSR=1, an attempt in VS-mode to execute SRET raises a virtual-instruction exception.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register", + "line_range": [ + 202, + 217 + ] + }, + { + "text": "When VTW=1 (and assuming `mstatus`.TW=0), an attempt in VS-mode to execute WFI raises a virtual-instruction exception if the WFI does not complete within an implementation-specific, bounded time limit.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register", + "line_range": [ + 202, + 217 + ] + }, + { + "text": "An implementation may have WFI always raise a virtual-instruction exception in VS-mode when VTW=1 (and `mstatus`.TW=0), even if there are pending globally-disabled interrupts when the instruction is executed.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register", + "line_range": [ + 202, + 217 + ] + }, + { + "text": "When VTVM=1, an attempt in VS-mode to execute SFENCE.VMA or SINVAL.VMA or to access CSR `satp` raises a virtual-instruction exception.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register", + "line_range": [ + 202, + 217 + ] + }, + { + "text": "The VGEIN (Virtual Guest External Interrupt Number) field selects a guest external interrupt source for VS-level external interrupts. VGEIN is a *WLRL* field that must be able to hold values between zero and the maximum guest external interrupt number (known as GEILEN), inclusive.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register", + "line_range": [ + 219, + 228 + ] + }, + { + "text": "When VGEIN=0, no guest external interrupt source is selected for VS-level external interrupts. GEILEN may be zero, in which case VGEIN may be read-only zero.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register", + "line_range": [ + 219, + 228 + ] + }, + { + "text": "Guest external interrupts are explained in , and the use of VGEIN is covered further in .", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register", + "line_range": [ + 219, + 228 + ] + }, + { + "text": "Field HU (Hypervisor in U-mode) controls whether the virtual-machine load/store instructions, HLV, HLVX, and HSV, can be used also in U-mode.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register", + "line_range": [ + 230, + 235 + ] + }, + { + "text": "When HU=1, these instructions can be executed in U-mode the same as in HS-mode.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register", + "line_range": [ + 230, + 235 + ] + }, + { + "text": "When HU=0, all hypervisor instructions cause an illegal-instruction exception in U-mode.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register", + "line_range": [ + 230, + 235 + ] + }, + { + "text": "When Ssnpm extension is implemented, the `HUPMM` field enables or disables pointer masking (see ) for `HLV.\\*` and `HSV.*` instructions in U-mode, according to the values in , when their explicit memory access is performed as though in VU-mode.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register", + "line_range": [ + 237, + 246 + ] + }, + { + "text": "In HS- and M-modes, pointer masking for these instructions is enabled or disabled by `senvcfg.PMM`, when their explicit memory access is performed as though in VU-mode.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register", + "line_range": [ + 237, + 246 + ] + }, + { + "text": "Setting `henvcfg.PMM` enables or disables pointer masking for `HLV.\\*` and `HSV.*` when their explicit memory access is performed as though in VS-mode.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register", + "line_range": [ + 237, + 246 + ] + }, + { + "text": "When the Ssnpm extension is not implemented, the `HUPMM` field is read-only zero.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register", + "line_range": [ + 237, + 246 + ] + }, + { + "text": "The `HUPMM` field is read-only zero for RV32.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register", + "line_range": [ + 237, + 246 + ] + }, + { + "text": "The SPV bit (Supervisor Previous Virtualization mode) is written by the implementation whenever a trap is taken into HS-mode.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register", + "line_range": [ + 248, + 253 + ] + }, + { + "text": "Just as the SPP bit in `sstatus` is set to the (nominal) privilege mode at the time of the trap, the SPV bit in `hstatus` is set to the value of the virtualization mode V at the time of the trap.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register", + "line_range": [ + 248, + 253 + ] + }, + { + "text": "When an SRET instruction is executed when V=0, V is set to SPV.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register", + "line_range": [ + 248, + 253 + ] + }, + { + "text": "When V=1 and a trap is taken into HS-mode, bit SPVP (Supervisor Previous Virtual Privilege) is set to the nominal privilege mode at the time of the trap, the same as `sstatus`.SPP.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register", + "line_range": [ + 255, + 261 + ] + }, + { + "text": "But if V=0 before a trap, SPVP is left unchanged on trap entry. SPVP controls the effective privilege of explicit memory accesses made by the virtual-machine load/store instructions, HLV, HLVX, and HSV.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register", + "line_range": [ + 255, + 261 + ] + }, + { + "text": "Field GVA (Guest Virtual Address) is written by the implementation whenever a trap is taken into HS-mode.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register", + "line_range": [ + 263, + 268 + ] + }, + { + "text": "For any trap (breakpoint, address misaligned, access fault, page fault, or guest-page fault) that writes a guest virtual address to `stval`, GVA is set to 1.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register", + "line_range": [ + 263, + 268 + ] + }, + { + "text": "For any other trap into HS-mode, GVA is set to 0.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register", + "line_range": [ + 263, + 268 + ] + }, + { + "text": "The VSBE bit is a *WARL* field that controls the endianness of explicit memory accesses made from VS-mode.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register", + "line_range": [ + 270, + 277 + ] + }, + { + "text": "If VSBE=0, explicit load and store memory accesses made from VS-mode are little-endian, and if VSBE=1, they are big-endian. VSBE also controls the endianness of all implicit accesses to VS-level memory management data structures, such as page tables.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register", + "line_range": [ + 270, + 277 + ] + }, + { + "text": "An implementation may make VSBE a read-only field that always specifies the same endianness as HS-mode.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Status (`hstatus`) Register", + "line_range": [ + 270, + 277 + ] + }, + { + "text": "Register `hedeleg` is a 64-bit read/write register, formatted as shown in .", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Delegation (`hedeleg` and `hideleg`) Registers", + "line_range": [ + 281, + 289 + ] + }, + { + "text": "Register `hideleg` is an HSXLEN-bit read/write register, formatted as shown in .", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Delegation (`hedeleg` and `hideleg`) Registers", + "line_range": [ + 281, + 289 + ] + }, + { + "text": "By default, all traps at any privilege level are handled in M-mode, though M-mode usually uses the `medeleg` and `mideleg` CSRs to delegate some traps to HS-mode.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Delegation (`hedeleg` and `hideleg`) Registers", + "line_range": [ + 281, + 289 + ] + }, + { + "text": "The `hedeleg` and `hideleg` CSRs allow these traps to be further delegated to a VS-mode guest; their layout is the same as `medeleg` and `mideleg`.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Delegation (`hedeleg` and `hideleg`) Registers", + "line_range": [ + 281, + 289 + ] + }, + { + "text": ".Hypervisor exception delegation register (`hedeleg`). include::images/bytefield/hedelegreg.edn[]", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Delegation (`hedeleg` and `hideleg`) Registers", + "line_range": [ + 291, + 293 + ] + }, + { + "text": ".Hypervisor interrupt delegation register (`hideleg`). include::images/bytefield/hidelegreg.edn[]", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Delegation (`hedeleg` and `hideleg`) Registers", + "line_range": [ + 295, + 297 + ] + }, + { + "text": "A synchronous trap that has been delegated to HS-mode (using `medeleg`) is further delegated to VS-mode if V=1 before the trap and the corresponding `hedeleg` bit is set.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Delegation (`hedeleg` and `hideleg`) Registers", + "line_range": [ + 299, + 307 + ] + }, + { + "text": "Each bit of `hedeleg` shall be either writable or read-only zero.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Delegation (`hedeleg` and `hideleg`) Registers", + "line_range": [ + 299, + 307 + ] + }, + { + "text": "Many bits of `hedeleg` are required specifically to be writable or zero, as enumerated in .", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Delegation (`hedeleg` and `hideleg`) Registers", + "line_range": [ + 299, + 307 + ] + }, + { + "text": "Bit 0, corresponding to instruction address-misaligned exceptions, must be writable if IALIGN=32.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Delegation (`hedeleg` and `hideleg`) Registers", + "line_range": [ + 299, + 307 + ] + }, + { + "text": "When XLEN=32, `hedelegh` is a 32-bit read/write register that aliases bits 63:32 of `hedeleg`.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Delegation (`hedeleg` and `hideleg`) Registers", + "line_range": [ + 309, + 312 + ] + }, + { + "text": "Register `hedelegh` does not exist when XLEN=64.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Delegation (`hedeleg` and `hideleg`) Registers", + "line_range": [ + 309, + 312 + ] + }, + { + "text": "An interrupt that has been delegated to HS-mode (using `mideleg`) is further delegated to VS-mode if the corresponding `hideleg` bit is set.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Delegation (`hedeleg` and `hideleg`) Registers", + "line_range": [ + 314, + 318 + ] + }, + { + "text": "Among bits 15:0 of `hideleg`, bits 10, 6, and 2 (corresponding to the standard VS-level interrupts) are writable, and bits 12, 9, 5, and 1 (corresponding to the standard S-level interrupts) are read-only zeros.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Delegation (`hedeleg` and `hideleg`) Registers", + "line_range": [ + 314, + 318 + ] + }, + { + "text": "When a virtual supervisor external interrupt (code 10) is delegated to VS-mode, it is automatically translated by the machine into a supervisor external interrupt (code 9) for VS-mode, including the value written to `vscause` on an interrupt trap.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Delegation (`hedeleg` and `hideleg`) Registers", + "line_range": [ + 320, + 329 + ] + }, + { + "text": "Likewise, a virtual supervisor timer interrupt (6) is translated into a supervisor timer interrupt (5) for VS-mode, and a virtual supervisor software interrupt (2) is translated into a supervisor software interrupt (1) for VS-mode.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Delegation (`hedeleg` and `hideleg`) Registers", + "line_range": [ + 320, + 329 + ] + }, + { + "text": "Similar translations may or may not be done for platform interrupt causes (codes 16 and above).", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Delegation (`hedeleg` and `hideleg`) Registers", + "line_range": [ + 320, + 329 + ] + }, + { + "text": ".Bits of `hedeleg` that must be writable or must be read-only zero. | |Bit |Attribute |Corresponding Exception |0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 11 + 12 + 13 + 15 + 16 + 18 + 19 + 20 + 21 + 22 + 23 |(See text) + Writable + Writable + Writable + Writable + Writable + Writable + Writable + Writable + Read-only 0 + Read-only 0 + Read-only 0 + Writable + Writable + Writable + Read-only 0 + Writable + Writable + Read-only 0 + Read-only 0 + Read-only 0 + Read-only 0 |Instruction address misaligned + Instruction access fault + Illegal instruction + Breakpoint + Load address misaligned + Load access fault + Store/AMO address misaligned + Store/AMO access fault + Environment call from U-mode or VU-mode + Environment call from HS-mode + Environment call from VS-mode + Environment call from M-mode + Instruction page fault + Load page fault + Store/AMO page fault + Double trap + Software check + Hardware error + Instruction guest-page fault + Load guest-page fault + Virtual instruction + Store/AMO guest-page fault |", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Delegation (`hedeleg` and `hideleg`) Registers", + "line_range": [ + 331, + 402 + ] + }, + { + "text": "Register `hvip` is an HSXLEN-bit read/write register that a hypervisor can write to indicate virtual interrupts intended for VS-mode.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers", + "line_range": [ + 407, + 410 + ] + }, + { + "text": "Bits of `hvip` that are not writable are read-only zeros.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers", + "line_range": [ + 407, + 410 + ] + }, + { + "text": ".Hypervisor virtual-interrupt-pending register(`hvip`). include::images/bytefield/hvipreg.edn[]", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers", + "line_range": [ + 412, + 414 + ] + }, + { + "text": "The standard portion (bits 15:0) of `hvip` is formatted as shown in .", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers", + "line_range": [ + 416, + 421 + ] + }, + { + "text": "Bits VSEIP, VSTIP, and VSSIP of `hvip` are writable.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers", + "line_range": [ + 416, + 421 + ] + }, + { + "text": "Setting VSEIP=1 in `hvip` asserts a VS-level external interrupt; setting VSTIP asserts a VS-level timer interrupt; and setting VSSIP asserts a VS-level software interrupt.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers", + "line_range": [ + 416, + 421 + ] + }, + { + "text": ".Standard portion (bits 15:0) of `hvip`. include::images/bytefield/hvipreg-standard.edn[]", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers", + "line_range": [ + 423, + 425 + ] + }, + { + "text": "Registers `hip` and `hie` are HSXLEN-bit read/write registers that supplement HS-level’s `sip` and `sie` respectively.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers", + "line_range": [ + 427, + 430 + ] + }, + { + "text": "The `hip` register indicates pending VS-level and hypervisor-specific interrupts, while `hie` contains enable bits for the same interrupts.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers", + "line_range": [ + 427, + 430 + ] + }, + { + "text": ".Hypervisor interrupt-pending register (`hip`). include::images/bytefield/hipreg.edn[]", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers", + "line_range": [ + 432, + 434 + ] + }, + { + "text": ".Hypervisor interrupt-enable register (`hie`). include::images/bytefield/hiereg.edn[]", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers", + "line_range": [ + 436, + 438 + ] + }, + { + "text": "For each writable bit in `sie`, the corresponding bit shall be read-only zero in both `hip` and `hie`.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers", + "line_range": [ + 440, + 443 + ] + }, + { + "text": "Hence, the nonzero bits in `sie` and `hie` are always mutually exclusive, and likewise for `sip` and `hip`.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers", + "line_range": [ + 440, + 443 + ] + }, + { + "text": "An interrupt i will trap to HS-mode whenever all of the following are true: (a) either the current operating mode is HS-mode and the SIE bit in the `sstatus` register is set, or the current operating mode has less privilege than HS-mode; (b) bit i is set in both `sip` and `sie`, or in both `hip` and `hie`; and (c) bit i is not set in `hideleg`.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers", + "line_range": [ + 445, + 450 + ] + }, + { + "text": "If bit i of `sie` is read-only zero, the same bit in register `hip` may be writable or may be read-only.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers", + "line_range": [ + 452, + 460 + ] + }, + { + "text": "When bit i in `hip` is writable, a pending interrupt i can be cleared by writing 0 to this bit.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers", + "line_range": [ + 452, + 460 + ] + }, + { + "text": "If interrupt i can become pending in `hip` but bit i in `hip` is read-only, then either the interrupt can be cleared by clearing bit i of `hvip`, or the implementation must provide some other mechanism for clearing the pending interrupt (which may involve a call to the execution environment).", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers", + "line_range": [ + 452, + 460 + ] + }, + { + "text": "A bit in `hie` shall be writable if the corresponding interrupt can ever become pending in `hip`.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers", + "line_range": [ + 462, + 465 + ] + }, + { + "text": "Bits of `hie` that are not writable shall be read-only zero.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers", + "line_range": [ + 462, + 465 + ] + }, + { + "text": "The standard portions (bits 15:0) of registers `hip` and `hie` are formatted as shown in and respectively.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers", + "line_range": [ + 467, + 468 + ] + }, + { + "text": ".Standard portion (bits 15:0) of `hip`. include::images/bytefield/hipreg-standard.edn[]", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers", + "line_range": [ + 470, + 472 + ] + }, + { + "text": ".Standard portion (bits 15:0) of `hie`. include::images/bytefield/hiereg-standard.edn[]", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers", + "line_range": [ + 474, + 476 + ] + }, + { + "text": "Bits `hip`.SGEIP and `hie`.SGEIE are the interrupt-pending and interrupt-enable bits for guest external interrupts at supervisor level (HS-level). SGEIP is read-only in `hip`, and is 1 if and only if the bitwise logical-AND of CSRs `hgeip` and `hgeie` is nonzero in any bit. (See .)", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers", + "line_range": [ + 478, + 483 + ] + }, + { + "text": "Bits `hip`.VSEIP and `hie`.VSEIE are the interrupt-pending and interrupt-enable bits for VS-level external interrupts. VSEIP is read-only in `hip`, and is the logical-OR of these interrupt sources:", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers", + "line_range": [ + 485, + 488 + ] + }, + { + "text": "bit VSEIP of `hvip`; * the bit of `hgeip` selected by `hstatus`.VGEIN; and * any other platform-specific external interrupt signal directed to VS-level.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers", + "line_range": [ + 490, + 493 + ] + }, + { + "text": "Bits `hip`.VSTIP and `hie`.VSTIE are the interrupt-pending and interrupt-enable bits for VS-level timer interrupts. VSTIP is read-only in `hip`, and is the logical-OR of `hvip`.VSTIP and, when the Sstc extension is implemented, the timer interrupt signal resulting from `vstimecmp`.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers", + "line_range": [ + 495, + 503 + ] + }, + { + "text": "The `hip`.VSTIP bit, in response to timer interrupts generated by `vstimecmp`, is set by writing `vstimecmp` with a value that is less than or equal to the sum of `time` and `htimedelta`, truncated to 64 bits; it is cleared by writing `vstimecmp` with a greater value.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers", + "line_range": [ + 495, + 503 + ] + }, + { + "text": "The `hip`.VSTIP bit remains defined while V=0 as well as V=1.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers", + "line_range": [ + 495, + 503 + ] + }, + { + "text": "Bits `hip`.VSSIP and `hie`.VSSIE are the interrupt-pending and interrupt-enable bits for VS-level software interrupts. VSSIP in `hip` is an alias (writable) of the same bit in `hvip`.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers", + "line_range": [ + 505, + 508 + ] + }, + { + "text": "Multiple simultaneous interrupts destined for HS-mode are handled in the following decreasing priority order: SEI, SSI, STI, SGEI, VSEI, VSSI, VSTI, LCOFI.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Interrupt (`hvip`, `hip`, and `hie`) Registers", + "line_range": [ + 510, + 513 + ] + }, + { + "text": "The `hgeip` register is an HSXLEN-bit read-only register, formatted as shown in , that indicates pending guest external interrupts for this hart.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest External Interrupt Registers (`hgeip` and `hgeie`)", + "line_range": [ + 518, + 525 + ] + }, + { + "text": "The `hgeie` register is an HSXLEN-bit read/write register, formatted as shown in , that contains enable bits for the guest external interrupts at this hart.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest External Interrupt Registers (`hgeip` and `hgeie`)", + "line_range": [ + 518, + 525 + ] + }, + { + "text": "Guest external interrupt number i corresponds with bit i in both `hgeip` and `hgeie`.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest External Interrupt Registers (`hgeip` and `hgeie`)", + "line_range": [ + 518, + 525 + ] + }, + { + "text": ".Hypervisor guest external interrupt-pending register (`hgeip`). include::images/bytefield/hgeipreg.edn[]", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest External Interrupt Registers (`hgeip` and `hgeie`)", + "line_range": [ + 527, + 529 + ] + }, + { + "text": ".Hypervisor guest external interrupt-enable register (`hgeie`). include::images/bytefield/hgeiereg.edn[]", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest External Interrupt Registers (`hgeip` and `hgeie`)", + "line_range": [ + 531, + 533 + ] + }, + { + "text": "Guest external interrupts represent interrupts directed to individual virtual machines at VS-level.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest External Interrupt Registers (`hgeip` and `hgeie`)", + "line_range": [ + 535, + 544 + ] + }, + { + "text": "If a RISC-V platform supports placing a physical device under the direct control of a guest OS with minimal hypervisor intervention (known as pass-through or direct assignment between a virtual machine and the physical device), then, in such circumstance, interrupts from the device are intended for a specific virtual machine.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest External Interrupt Registers (`hgeip` and `hgeie`)", + "line_range": [ + 535, + 544 + ] + }, + { + "text": "Each bit of `hgeip` summarizes all pending interrupts directed to one virtual hart, as collected and reported by an interrupt controller.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest External Interrupt Registers (`hgeip` and `hgeie`)", + "line_range": [ + 535, + 544 + ] + }, + { + "text": "To distinguish specific pending interrupts from multiple devices, software must query the interrupt controller.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest External Interrupt Registers (`hgeip` and `hgeie`)", + "line_range": [ + 535, + 544 + ] + }, + { + "text": "The number of bits implemented in `hgeip` and `hgeie` for guest external interrupts is UNSPECIFIED and may be zero.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest External Interrupt Registers (`hgeip` and `hgeie`)", + "line_range": [ + 546, + 552 + ] + }, + { + "text": "This number is known as GEILEN.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest External Interrupt Registers (`hgeip` and `hgeie`)", + "line_range": [ + 546, + 552 + ] + }, + { + "text": "The least-significant bits are implemented first, apart from bit 0.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest External Interrupt Registers (`hgeip` and `hgeie`)", + "line_range": [ + 546, + 552 + ] + }, + { + "text": "Hence, if GEILEN is nonzero, bits GEILEN:1 shall be writable in `hgeie`, and all other bit positions shall be read-only zeros in both `hgeip` and `hgeie`.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest External Interrupt Registers (`hgeip` and `hgeie`)", + "line_range": [ + 546, + 552 + ] + }, + { + "text": "Register `hgeie` selects the subset of guest external interrupts that cause a supervisor-level (HS-level) guest external interrupt.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest External Interrupt Registers (`hgeip` and `hgeie`)", + "line_range": [ + 554, + 558 + ] + }, + { + "text": "The enable bits in `hgeie` do not affect the VS-level external interrupt signal selected from `hgeip` by `hstatus`.VGEIN.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest External Interrupt Registers (`hgeip` and `hgeie`)", + "line_range": [ + 554, + 558 + ] + }, + { + "text": "The `henvcfg` CSR is a 64-bit read/write register, formatted as shown in , that controls certain characteristics of the execution environment when virtualization mode V=1.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "line_range": [ + 564, + 568 + ] + }, + { + "text": ".Hypervisor environment configuration register (`henvcfg`). [wavedrom, ,svg] .... {reg: [ {bits: 1, name: 'FIOM'}, {bits: 1, name: 'WPRI'}, {bits: 1, name: 'LPE'}, {bits: 1, name: 'SSE'}, {bits: 2, name: 'CBIE'}, {bits: 1, name: 'CBCFE'}, {bits: 1, name: 'CBZE'}, {bits: 24, name: 'WPRI'}, {bits: 2, name: 'PMM'}, {bits: 25, name: 'WPRI'}, {bits: 1, name: 'DTE'}, {bits: 1, name: 'WPRI'}, {bits: 1, name: 'ADUE'}, {bits: 1, name: 'PBMTE'}, {bits: 1, name: 'STCE'}, ], config:{lanes: 4, hspace:1024}} ....", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "line_range": [ + 570, + 591 + ] + }, + { + "text": "If bit FIOM (Fence of I/O implies Memory) is set to one in `henvcfg`, FENCE instructions executed when V=1 are modified so the requirement to order accesses to device I/O implies also the requirement to order main memory accesses. details the modified interpretation of FENCE instruction bits PI, PO, SI, and SO when FIOM=1 and V=1.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "line_range": [ + 593, + 599 + ] + }, + { + "text": "Similarly, when FIOM=1 and V=1, if an atomic instruction that accesses a region ordered as device I/O has its aq and/or rl bit set, then that instruction is ordered as though it accesses both device I/O and memory.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "line_range": [ + 601, + 604 + ] + }, + { + "text": ".Modified interpretation of FENCE predecessor and successor sets when FIOM=1 and virtualization mode V=1. | |Instruction bit |Meaning when set |PI + PO |Predecessor device input and memory reads (PR implied) + Predecessor device output and memory writes (PW implied) |SI + SO |Successor device input and memory reads (SR implied) + Successor device output and memory writes (SW implied) |", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "line_range": [ + 606, + 619 + ] + }, + { + "text": "The PBMTE bit controls whether the Svpbmt extension is available for use in VS-stage address translation.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "line_range": [ + 621, + 626 + ] + }, + { + "text": "When PBMTE=1, Svpbmt is available for VS-stage address translation.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "line_range": [ + 621, + 626 + ] + }, + { + "text": "When PBMTE=0, the implementation behaves as though Svpbmt were not implemented for VS-stage address translation.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "line_range": [ + 621, + 626 + ] + }, + { + "text": "If Svpbmt is not implemented, PBMTE is read-only zero.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "line_range": [ + 621, + 626 + ] + }, + { + "text": "If the Svadu extension is implemented, the ADUE bit controls whether hardware updating of PTE A/D bits is enabled for VS-stage address translation.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "line_range": [ + 628, + 636 + ] + }, + { + "text": "When ADUE=1, hardware updating of PTE A/D bits is enabled during VS-stage address translation, and the implementation behaves as though the Svade extension were not implemented for VS-mode address translation.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "line_range": [ + 628, + 636 + ] + }, + { + "text": "When ADUE=0, the implementation behaves as though Svade were implemented for VS-stage address translation.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "line_range": [ + 628, + 636 + ] + }, + { + "text": "If Svadu is not implemented, ADUE is read-only zero.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "line_range": [ + 628, + 636 + ] + }, + { + "text": "The Sstc extension adds the `STCE` (STimecmp Enable) bit to `henvcfg` CSR.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "line_range": [ + 638, + 644 + ] + }, + { + "text": "When the Sstc extension is not implemented, `STCE` is read-only zero.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "line_range": [ + 638, + 644 + ] + }, + { + "text": "The `STCE` bit enables `vstimecmp` for VS-mode when set to one.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "line_range": [ + 638, + 644 + ] + }, + { + "text": "When `STCE` bit is `henvcfg` is zero, an attempt to access `stimecmp` (really `vstimecmp`) when V=1 raises a virtual-instruction exception, and `VSTIP` in `hip` reverts to its defined behavior as if this extension is not implemented.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "line_range": [ + 638, + 644 + ] + }, + { + "text": "The Zicboz extension adds the `CBZE` (Cache Block Zero instruction enable) field to `henvcfg`.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "line_range": [ + 646, + 654 + ] + }, + { + "text": "The `CBZE` field applies to execution of the cache block zero instruction (`CBO.ZERO`) in privilege modes VS and VU, and only when the instruction is HS-qualified.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "line_range": [ + 646, + 654 + ] + }, + { + "text": "If the instruction is not HS-qualified, it raises an illegal-instruction exception.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "line_range": [ + 646, + 654 + ] + }, + { + "text": "If the instruction is HS-qualified and the `CBZE` field is set to 1, the instruction is enabled for execution; otherwise, if the `CBZE` field is set to 0, it raises a virtual-instruction exception.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "line_range": [ + 646, + 654 + ] + }, + { + "text": "When the Zicboz extension is not implemented, `CBZE` is read-only zero.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "line_range": [ + 646, + 654 + ] + }, + { + "text": "The Zicbom extension adds the `CBCFE` (Cache Block Clean and Flush instruction Enable) field to `henvcfg`.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "line_range": [ + 656, + 663 + ] + }, + { + "text": "When V=1, if the `CBO.CLEAN` and `CBO.FLUSH` instructions are not HS-qualified, they raise an illegal-instruction exception.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "line_range": [ + 656, + 663 + ] + }, + { + "text": "If the instructions are HS-qualified and the `CBCFE` field is set to 1, the instructions are enabled for execution; otherwise, if the `CBCFE` field is set to 0, they raise a virtual-instruction exception.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "line_range": [ + 656, + 663 + ] + }, + { + "text": "When the Zicbom extension is not implemented, `CBCFE` is read-only zero.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "line_range": [ + 656, + 663 + ] + }, + { + "text": "The Zicbom extension adds the `CBIE` (Cache Block Invalidate instruction Enable) WARL field to `henvcfg`.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "line_range": [ + 665, + 670 + ] + }, + { + "text": "The `CBIE` field controls execution of the cache block invalidate instruction (`CBO.INVAL`) in privilege modes VS and VU.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "line_range": [ + 665, + 670 + ] + }, + { + "text": "The encoding `10b` is reserved.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "line_range": [ + 665, + 670 + ] + }, + { + "text": "When the Zicbom extension is not implemented, `CBIE` is read-only zero.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "line_range": [ + 665, + 670 + ] + }, + { + "text": "When V=1, if the `CBO.INVAL` instruction is not HS-qualified, it raises an illegal-instruction exception.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "line_range": [ + 672, + 676 + ] + }, + { + "text": "If the instruction is HS-qualified and the `CBIE` field is set to `01b` or `11b`, the instruction is enabled for execution; otherwise, it raises a virtual-instruction exception.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "line_range": [ + 672, + 676 + ] + }, + { + "text": "If `CBO.INVAL` is enabled in HS-mode to perform a flush operation, then when the instruction is enabled in VS- or VU-mode it performs a flush operation, even if `CBIE` is set to `11b`.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "line_range": [ + 678, + 681 + ] + }, + { + "text": "Otherwise, when the instruction is enabled for execution, its behavior depends on the `CBIE` encoding, as follows:", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "line_range": [ + 678, + 681 + ] + }, + { + "text": "`01b` -- The instruction is executed and performs a flush operation, even if configured by VS-mode to perform an invalidate operation. * `11b` -- The instruction is executed and performs an invalidate operation, unless configured by VS-mode to perform a flush operation.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "line_range": [ + 683, + 686 + ] + }, + { + "text": "If the Ssnpm extension is implemented, the `PMM` field enables or disables pointer masking (see ) for VS-mode, according to the values in .", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "line_range": [ + 688, + 692 + ] + }, + { + "text": "When the Ssnpm extension is not implemented, the `PMM` field is read-only zero.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "line_range": [ + 688, + 692 + ] + }, + { + "text": "The `PMM` field is read-only zero for RV32.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "line_range": [ + 688, + 692 + ] + }, + { + "text": ".Legal values of `PMM` WARL field | |Value|Description |00|Pointer masking is disabled (PMLEN = 0) |01|Reserved |10|Pointer masking is enabled with PMLEN = XLEN - 57 (PMLEN = 7 on RV64) |11|Pointer masking is enabled with PMLEN = XLEN - 48 (PMLEN = 16 on RV64) |", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "line_range": [ + 696, + 704 + ] + }, + { + "text": "The Zicfilp extension adds the `LPE` field in `henvcfg`.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "line_range": [ + 706, + 710 + ] + }, + { + "text": "When the `LPE` field is set to 1, the Zicfilp extension is enabled in VS-mode.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "line_range": [ + 706, + 710 + ] + }, + { + "text": "When the `LPE` field is 0, the Zicfilp extension is not enabled in VS-mode and the following rules apply to VS-mode:", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "line_range": [ + 706, + 710 + ] + }, + { + "text": "The hart does not update the `ELP` state; it remains as `NOLPEXPECTED`. * The `LPAD` instruction operates as a no-op.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "line_range": [ + 712, + 713 + ] + }, + { + "text": "The Zicfiss extension adds the `SSE` field in `henvcfg`.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "line_range": [ + 715, + 719 + ] + }, + { + "text": "If the `SSE` field is set to 1, the Zicfiss extension is activated in VS-mode.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "line_range": [ + 715, + 719 + ] + }, + { + "text": "When the `SSE` field is 0, the Zicfiss extension remains inactive in VS-mode, and the following rules apply when `V=1`:", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "line_range": [ + 715, + 719 + ] + }, + { + "text": "32-bit Zicfiss instructions will revert to their behavior as defined by Zimop. * 16-bit Zicfiss instructions will revert to their behavior as defined by Zcmop. * The `pte.xwr=010b` encoding in VS-stage page tables becomes reserved. * The `senvcfg.SSE` field will read as zero and is read-only. *", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "line_range": [ + 721, + 726 + ] + }, + { + "text": "When `menvcfg.SSE` is one, `SSAMOSWAP.W/D` raises a virtual-instruction exception.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "line_range": [ + 721, + 726 + ] + }, + { + "text": "The Ssdbltrp extension adds the double-trap-enable (`DTE`) field in `henvcfg`.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "line_range": [ + 728, + 731 + ] + }, + { + "text": "When `henvcfg.DTE` is zero, the implementation behaves as though Ssdbltrp is not implemented for VS-mode and the `vsstatus.SDT` bit is read-only zero.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "line_range": [ + 728, + 731 + ] + }, + { + "text": "When XLEN=32, `henvcfgh` is a 32-bit read/write register that aliases bits 63:32 of `henvcfg`.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "line_range": [ + 733, + 737 + ] + }, + { + "text": "Register `henvcfgh` does not exist when XLEN=64.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Environment Configuration Register (`henvcfg`)", + "line_range": [ + 733, + 737 + ] + }, + { + "text": "The counter-enable register `hcounteren` is a 32-bit register that controls the availability of the hardware performance monitoring counters to the guest virtual machine.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Counter-Enable (`hcounteren`) Register", + "line_range": [ + 741, + 744 + ] + }, + { + "text": ".Hypervisor counter-enable register (`hcounteren`). include::images/bytefield/hcounterenreg.edn[]", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Counter-Enable (`hcounteren`) Register", + "line_range": [ + 746, + 747 + ] + }, + { + "text": "When the CY, TM, IR, or HPMn bit in the `hcounteren` register is clear, attempts to read the `cycle`, `time`, `instret`, or `hpmcounter` n register while V=1 will cause a virtual-instruction exception if the same bit in `mcounteren` is 1.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Counter-Enable (`hcounteren`) Register", + "line_range": [ + 749, + 757 + ] + }, + { + "text": "When one of these bits is set, access to the corresponding register is permitted when V=1, unless prevented for some other reason.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Counter-Enable (`hcounteren`) Register", + "line_range": [ + 749, + 757 + ] + }, + { + "text": "In VU-mode, a counter is not readable unless the applicable bits are set in both `hcounteren` and `scounteren`.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Counter-Enable (`hcounteren`) Register", + "line_range": [ + 749, + 757 + ] + }, + { + "text": "In addition, when the TM bit in the `hcounteren` register is clear, attempts to access the `vstimecmp` register (via `stimecmp`) while executing in VS-mode will cause a virtual-instruction exception if the same bit in `mcounteren` is set.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Counter-Enable (`hcounteren`) Register", + "line_range": [ + 759, + 764 + ] + }, + { + "text": "When this bit and the same bit in `mcounteren` are both set, access to the `vstimecmp` register (if implemented) is permitted in VS-mode.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Counter-Enable (`hcounteren`) Register", + "line_range": [ + 759, + 764 + ] + }, + { + "text": "`hcounteren` must be implemented.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Counter-Enable (`hcounteren`) Register", + "line_range": [ + 766, + 769 + ] + }, + { + "text": "However, any of the bits may be read-only zero, indicating reads to the corresponding counter will cause an exception when V=1.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Counter-Enable (`hcounteren`) Register", + "line_range": [ + 766, + 769 + ] + }, + { + "text": "Hence, they are effectively *WARL* fields.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Counter-Enable (`hcounteren`) Register", + "line_range": [ + 766, + 769 + ] + }, + { + "text": "The `htimedelta` CSR is a 64-bit read/write register that contains the delta between the value of the `time` CSR and the value returned in VS-mode or VU-mode.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Time Delta (`htimedelta`) Register", + "line_range": [ + 773, + 777 + ] + }, + { + "text": "That is, reading the `time` CSR in VS or VU mode returns the sum of the contents of `htimedelta` and the actual value of `time`.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Time Delta (`htimedelta`) Register", + "line_range": [ + 773, + 777 + ] + }, + { + "text": ".Hypervisor time delta register. include::images/bytefield/htimedelta.edn[]", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Time Delta (`htimedelta`) Register", + "line_range": [ + 779, + 780 + ] + }, + { + "text": "When XLEN=32, `htimedeltah` is a 32-bit read/write register that aliases bits 63:32 of `htimedelta`.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Time Delta (`htimedelta`) Register", + "line_range": [ + 782, + 785 + ] + }, + { + "text": "Register `htimedeltah` does not exist when XLEN=64.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Time Delta (`htimedelta`) Register", + "line_range": [ + 782, + 785 + ] + }, + { + "text": "If the `time` CSR is implemented, `htimedelta` (and `htimedeltah` for XLEN=32) must be implemented.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Time Delta (`htimedelta`) Register", + "line_range": [ + 787, + 789 + ] + }, + { + "text": "The `htval` register is an HSXLEN-bit read/write register formatted as shown in .", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Value (`htval`) Register", + "line_range": [ + 793, + 797 + ] + }, + { + "text": "When a trap is taken into HS-mode, `htval` is written with additional exception-specific information, alongside `stval`, to assist software in handling the trap.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Value (`htval`) Register", + "line_range": [ + 793, + 797 + ] + }, + { + "text": ".Hypervisor trap value register (`htval`). include::images/bytefield/htvalreg.edn[]", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Value (`htval`) Register", + "line_range": [ + 799, + 801 + ] + }, + { + "text": "When a guest-page-fault trap is taken into HS-mode, `htval` is written with either zero or the guest physical address that faulted, shifted right by 2 bits.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Value (`htval`) Register", + "line_range": [ + 803, + 807 + ] + }, + { + "text": "For other traps, `htval` is set to zero, but a future standard or extension may redefine `htval's` setting for other traps.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Value (`htval`) Register", + "line_range": [ + 803, + 807 + ] + }, + { + "text": "A guest-page fault may arise due to an implicit memory access during first-stage (VS-stage) address translation, in which case a guest physical address written to `htval` is that of the implicit memory access that faulted—for example, the address of a VS-level page table entry that could not be read. (The guest physical address corresponding to the original virtual address is unknown when VS-stage translation fails to complete.) Additional information is provided in CSR `htinst` to disambiguate such situations.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Value (`htval`) Register", + "line_range": [ + 809, + 816 + ] + }, + { + "text": "Otherwise, for misaligned loads and stores that cause guest-page faults, a nonzero guest physical address in `htval` corresponds to the faulting portion of the access as indicated by the virtual address in `stval`.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Value (`htval`) Register", + "line_range": [ + 818, + 823 + ] + }, + { + "text": "For instruction guest-page faults on systems with variable-length instructions, a nonzero `htval` corresponds to the faulting portion of the instruction as indicated by the virtual address in `stval`.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Value (`htval`) Register", + "line_range": [ + 818, + 823 + ] + }, + { + "text": "`htval` is a *WARL* register that must be able to hold zero and may be capable of holding only an arbitrary subset of other 2-bit-shifted guest physical addresses, if any.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Value (`htval`) Register", + "line_range": [ + 825, + 828 + ] + }, + { + "text": "The `htinst` register is an HSXLEN-bit read/write register formatted as shown in .", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Instruction (`htinst`) Register", + "line_range": [ + 832, + 838 + ] + }, + { + "text": "When a trap is taken into HS-mode, `htinst` is written with a value that, if nonzero, provides information about the instruction that trapped, to assist software in handling the trap.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Instruction (`htinst`) Register", + "line_range": [ + 832, + 838 + ] + }, + { + "text": "The values that may be written to `htinst` on a trap are documented in .", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Instruction (`htinst`) Register", + "line_range": [ + 832, + 838 + ] + }, + { + "text": ".Hypervisor trap instruction (`htinst`) register. include::images/bytefield/htinstreg.edn[]", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Instruction (`htinst`) Register", + "line_range": [ + 840, + 842 + ] + }, + { + "text": "`htinst` is a *WARL* register that need only be able to hold the values that the implementation may automatically write to it on a trap.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Trap Instruction (`htinst`) Register", + "line_range": [ + 844, + 846 + ] + }, + { + "text": "The `hgatp` register is an HSXLEN-bit read/write register, formatted as shown in for HSXLEN=32 and for HSXLEN=64, which controls G-stage address translation and protection, the second stage of two-stage translation for guest virtual addresses (see ).", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest Address Translation and Protection (`hgatp`) Register", + "line_range": [ + 851, + 862 + ] + }, + { + "text": "Similar to CSR `satp`, this register holds the physical page number (PPN) of the guest-physical root page table; a virtual machine identifier (VMID), which facilitates address-translation fences on a per-virtual-machine basis; and the MODE field, which selects the address-translation scheme for guest physical addresses.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest Address Translation and Protection (`hgatp`) Register", + "line_range": [ + 851, + 862 + ] + }, + { + "text": "When `mstatus`.TVM=1, attempts to read or write `hgatp` while executing in HS-mode will raise an illegal-instruction exception.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest Address Translation and Protection (`hgatp`) Register", + "line_range": [ + 851, + 862 + ] + }, + { + "text": ".Hypervisor guest address translation and protection register `hgatp` when HSXLEN=32. include::images/bytefield/rv32hgatp.edn[]", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest Address Translation and Protection (`hgatp`) Register", + "line_range": [ + 864, + 866 + ] + }, + { + "text": ".Hypervisor guest address translation and protection register `hgatp` when HSXLEN=64 for MODE values Bare, Sv39x4, Sv48x4, and Sv57x4. include::images/bytefield/rv64hgatp.edn[]", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest Address Translation and Protection (`hgatp`) Register", + "line_range": [ + 868, + 870 + ] + }, + { + "text": "shows the encodings of the MODE field when HSXLEN=32 and HSXLEN=64.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest Address Translation and Protection (`hgatp`) Register", + "line_range": [ + 872, + 880 + ] + }, + { + "text": "When MODE=Bare, guest physical addresses are equal to supervisor physical addresses, and there is no further memory protection for a guest virtual machine beyond the physical memory protection scheme described in .", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest Address Translation and Protection (`hgatp`) Register", + "line_range": [ + 872, + 880 + ] + }, + { + "text": "In this case, software must write zero to the remaining fields in `hgatp`.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest Address Translation and Protection (`hgatp`) Register", + "line_range": [ + 872, + 880 + ] + }, + { + "text": "Attempting to select MODE=Bare with a nonzero pattern in the remaining fields has an UNSPECIFIED effect on the value that the remaining fields assume and an UNSPECIFIED effect on G-stage address translation and protection behavior.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest Address Translation and Protection (`hgatp`) Register", + "line_range": [ + 872, + 880 + ] + }, + { + "text": "When HSXLEN=32, the only other valid setting for MODE is Sv32x4, which is a modification of the usual Sv32 paged virtual-memory scheme, extended to support 34-bit guest physical addresses.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest Address Translation and Protection (`hgatp`) Register", + "line_range": [ + 882, + 889 + ] + }, + { + "text": "When HSXLEN=64, modes Sv39x4, Sv48x4, and Sv57x4 are defined as modifications of the Sv39, Sv48, and Sv57 paged virtual-memory schemes.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest Address Translation and Protection (`hgatp`) Register", + "line_range": [ + 882, + 889 + ] + }, + { + "text": "All of these paged virtual-memory schemes are described in .", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest Address Translation and Protection (`hgatp`) Register", + "line_range": [ + 882, + 889 + ] + }, + { + "text": "The remaining MODE settings when HSXLEN=64 are reserved for future use and may define different interpretations of the other fields in `hgatp`.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest Address Translation and Protection (`hgatp`) Register", + "line_range": [ + 891, + 892 + ] + }, + { + "text": ".Encoding of `hgatp` MODE field. | 3+|HSXLEN=32 |Value |Name |Description |0 + 1 |Bare + Sv32x4 |No translation or protection. + Page-based 34-bit virtual addressing (2-bit extension of Sv32). 3+s|HSXLEN=64 |Value |Name |Description |0 + 1-7 + 8 + 9 + 10 + 11-15 |Bare + — + Sv39x4 + Sv48x4 + Sv57x4 + — |No translation or protection. + Reserved + Page-based 41-bit virtual addressing (2-bit extension of Sv39). + Page-based 50-bit virtual addressing (2-bit extension of Sv48). + Page-based 59-bit virtual addressing (2-bit extension of Sv57). + Reserved |", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest Address Translation and Protection (`hgatp`) Register", + "line_range": [ + 894, + 930 + ] + }, + { + "text": "Implementations are not required to support all defined MODE settings when HSXLEN=64.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest Address Translation and Protection (`hgatp`) Register", + "line_range": [ + 932, + 933 + ] + }, + { + "text": "A write to `hgatp` with an unsupported MODE value is not ignored as it is for `satp`.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest Address Translation and Protection (`hgatp`) Register", + "line_range": [ + 935, + 938 + ] + }, + { + "text": "Instead, the fields of `hgatp` are *WARL* in the normal way, when so indicated.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest Address Translation and Protection (`hgatp`) Register", + "line_range": [ + 935, + 938 + ] + }, + { + "text": "As explained in , for the paged virtual-memory schemes (Sv32x4, Sv39x4, Sv48x4, and Sv57x4), the root page table is 16 KiB and must be aligned to a 16-KiB boundary.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest Address Translation and Protection (`hgatp`) Register", + "line_range": [ + 940, + 947 + ] + }, + { + "text": "In these modes, the lowest two bits of the physical page number (PPN) in `hgatp` always read as zeros.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest Address Translation and Protection (`hgatp`) Register", + "line_range": [ + 940, + 947 + ] + }, + { + "text": "An implementation that supports only the defined paged virtual-memory schemes and/or Bare may make PPN[1:0] read-only zero.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest Address Translation and Protection (`hgatp`) Register", + "line_range": [ + 940, + 947 + ] + }, + { + "text": "The number of VMID bits is UNSPECIFIED and may be zero.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest Address Translation and Protection (`hgatp`) Register", + "line_range": [ + 949, + 956 + ] + }, + { + "text": "The number of implemented VMID bits, termed VMIDLEN, may be determined by writing one to every bit position in the VMID field, then reading back the value in `hgatp` to see which bit positions in the VMID field hold a one.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest Address Translation and Protection (`hgatp`) Register", + "line_range": [ + 949, + 956 + ] + }, + { + "text": "The least-significant bits of VMID are implemented first: that is, if VMIDLEN > 0, VMID[VMIDLEN-1:0] is writable.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest Address Translation and Protection (`hgatp`) Register", + "line_range": [ + 949, + 956 + ] + }, + { + "text": "The maximal value of VMIDLEN, termed VMIDMAX, is 7 for Sv32x4 or 14 for Sv39x4, Sv48x4, and Sv57x4.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest Address Translation and Protection (`hgatp`) Register", + "line_range": [ + 949, + 956 + ] + }, + { + "text": "The `hgatp` register is considered active for the purposes of the address-translation algorithm unless the effective privilege mode is U and `hstatus`.HU=0.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest Address Translation and Protection (`hgatp`) Register", + "line_range": [ + 958, + 960 + ] + }, + { + "text": "Note that writing `hgatp` does not imply any ordering constraints between page-table updates and subsequent G-stage address translations.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest Address Translation and Protection (`hgatp`) Register", + "line_range": [ + 962, + 967 + ] + }, + { + "text": "If the new virtual machine’s guest physical page tables have been modified, or if a VMID is reused, it may be necessary to execute an HFENCE.GVMA instruction (see ) before or after writing `hgatp`.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Hypervisor Guest Address Translation and Protection (`hgatp`) Register", + "line_range": [ + 962, + 967 + ] + }, + { + "text": "The `vsstatus` register is a VSXLEN-bit read/write register that is VS-mode’s version of supervisor register `sstatus`, formatted as shown in when VSXLEN=32 and when VSXLEN=64.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Status (`vsstatus`) Register", + "line_range": [ + 972, + 978 + ] + }, + { + "text": "When V=1, `vsstatus` substitutes for the usual `sstatus`, so instructions that normally read or modify `sstatus` actually access `vsstatus` instead.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Status (`vsstatus`) Register", + "line_range": [ + 972, + 978 + ] + }, + { + "text": ".Virtual supervisor status (`vsstatus`) register when VSXLEN=32. [wavedrom, ,svg] .... {reg: [ {bits: 1, name: 'WPRI'}, {bits: 1, name: 'SIE'}, {bits: 3, name: 'WPRI'}, {bits: 1, name: 'SPIE'}, {bits: 1, name: 'UBE'}, {bits: 1, name: 'WPRI'}, {bits: 1, name: 'SPP'}, {bits: 2, name: 'VS[1:0]'}, {bits: 2, name: 'WPRI'}, {bits: 2, name: 'FS[1:0]'}, {bits: 2, name: 'XS[1:0]'}, {bits: 1, name: 'WPRI'}, {bits: 1, name: 'SUM'}, {bits: 1, name: 'MXR'}, {bits: 3, name: 'WPRI'}, {bits: 1, name: 'SPELP'}, {bits: 1, name: 'SDT'}, {bits: 6, name: 'WPRI'}, {bits: 1, name: 'SD'}, ], config:{lanes: 2, hspace:1024}} ....", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Status (`vsstatus`) Register", + "line_range": [ + 980, + 1005 + ] + }, + { + "text": ".Virtual supervisor status (`vsstatus`) register when VSXLEN=64. [wavedrom, ,svg] .... {reg: [ {bits: 1, name: 'WPRI'}, {bits: 1, name: 'SIE'}, {bits: 3, name: 'WPRI'}, {bits: 1, name: 'SPIE'}, {bits: 1, name: 'UBE'}, {bits: 1, name: 'WPRI'}, {bits: 1, name: 'SPP'}, {bits: 2, name: 'VS[1:0]'}, {bits: 2, name: 'WPRI'}, {bits: 2, name: 'FS[1:0]'}, {bits: 2, name: 'XS[1:0]'}, {bits: 1, name: 'WPRI'}, {bits: 1, name: 'SUM'}, {bits: 1, name: 'MXR'}, {bits: 3, name: 'WPRI'}, {bits: 1, name: 'SPELP'}, {bits: 1, name: 'SDT'}, {bits: 7, name: 'WPRI'}, {bits: 2, name: 'UXL[1:0]'}, {bits: 29, name: 'WPRI'}, {bits: 1, name: 'SD'}, ], config:{lanes: 4, hspace:1024}} ....", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Status (`vsstatus`) Register", + "line_range": [ + 1007, + 1034 + ] + }, + { + "text": "The UXL field controls the effective XLEN for VU-mode, which may differ from the XLEN for VS-mode (VSXLEN).", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Status (`vsstatus`) Register", + "line_range": [ + 1036, + 1040 + ] + }, + { + "text": "When VSXLEN=32, the UXL field does not exist, and VU-mode XLEN=32.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Status (`vsstatus`) Register", + "line_range": [ + 1036, + 1040 + ] + }, + { + "text": "When VSXLEN=64, UXL is a *WARL* field that is encoded the same as the MXL field of `misa`, shown in .", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Status (`vsstatus`) Register", + "line_range": [ + 1036, + 1040 + ] + }, + { + "text": "In particular, an implementation may make UXL be a read-only copy of field VSXL of `hstatus`, forcing VU-mode XLEN=VSXLEN.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Status (`vsstatus`) Register", + "line_range": [ + 1036, + 1040 + ] + }, + { + "text": "If VSXLEN is changed from 32 to a wider width, and if field UXL is not restricted to a single value, it gets the value corresponding to the widest supported width not wider than the new VSXLEN.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Status (`vsstatus`) Register", + "line_range": [ + 1042, + 1045 + ] + }, + { + "text": "When V=1, both `vsstatus`.FS and the HS-level `sstatus`.FS are in effect.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Status (`vsstatus`) Register", + "line_range": [ + 1047, + 1051 + ] + }, + { + "text": "Attempts to execute a floating-point instruction when either field is 0 (Off) raise an illegal-instruction exception.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Status (`vsstatus`) Register", + "line_range": [ + 1047, + 1051 + ] + }, + { + "text": "Modifying the floating-point state when V=1 causes both fields to be set to 3 (Dirty).", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Status (`vsstatus`) Register", + "line_range": [ + 1047, + 1051 + ] + }, + { + "text": "Similarly, when V=1, both `vsstatus`.VS and the HS-level `sstatus`.VS are in effect.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Status (`vsstatus`) Register", + "line_range": [ + 1053, + 1057 + ] + }, + { + "text": "Attempts to execute a vector instruction when either field is 0 (Off) raise an illegal-instruction exception.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Status (`vsstatus`) Register", + "line_range": [ + 1053, + 1057 + ] + }, + { + "text": "Modifying the vector state when V=1 causes both fields to be set to 3 (Dirty).", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Status (`vsstatus`) Register", + "line_range": [ + 1053, + 1057 + ] + }, + { + "text": "Read-only fields SD and XS summarize the extension context status as it is visible to VS-mode only.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Status (`vsstatus`) Register", + "line_range": [ + 1059, + 1062 + ] + }, + { + "text": "For example, the value of the HS-level `sstatus`.FS does not affect `vsstatus`.SD.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Status (`vsstatus`) Register", + "line_range": [ + 1059, + 1062 + ] + }, + { + "text": "An implementation may make field UBE be a read-only copy of `hstatus`.VSBE.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Status (`vsstatus`) Register", + "line_range": [ + 1064, + 1066 + ] + }, + { + "text": "When V=0, `vsstatus` does not directly affect the behavior of the machine, unless a virtual-machine load/store (HLV, HLVX, or HSV) or the MPRV feature in the `mstatus` register is used to execute a load or store as though V=1.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Status (`vsstatus`) Register", + "line_range": [ + 1068, + 1072 + ] + }, + { + "text": "The Zicfilp extension adds the `SPELP` field that holds the previous `ELP`, and is updated as specified in .", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Status (`vsstatus`) Register", + "line_range": [ + 1074, + 1077 + ] + }, + { + "text": "The `SPELP` field is encoded as follows:", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Status (`vsstatus`) Register", + "line_range": [ + 1074, + 1077 + ] + }, + { + "text": "0 - `NOLPEXPECTED` - no landing pad instruction expected. * 1 - `LPEXPECTED` - a landing pad instruction is expected.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Status (`vsstatus`) Register", + "line_range": [ + 1079, + 1080 + ] + }, + { + "text": "The Ssdbltrp adds an S-mode-disable-trap (`SDT`) field extension to address double trap (See ) in VS-mode.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Status (`vsstatus`) Register", + "line_range": [ + 1082, + 1084 + ] + }, + { + "text": "The `vsip` and `vsie` registers are VSXLEN-bit read/write registers that are VS-mode’s versions of supervisor CSRs `sip` and `sie`, formatted as shown in and respectively.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Interrupt (`vsip` and `vsie`) Registers", + "line_range": [ + 1088, + 1096 + ] + }, + { + "text": "When V=1, `vsip` and `vsie` substitute for the usual `sip` and `sie`, so instructions that normally read or modify `sip`/`sie` actually access `vsip`/`vsie` instead.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Interrupt (`vsip` and `vsie`) Registers", + "line_range": [ + 1088, + 1096 + ] + }, + { + "text": "However, interrupts directed to HS-level continue to be indicated in the HS-level `sip` register, not in `vsip`, when V=1.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Interrupt (`vsip` and `vsie`) Registers", + "line_range": [ + 1088, + 1096 + ] + }, + { + "text": ".Virtual supervisor interrupt-pending register (`vsip`). include::images/bytefield/vsipreg.edn[]", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Interrupt (`vsip` and `vsie`) Registers", + "line_range": [ + 1098, + 1100 + ] + }, + { + "text": ".Virtual supervisor interrupt-enable register (`vsie`). include::images/bytefield/vsiereg.edn[]", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Interrupt (`vsip` and `vsie`) Registers", + "line_range": [ + 1102, + 1104 + ] + }, + { + "text": "The standard portions (bits 15:0) of registers `vsip` and `vsie` are formatted as shown in and respectively.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Interrupt (`vsip` and `vsie`) Registers", + "line_range": [ + 1106, + 1108 + ] + }, + { + "text": ".Standard portion (bits 15:0) of `vsip`. include::images/bytefield/vsipreg-standard.edn[]", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Interrupt (`vsip` and `vsie`) Registers", + "line_range": [ + 1110, + 1112 + ] + }, + { + "text": ".Standard portion (bits 15:0) of `vsie`. include::images/bytefield/vsiereg-standard.edn[]", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Interrupt (`vsip` and `vsie`) Registers", + "line_range": [ + 1114, + 1116 + ] + }, + { + "text": "Extension Shlcofideleg supports delegating LCOFI interrupts to VS-mode.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Interrupt (`vsip` and `vsie`) Registers", + "line_range": [ + 1118, + 1125 + ] + }, + { + "text": "If the Shlcofideleg extension is implemented, `hideleg` bit 13 is writable; otherwise, it is read-only zero.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Interrupt (`vsip` and `vsie`) Registers", + "line_range": [ + 1118, + 1125 + ] + }, + { + "text": "When bit 13 of `hideleg` is zero, `vsip`.LCOFIP and `vsie`.LCOFIE are read-only zeros.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Interrupt (`vsip` and `vsie`) Registers", + "line_range": [ + 1118, + 1125 + ] + }, + { + "text": "Else, `vsip`.LCOFIP and `vsie`.LCOFIE are aliases of `sip`.LCOFIP and `sie`.LCOFIE.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Interrupt (`vsip` and `vsie`) Registers", + "line_range": [ + 1118, + 1125 + ] + }, + { + "text": "When bit 10 of `hideleg` is zero, `vsip`.SEIP and `vsie`.SEIE are read-only zeros.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Interrupt (`vsip` and `vsie`) Registers", + "line_range": [ + 1127, + 1130 + ] + }, + { + "text": "Else, `vsip`.SEIP and `vsie`.SEIE are aliases of `hip`.VSEIP and `hie`.VSEIE.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Interrupt (`vsip` and `vsie`) Registers", + "line_range": [ + 1127, + 1130 + ] + }, + { + "text": "When bit 6 of `hideleg` is zero, `vsip`.STIP and `vsie`.STIE are read-only zeros.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Interrupt (`vsip` and `vsie`) Registers", + "line_range": [ + 1132, + 1135 + ] + }, + { + "text": "Else, `vsip`.STIP and `vsie`.STIE are aliases of `hip`.VSTIP and `hie`.VSTIE.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Interrupt (`vsip` and `vsie`) Registers", + "line_range": [ + 1132, + 1135 + ] + }, + { + "text": "When bit 2 of `hideleg` is zero, `vsip`.SSIP and `vsie`.SSIE are read-only zeros.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Interrupt (`vsip` and `vsie`) Registers", + "line_range": [ + 1137, + 1140 + ] + }, + { + "text": "Else, `vsip`.SSIP and `vsie`.SSIE are aliases of `hip`.VSSIP and `hie`.VSSIE.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Interrupt (`vsip` and `vsie`) Registers", + "line_range": [ + 1137, + 1140 + ] + }, + { + "text": "The `vstvec` register is a VSXLEN-bit read/write register that is VS-mode’s version of supervisor register `stvec`, formatted as shown in .", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Trap Vector Base Address (`vstvec`) Register", + "line_range": [ + 1144, + 1150 + ] + }, + { + "text": "When V=1, `vstvec` substitutes for the usual `stvec`, so instructions that normally read or modify `stvec` actually access `vstvec` instead.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Trap Vector Base Address (`vstvec`) Register", + "line_range": [ + 1144, + 1150 + ] + }, + { + "text": "When V=0, `vstvec` does not directly affect the behavior of the machine.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Trap Vector Base Address (`vstvec`) Register", + "line_range": [ + 1144, + 1150 + ] + }, + { + "text": ".Virtual supervisor trap vector base address register `vstvec`. include::images/bytefield/vstvecreg.edn[]", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Trap Vector Base Address (`vstvec`) Register", + "line_range": [ + 1152, + 1154 + ] + }, + { + "text": "The `vsscratch` register is a VSXLEN-bit read/write register that is VS-mode’s version of supervisor register `sscratch`, formatted as shown in .", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Scratch (`vsscratch`) Register", + "line_range": [ + 1158, + 1164 + ] + }, + { + "text": "When V=1, `vsscratch` substitutes for the usual `sscratch`, so instructions that normally read or modify `sscratch` actually access `vsscratch` instead.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Scratch (`vsscratch`) Register", + "line_range": [ + 1158, + 1164 + ] + }, + { + "text": "The contents of `vsscratch` never directly affect the behavior of the machine.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Scratch (`vsscratch`) Register", + "line_range": [ + 1158, + 1164 + ] + }, + { + "text": ".Virtual supervisor scratch register `vsscratch`. include::images/bytefield/vsscratchreg.edn[]", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Scratch (`vsscratch`) Register", + "line_range": [ + 1166, + 1168 + ] + }, + { + "text": "The `vsepc` register is a VSXLEN-bit read/write register that is VS-mode’s version of supervisor register `sepc`, formatted as shown in .", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Exception Program Counter (`vsepc`) Register", + "line_range": [ + 1172, + 1178 + ] + }, + { + "text": "When V=1, `vsepc` substitutes for the usual `sepc`, so instructions that normally read or modify `sepc` actually access `vsepc` instead.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Exception Program Counter (`vsepc`) Register", + "line_range": [ + 1172, + 1178 + ] + }, + { + "text": "When V=0, `vsepc` does not directly affect the behavior of the machine.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Exception Program Counter (`vsepc`) Register", + "line_range": [ + 1172, + 1178 + ] + }, + { + "text": "`vsepc` is a *WARL* register that must be able to hold the same set of values that `sepc` can hold.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Exception Program Counter (`vsepc`) Register", + "line_range": [ + 1180, + 1182 + ] + }, + { + "text": ".Virtual supervisor exception program counter (`vsepc`). include::images/bytefield/vsepcreg.edn[]", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Exception Program Counter (`vsepc`) Register", + "line_range": [ + 1184, + 1186 + ] + }, + { + "text": "The `vscause` register is a VSXLEN-bit read/write register that is VS-mode’s version of supervisor register `scause`, formatted as shown in .", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Cause (`vscause`) Register", + "line_range": [ + 1190, + 1196 + ] + }, + { + "text": "When V=1, `vscause` substitutes for the usual `scause`, so instructions that normally read or modify `scause` actually access `vscause` instead.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Cause (`vscause`) Register", + "line_range": [ + 1190, + 1196 + ] + }, + { + "text": "When V=0, `vscause` does not directly affect the behavior of the machine.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Cause (`vscause`) Register", + "line_range": [ + 1190, + 1196 + ] + }, + { + "text": "`vscause` is a *WLRL* register that must be able to hold the same set of values that `scause` can hold.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Cause (`vscause`) Register", + "line_range": [ + 1198, + 1200 + ] + }, + { + "text": ".Virtual supervisor cause register (`vscause`). include::images/bytefield/vscausereg.edn[]", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Cause (`vscause`) Register", + "line_range": [ + 1202, + 1204 + ] + }, + { + "text": "The `vstval` register is a VSXLEN-bit read/write register that is VS-mode’s version of supervisor register `stval`, formatted as shown in .", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Trap Value (`vstval`) Register", + "line_range": [ + 1208, + 1214 + ] + }, + { + "text": "When V=1, `vstval` substitutes for the usual `stval`, so instructions that normally read or modify `stval` actually access `vstval` instead.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Trap Value (`vstval`) Register", + "line_range": [ + 1208, + 1214 + ] + }, + { + "text": "When V=0, `vstval` does not directly affect the behavior of the machine.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Trap Value (`vstval`) Register", + "line_range": [ + 1208, + 1214 + ] + }, + { + "text": "`vstval` is a *WARL* register that must be able to hold the same set of values that `stval` can hold.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Trap Value (`vstval`) Register", + "line_range": [ + 1216, + 1218 + ] + }, + { + "text": ".Virtual supervisor trap value register (`vstval`). include::images/bytefield/vstvalreg.edn[]", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Trap Value (`vstval`) Register", + "line_range": [ + 1220, + 1222 + ] + }, + { + "text": "The `vsatp` register is a VSXLEN-bit read/write register that is VS-mode’s version of supervisor register `satp`, formatted as shown in for VSXLEN=32 and for VSXLEN=64.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Address Translation and Protection (`vsatp`) Register", + "line_range": [ + 1226, + 1234 + ] + }, + { + "text": "When V=1, `vsatp` substitutes for the usual `satp`, so instructions that normally read or modify `satp` actually access `vsatp` instead. `vsatp` controls VS-stage address translation, the first stage of two-stage translation for guest virtual addresses (see ).", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Address Translation and Protection (`vsatp`) Register", + "line_range": [ + 1226, + 1234 + ] + }, + { + "text": ".Virtual supervisor address translation and protection `vsatp` register when VSXLEN=32. include::images/bytefield/rv32vsatpreg.edn[]", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Address Translation and Protection (`vsatp`) Register", + "line_range": [ + 1236, + 1238 + ] + }, + { + "text": ".Virtual supervisor address translation and protection `vsatp` register when VSXLEN=64. include::images/bytefield/rv64vsatpreg.edn[]", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Address Translation and Protection (`vsatp`) Register", + "line_range": [ + 1240, + 1242 + ] + }, + { + "text": "The `vsatp` register is considered active for the purposes of the address-translation algorithm unless the effective privilege mode is U and `hstatus`.HU=0.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Address Translation and Protection (`vsatp`) Register", + "line_range": [ + 1244, + 1248 + ] + }, + { + "text": "However, even when `vsatp` is active, VS-stage page-table entries’ A bits must not be set as a result of speculative execution, unless the effective privilege mode is VS or VU.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Address Translation and Protection (`vsatp`) Register", + "line_range": [ + 1244, + 1248 + ] + }, + { + "text": "When V=0, a write to `vsatp` with an unsupported MODE value is either ignored as it is for `satp`, or the fields of `vsatp` are treated as *WARL* in the normal way.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Address Translation and Protection (`vsatp`) Register", + "line_range": [ + 1250, + 1253 + ] + }, + { + "text": "However, when V=1, a write to `satp` with an unsupported MODE value is ignored and no write to `vsatp` is effected.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Address Translation and Protection (`vsatp`) Register", + "line_range": [ + 1250, + 1253 + ] + }, + { + "text": "When V=0, `vsatp` does not directly affect the behavior of the machine, unless a virtual-machine load/store (HLV, HLVX, or HSV) or the MPRV feature in the `mstatus` register is used to execute a load or store as though V=1.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Address Translation and Protection (`vsatp`) Register", + "line_range": [ + 1255, + 1259 + ] + }, + { + "text": "The `vstimecmp` CSR is a 64-bit register and has 64-bit precision on all RV32 and RV64 systems.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Timer (`vstimecmp`) Register", + "line_range": [ + 1264, + 1267 + ] + }, + { + "text": "In RV32 only, accesses to the `vstimecmp` CSR access the low 32 bits, while accesses to the `vstimecmph` CSR access the high 32 bits of `vstimecmp`.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Timer (`vstimecmp`) Register", + "line_range": [ + 1264, + 1267 + ] + }, + { + "text": "A virtual supervisor timer interrupt becomes pending, as reflected in the VSTIP bit in the `hip` register, whenever (`time` + `htimedelta`), truncated to 64 bits, contains a value greater than or equal to `vstimecmp`, treating the values as unsigned integers.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Timer (`vstimecmp`) Register", + "line_range": [ + 1269, + 1278 + ] + }, + { + "text": "If the result of this comparison changes, it is guaranteed to be reflected in VSTIP eventually, but not necessarily immediately.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Timer (`vstimecmp`) Register", + "line_range": [ + 1269, + 1278 + ] + }, + { + "text": "The interrupt remains posted until `vstimecmp` becomes greater than (`time` + `htimedelta`), typically as a result of writing `vstimecmp`.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Timer (`vstimecmp`) Register", + "line_range": [ + 1269, + 1278 + ] + }, + { + "text": "The interrupt will be taken based on the standard interrupt enable and delegation rules while V=1.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor and Virtual Supervisor CSRs > Virtual Supervisor Timer (`vstimecmp`) Register", + "line_range": [ + 1269, + 1278 + ] + }, + { + "text": "The hypervisor extension adds virtual-machine load and store instructions and two privileged fence instructions.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions", + "line_range": [ + 1282, + 1283 + ] + }, + { + "text": "The hypervisor virtual-machine load and store instructions are valid only in M-mode or HS-mode, or in U-mode when `hstatus`.HU=1.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Virtual-Machine Load and Store Instructions", + "line_range": [ + 1289, + 1302 + ] + }, + { + "text": "Each instruction performs an explicit memory access with an effective privilege mode of VS or VU.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Virtual-Machine Load and Store Instructions", + "line_range": [ + 1289, + 1302 + ] + }, + { + "text": "The effective privilege mode of the explicit memory access is VU when `hstatus`.SPVP=0, and VS when `hstatus`.SPVP=1.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Virtual-Machine Load and Store Instructions", + "line_range": [ + 1289, + 1302 + ] + }, + { + "text": "As usual for VS-mode and VU-mode, two-stage address translation is applied, and the HS-level `sstatus`.SUM is ignored. HS-level `sstatus`.MXR makes execute-only pages readable by explicit loads for both stages of address translation (VS-stage and G-stage), whereas `vsstatus`.MXR affects only the first translation stage (VS-stage).", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Virtual-Machine Load and Store Instructions", + "line_range": [ + 1289, + 1302 + ] + }, + { + "text": "For every RV32I or RV64I load instruction, LB, LBU, LH, LHU, LW, LWU, and LD, there is a corresponding virtual-machine load instruction: HLV.B, HLV.BU, HLV.H, HLV.HU, HLV.W, HLV.WU, and HLV.D.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Virtual-Machine Load and Store Instructions", + "line_range": [ + 1304, + 1310 + ] + }, + { + "text": "For every RV32I or RV64I store instruction, SB, SH, SW, and SD, there is a corresponding virtual-machine store instruction: HSV.B, HSV.H, HSV.W, and HSV.D.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Virtual-Machine Load and Store Instructions", + "line_range": [ + 1304, + 1310 + ] + }, + { + "text": "Instructions HLV.WU, HLV.D, and HSV.D are not valid for RV32, of course.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Virtual-Machine Load and Store Instructions", + "line_range": [ + 1304, + 1310 + ] + }, + { + "text": "Instructions HLVX.HU and HLVX.WU are the same as HLV.HU and HLV.WU, except that execute permission takes the place of read permission during address translation.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Virtual-Machine Load and Store Instructions", + "line_range": [ + 1312, + 1322 + ] + }, + { + "text": "That is, the memory being read must be executable in both stages of address translation, but read permission is not required.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Virtual-Machine Load and Store Instructions", + "line_range": [ + 1312, + 1322 + ] + }, + { + "text": "For the supervisor physical address that results from address translation, the supervisor physical memory attributes must grant both execute and read permissions. (The supervisor physical memory attributes are the machine’s physical memory attributes as modified by physical memory protection, , for supervisor level.)", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Virtual-Machine Load and Store Instructions", + "line_range": [ + 1312, + 1322 + ] + }, + { + "text": "HLVX.WU is valid for RV32, even though LWU and HLV.WU are not. (For RV32, HLVX.WU can be considered a variant of HLV.W, as sign extension is irrelevant for 32-bit values.)", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Virtual-Machine Load and Store Instructions", + "line_range": [ + 1324, + 1327 + ] + }, + { + "text": "The memory accesses performed by the `HLVX.*` instructions are not subject to pointer masking (see ).", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Virtual-Machine Load and Store Instructions", + "line_range": [ + 1329, + 1330 + ] + }, + { + "text": "Attempts to execute a virtual-machine load/store instruction (HLV, HLVX, or HSV) when V=1 cause a virtual-instruction exception.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Virtual-Machine Load and Store Instructions", + "line_range": [ + 1332, + 1335 + ] + }, + { + "text": "Attempts to execute one of these same instructions from U-mode when `hstatus`.HU=0 cause an illegal-instruction exception.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Virtual-Machine Load and Store Instructions", + "line_range": [ + 1332, + 1335 + ] + }, + { + "text": "The hypervisor memory-management fence instructions, HFENCE.VVMA and HFENCE.GVMA, perform a function similar to SFENCE.VMA (), except applying to the VS-level memory-management data structures controlled by CSR `vsatp` (HFENCE.VVMA) or the guest-physical memory-management data structures controlled by CSR `hgatp` (HFENCE.GVMA).", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Memory-Management Fence Instructions", + "line_range": [ + 1342, + 1350 + ] + }, + { + "text": "Instruction SFENCE.VMA applies only to the memory-management data structures controlled by the current `satp` (either the HS-level `satp` when V=0 or `vsatp` when V=1).", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Memory-Management Fence Instructions", + "line_range": [ + 1342, + 1350 + ] + }, + { + "text": "HFENCE.VVMA is valid only in M-mode or HS-mode.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Memory-Management Fence Instructions", + "line_range": [ + 1352, + 1357 + ] + }, + { + "text": "Its effect is much the same as temporarily entering VS-mode and executing SFENCE.VMA.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Memory-Management Fence Instructions", + "line_range": [ + 1352, + 1357 + ] + }, + { + "text": "Executing an HFENCE.VVMA guarantees that any previous stores already visible to the current hart are ordered before all implicit reads by that hart done for VS-stage address translation for instructions that", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Memory-Management Fence Instructions", + "line_range": [ + 1352, + 1357 + ] + }, + { + "text": "are subsequent to the HFENCE.VVMA, and * execute when `hgatp`.VMID has the same setting as it did when HFENCE.VVMA executed.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Memory-Management Fence Instructions", + "line_range": [ + 1359, + 1361 + ] + }, + { + "text": "Implicit reads need not be ordered when `hgatp`.VMID is different than at the time HFENCE.VVMA executed.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Memory-Management Fence Instructions", + "line_range": [ + 1363, + 1365 + ] + }, + { + "text": "If operand rs1!=`x0`, it specifies a single guest virtual address, and if operand rs2!=`x0`, it specifies a single guest address-space identifier (ASID).", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Memory-Management Fence Instructions", + "line_range": [ + 1363, + 1365 + ] + }, + { + "text": "When rs2!=`x0`, bits XLEN-1:ASIDMAX of the value held in rs2 are reserved for future standard use.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Memory-Management Fence Instructions", + "line_range": [ + 1367, + 1373 + ] + }, + { + "text": "Until their use is defined by a standard extension, they should be zeroed by software and ignored by current implementations.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Memory-Management Fence Instructions", + "line_range": [ + 1367, + 1373 + ] + }, + { + "text": "Furthermore, if ASIDLEN < ASIDMAX, the implementation shall ignore bits ASIDMAX-1:ASIDLEN of the value held in rs2.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Memory-Management Fence Instructions", + "line_range": [ + 1367, + 1373 + ] + }, + { + "text": "Neither `mstatus`.TVM nor `hstatus`.VTVM causes HFENCE.VVMA to trap.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Memory-Management Fence Instructions", + "line_range": [ + 1375, + 1376 + ] + }, + { + "text": "HFENCE.GVMA is valid only in HS-mode when `mstatus`.TVM=0, or in M-mode (irrespective of `mstatus`.TVM).", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Memory-Management Fence Instructions", + "line_range": [ + 1378, + 1387 + ] + }, + { + "text": "Executing an HFENCE.GVMA instruction guarantees that any previous stores already visible to the current hart are ordered before all implicit reads by that hart done for G-stage address translation for instructions that follow the HFENCE.GVMA.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Memory-Management Fence Instructions", + "line_range": [ + 1378, + 1387 + ] + }, + { + "text": "If operand rs1!=`x0`, it specifies a single guest physical address, shifted right by 2 bits, and if operand rs2!=`x0`, it specifies a single virtual machine identifier (VMID).", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Memory-Management Fence Instructions", + "line_range": [ + 1378, + 1387 + ] + }, + { + "text": "When rs2!=`x0`, bits XLEN-1:VMIDMAX of the value held in rs2 are reserved for future standard use.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Memory-Management Fence Instructions", + "line_range": [ + 1389, + 1395 + ] + }, + { + "text": "Until their use is defined by a standard extension, they should be zeroed by software and ignored by current implementations.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Memory-Management Fence Instructions", + "line_range": [ + 1389, + 1395 + ] + }, + { + "text": "Furthermore, if VMIDLEN < VMIDMAX, the implementation shall ignore bits VMIDMAX-1:VMIDLEN of the value held in rs2.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Memory-Management Fence Instructions", + "line_range": [ + 1389, + 1395 + ] + }, + { + "text": "If `hgatp`.MODE is changed for a given VMID, an HFENCE.GVMA with rs1=`x0` (and rs2 set to either `x0` or the VMID) must be executed to order subsequent guest translations with the MODE change—even if the old MODE or new MODE is Bare.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Memory-Management Fence Instructions", + "line_range": [ + 1397, + 1401 + ] + }, + { + "text": "Attempts to execute HFENCE.VVMA or HFENCE.GVMA when V=1 cause a virtual-instruction exception, while attempts to do the same in U-mode cause an illegal-instruction exception.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Memory-Management Fence Instructions", + "line_range": [ + 1403, + 1407 + ] + }, + { + "text": "Attempting to execute HFENCE.GVMA in HS-mode when `mstatus`.TVM=1 also causes an illegal-instruction exception.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Hypervisor Instructions > Hypervisor Memory-Management Fence Instructions", + "line_range": [ + 1403, + 1407 + ] + }, + { + "text": "The hypervisor extension augments or modifies machine CSRs `mstatus`, `mstatush`, `mideleg`, `mip`, and `mie`, and adds CSRs `mtval2` and `mtinst`.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs", + "line_range": [ + 1411, + 1413 + ] + }, + { + "text": "The hypervisor extension adds two fields, MPV and GVA, to the machine-level `mstatus` or `mstatush` CSR, and modifies the behavior of several existing `mstatus` fields. shows the modified `mstatus` register when the hypervisor extension is implemented and MXLEN=64.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers", + "line_range": [ + 1417, + 1426 + ] + }, + { + "text": "When MXLEN=32, the hypervisor extension adds MPV and GVA not to `mstatus` but to `mstatush`. shows the `mstatush` register when the hypervisor extension is implemented and MXLEN=32.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers", + "line_range": [ + 1417, + 1426 + ] + }, + { + "text": ".Machine status (`mstatus`) register for RV64 when the hypervisor extension is implemented. include::images/bytefield/hypv-mstatus.edn[]", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers", + "line_range": [ + 1428, + 1430 + ] + }, + { + "text": ".Additional machine status (`mstatush`) register for RV32 when the hypervisor extension is implemented.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers", + "line_range": [ + 1432, + 1434 + ] + }, + { + "text": "The format of `mstatus` is unchanged for RV32. include::images/bytefield/hypv-mstatush.edn[]", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers", + "line_range": [ + 1432, + 1434 + ] + }, + { + "text": "The MPV bit (Machine Previous Virtualization Mode) is written by the implementation whenever a trap is taken into M-mode.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers", + "line_range": [ + 1436, + 1442 + ] + }, + { + "text": "Just as the MPP field is set to the (nominal) privilege mode at the time of the trap, the MPV bit is set to the value of the virtualization mode V at the time of the trap.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers", + "line_range": [ + 1436, + 1442 + ] + }, + { + "text": "When an MRET instruction is executed, the virtualization mode V is set to MPV, unless MPP=3, in which case V remains 0.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers", + "line_range": [ + 1436, + 1442 + ] + }, + { + "text": "Field GVA (Guest Virtual Address) is written by the implementation whenever a trap is taken into M-mode.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers", + "line_range": [ + 1444, + 1449 + ] + }, + { + "text": "For any trap (breakpoint, address misaligned, access fault, page fault, or guest-page fault) that writes a guest virtual address to `mtval`, GVA is set to 1.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers", + "line_range": [ + 1444, + 1449 + ] + }, + { + "text": "For any other trap into M-mode, GVA is set to 0.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers", + "line_range": [ + 1444, + 1449 + ] + }, + { + "text": "The TSR and TVM fields of `mstatus` affect execution only in HS-mode, not in VS-mode.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers", + "line_range": [ + 1451, + 1454 + ] + }, + { + "text": "The TW field affects execution in all modes except M-mode.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers", + "line_range": [ + 1451, + 1454 + ] + }, + { + "text": "Setting TVM=1 prevents HS-mode from accessing `hgatp` or executing HFENCE.GVMA or HINVAL.GVMA, but has no effect on accesses to `vsatp` or instructions HFENCE.VVMA or HINVAL.VVMA.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers", + "line_range": [ + 1456, + 1459 + ] + }, + { + "text": "The hypervisor extension changes the behavior of the Modify Privilege field, MPRV, of `mstatus`.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers", + "line_range": [ + 1461, + 1467 + ] + }, + { + "text": "When MPRV=0, translation and protection behave as normal.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers", + "line_range": [ + 1461, + 1467 + ] + }, + { + "text": "When MPRV=1, explicit memory accesses are translated and protected, and endianness is applied, as though the current virtualization mode were set to MPV and the current nominal privilege mode were set to MPP. enumerates the cases.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers", + "line_range": [ + 1461, + 1467 + ] + }, + { + "text": ".Effect of MPRV on the translation and protection of explicit memory accesses. [float=\"center\",align=\"center\",cols=\"^15,^10,^10,<70\",options=\"header\"] | |MPRV |MPV |MPP |Effect |0 |- |- |Normal access; current privilege mode applies.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers", + "line_range": [ + 1469, + 1474 + ] + }, + { + "text": "|1 |0 |0 |U-level access with HS-level translation and protection only.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers", + "line_range": [ + 1476, + 1476 + ] + }, + { + "text": "|1 |0 |1 |HS-level access with HS-level translation and protection only.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers", + "line_range": [ + 1478, + 1478 + ] + }, + { + "text": "|1 |- |3 |M-level access with no translation.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers", + "line_range": [ + 1480, + 1480 + ] + }, + { + "text": "|1 |1 |0 |VU-level access with two-stage translation and protection.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers", + "line_range": [ + 1482, + 1485 + ] + }, + { + "text": "The HS-level MXR bit makes any executable page readable. `vsstatus`.MXR makes readable those pages marked executable at the VS translation stage, but only if readable at the guest-physical translation stage.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers", + "line_range": [ + 1482, + 1485 + ] + }, + { + "text": "|1 |1 |1 |VS-level access with two-stage translation and protection.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers", + "line_range": [ + 1487, + 1492 + ] + }, + { + "text": "The HS-level MXR bit makes any executable page readable. `vsstatus`.MXR makes readable those pages marked executable at the VS translation stage, but only if readable at the guest-physical translation stage. `vsstatus`.SUM applies instead of the HS-level SUM bit. |", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers", + "line_range": [ + 1487, + 1492 + ] + }, + { + "text": "MPRV does not affect the virtual-machine load/store instructions, HLV, HLVX, and HSV.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers", + "line_range": [ + 1494, + 1498 + ] + }, + { + "text": "The explicit loads and stores of these instructions always act as though V=1 and the nominal privilege mode were `hstatus`.SPVP, overriding MPRV.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers", + "line_range": [ + 1494, + 1498 + ] + }, + { + "text": "The `mstatus` register is a superset of the HS-level `sstatus` register but is not a superset of `vsstatus`.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers", + "line_range": [ + 1500, + 1501 + ] + }, + { + "text": "When the hypervisor extension is implemented, bits 10, 6, and 2 of `mideleg` (corresponding to the standard VS-level interrupts) are each read-only one.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Interrupt Delegation (`mideleg`) Register", + "line_range": [ + 1505, + 1512 + ] + }, + { + "text": "Furthermore, if any guest external interrupts are implemented (GEILEN is nonzero), bit 12 of `mideleg` (corresponding to supervisor-level guest external interrupts) is also read-only one. VS-level interrupts and guest external interrupts are always delegated past M-mode to HS-mode.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Interrupt Delegation (`mideleg`) Register", + "line_range": [ + 1505, + 1512 + ] + }, + { + "text": "For bits of `mideleg` that are zero, the corresponding bits in `hideleg`, `hip`, and `hie` are read-only zeros.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Interrupt Delegation (`mideleg`) Register", + "line_range": [ + 1514, + 1516 + ] + }, + { + "text": "The hypervisor extension gives registers `mip` and `mie` additional active bits for the hypervisor-added interrupts. and show the standard portions (bits 15:0) of registers `mip` and `mie` when the hypervisor extension is implemented.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "line_range": [ + 1520, + 1524 + ] + }, + { + "text": ".Standard portion (bits 15:0) of `mip`. include::images/bytefield/hypv-mipreg-standard.edn[]", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "line_range": [ + 1526, + 1528 + ] + }, + { + "text": ".Standard portion (bits 15:0) of `mie`. include::images/bytefield/hypv-miereg-standard.edn[]", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "line_range": [ + 1530, + 1532 + ] + }, + { + "text": "Bits SGEIP, VSEIP, VSTIP, and VSSIP in `mip` are aliases for the same bits in hypervisor CSR `hip`, while SGEIE, VSEIE, VSTIE, and VSSIE in `mie` are aliases for the same bits in `hie`.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "line_range": [ + 1534, + 1537 + ] + }, + { + "text": "The `mtval2` register is an MXLEN-bit read/write register formatted as shown in .", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Second Trap Value (`mtval2`) Register", + "line_range": [ + 1541, + 1545 + ] + }, + { + "text": "When a trap is taken into M-mode, `mtval2` is written with additional exception-specific information, alongside `mtval`, to assist software in handling the trap.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Second Trap Value (`mtval2`) Register", + "line_range": [ + 1541, + 1545 + ] + }, + { + "text": ".Machine second trap value register (`mtval2`). include::images/bytefield/mtval2reg.edn[]", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Second Trap Value (`mtval2`) Register", + "line_range": [ + 1547, + 1549 + ] + }, + { + "text": "When a guest-page-fault trap is taken into M-mode, `mtval2` is written with either zero or the guest physical address that faulted, shifted right by 2 bits.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Second Trap Value (`mtval2`) Register", + "line_range": [ + 1551, + 1555 + ] + }, + { + "text": "For other traps, `mtval2` is set to zero, but a future standard or extension may redefine `mtval2's` setting for other traps.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Second Trap Value (`mtval2`) Register", + "line_range": [ + 1551, + 1555 + ] + }, + { + "text": "If a guest-page fault is due to an implicit memory access during first-stage (VS-stage) address translation, a guest physical address written to `mtval2` is that of the implicit memory access that faulted.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Second Trap Value (`mtval2`) Register", + "line_range": [ + 1557, + 1562 + ] + }, + { + "text": "Additional information is provided in CSR `mtinst` to disambiguate such situations.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Second Trap Value (`mtval2`) Register", + "line_range": [ + 1557, + 1562 + ] + }, + { + "text": "Otherwise, for misaligned loads and stores that cause guest-page faults, a nonzero guest physical address in `mtval2` corresponds to the faulting portion of the access as indicated by the virtual address in `mtval`.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Second Trap Value (`mtval2`) Register", + "line_range": [ + 1564, + 1570 + ] + }, + { + "text": "For instruction guest-page faults on systems with variable-length instructions, a nonzero `mtval2` corresponds to the faulting portion of the instruction as indicated by the virtual address in `mtval`.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Second Trap Value (`mtval2`) Register", + "line_range": [ + 1564, + 1570 + ] + }, + { + "text": "`mtval2` is a *WARL* register that must be able to hold zero and may be capable of holding only an arbitrary subset of other 2-bit-shifted guest physical addresses, if any.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Second Trap Value (`mtval2`) Register", + "line_range": [ + 1572, + 1575 + ] + }, + { + "text": "The Ssdbltrap extension (See ) requires the implementation of the `mtval2` CSR.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Second Trap Value (`mtval2`) Register", + "line_range": [ + 1577, + 1579 + ] + }, + { + "text": "The `mtinst` register is an MXLEN-bit read/write register formatted as shown in .", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Trap Instruction (`mtinst`) Register", + "line_range": [ + 1584, + 1590 + ] + }, + { + "text": "When a trap is taken into M-mode, `mtinst` is written with a value that, if nonzero, provides information about the instruction that trapped, to assist software in handling the trap.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Trap Instruction (`mtinst`) Register", + "line_range": [ + 1584, + 1590 + ] + }, + { + "text": "The values that may be written to `mtinst` on a trap are documented in .", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Trap Instruction (`mtinst`) Register", + "line_range": [ + 1584, + 1590 + ] + }, + { + "text": ".Machine trap instruction (`mtinst`) register. include::images/bytefield/mtinstreg.edn[]", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Trap Instruction (`mtinst`) Register", + "line_range": [ + 1592, + 1594 + ] + }, + { + "text": "`mtinst` is a *WARL* register that need only be able to hold the values that the implementation may automatically write to it on a trap.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Machine-Level CSRs > Machine Trap Instruction (`mtinst`) Register", + "line_range": [ + 1596, + 1598 + ] + }, + { + "text": "Whenever the current virtualization mode V is 1, two-stage address translation and protection is in effect.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation", + "line_range": [ + 1603, + 1614 + ] + }, + { + "text": "For any virtual memory access, the original virtual address is converted in the first stage by VS-level address translation, as controlled by the `vsatp` register, into a guest physical address.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation", + "line_range": [ + 1603, + 1614 + ] + }, + { + "text": "The guest physical address is then converted in the second stage by guest physical address translation, as controlled by the `hgatp` register, into a supervisor physical address.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation", + "line_range": [ + 1603, + 1614 + ] + }, + { + "text": "The two stages are known also as VS-stage and G-stage translation.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation", + "line_range": [ + 1603, + 1614 + ] + }, + { + "text": "Although there is no option to disable two-stage address translation when V=1, either stage of translation can be effectively disabled by zeroing the corresponding `vsatp` or `hgatp` register.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation", + "line_range": [ + 1603, + 1614 + ] + }, + { + "text": "The `vsstatus` field MXR, which makes execute-only pages readable by explicit loads, only overrides VS-stage page protection.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation", + "line_range": [ + 1616, + 1620 + ] + }, + { + "text": "Setting MXR at VS-level does not override guest-physical page protections.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation", + "line_range": [ + 1616, + 1620 + ] + }, + { + "text": "Setting MXR at HS-level, however, overrides both VS-stage and G-stage execute-only permissions.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation", + "line_range": [ + 1616, + 1620 + ] + }, + { + "text": "When V=1, memory accesses that would normally bypass address translation are subject to G-stage address translation alone.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation", + "line_range": [ + 1622, + 1626 + ] + }, + { + "text": "This includes memory accesses made in support of VS-stage address translation, such as reads and writes of VS-level page tables.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation", + "line_range": [ + 1622, + 1626 + ] + }, + { + "text": "Machine-level physical memory protection applies to supervisor physical addresses and is in effect regardless of virtualization mode.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation", + "line_range": [ + 1628, + 1630 + ] + }, + { + "text": "The mapping of guest physical addresses to supervisor physical addresses is controlled by CSR `hgatp` ().", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest Physical Address Translation", + "line_range": [ + 1635, + 1636 + ] + }, + { + "text": "When the address translation scheme selected by the MODE field of `hgatp` is Bare, guest physical addresses are equal to supervisor physical addresses without modification, and no memory protection applies in the trivial translation of guest physical addresses to supervisor physical addresses.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest Physical Address Translation", + "line_range": [ + 1638, + 1643 + ] + }, + { + "text": "When `hgatp`.MODE specifies a translation scheme of Sv32x4, Sv39x4, Sv48x4, or Sv57x4, G-stage address translation is a variation on the usual page-based virtual address translation scheme of Sv32, Sv39, Sv48, or Sv57, respectively.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest Physical Address Translation", + "line_range": [ + 1645, + 1657 + ] + }, + { + "text": "In each case, the size of the incoming address is widened by 2 bits (to 34, 41, 50, or 59 bits).", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest Physical Address Translation", + "line_range": [ + 1645, + 1657 + ] + }, + { + "text": "To accommodate the 2 extra bits, the root page table (only) is expanded by a factor of four to be 16 KiB instead of the usual 4 KiB.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest Physical Address Translation", + "line_range": [ + 1645, + 1657 + ] + }, + { + "text": "Matching its larger size, the root page table also must be aligned to a 16 KiB boundary instead of the usual 4 KiB page boundary.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest Physical Address Translation", + "line_range": [ + 1645, + 1657 + ] + }, + { + "text": "Except as noted, all other aspects of Sv32, Sv39, Sv48, or Sv57 are adopted unchanged for G-stage translation.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest Physical Address Translation", + "line_range": [ + 1645, + 1657 + ] + }, + { + "text": "Non-root page tables and all page table entries (PTEs) have the same formats as documented in , , , and .", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest Physical Address Translation", + "line_range": [ + 1645, + 1657 + ] + }, + { + "text": "For Sv32x4, an incoming guest physical address is partitioned into a virtual page number (VPN) and page offset as shown in .", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest Physical Address Translation", + "line_range": [ + 1659, + 1668 + ] + }, + { + "text": "This partitioning is identical to that for an Sv32 virtual address as depicted in , except with 2 more bits at the high end in VPN[1]. (Note that the fields of a partitioned guest physical address also correspond one-for-one with the structure that Sv32 assigns to a physical address, depicted in .)", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest Physical Address Translation", + "line_range": [ + 1659, + 1668 + ] + }, + { + "text": ".Sv32x4 virtual address (guest physical address). include::images/bytefield/sv32x4va.edn[]", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest Physical Address Translation", + "line_range": [ + 1670, + 1672 + ] + }, + { + "text": "For Sv39x4, an incoming guest physical address is partitioned as shown in .", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest Physical Address Translation", + "line_range": [ + 1674, + 1678 + ] + }, + { + "text": "This partitioning is identical to that for an Sv39 virtual address as depicted in , except with 2 more bits at the high end in VPN[2].", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest Physical Address Translation", + "line_range": [ + 1674, + 1678 + ] + }, + { + "text": "Address bits 63:41 must all be zeros, or else a guest-page-fault exception occurs.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest Physical Address Translation", + "line_range": [ + 1674, + 1678 + ] + }, + { + "text": ".Sv39x4 virtual address (guest physical address). include::images/bytefield/sv39x4va.edn[]", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest Physical Address Translation", + "line_range": [ + 1680, + 1682 + ] + }, + { + "text": "For Sv48x4, an incoming guest physical address is partitioned as shown in .", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest Physical Address Translation", + "line_range": [ + 1684, + 1690 + ] + }, + { + "text": "This partitioning is identical to that for an Sv48 virtual address as depicted in , except with 2 more bits at the high end in VPN[3].", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest Physical Address Translation", + "line_range": [ + 1684, + 1690 + ] + }, + { + "text": "Address bits 63:50 must all be zeros, or else a guest-page-fault exception occurs.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest Physical Address Translation", + "line_range": [ + 1684, + 1690 + ] + }, + { + "text": ".Sv48x4 virtual address (guest physical address). include::images/bytefield/sv48x4va.edn[]", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest Physical Address Translation", + "line_range": [ + 1692, + 1694 + ] + }, + { + "text": "For Sv57x4, an incoming guest physical address is partitioned as shown in .", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest Physical Address Translation", + "line_range": [ + 1696, + 1702 + ] + }, + { + "text": "This partitioning is identical to that for an Sv57 virtual address as depicted in , except with 2 more bits at the high end in VPN[4].", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest Physical Address Translation", + "line_range": [ + 1696, + 1702 + ] + }, + { + "text": "Address bits 63:59 must all be zeros, or else a guest-page-fault exception occurs.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest Physical Address Translation", + "line_range": [ + 1696, + 1702 + ] + }, + { + "text": ".Sv57x4 virtual address (guest physical address). include::images/bytefield/sv57x4va.edn[]", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest Physical Address Translation", + "line_range": [ + 1704, + 1706 + ] + }, + { + "text": "The conversion of an Sv32x4, Sv39x4, Sv48x4, or Sv57x4 guest physical address is accomplished with the same algorithm used for Sv32, Sv39, Sv48, or Sv57, as presented in , except that:", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest Physical Address Translation", + "line_range": [ + 1708, + 1712 + ] + }, + { + "text": "`hgatp` substitutes for the usual `satp`; * for the translation to begin, the effective privilege mode must be VS-mode or VU-mode; * when checking the U bit, the current privilege mode is always taken to be U-mode; and * guest-page-fault exceptions are raised instead of regular page-fault exceptions.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest Physical Address Translation", + "line_range": [ + 1714, + 1720 + ] + }, + { + "text": "For G-stage address translation, all memory accesses (including those made to access data structures for VS-stage address translation) are considered to be user-level accesses, as though executed in U-mode.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest Physical Address Translation", + "line_range": [ + 1722, + 1733 + ] + }, + { + "text": "Access type permissions—readable, writable, or executable—are checked during G-stage translation the same as for VS-stage translation.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest Physical Address Translation", + "line_range": [ + 1722, + 1733 + ] + }, + { + "text": "For a memory access made to support VS-stage address translation (such as to read/write a VS-level page table), permissions and the need to set A and/or D bits at the G-stage level are checked as though for an implicit load or store, not for the original access type.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest Physical Address Translation", + "line_range": [ + 1722, + 1733 + ] + }, + { + "text": "However, any exception is always reported for the original access type (instruction, load, or store/AMO).", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest Physical Address Translation", + "line_range": [ + 1722, + 1733 + ] + }, + { + "text": "The G bit in all G-stage PTEs is currently not used.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest Physical Address Translation", + "line_range": [ + 1735, + 1738 + ] + }, + { + "text": "Until its use is defined by a standard extension, it should be cleared by software for forward compatibility, and must be ignored by hardware.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest Physical Address Translation", + "line_range": [ + 1735, + 1738 + ] + }, + { + "text": "Guest-page-fault traps may be delegated from M-mode to HS-mode under the control of CSR `medeleg`, but cannot be delegated to other privilege modes.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest-Page Faults", + "line_range": [ + 1742, + 1750 + ] + }, + { + "text": "On a guest-page fault, CSR `mtval` or `stval` is written with the faulting guest virtual address as usual, and `mtval2` or `htval` is written either with zero or with the faulting guest physical address, shifted right by 2 bits. CSR `mtinst` or `htinst` may also be written with information about the faulting instruction or other reason for the access, as explained in .", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest-Page Faults", + "line_range": [ + 1742, + 1750 + ] + }, + { + "text": "When an instruction fetch or a misaligned memory access straddles a page boundary, two different address translations are involved.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest-Page Faults", + "line_range": [ + 1752, + 1760 + ] + }, + { + "text": "When a guest-page fault occurs in such a circumstance, the faulting virtual address written to `mtval`/`stval` is the same as would be required for a regular page fault.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest-Page Faults", + "line_range": [ + 1752, + 1760 + ] + }, + { + "text": "Thus, the faulting virtual address may be a page-boundary address that is higher than the instruction's original virtual address, if the byte at that page boundary is among the accessed bytes.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest-Page Faults", + "line_range": [ + 1752, + 1760 + ] + }, + { + "text": "When a guest-page fault is not due to an implicit memory access for VS-stage address translation, a nonzero guest physical address written to `mtval2`/`htval` shall correspond to the exact virtual address written to `mtval`/`stval`.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Guest-Page Faults", + "line_range": [ + 1762, + 1766 + ] + }, + { + "text": "The behavior of the SFENCE.VMA instruction is affected by the current virtualization mode V.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Memory-Management Fences", + "line_range": [ + 1771, + 1776 + ] + }, + { + "text": "When V=0, the virtual-address argument is an HS-level virtual address, and the ASID argument is an HS-level ASID.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Memory-Management Fences", + "line_range": [ + 1771, + 1776 + ] + }, + { + "text": "The instruction orders stores only to HS-level address-translation structures with subsequent HS-level address translations.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Memory-Management Fences", + "line_range": [ + 1771, + 1776 + ] + }, + { + "text": "When V=1, the virtual-address argument to SFENCE.VMA is a guest virtual address within the current virtual machine, and the ASID argument is a VS-level ASID within the current virtual machine.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Memory-Management Fences", + "line_range": [ + 1778, + 1787 + ] + }, + { + "text": "The current virtual machine is identified by the VMID field of CSR `hgatp`, and the effective ASID can be considered to be the combination of this VMID with the VS-level ASID.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Memory-Management Fences", + "line_range": [ + 1778, + 1787 + ] + }, + { + "text": "The SFENCE.VMA instruction orders stores only to the VS-level address-translation structures with subsequent VS-stage address translations for the same virtual machine, i.e., only when `hgatp`.VMID is the same as when the SFENCE.VMA executed.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Memory-Management Fences", + "line_range": [ + 1778, + 1787 + ] + }, + { + "text": "Hypervisor instructions HFENCE.VVMA and HFENCE.GVMA provide additional memory-management fences to complement SFENCE.VMA.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Memory-Management Fences", + "line_range": [ + 1789, + 1791 + ] + }, + { + "text": "These instructions are described in .", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Memory-Management Fences", + "line_range": [ + 1789, + 1791 + ] + }, + { + "text": "discusses the intersection between physical memory protection (PMP) and page-based address translation.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Memory-Management Fences", + "line_range": [ + 1793, + 1806 + ] + }, + { + "text": "It is noted there that, when PMP settings are modified in a manner that affects either the physical memory that holds page tables or the physical memory to which page tables point, M-mode software must synchronize the PMP settings with the virtual memory system.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Memory-Management Fences", + "line_range": [ + 1793, + 1806 + ] + }, + { + "text": "For HS-level address translation, this is accomplished by executing in M-mode an SFENCE.VMA instruction with rs1=`x0` and rs2=`x0`, after the PMP CSRs are written.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Memory-Management Fences", + "line_range": [ + 1793, + 1806 + ] + }, + { + "text": "Synchronization with G-stage and VS-stage data structures is also needed.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Memory-Management Fences", + "line_range": [ + 1793, + 1806 + ] + }, + { + "text": "Executing an HFENCE.GVMA instruction with rs1=`x0` and rs2=`x0` suffices to flush all G-stage or VS-stage address-translation cache entries that have cached PMP settings corresponding to the final translated supervisor physical address.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Memory-Management Fences", + "line_range": [ + 1793, + 1806 + ] + }, + { + "text": "An HFENCE.VVMA instruction is not required.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Memory-Management Fences", + "line_range": [ + 1793, + 1806 + ] + }, + { + "text": "Similarly, if the setting of the PBMTE or ADUE bits in `menvcfg` are changed, an HFENCE.GVMA instruction with rs1=`x0` and rs2=`x0` suffices to synchronize with respect to the altered interpretation of G-stage and VS-stage PTEs' PBMT and A/D bit fields, respectively.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Memory-Management Fences", + "line_range": [ + 1808, + 1811 + ] + }, + { + "text": "By contrast, if the PBMTE or ADUE bits in `henvcfg` are changed, executing an HFENCE.VVMA with rs1=`x0` and rs2=`x0` suffices to synchronize with respect to the altered interpretation of VS-stage PTEs' PBMT and A/D bit fields for the currently active VMID.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Memory-Management Fences", + "line_range": [ + 1813, + 1816 + ] + }, + { + "text": "NOTE: No mechanism is provided to atomically change `vsatp` and `hgatp` together.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Memory-Management Fences", + "line_range": [ + 1818, + 1824 + ] + }, + { + "text": "Hence, to prevent speculative execution causing one guest's VS-stage translations to be cached under another guest's VMID, world-switch code should zero `vsatp`, then swap `hgatp`, then finally write the new `vsatp` value.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Memory-Management Fences", + "line_range": [ + 1818, + 1824 + ] + }, + { + "text": "Similarly, if `henvcfg`.PBMTE/ADUE need be world-switched, they should be switched after zeroing `vsatp` but before writing the new `vsatp` value, obviating the need to execute an HFENCE.VVMA instruction.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Memory-Management Fences", + "line_range": [ + 1818, + 1824 + ] + }, + { + "text": "Guest physical addresses (GPAs) are 2 bits wider than the corresponding virtual address translation modes, resulting in additional address translation schemes Sv32x4, Sv39x4, Sv48x4, and Sv57x4 for translating guest physical addresses to supervisor physical addresses.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Interaction with Pointer Masking", + "line_range": [ + 1829, + 1835 + ] + }, + { + "text": "When running with virtualization in VS/VU mode with `vsatp.MODE` = Bare, this means that those two bits may be subject to pointer masking, depending on `hgatp.MODE` and `senvcfg.PMM`/`henvcfg.PMM` (for VU/VS mode).", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Interaction with Pointer Masking", + "line_range": [ + 1829, + 1835 + ] + }, + { + "text": "If `vsatp.MODE` != BARE, this issue does *not* apply.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Interaction with Pointer Masking", + "line_range": [ + 1829, + 1835 + ] + }, + { + "text": "To support implementations where (XLEN-PMLEN) can be less than the GPA width supported by `hgatp.MODE`, hypervisors should execute an `HFENCE.GVMA` with rs1=`x0` if the `henvcfg.PMM` is changed from or to a value where (XLEN-PMLEN) is less than GPA width supported by the `hgatp` translation mode of that guest.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Interaction with Pointer Masking", + "line_range": [ + 1837, + 1841 + ] + }, + { + "text": "Specifically, these cases are:", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Interaction with Pointer Masking", + "line_range": [ + 1837, + 1841 + ] + }, + { + "text": "`PMLEN=7` and `hgatp.MODE=sv57x4` * `PMLEN=16` and `hgatp.MODE=sv57x4` * `PMLEN=16` and `hgatp.MODE=sv48x4`", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Interaction with Pointer Masking", + "line_range": [ + 1843, + 1845 + ] + }, + { + "text": "Implementation of an address-specific `HFENCE.GVMA` should either ignore the address argument, or should ignore the top masked GPA bits of entries when comparing for an address match.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Two-Stage Address Translation > Interaction with Pointer Masking", + "line_range": [ + 1847, + 1849 + ] + }, + { + "text": "The hypervisor extension augments the trap cause encoding. lists the possible M-mode and HS-mode trap cause codes when the hypervisor extension is implemented.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes", + "line_range": [ + 1856, + 1865 + ] + }, + { + "text": "Codes are added for VS-level interrupts (interrupts 2, 6, 10), for supervisor-level guest external interrupts (interrupt 12), for virtual-instruction exceptions (exception 22), and for guest-page faults (exceptions 20, 21, 23).", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes", + "line_range": [ + 1856, + 1865 + ] + }, + { + "text": "Furthermore, environment calls from VS-mode are assigned cause 10, whereas those from HS-mode or S-mode use cause 9 as usual.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes", + "line_range": [ + 1856, + 1865 + ] + }, + { + "text": ".Machine and supervisor cause register (`mcause` and `scause`) values when the hypervisor extension is implemented. | |Interrupt |Exception Code |Description |1 + 1 + 1 + 1 |0 + 1 + 2 + 3 |Reserved + Supervisor software interrupt + Virtual supervisor software interrupt + Machine software interrupt |1 + 1 + 1 + 1 |4 + 5 + 6 + 7 |Reserved + Supervisor timer interrupt + Virtual supervisor timer interrupt + Machine timer interrupt |1 + 1 + 1 + 1 |8 + 9 + 10 + 11 |Reserved + Supervisor external interrupt + Virtual supervisor external interrupt + Machine external interrupt |1 + 1 + 1 + 1 |12 + 13 + 14-15 + {ge}16 |Supervisor guest external interrupt + Counter-overflow interrupt + Reserved + Designated for platform use |0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + |0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 11 + 12 + 13 + 14 + 15 + 16 + 17 + 18 + 19 + 20 + 21 + 22 + 23 + 24-31 + 32-47 + 48-63 + {ge}64 |Instruction address misaligned + Instruction access fault + Illegal instruction + Breakpoint + Load address misaligned + Load access fault + Store/AMO address misaligned + Store/AMO access fault + Environment call from U-mode or VU-mode + Environment call from HS-mode + Environment call from VS-mode + Environment call from M-mode + Instruction page fault + Load page fault + Reserved + Store/AMO page fault + Double trap + Reserved + Software check + Hardware error + Instruction guest-page fault + Load guest-page fault + Virtual instruction + Store/AMO guest-page fault + Designated for custom use + Reserved + Designated for custom use + Reserved |", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes", + "line_range": [ + 1867, + 2004 + ] + }, + { + "text": "HS-mode and VS-mode ECALLs use different cause values so they can be delegated separately.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes", + "line_range": [ + 2006, + 2008 + ] + }, + { + "text": "When V=1, a virtual-instruction exception (code 22) is normally raised instead of an illegal-instruction exception if the attempted instruction is HS-qualified but is prevented from executing when V=1 either due to insufficient privilege or because the instruction is expressly disabled by a supervisor or hypervisor CSR such as `scounteren` or `hcounteren`.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes", + "line_range": [ + 2010, + 2018 + ] + }, + { + "text": "An instruction is HS-qualified if it would be valid to execute in HS-mode (for some values of the instruction's register operands), assuming fields TSR and TVM of CSR `mstatus` are both zero.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes", + "line_range": [ + 2010, + 2018 + ] + }, + { + "text": "A special rule applies for CSR instructions that access 32-bit high-half CSRs such as `cycleh` and `htimedeltah`.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes", + "line_range": [ + 2020, + 2027 + ] + }, + { + "text": "When V=1 and XLEN=32, an invalid attempt to access a high-half CSR raises a virtual-instruction exception instead of an illegal-instruction exception if the same CSR instruction for the corresponding low-half CSR (e.g.`cycle` or `htimedelta`) is HS-qualified.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes", + "line_range": [ + 2020, + 2027 + ] + }, + { + "text": "Specifically, a virtual-instruction exception is raised for the following cases:", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes", + "line_range": [ + 2029, + 2030 + ] + }, + { + "text": "in VS-mode, attempts to access a non-high-half counter CSR when the corresponding bit in `hcounteren` is 0 and the same bit in `mcounteren` is 1;", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes", + "line_range": [ + 2032, + 2034 + ] + }, + { + "text": "in VS-mode, if XLEN=32, attempts to access a high-half counter CSR when the corresponding bit in `hcounteren` is 0 and the same bit in `mcounteren` is 1;", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes", + "line_range": [ + 2036, + 2038 + ] + }, + { + "text": "in VU-mode, attempts to access a non-high-half counter CSR when the corresponding bit in either `hcounteren` or `scounteren` is 0 and the same bit in `mcounteren` is 1;", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes", + "line_range": [ + 2040, + 2042 + ] + }, + { + "text": "in VU-mode, if XLEN=32, attempts to access a high-half counter CSR when the corresponding bit in either `hcounteren` or `scounteren` is 0 and the same bit in `mcounteren` is 1;", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes", + "line_range": [ + 2044, + 2046 + ] + }, + { + "text": "in VS-mode or VU-mode, attempts to execute a hypervisor instruction (HLV, HLVX, HSV, or HFENCE);", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes", + "line_range": [ + 2048, + 2049 + ] + }, + { + "text": "in VS-mode or VU-mode, attempts to access an implemented non-high-half hypervisor CSR or VS CSR when the same access (read/write) would be allowed in HS-mode, assuming `mstatus`.TVM=0;", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes", + "line_range": [ + 2051, + 2053 + ] + }, + { + "text": "in VS-mode or VU-mode, if XLEN=32, attempts to access an implemented high-half hypervisor CSR or high-half VS CSR when the same access (read/write) to the CSR\"s low-half partner would be allowed in HS-mode, assuming `mstatus`.TVM=0;", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes", + "line_range": [ + 2055, + 2058 + ] + }, + { + "text": "in VU-mode, attempts to execute WFI when `mstatus`.TW=0, or to execute a supervisor instruction (SRET or SFENCE);", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes", + "line_range": [ + 2060, + 2062 + ] + }, + { + "text": "in VU-mode, attempts to access an implemented non-high-half supervisor CSR when the same access (read/write) would be allowed in HS-mode, assuming `mstatus`.TVM=0;", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes", + "line_range": [ + 2064, + 2066 + ] + }, + { + "text": "in VU-mode, if XLEN=32, attempts to access an implemented high-half supervisor CSR when the same access to the CSR's low-half partner would be allowed in HS-mode, assuming `mstatus`.TVM=0;", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes", + "line_range": [ + 2068, + 2070 + ] + }, + { + "text": "in VS-mode, attempts to execute WFI when `hstatus`.VTW=1 and `mstatus`.TW=0, unless the instruction completes within an implementation-specific, bounded time;", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes", + "line_range": [ + 2072, + 2074 + ] + }, + { + "text": "in VS-mode, attempts to execute SRET when `hstatus`.VTSR=1; and", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes", + "line_range": [ + 2076, + 2076 + ] + }, + { + "text": "in VS-mode, attempts to execute an SFENCE.VMA or SINVAL.VMA instruction or to access `satp`, when `hstatus`.VTVM=1.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes", + "line_range": [ + 2078, + 2079 + ] + }, + { + "text": "Other extensions to the RISC-V Privileged Architecture may add to the set of circumstances that cause a virtual-instruction exception when V=1.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes", + "line_range": [ + 2081, + 2083 + ] + }, + { + "text": "On a virtual-instruction trap, `mtval` or `stval` is written the same as for an illegal-instruction trap.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes", + "line_range": [ + 2085, + 2087 + ] + }, + { + "text": "Fields FS and VS in registers `sstatus` and `vsstatus` deviate from the usual HS-qualified rule.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes", + "line_range": [ + 2089, + 2094 + ] + }, + { + "text": "If an instruction is prevented from executing because FS or VS is zero in either `sstatus` or `vsstatus`, the exception raised is always an illegal-instruction exception, never a virtual-instruction exception.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes", + "line_range": [ + 2089, + 2094 + ] + }, + { + "text": ".Synchronous exception priority when the hypervisor extension is implemented. | |Priority |Exc.Code |Description |Highest |3 |Instruction address breakpoint", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes", + "line_range": [ + 2098, + 2103 + ] + }, + { + "text": "| .>|12, 20, 1 |During instruction address translation: + {nbsp}{nbsp}{nbsp}First encountered page fault, guest-page fault, or access fault", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes", + "line_range": [ + 2105, + 2107 + ] + }, + { + "text": "| .>|1 |With physical address for instruction: + {nbsp}{nbsp}{nbsp}Instruction access fault", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes", + "line_range": [ + 2109, + 2110 + ] + }, + { + "text": "| |2 + 22 + 0 + 8, 9, 10, 11 + 3 + 3|Illegal instruction + Virtual instruction + Instruction address misaligned + Environment call + Environment break + {nbsp}{nbsp}{nbsp}Load/store/AMO address breakpoint", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes", + "line_range": [ + 2112, + 2122 + ] + }, + { + "text": "| .>|4,6 |Optionally: + {nbsp}{nbsp}{nbsp}Load/store/AMO address misaligned", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes", + "line_range": [ + 2124, + 2125 + ] + }, + { + "text": "| .>|13, 15, 21, 23, 5, 7 |During address translation for an explicit memory access: + {nbsp}{nbsp}{nbsp}First encountered page fault, guest-page fault, or access fault", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes", + "line_range": [ + 2127, + 2129 + ] + }, + { + "text": "| .>|5, 7 |With physical address for an explicit memory access: + {nbsp}{nbsp}{nbsp}Load/store/AMO access fault", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes", + "line_range": [ + 2131, + 2132 + ] + }, + { + "text": "If not higher priority: + {nbsp}{nbsp}{nbsp}Load/store/AMO address misaligned |", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes", + "line_range": [ + 2134, + 2136 + ] + }, + { + "text": "If an instruction may raise multiple synchronous exceptions, the decreasing priority order of indicates which exception is taken and reported in `mcause` or `scause`.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Cause Codes", + "line_range": [ + 2138, + 2141 + ] + }, + { + "text": "When a trap occurs in HS-mode or U-mode, it goes to M-mode, unless delegated by `medeleg` or `mideleg`, in which case it goes to HS-mode.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Entry", + "line_range": [ + 2145, + 2151 + ] + }, + { + "text": "When a trap occurs in VS-mode or VU-mode, it goes to M-mode, unless delegated by `medeleg` or `mideleg`, in which case it goes to HS-mode, unless further delegated by `hedeleg` or `hideleg`, in which case it goes to VS-mode.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Entry", + "line_range": [ + 2145, + 2151 + ] + }, + { + "text": "When a trap is taken into M-mode, virtualization mode V gets set to 0, and fields MPV and MPP in `mstatus` (or `mstatush`) are set according to . A trap into M-mode also writes fields GVA, MPIE, and MIE in `mstatus`/`mstatush` and writes CSRs `mepc`, `mcause`, `mtval`, `mtval2`, and `mtinst`.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Entry", + "line_range": [ + 2153, + 2158 + ] + }, + { + "text": ".Value of `mstatus`/`mstatush` fields MPV and MPP after a trap into M-mode.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Entry", + "line_range": [ + 2160, + 2176 + ] + }, + { + "text": "Upon trap return, MPV is ignored when MPP=3. | |Previous Mode |MPV |MPP |U-mode + HS-mode + M-mode|0 + 0 + 0|0 + 1 + 3 |VU-mode + VS-mode|1 + 1|0 + 1 |", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Entry", + "line_range": [ + 2160, + 2176 + ] + }, + { + "text": "When a trap is taken into HS-mode, virtualization mode V is set to 0, and `hstatus`.SPV and `sstatus`.SPP are set according to .", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Entry", + "line_range": [ + 2178, + 2185 + ] + }, + { + "text": "If V was 1 before the trap, field SPVP in `hstatus` is set the same as `sstatus`.SPP; otherwise, SPVP is left unchanged. A trap into HS-mode also writes field GVA in `hstatus`, fields SPIE and SIE in `sstatus`, and CSRs `sepc`, `scause`, `stval`, `htval`, and `htinst`.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Entry", + "line_range": [ + 2178, + 2185 + ] + }, + { + "text": ".Value of `hstatus` field SPV and `sstatus` field SPP after a trap into HS-mode. | |Previous Mode |SPV |SPP |U-mode + HS-mode + |0 + 0 |0 + 1 |VU-mode + VS-mode|1 + 1 |0 + 1 |", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Entry", + "line_range": [ + 2187, + 2200 + ] + }, + { + "text": "When a trap is taken into VS-mode, `vsstatus`.SPP is set according to .", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Entry", + "line_range": [ + 2202, + 2207 + ] + }, + { + "text": "Register `hstatus` and the HS-level `sstatus` are not modified, and the virtualization mode V remains 1. A trap into VS-mode also writes fields SPIE and SIE in `vsstatus` and writes CSRs `vsepc`, `vscause`, and `vstval`.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Entry", + "line_range": [ + 2202, + 2207 + ] + }, + { + "text": ".Value of `vsstatus` field SPP after a trap into VS-mode. | |Previous Mode |SPP |VU-mode + VS-mode |0 + 1 |", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Entry", + "line_range": [ + 2209, + 2217 + ] + }, + { + "text": "On any trap into M-mode or HS-mode, one of these values is written automatically into the appropriate trap instruction CSR, `mtinst` or `htinst`:", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "line_range": [ + 2222, + 2225 + ] + }, + { + "text": "zero; * a transformation of the trapping instruction; * a custom value (allowed only if the trapping instruction is non-standard); or * a special pseudoinstruction.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "line_range": [ + 2227, + 2231 + ] + }, + { + "text": "Except when a pseudoinstruction value is required (described later), the value written to `mtinst` or `htinst` may always be zero, indicating that the hardware is providing no information in the register for this particular trap.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "line_range": [ + 2233, + 2236 + ] + }, + { + "text": "On an interrupt, the value written to the trap instruction register is always zero.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "line_range": [ + 2238, + 2241 + ] + }, + { + "text": "On a synchronous exception, if a nonzero value is written, one of the following shall be true about the value:", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "line_range": [ + 2238, + 2241 + ] + }, + { + "text": "* Bit 0 is `1`, and replacing bit 1 with `1` makes the value into a valid encoding of a standard instruction. + In this case, the instruction that trapped is the same kind as indicated by the register value, and the register value is the transformation of the trapping instruction, as defined later.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "line_range": [ + 2243, + 2261 + ] + }, + { + "text": "For example, if bits 1:0 are binary `11` and the register value is the encoding of a standard LW (load word) instruction, then the trapping instruction is LW, and the register value is the transformation of the trapping LW instruction. * Bit 0 is `1`, and replacing bit 1 with `1` makes the value into an instruction encoding that is explicitly designated for a custom instruction (not an unused reserved encoding). + This is a custom value.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "line_range": [ + 2243, + 2261 + ] + }, + { + "text": "The instruction that trapped is a non-standard instruction.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "line_range": [ + 2243, + 2261 + ] + }, + { + "text": "The interpretation of a custom value is not otherwise specified by this standard. * The value is one of the special pseudoinstructions defined later, all of which have bits 1:0 equal to `00`.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "line_range": [ + 2243, + 2261 + ] + }, + { + "text": "These three cases exclude a large number of other possible values, such as all those having bits 1:0 equal to binary `10`. A future standard or extension may define additional cases, thus allowing values that are currently excluded.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "line_range": [ + 2263, + 2267 + ] + }, + { + "text": "Software may safely treat an unrecognized value in a trap instruction register the same as zero.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "line_range": [ + 2263, + 2267 + ] + }, + { + "text": "shows the values that may be automatically written to the trap instruction register for each standard exception cause.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "line_range": [ + 2269, + 2277 + ] + }, + { + "text": "For exceptions that prevent the fetching of an instruction, only zero or a pseudoinstruction value may be written. A custom value may be automatically written only if the instruction that traps is non-standard. A future standard or extension may permit other values to be written, chosen from the set of allowed values established earlier.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "line_range": [ + 2269, + 2277 + ] + }, + { + "text": ".Values that may be automatically written to the trap instruction (`mtinst` or `htinst`) register on an exception trap. [float=\"center\",align=\"center\",cols=\"2,^,^,^,^\",options=\"header\"] | <.>|Exception ^.>|Zero |Transformed + Standard + Instruction ^.>|Custom Value ^.>|Pseudoinstruction Value |Instruction address misaligned |Yes |No |Yes |No |Instruction access fault + Illegal instruction + Breakpoint + Virtual instruction |Yes + Yes + Yes + Yes |No + No + No + No + |No + No + Yes + Yes |No + No + No + No |Load address misaligned + Load access fault + Store/AMO address misaligned + Store/AMO access fault |Yes + Yes + Yes + Yes |Yes + Yes + Yes + Yes |Yes + Yes + Yes + Yes |No + No + No + No |Environment call |Yes |No |Yes |No |Instruction page fault + Load page fault + Store/AMO page fault |Yes + Yes + Yes |No + Yes + Yes |No + Yes + Yes |No + No + No |Instruction guest-page fault + Load guest-page fault + Store/AMO guest-page fault |Yes + Yes + Yes |No + Yes + Yes |No + Yes + Yes |Yes + Yes + Yes |", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "line_range": [ + 2281, + 2364 + ] + }, + { + "text": "As enumerated in the table, a synchronous exception may write to the trap instruction register a standard transformation of the trapping instruction only for exceptions that arise from explicit memory accesses (from loads, stores, and AMO instructions).", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "line_range": [ + 2366, + 2374 + ] + }, + { + "text": "Accordingly, standard transformations are currently defined only for these memory-access instructions.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "line_range": [ + 2366, + 2374 + ] + }, + { + "text": "If a synchronous trap occurs for a standard instruction for which no transformation has been defined, the trap instruction register shall be written with zero (or, under certain circumstances, with a special pseudoinstruction value).", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "line_range": [ + 2366, + 2374 + ] + }, + { + "text": "For a standard load instruction that is not a compressed instruction and is one of LB, LBU, LH, LHU, LW, LWU, LD, FLW, FLD, FLQ, or FLH, the transformed instruction has the format shown in .", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "line_range": [ + 2376, + 2379 + ] + }, + { + "text": ".Transformed load instruction (LB, LBU, LH, LHU, LW, LWU, LD, FLW, FLD, FLQ, or FLH).", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "line_range": [ + 2381, + 2383 + ] + }, + { + "text": "Fields funct3, rd, and opcode are the same as the trapping load instruction. include::images/wavedrom/transformedloadinst.edn[]", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "line_range": [ + 2381, + 2383 + ] + }, + { + "text": "For a standard store instruction that is not a compressed instruction and is one of SB, SH, SW, SD, FSW, FSD, FSQ, or FSH, the transformed instruction has the format shown in .", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "line_range": [ + 2385, + 2388 + ] + }, + { + "text": ".Transformed store instruction (SB, SH, SW, SD, FSW, FSD, FSQ, or FSH).", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "line_range": [ + 2390, + 2392 + ] + }, + { + "text": "Fields rs2, funct3, and opcode are the same as the trapping store instruction. include::images/wavedrom/transformedstoreinst.edn[]", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "line_range": [ + 2390, + 2392 + ] + }, + { + "text": "For a standard atomic instruction (load-reserved, store-conditional, or AMO instruction), the transformed instruction has the format shown in .", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "line_range": [ + 2394, + 2394 + ] + }, + { + "text": ".Transformed atomic instruction (load-reserved, store-conditional, or AMO instruction).", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "line_range": [ + 2396, + 2398 + ] + }, + { + "text": "All fields are the same as the trapping instruction except bits 19:15, Addr.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "line_range": [ + 2396, + 2398 + ] + }, + { + "text": "Offset. include::images/wavedrom/transformedatomicinst.edn[]", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "line_range": [ + 2396, + 2398 + ] + }, + { + "text": "For a standard virtual-machine load/store instruction (HLV, HLVX, or HSV), the transformed instruction has the format shown in .", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "line_range": [ + 2400, + 2400 + ] + }, + { + "text": ".Transformed virtual-machine load/store instruction (HLV, HLVX, HSV).", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "line_range": [ + 2402, + 2404 + ] + }, + { + "text": "All fields are the same as the trapping instruction except bits 19:15, Addr.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "line_range": [ + 2402, + 2404 + ] + }, + { + "text": "Offset include::images/wavedrom/transformedvmaccessinst.edn[]", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "line_range": [ + 2402, + 2404 + ] + }, + { + "text": "In all the transformed instructions above, the Addr.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "line_range": [ + 2406, + 2412 + ] + }, + { + "text": "Offset field that replaces the instruction’s rs1 field in bits 19:15 is the positive difference between the faulting virtual address (written to `mtval` or `stval`) and the original virtual address.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "line_range": [ + 2406, + 2412 + ] + }, + { + "text": "This difference can be nonzero only for a misaligned memory access.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "line_range": [ + 2406, + 2412 + ] + }, + { + "text": "Note also that, for basic loads and stores, the transformations replace the instruction’s immediate offset fields with zero.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "line_range": [ + 2406, + 2412 + ] + }, + { + "text": "For a standard compressed instruction (16-bit size), the transformed instruction is found as follows:", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "line_range": [ + 2414, + 2415 + ] + }, + { + "text": "Expand the compressed instruction to its 32-bit equivalent. .", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "line_range": [ + 2417, + 2419 + ] + }, + { + "text": "Transform the 32-bit equivalent instruction. .", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "line_range": [ + 2417, + 2419 + ] + }, + { + "text": "Bits 1:0 of a transformed standard instruction will be binary `01` if the trapping instruction is compressed and `11` if not.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "line_range": [ + 2421, + 2430 + ] + }, + { + "text": "For guest-page faults, the trap instruction register is written with a special pseudoinstruction value if: (a) the fault is caused by an implicit memory access for VS-stage address translation, and (b) a nonzero value (the faulting guest physical address) is written to `mtval2` or `htval`.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "line_range": [ + 2421, + 2430 + ] + }, + { + "text": "If both conditions are met, the value written to `mtinst` or `htinst` must be taken from ; zero is not allowed.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "line_range": [ + 2421, + 2430 + ] + }, + { + "text": ".Special pseudoinstruction values for guest-page faults.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "line_range": [ + 2432, + 2440 + ] + }, + { + "text": "The RV32 values are used when VSXLEN=32, and the RV64 values when VSXLEN=64. | |Value |Meaning |`0x00002000` + `0x00002020` |32-bit read for VS-stage address translation (RV32) + 32-bit write for VS-stage address translation (RV32)", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "line_range": [ + 2432, + 2440 + ] + }, + { + "text": "|`0x00003000` + `0x00003020` |64-bit read for VS-stage address translation (RV64) + 64-bit write for VS-stage address translation (RV64) |", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "line_range": [ + 2442, + 2446 + ] + }, + { + "text": "The defined pseudoinstruction values are designed to correspond closely with the encodings of basic loads and stores, as illustrated by .", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "line_range": [ + 2448, + 2450 + ] + }, + { + "text": ".Standard instructions corresponding to the special pseudoinstructions of . | |Encoding |Instruction |`0x00002003` + `0x00002023` |`lw x0,0(x0)` + `sw x0,0(x0)`", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "line_range": [ + 2452, + 2460 + ] + }, + { + "text": "|`0x00003003` + `0x00003023` |`ld x0,0(x0)` + `sd x0,0(x0)` |", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "line_range": [ + 2462, + 2466 + ] + }, + { + "text": "A write pseudoinstruction (`0x00002020` or `0x00003020`) is used for the case that the machine is attempting automatically to update bits A and/or D in VS-level page tables.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "line_range": [ + 2468, + 2476 + ] + }, + { + "text": "All other implicit memory accesses for VS-stage address translation will be reads.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "line_range": [ + 2468, + 2476 + ] + }, + { + "text": "If a machine never automatically updates bits A or D in VS-level page tables (leaving this to software), the write case will never arise.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "line_range": [ + 2468, + 2476 + ] + }, + { + "text": "The fact that such a page table update must actually be atomic, not just a simple write, is ignored for the pseudoinstruction.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Transformed Instruction or Pseudoinstruction for `mtinst` or `htinst`", + "line_range": [ + 2468, + 2476 + ] + }, + { + "text": "The MRET instruction is used to return from a trap taken into M-mode. MRET first determines what the new privilege mode will be according to the values of MPP and MPV in `mstatus` or `mstatush`, as encoded in . MRET then in `mstatus`/`mstatush` sets MPV=0, MPP=0, MIE=MPIE, and MPIE=1.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Return", + "line_range": [ + 2480, + 2486 + ] + }, + { + "text": "Lastly, MRET sets the privilege mode as previously determined, and sets `pc`=`mepc`.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Return", + "line_range": [ + 2480, + 2486 + ] + }, + { + "text": "The SRET instruction is used to return from a trap taken into HS-mode or VS-mode.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Return", + "line_range": [ + 2488, + 2490 + ] + }, + { + "text": "Its behavior depends on the current virtualization mode.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Return", + "line_range": [ + 2488, + 2490 + ] + }, + { + "text": "When executed in M-mode or HS-mode (i.e., V=0), SRET first determines what the new privilege mode will be according to the values in `hstatus`.SPV and `sstatus`.SPP, as encoded in . SRET then sets `hstatus`.SPV=0, and in `sstatus` sets SPP=0, SIE=SPIE, and SPIE=1.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Return", + "line_range": [ + 2492, + 2498 + ] + }, + { + "text": "Lastly, SRET sets the privilege mode as previously determined, and sets `pc`=`sepc`.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Return", + "line_range": [ + 2492, + 2498 + ] + }, + { + "text": "When executed in VS-mode (i.e., V=1), SRET sets the privilege mode according to , in `vsstatus` sets SPP=0, SIE=SPIE, and SPIE=1, and lastly sets `pc`=`vsepc`.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Return", + "line_range": [ + 2500, + 2503 + ] + }, + { + "text": "If the Ssdbltrp extension is implemented, when `SRET` is executed in HS-mode, if the new privilege mode is VU, the `SRET` instruction sets `vsstatus.SDT` to 0.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Return", + "line_range": [ + 2505, + 2508 + ] + }, + { + "text": "When executed in VS-mode, `vsstatus.SDT` is set to 0.", + "section": "Preamble > \"H\" Extension for Hypervisor Support, Version 1.0 > Traps > Trap Return", + "line_range": [ + 2505, + 2508 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__priv__insns.json b/tools/llm-extraction/data/output/raw_chunks/src__priv__insns.json new file mode 100644 index 0000000000..7f4d56f35d --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__priv__insns.json @@ -0,0 +1,30 @@ +{ + "source_file": "src/priv/insns.adoc", + "total": 3, + "sentences": [ + { + "text": "This chapter presents instruction-set listings for all instructions defined in the RISC-V Privileged Architecture.", + "section": "Preamble > RISC-V Privileged Instruction Set Listings", + "line_range": [ + 3, + 4 + ] + }, + { + "text": "The instruction-set listings for unprivileged instructions, including the ECALL and EBREAK instructions, are provided in .", + "section": "Preamble > RISC-V Privileged Instruction Set Listings", + "line_range": [ + 6, + 7 + ] + }, + { + "text": ".RISC-V Privileged Instructions include::images/bytefield/priv-instr-set.edn[]", + "section": "Preamble > RISC-V Privileged Instruction Set Listings", + "line_range": [ + 9, + 10 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__priv__intro.json b/tools/llm-extraction/data/output/raw_chunks/src__priv__intro.json new file mode 100644 index 0000000000..f1974b0c92 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__priv__intro.json @@ -0,0 +1,358 @@ +{ + "source_file": "src/priv/intro.adoc", + "total": 44, + "sentences": [ + { + "text": "This volume describes the RISC-V privileged architecture, which covers all aspects of RISC-V systems beyond the unprivileged ISA, including privileged instructions as well as additional functionality required for running operating systems and attaching external devices.", + "section": "Preamble > Introduction", + "line_range": [ + 4, + 7 + ] + }, + { + "text": "This section describes the terminology we use to describe components of the wide range of possible privileged software stacks for RISC-V.", + "section": "Preamble > Introduction > RISC-V Privileged Software Stack Terminology", + "line_range": [ + 11, + 12 + ] + }, + { + "text": "shows some of the possible software stacks that can be supported by the RISC-V architecture.", + "section": "Preamble > Introduction > RISC-V Privileged Software Stack Terminology", + "line_range": [ + 14, + 24 + ] + }, + { + "text": "The left-hand side shows a simple system that supports only a single application running on an application execution environment (AEE).", + "section": "Preamble > Introduction > RISC-V Privileged Software Stack Terminology", + "line_range": [ + 14, + 24 + ] + }, + { + "text": "The application is coded to run with a particular application binary interface (ABI).", + "section": "Preamble > Introduction > RISC-V Privileged Software Stack Terminology", + "line_range": [ + 14, + 24 + ] + }, + { + "text": "The ABI includes the supported user-level ISA plus a set of ABI calls to interact with the AEE.", + "section": "Preamble > Introduction > RISC-V Privileged Software Stack Terminology", + "line_range": [ + 14, + 24 + ] + }, + { + "text": "The ABI hides details of the AEE from the application to allow greater flexibility in implementing the AEE.", + "section": "Preamble > Introduction > RISC-V Privileged Software Stack Terminology", + "line_range": [ + 14, + 24 + ] + }, + { + "text": "The same ABI could be implemented natively on multiple different host OSs, or could be supported by a user-mode emulation environment running on a machine with a different native ISA.", + "section": "Preamble > Introduction > RISC-V Privileged Software Stack Terminology", + "line_range": [ + 14, + 24 + ] + }, + { + "text": ".Different implementation stacks supporting various forms of privileged execution. image::png/privimps.png[]", + "section": "Preamble > Introduction > RISC-V Privileged Software Stack Terminology", + "line_range": [ + 26, + 28 + ] + }, + { + "text": "The middle configuration shows a conventional operating system (OS) that can support multiprogrammed execution of multiple applications.", + "section": "Preamble > Introduction > RISC-V Privileged Software Stack Terminology", + "line_range": [ + 30, + 42 + ] + }, + { + "text": "Each application communicates over an ABI with the OS, which provides the AEE.", + "section": "Preamble > Introduction > RISC-V Privileged Software Stack Terminology", + "line_range": [ + 30, + 42 + ] + }, + { + "text": "Just as applications interface with an AEE via an ABI, RISC-V operating systems interface with a supervisor execution environment (SEE) via a supervisor binary interface (SBI).", + "section": "Preamble > Introduction > RISC-V Privileged Software Stack Terminology", + "line_range": [ + 30, + 42 + ] + }, + { + "text": "An SBI comprises the user-level and supervisor-level ISA together with a set of SBI function calls.", + "section": "Preamble > Introduction > RISC-V Privileged Software Stack Terminology", + "line_range": [ + 30, + 42 + ] + }, + { + "text": "Using a single SBI across all SEE implementations allows a single OS binary image to run on any SEE.", + "section": "Preamble > Introduction > RISC-V Privileged Software Stack Terminology", + "line_range": [ + 30, + 42 + ] + }, + { + "text": "The SEE can be a simple boot loader and BIOS-style IO system in a low-end hardware platform, or a hypervisor-provided virtual machine in a high-end server, or a thin translation layer over a host operating system in an architecture simulation environment.", + "section": "Preamble > Introduction > RISC-V Privileged Software Stack Terminology", + "line_range": [ + 30, + 42 + ] + }, + { + "text": "The rightmost configuration shows a virtual machine monitor configuration where multiple multiprogrammed OSs are supported by a single hypervisor.", + "section": "Preamble > Introduction > RISC-V Privileged Software Stack Terminology", + "line_range": [ + 44, + 49 + ] + }, + { + "text": "Each OS communicates via an SBI with the hypervisor, which provides the SEE.", + "section": "Preamble > Introduction > RISC-V Privileged Software Stack Terminology", + "line_range": [ + 44, + 49 + ] + }, + { + "text": "The hypervisor communicates with the hypervisor execution environment (HEE) using a hypervisor binary interface (HBI), to isolate the hypervisor from details of the hardware platform.", + "section": "Preamble > Introduction > RISC-V Privileged Software Stack Terminology", + "line_range": [ + 44, + 49 + ] + }, + { + "text": "Hardware implementations of the RISC-V ISA will generally require additional features beyond the privileged ISA to support the various execution environments (AEE, SEE, or HEE).", + "section": "Preamble > Introduction > RISC-V Privileged Software Stack Terminology", + "line_range": [ + 51, + 53 + ] + }, + { + "text": "At any time, a RISC-V hardware thread (hart) is running at some privilege level encoded as a mode in one or more CSRs (control and status registers).", + "section": "Preamble > Introduction > Privilege Levels", + "line_range": [ + 57, + 61 + ] + }, + { + "text": "Three RISC-V privilege levels are currently defined as shown in .", + "section": "Preamble > Introduction > Privilege Levels", + "line_range": [ + 57, + 61 + ] + }, + { + "text": ".RISC-V privilege levels. | |Level |Encoding |Name |Abbreviation |0 |`00` |User/Application |U |1 |`01` |Supervisor |S |2 |`10` |Reserved |{nbsp} |3 |`11` |Machine |M |", + "section": "Preamble > Introduction > Privilege Levels", + "line_range": [ + 63, + 72 + ] + }, + { + "text": "Privilege levels are used to provide protection between different components of the software stack, and attempts to perform operations not permitted by the current privilege mode will cause an exception to be raised.", + "section": "Preamble > Introduction > Privilege Levels", + "line_range": [ + 74, + 78 + ] + }, + { + "text": "These exceptions will normally cause traps into an underlying execution environment.", + "section": "Preamble > Introduction > Privilege Levels", + "line_range": [ + 74, + 78 + ] + }, + { + "text": "The machine level has the highest privileges and is the only mandatory privilege level for a RISC-V hardware platform.", + "section": "Preamble > Introduction > Privilege Levels", + "line_range": [ + 80, + 86 + ] + }, + { + "text": "Code run in machine-mode (M-mode) is usually inherently trusted, as it has low-level access to the machine implementation. M-mode can be used to manage secure execution environments on RISC-V.", + "section": "Preamble > Introduction > Privilege Levels", + "line_range": [ + 80, + 86 + ] + }, + { + "text": "User-mode (U-mode) and supervisor-mode (S-mode) are intended for conventional application and operating system usage respectively.", + "section": "Preamble > Introduction > Privilege Levels", + "line_range": [ + 80, + 86 + ] + }, + { + "text": "Each privilege level has a core set of privileged ISA extensions with optional extensions and variants.", + "section": "Preamble > Introduction > Privilege Levels", + "line_range": [ + 88, + 92 + ] + }, + { + "text": "For example, machine-mode supports an optional standard extension for memory protection.", + "section": "Preamble > Introduction > Privilege Levels", + "line_range": [ + 88, + 92 + ] + }, + { + "text": "Also, supervisor mode can be extended to support Type-2 hypervisor execution as described in .", + "section": "Preamble > Introduction > Privilege Levels", + "line_range": [ + 88, + 92 + ] + }, + { + "text": "Implementations might provide anywhere from 1 to 3 privilege modes trading off reduced isolation for lower implementation cost, as shown in .", + "section": "Preamble > Introduction > Privilege Levels", + "line_range": [ + 94, + 96 + ] + }, + { + "text": ".Supported combination of privilege modes. | |Number of levels |Supported Modes |Intended Usage |1 |M |Simple embedded systems |2 |M, U |Secure embedded systems |3 |M, S, U |Systems running Unix-like operating systems |", + "section": "Preamble > Introduction > Privilege Levels", + "line_range": [ + 98, + 106 + ] + }, + { + "text": "All hardware implementations must provide M-mode, as this is the only mode that has unfettered access to the whole machine.", + "section": "Preamble > Introduction > Privilege Levels", + "line_range": [ + 108, + 111 + ] + }, + { + "text": "The simplest RISC-V implementations may provide only M-mode, though this will provide no protection against incorrect or malicious application code.", + "section": "Preamble > Introduction > Privilege Levels", + "line_range": [ + 108, + 111 + ] + }, + { + "text": "Many RISC-V implementations will also support at least user mode (U-mode) to protect the rest of the system from application code.", + "section": "Preamble > Introduction > Privilege Levels", + "line_range": [ + 113, + 116 + ] + }, + { + "text": "Supervisor mode (S-mode) can be added to provide isolation between a supervisor-level operating system and the SEE.", + "section": "Preamble > Introduction > Privilege Levels", + "line_range": [ + 113, + 116 + ] + }, + { + "text": "A hart normally runs application code in U-mode until some trap (e.g., a supervisor call or a timer interrupt) forces a switch to a trap handler, which usually runs in a more privileged mode.", + "section": "Preamble > Introduction > Privilege Levels", + "line_range": [ + 118, + 126 + ] + }, + { + "text": "The hart will then execute the trap handler, which will eventually resume execution at or after the original trapped instruction in U-mode.", + "section": "Preamble > Introduction > Privilege Levels", + "line_range": [ + 118, + 126 + ] + }, + { + "text": "Traps that increase privilege level are termed vertical traps, while traps that remain at the same privilege level are termed horizontal traps.", + "section": "Preamble > Introduction > Privilege Levels", + "line_range": [ + 118, + 126 + ] + }, + { + "text": "The RISC-V privileged architecture provides flexible routing of traps to different privilege layers.", + "section": "Preamble > Introduction > Privilege Levels", + "line_range": [ + 118, + 126 + ] + }, + { + "text": "Implementations may also include a debug mode to support off-chip debugging and/or manufacturing test.", + "section": "Preamble > Introduction > Debug Mode", + "line_range": [ + 130, + 136 + ] + }, + { + "text": "Debug mode (D-mode) can be considered an additional privilege mode, with even more access than M-mode.", + "section": "Preamble > Introduction > Debug Mode", + "line_range": [ + 130, + 136 + ] + }, + { + "text": "The separate debug specification describes operation of a RISC-V hart in debug mode.", + "section": "Preamble > Introduction > Debug Mode", + "line_range": [ + 130, + 136 + ] + }, + { + "text": "Debug mode reserves a few CSR addresses that are only accessible in D-mode, and may also reserve some portions of the physical address space on a platform.", + "section": "Preamble > Introduction > Debug Mode", + "line_range": [ + 130, + 136 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__priv__machine.json b/tools/llm-extraction/data/output/raw_chunks/src__priv__machine.json new file mode 100644 index 0000000000..89fc0994eb --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__priv__machine.json @@ -0,0 +1,6334 @@ +{ + "source_file": "src/priv/machine.adoc", + "total": 791, + "sentences": [ + { + "text": "This chapter describes the machine-level operations available in machine-mode (M-mode), which is the highest privilege mode in a RISC-V hart. M-mode is used for low-level access to a hardware platform and is the first mode entered at reset. M-mode can also be used to implement features that are too difficult or expensive to implement in hardware directly.", + "section": "Preamble > Machine-Level ISA, Version 1.13", + "line_range": [ + 3, + 10 + ] + }, + { + "text": "The RISC-V machine-level ISA contains a common core that is extended depending on which other privilege levels are supported and other details of the hardware implementation.", + "section": "Preamble > Machine-Level ISA, Version 1.13", + "line_range": [ + 3, + 10 + ] + }, + { + "text": "In addition to the machine-level CSRs described in this section, M-mode code can access all CSRs at lower privilege levels.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs", + "line_range": [ + 14, + 15 + ] + }, + { + "text": "The `misa` CSR is a *WARL* read-write register reporting the ISA supported by the hart.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register", + "line_range": [ + 20, + 22 + ] + }, + { + "text": "This register must be readable in any implementation, but a value of zero can be returned to indicate the `misa` register has not been implemented, requiring that CPU capabilities be determined through a separate non-standard mechanism.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register", + "line_range": [ + 20, + 22 + ] + }, + { + "text": ".Machine ISA register (misa) include::images/bytefield/misareg.edn[]", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register", + "line_range": [ + 24, + 26 + ] + }, + { + "text": "The MXL (Machine XLEN) field encodes the native base integer ISA width as shown in .", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register", + "line_range": [ + 28, + 34 + ] + }, + { + "text": "The MXL field is read-only.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register", + "line_range": [ + 28, + 34 + ] + }, + { + "text": "If `misa` is nonzero, the MXL field indicates the effective XLEN in M-mode, a constant termed MXLEN. XLEN is never greater than MXLEN, but XLEN might be smaller than MXLEN in less-privileged modes.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register", + "line_range": [ + 28, + 34 + ] + }, + { + "text": ".Encoding of MXL field in `misa` | |MXL |XLEN |1 + 2 + 3 |32 + 64 + Reserved |", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register", + "line_range": [ + 36, + 47 + ] + }, + { + "text": "The `misa` CSR is MXLEN bits wide.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register", + "line_range": [ + 49, + 49 + ] + }, + { + "text": "The Extensions field encodes the presence of the standard extensions, with a single bit per letter of the alphabet (bit 0 encodes presence of extension \"A\" , bit 1 encodes presence of extension \"B\", through to bit 25 which encodes \"Z\").", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register", + "line_range": [ + 51, + 60 + ] + }, + { + "text": "The \"I\" bit will be set for the RV32I and RV64I base ISAs, and the \"E\" bit will be set for RV32E and RV64E.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register", + "line_range": [ + 51, + 60 + ] + }, + { + "text": "The Extensions field is a *WARL* field that can contain writable bits where the implementation allows the supported ISA to be modified.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register", + "line_range": [ + 51, + 60 + ] + }, + { + "text": "At reset, the Extensions field shall contain the maximal set of supported extensions, and \"I\" shall be selected over \"E\" if both are available.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register", + "line_range": [ + 51, + 60 + ] + }, + { + "text": "When a standard extension is disabled by clearing its bit in `misa`, the instructions and CSRs defined or modified by the extension revert to their defined or reserved behaviors as if the extension is not implemented.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register", + "line_range": [ + 62, + 66 + ] + }, + { + "text": "All bits that are reserved for future use must return zero when read.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register", + "line_range": [ + 68, + 68 + ] + }, + { + "text": ".Encoding of Extensions field in `misa`. | |Bit |Character |Description |0 |A |Atomic extension |1 |B |B extension |2 |C |Compressed extension |3 |D |Double-precision floating-point extension |4 |E |RV32E/64E base ISA |5 |F |Single-precision floating-point extension |6 |G |Reserved |7 |H |Hypervisor extension |8 |I |RV32I/64I base ISA |9 |J |Reserved |10 |K |Reserved |11 |L |Reserved |12 |M |Integer Multiply/Divide extension |13 |N |Tentatively reserved for User-Level Interrupts extension |14 |O |Reserved |15 |P |Tentatively reserved for Packed-SIMD extension |16 |Q |Quad-precision floating-point extension |17 |R |Reserved |18 |S |Supervisor mode implemented |19 |T |Reserved |20 |U |User mode implemented |21 |V |Vector extension |22 |W |Reserved |23 |X |Non-standard extensions implemented |24 |Y |Reserved |25 |Z |Reserved |", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register", + "line_range": [ + 70, + 101 + ] + }, + { + "text": "The \"X\" bit will be set if there are any non-standard extensions.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register", + "line_range": [ + 103, + 103 + ] + }, + { + "text": "When the \"B\" bit is 1, the implementation supports the instructions provided by the Zba, Zbb, and Zbs extensions.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register", + "line_range": [ + 105, + 107 + ] + }, + { + "text": "When the \"B\" bit is 0, it indicates that the implementation might not support one or more of the Zba, Zbb, or Zbs extensions.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register", + "line_range": [ + 105, + 107 + ] + }, + { + "text": "When the \"M\" bit is 1, the implementation supports all multiply and division instructions defined by the M extension.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register", + "line_range": [ + 109, + 114 + ] + }, + { + "text": "When the \"M\" bit is 0, it indicates that the implementation might not support those instructions.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register", + "line_range": [ + 109, + 114 + ] + }, + { + "text": "However if the Zmmul extension is supported then the multiply instructions it specifies are supported irrespective of the value of the \"M\" bit.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register", + "line_range": [ + 109, + 114 + ] + }, + { + "text": "When the \"S\" bit is 1, the implementation supports supervisor mode.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register", + "line_range": [ + 116, + 117 + ] + }, + { + "text": "When the \"S\" bit is 0, the implementation might not support supervisor mode.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register", + "line_range": [ + 116, + 117 + ] + }, + { + "text": "When the \"U\" bit is 1, the implementation supports user mode.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register", + "line_range": [ + 119, + 120 + ] + }, + { + "text": "When the \"U\" bit is 0, the implementation might not support user mode.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register", + "line_range": [ + 119, + 120 + ] + }, + { + "text": "Unless `misa` is all read-only zero, the \"E\" bit always reads as the complement of the \"I\" bit.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register", + "line_range": [ + 122, + 126 + ] + }, + { + "text": "If an execution environment supports both RV32E and RV32I, software can select RV32E by clearing the \"I\" bit.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register", + "line_range": [ + 122, + 126 + ] + }, + { + "text": "If an ISA feature x depends on an ISA feature y, then attempting to enable feature x but disable feature y results in both features being disabled.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register", + "line_range": [ + 128, + 132 + ] + }, + { + "text": "For example, setting \"F\"=0 and \"D\"=1 results in both \"F\" and \"D\" being cleared.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register", + "line_range": [ + 128, + 132 + ] + }, + { + "text": "Similarly, setting \"U\"=0 and \"S\"=1\" results in both \"U\" and \"S\" being cleared.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register", + "line_range": [ + 128, + 132 + ] + }, + { + "text": "An implementation may impose additional constraints on the collective setting of two or more `misa` fields, in which case they function collectively as a single *WARL* field.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register", + "line_range": [ + 134, + 136 + ] + }, + { + "text": "An attempt to write an unsupported combination causes those bits to be set to some supported combination.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register", + "line_range": [ + 134, + 136 + ] + }, + { + "text": "Writing `misa` may increase IALIGN, e.g., by disabling the \"C\" extension.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register", + "line_range": [ + 138, + 141 + ] + }, + { + "text": "If an instruction that would write `misa` increases IALIGN, and the subsequent instruction's address is not IALIGN-bit aligned, the write to `misa` is suppressed, leaving `misa` unchanged.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register", + "line_range": [ + 138, + 141 + ] + }, + { + "text": "When software enables an extension that was previously disabled, then all state uniquely associated with that extension is UNSPECIFIED, unless otherwise specified by that extension.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register", + "line_range": [ + 143, + 144 + ] + }, + { + "text": "NOTE: Although one of the bits 25--0 in `misa` being set to 1 implies that the corresponding feature is implemented, the inverse is not necessarily true: one of these bits being clear does not necessarily imply that the corresponding feature is not implemented.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register", + "line_range": [ + 146, + 151 + ] + }, + { + "text": "This follows from the fact that, when a feature is not implemented, the corresponding opcodes and CSRs become reserved, not necessarily illegal.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine ISA (`misa`) Register", + "line_range": [ + 146, + 151 + ] + }, + { + "text": "The `mvendorid` CSR is a 32-bit read-only register providing the JEDEC manufacturer ID of the provider of the core.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Vendor ID (`mvendorid`) Register", + "line_range": [ + 155, + 158 + ] + }, + { + "text": "This register must be readable in any implementation, but a value of 0 can be returned to indicate the field is not implemented or that this is a non-commercial implementation.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Vendor ID (`mvendorid`) Register", + "line_range": [ + 155, + 158 + ] + }, + { + "text": ".Vendor ID register (`mvendorid`) include::images/bytefield/mvendorid.edn[]", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Vendor ID (`mvendorid`) Register", + "line_range": [ + 160, + 161 + ] + }, + { + "text": "JEDEC manufacturer IDs are ordinarily encoded as a sequence of one-byte continuation codes `0x7f`, terminated by a one-byte ID not equal to `0x7f`, with an odd parity bit in the most-significant bit of each byte. `mvendorid` encodes the number of one-byte continuation codes in the Bank field, and encodes the final byte in the Offset field, discarding the parity bit.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Vendor ID (`mvendorid`) Register", + "line_range": [ + 163, + 171 + ] + }, + { + "text": "For example, the JEDEC manufacturer ID `0x7f 0x7f 0x7f 0x7f 0x7f 0x7f 0x7f 0x7f 0x7f 0x7f 0x7f 0x7f 0x8a` (twelve continuation codes followed by `0x8a`) would be encoded in the `mvendorid` CSR as `0x60a`.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Vendor ID (`mvendorid`) Register", + "line_range": [ + 163, + 171 + ] + }, + { + "text": "The `marchid` CSR is an MXLEN-bit read-only register encoding the base microarchitecture of the hart.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Architecture ID (`marchid`) Register", + "line_range": [ + 175, + 179 + ] + }, + { + "text": "This register must be readable in any implementation, but a value of 0 can be returned to indicate the field is not implemented.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Architecture ID (`marchid`) Register", + "line_range": [ + 175, + 179 + ] + }, + { + "text": "The combination of `mvendorid` and `marchid` should uniquely identify the type of hart microarchitecture that is implemented.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Architecture ID (`marchid`) Register", + "line_range": [ + 175, + 179 + ] + }, + { + "text": ".Machine Architecture ID (`marchid`) register include::images/bytefield/marchid.edn[]", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Architecture ID (`marchid`) Register", + "line_range": [ + 181, + 182 + ] + }, + { + "text": "Open-source project architecture IDs are allocated globally by RISC-V International, and have non-zero architecture IDs with a zero most-significant-bit (MSB).", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Architecture ID (`marchid`) Register", + "line_range": [ + 184, + 188 + ] + }, + { + "text": "Commercial architecture IDs are allocated by each commercial vendor independently, but must have the MSB set and cannot contain zero in the remaining MXLEN-1 bits.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Architecture ID (`marchid`) Register", + "line_range": [ + 184, + 188 + ] + }, + { + "text": "The `mimpid` CSR provides a unique encoding of the version of the processor implementation.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Implementation ID (`mimpid`) Register", + "line_range": [ + 192, + 196 + ] + }, + { + "text": "This register must be readable in any implementation, but a value of 0 can be returned to indicate that the field is not implemented.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Implementation ID (`mimpid`) Register", + "line_range": [ + 192, + 196 + ] + }, + { + "text": "The Implementation value should reflect the design of the RISC-V processor itself and not any surrounding system.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Implementation ID (`mimpid`) Register", + "line_range": [ + 192, + 196 + ] + }, + { + "text": ".Machine Implementation ID (`mimpid`) register include::images/bytefield/mimpid.edn[]", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Implementation ID (`mimpid`) Register", + "line_range": [ + 198, + 199 + ] + }, + { + "text": "The `mhartid` CSR is an MXLEN-bit read-only register containing the integer ID of the hardware thread running the code.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Hart ID (`mhartid`) Register", + "line_range": [ + 203, + 208 + ] + }, + { + "text": "This register must be readable in any implementation.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Hart ID (`mhartid`) Register", + "line_range": [ + 203, + 208 + ] + }, + { + "text": "Hart IDs might not necessarily be numbered contiguously in a multiprocessor system, but one hart must have a hart ID of zero.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Hart ID (`mhartid`) Register", + "line_range": [ + 203, + 208 + ] + }, + { + "text": "Hart IDs must be unique within the execution environment.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Hart ID (`mhartid`) Register", + "line_range": [ + 203, + 208 + ] + }, + { + "text": ".Hart ID (`mhartid`) register include::images/bytefield/mhartid.edn[]", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Hart ID (`mhartid`) Register", + "line_range": [ + 210, + 211 + ] + }, + { + "text": "The `mstatus` register is an MXLEN-bit read/write register formatted as shown in for RV32 and for RV64.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers", + "line_range": [ + 216, + 219 + ] + }, + { + "text": "The `mstatus` register keeps track of and controls the hart’s current operating state. A restricted view of `mstatus` appears as the `sstatus` register in the S-level ISA.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers", + "line_range": [ + 216, + 219 + ] + }, + { + "text": ".Machine-mode status (`mstatus`) register for RV32 include::images/wavedrom/mstatusreg-rv321.edn[]", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers", + "line_range": [ + 221, + 223 + ] + }, + { + "text": ".Machine-mode status (`mstatus`) register for RV64 include::images/wavedrom/mstatusreg.edn[]", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers", + "line_range": [ + 225, + 227 + ] + }, + { + "text": "For RV32 only, `mstatush` is a 32-bit read/write register formatted as shown in .", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers", + "line_range": [ + 229, + 230 + ] + }, + { + "text": "Bits 30:4 of `mstatush` generally contain the same fields found in bits 62:36 of `mstatus` for RV64.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers", + "line_range": [ + 229, + 230 + ] + }, + { + "text": "Fields SD, SXL, and UXL do not exist in `mstatush`.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers", + "line_range": [ + 229, + 230 + ] + }, + { + "text": ".Additional machine-mode status (`mstatush`) register for RV32. include::images/wavedrom/mstatushreg.edn[]", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers", + "line_range": [ + 232, + 234 + ] + }, + { + "text": "Global interrupt-enable bits, MIE and SIE, are provided for M-mode and S-mode respectively.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Privilege and Global Interrupt-Enable Stack in `mstatus` register", + "line_range": [ + 239, + 241 + ] + }, + { + "text": "These bits are primarily used to guarantee atomicity with respect to interrupt handlers in the current privilege mode.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Privilege and Global Interrupt-Enable Stack in `mstatus` register", + "line_range": [ + 239, + 241 + ] + }, + { + "text": "When a hart is executing in privilege mode x, interrupts are globally enabled when xIE=1 and globally disabled when xIE=0.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Privilege and Global Interrupt-Enable Stack in `mstatus` register", + "line_range": [ + 243, + 253 + ] + }, + { + "text": "Interrupts for lower-privilege modes, w Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Privilege and Global Interrupt-Enable Stack in `mstatus` register", + "line_range": [ + 243, + 253 + ] + }, + { + "text": "Interrupts for higher-privilege modes, y>x, are always globally enabled regardless of the setting of the global yIE bit for the higher-privilege mode.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Privilege and Global Interrupt-Enable Stack in `mstatus` register", + "line_range": [ + 243, + 253 + ] + }, + { + "text": "Higher-privilege-level code can use separate per-interrupt enable bits to disable selected higher-privilege-mode interrupts before ceding control to a lower-privilege mode.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Privilege and Global Interrupt-Enable Stack in `mstatus` register", + "line_range": [ + 243, + 253 + ] + }, + { + "text": "If supervisor mode is not implemented, then SIE and SPIE are read-only 0.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Privilege and Global Interrupt-Enable Stack in `mstatus` register", + "line_range": [ + 243, + 253 + ] + }, + { + "text": "To support nested traps, each privilege mode x that can respond to interrupts has a two-level stack of interrupt-enable bits and privilege modes. xPIE holds the value of the interrupt-enable bit active prior to the trap, and xPP holds the previous privilege mode.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Privilege and Global Interrupt-Enable Stack in `mstatus` register", + "line_range": [ + 255, + 263 + ] + }, + { + "text": "The xPP fields can only hold privilege modes up to x, so MPP is two bits wide and SPP is one bit wide.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Privilege and Global Interrupt-Enable Stack in `mstatus` register", + "line_range": [ + 255, + 263 + ] + }, + { + "text": "When a trap is taken from privilege mode y into privilege mode x, xPIE is set to the value of xIE; xIE is set to 0; and xPP is set to y.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Privilege and Global Interrupt-Enable Stack in `mstatus` register", + "line_range": [ + 255, + 263 + ] + }, + { + "text": "An MRET or SRET instruction is used to return from a trap in M-mode or S-mode respectively.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Privilege and Global Interrupt-Enable Stack in `mstatus` register", + "line_range": [ + 265, + 270 + ] + }, + { + "text": "When executing an xRET instruction, supposing xPP holds the value y, xIE is set to xPIE; the privilege mode is changed to y; xPIE is set to 1; and xPP is set to the least-privileged supported mode (U if U-mode is implemented, else M).", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Privilege and Global Interrupt-Enable Stack in `mstatus` register", + "line_range": [ + 265, + 270 + ] + }, + { + "text": "If y{ne}M, xRET also sets MPRV=0.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Privilege and Global Interrupt-Enable Stack in `mstatus` register", + "line_range": [ + 265, + 270 + ] + }, + { + "text": "xPP fields are *WARL* fields that can hold only privilege mode x and any implemented privilege mode lower than x.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Privilege and Global Interrupt-Enable Stack in `mstatus` register", + "line_range": [ + 272, + 273 + ] + }, + { + "text": "If privilege mode x is not implemented, then xPP must be read-only 0.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Privilege and Global Interrupt-Enable Stack in `mstatus` register", + "line_range": [ + 272, + 273 + ] + }, + { + "text": "A double trap typically arises during a sensitive phase in trap handling operations -- when an exception or interrupt occurs while the trap handler (the component responsible for managing these events) is in a non-reentrant state.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register", + "line_range": [ + 278, + 290 + ] + }, + { + "text": "This non-reentrancy usually occurs in the early phase of trap handling, wherein the trap handler has not yet preserved the necessary state to handle and resume from the trap.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register", + "line_range": [ + 278, + 290 + ] + }, + { + "text": "The occurrence of a trap during this phase can lead to an overwrite of critical state information, resulting in the loss of data needed to recover from the initial trap.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register", + "line_range": [ + 278, + 290 + ] + }, + { + "text": "The trap that caused this critical error condition is henceforth called the unexpected trap.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register", + "line_range": [ + 278, + 290 + ] + }, + { + "text": "Trap handlers are designed to neither enable interrupts nor cause exceptions during this phase of handling.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register", + "line_range": [ + 278, + 290 + ] + }, + { + "text": "However, managing Hardware-Error exceptions, which may occur unpredictably, presents significant challenges in trap handler implementation due to the potential risk of a double trap.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register", + "line_range": [ + 278, + 290 + ] + }, + { + "text": "The M-mode-disable-trap (`MDT`) bit is a WARL field introduced by the Smdbltrp extension.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register", + "line_range": [ + 292, + 300 + ] + }, + { + "text": "Upon reset, the `MDT` field is set to 1.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register", + "line_range": [ + 292, + 300 + ] + }, + { + "text": "When the `MDT` bit is set to 1 by an explicit CSR write, the `MIE` (Machine Interrupt Enable) bit is cleared to 0.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register", + "line_range": [ + 292, + 300 + ] + }, + { + "text": "For RV64, this clearing occurs regardless of the value written, if any, to the `MIE` bit by the same write.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register", + "line_range": [ + 292, + 300 + ] + }, + { + "text": "The `MIE` bit can only be set to 1 by an explicit CSR write if the `MDT` bit is already 0 or, for RV64, is being set to 0 by the same write (For RV32, the `MDT` bit is in `mstatush` and the `MIE` bit in `mstatus` register).", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register", + "line_range": [ + 292, + 300 + ] + }, + { + "text": "When a trap is to be taken into M-mode, if the `MDT` bit is currently 0, it is then set to 1, and the trap is delivered as expected.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register", + "line_range": [ + 302, + 309 + ] + }, + { + "text": "However, if `MDT` is already set to 1, then this is an unexpected trap.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register", + "line_range": [ + 302, + 309 + ] + }, + { + "text": "When the Smrnmi extension is implemented, a trap caused by an RNMI is not considered an unexpected trap irrespective of the state of the `MDT` bit. A trap caused by an RNMI does not set the `MDT` bit.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register", + "line_range": [ + 302, + 309 + ] + }, + { + "text": "However, a trap that occurs when executing in M-mode with `mnstatus.NMIE` set to 0 is an unexpected trap.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register", + "line_range": [ + 302, + 309 + ] + }, + { + "text": "In the event of a unexpected trap, the handling is as follows:", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register", + "line_range": [ + 311, + 311 + ] + }, + { + "text": "When the Smrnmi extension is implemented and `mnstatus.NMIE` is 1, the hart traps to the RNMI handler.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register", + "line_range": [ + 313, + 318 + ] + }, + { + "text": "To deliver this trap, the `mnepc` and `mncause` registers are written with the values that the unexpected trap would have written to the `mepc` and `mcause` registers respectively.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register", + "line_range": [ + 313, + 318 + ] + }, + { + "text": "The privilege mode information fields in the `mnstatus` register are written to indicate M-mode and its `NMIE` field is set to 0.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register", + "line_range": [ + 313, + 318 + ] + }, + { + "text": "When the Smrnmi extension is not implemented, or if the Smrnmi extension is implemented and `mnstatus.NMIE` is 0, the hart enters a critical-error state without updating any architectural state, including the `pc`.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register", + "line_range": [ + 320, + 325 + ] + }, + { + "text": "This state involves ceasing execution, disabling all interrupts (including NMIs), and asserting a `critical-error` signal to the platform.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register", + "line_range": [ + 320, + 325 + ] + }, + { + "text": "Whether performance counters and timers are updated in the critical-error state is UNSPECIFIED.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register", + "line_range": [ + 320, + 325 + ] + }, + { + "text": "When the Smdbltrp extension is implemented, executing an `MRET` instruction, or executing an `SRET` instruction while the current privilege mode is M, has the following additional effects.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register", + "line_range": [ + 327, + 332 + ] + }, + { + "text": "The `MDT` bit is set to 0.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register", + "line_range": [ + 327, + 332 + ] + }, + { + "text": "If the Ssdbltrp extension is also implemented, and the new privilege mode is U, VS, or VU, then `sstatus.SDT` is also set to 0.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register", + "line_range": [ + 327, + 332 + ] + }, + { + "text": "Additionally, if it is VU, then `vsstatus.SDT` is also set to 0.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register", + "line_range": [ + 327, + 332 + ] + }, + { + "text": "When the Smdbltrp extension is implemented, the `MNRET` instruction, provided by the Smrnmi extension, sets the `MDT` bit to 0 if the new privilege mode is not M.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register", + "line_range": [ + 334, + 336 + ] + }, + { + "text": "If the Ssdbltrp extension is also implemented, and the new privilege mode is U, VS, or VU, then `sstatus.SDT` is also set to 0.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register", + "line_range": [ + 334, + 336 + ] + }, + { + "text": "Additionally, if it is VU, then `vsstatus.SDT` is also set to 0.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Double Trap Control in `mstatus` Register", + "line_range": [ + 334, + 336 + ] + }, + { + "text": "For RV64 harts, the SXL and UXL fields are *WARL* fields that control the value of XLEN for S-mode and U-mode, respectively.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Base ISA Control in `mstatus` Register", + "line_range": [ + 341, + 344 + ] + }, + { + "text": "The encoding of these fields is the same as the MXL field of `misa`, shown in .", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Base ISA Control in `mstatus` Register", + "line_range": [ + 341, + 344 + ] + }, + { + "text": "The effective XLEN in S-mode and U-mode are termed SXLEN and UXLEN, respectively.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Base ISA Control in `mstatus` Register", + "line_range": [ + 341, + 344 + ] + }, + { + "text": "When MXLEN=32, the SXL and UXL fields do not exist, and SXLEN=32 and UXLEN=32.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Base ISA Control in `mstatus` Register", + "line_range": [ + 346, + 347 + ] + }, + { + "text": "When MXLEN=64, if S-mode is not supported, then SXL is read-only zero.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Base ISA Control in `mstatus` Register", + "line_range": [ + 349, + 352 + ] + }, + { + "text": "Otherwise, it is a *WARL* field that encodes the current value of SXLEN.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Base ISA Control in `mstatus` Register", + "line_range": [ + 349, + 352 + ] + }, + { + "text": "In particular, an implementation may make SXL be a read-only field whose value always ensures that SXLEN=MXLEN.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Base ISA Control in `mstatus` Register", + "line_range": [ + 349, + 352 + ] + }, + { + "text": "When MXLEN=64, if U-mode is not supported, then UXL is read-only zero.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Base ISA Control in `mstatus` Register", + "line_range": [ + 354, + 357 + ] + }, + { + "text": "Otherwise, it is a *WARL* field that encodes the current value of UXLEN.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Base ISA Control in `mstatus` Register", + "line_range": [ + 354, + 357 + ] + }, + { + "text": "In particular, an implementation may make UXL be a read-only field whose value always ensures that UXLEN=MXLEN or UXLEN=SXLEN.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Base ISA Control in `mstatus` Register", + "line_range": [ + 354, + 357 + ] + }, + { + "text": "If S-mode is implemented, the set of legal values that the UXL field may assume excludes those that would cause UXLEN to be greater than SXLEN.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Base ISA Control in `mstatus` Register", + "line_range": [ + 359, + 361 + ] + }, + { + "text": "Whenever XLEN in any mode is set to a value less than the widest supported XLEN, all operations must ignore source operand register bits above the configured XLEN, and must sign-extend results to fill the entire widest supported XLEN in the destination register.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Base ISA Control in `mstatus` Register", + "line_range": [ + 363, + 369 + ] + }, + { + "text": "Similarly, `pc` bits above XLEN are ignored, and when the `pc` is written, it is sign-extended to fill the widest supported XLEN.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Base ISA Control in `mstatus` Register", + "line_range": [ + 363, + 369 + ] + }, + { + "text": "Some HINT instructions are encoded as integer computational instructions that overwrite their destination register with its current value, e.g., `c.addi x8, 0`.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Base ISA Control in `mstatus` Register", + "line_range": [ + 371, + 378 + ] + }, + { + "text": "When such a HINT is executed with XLEN < MXLEN and bits MXLEN..XLEN of the destination register not all equal to bit XLEN-1, it is implementation-defined whether bits MXLEN..XLEN of the destination register are unchanged or are overwritten with copies of bit XLEN-1.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Base ISA Control in `mstatus` Register", + "line_range": [ + 371, + 378 + ] + }, + { + "text": "NOTE: This definition allows implementations to elide register write-back for some HINTs, while allowing them to execute other HINTs in the same manner as other integer computational instructions.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Base ISA Control in `mstatus` Register", + "line_range": [ + 380, + 386 + ] + }, + { + "text": "The implementation choice is observable only by privilege modes with an XLEN setting greater than the current XLEN; it is invisible to the current privilege mode.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Base ISA Control in `mstatus` Register", + "line_range": [ + 380, + 386 + ] + }, + { + "text": "The MPRV (Modify PRiVilege) bit modifies the effective privilege mode, i.e., the privilege level at which explicit memory accesses execute.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Memory Privilege in `mstatus` Register", + "line_range": [ + 390, + 399 + ] + }, + { + "text": "When MPRV=0, explicit memory accesses behave as normal, using the translation and protection mechanisms of the current privilege mode.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Memory Privilege in `mstatus` Register", + "line_range": [ + 390, + 399 + ] + }, + { + "text": "When MPRV=1, load and store memory addresses are translated and protected, and endianness is applied, as though the current privilege mode were set to MPP.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Memory Privilege in `mstatus` Register", + "line_range": [ + 390, + 399 + ] + }, + { + "text": "Instruction address-translation and protection are unaffected by the setting of MPRV. MPRV is read-only 0 if U-mode is not supported.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Memory Privilege in `mstatus` Register", + "line_range": [ + 390, + 399 + ] + }, + { + "text": "An MRET or SRET instruction that changes the privilege mode to a mode less privileged than M also sets MPRV=0.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Memory Privilege in `mstatus` Register", + "line_range": [ + 401, + 402 + ] + }, + { + "text": "The MXR (Make eXecutable Readable) bit modifies the privilege with which loads access virtual memory.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Memory Privilege in `mstatus` Register", + "line_range": [ + 404, + 408 + ] + }, + { + "text": "When MXR=0, only loads from pages marked readable (R=1 in ) will succeed.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Memory Privilege in `mstatus` Register", + "line_range": [ + 404, + 408 + ] + }, + { + "text": "When MXR=1, loads from pages marked either readable or executable (R=1 or X=1) will succeed. MXR has no effect when page-based virtual memory is not in effect. MXR is read-only 0 if S-mode is not supported.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Memory Privilege in `mstatus` Register", + "line_range": [ + 404, + 408 + ] + }, + { + "text": "The SUM (permit Supervisor User Memory access) bit modifies the privilege with which S-mode loads and stores access virtual memory.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Memory Privilege in `mstatus` Register", + "line_range": [ + 410, + 417 + ] + }, + { + "text": "When SUM=0, S-mode memory accesses to pages that are accessible by U-mode (U=1 in ) will fault.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Memory Privilege in `mstatus` Register", + "line_range": [ + 410, + 417 + ] + }, + { + "text": "When SUM=1, these accesses are permitted. SUM has no effect when page-based virtual memory is not in effect.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Memory Privilege in `mstatus` Register", + "line_range": [ + 410, + 417 + ] + }, + { + "text": "Note that, while SUM is ordinarily ignored when not executing in S-mode, it is in effect when MPRV=1 and MPP=S. SUM is read-only 0 if S-mode is not supported or if `satp`.MODE is read-only 0.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Memory Privilege in `mstatus` Register", + "line_range": [ + 410, + 417 + ] + }, + { + "text": "The MXR and SUM mechanisms only affect the interpretation of permissions encoded in page-table entries.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Memory Privilege in `mstatus` Register", + "line_range": [ + 419, + 422 + ] + }, + { + "text": "In particular, they have no impact on whether access-fault exceptions are raised due to PMAs or PMP.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Memory Privilege in `mstatus` Register", + "line_range": [ + 419, + 422 + ] + }, + { + "text": "The MBE, SBE, and UBE bits in `mstatus` and `mstatush` are *WARL* fields that control the endianness of memory accesses other than instruction fetches.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Endianness Control in `mstatus` and `mstatush` Registers", + "line_range": [ + 426, + 428 + ] + }, + { + "text": "Instruction fetches are always little-endian.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Endianness Control in `mstatus` and `mstatush` Registers", + "line_range": [ + 426, + 428 + ] + }, + { + "text": "MBE controls whether non-instruction-fetch memory accesses made from M-mode (assuming `mstatus`.MPRV=0) are little-endian (MBE=0) or big-endian (MBE=1).", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Endianness Control in `mstatus` and `mstatush` Registers", + "line_range": [ + 430, + 433 + ] + }, + { + "text": "If S-mode is not supported, SBE is read-only 0.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Endianness Control in `mstatus` and `mstatush` Registers", + "line_range": [ + 435, + 438 + ] + }, + { + "text": "Otherwise, SBE controls whether explicit load and store memory accesses made from S-mode are little-endian (SBE=0) or big-endian (SBE=1).", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Endianness Control in `mstatus` and `mstatush` Registers", + "line_range": [ + 435, + 438 + ] + }, + { + "text": "If U-mode is not supported, UBE is read-only 0.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Endianness Control in `mstatus` and `mstatush` Registers", + "line_range": [ + 440, + 443 + ] + }, + { + "text": "Otherwise, UBE controls whether explicit load and store memory accesses made from U-mode are little-endian (UBE=0) or big-endian (UBE=1).", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Endianness Control in `mstatus` and `mstatush` Registers", + "line_range": [ + 440, + 443 + ] + }, + { + "text": "For implicit accesses to supervisor-level memory management data structures, such as page tables, endianness is always controlled by SBE.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Endianness Control in `mstatus` and `mstatush` Registers", + "line_range": [ + 445, + 450 + ] + }, + { + "text": "Since changing SBE alters the implementation’s interpretation of these data structures, if any such data structures remain in use across a change to SBE, M-mode software must follow such a change to SBE by executing an SFENCE.VMA instruction with rs1=`x0` and rs2=`x0`.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Endianness Control in `mstatus` and `mstatush` Registers", + "line_range": [ + 445, + 450 + ] + }, + { + "text": "If S-mode is supported, an implementation may make SBE be a read-only copy of MBE.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Endianness Control in `mstatus` and `mstatush` Registers", + "line_range": [ + 452, + 455 + ] + }, + { + "text": "If U-mode is supported, an implementation may make UBE be a read-only copy of either MBE or SBE.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Endianness Control in `mstatus` and `mstatush` Registers", + "line_range": [ + 452, + 455 + ] + }, + { + "text": "The TVM (Trap Virtual Memory) bit is a *WARL* field that supports intercepting supervisor virtual-memory management operations.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Virtualization Support in `mstatus` Register", + "line_range": [ + 460, + 466 + ] + }, + { + "text": "When TVM=1, attempts to read or write the `satp` CSR or execute an SFENCE.VMA or SINVAL.VMA instruction while executing in S-mode will raise an illegal-instruction exception.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Virtualization Support in `mstatus` Register", + "line_range": [ + 460, + 466 + ] + }, + { + "text": "When TVM=0, these operations are permitted in S-mode. TVM is read-only 0 when S-mode is not supported.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Virtualization Support in `mstatus` Register", + "line_range": [ + 460, + 466 + ] + }, + { + "text": "The TW (Timeout Wait) bit is a *WARL* field that supports intercepting the WFI instruction (see ).", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Virtualization Support in `mstatus` Register", + "line_range": [ + 468, + 480 + ] + }, + { + "text": "When TW=0, the WFI instruction may execute in modes less privileged than M when not prevented for some other reason.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Virtualization Support in `mstatus` Register", + "line_range": [ + 468, + 480 + ] + }, + { + "text": "When TW=1, then if WFI is executed in any less-privileged mode, and it does not complete within an implementation-specific, bounded time limit, the WFI instruction causes an illegal-instruction exception.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Virtualization Support in `mstatus` Register", + "line_range": [ + 468, + 480 + ] + }, + { + "text": "An implementation may have WFI always raise an illegal-instruction exception in modes less privileged than M when TW=1, even if there are pending globally-disabled interrupts when the instruction is executed. TW is read-only 0 when there are no modes less privileged than M.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Virtualization Support in `mstatus` Register", + "line_range": [ + 468, + 480 + ] + }, + { + "text": "When S-mode is implemented, then executing WFI in U-mode causes an illegal-instruction exception, regardless of the value of the TW bit, unless the instruction completes within an implementation-specific, bounded time limit.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Virtualization Support in `mstatus` Register", + "line_range": [ + 482, + 484 + ] + }, + { + "text": "The TSR (Trap SRET) bit is a *WARL* field that supports intercepting the supervisor exception return instruction, SRET.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Virtualization Support in `mstatus` Register", + "line_range": [ + 486, + 491 + ] + }, + { + "text": "When TSR=1, attempts to execute SRET while executing in S-mode will raise an illegal-instruction exception.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Virtualization Support in `mstatus` Register", + "line_range": [ + 486, + 491 + ] + }, + { + "text": "When TSR=0, this operation is permitted in S-mode. TSR is read-only 0 when S-mode is not supported.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Virtualization Support in `mstatus` Register", + "line_range": [ + 486, + 491 + ] + }, + { + "text": "Supporting substantial extensions is one of the primary goals of RISC-V, and hence we define a standard interface to allow unchanged privileged-mode code, particularly a supervisor-level OS, to support arbitrary user-mode state extensions.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "line_range": [ + 495, + 498 + ] + }, + { + "text": "The FS[1:0] and VS[1:0] *WARL* fields and the XS[1:0] read-only field are used to reduce the cost of context save and restore by setting and tracking the current state of the floating-point unit and any other user-mode extensions respectively.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "line_range": [ + 500, + 517 + ] + }, + { + "text": "The FS field encodes the status of the floating-point unit state, including the floating-point registers `f0`–`f31` and the CSRs `fcsr`, `frm`, and `fflags`.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "line_range": [ + 500, + 517 + ] + }, + { + "text": "The VS field encodes the status of the vector extension state, including the vector registers `v0`–`v31` and the CSRs `vcsr`, `vxrm`, `vxsat`, `vstart`, `vl`, `vtype`, and `vlenb`.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "line_range": [ + 500, + 517 + ] + }, + { + "text": "The XS field encodes the status of additional user-mode extensions and associated state.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "line_range": [ + 500, + 517 + ] + }, + { + "text": "These fields can be checked by a context switch routine to quickly determine whether a state save or restore is required.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "line_range": [ + 500, + 517 + ] + }, + { + "text": "If a save or restore is required, additional instructions and CSRs are typically required to effect and optimize the process.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "line_range": [ + 500, + 517 + ] + }, + { + "text": "The FS, VS, and XS fields use the same status encoding as shown in , with the four possible status values being Off, Initial, Clean, and Dirty.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "line_range": [ + 519, + 521 + ] + }, + { + "text": ".Encoding of FS[1:0], VS[1:0], and XS[1:0] status fields | |Status |FS and VS Meaning |XS Meaning |0 + 1 + 2 + 3 |Off + Initial + Clean + Dirty |All off + None dirty or clean, some on + None dirty, some clean + Some dirty |", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "line_range": [ + 523, + 540 + ] + }, + { + "text": "If the F extension is implemented, the FS field shall not be read-only zero.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "line_range": [ + 542, + 543 + ] + }, + { + "text": "If neither the F extension nor S-mode is implemented, then FS is read-only zero.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "line_range": [ + 545, + 547 + ] + }, + { + "text": "If S-mode is implemented but the F extension is not, FS may optionally be read-only zero.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "line_range": [ + 545, + 547 + ] + }, + { + "text": "If the `v` registers are implemented, the VS field shall not be read-only zero.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "line_range": [ + 549, + 550 + ] + }, + { + "text": "If neither the `v` registers nor S-mode is implemented, then VS is read-only zero.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "line_range": [ + 552, + 555 + ] + }, + { + "text": "If S-mode is implemented but the `v` registers are not, VS may optionally be read-only zero.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "line_range": [ + 552, + 555 + ] + }, + { + "text": "In harts without additional user extensions requiring new state, the XS field is read-only zero.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "line_range": [ + 557, + 562 + ] + }, + { + "text": "Every additional extension with state provides a CSR field that encodes the equivalent of the XS states.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "line_range": [ + 557, + 562 + ] + }, + { + "text": "The XS field represents a summary of all extensions' status as shown in .", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "line_range": [ + 557, + 562 + ] + }, + { + "text": "The SD bit is a read-only bit that summarizes whether either the FS, VS, or XS fields signal the presence of some dirty state that will require saving extended user context to memory.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "line_range": [ + 564, + 568 + ] + }, + { + "text": "If FS, XS, and VS are all read-only zero, then SD is also always zero.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "line_range": [ + 564, + 568 + ] + }, + { + "text": "When an extension's status is set to Off, any instruction that attempts to read or write the corresponding state will cause an illegal-instruction exception.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "line_range": [ + 570, + 579 + ] + }, + { + "text": "When the status is Initial, the corresponding state should have an initial constant value.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "line_range": [ + 570, + 579 + ] + }, + { + "text": "When the status is Clean, the corresponding state is potentially different from the initial value, but matches the last value stored on a context swap.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "line_range": [ + 570, + 579 + ] + }, + { + "text": "When the status is Dirty, the corresponding state has potentially been modified since the last context save.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "line_range": [ + 570, + 579 + ] + }, + { + "text": "During a context save, the responsible privileged code need only write out the corresponding state if its status is Dirty, and can then reset the extension's status to Clean.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "line_range": [ + 581, + 589 + ] + }, + { + "text": "During a context restore, the context need only be loaded from memory if the status is Clean (it should never be Dirty at restore).", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "line_range": [ + 581, + 589 + ] + }, + { + "text": "If the status is Initial, the context must be set to an initial constant value on context restore to avoid a security hole, but this can be done without accessing memory.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "line_range": [ + 581, + 589 + ] + }, + { + "text": "For example, the floating-point registers can all be initialized to the immediate value 0.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "line_range": [ + 581, + 589 + ] + }, + { + "text": "The FS and XS fields are read by the privileged code before saving the context.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "line_range": [ + 591, + 596 + ] + }, + { + "text": "The FS field is set directly by privileged code when resuming a user context, while the XS field is set indirectly by writing to the status register of the individual extensions.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "line_range": [ + 591, + 596 + ] + }, + { + "text": "The status fields will also be updated during execution of instructions, regardless of privilege mode.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "line_range": [ + 591, + 596 + ] + }, + { + "text": "Extensions to the user-mode ISA often include additional user-mode state, and this state can be considerably larger than the base integer registers.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "line_range": [ + 598, + 604 + ] + }, + { + "text": "The extensions might only be used for some applications, or might only be needed for short phases within a single application.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "line_range": [ + 598, + 604 + ] + }, + { + "text": "To improve performance, the user-mode extension can define additional instructions to allow user-mode software to return the unit to an initial state or even to turn off the unit.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "line_range": [ + 598, + 604 + ] + }, + { + "text": "For example, a coprocessor might require to be configured before use and can be \"unconfigured\" after use.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "line_range": [ + 606, + 614 + ] + }, + { + "text": "The unconfigured state would be represented as the Initial state for context save.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "line_range": [ + 606, + 614 + ] + }, + { + "text": "If the same application remains running between the unconfigure and the next configure (which would set status to Dirty), there is no need to actually reinitialize the state at the unconfigure instruction, as all state is local to the user process, i.e., the Initial state may only cause the coprocessor state to be initialized to a constant value at context restore, not at every unconfigure.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "line_range": [ + 606, + 614 + ] + }, + { + "text": "Executing a user-mode instruction to disable a unit and place it into the Off state will cause an illegal-instruction exception to be raised if any subsequent instruction tries to use the unit before it is turned back on. A user-mode instruction to turn a unit on must also ensure the unit's state is properly initialized, as the unit might have been used by another context meantime.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "line_range": [ + 616, + 621 + ] + }, + { + "text": "Changing the setting of FS has no effect on the contents of the floating-point register state.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "line_range": [ + 623, + 628 + ] + }, + { + "text": "In particular, setting FS=Off does not destroy the state, nor does setting FS=Initial clear the contents.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "line_range": [ + 623, + 628 + ] + }, + { + "text": "Similarly, the setting of VS has no effect on the contents of the vector register state.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "line_range": [ + 623, + 628 + ] + }, + { + "text": "Other extensions, however, might not preserve state when set to Off.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "line_range": [ + 623, + 628 + ] + }, + { + "text": "Implementations may choose to track the dirtiness of the floating-point register state imprecisely by reporting the state to be dirty even when it has not been modified.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "line_range": [ + 630, + 639 + ] + }, + { + "text": "On some implementations, some instructions that do not mutate the floating-point state may cause the state to transition from Initial or Clean to Dirty.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "line_range": [ + 630, + 639 + ] + }, + { + "text": "On other implementations, dirtiness might not be tracked at all, in which case the valid FS states are Off and Dirty, and an attempt to set FS to Initial or Clean causes it to be set to Dirty.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "line_range": [ + 630, + 639 + ] + }, + { + "text": "If an instruction explicitly or implicitly writes a floating-point register or the `fcsr` but does not alter its contents, and FS=Initial or FS=Clean, it is implementation-defined whether FS transitions to Dirty.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "line_range": [ + 641, + 644 + ] + }, + { + "text": "Implementations may choose to track the dirtiness of the vector register state in an analogous imprecise fashion, including possibly setting VS to Dirty when software attempts to set VS=Initial or VS=Clean.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "line_range": [ + 646, + 651 + ] + }, + { + "text": "When VS=Initial or VS=Clean, it is implementation-defined whether an instruction that writes a vector register or vector CSR but does not alter its contents causes VS to transition to Dirty.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "line_range": [ + 646, + 651 + ] + }, + { + "text": "shows all the possible state transitions for the FS, VS, or XS status bits.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "line_range": [ + 653, + 656 + ] + }, + { + "text": "Note that the standard floating-point and vector extensions do not support user-mode unconfigure or disable/enable instructions.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "line_range": [ + 653, + 656 + ] + }, + { + "text": ".FS, VS, and XS state transitions. [width=75,align=center,float=center,cols=\"<,<,<,<,<\"] | |Current State + Action |Off |Initial |Clean |Dirty |", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "line_range": [ + 660, + 666 + ] + }, + { + "text": "[width=75,align=center,float=center,cols=\"<,<,<,<,<\"] | 5+^|At context save in privileged code", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "line_range": [ + 668, + 670 + ] + }, + { + "text": "|Save state? + Next state |No + Off |No + Initial |No + Clean |Yes + Clean |", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "line_range": [ + 672, + 682 + ] + }, + { + "text": "[width=75,align=center,float=center,cols=\"<,<,<,<,<\"] | 5+^|At context restore in privileged code", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "line_range": [ + 684, + 686 + ] + }, + { + "text": "|Restore state? + Next state |No + Off |Yes, to initial + Initial |Yes, from memory + Clean |N/A + N/A |", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "line_range": [ + 688, + 698 + ] + }, + { + "text": "[width=75,align=center,float=center,cols=\"<,<,<,<,<\"] | 5+^|Execute instruction to read state", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "line_range": [ + 700, + 702 + ] + }, + { + "text": "|Action? + Next state |Exception + Off |Execute + Initial |Execute + Clean |Execute + Dirty |", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "line_range": [ + 704, + 714 + ] + }, + { + "text": "[width=75,align=center,float=center,cols=\"<,<,<,<,<\"] | 5+^|Execute instruction that possibly modifies state, including configuration", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "line_range": [ + 716, + 718 + ] + }, + { + "text": "|Action? + Next state |Exception + Off |Execute + Dirty |Execute + Dirty |Execute + Dirty |", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "line_range": [ + 720, + 730 + ] + }, + { + "text": "[width=75,align=center,float=center,cols=\"<,<,<,<,<\"] | 5+^|Execute instruction to unconfigure unit", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "line_range": [ + 732, + 734 + ] + }, + { + "text": "|Action? + Next state |Exception + Off |Execute + Initial |Execute + Initial |Execute + Initial |", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "line_range": [ + 736, + 746 + ] + }, + { + "text": "[width=75,align=center,float=center,cols=\"<,<,<,<,<\"] | 5+^|Execute instruction to disable unit", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "line_range": [ + 748, + 750 + ] + }, + { + "text": "|Action? + Next state |Execute + Off |Execute + Off |Execute + Off |Execute + Off |", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "line_range": [ + 752, + 762 + ] + }, + { + "text": "[width=75,align=center,float=center,cols=\"<,<,<,<,<\"] | 5+^|Execute instruction to enable unit", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "line_range": [ + 764, + 766 + ] + }, + { + "text": "|Action? + Next state |Execute + Initial |Execute + Initial |Execute + Initial |Execute + Initial |", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "line_range": [ + 768, + 778 + ] + }, + { + "text": "Standard privileged instructions to initialize, save, and restore extension state are provided to insulate privileged code from details of the added extension state by treating the state as an opaque object.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "line_range": [ + 780, + 782 + ] + }, + { + "text": "The XS field provides a summary of all added extension state, but additional microarchitectural bits might be maintained in the extension to further reduce context save and restore overhead.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "line_range": [ + 784, + 786 + ] + }, + { + "text": "The SD bit is read-only and is set when either the FS, VS, or XS bits encode a Dirty state (i.e., `SD=(FS0b11 OR XS0b11 OR VS0b11)`).", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "line_range": [ + 788, + 791 + ] + }, + { + "text": "This allows privileged code to quickly determine when no additional context save is required beyond the integer register set and `pc`.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "line_range": [ + 788, + 791 + ] + }, + { + "text": "The floating-point unit state is always initialized, saved, and restored using standard instructions (F, D, and/or Q), and privileged code must be aware of FLEN to determine the appropriate space to reserve for each `f` register.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "line_range": [ + 793, + 796 + ] + }, + { + "text": "Machine and Supervisor modes share a single copy of the FS, VS, and XS bits.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "line_range": [ + 798, + 803 + ] + }, + { + "text": "Supervisor-level software normally uses the FS, VS, and XS bits directly to record the status with respect to the supervisor-level saved context.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "line_range": [ + 798, + 803 + ] + }, + { + "text": "Machine-level software must be more conservative in saving and restoring the extension state in their corresponding version of the context.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Extension Context Status in `mstatus` Register", + "line_range": [ + 798, + 803 + ] + }, + { + "text": "The Zicfilp extension adds the `SPELP` and `MPELP` fields that hold the previous `ELP`, and are updated as specified in .", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Previous Expected Landing Pad (ELP) State in `mstatus` Register", + "line_range": [ + 807, + 809 + ] + }, + { + "text": "The *x*`PELP` fields are encoded as follows:", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Previous Expected Landing Pad (ELP) State in `mstatus` Register", + "line_range": [ + 807, + 809 + ] + }, + { + "text": "* 0 - `NOLPEXPECTED` - no landing pad instruction expected. * 1 - `LPEXPECTED` - a landing pad instruction is expected.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Status (`mstatus` and `mstatush`) Registers > Previous Expected Landing Pad (ELP) State in `mstatus` Register", + "line_range": [ + 811, + 813 + ] + }, + { + "text": "The `mtvec` register is an MXLEN-bit *WARL* read/write register that holds trap vector configuration, consisting of a vector base address (BASE) and a vector mode (MODE).", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap-Vector Base-Address (`mtvec`) Register", + "line_range": [ + 817, + 819 + ] + }, + { + "text": ".Encoding of mtvec MODE field. include::images/bytefield/mtvec.edn[]", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap-Vector Base-Address (`mtvec`) Register", + "line_range": [ + 821, + 823 + ] + }, + { + "text": "The `mtvec` register must always be implemented, but can contain a read-only value.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap-Vector Base-Address (`mtvec`) Register", + "line_range": [ + 825, + 835 + ] + }, + { + "text": "If `mtvec` is writable, the set of values the register may hold can vary by implementation.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap-Vector Base-Address (`mtvec`) Register", + "line_range": [ + 825, + 835 + ] + }, + { + "text": "The value in the BASE field must always be aligned on a 4-byte boundary, and the MODE setting may impose additional alignment constraints on the value in the BASE field.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap-Vector Base-Address (`mtvec`) Register", + "line_range": [ + 825, + 835 + ] + }, + { + "text": "Note that the CSR contains only bits XLEN-1 through 2 of the address BASE.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap-Vector Base-Address (`mtvec`) Register", + "line_range": [ + 825, + 835 + ] + }, + { + "text": "When used as an address, the lower two bits are filled with zeroes to obtain an XLEN-bit address that is always aligned on a 4-byte boundary.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap-Vector Base-Address (`mtvec`) Register", + "line_range": [ + 825, + 835 + ] + }, + { + "text": ".Encoding of mtvec MODE field. | |Value |Name |Description |0 + 1 + {ge}2 |Direct + Vectored + --- |All traps set `pc` to BASE. + Asynchronous interrupts set `pc` to BASE+4{times}cause. + Reserved |", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap-Vector Base-Address (`mtvec`) Register", + "line_range": [ + 837, + 851 + ] + }, + { + "text": "The encoding of the MODE field is shown in .", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap-Vector Base-Address (`mtvec`) Register", + "line_range": [ + 853, + 860 + ] + }, + { + "text": "When MODE=Direct, all traps into machine mode cause the `pc` to be set to the address in the BASE field.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap-Vector Base-Address (`mtvec`) Register", + "line_range": [ + 853, + 860 + ] + }, + { + "text": "When MODE=Vectored, all synchronous exceptions into machine mode cause the `pc` to be set to the address in the BASE field, whereas interrupts cause the `pc` to be set to the address in the BASE field plus four times the interrupt cause number.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap-Vector Base-Address (`mtvec`) Register", + "line_range": [ + 853, + 860 + ] + }, + { + "text": "For example, a machine-mode timer interrupt (see ) causes the `pc` to be set to BASE+`0x1c`.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap-Vector Base-Address (`mtvec`) Register", + "line_range": [ + 853, + 860 + ] + }, + { + "text": "An implementation may have different alignment constraints for different modes.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap-Vector Base-Address (`mtvec`) Register", + "line_range": [ + 862, + 864 + ] + }, + { + "text": "In particular, MODE=Vectored may have stricter alignment constraints than MODE=Direct.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap-Vector Base-Address (`mtvec`) Register", + "line_range": [ + 862, + 864 + ] + }, + { + "text": "By default, all traps at any privilege level are handled in machine mode, though a machine-mode handler can redirect traps back to the appropriate level with the MRET instruction ().", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Delegation (`medeleg` and `mideleg`) Registers", + "line_range": [ + 868, + 876 + ] + }, + { + "text": "To increase performance, implementations can provide individual read/write bits within `medeleg` and `mideleg` to indicate that certain exceptions and interrupts should be processed directly by a lower privilege level.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Delegation (`medeleg` and `mideleg`) Registers", + "line_range": [ + 868, + 876 + ] + }, + { + "text": "The machine exception delegation register (`medeleg`) is a 64-bit read/write register.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Delegation (`medeleg` and `mideleg`) Registers", + "line_range": [ + 868, + 876 + ] + }, + { + "text": "The machine interrupt delegation (`mideleg`) register is an MXLEN-bit read/write register.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Delegation (`medeleg` and `mideleg`) Registers", + "line_range": [ + 868, + 876 + ] + }, + { + "text": "In harts with S-mode, the `medeleg` and `mideleg` registers must exist, and setting a bit in `medeleg` or `mideleg` will delegate the corresponding trap, when occurring in S-mode or U-mode, to the S-mode trap handler.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Delegation (`medeleg` and `mideleg`) Registers", + "line_range": [ + 878, + 882 + ] + }, + { + "text": "In harts without S-mode, the `medeleg` and `mideleg` registers should not exist.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Delegation (`medeleg` and `mideleg`) Registers", + "line_range": [ + 878, + 882 + ] + }, + { + "text": "When a trap is delegated to S-mode, the `scause` register is written with the trap cause; the `sepc` register is written with the virtual address of the instruction that took the trap; the `stval` register is written with an exception-specific datum; the SPP field of `mstatus` is written with the active privilege mode at the time of the trap; the SPIE field of `mstatus` is written with the value of the SIE field at the time of the trap; and the SIE field of `mstatus` is cleared.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Delegation (`medeleg` and `mideleg`) Registers", + "line_range": [ + 884, + 893 + ] + }, + { + "text": "The `mcause`, `mepc`, and `mtval` registers and the MPP and MPIE fields of `mstatus` are not written.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Delegation (`medeleg` and `mideleg`) Registers", + "line_range": [ + 884, + 893 + ] + }, + { + "text": "An implementation can choose to subset the delegatable traps, with the supported delegatable bits found by writing one to every bit location, then reading back the value in `medeleg` or `mideleg` to see which bit positions hold a one.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Delegation (`medeleg` and `mideleg`) Registers", + "line_range": [ + 895, + 898 + ] + }, + { + "text": "An implementation shall not have any bits of `medeleg` be read-only one, i.e., any synchronous trap that can be delegated must support not being delegated.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Delegation (`medeleg` and `mideleg`) Registers", + "line_range": [ + 900, + 905 + ] + }, + { + "text": "Similarly, an implementation shall not fix as read-only one any bits of `mideleg` corresponding to machine-level interrupts (but may do so for lower-level interrupts).", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Delegation (`medeleg` and `mideleg`) Registers", + "line_range": [ + 900, + 905 + ] + }, + { + "text": "Traps never transition from a more-privileged mode to a less-privileged mode.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Delegation (`medeleg` and `mideleg`) Registers", + "line_range": [ + 907, + 914 + ] + }, + { + "text": "For example, if M-mode has delegated illegal-instruction exceptions to S-mode, and M-mode software later executes an illegal instruction, the trap is taken in M-mode, rather than being delegated to S-mode.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Delegation (`medeleg` and `mideleg`) Registers", + "line_range": [ + 907, + 914 + ] + }, + { + "text": "By contrast, traps may be taken horizontally.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Delegation (`medeleg` and `mideleg`) Registers", + "line_range": [ + 907, + 914 + ] + }, + { + "text": "Using the same example, if M-mode has delegated illegal-instruction exceptions to S-mode, and S-mode software later executes an illegal instruction, the trap is taken in S-mode.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Delegation (`medeleg` and `mideleg`) Registers", + "line_range": [ + 907, + 914 + ] + }, + { + "text": "Delegated interrupts result in the interrupt being masked at the delegator privilege level.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Delegation (`medeleg` and `mideleg`) Registers", + "line_range": [ + 916, + 921 + ] + }, + { + "text": "For example, if the supervisor timer interrupt (STI) is delegated to S-mode by setting `mideleg`[5], STIs will not be taken when executing in M-mode.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Delegation (`medeleg` and `mideleg`) Registers", + "line_range": [ + 916, + 921 + ] + }, + { + "text": "By contrast, if `mideleg`[5] is clear, STIs can be taken in any mode and regardless of current mode will transfer control to M-mode.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Delegation (`medeleg` and `mideleg`) Registers", + "line_range": [ + 916, + 921 + ] + }, + { + "text": ".Machine Exception Delegation (`medeleg`) register. include::images/bytefield/medeleg.edn[]", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Delegation (`medeleg` and `mideleg`) Registers", + "line_range": [ + 923, + 925 + ] + }, + { + "text": "`medeleg` has a bit position allocated for every synchronous exception shown in , with the index of the bit position equal to the value returned in the `mcause` register (i.e., setting bit 8 allows user-mode environment calls to be delegated to a lower-privilege trap handler).", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Delegation (`medeleg` and `mideleg`) Registers", + "line_range": [ + 927, + 931 + ] + }, + { + "text": "When XLEN=32, `medelegh` is a 32-bit read/write register that aliases bits 63:32 of `medeleg`.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Delegation (`medeleg` and `mideleg`) Registers", + "line_range": [ + 933, + 935 + ] + }, + { + "text": "The `medelegh` register does not exist when XLEN=64.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Delegation (`medeleg` and `mideleg`) Registers", + "line_range": [ + 933, + 935 + ] + }, + { + "text": ".Machine Interrupt Delegation (`mideleg`) Register. include::images/bytefield/mideleg.edn[]", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Delegation (`medeleg` and `mideleg`) Registers", + "line_range": [ + 937, + 939 + ] + }, + { + "text": "`mideleg` holds trap delegation bits for individual interrupts, with the layout of bits matching those in the `mip` register (i.e., STIP interrupt delegation control is located in bit 5).", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Delegation (`medeleg` and `mideleg`) Registers", + "line_range": [ + 941, + 943 + ] + }, + { + "text": "For exceptions that cannot occur in less privileged modes, the corresponding `medeleg` bits should be read-only zero.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Delegation (`medeleg` and `mideleg`) Registers", + "line_range": [ + 945, + 947 + ] + }, + { + "text": "In particular, `medeleg`[11] is read-only zero.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Delegation (`medeleg` and `mideleg`) Registers", + "line_range": [ + 945, + 947 + ] + }, + { + "text": "The `medeleg`[16] is read-only zero as double trap is not delegatable.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Delegation (`medeleg` and `mideleg`) Registers", + "line_range": [ + 949, + 949 + ] + }, + { + "text": "The `mip` register is an MXLEN-bit read/write register containing information on pending interrupts, while `mie` is the corresponding MXLEN-bit read/write register containing interrupt enable bits.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "line_range": [ + 953, + 959 + ] + }, + { + "text": "Interrupt cause number i (as reported in CSR `mcause`, ) corresponds with bit i in both `mip` and `mie`.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "line_range": [ + 953, + 959 + ] + }, + { + "text": "Bits 15:0 are allocated to standard interrupt causes only, while bits 16 and above are designated for platform use.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "line_range": [ + 953, + 959 + ] + }, + { + "text": "NOTE: Interrupts designated for platform use may be designated for custom use at the platform's discretion.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "line_range": [ + 961, + 962 + ] + }, + { + "text": ".Machine Interrupt-Pending (`mip`) register. include::images/bytefield/mideleg.edn[]", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "line_range": [ + 964, + 966 + ] + }, + { + "text": ".Machine Interrupt-Enable (`mie`) register include::images/bytefield/mideleg.edn[]", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "line_range": [ + 968, + 970 + ] + }, + { + "text": "An interrupt i will trap to M-mode (causing the privilege mode to change to M-mode) if all of the following are true: (a) either the current privilege mode is M and the MIE bit in the `mstatus` register is set, or the current privilege mode has less privilege than M-mode; (b) bit i is set in both `mip` and `mie`; and (c) if register `mideleg` exists, bit i is not set in `mideleg`.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "line_range": [ + 972, + 977 + ] + }, + { + "text": "These conditions for an interrupt trap to occur must be evaluated in a bounded amount of time from when an interrupt becomes, or ceases to be, pending in `mip`, and must also be evaluated immediately following the execution of an xRET instruction or an explicit write to a CSR on which these interrupt trap conditions expressly depend (including `mip`, `mie`, `mstatus`, and `mideleg`).", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "line_range": [ + 979, + 984 + ] + }, + { + "text": "Interrupts to M-mode take priority over any interrupts to lower privilege modes.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "line_range": [ + 986, + 987 + ] + }, + { + "text": "Each individual bit in register `mip` may be writable or may be read-only.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "line_range": [ + 989, + 993 + ] + }, + { + "text": "When bit i in `mip` is writable, a pending interrupt i can be cleared by writing 0 to this bit.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "line_range": [ + 989, + 993 + ] + }, + { + "text": "If interrupt i can become pending but bit i in `mip` is read-only, the implementation must provide some other mechanism for clearing the pending interrupt.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "line_range": [ + 989, + 993 + ] + }, + { + "text": "A bit in `mie` must be writable if the corresponding interrupt can ever become pending.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "line_range": [ + 995, + 996 + ] + }, + { + "text": "Bits of `mie` that are not writable must be read-only zero.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "line_range": [ + 995, + 996 + ] + }, + { + "text": "The standard portions (bits 15:0) of the `mip` and `mie` registers are formatted as shown in and respectively.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "line_range": [ + 998, + 999 + ] + }, + { + "text": ".Standard portion (bits 15:0) of `mip`. include::images/bytefield/mipreg-standard.edn[]", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "line_range": [ + 1001, + 1003 + ] + }, + { + "text": ".Standard portion (bits 15:0) of `mie`. include::images/bytefield/miereg-standard.edn[]", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "line_range": [ + 1005, + 1007 + ] + }, + { + "text": "Bits `mip`.MEIP and `mie`.MEIE are the interrupt-pending and interrupt-enable bits for machine-level external interrupts. MEIP is read-only in `mip`, and is set and cleared by a platform-specific interrupt controller.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "line_range": [ + 1009, + 1012 + ] + }, + { + "text": "Bits `mip`.MTIP and `mie`.MTIE are the interrupt-pending and interrupt-enable bits for machine timer interrupts. MTIP is read-only in the `mip` register, and is cleared by writing to the memory-mapped machine-mode timer compare register.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "line_range": [ + 1014, + 1017 + ] + }, + { + "text": "Bits `mip`.MSIP and `mie`.MSIE are the interrupt-pending and interrupt-enable bits for machine-level software interrupts. MSIP is read-only in `mip`, and is written by accesses to memory-mapped control registers, which are used to provide machine-level interprocessor interrupts.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "line_range": [ + 1019, + 1022 + ] + }, + { + "text": "A hart's memory-mapped `msip` register is a 32-bit read/write register, where bits 31--1 read as zero and bit 0 contains the MSIP bit.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "line_range": [ + 1024, + 1031 + ] + }, + { + "text": "When the memory-mapped `msip` register changes, it is guaranteed to be reflected in `mip`.MSIP eventually, but not necessarily immediately.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "line_range": [ + 1024, + 1031 + ] + }, + { + "text": "If a system has only one hart, or if a platform standard supports the delivery of machine-level interprocessor interrupts through external interrupts (MEI) instead, then `mip`.MSIP and `mie`.MSIE may both be read-only zeros.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "line_range": [ + 1024, + 1031 + ] + }, + { + "text": "If supervisor mode is not implemented, bits SEIP, STIP, and SSIP of `mip` and SEIE, STIE, and SSIE of `mie` are read-only zeros.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "line_range": [ + 1033, + 1034 + ] + }, + { + "text": "If supervisor mode is implemented, bits `mip`.SEIP and `mie`.SEIE are the interrupt-pending and interrupt-enable bits for supervisor-level external interrupts. SEIP is writable in `mip`, and may be written by M-mode software to indicate to S-mode that an external interrupt is pending.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "line_range": [ + 1036, + 1049 + ] + }, + { + "text": "Additionally, the platform-level interrupt controller may generate supervisor-level external interrupts.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "line_range": [ + 1036, + 1049 + ] + }, + { + "text": "Supervisor-level external interrupts are made pending based on the logical-OR of the software-writable SEIP bit and the signal from the external interrupt controller.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "line_range": [ + 1036, + 1049 + ] + }, + { + "text": "When `mip` is read with a CSR instruction, the value of the SEIP bit returned in the `rd` destination register is the logical-OR of the software-writable bit and the interrupt signal from the interrupt controller, but the signal from the interrupt controller is not used to calculate the value written to SEIP.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "line_range": [ + 1036, + 1049 + ] + }, + { + "text": "Only the software-writable SEIP bit participates in the read-modify-write sequence of a CSRRS or CSRRC instruction.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "line_range": [ + 1036, + 1049 + ] + }, + { + "text": "If supervisor mode is implemented, its `mip`.STIP and `mie`.STIE are the interrupt-pending and interrupt-enable bits for supervisor-level timer interrupts.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "line_range": [ + 1051, + 1058 + ] + }, + { + "text": "If the stimecmp register is not implemented, STIP is writable in mip, and may be written by M-mode software to deliver timer interrupts to S-mode.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "line_range": [ + 1051, + 1058 + ] + }, + { + "text": "If the `stimecmp` (supervisor-mode timer compare) register is implemented, STIP is read-only in mip and reflects the supervisor-level timer interrupt signal resulting from stimecmp.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "line_range": [ + 1051, + 1058 + ] + }, + { + "text": "This timer interrupt signal is cleared by writing `stimecmp` with a value greater than the current time value.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "line_range": [ + 1051, + 1058 + ] + }, + { + "text": "If supervisor mode is implemented, bits `mip`.SSIP and `mie`.SSIE are the interrupt-pending and interrupt-enable bits for supervisor-level software interrupts. SSIP is writable in `mip` and may also be set to 1 by a platform-specific interrupt controller.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "line_range": [ + 1060, + 1063 + ] + }, + { + "text": "If the Sscofpmf extension is implemented, bits `mip`.LCOFIP and `mie`.LCOFIE are the interrupt-pending and interrupt-enable bits for local-counter-overflow interrupts. LCOFIP is read-write in `mip` and reflects the occurrence of a local counter-overflow overflow interrupt request resulting from any of the `mhpmeventn`.OF bits being set.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "line_range": [ + 1065, + 1070 + ] + }, + { + "text": "If the Sscofpmf extension is not implemented, `mip`.LCOFIP and `mie`.LCOFIE are read-only zeros.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "line_range": [ + 1065, + 1070 + ] + }, + { + "text": "Multiple simultaneous interrupts destined for M-mode are handled in the following decreasing priority order: MEI, MSI, MTI, SEI, SSI, STI, LCOFI.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "line_range": [ + 1072, + 1073 + ] + }, + { + "text": "Restricted views of the `mip` and `mie` registers appear as the `sip` and `sie` registers for supervisor level.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "line_range": [ + 1075, + 1079 + ] + }, + { + "text": "If an interrupt is delegated to S-mode by setting a bit in the `mideleg` register, it becomes visible in the `sip` register and is maskable using the `sie` register.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "line_range": [ + 1075, + 1079 + ] + }, + { + "text": "Otherwise, the corresponding bits in `sip` and `sie` are read-only zero.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Interrupt (`mip` and `mie`) Registers", + "line_range": [ + 1075, + 1079 + ] + }, + { + "text": "M-mode includes a basic hardware performance-monitoring facility.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Hardware Performance Monitor", + "line_range": [ + 1083, + 1087 + ] + }, + { + "text": "The `mcycle` CSR counts the number of clock cycles executed by the processor core on which the hart is running.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Hardware Performance Monitor", + "line_range": [ + 1083, + 1087 + ] + }, + { + "text": "The `minstret` CSR counts the number of instructions the hart has retired.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Hardware Performance Monitor", + "line_range": [ + 1083, + 1087 + ] + }, + { + "text": "The `mcycle` and `minstret` registers have 64-bit precision on all RV32 and RV64 harts.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Hardware Performance Monitor", + "line_range": [ + 1083, + 1087 + ] + }, + { + "text": "The counter registers have an arbitrary value after the hart is reset, and can be written with a given value.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Hardware Performance Monitor", + "line_range": [ + 1089, + 1095 + ] + }, + { + "text": "Any CSR write takes effect after the writing instruction has otherwise completed.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Hardware Performance Monitor", + "line_range": [ + 1089, + 1095 + ] + }, + { + "text": "The `mcycle` CSR may be shared between harts on the same core, in which case writes to `mcycle` will be visible to those harts.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Hardware Performance Monitor", + "line_range": [ + 1089, + 1095 + ] + }, + { + "text": "The platform should provide a mechanism to indicate which harts share an `mcycle` CSR.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Hardware Performance Monitor", + "line_range": [ + 1089, + 1095 + ] + }, + { + "text": "The hardware performance monitor includes 29 additional 64-bit event counters, `mhpmcounter3`-`mhpmcounter31`.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Hardware Performance Monitor", + "line_range": [ + 1097, + 1105 + ] + }, + { + "text": "The event selector CSRs, `mhpmevent3`-`mhpmevent31`, are 64-bit *WARL* registers that control which event causes the corresponding counter to increment.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Hardware Performance Monitor", + "line_range": [ + 1097, + 1105 + ] + }, + { + "text": "The meaning of these events is defined by the platform, but event 0 is defined to mean \"no event.\" All counters should be implemented, but a legal implementation is to make both the counter and its corresponding event selector be read-only 0.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Hardware Performance Monitor", + "line_range": [ + 1097, + 1105 + ] + }, + { + "text": ".Hardware performance monitor counters. include::images/bytefield/hpmevents.edn[]", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Hardware Performance Monitor", + "line_range": [ + 1107, + 1108 + ] + }, + { + "text": "The `mhpmcounters` are *WARL* registers that support up to 64 bits of precision on RV32 and RV64.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Hardware Performance Monitor", + "line_range": [ + 1110, + 1111 + ] + }, + { + "text": "When XLEN=32, reads of the `mcycle`, `minstret`, `mhpmcountern`, and `mhpmeventn` CSRs return bitj 31-0 of the corresponding register, and writes change only bits 31-0; reads of the `mcycleh`, `minstreth`, `mhpmcounternh`, and `mhpmeventnh` CSRs return bits 63-32 of the corresponding register, and writes change only bits 63-32.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Hardware Performance Monitor", + "line_range": [ + 1113, + 1117 + ] + }, + { + "text": "The `mhpmeventnh` CSRs are provided only if the Sscofpmf extension is implemented.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Hardware Performance Monitor", + "line_range": [ + 1113, + 1117 + ] + }, + { + "text": "The counter-enable `mcounteren` register is a 32-bit register that controls the availability of the hardware performance-monitoring counters to the next-lower privileged mode.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Counter-Enable (`mcounteren`) Register", + "line_range": [ + 1122, + 1124 + ] + }, + { + "text": ".Counter-enable (`mcounteren`) register. include::images/bytefield/counteren.edn[]", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Counter-Enable (`mcounteren`) Register", + "line_range": [ + 1126, + 1128 + ] + }, + { + "text": "The settings in this register only control accessibility.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Counter-Enable (`mcounteren`) Register", + "line_range": [ + 1130, + 1132 + ] + }, + { + "text": "The act of reading or writing this register does not affect the underlying counters, which continue to increment even when not accessible.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Counter-Enable (`mcounteren`) Register", + "line_range": [ + 1130, + 1132 + ] + }, + { + "text": "When the CY, TM, IR, or HPMn bit in the `mcounteren` register is clear, attempts to read the `cycle`, `time`, `instret`, or `hpmcountern` register while executing in S-mode or U-mode will cause an illegal-instruction exception.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Counter-Enable (`mcounteren`) Register", + "line_range": [ + 1134, + 1140 + ] + }, + { + "text": "When one of these bits is set, access to the corresponding register is permitted in the next implemented privilege mode (S-mode if implemented, otherwise U-mode).", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Counter-Enable (`mcounteren`) Register", + "line_range": [ + 1134, + 1140 + ] + }, + { + "text": "In addition, when the TM bit in the `mcounteren` register is clear, attempts to access the `stimecmp` or `vstimecmp` register while executing in a mode less privileged than M will cause an illegal-instruction exception.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Counter-Enable (`mcounteren`) Register", + "line_range": [ + 1142, + 1148 + ] + }, + { + "text": "When this bit is set, access to the `stimecmp` or `vstimecmp` register is permitted in S-mode if implemented, and access to the `vstimecmp` register (via `stimecmp`) is permitted in VS-mode if implemented and not otherwise prevented by the TM bit in `hcounteren`.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Counter-Enable (`mcounteren`) Register", + "line_range": [ + 1142, + 1148 + ] + }, + { + "text": "The `cycle`, `instret`, and `hpmcountern` CSRs are read-only shadows of `mcycle`, `minstret`, and `mhpmcounter n`, respectively.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Counter-Enable (`mcounteren`) Register", + "line_range": [ + 1150, + 1156 + ] + }, + { + "text": "The `time` CSR is a read-only shadow of the memory-mapped `mtime` register.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Counter-Enable (`mcounteren`) Register", + "line_range": [ + 1150, + 1156 + ] + }, + { + "text": "Analogously, when XLEN=32, the `cycleh`, `instreth` and `hpmcounternh` CSRs are read-only shadows of `mcycleh`, `minstreth` and `mhpmcounternh`, respectively.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Counter-Enable (`mcounteren`) Register", + "line_range": [ + 1150, + 1156 + ] + }, + { + "text": "When XLEN=32, the `timeh` CSR is a read-only shadow of the upper 32 bits of the memory-mapped `mtime` register, while `time` shadows only the lower 32 bits of `mtime`.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Counter-Enable (`mcounteren`) Register", + "line_range": [ + 1150, + 1156 + ] + }, + { + "text": "In harts with U-mode, the `mcounteren` must be implemented, but all fields are *WARL* and may be read-only zero, indicating reads to the corresponding counter will cause an illegal-instruction exception when executing in a less-privileged mode.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Counter-Enable (`mcounteren`) Register", + "line_range": [ + 1158, + 1163 + ] + }, + { + "text": "In harts without U-mode, the `mcounteren` register should not exist.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Counter-Enable (`mcounteren`) Register", + "line_range": [ + 1158, + 1163 + ] + }, + { + "text": ".Counter-inhibit `mcountinhibit` register include::images/bytefield/counterinh.edn[]", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Counter-Inhibit (`mcountinhibit`) Register", + "line_range": [ + 1167, + 1169 + ] + }, + { + "text": "The counter-inhibit register `mcountinhibit` is a 32-bit *WARL* register that controls which of the hardware performance-monitoring counters increment.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Counter-Inhibit (`mcountinhibit`) Register", + "line_range": [ + 1171, + 1175 + ] + }, + { + "text": "The settings in this register only control whether the counters increment; their accessibility is not affected by the setting of this register.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Counter-Inhibit (`mcountinhibit`) Register", + "line_range": [ + 1171, + 1175 + ] + }, + { + "text": "When the CY, IR, or HPMn bit in the `mcountinhibit` register is clear, the `mcycle`, `minstret`, or `mhpmcountern` register increments as usual.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Counter-Inhibit (`mcountinhibit`) Register", + "line_range": [ + 1177, + 1180 + ] + }, + { + "text": "When the CY, IR, or HPMn bit is set, the corresponding counter does not increment.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Counter-Inhibit (`mcountinhibit`) Register", + "line_range": [ + 1177, + 1180 + ] + }, + { + "text": "The `mcycle` CSR may be shared between harts on the same core, in which case the `mcountinhibit.CY` field is also shared between those harts, and so writes to `mcountinhibit.CY` will be visible to those harts.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Counter-Inhibit (`mcountinhibit`) Register", + "line_range": [ + 1182, + 1184 + ] + }, + { + "text": "If the `mcountinhibit` register is not implemented, the implementation behaves as though the register were set to zero.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Counter-Inhibit (`mcountinhibit`) Register", + "line_range": [ + 1186, + 1187 + ] + }, + { + "text": "The `mscratch` register is an MXLEN-bit read/write register dedicated for use by machine mode.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Scratch (`mscratch`) Register", + "line_range": [ + 1191, + 1194 + ] + }, + { + "text": "Typically, it is used to hold a pointer to a machine-mode hart-local context space and swapped with a user register upon entry to an M-mode trap handler.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Scratch (`mscratch`) Register", + "line_range": [ + 1191, + 1194 + ] + }, + { + "text": ".Machine-mode scratch register. include::images/bytefield/mscratch.edn[]", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Scratch (`mscratch`) Register", + "line_range": [ + 1196, + 1198 + ] + }, + { + "text": "`mepc` is an MXLEN-bit read/write register formatted as shown in .", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Exception Program Counter (`mepc`) Register", + "line_range": [ + 1202, + 1203 + ] + }, + { + "text": "The low bit of `mepc` (`mepc[0]`) is always zero.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Exception Program Counter (`mepc`) Register", + "line_range": [ + 1202, + 1203 + ] + }, + { + "text": "On implementations that support only IALIGN=32, the two low bits (`mepc[1:0]`) are always zero.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Exception Program Counter (`mepc`) Register", + "line_range": [ + 1202, + 1203 + ] + }, + { + "text": "If an implementation allows IALIGN to be either 16 or 32 (by changing CSR `misa`, for example), then, whenever IALIGN=32, bit `mepc[1]` is masked on reads so that it appears to be 0.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Exception Program Counter (`mepc`) Register", + "line_range": [ + 1205, + 1209 + ] + }, + { + "text": "This masking occurs also for the implicit read by the MRET instruction.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Exception Program Counter (`mepc`) Register", + "line_range": [ + 1205, + 1209 + ] + }, + { + "text": "Though masked, `mepc[1]` remains writable when IALIGN=32.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Exception Program Counter (`mepc`) Register", + "line_range": [ + 1205, + 1209 + ] + }, + { + "text": "`mepc` is a *WARL* register that must be able to hold all valid virtual addresses.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Exception Program Counter (`mepc`) Register", + "line_range": [ + 1211, + 1214 + ] + }, + { + "text": "It need not be capable of holding all possible invalid addresses.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Exception Program Counter (`mepc`) Register", + "line_range": [ + 1211, + 1214 + ] + }, + { + "text": "Prior to writing `mepc`, implementations may convert an invalid address into some other invalid address that `mepc` is capable of holding.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Exception Program Counter (`mepc`) Register", + "line_range": [ + 1211, + 1214 + ] + }, + { + "text": "When a trap is taken into M-mode, `mepc` is written with the virtual address of the instruction that was interrupted or that encountered the exception.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Exception Program Counter (`mepc`) Register", + "line_range": [ + 1216, + 1219 + ] + }, + { + "text": "Otherwise, `mepc` is never written by the implementation, though it may be explicitly written by software.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Exception Program Counter (`mepc`) Register", + "line_range": [ + 1216, + 1219 + ] + }, + { + "text": ".Machine exception program counter register. include::images/bytefield/mepcreg.edn[]", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Exception Program Counter (`mepc`) Register", + "line_range": [ + 1221, + 1223 + ] + }, + { + "text": "The `mcause` register is an MXLEN-bit read-write register formatted as shown in .", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Cause (`mcause`) Register", + "line_range": [ + 1228, + 1233 + ] + }, + { + "text": "When a trap is taken into M-mode, `mcause` is written with a code indicating the event that caused the trap.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Cause (`mcause`) Register", + "line_range": [ + 1228, + 1233 + ] + }, + { + "text": "Otherwise, `mcause` is never written by the implementation, though it may be explicitly written by software.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Cause (`mcause`) Register", + "line_range": [ + 1228, + 1233 + ] + }, + { + "text": "The Interrupt bit in the `mcause` register is set if the trap was caused by an interrupt.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Cause (`mcause`) Register", + "line_range": [ + 1235, + 1240 + ] + }, + { + "text": "The Exception Code field contains a code identifying the last exception or interrupt. lists the possible machine-level exception codes.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Cause (`mcause`) Register", + "line_range": [ + 1235, + 1240 + ] + }, + { + "text": "The Exception Code is a *WLRL* field, so is only guaranteed to hold supported exception codes.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Cause (`mcause`) Register", + "line_range": [ + 1235, + 1240 + ] + }, + { + "text": ".Machine Cause (`mcause`) register. include::images/bytefield/mcausereg.edn[]", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Cause (`mcause`) Register", + "line_range": [ + 1242, + 1244 + ] + }, + { + "text": "Note that load and load-reserved instructions generate load exceptions, whereas store, store-conditional, and AMO instructions generate store/AMO exceptions.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Cause (`mcause`) Register", + "line_range": [ + 1246, + 1248 + ] + }, + { + "text": "If an instruction may raise multiple synchronous exceptions, the decreasing priority order of indicates which exception is taken and reported in `mcause`.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Cause (`mcause`) Register", + "line_range": [ + 1250, + 1253 + ] + }, + { + "text": "The priority of any custom synchronous exceptions is implementation-defined.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Cause (`mcause`) Register", + "line_range": [ + 1250, + 1253 + ] + }, + { + "text": ".Machine cause (`mcause`) register values after trap. | |Interrupt |Exception Code |Description |1 + 1 + 1 + 1 |0 + 1 + 2 + 3 |Reserved + Supervisor software interrupt + Reserved + Machine software interrupt", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Cause (`mcause`) Register", + "line_range": [ + 1257, + 1273 + ] + }, + { + "text": "|1 + 1 + 1 + 1 |4 + 5 + 6 + 7 |Reserved + Supervisor timer interrupt + Reserved + Machine timer interrupt |1 + 1 + 1 + 1 |8 + 9 + 10 + 11 |Reserved + Supervisor external interrupt + Reserved + Machine external interrupt |1 + 1 + 1 + 1 |12 + 13 + 14-15 + {ge}16 |Reserved + Counter-overflow interrupt + Reserved + Designated for platform use |0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 |0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 11 + 12 + 13 + 14 + 15 + 16 + 17 + 18 + 19 + 20-23 + 24-31 + 32-47 + 48-63 + {ge}64 |Instruction address misaligned + Instruction access fault + Illegal instruction + Breakpoint + Load address misaligned + Load access fault + Store/AMO address misaligned + Store/AMO access fault + Environment call from U-mode + Environment call from S-mode + Reserved + Environment call from M-mode + Instruction page fault + Load page fault + Reserved + Store/AMO page fault + Double trap + Reserved + Software check + Hardware error + Reserved + Designated for custom use + Reserved + Designated for custom use + Reserved |", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Cause (`mcause`) Register", + "line_range": [ + 1275, + 1386 + ] + }, + { + "text": ".Synchronous exception priority in decreasing priority order. | |Priority |Exc.Code |Description |Highest |3 |Instruction address breakpoint | .>|12, 1 .<|During instruction address translation: + First encountered page fault or access fault | .>|1 .<|With physical address for instruction: + Instruction access fault", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Cause (`mcause`) Register", + "line_range": [ + 1390, + 1399 + ] + }, + { + "text": "| .>|2 + 0 + 8,9,11 + 3 + 3 .<|Illegal instruction + Instruction address misaligned + Environment call + Environment break + Load/store/AMO address breakpoint", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Cause (`mcause`) Register", + "line_range": [ + 1401, + 1409 + ] + }, + { + "text": "| .>|4,6 .<|Optionally: + Load/store/AMO address misaligned | .>|13, 15, 5, 7 .<|During address translation for an explicit memory access: + First encountered page fault or access fault | .>|5,7 .<|With physical address for an explicit memory access: + Load/store/AMO access fault .>|Lowest .>|4,6 .<|", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Cause (`mcause`) Register", + "line_range": [ + 1411, + 1419 + ] + }, + { + "text": "If not higher priority: + Load/store/AMO address misaligned |", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Cause (`mcause`) Register", + "line_range": [ + 1411, + 1419 + ] + }, + { + "text": "When a virtual address is translated into a physical address, the address translation algorithm determines what specific exception may be raised.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Cause (`mcause`) Register", + "line_range": [ + 1421, + 1423 + ] + }, + { + "text": "Load/store/AMO address-misaligned exceptions may have either higher or lower priority than load/store/AMO page-fault and access-fault exceptions.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Cause (`mcause`) Register", + "line_range": [ + 1425, + 1426 + ] + }, + { + "text": "The `mtval` register is an MXLEN-bit read-write register formatted as shown in .", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register", + "line_range": [ + 1430, + 1442 + ] + }, + { + "text": "When a trap is taken into M-mode, `mtval` is either set to zero or written with exception-specific information to assist software in handling the trap.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register", + "line_range": [ + 1430, + 1442 + ] + }, + { + "text": "Otherwise, `mtval` is never written by the implementation, though it may be explicitly written by software.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register", + "line_range": [ + 1430, + 1442 + ] + }, + { + "text": "The hardware platform will specify which exceptions must set `mtval` informatively, which may unconditionally set it to zero, and which may exhibit either behavior, depending on the underlying event that caused the exception.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register", + "line_range": [ + 1430, + 1442 + ] + }, + { + "text": "If the hardware platform specifies that no exceptions set `mtval` to a nonzero value, then `mtval` is read-only zero.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register", + "line_range": [ + 1430, + 1442 + ] + }, + { + "text": "If `mtval` is written with a nonzero value when a breakpoint, address-misaligned, access-fault, page-fault, or hardware-error exception occurs on an instruction fetch, load, or store, then `mtval` will contain the faulting virtual address.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register", + "line_range": [ + 1444, + 1447 + ] + }, + { + "text": "On a breakpoint exception raised by an EBREAK or C.EBREAK instruction, `mtval` is written with either zero or the virtual address of the instruction.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register", + "line_range": [ + 1449, + 1450 + ] + }, + { + "text": "NOTE: For breakpoint exceptions raised by [C.]EBREAK, the virtual address of the instruction is already recorded in `mepc`.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register", + "line_range": [ + 1452, + 1455 + ] + }, + { + "text": "Recording the same address in `mtval` is redundant; the option is provided for backwards compatibility.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register", + "line_range": [ + 1452, + 1455 + ] + }, + { + "text": "When page-based virtual memory is enabled, `mtval` is written with the faulting virtual address, even for physical-memory access-fault exceptions.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register", + "line_range": [ + 1457, + 1460 + ] + }, + { + "text": "This design reduces datapath cost for most implementations, particularly those with hardware page-table walkers.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register", + "line_range": [ + 1457, + 1460 + ] + }, + { + "text": ".Machine Trap Value (`mtval`) register. include::images/bytefield/mtvalreg.edn[]", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register", + "line_range": [ + 1462, + 1464 + ] + }, + { + "text": "If `mtval` is written with a nonzero value when a misaligned load or store causes an access-fault, page-fault, or hardware-error exception, then `mtval` will contain the virtual address of the portion of the access that caused the fault.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register", + "line_range": [ + 1466, + 1468 + ] + }, + { + "text": "If `mtval` is written with a nonzero value when an instruction access-fault, page-fault, or hardware-error exception occurs on a hart with variable-length instructions, then `mtval` will contain the virtual address of the portion of the instruction that caused the fault, while `mepc` will point to the beginning of the instruction.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register", + "line_range": [ + 1470, + 1474 + ] + }, + { + "text": "The `mtval` register can optionally also be used to return the faulting instruction bits on an illegal-instruction exception (`mepc` points to the faulting instruction in memory).", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register", + "line_range": [ + 1476, + 1480 + ] + }, + { + "text": "If `mtval` is written with a nonzero value when an illegal-instruction exception occurs, then `mtval` will contain the shortest of:", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register", + "line_range": [ + 1476, + 1480 + ] + }, + { + "text": "* the actual faulting instruction", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register", + "line_range": [ + 1482, + 1483 + ] + }, + { + "text": "the first ILEN bits of the faulting instruction", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register", + "line_range": [ + 1485, + 1485 + ] + }, + { + "text": "the first MXLEN bits of the faulting instruction", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register", + "line_range": [ + 1487, + 1487 + ] + }, + { + "text": "The value loaded into `mtval` on an illegal-instruction exception is right-justified and all unused upper bits are cleared to zero.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register", + "line_range": [ + 1489, + 1490 + ] + }, + { + "text": "On a trap caused by a software-check exception, the `mtval` register holds the cause for the exception.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register", + "line_range": [ + 1492, + 1493 + ] + }, + { + "text": "The following encodings are defined:", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register", + "line_range": [ + 1492, + 1493 + ] + }, + { + "text": "* 0 - No information provided. * 2 - Landing Pad Fault.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register", + "line_range": [ + 1495, + 1498 + ] + }, + { + "text": "Defined by the Zicfilp extension (). * 3 - Shadow Stack Fault.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register", + "line_range": [ + 1495, + 1498 + ] + }, + { + "text": "Defined by the Zicfiss extension ().", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register", + "line_range": [ + 1495, + 1498 + ] + }, + { + "text": "For other traps, `mtval` is set to zero, but a future standard may redefine `mtval`’s setting for other traps.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register", + "line_range": [ + 1500, + 1501 + ] + }, + { + "text": "If `mtval` is not read-only zero, it is a *WARL* register that must be able to hold all valid virtual addresses and the value zero.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register", + "line_range": [ + 1503, + 1510 + ] + }, + { + "text": "It need not be capable of holding all possible invalid addresses.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register", + "line_range": [ + 1503, + 1510 + ] + }, + { + "text": "Prior to writing `mtval`, implementations may convert an invalid address into some other invalid address that `mtval` is capable of holding.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register", + "line_range": [ + 1503, + 1510 + ] + }, + { + "text": "If the feature to return the faulting instruction bits is implemented, `mtval` must also be able to hold all values less than 2^N^, where N is the smaller of MXLEN and ILEN.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Trap Value (`mtval`) Register", + "line_range": [ + 1503, + 1510 + ] + }, + { + "text": "The `mconfigptr` register is an MXLEN-bit read-only CSR formatted as shown in , that holds the physical address of a configuration data structure.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Configuration Pointer (`mconfigptr`) Register", + "line_range": [ + 1514, + 1517 + ] + }, + { + "text": "Software can traverse this data structure to discover information about the harts, the platform, and their configuration.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Configuration Pointer (`mconfigptr`) Register", + "line_range": [ + 1514, + 1517 + ] + }, + { + "text": ".Machine Configuration Pointer (`mconfigptr`) register. include::images/bytefield/mconfigptrreg.edn[]", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Configuration Pointer (`mconfigptr`) Register", + "line_range": [ + 1519, + 1521 + ] + }, + { + "text": "The pointer alignment in bits must be no smaller than MXLEN: i.e., if MXLEN is 8{times}n, then `mconfigptr`[log~2n~-1:0] must be zero.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Configuration Pointer (`mconfigptr`) Register", + "line_range": [ + 1523, + 1524 + ] + }, + { + "text": "The `mconfigptr` register must be implemented, but it may be zero to indicate the configuration data structure does not exist or that an alternative mechanism must be used to locate it.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Configuration Pointer (`mconfigptr`) Register", + "line_range": [ + 1526, + 1529 + ] + }, + { + "text": "The `menvcfg` CSR is a 64-bit read/write register, formatted as shown in , that controls certain characteristics of the execution environment for modes less privileged than M.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "line_range": [ + 1534, + 1537 + ] + }, + { + "text": ".Machine environment configuration (`menvcfg`) register. include::images/wavedrom/menvcfgreg.edn[]", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "line_range": [ + 1539, + 1541 + ] + }, + { + "text": "If bit FIOM (Fence of I/O implies Memory) is set to one in `menvcfg`, FENCE instructions executed in modes less privileged than M are modified so the requirement to order accesses to device I/O implies also the requirement to order main memory accesses. details the modified interpretation of FENCE instruction bits PI, PO, SI, and SO for modes less privileged than M when FIOM=1.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "line_range": [ + 1543, + 1548 + ] + }, + { + "text": "Similarly, for modes less privileged than M when FIOM=1, if an atomic instruction that accesses a region ordered as device I/O has its aq and/or rl bit set, then that instruction is ordered as though it accesses both device I/O and memory.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "line_range": [ + 1550, + 1553 + ] + }, + { + "text": "If S-mode is not supported, or if `satp`.MODE is read-only zero (always Bare), the implementation may make FIOM read-only zero.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "line_range": [ + 1555, + 1556 + ] + }, + { + "text": ".Modified interpretation of FENCE predecessor and successor sets for modes less privileged than M when FIOM=1. | |Instruction bit |Meaning when set |PI + PO |Predecessor device input and memory reads (PR implied) + Predecessor device output and memory writes (PW implied) |SI + SO |Successor device input and memory reads (SR implied) + Successor device output and memory writes (SW implied) |", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "line_range": [ + 1558, + 1571 + ] + }, + { + "text": "The PBMTE bit controls whether the Svpbmt extension is available for use in S-mode and G-stage address translation (i.e., for page tables pointed to by `satp` or `hgatp`).", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "line_range": [ + 1573, + 1581 + ] + }, + { + "text": "When PBMTE=1, Svpbmt is available for S-mode and G-stage address translation.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "line_range": [ + 1573, + 1581 + ] + }, + { + "text": "When PBMTE=0, the implementation behaves as though Svpbmt were not implemented.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "line_range": [ + 1573, + 1581 + ] + }, + { + "text": "If Svpbmt is not implemented, PBMTE is read-only zero.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "line_range": [ + 1573, + 1581 + ] + }, + { + "text": "Furthermore, for implementations with the hypervisor extension, `henvcfg`.PBMTE is read-only zero if `menvcfg`.PBMTE is zero.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "line_range": [ + 1573, + 1581 + ] + }, + { + "text": "After changing `menvcfg`.PBMTE, executing an SFENCE.VMA instruction with rs1=`x0` and rs2=`x0` suffices to synchronize address-translation caches with respect to the altered interpretation of page-table entries' PBMT fields.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "line_range": [ + 1583, + 1587 + ] + }, + { + "text": "See for additional synchronization requirements when the hypervisor extension is implemented.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "line_range": [ + 1583, + 1587 + ] + }, + { + "text": "If the Svadu extension is implemented, the ADUE bit controls whether hardware updating of PTE A/D bits is enabled for S-mode and G-stage address translations.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "line_range": [ + 1589, + 1602 + ] + }, + { + "text": "When ADUE=1, hardware updating of PTE A/D bits is enabled during S-mode address translation, and the implementation behaves as though the Svade extension were not implemented for S-mode address translation.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "line_range": [ + 1589, + 1602 + ] + }, + { + "text": "When the hypervisor extension is implemented, if ADUE=1, hardware updating of PTE A/D bits is enabled during G-stage address translation, and the implementation behaves as though the Svade extension were not implemented for G-stage address translation.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "line_range": [ + 1589, + 1602 + ] + }, + { + "text": "When ADUE=0, the implementation behaves as though Svade were implemented for S-mode and G-stage address translation.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "line_range": [ + 1589, + 1602 + ] + }, + { + "text": "If Svadu is not implemented, ADUE is read-only zero.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "line_range": [ + 1589, + 1602 + ] + }, + { + "text": "Furthermore, for implementations with the hypervisor extension, `henvcfg`.ADUE is read-only zero if `menvcfg`.ADUE is zero.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "line_range": [ + 1589, + 1602 + ] + }, + { + "text": "After changing `menvcfg`.ADUE, executing an SFENCE.VMA instruction with rs1=`x0` and rs2=`x0` suffices to synchronize address-translation caches with respect to the altered interpretation of page-table entries' A/D bits.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "line_range": [ + 1604, + 1608 + ] + }, + { + "text": "See for additional synchronization requirements when the hypervisor extension is implemented.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "line_range": [ + 1604, + 1608 + ] + }, + { + "text": "NOTE: The Svade extension requires page-fault exceptions be raised when PTE A/D bits need be set, hence Svade is implemented when ADUE=0.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "line_range": [ + 1610, + 1611 + ] + }, + { + "text": "If the Smcdeleg extension is implemented, the CDE (Counter Delegation Enable) bit controls whether Zicntr and Zihpm counters can be delegated to S-mode.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "line_range": [ + 1613, + 1616 + ] + }, + { + "text": "When CDE=1, the Smcdeleg extension is enabled, see .", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "line_range": [ + 1613, + 1616 + ] + }, + { + "text": "When CDE=0, the Smcdeleg and Ssccfg extensions appear to be not implemented.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "line_range": [ + 1613, + 1616 + ] + }, + { + "text": "If Smcdeleg is not implemented, CDE is read-only zero.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "line_range": [ + 1613, + 1616 + ] + }, + { + "text": "The Sstc extension adds the `STCE` (STimecmp Enable) bit to `menvcfg` CSR.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "line_range": [ + 1618, + 1626 + ] + }, + { + "text": "When the Sstc extension is not implemented, `STCE` is read-only zero.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "line_range": [ + 1618, + 1626 + ] + }, + { + "text": "The `STCE` bit enables `stimecmp` for S-mode when set to one.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "line_range": [ + 1618, + 1626 + ] + }, + { + "text": "When this extension is implemented and `STCE` in `menvcfg` is zero, an attempt to access `stimecmp` in a mode other than M-mode raises an illegal-instruction exception, `STCE` in `henvcfg` is read-only zero, and `STIP` in `mip` and `sip` reverts to its defined behavior as if this extension is not implemented.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "line_range": [ + 1618, + 1626 + ] + }, + { + "text": "Further, if the H extension is implemented, then `hip`.VSTIP also reverts its defined behavior as if this extension is not implemented.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "line_range": [ + 1618, + 1626 + ] + }, + { + "text": "The Zicboz extension adds the `CBZE` (Cache Block Zero instruction enable) field to `menvcfg`.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "line_range": [ + 1628, + 1633 + ] + }, + { + "text": "When the `CBZE` field is set to 1, it enables execution of the cache block zero instruction, `CBO.ZERO`, in modes less privileged than M.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "line_range": [ + 1628, + 1633 + ] + }, + { + "text": "Otherwise, the instruction raises an illegal-instruction exception in modes less privileged than M.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "line_range": [ + 1628, + 1633 + ] + }, + { + "text": "When the Zicboz extension is not implemented, `CBZE` is read-only zero.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "line_range": [ + 1628, + 1633 + ] + }, + { + "text": "The Zicbom extension adds the `CBCFE` (Cache Block Clean and Flush instruction Enable) field to `menvcfg`.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "line_range": [ + 1635, + 1640 + ] + }, + { + "text": "When the `CBCFE` field is set to 1, it enables execution of the cache block clean instruction (`CBO.CLEAN`) and the cache block flush instruction (`CBO.FLUSH`) in modes less privileged than M.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "line_range": [ + 1635, + 1640 + ] + }, + { + "text": "Otherwise, these instructions raise an illegal-instruction exception in modes less privileged than M.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "line_range": [ + 1635, + 1640 + ] + }, + { + "text": "When the Zicbom extension is not implemented, `CBCFE` is read-only zero.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "line_range": [ + 1635, + 1640 + ] + }, + { + "text": "The Zicbom extension adds the `CBIE` (Cache Block Invalidate instruction Enable) WARL field to `menvcfg` to control execution of the cache block invalidate instruction (`CBO.INVAL`) in modes less privileged than M.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "line_range": [ + 1642, + 1651 + ] + }, + { + "text": "When `CBIE` is set to `00b`, the instruction raises an illegal-instruction exception in modes less privileged than M.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "line_range": [ + 1642, + 1651 + ] + }, + { + "text": "When the Zicbom extension is not implemented, `CBIE` is read-only zero.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "line_range": [ + 1642, + 1651 + ] + }, + { + "text": "The encoding `10b` is reserved.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "line_range": [ + 1642, + 1651 + ] + }, + { + "text": "When `CBIE` is set to `01b` or `11b`, and when enabled for execution in modes less privileged than M, it behaves as follows:", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "line_range": [ + 1642, + 1651 + ] + }, + { + "text": "* `01b` -- The instruction is executed and performs a flush operation, even if configured by a mode less privileged than M to perform an invalidate operation. * `11b` -- The instruction is executed and performs an invalidate operation, unless configured by a mode less privileged than M to perform a flush operation.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "line_range": [ + 1653, + 1658 + ] + }, + { + "text": "If the Smnpm extension is implemented, the `PMM` field enables or disables pointer masking (see ) for the next-lower privilege mode (S-/HS-mode if S-mode is implemented, or U-mode otherwise), according to the values in .", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "line_range": [ + 1660, + 1665 + ] + }, + { + "text": "If Smnpm is not implemented, `PMM` is read-only zero.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "line_range": [ + 1660, + 1665 + ] + }, + { + "text": "The `PMM` field is read-only zero for RV32.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "line_range": [ + 1660, + 1665 + ] + }, + { + "text": ".Legal values of `PMM` WARL field | |Value|Description |00|Pointer masking is disabled (PMLEN = 0) |01|Reserved |10|Pointer masking is enabled with PMLEN = XLEN - 57 (PMLEN = 7 on RV64) |11|Pointer masking is enabled with PMLEN = XLEN - 48 (PMLEN = 16 on RV64) |", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "line_range": [ + 1667, + 1676 + ] + }, + { + "text": "The Zicfilp extension adds the `LPE` field in `menvcfg`.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "line_range": [ + 1678, + 1683 + ] + }, + { + "text": "When the `LPE` field is set to 1 and S-mode is implemented, the Zicfilp extension is enabled in S-mode.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "line_range": [ + 1678, + 1683 + ] + }, + { + "text": "If `LPE` field is set to 1 and S-mode is not implemented, the Zicfilp extension is enabled in U-mode.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "line_range": [ + 1678, + 1683 + ] + }, + { + "text": "When the `LPE` field is 0, the Zicfilp extension is not enabled in S-mode, and the following rules apply to S-mode.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "line_range": [ + 1678, + 1683 + ] + }, + { + "text": "If the `LPE` field is 0 and S-mode is not implemented, then the same rules apply to U-mode.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "line_range": [ + 1678, + 1683 + ] + }, + { + "text": "* The hart does not update the `ELP` state; it remains as `NOLPEXPECTED`. * The `LPAD` instruction operates as a no-op.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "line_range": [ + 1685, + 1687 + ] + }, + { + "text": "The Zicfiss extension adds the `SSE` field to `menvcfg`.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "line_range": [ + 1689, + 1691 + ] + }, + { + "text": "When the `SSE` field is set to 1 the Zicfiss extension is activated in S-mode.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "line_range": [ + 1689, + 1691 + ] + }, + { + "text": "When `SSE` field is 0, the following rules apply to privilege modes that are less than M:", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "line_range": [ + 1689, + 1691 + ] + }, + { + "text": "* 32-bit Zicfiss instructions will revert to their behavior as defined by Zimop. * 16-bit Zicfiss instructions will revert to their behavior as defined by Zcmop. * The `pte.xwr=010b` encoding in VS/S-stage page tables becomes reserved. * `SSAMOSWAP.W/D` raises an illegal-instruction exception.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "line_range": [ + 1693, + 1697 + ] + }, + { + "text": "When `menvcfg.SSE` is 0, the `henvcfg.SSE` and `senvcfg.SSE` fields are read-only zero.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "line_range": [ + 1699, + 1700 + ] + }, + { + "text": "The Ssdbltrp extension adds the double-trap-enable (`DTE`) field in `menvcfg`.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "line_range": [ + 1702, + 1705 + ] + }, + { + "text": "When `menvcfg.DTE` is zero, the implementation behaves as though Ssdbltrp is not implemented.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "line_range": [ + 1702, + 1705 + ] + }, + { + "text": "When Ssdbltrp is not implemented `sstatus.SDT`, `vsstatus.SDT`, and `henvcfg.DTE` bits are read-only zero.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "line_range": [ + 1702, + 1705 + ] + }, + { + "text": "When XLEN=32, `menvcfgh` is a 32-bit read/write register that aliases bits 63:32 of `menvcfg`.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "line_range": [ + 1707, + 1709 + ] + }, + { + "text": "The `menvcfgh` register does not exist when XLEN=64.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "line_range": [ + 1707, + 1709 + ] + }, + { + "text": "If U-mode is not supported, then registers `menvcfg` and `menvcfgh` do not exist.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Environment Configuration (`menvcfg`) Register", + "line_range": [ + 1711, + 1712 + ] + }, + { + "text": "`mseccfg` is a 64-bit read/write register, formatted as shown in , that controls security features.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "line_range": [ + 1718, + 1720 + ] + }, + { + "text": "It exists if any extension that adds a field to `mseccfg` is implemented.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "line_range": [ + 1718, + 1720 + ] + }, + { + "text": "Otherwise, it is reserved.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "line_range": [ + 1718, + 1720 + ] + }, + { + "text": ".Machine security configuration (`mseccfg`) register. include::images/wavedrom/mseccfg.edn[]", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "line_range": [ + 1722, + 1724 + ] + }, + { + "text": "The Zkr extension adds the `SSEED` and `USEED` fields to the `mseccfg` CSR to control access to the `seed` CSR from modes less privileged than M.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "line_range": [ + 1726, + 1728 + ] + }, + { + "text": "When `USEED` is 0, access to the `seed` CSR in U-mode raises an illegal-instruction exception.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "line_range": [ + 1730, + 1734 + ] + }, + { + "text": "When `USEED` is 1, read-write access to the `seed` CSR from U-mode is allowed; all other types of accesses raise an illegal-instruction exception.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "line_range": [ + 1730, + 1734 + ] + }, + { + "text": "If Zkr or U-mode is not implemented, `USEED` is read-only zero.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "line_range": [ + 1730, + 1734 + ] + }, + { + "text": "When `SSEED` is 0, access to the `seed` CSR from S-/HS-mode raises an illegal-instruction exception.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "line_range": [ + 1736, + 1740 + ] + }, + { + "text": "When `SSEED` is 1, read-write access to the `seed` CSR from S-/HS-mode is allowed; all other types of accesses raise an illegal-instruction exception.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "line_range": [ + 1736, + 1740 + ] + }, + { + "text": "If Zkr or S-mode is not implemented, `SSEED` is read-only zero.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "line_range": [ + 1736, + 1740 + ] + }, + { + "text": "When the H extension is also implemented, access to the `seed` CSR from an HS-qualified instruction leads to a virtual-instruction exception in VS and VU modes; all other types of accesses raise an illegal-instruction exception.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "line_range": [ + 1742, + 1745 + ] + }, + { + "text": ".Entropy Source Access Control. [cols=\"1,1,1,7\",options=\"header\",] | |Mode | `SSEED` | `USEED` | Description | M | - | - | The `seed` CSR is always available in machine mode as normal (with a CSR read-write instruction.) Attempted read without a write raises an illegal-instruction exception regardless of mode and access control bits. | U | - | `0` | Any `seed` CSR access raises an illegal-instruction exception. | U | - | `1` | The `seed` CSR is accessible as normal.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "line_range": [ + 1747, + 1770 + ] + }, + { + "text": "No exception is raised for read-write. | S/HS | `0` | - | Any `seed` CSR access raises an illegal-instruction exception. | S/HS | `1` | - | The `seed` CSR is accessible as normal.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "line_range": [ + 1747, + 1770 + ] + }, + { + "text": "No exception is raised for read-write. | VS/VU | `0` | - | Any `seed` CSR access raises an illegal-instruction exception. | VS/VU | `1` | - | A read-write `seed` access raises a virtual-instruction exception, while other access conditions raise an illegal-instruction exception. |", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "line_range": [ + 1747, + 1770 + ] + }, + { + "text": "The Smepmp extension adds the `RLB`, `MMWP`, and the `MML` fields in `mseccfg`.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "line_range": [ + 1772, + 1774 + ] + }, + { + "text": "When `mseccfg.RLB` (Rule Locking Bypass) a WARL field that provides a mechanism to temporarily modify *Locked* PMP rules.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "line_range": [ + 1776, + 1782 + ] + }, + { + "text": "When `mseccfg.RLB` is 1, locked PMP rules may be removed or modified and locked PMP rules may be edited.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "line_range": [ + 1776, + 1782 + ] + }, + { + "text": "When `mseccfg.RLB` is 0 and `pmpcfg.L` is 1 in any rule or entry (including disabled entries), then `mseccfg.RLB` remains 0 and any further modifications to `mseccfg.RLB` are ignored until a *PMP reset*.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "line_range": [ + 1776, + 1782 + ] + }, + { + "text": "The `mseccfg.MMWP` (Machine-Mode Allowlist Policy) is a WARL field.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "line_range": [ + 1784, + 1790 + ] + }, + { + "text": "This field changes the default PMP policy for Machine mode when accessing memory regions that don't have a matching PMP rule.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "line_range": [ + 1784, + 1790 + ] + }, + { + "text": "This is a sticky bit, meaning that once set it cannot be unset until a *PMP reset*.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "line_range": [ + 1784, + 1790 + ] + }, + { + "text": "When set it changes the default PMP policy for M-mode when accessing memory regions that don’t have a matching *PMP rule*, to *denied* instead of *ignored*.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "line_range": [ + 1784, + 1790 + ] + }, + { + "text": "The `mseccfg.MML` (Machine Mode Lockdown) is a WARL field.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "line_range": [ + 1792, + 1796 + ] + }, + { + "text": "The `MML` bit changes the interpretation of the `pmpcfg.L` bit defined in .", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "line_range": [ + 1792, + 1796 + ] + }, + { + "text": "This is a sticky bit, meaning that once set it cannot be unset until a *PMP reset*.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "line_range": [ + 1792, + 1796 + ] + }, + { + "text": "When `mseccfg.MML` is set the system's behavior changes in the following way:", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "line_range": [ + 1792, + 1796 + ] + }, + { + "text": "The meaning of `pmpcfg.L` changes: Instead of marking a rule as *locked* and *enforced* in all modes, it now marks a rule as *M-mode-only* when set and *S/U-mode-only* when unset.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "line_range": [ + 1798, + 1814 + ] + }, + { + "text": "The formerly reserved encoding of `pmpcfg.RW=01`, and the encoding `pmpcfg.LRWX=1111`, now encode a *Shared-Region*. + + An M-mode-only rule is *enforced* on Machine mode and *denied* in Supervisor or User mode.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "line_range": [ + 1798, + 1814 + ] + }, + { + "text": "It also remains *locked* so that any further modifications to its associated configuration or address registers are ignored until a *PMP reset*, unless `mseccfg.RLB` is set. + + An S/U-mode-only rule is *enforced* on Supervisor and User modes and *denied* on Machine mode. + + A Shared-Region rule is *enforced* on all modes, with restrictions depending on the `pmpcfg.L` and `pmpcfg.X` bits: + +", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "line_range": [ + 1798, + 1814 + ] + }, + { + "text": "A Shared-Region rule where `pmpcfg.L` is not set can be used for sharing data between M-mode and S/U-mode, so is not executable. M-mode has read/write access to that region, and S/U-mode has read access if `pmpcfg.X` is not set, or read/write access if `pmpcfg.X` is set. + * A Shared-Region rule where `pmpcfg.L` is set can be used for sharing code between M-mode and S/U-mode, so is not writable.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "line_range": [ + 1816, + 1832 + ] + }, + { + "text": "Both M-mode and S/U-mode have execute access on the region, and M-mode also has read access if `pmpcfg.X` is set.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "line_range": [ + 1816, + 1832 + ] + }, + { + "text": "The rule remains *locked* so that any further modifications to its associated configuration or address registers are ignored until a *PMP reset*, unless `mseccfg.RLB` is set. + * The encoding `pmpcfg.LRWX=1111` can be used for sharing data between M-mode and S/U mode, where both modes only have read-only access to the region.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "line_range": [ + 1816, + 1832 + ] + }, + { + "text": "The rule remains *locked* so that any further modifications to its associated configuration or address registers are ignored until a *PMP reset*, unless `mseccfg.RLB` is set.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "line_range": [ + 1816, + 1832 + ] + }, + { + "text": "Adding a rule with executable privileges that either is *M-mode-only* or a *locked* *Shared-Region* is not possible and such `pmpcfg` writes are ignored, leaving `pmpcfg` unchanged.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "line_range": [ + 1834, + 1837 + ] + }, + { + "text": "This restriction can be temporarily lifted by setting `mseccfg.RLB` e.g. during the boot process.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "line_range": [ + 1834, + 1837 + ] + }, + { + "text": "Executing code with Machine mode privileges is only possible from memory regions with a matching *M-mode-only* rule or a *locked* *Shared-Region* rule with executable privileges.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "line_range": [ + 1839, + 1842 + ] + }, + { + "text": "Executing code from a region without a matching rule or with a matching S/U-mode-only rule is *denied*.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "line_range": [ + 1839, + 1842 + ] + }, + { + "text": "If `mseccfg.MML` is not set, the combination of `pmpcfg.RW=01` remains reserved for future standard use.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "line_range": [ + 1844, + 1845 + ] + }, + { + "text": "If the Smmpm extension is implemented, the `PMM` field enables or disables pointer masking (see ) for M-mode according to the values in .", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "line_range": [ + 1847, + 1851 + ] + }, + { + "text": "If Smmpm is not implemented, `PMM` is read-only zero.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "line_range": [ + 1847, + 1851 + ] + }, + { + "text": "The `PMM` field is read-only zero for RV32.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "line_range": [ + 1847, + 1851 + ] + }, + { + "text": ".Legal values of `PMM` WARL field | |Value|Description |00|Pointer masking is disabled (PMLEN = 0) |01|Reserved |10|Pointer masking is enabled with PMLEN = XLEN - 57 (PMLEN = 7 on RV64) |11|Pointer masking is enabled with PMLEN = XLEN - 48 (PMLEN = 16 on RV64) |", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "line_range": [ + 1853, + 1862 + ] + }, + { + "text": "The Zicfilp extension adds the `MLPE` field in `mseccfg`.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "line_range": [ + 1864, + 1867 + ] + }, + { + "text": "When `MLPE` field is 1, Zicfilp extension is enabled in M-mode.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "line_range": [ + 1864, + 1867 + ] + }, + { + "text": "When the `MLPE` field is 0, the Zicfilp extension is not enabled in M-mode and the following rules apply to M-mode.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "line_range": [ + 1864, + 1867 + ] + }, + { + "text": "* The hart does not update the `ELP` state; it remains as `NOLPEXPECTED`. * The `LPAD` instruction operates as a no-op.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "line_range": [ + 1869, + 1871 + ] + }, + { + "text": "When XLEN=32 only, `mseccfgh` is a 32-bit read/write register that aliases bits 63:32 of `mseccfg`.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "line_range": [ + 1873, + 1876 + ] + }, + { + "text": "Register `mseccfgh` exists when XLEN=32 and `mseccfg` is implemented; it does not exist when XLEN=64.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level CSRs > Machine Security Configuration (`mseccfg`) Register", + "line_range": [ + 1873, + 1876 + ] + }, + { + "text": "Platforms provide a real-time counter, exposed as a memory-mapped machine-mode read-write register, `mtime`. `mtime` must increment at constant frequency, and the platform must provide a mechanism for determining the period of an `mtime` tick.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level Memory-Mapped Registers > Machine Timer (`mtime` and `mtimecmp`) Registers", + "line_range": [ + 1882, + 1887 + ] + }, + { + "text": "The `mtime` register will wrap around if the count overflows.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level Memory-Mapped Registers > Machine Timer (`mtime` and `mtimecmp`) Registers", + "line_range": [ + 1882, + 1887 + ] + }, + { + "text": "The `mtime` register has a 64-bit precision on all RV32 and RV64 systems.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level Memory-Mapped Registers > Machine Timer (`mtime` and `mtimecmp`) Registers", + "line_range": [ + 1889, + 1898 + ] + }, + { + "text": "Platforms provide a 64-bit memory-mapped machine-mode timer compare register (`mtimecmp`). A machine timer interrupt becomes pending whenever `mtime` contains a value greater than or equal to `mtimecmp`, treating the values as unsigned integers.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level Memory-Mapped Registers > Machine Timer (`mtime` and `mtimecmp`) Registers", + "line_range": [ + 1889, + 1898 + ] + }, + { + "text": "The interrupt remains posted until `mtimecmp` becomes greater than `mtime` (typically as a result of writing `mtimecmp`).", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level Memory-Mapped Registers > Machine Timer (`mtime` and `mtimecmp`) Registers", + "line_range": [ + 1889, + 1898 + ] + }, + { + "text": "The interrupt will only be taken if interrupts are enabled and the MTIE bit is set in the `mie` register.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level Memory-Mapped Registers > Machine Timer (`mtime` and `mtimecmp`) Registers", + "line_range": [ + 1889, + 1898 + ] + }, + { + "text": ".Machine time register (memory-mapped control register). include::images/bytefield/mtime.edn[]", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level Memory-Mapped Registers > Machine Timer (`mtime` and `mtimecmp`) Registers", + "line_range": [ + 1900, + 1902 + ] + }, + { + "text": ".Machine time compare register (memory-mapped control register). include::images/bytefield/mtimecmp.edn[]", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level Memory-Mapped Registers > Machine Timer (`mtime` and `mtimecmp`) Registers", + "line_range": [ + 1904, + 1906 + ] + }, + { + "text": "If the result of the comparison between `mtime` and `mtimecmp` changes, it is guaranteed to be reflected in MTIP eventually, but not necessarily immediately.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level Memory-Mapped Registers > Machine Timer (`mtime` and `mtimecmp`) Registers", + "line_range": [ + 1908, + 1909 + ] + }, + { + "text": "In RV32, memory-mapped writes to `mtimecmp` modify only one 32-bit part of the register.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level Memory-Mapped Registers > Machine Timer (`mtime` and `mtimecmp`) Registers", + "line_range": [ + 1911, + 1914 + ] + }, + { + "text": "The following code sequence sets a 64-bit `mtimecmp` value without spuriously generating a timer interrupt due to the intermediate value of the comparand:", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level Memory-Mapped Registers > Machine Timer (`mtime` and `mtimecmp`) Registers", + "line_range": [ + 1911, + 1914 + ] + }, + { + "text": "For RV64, naturally aligned 64-bit memory accesses to the `mtime` and `mtimecmp` registers are additionally supported and are atomic.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level Memory-Mapped Registers > Machine Timer (`mtime` and `mtimecmp`) Registers", + "line_range": [ + 1916, + 1917 + ] + }, + { + "text": ".Sample code for setting the 64-bit time comparand in RV32 assuming a little-endian memory system and that the registers live in a strongly ordered I/O region.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level Memory-Mapped Registers > Machine Timer (`mtime` and `mtimecmp`) Registers", + "line_range": [ + 1919, + 1927 + ] + }, + { + "text": "Storing -1 to the low-order bits of `mtimecmp` prevents `mtimecmp` from temporarily becoming smaller than the lesser of the old and new values. ....", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level Memory-Mapped Registers > Machine Timer (`mtime` and `mtimecmp`) Registers", + "line_range": [ + 1919, + 1927 + ] + }, + { + "text": "New comparand is in a1:a0. li t0, -1 la t1, mtimecmp sw t0, 0(t1) No smaller than old value. sw a1, 4(t1) No smaller than new value. sw a0, 0(t1) New value. ....", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level Memory-Mapped Registers > Machine Timer (`mtime` and `mtimecmp`) Registers", + "line_range": [ + 1919, + 1927 + ] + }, + { + "text": "The `time` CSR is a read-only shadow of the memory-mapped `mtime` register.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level Memory-Mapped Registers > Machine Timer (`mtime` and `mtimecmp`) Registers", + "line_range": [ + 1929, + 1934 + ] + }, + { + "text": "When XLEN=32, the `timeh` CSR is a read-only shadow of the upper 32 bits of the memory-mapped `mtime` register, while `time` shadows only the lower 32 bits of `mtime`.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level Memory-Mapped Registers > Machine Timer (`mtime` and `mtimecmp`) Registers", + "line_range": [ + 1929, + 1934 + ] + }, + { + "text": "When `mtime` changes, it is guaranteed to be reflected in `time` and `timeh` eventually, but not necessarily immediately.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Level Memory-Mapped Registers > Machine Timer (`mtime` and `mtimecmp`) Registers", + "line_range": [ + 1929, + 1934 + ] + }, + { + "text": "The ECALL instruction is used to make a request to the supporting execution environment.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Mode Privileged Instructions > Environment Call and Breakpoint", + "line_range": [ + 1943, + 1948 + ] + }, + { + "text": "When executed in U-mode, S-mode, or M-mode, it generates an environment-call-from-U-mode exception, environment-call-from-S-mode exception, or environment-call-from-M-mode exception, respectively, and performs no other operation.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Mode Privileged Instructions > Environment Call and Breakpoint", + "line_range": [ + 1943, + 1948 + ] + }, + { + "text": "The EBREAK instruction is used by debuggers to cause control to be transferred back to a debugging environment.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Mode Privileged Instructions > Environment Call and Breakpoint", + "line_range": [ + 1950, + 1954 + ] + }, + { + "text": "Unless overridden by an external debug environment, EBREAK raises a breakpoint exception and performs no other operation.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Mode Privileged Instructions > Environment Call and Breakpoint", + "line_range": [ + 1950, + 1954 + ] + }, + { + "text": "ECALL and EBREAK cause the receiving privilege mode’s `epc` register to be set to the address of the ECALL or EBREAK instruction itself, not the address of the following instruction.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Mode Privileged Instructions > Environment Call and Breakpoint", + "line_range": [ + 1956, + 1961 + ] + }, + { + "text": "As ECALL and EBREAK cause synchronous exceptions, they are not considered to retire, and should not increment the `minstret` CSR.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Mode Privileged Instructions > Environment Call and Breakpoint", + "line_range": [ + 1956, + 1961 + ] + }, + { + "text": "Instructions to return from trap are encoded under the PRIV minor opcode.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Mode Privileged Instructions > Trap-Return Instructions", + "line_range": [ + 1966, + 1967 + ] + }, + { + "text": "include::images/wavedrom/trap-return.edn[]", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Mode Privileged Instructions > Trap-Return Instructions", + "line_range": [ + 1969, + 1970 + ] + }, + { + "text": "To return after handling a trap, there are separate trap return instructions per privilege level, MRET and SRET. MRET is always provided. SRET must be provided if supervisor mode is supported, and should raise an illegal-instruction exception otherwise. SRET should also raise an illegal-instruction exception when TSR=1 in `mstatus`, as described in .", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Mode Privileged Instructions > Trap-Return Instructions", + "line_range": [ + 1972, + 1984 + ] + }, + { + "text": "An xRET instruction can be executed in privilege mode x or higher, where executing a lower-privilege xRET instruction will pop the relevant lower-privilege interrupt enable and privilege mode stack.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Mode Privileged Instructions > Trap-Return Instructions", + "line_range": [ + 1972, + 1984 + ] + }, + { + "text": "Attempting to execute an xRET instruction in a mode less privileged than x will raise an illegal-instruction exception.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Mode Privileged Instructions > Trap-Return Instructions", + "line_range": [ + 1972, + 1984 + ] + }, + { + "text": "In addition to manipulating the privilege stack as described in , xRET sets the `pc` to the value stored in the `xepc` register.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Mode Privileged Instructions > Trap-Return Instructions", + "line_range": [ + 1986, + 1987 + ] + }, + { + "text": "If the Zalrsc extension is supported, the xRET instruction is allowed to clear any outstanding LR address reservation but is not required to.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Mode Privileged Instructions > Trap-Return Instructions", + "line_range": [ + 1989, + 1992 + ] + }, + { + "text": "Trap handlers should explicitly clear the reservation if required (e.g., by using a dummy SC) before executing the xRET.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Mode Privileged Instructions > Trap-Return Instructions", + "line_range": [ + 1989, + 1992 + ] + }, + { + "text": "The Wait for Interrupt instruction (WFI) informs the implementation that the current hart can be stalled until an interrupt might need servicing.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Mode Privileged Instructions > Wait for Interrupt", + "line_range": [ + 1997, + 2005 + ] + }, + { + "text": "Execution of the WFI instruction can also be used to inform the hardware platform that suitable interrupts should preferentially be routed to this hart. WFI is available in all privileged modes, and optionally available to U-mode.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Mode Privileged Instructions > Wait for Interrupt", + "line_range": [ + 1997, + 2005 + ] + }, + { + "text": "This instruction may raise an illegal-instruction exception when TW=1 in `mstatus`, as described in .", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Mode Privileged Instructions > Wait for Interrupt", + "line_range": [ + 1997, + 2005 + ] + }, + { + "text": "include::images/wavedrom/wfi.edn[]", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Mode Privileged Instructions > Wait for Interrupt", + "line_range": [ + 2007, + 2008 + ] + }, + { + "text": "If an enabled interrupt is present or later becomes present while the hart is stalled, the interrupt trap will be taken on the following instruction, i.e., execution resumes in the trap handler and `mepc` = `pc` + 4.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Mode Privileged Instructions > Wait for Interrupt", + "line_range": [ + 2010, + 2012 + ] + }, + { + "text": "Implementations are permitted to resume execution for any reason, even if an enabled interrupt has not become pending.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Mode Privileged Instructions > Wait for Interrupt", + "line_range": [ + 2014, + 2016 + ] + }, + { + "text": "Hence, a legal implementation is to simply implement the WFI instruction as a NOP.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Mode Privileged Instructions > Wait for Interrupt", + "line_range": [ + 2014, + 2016 + ] + }, + { + "text": "The WFI instruction can also be executed when interrupts are disabled.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Mode Privileged Instructions > Wait for Interrupt", + "line_range": [ + 2018, + 2027 + ] + }, + { + "text": "The operation of WFI must be unaffected by the global interrupt bits in `mstatus` (MIE and SIE) and the delegation register `mideleg` (i.e., the hart must resume if a locally enabled interrupt becomes pending, even if it has been delegated to a less-privileged mode), but should honor the individual interrupt enables (e.g, MTIE) (i.e., implementations should avoid resuming the hart if the interrupt is pending but not individually enabled). WFI is also required to resume execution for locally enabled interrupts pending at any privilege level, regardless of the global interrupt enable at each privilege level.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Mode Privileged Instructions > Wait for Interrupt", + "line_range": [ + 2018, + 2027 + ] + }, + { + "text": "If the event that causes the hart to resume execution does not cause an interrupt to be taken, execution will resume at `pc` + 4, and software must determine what action to take, including looping back to repeat the WFI if there was no actionable event.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Mode Privileged Instructions > Wait for Interrupt", + "line_range": [ + 2029, + 2032 + ] + }, + { + "text": "The subspace of the SYSTEM major opcode shown in is designated for custom use.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Mode Privileged Instructions > Custom SYSTEM Instructions", + "line_range": [ + 2036, + 2037 + ] + }, + { + "text": "It is recommended that these instructions use bits 29:28 to designate the minimum required privilege mode, as do other SYSTEM instructions.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Mode Privileged Instructions > Custom SYSTEM Instructions", + "line_range": [ + 2036, + 2037 + ] + }, + { + "text": ".SYSTEM instruction encodings designated for custom use. include::images/bytefield/cust-sys-instr.edn[]", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Machine-Mode Privileged Instructions > Custom SYSTEM Instructions", + "line_range": [ + 2039, + 2041 + ] + }, + { + "text": "Upon reset, a hart’s privilege mode is set to M.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Reset", + "line_range": [ + 2046, + 2063 + ] + }, + { + "text": "The `mstatus` fields MIE and MPRV are reset to 0.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Reset", + "line_range": [ + 2046, + 2063 + ] + }, + { + "text": "If little-endian memory accesses are supported, the `mstatus`/`mstatush` field MBE is reset to 0.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Reset", + "line_range": [ + 2046, + 2063 + ] + }, + { + "text": "The `misa` register is reset to enable the maximal set of supported extensions, as described in .", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Reset", + "line_range": [ + 2046, + 2063 + ] + }, + { + "text": "For implementations with the Zalrsc standard extension, there is no valid load reservation.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Reset", + "line_range": [ + 2046, + 2063 + ] + }, + { + "text": "The `pc` is set to an implementation-defined reset vector.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Reset", + "line_range": [ + 2046, + 2063 + ] + }, + { + "text": "The `mcause` register is set to a value indicating the cause of the reset.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Reset", + "line_range": [ + 2046, + 2063 + ] + }, + { + "text": "Writable PMP registers’ A and L fields are set to 0, unless the platform mandates a different reset value for some PMP registers’ A and L fields.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Reset", + "line_range": [ + 2046, + 2063 + ] + }, + { + "text": "If the hypervisor extension is implemented, the `hgatp`.MODE and `vsatp`.MODE fields are reset to 0.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Reset", + "line_range": [ + 2046, + 2063 + ] + }, + { + "text": "If the Smrnmi extension is implemented, the `mnstatus`.NMIE field is reset to 0.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Reset", + "line_range": [ + 2046, + 2063 + ] + }, + { + "text": "No *WARL* field contains an illegal value.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Reset", + "line_range": [ + 2046, + 2063 + ] + }, + { + "text": "If the Zicfilp extension is implemented, the `mseccfg`.MLPE field is reset to 0.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Reset", + "line_range": [ + 2046, + 2063 + ] + }, + { + "text": "All other hart state is UNSPECIFIED.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Reset", + "line_range": [ + 2046, + 2063 + ] + }, + { + "text": "The `MML`, `MMWP`, and `RLB` fields of the `mseccfg` register are set to 0, unless the platform mandates a different reset value.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Reset", + "line_range": [ + 2065, + 2066 + ] + }, + { + "text": "The `mcause` values after reset have implementation-specific interpretation, but the value 0 should be returned on implementations that do not distinguish different reset conditions.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Reset", + "line_range": [ + 2068, + 2072 + ] + }, + { + "text": "Implementations that distinguish different reset conditions should only use 0 to indicate the most complete reset.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Reset", + "line_range": [ + 2068, + 2072 + ] + }, + { + "text": "The `USEED` and `SSEED` fields of the `mseccfg` CSR must have defined reset values.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Reset", + "line_range": [ + 2074, + 2076 + ] + }, + { + "text": "The system must not allow them to be in an undefined state after reset.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Reset", + "line_range": [ + 2074, + 2076 + ] + }, + { + "text": "Non-maskable interrupts (NMIs) are only used for hardware error conditions, and cause an immediate jump to an implementation-defined NMI vector running in M-mode regardless of the state of a hart’s interrupt enable bits.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Non-Maskable Interrupts", + "line_range": [ + 2081, + 2087 + ] + }, + { + "text": "The `mepc` register is written with the virtual address of the instruction that was interrupted, and `mcause` is set to a value indicating the source of the NMI.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Non-Maskable Interrupts", + "line_range": [ + 2081, + 2087 + ] + }, + { + "text": "The NMI can thus overwrite state in an active machine-mode interrupt handler.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Non-Maskable Interrupts", + "line_range": [ + 2081, + 2087 + ] + }, + { + "text": "The values written to `mcause` on an NMI are implementation-defined.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Non-Maskable Interrupts", + "line_range": [ + 2089, + 2093 + ] + }, + { + "text": "The high Interrupt bit of `mcause` should be set to indicate that this was an interrupt.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Non-Maskable Interrupts", + "line_range": [ + 2089, + 2093 + ] + }, + { + "text": "An Exception Code of 0 is reserved to mean \"unknown cause\" and implementations that do not distinguish sources of NMIs via the `mcause` register should return 0 in the Exception Code.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Non-Maskable Interrupts", + "line_range": [ + 2089, + 2093 + ] + }, + { + "text": "Unlike resets, NMIs do not reset processor state, enabling diagnosis, reporting, and possible containment of the hardware error.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Non-Maskable Interrupts", + "line_range": [ + 2095, + 2096 + ] + }, + { + "text": "The physical memory map for a complete system includes various address ranges, some corresponding to memory regions and some to memory-mapped control registers, portions of which might not be accessible.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes", + "line_range": [ + 2101, + 2113 + ] + }, + { + "text": "Some memory regions might not support reads, writes, or execution; some might not support subword or subblock accesses; some might not support atomic operations; and some might not support cache coherence or might have different memory models.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes", + "line_range": [ + 2101, + 2113 + ] + }, + { + "text": "Similarly, memory-mapped control registers vary in their supported access widths, support for atomic operations, and whether read and write accesses have associated side effects.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes", + "line_range": [ + 2101, + 2113 + ] + }, + { + "text": "In RISC-V systems, these properties and capabilities of each region of the machine's physical address space are termed physical memory attributes (PMAs).", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes", + "line_range": [ + 2101, + 2113 + ] + }, + { + "text": "This section describes RISC-V PMA terminology and how RISC-V systems implement and check PMAs.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes", + "line_range": [ + 2101, + 2113 + ] + }, + { + "text": "PMAs are inherent properties of the underlying hardware and rarely change during system operation.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes", + "line_range": [ + 2115, + 2127 + ] + }, + { + "text": "Unlike physical memory protection values described in , PMAs do not vary by execution context.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes", + "line_range": [ + 2115, + 2127 + ] + }, + { + "text": "The PMAs of some memory regions are fixed at chip design time—for example, for an on-chip ROM.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes", + "line_range": [ + 2115, + 2127 + ] + }, + { + "text": "Others are fixed at board design time, depending, for example, on which other chips are connected to off-chip buses.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes", + "line_range": [ + 2115, + 2127 + ] + }, + { + "text": "Off-chip buses might also support devices that could be changed on every power cycle (cold pluggable) or dynamically while the system is running (hot pluggable).", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes", + "line_range": [ + 2115, + 2127 + ] + }, + { + "text": "Some devices might be configurable at run time to support different uses that imply different PMAs—for example, an on-chip scratchpad RAM might be cached privately by one core in one end-application, or accessed as a shared non-cached memory in another end-application.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes", + "line_range": [ + 2115, + 2127 + ] + }, + { + "text": "Most systems will require that at least some PMAs are dynamically checked in hardware later in the execution pipeline after the physical address is known, as some operations will not be supported at all physical memory addresses, and some operations require knowing the current setting of a configurable PMA attribute.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes", + "line_range": [ + 2129, + 2141 + ] + }, + { + "text": "While many other architectures specify some PMAs in the virtual memory page tables and use the TLB to inform the pipeline of these properties, this approach injects platform-specific information into a virtualized layer and can cause system errors unless attributes are correctly initialized in each page-table entry for each physical memory region.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes", + "line_range": [ + 2129, + 2141 + ] + }, + { + "text": "In addition, the available page sizes might not be optimal for specifying attributes in the physical memory space, leading to address-space fragmentation and inefficient use of expensive TLB entries.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes", + "line_range": [ + 2129, + 2141 + ] + }, + { + "text": "For RISC-V, we separate out specification and checking of PMAs into a separate hardware structure, the PMA checker.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes", + "line_range": [ + 2143, + 2161 + ] + }, + { + "text": "In many cases, the attributes are known at system design time for each physical address region, and can be hardwired into the PMA checker.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes", + "line_range": [ + 2143, + 2161 + ] + }, + { + "text": "Where the attributes are run-time configurable, platform-specific memory-mapped control registers can be provided to specify these attributes at a granularity appropriate to each region on the platform (e.g., for an on-chip SRAM that can be flexibly divided between cacheable and uncacheable uses). PMAs are checked for any access to physical memory, including accesses that have undergone virtual to physical memory translation.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes", + "line_range": [ + 2143, + 2161 + ] + }, + { + "text": "To aid in system debugging, we strongly recommend that, where possible, RISC-V processors precisely trap physical memory accesses that fail PMA checks.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes", + "line_range": [ + 2143, + 2161 + ] + }, + { + "text": "Precisely trapped PMA violations manifest as instruction, load, or store access-fault exceptions, distinct from virtual-memory page-fault exceptions.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes", + "line_range": [ + 2143, + 2161 + ] + }, + { + "text": "Precise PMA traps might not always be possible, for example, when probing a legacy bus architecture that uses access failures as part of the discovery mechanism.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes", + "line_range": [ + 2143, + 2161 + ] + }, + { + "text": "In this case, error responses from peripheral devices will be reported as imprecise bus-error interrupts.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes", + "line_range": [ + 2143, + 2161 + ] + }, + { + "text": "PMAs must also be readable by software to correctly access certain devices or to correctly configure other hardware components that access memory, such as DMA engines.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes", + "line_range": [ + 2163, + 2173 + ] + }, + { + "text": "As PMAs are tightly tied to a given physical platform’s organization, many details are inherently platform-specific, as is the means by which software can learn the PMA values for a platform.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes", + "line_range": [ + 2163, + 2173 + ] + }, + { + "text": "Some devices, particularly legacy buses, do not support discovery of PMAs and so will give error responses or time out if an unsupported access is attempted.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes", + "line_range": [ + 2163, + 2173 + ] + }, + { + "text": "Typically, platform-specific machine-mode code will extract PMAs and ultimately present this information to higher-level less-privileged software using some standard representation.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes", + "line_range": [ + 2163, + 2173 + ] + }, + { + "text": "Where platforms support dynamic reconfiguration of PMAs, an interface will be provided to set the attributes by passing requests to a machine-mode driver that can correctly reconfigure the platform.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes", + "line_range": [ + 2175, + 2180 + ] + }, + { + "text": "For example, switching cacheability attributes on some memory regions might involve platform-specific operations, such as cache flushes, that are available only to machine-mode.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes", + "line_range": [ + 2175, + 2180 + ] + }, + { + "text": "The most important characterization of a given memory address range is whether it holds regular main memory or I/O devices.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Main Memory versus I/O Regions", + "line_range": [ + 2184, + 2190 + ] + }, + { + "text": "Regular main memory is required to have a number of properties, specified below, whereas I/O devices can have a much broader range of attributes.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Main Memory versus I/O Regions", + "line_range": [ + 2184, + 2190 + ] + }, + { + "text": "Memory regions that do not fit into regular main memory, for example, device scratchpad RAMs, are categorized as I/O regions.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Main Memory versus I/O Regions", + "line_range": [ + 2184, + 2190 + ] + }, + { + "text": "NOTE: What previous versions of this specification termed vacant regions are no longer a distinct category; they are now described as I/O regions that are not accessible (i.e. lacking read, write, and execute permissions).", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Main Memory versus I/O Regions", + "line_range": [ + 2192, + 2195 + ] + }, + { + "text": "Main memory regions that are not accessible are also allowed.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Main Memory versus I/O Regions", + "line_range": [ + 2192, + 2195 + ] + }, + { + "text": "Access types specify which access widths, from 8-bit byte to long multi-word burst, are supported, and also whether misaligned accesses are supported for each access width.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Supported Access Type PMAs", + "line_range": [ + 2199, + 2201 + ] + }, + { + "text": "Main memory regions always support read and write of all access widths required by the attached devices, and can specify whether instruction fetch is supported.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Supported Access Type PMAs", + "line_range": [ + 2203, + 2204 + ] + }, + { + "text": "I/O regions can specify which combinations of read, write, or execute accesses to which data widths are supported.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Supported Access Type PMAs", + "line_range": [ + 2206, + 2207 + ] + }, + { + "text": "For systems with page-based virtual memory, I/O and memory regions can specify which combinations of hardware page-table reads and hardware page-table writes are supported.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Supported Access Type PMAs", + "line_range": [ + 2209, + 2211 + ] + }, + { + "text": "Atomicity PMAs describes which atomic instructions are supported in this address region.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Atomicity PMAs", + "line_range": [ + 2215, + 2217 + ] + }, + { + "text": "Support for atomic instructions is divided into two categories: LR/SC and AMOs.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Atomicity PMAs", + "line_range": [ + 2215, + 2217 + ] + }, + { + "text": "Within AMOs, there are four levels of support: AMONone, AMOSwap, AMOLogical, and AMOArithmetic. AMONone indicates that no AMO operations are supported. AMOSwap indicates that only `amoswap` instructions are supported in this address range. AMOLogical indicates that swap instructions plus all the logical AMOs (`amoand`, `amoor`, `amoxor`) are supported. AMOArithmetic indicates that all RISC-V AMOs defined by the A extension are supported.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Atomicity PMAs > AMO PMA", + "line_range": [ + 2221, + 2230 + ] + }, + { + "text": "For each level of support, naturally aligned AMOs of a given width are supported if the underlying memory region supports reads and writes of that width.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Atomicity PMAs > AMO PMA", + "line_range": [ + 2221, + 2230 + ] + }, + { + "text": "Main memory and I/O regions may only support a subset or none of the processor-supported atomic operations.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Atomicity PMAs > AMO PMA", + "line_range": [ + 2221, + 2230 + ] + }, + { + "text": ".Classes of AMOs supported by I/O regions. [i%autowidth,float=\"center\",align=\"center\",cols=\"<,<\",options=\"header\"] | |AMO Class |Supported Operations |AMONone + AMOSwap + AMOLogical + AMOArithmetic |None + `amoswap` + above + `amoand`, `amoor`, `amoxor` + above + `amoadd`, `amomin`, `amomax`, `amominu`, `amomaxu` |", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Atomicity PMAs > AMO PMA", + "line_range": [ + 2232, + 2245 + ] + }, + { + "text": "The Zacas extension defines three additional levels of support: AMOCASW, AMOCASD, and AMOCASQ.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Atomicity PMAs > AMO PMA", + "line_range": [ + 2247, + 2248 + ] + }, + { + "text": "AMOCASW indicates that in addition to instructions indicated by AMOArithmetic level support, the `AMOCAS.W` instruction is supported. AMOCASD indicates that in addition to instructions indicated by AMOCASW level support, the `AMOCAS.D` instruction is supported. AMOCASQ indicates that in addition to instructions indicated by AMOCASD level support, the `AMOCAS.Q` instruction is supported.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Atomicity PMAs > AMO PMA", + "line_range": [ + 2250, + 2254 + ] + }, + { + "text": "The AMOs specified by the Zabha extension require the same level of support as the corresponding instructions in the Zaamo standard extension or the Zacas extension.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Atomicity PMAs > AMO PMA", + "line_range": [ + 2256, + 2257 + ] + }, + { + "text": "The Ziccamoc extension requires AMOCASQ level support to main memory regions with both the coherence and cacheability PMAs.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Atomicity PMAs > AMO PMA", + "line_range": [ + 2259, + 2260 + ] + }, + { + "text": "For LR/SC, there are three levels of support indicating combinations of the reservability and eventuality properties: RsrvNone, RsrvNonEventual, and RsrvEventual.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Atomicity PMAs > Reservability PMA", + "line_range": [ + 2264, + 2271 + ] + }, + { + "text": "RsrvNone indicates that no LR/SC operations are supported (the location is non-reservable).", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Atomicity PMAs > Reservability PMA", + "line_range": [ + 2264, + 2271 + ] + }, + { + "text": "RsrvNonEventual indicates that the operations are supported (the location is reservable), but without the eventual success guarantee described in the unprivileged ISA specification.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Atomicity PMAs > Reservability PMA", + "line_range": [ + 2264, + 2271 + ] + }, + { + "text": "RsrvEventual indicates that the operations are supported and provide the eventual success guarantee.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Atomicity PMAs > Reservability PMA", + "line_range": [ + 2264, + 2271 + ] + }, + { + "text": "The misaligned atomicity granule PMA provides constrained support for misaligned AMOs.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Misaligned Atomicity Granule PMA", + "line_range": [ + 2276, + 2282 + ] + }, + { + "text": "This PMA, if present, specifies the size of a misaligned atomicity granule, a naturally aligned power-of-two number of bytes.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Misaligned Atomicity Granule PMA", + "line_range": [ + 2276, + 2282 + ] + }, + { + "text": "Specific supported values for this PMA are represented by MAGNN, e.g., MAG16 indicates the misaligned atomicity granule is at least 16 bytes.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Misaligned Atomicity Granule PMA", + "line_range": [ + 2276, + 2282 + ] + }, + { + "text": "The misaligned atomicity granule PMA applies only to AMOs, loads and stores defined in the base ISAs, and loads and stores of no more than XLEN bits defined in the F, D, and Q extensions, and compressed encodings thereof.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Misaligned Atomicity Granule PMA", + "line_range": [ + 2284, + 2290 + ] + }, + { + "text": "For an instruction in that set, if all accessed bytes lie within the same misaligned atomicity granule, the instruction will not raise an exception for reasons of address alignment, and the instruction will give rise to only one memory operation for the purposes of RVWMO--i.e., it will execute atomically.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Misaligned Atomicity Granule PMA", + "line_range": [ + 2284, + 2290 + ] + }, + { + "text": "If a misaligned AMO accesses a region that does not specify a misaligned atomicity granule PMA, or if not all accessed bytes lie within the same misaligned atomicity granule, then an exception is raised.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Misaligned Atomicity Granule PMA", + "line_range": [ + 2292, + 2300 + ] + }, + { + "text": "For regular loads and stores that access such a region or for which not all accessed bytes lie within the same atomicity granule, then either an exception is raised, or the access proceeds but is not guaranteed to be atomic.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Misaligned Atomicity Granule PMA", + "line_range": [ + 2292, + 2300 + ] + }, + { + "text": "Implementations may raise access-fault exceptions instead of address-misaligned exceptions for some misaligned accesses, indicating the instruction should not be emulated by a trap handler.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Misaligned Atomicity Granule PMA", + "line_range": [ + 2292, + 2300 + ] + }, + { + "text": "NOTE: LR/SC instructions are unaffected by this PMA and so always raise an exception when misaligned.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Misaligned Atomicity Granule PMA", + "line_range": [ + 2302, + 2306 + ] + }, + { + "text": "Vector memory accesses are also unaffected, so might execute non-atomically even when contained within a misaligned atomicity granule.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Misaligned Atomicity Granule PMA", + "line_range": [ + 2302, + 2306 + ] + }, + { + "text": "Implicit accesses are similarly unaffected by this PMA.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Misaligned Atomicity Granule PMA", + "line_range": [ + 2302, + 2306 + ] + }, + { + "text": "The Zama16b extension requires MAG16 support to main memory regions.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Misaligned Atomicity Granule PMA", + "line_range": [ + 2308, + 2309 + ] + }, + { + "text": "Regions of the address space are classified as either main memory or I/O for the purposes of ordering by the FENCE instruction and atomic-instruction ordering bits.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Memory-Ordering PMAs", + "line_range": [ + 2314, + 2316 + ] + }, + { + "text": "Accesses by one hart to main memory regions are observable not only by other harts but also by other devices with the capability to initiate requests in the main memory system (e.g., DMA engines).", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Memory-Ordering PMAs", + "line_range": [ + 2318, + 2323 + ] + }, + { + "text": "Coherent main memory regions always have either the RVWMO or RVTSO memory model.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Memory-Ordering PMAs", + "line_range": [ + 2318, + 2323 + ] + }, + { + "text": "Incoherent main memory regions have an implementation-defined memory model.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Memory-Ordering PMAs", + "line_range": [ + 2318, + 2323 + ] + }, + { + "text": "Accesses by one hart to an I/O region are observable not only by other harts and bus mastering devices but also by the targeted I/O devices, and I/O regions may be accessed with either relaxed or strong ordering.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Memory-Ordering PMAs", + "line_range": [ + 2325, + 2334 + ] + }, + { + "text": "Accesses to an I/O region with relaxed ordering are generally observed by other harts and bus mastering devices in a manner similar to the ordering of accesses to an RVWMO memory region, as discussed in the I/O Ordering section in .", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Memory-Ordering PMAs", + "line_range": [ + 2325, + 2334 + ] + }, + { + "text": "By contrast, accesses to an I/O region with strong ordering are generally observed by other harts and bus mastering devices in program order.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Memory-Ordering PMAs", + "line_range": [ + 2325, + 2334 + ] + }, + { + "text": "Each strongly ordered I/O region specifies a numbered ordering channel, which is a mechanism by which ordering guarantees can be provided between different I/O regions.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Memory-Ordering PMAs", + "line_range": [ + 2336, + 2341 + ] + }, + { + "text": "Channel 0 is used to indicate point-to-point strong ordering only, where only accesses by the hart to the single associated I/O region are strongly ordered.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Memory-Ordering PMAs", + "line_range": [ + 2336, + 2341 + ] + }, + { + "text": "Channel 1 is used to provide global strong ordering across all I/O regions.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Memory-Ordering PMAs", + "line_range": [ + 2343, + 2351 + ] + }, + { + "text": "Any accesses by a hart to any I/O region associated with channel 1 can only be observed to have occurred in program order by all other harts and I/O devices, including relative to accesses made by that hart to relaxed I/O regions or strongly ordered I/O regions with different channel numbers.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Memory-Ordering PMAs", + "line_range": [ + 2343, + 2351 + ] + }, + { + "text": "In other words, any access to a region in channel 1 is equivalent to executing a `fence io,io` instruction before and after the instruction.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Memory-Ordering PMAs", + "line_range": [ + 2343, + 2351 + ] + }, + { + "text": "Other larger channel numbers provide program ordering to accesses by that hart across any regions with the same channel number", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Memory-Ordering PMAs", + "line_range": [ + 2353, + 2355 + ] + }, + { + "text": "Systems might support dynamic configuration of ordering properties on each memory region.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Memory-Ordering PMAs", + "line_range": [ + 2357, + 2358 + ] + }, + { + "text": "Coherence is a property defined for a single physical address, and indicates that writes to that address by one agent will eventually be made visible to other coherent agents in the system.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Coherence and Cacheability PMAs", + "line_range": [ + 2362, + 2369 + ] + }, + { + "text": "Coherence is not to be confused with the memory consistency model of a system, which defines what values a memory read can return given the previous history of reads and writes to the entire memory system.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Coherence and Cacheability PMAs", + "line_range": [ + 2362, + 2369 + ] + }, + { + "text": "In RISC-V platforms, the use of hardware-incoherent regions is discouraged due to software complexity, performance, and energy impacts.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Coherence and Cacheability PMAs", + "line_range": [ + 2362, + 2369 + ] + }, + { + "text": "The cacheability of a memory region should not affect the software view of the region except for differences reflected in other PMAs, such as main memory versus I/O classification, memory ordering, supported accesses and atomic operations, and coherence.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Coherence and Cacheability PMAs", + "line_range": [ + 2371, + 2376 + ] + }, + { + "text": "For this reason, we treat cacheability as a platform-level setting managed by machine-mode software only.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Coherence and Cacheability PMAs", + "line_range": [ + 2371, + 2376 + ] + }, + { + "text": "Where a platform supports configurable cacheability settings for a memory region, a platform-specific machine-mode routine will change the settings and flush caches if necessary, so the system is only incoherent during the transition between cacheability settings.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Coherence and Cacheability PMAs", + "line_range": [ + 2378, + 2382 + ] + }, + { + "text": "This transitory state should not be visible to lower privilege levels.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Coherence and Cacheability PMAs", + "line_range": [ + 2378, + 2382 + ] + }, + { + "text": "If a PMA indicates non-cacheability, then accesses to that region must be satisfied by the memory itself, not by any caches.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Coherence and Cacheability PMAs", + "line_range": [ + 2384, + 2385 + ] + }, + { + "text": "Idempotency PMAs describe whether reads and writes to an address region are idempotent.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Idempotency PMAs", + "line_range": [ + 2389, + 2394 + ] + }, + { + "text": "Main memory regions are assumed to be idempotent.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Idempotency PMAs", + "line_range": [ + 2389, + 2394 + ] + }, + { + "text": "For I/O regions, idempotency on reads and writes can be specified separately (e.g., reads are idempotent but writes are not).", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Idempotency PMAs", + "line_range": [ + 2389, + 2394 + ] + }, + { + "text": "If accesses are non-idempotent, i.e., there is potentially a side effect on any read or write access, then speculative or redundant accesses must be avoided.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Idempotency PMAs", + "line_range": [ + 2389, + 2394 + ] + }, + { + "text": "For the purposes of defining the idempotency PMAs, changes in observed memory ordering created by redundant accesses are not considered a side effect.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Idempotency PMAs", + "line_range": [ + 2396, + 2398 + ] + }, + { + "text": "For non-idempotent regions, implicit reads and writes must not be performed early or speculatively, with the following exceptions.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Idempotency PMAs", + "line_range": [ + 2400, + 2413 + ] + }, + { + "text": "When a non-speculative implicit read is performed, an implementation is permitted to additionally read any of the bytes within a naturally aligned power-of-2 region containing the address of the non-speculative implicit read.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Idempotency PMAs", + "line_range": [ + 2400, + 2413 + ] + }, + { + "text": "Furthermore, when a non-speculative instruction fetch is performed, an implementation is permitted to additionally read any of the bytes within the next naturally aligned power-of-2 region of the same size (with the address of the region taken modulo 2^XLEN^).", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Idempotency PMAs", + "line_range": [ + 2400, + 2413 + ] + }, + { + "text": "The results of these additional reads may be used to satisfy subsequent early or speculative implicit reads.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Idempotency PMAs", + "line_range": [ + 2400, + 2413 + ] + }, + { + "text": "The size of these naturally aligned power-of-2 regions is implementation-defined, but, for systems with page-based virtual memory, must not exceed the smallest supported page size.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Attributes > Idempotency PMAs", + "line_range": [ + 2400, + 2413 + ] + }, + { + "text": "To support secure processing and contain faults, it is desirable to limit the physical addresses accessible by software running on a hart.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection", + "line_range": [ + 2418, + 2424 + ] + }, + { + "text": "An optional physical memory protection (PMP) unit provides per-hart machine-mode control registers to allow physical memory access privileges (read, write, execute) to be specified for each physical memory region.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection", + "line_range": [ + 2418, + 2424 + ] + }, + { + "text": "The PMP values are checked in parallel with the PMA checks described in .", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection", + "line_range": [ + 2418, + 2424 + ] + }, + { + "text": "The granularity of PMP access control settings are platform-specific, but the standard PMP encoding supports regions as small as four bytes.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection", + "line_range": [ + 2426, + 2430 + ] + }, + { + "text": "Certain regions’ privileges can be hardwired—for example, some regions might only ever be visible in machine mode but in no lower-privilege layers.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection", + "line_range": [ + 2426, + 2430 + ] + }, + { + "text": "PMP checks are applied to all accesses whose effective privilege mode is S or U, including instruction fetches and data accesses in S and U mode, and data accesses in M-mode when the MPRV bit in `mstatus` is set and the MPP field in `mstatus` contains S or U. PMP checks are also applied to page-table accesses for virtual-address translation, for which the effective privilege mode is S.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection", + "line_range": [ + 2432, + 2442 + ] + }, + { + "text": "Optionally, PMP checks may additionally apply to M-mode accesses, in which case the PMP registers themselves are locked, so that even M-mode software cannot change them until the hart is reset.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection", + "line_range": [ + 2432, + 2442 + ] + }, + { + "text": "In effect, PMP can grant permissions to S and U modes, which by default have none, and can revoke permissions from M-mode, which by default has full permissions.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection", + "line_range": [ + 2432, + 2442 + ] + }, + { + "text": "PMP violations are always trapped precisely at the processor.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection", + "line_range": [ + 2444, + 2444 + ] + }, + { + "text": "PMP entries are described by an 8-bit configuration register and one MXLEN-bit address register.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs", + "line_range": [ + 2448, + 2454 + ] + }, + { + "text": "Some PMP settings additionally use the address register associated with the preceding PMP entry.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs", + "line_range": [ + 2448, + 2454 + ] + }, + { + "text": "Up to 64 PMP entries are supported.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs", + "line_range": [ + 2448, + 2454 + ] + }, + { + "text": "Implementations may implement zero, 16, or 64 PMP entries; the lowest-numbered PMP entries must be implemented first.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs", + "line_range": [ + 2448, + 2454 + ] + }, + { + "text": "All PMP CSR fields are *WARL* and may be read-only zero. PMP CSRs are only accessible to M-mode.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs", + "line_range": [ + 2448, + 2454 + ] + }, + { + "text": "The PMP configuration registers are densely packed into CSRs to minimize context-switch time.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs", + "line_range": [ + 2456, + 2464 + ] + }, + { + "text": "For RV32, sixteen CSRs, `pmpcfg0`–`pmpcfg15`, hold the configurations `pmp0cfg`–`pmp63cfg` for the 64 PMP entries, as shown in .", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs", + "line_range": [ + 2456, + 2464 + ] + }, + { + "text": "For RV64, eight even-numbered CSRs, `pmpcfg0`, `pmpcfg2`, …, `pmpcfg14`, hold the configurations for the 64 PMP entries, as shown in .", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs", + "line_range": [ + 2456, + 2464 + ] + }, + { + "text": "For RV64, the odd-numbered configuration registers, `pmpcfg1`, `pmpcfg3`, …, `pmpcfg15`, are illegal.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs", + "line_range": [ + 2456, + 2464 + ] + }, + { + "text": ".RV32 PMP configuration CSR layout. include::images/bytefield/pmp-rv32.edn[]", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs", + "line_range": [ + 2466, + 2468 + ] + }, + { + "text": ".RV64 PMP configuration CSR layout. include::images/bytefield/pmp-rv64.edn[]", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs", + "line_range": [ + 2470, + 2472 + ] + }, + { + "text": "The PMP address registers are CSRs named `pmpaddr0`-`pmpaddr63`.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs", + "line_range": [ + 2474, + 2480 + ] + }, + { + "text": "Each PMP address register encodes bits 33-2 of a 34-bit physical address for RV32, as shown in .", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs", + "line_range": [ + 2474, + 2480 + ] + }, + { + "text": "For RV64, each PMP address register encodes bits 55-2 of a 56-bit physical address, as shown in .", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs", + "line_range": [ + 2474, + 2480 + ] + }, + { + "text": "Not all physical address bits may be implemented, and so the `pmpaddr` registers are *WARL*.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs", + "line_range": [ + 2474, + 2480 + ] + }, + { + "text": ".PMP address register format, RV32. include::images/bytefield/pmpaddr-rv32.edn[]", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs", + "line_range": [ + 2482, + 2484 + ] + }, + { + "text": ".PMP address register format, RV64. include::images/bytefield/pmpaddr-rv64.edn[]", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs", + "line_range": [ + 2486, + 2488 + ] + }, + { + "text": "shows the layout of a PMP configuration register.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs", + "line_range": [ + 2490, + 2495 + ] + }, + { + "text": "The R, W, and X bits, when set, indicate that the PMP entry permits read, write, and instruction execution, respectively.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs", + "line_range": [ + 2490, + 2495 + ] + }, + { + "text": "When one of these bits is clear, the corresponding access type is denied.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs", + "line_range": [ + 2490, + 2495 + ] + }, + { + "text": "The R, W, and X fields form a collective *WARL* field for which the combinations with R=0 and W=1 are reserved.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs", + "line_range": [ + 2490, + 2495 + ] + }, + { + "text": "The remaining two fields, A and L, are described in the following sections.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs", + "line_range": [ + 2490, + 2495 + ] + }, + { + "text": ".PMP configuration register format. include::images/bytefield/pmpcfg.edn[]", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs", + "line_range": [ + 2497, + 2499 + ] + }, + { + "text": "Attempting to fetch an instruction from a PMP region that does not have execute permissions raises an instruction access-fault exception.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs", + "line_range": [ + 2501, + 2508 + ] + }, + { + "text": "Attempting to execute a load, load-reserved, or cache-block management instruction which accesses a physical address within a PMP region without read permissions raises a load access-fault exception.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs", + "line_range": [ + 2501, + 2508 + ] + }, + { + "text": "Attempting to execute a store, store-conditional, AMO, or cache-block zero instruction which accesses a physical address within a PMP region without write permissions raises a store access-fault exception.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs", + "line_range": [ + 2501, + 2508 + ] + }, + { + "text": "The A field in a PMP entry's configuration register encodes the address-matching mode of the associated PMP address register.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Address Matching", + "line_range": [ + 2514, + 2521 + ] + }, + { + "text": "The encoding of this field is shown in .", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Address Matching", + "line_range": [ + 2514, + 2521 + ] + }, + { + "text": "When A=0, this PMP entry is disabled and matches no addresses.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Address Matching", + "line_range": [ + 2514, + 2521 + ] + }, + { + "text": "Two other address-matching modes are supported: naturally aligned power-of-2 regions (NAPOT), including the special case of naturally aligned four-byte regions (NA4); and the top boundary of an arbitrary range (TOR).", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Address Matching", + "line_range": [ + 2514, + 2521 + ] + }, + { + "text": "These modes support four-byte granularity.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Address Matching", + "line_range": [ + 2514, + 2521 + ] + }, + { + "text": ".Encoding of A field in PMP configuration registers. | |A |Name |Description |0 + 1 + 2 + 3 |OFF + TOR + NA4 + NAPOT |Null region (disabled) + Top of range + Naturally aligned four-byte region + Naturally aligned power-of-two region, {ge}8 bytes |", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Address Matching", + "line_range": [ + 2523, + 2541 + ] + }, + { + "text": "NAPOT ranges make use of the low-order bits of the associated address register to encode the size of the range, as shown in .", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Address Matching", + "line_range": [ + 2543, + 2545 + ] + }, + { + "text": ".`NAPOT` range encoding in PMP address and configuration registers. | |`pmpaddr` |`pmpcfg`.A |Match type and size |`yyyy...yyyy` + `yyyy...yyy0` + `yyyy...yy01` + `yyyy...y011` + ... + `yy01...1111` + `y011...1111` + `0111...1111` + `1111...1111` |NA4 + NAPOT + NAPOT + NAPOT + ... + NAPOT + NAPOT + NAPOT + NAPOT |4-byte NAPOT range + 8-byte NAPOT range + 16-byte NAPOT range + 32-byte NAPOT range + … + 2^XLEN^-byte NAPOT range + 2^XLEN+1^-byte NAPOT range + 2^XLEN+2^-byte NAPOT range + 2^XLEN+3^-byte NAPOT range |", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Address Matching", + "line_range": [ + 2547, + 2579 + ] + }, + { + "text": "If TOR is selected, the associated address register forms the top of the address range, and the preceding PMP address register forms the bottom of the address range.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Address Matching", + "line_range": [ + 2581, + 2585 + ] + }, + { + "text": "If PMP entry i's A field is set to TOR, the entry matches any address y such that `pmpaddr~i-1~`{le}y<``pmpaddr~i~`` (irrespective of the value of `pmpcfg~i-1~`).", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Address Matching", + "line_range": [ + 2581, + 2585 + ] + }, + { + "text": "If PMP entry 0's A field is set to TOR, zero is used for the lower bound, and so it matches any address `y Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Address Matching", + "line_range": [ + 2581, + 2585 + ] + }, + { + "text": "Although the PMP mechanism supports regions as small as four bytes, platforms may specify coarser PMP regions.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Address Matching", + "line_range": [ + 2587, + 2602 + ] + }, + { + "text": "In general, the PMP grain is 2^G+2^ bytes and must be the same across all PMP regions.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Address Matching", + "line_range": [ + 2587, + 2602 + ] + }, + { + "text": "When G {ge} 1, the NA4 mode is not selectable.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Address Matching", + "line_range": [ + 2587, + 2602 + ] + }, + { + "text": "When G {ge} 2 and pmpcfg~i~.A[1] is set, i.e. the mode is NAPOT, then bits pmpaddr~i~[G-2:0] read as all ones.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Address Matching", + "line_range": [ + 2587, + 2602 + ] + }, + { + "text": "When G {ge} 1 and pmpcfg~i~.A[1] is clear, i.e. the mode is OFF or TOR, then bits pmpaddr~i~[G-1:0] read as all zeros.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Address Matching", + "line_range": [ + 2587, + 2602 + ] + }, + { + "text": "Bits pmpaddr~i~[G-1:0] do not affect the TOR address-matching logic.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Address Matching", + "line_range": [ + 2587, + 2602 + ] + }, + { + "text": "Although changing pmpcfg~i~.A[1] affects the value read from pmpaddr~i~, it does not affect the underlying value stored in that register—in particular, pmpaddr~i~[G-1] retains its original value when pmpcfg~i~.A is changed from NAPOT to TOR/OFF then back to NAPOT.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Address Matching", + "line_range": [ + 2587, + 2602 + ] + }, + { + "text": "The L bit indicates that the PMP entry is locked, i.e., writes to the configuration register and associated address registers are ignored.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Locking and Privilege Mode", + "line_range": [ + 2607, + 2612 + ] + }, + { + "text": "Locked PMP entries remain locked until the hart is reset.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Locking and Privilege Mode", + "line_range": [ + 2607, + 2612 + ] + }, + { + "text": "If PMP entry i is locked, writes to ``pmp``i``cfg`` and ``pmpaddr``i are ignored.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Locking and Privilege Mode", + "line_range": [ + 2607, + 2612 + ] + }, + { + "text": "Additionally, if PMP entry i is locked and ``pmp``i``cfg.A`` is set to TOR, writes to ``pmpaddr``i-1 are ignored.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Locking and Privilege Mode", + "line_range": [ + 2607, + 2612 + ] + }, + { + "text": "In addition to locking the PMP entry, the L bit indicates whether the R/W/X permissions are additionally enforced on M-mode accesses.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Locking and Privilege Mode", + "line_range": [ + 2614, + 2619 + ] + }, + { + "text": "When the L bit is set, these permissions are enforced for all privilege modes.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Locking and Privilege Mode", + "line_range": [ + 2614, + 2619 + ] + }, + { + "text": "When the L bit is clear, any M-mode access matching the PMP entry will succeed; the R/W/X permissions apply only to S and U modes.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Locking and Privilege Mode", + "line_range": [ + 2614, + 2619 + ] + }, + { + "text": "On some implementations, misaligned loads, stores, and instruction fetches may be decomposed into multiple memory operations, some of which may succeed before an access-fault exception occurs, as described in the RVWMO specification. PMP checking is performed on each memory operation independently.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Priority and Matching Logic", + "line_range": [ + 2623, + 2630 + ] + }, + { + "text": "In particular, a portion of a misaligned store that passes the PMP check may become visible, even if another portion fails the PMP check.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Priority and Matching Logic", + "line_range": [ + 2623, + 2630 + ] + }, + { + "text": "The same behavior may manifest for stores wider than XLEN bits (e.g., the FSD instruction in RV32D), even when the store address is naturally aligned.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Priority and Matching Logic", + "line_range": [ + 2623, + 2630 + ] + }, + { + "text": "PMP entries are statically prioritized.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Priority and Matching Logic", + "line_range": [ + 2632, + 2639 + ] + }, + { + "text": "The lowest-numbered PMP entry that matches any byte of a memory operation determines whether that operation succeeds or fails.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Priority and Matching Logic", + "line_range": [ + 2632, + 2639 + ] + }, + { + "text": "The matching PMP entry must match all bytes of a memory operation, or the operation fails, irrespective of the L, R, W, and X bits.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Priority and Matching Logic", + "line_range": [ + 2632, + 2639 + ] + }, + { + "text": "For example, if a PMP entry is configured to match the four-byte range `0xC`–`0xF`, then an 8-byte access to the range `0x8`–`0xF` will fail, assuming that PMP entry is the highest-priority entry that matches those addresses.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Priority and Matching Logic", + "line_range": [ + 2632, + 2639 + ] + }, + { + "text": "If a PMP entry matches all bytes of a memory operation, then the L, R, W, and X bits determine whether the operation succeeds or fails.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Priority and Matching Logic", + "line_range": [ + 2641, + 2646 + ] + }, + { + "text": "If the L bit is clear and the privilege mode of the access is M, the operation succeeds.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Priority and Matching Logic", + "line_range": [ + 2641, + 2646 + ] + }, + { + "text": "Otherwise, if the L bit is set or the privilege mode of the access is S or U, then the operation succeeds only if the R, W, or X bit corresponding to the access type is set.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Priority and Matching Logic", + "line_range": [ + 2641, + 2646 + ] + }, + { + "text": "If no PMP entry matches an M-mode memory operation, the operation succeeds.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Priority and Matching Logic", + "line_range": [ + 2648, + 2650 + ] + }, + { + "text": "If no PMP entry matches an S-mode or U-mode memory operation, but at least one PMP entry is implemented, the operation fails.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Priority and Matching Logic", + "line_range": [ + 2648, + 2650 + ] + }, + { + "text": "Failed memory operations generate an instruction, load, or store access-fault exception.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Priority and Matching Logic", + "line_range": [ + 2652, + 2658 + ] + }, + { + "text": "Note that a single instruction may generate multiple memory operations, which may not be mutually atomic.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Priority and Matching Logic", + "line_range": [ + 2652, + 2658 + ] + }, + { + "text": "An access-fault exception is generated if at least one memory operation generated by an instruction fails, though other memory operations generated by that instruction may succeed with visible side effects.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Priority and Matching Logic", + "line_range": [ + 2652, + 2658 + ] + }, + { + "text": "Notably, instructions that reference virtual memory are decomposed into multiple memory operations.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection CSRs > Priority and Matching Logic", + "line_range": [ + 2652, + 2658 + ] + }, + { + "text": "The Physical Memory Protection mechanism is designed to compose with the page-based virtual memory systems described in .", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection and Paging", + "line_range": [ + 2664, + 2670 + ] + }, + { + "text": "When paging is enabled, instructions that access virtual memory may result in multiple physical-memory accesses, including implicit references to the page tables.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection and Paging", + "line_range": [ + 2664, + 2670 + ] + }, + { + "text": "The PMP checks apply to all of these accesses.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection and Paging", + "line_range": [ + 2664, + 2670 + ] + }, + { + "text": "The effective privilege mode for implicit page-table accesses is S.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection and Paging", + "line_range": [ + 2664, + 2670 + ] + }, + { + "text": "Implementations with virtual memory are permitted to perform address translations speculatively and earlier than required by an explicit memory access, and are permitted to cache them in address translation cache structures—including possibly caching the identity mappings from effective address to physical address used in Bare translation modes and M-mode.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection and Paging", + "line_range": [ + 2672, + 2685 + ] + }, + { + "text": "The PMP settings for the resulting physical address may be checked (and possibly cached) at any point between the address translation and the explicit memory access.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection and Paging", + "line_range": [ + 2672, + 2685 + ] + }, + { + "text": "Hence, when the PMP settings are modified, M-mode software must synchronize the PMP settings with the virtual memory system and any PMP or address-translation caches.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection and Paging", + "line_range": [ + 2672, + 2685 + ] + }, + { + "text": "This is accomplished by executing an SFENCE.VMA instruction with rs1=`x0` and rs2=`x0`, after the PMP CSRs are written.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection and Paging", + "line_range": [ + 2672, + 2685 + ] + }, + { + "text": "See for additional synchronization requirements when the hypervisor extension is implemented.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection and Paging", + "line_range": [ + 2672, + 2685 + ] + }, + { + "text": "If page-based virtual memory is not implemented, memory accesses check the PMP settings synchronously, so no SFENCE.VMA is needed.", + "section": "Preamble > Machine-Level ISA, Version 1.13 > Physical Memory Protection > Physical Memory Protection and Paging", + "line_range": [ + 2687, + 2688 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__priv__preface.json b/tools/llm-extraction/data/output/raw_chunks/src__priv__preface.json new file mode 100644 index 0000000000..3534a817ab --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__priv__preface.json @@ -0,0 +1,606 @@ +{ + "source_file": "src/priv/preface.adoc", + "total": 75, + "sentences": [ + { + "text": "[colophon] // Had to make the above a level 1 heading (two equals signs) to avoid error when building // the ISA manual as a book with other \"parts\".", + "section": "Preamble", + "line_range": [ + 1, + 8 + ] + }, + { + "text": "This is opposite to what the adoc says to do // but otherwise asciidoctor creates the error message: // // asciidoctor: ERROR: ext/riscv-isa-manual/src/priv-preface.adoc: line 2: invalid part, must have at least one section (e.g., chapter, appendix, etc.) // // See asciidoctor doc which seems wrong: https://docs.asciidoctor.org/asciidoc/latest/sections/colophon/", + "section": "Preamble", + "line_range": [ + 1, + 8 + ] + }, + { + "text": "This document describes the RISC-V privileged architecture.", + "section": "Preamble > Preface", + "line_range": [ + 10, + 12 + ] + }, + { + "text": "It contains the following versions of the RISC-V ISA modules, all of which have been ratified:", + "section": "Preamble > Preface", + "line_range": [ + 10, + 12 + ] + }, + { + "text": "| |Privilege Level |Version |*Machine* |*1.13* |*Supervisor* |*1.13*", + "section": "Preamble > Preface", + "line_range": [ + 14, + 18 + ] + }, + { + "text": "|*Smstateen/Ssstateen* |*1.0* |*Smcsrind/Sscsrind* |*1.0* |*Smepmp* |*1.0* |*Smcntrpmf* |*1.0* |*Smrnmi* |*1.0* |*Smcdeleg/Ssccfg* |*1.0* |*Smdbltrp* |*1.0* |*Smctr* |*1.0* |*Control-flow Integrity* |*1.0* |*Pointer Masking* |*1.0*", + "section": "Preamble > Preface", + "line_range": [ + 22, + 31 + ] + }, + { + "text": "|*Svade* |*1.0* |*Svnapot* |*1.0* |*Svpbmt* |*1.0* |*Svadu* |*1.0* |*Svinval* |*1.0* |*Svvptc* |*1.0* |*Svrsw60t59b* |*1.0*", + "section": "Preamble > Preface", + "line_range": [ + 33, + 39 + ] + }, + { + "text": "|*Ssqosid* |*1.0* |*Ssu64xl* |*1.0* |*Ssccptr* |*1.0* |*Sstvecd* |*1.0* |*Sstvala* |*1.0* |*Sscounterenw* |*1.0* |*Ssstrict* |*1.0* |*Sstc* |*1.0* |*Sscofpmf* |*1.0* |*Ssdbltrp* |*1.0*", + "section": "Preamble > Preface", + "line_range": [ + 41, + 50 + ] + }, + { + "text": "|*H* |*1.0* |*Shlcofideleg* |*1.0* |*Shvstvecd* |*1.0* |*Shcounterenw* |*1.0* |*Shvstvala* |*1.0* |*Shtvala* |*1.0* |*Shvsatpa* |*1.0* |*Shgatpa* |*1.0* |*Sha* |*1.0* |", + "section": "Preamble > Preface", + "line_range": [ + 52, + 61 + ] + }, + { + "text": "The following changes have been made since version 20260120:", + "section": "Preamble > Preface", + "line_range": [ + 63, + 63 + ] + }, + { + "text": "Addition of extensions that have already been ratified as part of the profile specifications.", + "section": "Preamble > Preface", + "line_range": [ + 65, + 66 + ] + }, + { + "text": "[.big]*Preface to Version 20260120*", + "section": "Preamble > Preface", + "line_range": [ + 68, + 68 + ] + }, + { + "text": "This document describes the RISC-V privileged architecture.", + "section": "Preamble > Preface", + "line_range": [ + 70, + 72 + ] + }, + { + "text": "It contains the following versions of the RISC-V ISA modules, all of which have been ratified:", + "section": "Preamble > Preface", + "line_range": [ + 70, + 72 + ] + }, + { + "text": "| |Module |Version |*Machine ISA* |*1.13* |*Smstateen Extension* |*1.0* |*Smcsrind/Sscsrind Extension* |*1.0* |*Smepmp Extension* |*1.0* |*Smcntrpmf Extension* |*1.0* |*Smrnmi Extension* |*1.0* |*Smcdeleg Extension* |*1.0* |*Smdbltrp Extension* |*1.0* |*Smctr Extension* |*1.0* |*Supervisor ISA* |*1.13* |*Svade Extension* |*1.0* |*Svnapot Extension* |*1.0* |*Svpbmt Extension* |*1.0* |*Svinval Extension* |*1.0* |*Svadu Extension* |*1.0* |*Svvptc Extension* |*1.0* |*Ssqosid Extension* |*1.0* |*Sstc Extension* |*1.0* |*Sscofpmf Extension* |*1.0* |*Ssdbltrp Extension* |*1.0* |*Hypervisor ISA* |*1.0* |*Shlcofideleg Extension* |*1.0* |*Svvptc Extension* |*1.0* |*Pointer-Masking Extensions* |*1.0* |*Svrsw60t59b Extension* |*1.0* |", + "section": "Preamble > Preface", + "line_range": [ + 74, + 102 + ] + }, + { + "text": "The following changes have been made since version 20250508:", + "section": "Preamble > Preface", + "line_range": [ + 104, + 104 + ] + }, + { + "text": "Addition of the Svrsw60t59b extension for additional PTE reserved-for-software bits.", + "section": "Preamble > Preface", + "line_range": [ + 106, + 106 + ] + }, + { + "text": "[.big]*Preface to Version 20250508*", + "section": "Preamble > Preface", + "line_range": [ + 108, + 108 + ] + }, + { + "text": "This document describes the RISC-V privileged architecture.", + "section": "Preamble > Preface", + "line_range": [ + 110, + 110 + ] + }, + { + "text": "The ISA modules marked *Ratified* have been ratified at this time.", + "section": "Preamble > Preface", + "line_range": [ + 112, + 115 + ] + }, + { + "text": "The modules marked Frozen are not expected to change significantly before being put up for ratification.", + "section": "Preamble > Preface", + "line_range": [ + 112, + 115 + ] + }, + { + "text": "The modules marked Draft are expected to change before ratification.", + "section": "Preamble > Preface", + "line_range": [ + 112, + 115 + ] + }, + { + "text": "The document contains the following versions of the RISC-V ISA modules:", + "section": "Preamble > Preface", + "line_range": [ + 117, + 117 + ] + }, + { + "text": "| |Module |Version |Status |*Machine ISA* |*1.13* |*Ratified* |*Smstateen Extension* |*1.0* |*Ratified* |*Smcsrind/Sscsrind Extension* |*1.0* |*Ratified* |*Smepmp Extension* |*1.0* |*Ratified* |*Smcntrpmf Extension* |*1.0* |*Ratified* |*Smrnmi Extension* |*1.0* |*Ratified* |*Smcdeleg Extension* |*1.0* |*Ratified* |*Smdbltrp Extension* |*1.0* |*Ratified* |*Smctr Extension* |*1.0* |*Ratified* |*Supervisor ISA* |*1.13* |*Ratified* |*Svade Extension* |*1.0* |*Ratified* |*Svnapot Extension* |*1.0* |*Ratified* |*Svpbmt Extension* |*1.0* |*Ratified* |*Svinval Extension* |*1.0* |*Ratified* |*Svadu Extension* |*1.0* |*Ratified* |*Svvptc Extension* |*1.0* |*Ratified* |*Ssqosid Extension* |*1.0* |*Ratified* |*Sstc Extension* |*1.0* |*Ratified* |*Sscofpmf Extension* |*1.0* |*Ratified* |*Ssdbltrp Extension* |*1.0* |*Ratified* |*Hypervisor ISA* |*1.0* |*Ratified* |*Shlcofideleg Extension* |*1.0* |*Ratified* |*Svvptc Extension* |*1.0* |*Ratified* |*Pointer-Masking Extensions* |*1.0* |*Ratified* |", + "section": "Preamble > Preface", + "line_range": [ + 119, + 146 + ] + }, + { + "text": "The following changes have been made since version 20241101:", + "section": "Preamble > Preface", + "line_range": [ + 148, + 148 + ] + }, + { + "text": "Addition of the Smctr Control Transfer Records extension. * Addition of the Svvptc Extension for Obviating Memory-Management Instructions after Marking PTEs Valid. * Addition of the Ssqosid Extension for Quality-of-Service Identifiers. * Addition of the Pointer-Masking Extensions.", + "section": "Preamble > Preface", + "line_range": [ + 150, + 153 + ] + }, + { + "text": "[.big]*Preface to Version 20241101*", + "section": "Preamble > Preface", + "line_range": [ + 155, + 155 + ] + }, + { + "text": "This document describes the RISC-V privileged architecture.", + "section": "Preamble > Preface", + "line_range": [ + 157, + 157 + ] + }, + { + "text": "The ISA modules marked *Ratified* have been ratified at this time.", + "section": "Preamble > Preface", + "line_range": [ + 159, + 162 + ] + }, + { + "text": "The modules marked Frozen are not expected to change significantly before being put up for ratification.", + "section": "Preamble > Preface", + "line_range": [ + 159, + 162 + ] + }, + { + "text": "The modules marked Draft are expected to change before ratification.", + "section": "Preamble > Preface", + "line_range": [ + 159, + 162 + ] + }, + { + "text": "The document contains the following versions of the RISC-V ISA modules:", + "section": "Preamble > Preface", + "line_range": [ + 164, + 164 + ] + }, + { + "text": "| |Module |Version |Status |*Machine ISA* |*1.13* |*Ratified* |*Smstateen Extension* |*1.0* |*Ratified* |*Smcsrind/Sscsrind Extension* |*1.0* |*Ratified* |*Smepmp Extension* |*1.0* |*Ratified* |*Smcntrpmf Extension* |*1.0* |*Ratified* |*Smrnmi Extension* |*1.0* |*Ratified* |*Smcdeleg Extension* |*1.0* |*Ratified* |*Smdbltrp Extension* |*1.0* |*Ratified* |*Supervisor ISA* |*1.13* |*Ratified* |*Svade Extension* |*1.0* |*Ratified* |*Svnapot Extension* |*1.0* |*Ratified* |*Svpbmt Extension* |*1.0* |*Ratified* |*Svinval Extension* |*1.0* |*Ratified* |*Svadu Extension* |*1.0* |*Ratified* |*Sstc Extension* |*1.0* |*Ratified* |*Sscofpmf Extension* |*1.0* |*Ratified* |*Ssdbltrp Extension* |*1.0* |*Ratified* |*Ssqosid Extension* |*1.0* |*Ratified* |*Hypervisor ISA* |*1.0* |*Ratified* |*Shlcofideleg Extension* |*1.0* |*Ratified* |*Svvptc Extension* |*1.0* |*Ratified* |", + "section": "Preamble > Preface", + "line_range": [ + 166, + 190 + ] + }, + { + "text": "[.big]*Preface to Version 20241017*", + "section": "Preamble > Preface", + "line_range": [ + 192, + 192 + ] + }, + { + "text": "This document describes the RISC-V privileged architecture.", + "section": "Preamble > Preface", + "line_range": [ + 194, + 196 + ] + }, + { + "text": "This release, version 20241017, contains the following versions of the RISC-V ISA modules:", + "section": "Preamble > Preface", + "line_range": [ + 194, + 196 + ] + }, + { + "text": "| |Module |Version |Status |*Machine ISA* |*1.13* |*Ratified* |*Smstateen Extension* |*1.0* |*Ratified* |*Smcsrind/Sscsrind Extension* |*1.0* |*Ratified* |*Smepmp* |*1.0* |*Ratified* |*Smcntrpmf* |*1.0* |*Ratified* |*Smrnmi Extension* |*1.0* |*Ratified* |*Smcdeleg* |*1.0* |*Ratified* |*Smdbltrp* |*1.0* |*Ratified* |*Supervisor ISA* |*1.13* |*Ratified* |*Svade Extension* |*1.0* |*Ratified* |*Svnapot Extension* |*1.0* |*Ratified* |*Svpbmt Extension* |*1.0* |*Ratified* |*Svinval Extension* |*1.0* |*Ratified* |*Svadu Extension* |*1.0* |*Ratified* |*Sstc* |*1.0* |*Ratified* |*Sscofpmf* |*1.0* |*Ratified* |*Ssdbltrp* |*1.0* |*Ratified* |*Hypervisor ISA* |*1.0* |*Ratified* |*Shlcofideleg* |*1.0* |*Ratified* |*Svvptc* |*1.0* |*Ratified* |", + "section": "Preamble > Preface", + "line_range": [ + 198, + 221 + ] + }, + { + "text": "The following changes have been made since version 1.12 of the Machine and Supervisor ISAs, which, while not strictly backwards compatible, are not anticipated to cause software portability problems in practice:", + "section": "Preamble > Preface", + "line_range": [ + 223, + 225 + ] + }, + { + "text": "Redefined `misa`.MXL to be read-only, making MXLEN a constant. * Added the constraint that SXLEN{ge}UXLEN.", + "section": "Preamble > Preface", + "line_range": [ + 227, + 228 + ] + }, + { + "text": "Additionally, the following compatible changes have been made to the Machine and Supervisor ISAs since version 1.12:", + "section": "Preamble > Preface", + "line_range": [ + 230, + 231 + ] + }, + { + "text": "Defined the `misa`.B field to reflect that the B extension has been implemented. * Defined the `misa`.V field to reflect that the V extension has been implemented. * Defined the RV32-only `medelegh` and `hedelegh` CSRs. * Defined the misaligned atomicity granule PMA, superseding the proposed Zam extension. * Allocated interrupt 13 for Sscofpmf LCOFI interrupt. * Defined hardware-error and software-check exception codes. * Specified synchronization requirements when changing the PBMTE and ADUE fields in `menvcfg` and `henvcfg`. * Exposed count-overflow interrupts to VS-mode via the Shlcofideleg extension. * Relaxed behavior of some HINTs when MXLEN > XLEN. * Defined the format of the memory-mapped `msip` registers.", + "section": "Preamble > Preface", + "line_range": [ + 233, + 246 + ] + }, + { + "text": "Finally, the following clarifications and document improvements have been made since the last document release:", + "section": "Preamble > Preface", + "line_range": [ + 248, + 249 + ] + }, + { + "text": "Transliterated the document from LaTeX into AsciiDoc. * Included all ratified extensions through March 2024. * Clarified that \"platform- or custom-use\" interrupts are actually \"platform-use interrupts\", where the platform can choose to make some custom. * Clarified semantics of explicit accesses to CSRs wider than XLEN bits. * Clarified that MXLEN{ge}SXLEN. * Clarified that WFI is not a HINT instruction. * Clarified that VS-stage page-table accesses set G-stage A/D bits. * Clarified ordering rules when PBMT=IO is used on main-memory regions. * Clarified ordering rules for hardware A/D bit updates. * Clarified that, for a given exception cause, `xtval` might sometimes be set to a nonzero value but sometimes not. * Clarified exception behavior of unimplemented or inaccessible CSRs. * Clarified that Svpbmt allows implementations to override additional PMAs. * Replaced the concept of vacant memory regions with inaccessible memory or I/O regions. * Clarified that timer and count-overflow interrupts' arrival in interrupt-pending registers is not immediate. * Clarified that MXR affects only explicit memory accesses.", + "section": "Preamble > Preface", + "line_range": [ + 251, + 268 + ] + }, + { + "text": "[.big]*Preface to Version 20211203*", + "section": "Preamble > Preface", + "line_range": [ + 270, + 270 + ] + }, + { + "text": "This document describes the RISC-V privileged architecture.", + "section": "Preamble > Preface", + "line_range": [ + 272, + 274 + ] + }, + { + "text": "This release, version 20211203, contains the following versions of the RISC-V ISA modules:", + "section": "Preamble > Preface", + "line_range": [ + 272, + 274 + ] + }, + { + "text": "| |Module |Version |Status |*Machine ISA* |*1.12* |*Ratified* |*Supervisor ISA* |*1.12* |*Ratified* |*Svnapot Extension* |*1.0* |*Ratified* |*Svpbmt Extension* |*1.0* |*Ratified* |*Svinval Extension* |*1.0* |*Ratified* |*Hypervisor ISA* |*1.0* |*Ratified* |", + "section": "Preamble > Preface", + "line_range": [ + 276, + 285 + ] + }, + { + "text": "The following changes have been made since version 1.11, which, while not strictly backwards compatible, are not anticipated to cause software portability problems in practice:", + "section": "Preamble > Preface", + "line_range": [ + 287, + 289 + ] + }, + { + "text": "Changed MRET and SRET to clear `mstatus`.MPRV when leaving M-mode. * Reserved additional `satp` patterns for future use. * Stated that the `scause` Exception Code field must implement bits 4–0 at minimum. * Relaxed I/O regions have been specified to follow RVWMO.", + "section": "Preamble > Preface", + "line_range": [ + 291, + 305 + ] + }, + { + "text": "The previous specification implied that PPO rules other than fences and acquire/release annotations did not apply. * Constrained the LR/SC reservation set size and shape when using page-based virtual memory. * PMP changes require an SFENCE.VMA on any hart that implements page-based virtual memory, even if VM is not currently enabled. * Allowed for speculative updates of page table entry A bits. * Clarify that if the address-translation algorithm non-speculatively reaches a PTE in which a bit reserved for future standard use is set, a page-fault exception must be raised.", + "section": "Preamble > Preface", + "line_range": [ + 291, + 305 + ] + }, + { + "text": "Additionally, the following compatible changes have been made since version 1.11:", + "section": "Preamble > Preface", + "line_range": [ + 307, + 308 + ] + }, + { + "text": "Removed the N extension. * Defined the mandatory RV32-only CSR `mstatush`, which contains most of the same fields as the upper 32 bits of RV64’s `mstatus`. * Defined the mandatory CSR `mconfigptr`, which if nonzero contains the address of a configuration data structure. * Defined `mseccfg` and `mseccfgh` CSRs, which control the machine’s security configuration. * Defined `menvcfg`, `henvcfg`, and `senvcfg` CSRs (and RV32-only `menvcfgh` and `henvcfgh` CSRs), which control various characteristics of the execution environment. * Designated part of SYSTEM major opcode for custom use. * Permitted the unconditional delegation of less-privileged interrupts. * Added optional big-endian and bi-endian support. * Made priority of load/store/AMO address-misaligned exceptions implementation-defined relative to load/store/AMO page-fault and access-fault exceptions. * PMP reset values are now platform-defined. * An additional 48 optional PMP registers have been defined. * Slightly relaxed the atomicity requirement for A and D bit updates performed by the implementation. * Clarify the architectural behavior of address-translation caches * Added Sv57 and Sv57x4 address translation modes. * Software breakpoint exceptions are permitted to write either 0 or the `pc` to `xtval`. * Clarified that bare S-mode need not support the SFENCE.VMA instruction. * Specified relaxed constraints for implicit reads of non-idempotent regions. * Added the Svnapot Standard Extension, along with the N bit in Sv39, Sv48, and Sv57 PTEs. * Added the Svpbmt Standard Extension, along with the PBMT bits in Sv39, Sv48, and Sv57 PTEs. * Added the Svinval Standard Extension and associated instructions.", + "section": "Preamble > Preface", + "line_range": [ + 310, + 342 + ] + }, + { + "text": "Finally, the hypervisor architecture proposal has been extensively revised.", + "section": "Preamble > Preface", + "line_range": [ + 344, + 345 + ] + }, + { + "text": "[.big]*Preface to Version 1.11*", + "section": "Preamble > Preface", + "line_range": [ + 347, + 347 + ] + }, + { + "text": "This is version 1.11 of the RISC-V privileged architecture.", + "section": "Preamble > Preface", + "line_range": [ + 349, + 350 + ] + }, + { + "text": "The document contains the following versions of the RISC-V ISA modules:", + "section": "Preamble > Preface", + "line_range": [ + 349, + 350 + ] + }, + { + "text": "| |Module |Version |Status |*Machine ISA* |*1.11* |*Ratified* |*Supervisor ISA* |*1.11* |*Ratified* |Hypervisor ISA |0.3 |Draft |", + "section": "Preamble > Preface", + "line_range": [ + 352, + 358 + ] + }, + { + "text": "Changes from version 1.10 include:", + "section": "Preamble > Preface", + "line_range": [ + 360, + 360 + ] + }, + { + "text": "Moved Machine and Supervisor spec to *Ratified* status. * Improvements to the description and commentary. * Added a draft proposal for a hypervisor extension. * Specified which interrupt sources are reserved for standard use. * Allocated some synchronous exception causes for custom use. * Specified the priority ordering of synchronous exceptions. * Added specification that xRET instructions may, but are not required to, clear LR reservations if A extension present. * The virtual-memory system no longer permits supervisor mode to execute instructions from user pages, regardless of the SUM setting. * Clarified that ASIDs are private to a hart, and added commentary about the possibility of a future global-ASID extension. * SFENCE.VMA semantics have been clarified. * Made the `mstatus`.MPP field *WARL*, rather than *WLRL*. * Made the unused `xip` fields *WPRI*, rather than *WIRI*. * Made the unused `misa` fields *WARL*, rather than *WIRI*. * Made the unused `pmpaddr` and `pmpcfg` fields *WARL*, rather than *WIRI*. * Required all harts in a system to employ the same PTE-update scheme as each other. * Rectified an editing error that misdescribed the mechanism by which `mstatus.xIE` is written upon an exception. * Described scheme for emulating misaligned AMOs. * Specified the behavior of the `misa` and `xepc` registers in systems with variable IALIGN. * Specified the behavior of writing self-contradictory values to the `misa` register. * Defined the `mcountinhibit` CSR, which stops performance counters from incrementing to reduce energy consumption. * Specified semantics for PMP regions coarser than four bytes. * Specified contents of CSRs across XLEN modification. * Moved PLIC chapter into its own document.", + "section": "Preamble > Preface", + "line_range": [ + 362, + 392 + ] + }, + { + "text": "[.big]*Preface to Version 1.10*", + "section": "Preamble > Preface", + "line_range": [ + 394, + 394 + ] + }, + { + "text": "This is version 1.10 of the RISC-V privileged architecture proposal.", + "section": "Preamble > Preface", + "line_range": [ + 396, + 397 + ] + }, + { + "text": "Changes from version 1.9.1 include:", + "section": "Preamble > Preface", + "line_range": [ + 396, + 397 + ] + }, + { + "text": "The previous version of this document was released under a Creative Commons Attribution 4.0 International License by the original authors, and this and future versions of this document will be released under the same license. * The explicit convention on shadow CSR addresses has been removed to reclaim CSR space.", + "section": "Preamble > Preface", + "line_range": [ + 399, + 455 + ] + }, + { + "text": "Shadow CSRs can still be added as needed. * The `mvendorid` register now contains the JEDEC code of the core provider as opposed to a code supplied by the Foundation.", + "section": "Preamble > Preface", + "line_range": [ + 399, + 455 + ] + }, + { + "text": "This avoids redundancy and offloads work from the Foundation. * The interrupt-enable stack discipline has been simplified. * An optional mechanism to change the base ISA used by supervisor and user modes has been added to the `mstatus` CSR, and the field previously called Base in `misa` has been renamed to `MXL` for consistency. * Clarified expected use of XS to summarize additional extension state status fields in `mstatus`. * Optional vectored interrupt support has been added to the `mtvec` and `stvec` CSRs. * The SEIP and UEIP bits in the `mip` CSR have been redefined to support software injection of external interrupts. * The `mbadaddr` register has been subsumed by a more general `mtval` register that can now capture bad instruction bits on an illegal-instruction fault to speed instruction emulation. * The machine-mode base-and-bounds translation and protection schemes have been removed from the specification as part of moving the virtual memory configuration to `sptbr` (now `satp`).", + "section": "Preamble > Preface", + "line_range": [ + 399, + 455 + ] + }, + { + "text": "Some of the motivation for the base and bound schemes are now covered by the PMP registers, but space remains available in `mstatus` to add these back at a later date if deemed useful. * In systems with only M-mode, or with both M-mode and U-mode but without U-mode trap support, the `medeleg` and `mideleg` registers now do not exist, whereas previously they returned zero. * Virtual-memory page faults now have `mcause` values distinct from physical-memory access faults.", + "section": "Preamble > Preface", + "line_range": [ + 399, + 455 + ] + }, + { + "text": "Page-fault exceptions can now be delegated to S-mode without delegating exceptions generated by PMA and PMP checks. * An optional physical-memory protection (PMP) scheme has been proposed. * The supervisor virtual memory configuration has been moved from the `mstatus` register to the `sptbr` register.", + "section": "Preamble > Preface", + "line_range": [ + 399, + 455 + ] + }, + { + "text": "Accordingly, the `sptbr` register has been renamed to `satp` (Supervisor Address Translation and Protection) to reflect its broadened role. * The SFENCE.VM instruction has been removed in favor of the improved SFENCE.VMA instruction. * The `mstatus` bit MXR has been exposed to S-mode via `sstatus`. * The polarity of the PUM bit in `sstatus` has been inverted to shorten code sequences involving MXR.", + "section": "Preamble > Preface", + "line_range": [ + 399, + 455 + ] + }, + { + "text": "The bit has been renamed to SUM. * Hardware management of page-table entry Accessed and Dirty bits has been made optional; simpler implementations may trap to software to set them. * The counter-enable scheme has changed, so that S-mode can control availability of counters to U-mode. * H-mode has been removed, as we are focusing on recursive virtualization support in S-mode.", + "section": "Preamble > Preface", + "line_range": [ + 399, + 455 + ] + }, + { + "text": "The encoding space has been reserved and may be repurposed at a later date. * A mechanism to improve virtualization performance by trapping S-mode virtual-memory management operations has been added. * The Supervisor Binary Interface (SBI) chapter has been removed, so that it can be maintained as a separate specification.", + "section": "Preamble > Preface", + "line_range": [ + 399, + 455 + ] + }, + { + "text": "[.big]*Preface to Version 1.9.1*", + "section": "Preamble > Preface", + "line_range": [ + 457, + 457 + ] + }, + { + "text": "This is version 1.9.1 of the RISC-V privileged architecture proposal.", + "section": "Preamble > Preface", + "line_range": [ + 459, + 460 + ] + }, + { + "text": "Changes from version 1.9 include:", + "section": "Preamble > Preface", + "line_range": [ + 459, + 460 + ] + }, + { + "text": "Numerous additions and improvements to the commentary sections. * Change configuration string proposal to be use a search process that supports various formats including Device Tree String and flattened Device Tree. * Made `misa` optionally writable to support modifying base and supported ISA extensions. CSR address of `misa` changed. * Added description of debug mode and debug CSRs. * Added a hardware performance monitoring scheme.", + "section": "Preamble > Preface", + "line_range": [ + 462, + 472 + ] + }, + { + "text": "Simplified the handling of existing hardware counters, removing privileged versions of the counters and the corresponding delta registers. * Fixed description of SPIE in presence of user-level interrupts.", + "section": "Preamble > Preface", + "line_range": [ + 462, + 472 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__priv__priv.json b/tools/llm-extraction/data/output/raw_chunks/src__priv__priv.json new file mode 100644 index 0000000000..4e8f115443 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__priv__priv.json @@ -0,0 +1,5 @@ +{ + "source_file": "src/priv/priv.adoc", + "total": 0, + "sentences": [] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__priv__rationale.json b/tools/llm-extraction/data/output/raw_chunks/src__priv__rationale.json new file mode 100644 index 0000000000..57984843f3 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__priv__rationale.json @@ -0,0 +1,286 @@ +{ + "source_file": "src/priv/rationale.adoc", + "total": 35, + "sentences": [ + { + "text": "This appendix contains the rationale for RISC-V ISA extensions at the time they were ratified.", + "section": "Preamble > Historical Rationale for Extensions", + "line_range": [ + 4, + 12 + ] + }, + { + "text": "Unlike the ISA specification, this appendix is ordered chronologically, so as to convey the motivation and architectural reasoning underpinning each extension at the time of ratification.", + "section": "Preamble > Historical Rationale for Extensions", + "line_range": [ + 4, + 12 + ] + }, + { + "text": "For extensions ratified prior to the conception of this appendix (ca. 2025), the rationale will be added over time.", + "section": "Preamble > Historical Rationale for Extensions", + "line_range": [ + 4, + 12 + ] + }, + { + "text": "In cases where the rationale was not recorded, the authors and editors will synthesize it from the historical record.", + "section": "Preamble > Historical Rationale for Extensions", + "line_range": [ + 4, + 12 + ] + }, + { + "text": "Since a CSR for security and / or global PMP behavior settings is not available with the current spec, we needed to define a new `mseccfg` CSR.", + "section": "Preamble > Historical Rationale for Extensions > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode", + "line_range": [ + 17, + 17 + ] + }, + { + "text": "This new CSR will allow us to add further security configuration options in the future and also allow developers to verify the existence of the new mechanisms defined on this extension.", + "section": "Preamble > Historical Rationale for Extensions > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode", + "line_range": [ + 17, + 17 + ] + }, + { + "text": "There are use cases where developers want to enforce PMP rules in M-mode during the boot process, that are also able to modify, merge, and / or remove later on.", + "section": "Preamble > Historical Rationale for Extensions > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode", + "line_range": [ + 19, + 32 + ] + }, + { + "text": "Since a rule that is enforced in M-mode also needs to be locked (or else badly written or malicious M-mode software can remove it at any time), the only way for developers to approach this is to keep adding PMP rules to the chain and rely on rule priority.", + "section": "Preamble > Historical Rationale for Extensions > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode", + "line_range": [ + 19, + 32 + ] + }, + { + "text": "This is a waste of PMP rules and since it’s only needed during boot, ``mseccfg.RLB`` is a simple workaround that can be used temporarily and then disabled and locked down. + Also when ``mseccfg.MML`` is set, according to 4b it’s not possible to add a Shared-Region rule with executable privileges.", + "section": "Preamble > Historical Rationale for Extensions > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode", + "line_range": [ + 19, + 32 + ] + }, + { + "text": "So RLB can be set temporarily during the boot process to register such regions.", + "section": "Preamble > Historical Rationale for Extensions > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode", + "line_range": [ + 19, + 32 + ] + }, + { + "text": "Note that it’s still possible to register executable Shared-Region rules using initial register settings (that may include ``mseccfg.MML`` being set and the rule being set on PMP registers) on *PMP reset*, without using RLB. + [WARNING] *Be aware that RLB introduces a security vulnerability if left set after the boot process is over and in general it should be used with caution, even when used temporarily.* Having editable PMP rules in M-mode gives a false sense of security since it only takes a few malicious instructions to lift any PMP restrictions this way.", + "section": "Preamble > Historical Rationale for Extensions > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode", + "line_range": [ + 19, + 32 + ] + }, + { + "text": "It doesn’t make sense to have a security control in place and leave it unprotected.", + "section": "Preamble > Historical Rationale for Extensions > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode", + "line_range": [ + 19, + 32 + ] + }, + { + "text": "Rule Locking Bypass is only meant as a way to optimize the allocation of PMP rules, catch errors during debugging, and allow the bootrom/firmware to register executable Shared-Region rules.", + "section": "Preamble > Historical Rationale for Extensions > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode", + "line_range": [ + 19, + 32 + ] + }, + { + "text": "If developers / vendors have no use for such functionality, they should never set ``mseccfg.RLB`` and if possible hard-wire it to 0.", + "section": "Preamble > Historical Rationale for Extensions > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode", + "line_range": [ + 19, + 32 + ] + }, + { + "text": "In any case *RLB should be disabled and locked as soon as possible*. + + [IMPORTANT] Since PMP rules with a higher priority override rules with a lower priority, locked rules must precede non-locked rules.", + "section": "Preamble > Historical Rationale for Extensions > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode", + "line_range": [ + 19, + 32 + ] + }, + { + "text": "With the current spec M-mode can access any memory region unless restricted by a PMP rule with the ``pmpcfg.L`` bit set.", + "section": "Preamble > Historical Rationale for Extensions > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode", + "line_range": [ + 34, + 34 + ] + }, + { + "text": "There are cases where this approach is overly permissive, and although it’s possible to restrict M-mode by adding PMP rules during the boot process, this can also be seen as a waste of PMP rules.", + "section": "Preamble > Historical Rationale for Extensions > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode", + "line_range": [ + 34, + 34 + ] + }, + { + "text": "Having the option to block anything by default, and use PMP as an allowlist for M-mode is considered a safer approach.", + "section": "Preamble > Historical Rationale for Extensions > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode", + "line_range": [ + 34, + 34 + ] + }, + { + "text": "This functionality may be used during the boot process or upon *PMP reset*, using initial register settings. +", + "section": "Preamble > Historical Rationale for Extensions > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode", + "line_range": [ + 34, + 34 + ] + }, + { + "text": "The current dual meaning of the ``pmpcfg.L`` bit that marks a rule as Locked and *enforced* on all modes is neither flexible nor clean.", + "section": "Preamble > Historical Rationale for Extensions > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode", + "line_range": [ + 36, + 36 + ] + }, + { + "text": "With the introduction of Machine Mode Lock-down the ``pmpcfg.L`` bit distinguishes between rules that are *enforced* *only* in M-mode (M-mode-only) or *only* in S/U-modes (S/U-mode-only).", + "section": "Preamble > Historical Rationale for Extensions > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode", + "line_range": [ + 36, + 36 + ] + }, + { + "text": "The rule locking becomes part of the definition of an M-mode-only rule, since when a rule is added in M mode, if not locked, can be modified or removed in a few instructions.", + "section": "Preamble > Historical Rationale for Extensions > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode", + "line_range": [ + 36, + 36 + ] + }, + { + "text": "On the other hand, S/U modes can’t modify PMP rules anyway so locking them doesn’t make sense.", + "section": "Preamble > Historical Rationale for Extensions > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode", + "line_range": [ + 36, + 36 + ] + }, + { + "text": "This separation between M-mode-only and S/U-mode-only rules also allows us to distinguish which regions are to be used by processes in Machine mode (``pmpcfg.L 1``) and which by Supervisor or User mode processes (``pmpcfg.L 0``), in the same way the U bit on the Virtual Memory’s PTEs marks which Virtual Memory pages are to be used by User mode applications (U=1) and which by the Supervisor / OS (U=0).", + "section": "Preamble > Historical Rationale for Extensions > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode", + "line_range": [ + 38, + 42 + ] + }, + { + "text": "With this distinction in place we are able to implement memory access and execution prevention in M-mode for any physical memory region that is not M-mode-only. + An attacker that manages to tamper with a memory region used by S/U mode, even after successfully tricking a process running in M-mode to use or execute that region, will fail to perform a successful attack since that region will be S/U-mode-only hence any access when in M-mode will trigger an access exception. + +", + "section": "Preamble > Historical Rationale for Extensions > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode", + "line_range": [ + 38, + 42 + ] + }, + { + "text": "+ Shared-region rules can be used both for zero-copy data transfers and for sharing code segments.", + "section": "Preamble > Historical Rationale for Extensions > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode", + "line_range": [ + 44, + 51 + ] + }, + { + "text": "The latter may be used for example to allow S/U-mode to execute code by the vendor, that makes use of some vendor-specific ISA extension, without having to go through the firmware with an ecall.", + "section": "Preamble > Historical Rationale for Extensions > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode", + "line_range": [ + 44, + 51 + ] + }, + { + "text": "This is similar to the vDSO approach followed on Linux, that allows user space code to execute kernel code without having to perform a system call. + To make sure that shared data regions can’t be executed and shared code regions can’t be modified, the encoding changes the meaning of the ``pmpcfg.X bit``.", + "section": "Preamble > Historical Rationale for Extensions > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode", + "line_range": [ + 44, + 51 + ] + }, + { + "text": "In case of shared data regions, with the exception of the ``pmpcfg.LRWX=1111`` encoding, the ``pmpcfg.X`` bit marks the capability of S/U-mode to write to that region, so it’s not possible to encode an executable shared data region.", + "section": "Preamble > Historical Rationale for Extensions > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode", + "line_range": [ + 44, + 51 + ] + }, + { + "text": "In case of shared code regions, the ``pmpcfg.X`` bit marks the capability of M-mode to read from that region, and since ``pmpcfg.RW=01`` is used for encoding the shared region, it’s not possible to encode a shared writable code region. + + + ..", + "section": "Preamble > Historical Rationale for Extensions > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode", + "line_range": [ + 44, + 51 + ] + }, + { + "text": "The idea with this restriction is that after the Firmware or the OS running in M-mode is initialized and ``mseccfg.MML`` is set, no new code regions are expected to be added since nothing else is expected to run in M-mode (everything else will run in S/U mode).", + "section": "Preamble > Historical Rationale for Extensions > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode", + "line_range": [ + 44, + 51 + ] + }, + { + "text": "Since we want to limit the attack surface of the system as much as possible, it makes sense to disallow any new code regions which may include malicious code, to be added/executed in M-mode.", + "section": "Preamble > Historical Rationale for Extensions > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode", + "line_range": [ + 44, + 51 + ] + }, + { + "text": "In case ``mseccfg.MMWP`` is not set, M-mode can still access and execute any region not covered by a PMP rule.", + "section": "Preamble > Historical Rationale for Extensions > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode", + "line_range": [ + 53, + 53 + ] + }, + { + "text": "Since we try to prevent M-mode from executing malicious code and since an attacker may manage to place code on some region not covered by PMP (e.g. a directly-addressable flash memory), we need to ensure that M-mode can only execute the code segments initialized during firmware / OS initialization.", + "section": "Preamble > Historical Rationale for Extensions > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode", + "line_range": [ + 53, + 53 + ] + }, + { + "text": "We are only using the encoding ``pmpcfg.RW=01`` together with ``mseccfg.MML``, if ``mseccfg.MML`` is not set the encoding remains usable for future use.", + "section": "Preamble > Historical Rationale for Extensions > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode", + "line_range": [ + 55, + 55 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__priv__sh.json b/tools/llm-extraction/data/output/raw_chunks/src__priv__sh.json new file mode 100644 index 0000000000..1bb3590af3 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__priv__sh.json @@ -0,0 +1,22 @@ +{ + "source_file": "src/priv/sh.adoc", + "total": 2, + "sentences": [ + { + "text": "NOTE: This chapter is currently being restructured.", + "section": "Preamble > \"Sh\" Hypervisor Extensions", + "line_range": [ + 3, + 4 + ] + }, + { + "text": "Its contents are normative, but the presentation might appear disjoint.", + "section": "Preamble > \"Sh\" Hypervisor Extensions", + "line_range": [ + 3, + 4 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__priv__sha.json b/tools/llm-extraction/data/output/raw_chunks/src__priv__sha.json new file mode 100644 index 0000000000..a9f807fd0d --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__priv__sha.json @@ -0,0 +1,22 @@ +{ + "source_file": "src/priv/sha.adoc", + "total": 2, + "sentences": [ + { + "text": "The Augmented Hypervisor Extension, Sha, adds several minor features to the hypervisor extension.", + "section": "Preamble > Sha Augmented Hypervisor Extension", + "line_range": [ + 3, + 4 + ] + }, + { + "text": "It depends on the following extensions:", + "section": "Preamble > Sha Augmented Hypervisor Extension", + "line_range": [ + 3, + 4 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__priv__shcounterenw.json b/tools/llm-extraction/data/output/raw_chunks/src__priv__shcounterenw.json new file mode 100644 index 0000000000..da83d27f53 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__priv__shcounterenw.json @@ -0,0 +1,14 @@ +{ + "source_file": "src/priv/shcounterenw.adoc", + "total": 1, + "sentences": [ + { + "text": "If the Shcounterenw extension is implemented, then for any `hpmcounter` that is not read-only zero, the corresponding bit in `hcounteren` must be writable.", + "section": "Preamble > Shcounterenw Extension for Counter-Enable Writability, Version 1.0", + "line_range": [ + 3, + 4 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__priv__shgatpa.json b/tools/llm-extraction/data/output/raw_chunks/src__priv__shgatpa.json new file mode 100644 index 0000000000..289e045b87 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__priv__shgatpa.json @@ -0,0 +1,22 @@ +{ + "source_file": "src/priv/shgatpa.adoc", + "total": 2, + "sentences": [ + { + "text": "If the Shgatpa extension is implemented, then for each supported virtual memory scheme SvNN supported in `satp`, the corresponding hgatp SvNNx4 mode must be supported.", + "section": "Preamble > Shgatpa Extension for Translation Mode Support, Version 1.0", + "line_range": [ + 3, + 6 + ] + }, + { + "text": "Furthermore, the `hgatp` mode Bare must also be supported.", + "section": "Preamble > Shgatpa Extension for Translation Mode Support, Version 1.0", + "line_range": [ + 3, + 6 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__priv__shtvala.json b/tools/llm-extraction/data/output/raw_chunks/src__priv__shtvala.json new file mode 100644 index 0000000000..e1cf476db9 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__priv__shtvala.json @@ -0,0 +1,14 @@ +{ + "source_file": "src/priv/shtvala.adoc", + "total": 1, + "sentences": [ + { + "text": "If the Shtvala extension is implemented, `htval` must be written with the faulting guest physical address in all circumstances permitted by the ISA.", + "section": "Preamble > Shtvala Extension for Trap Value Reporting, Version 1.0", + "line_range": [ + 3, + 4 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__priv__shvsatpa.json b/tools/llm-extraction/data/output/raw_chunks/src__priv__shvsatpa.json new file mode 100644 index 0000000000..aa93b81f3d --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__priv__shvsatpa.json @@ -0,0 +1,14 @@ +{ + "source_file": "src/priv/shvsatpa.adoc", + "total": 1, + "sentences": [ + { + "text": "If the Shvsatpa extension is implemented, all translation modes supported in `satp` must be supported in `vsatp`.", + "section": "Preamble > Shvsatpa Extension for Translation Mode Support, Version 1.0", + "line_range": [ + 3, + 4 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__priv__shvstvala.json b/tools/llm-extraction/data/output/raw_chunks/src__priv__shvstvala.json new file mode 100644 index 0000000000..66c5321070 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__priv__shvstvala.json @@ -0,0 +1,14 @@ +{ + "source_file": "src/priv/shvstvala.adoc", + "total": 1, + "sentences": [ + { + "text": "If the Shvstvala extension is implemented, `vstval` must be written in all cases described in for `stval`.", + "section": "Preamble > Shvstvala Extension for Trap Value Reporting, Version 1.0", + "line_range": [ + 3, + 4 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__priv__shvstvecd.json b/tools/llm-extraction/data/output/raw_chunks/src__priv__shvstvecd.json new file mode 100644 index 0000000000..a443518874 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__priv__shvstvecd.json @@ -0,0 +1,22 @@ +{ + "source_file": "src/priv/shvstvecd.adoc", + "total": 2, + "sentences": [ + { + "text": "If the Shvstvecd extension is implemented, then `vstvec.MODE` must be capable of holding the value 0 (Direct).", + "section": "Preamble > Shvstvecd Extension for Direct Trap Vectoring, Version 1.0", + "line_range": [ + 3, + 6 + ] + }, + { + "text": "Furthermore, when `vstvec.MODE`=Direct, `vstvec.BASE` must be capable of holding any valid four-byte-aligned address.", + "section": "Preamble > Shvstvecd Extension for Direct Trap Vectoring, Version 1.0", + "line_range": [ + 3, + 6 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__priv__sm.json b/tools/llm-extraction/data/output/raw_chunks/src__priv__sm.json new file mode 100644 index 0000000000..beec55b5ad --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__priv__sm.json @@ -0,0 +1,22 @@ +{ + "source_file": "src/priv/sm.adoc", + "total": 2, + "sentences": [ + { + "text": "NOTE: This chapter is currently being restructured.", + "section": "Preamble > \"Sm\" Machine Extensions", + "line_range": [ + 3, + 4 + ] + }, + { + "text": "Its contents are normative, but the presentation might appear disjoint.", + "section": "Preamble > \"Sm\" Machine Extensions", + "line_range": [ + 3, + 4 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__priv__smcdeleg.json b/tools/llm-extraction/data/output/raw_chunks/src__priv__smcdeleg.json new file mode 100644 index 0000000000..b914b9d9b8 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__priv__smcdeleg.json @@ -0,0 +1,318 @@ +{ + "source_file": "src/priv/smcdeleg.adoc", + "total": 39, + "sentences": [ + { + "text": "In modern “Rich OS” environments, hardware performance monitoring resources are managed by the kernel, kernel driver, and/or hypervisor.", + "section": "Preamble > \"Smcdeleg/Ssccfg\" Counter Delegation Extensions, Version 1.0", + "line_range": [ + 3, + 9 + ] + }, + { + "text": "Counters may be configured with differing scopes, in some cases counting events system-wide, while in others counting events on behalf of a single virtual machine or application.", + "section": "Preamble > \"Smcdeleg/Ssccfg\" Counter Delegation Extensions, Version 1.0", + "line_range": [ + 3, + 9 + ] + }, + { + "text": "In such environments, the latency of counter writes has a direct impact on overall profiling overhead as a result of frequent counter writes during:", + "section": "Preamble > \"Smcdeleg/Ssccfg\" Counter Delegation Extensions, Version 1.0", + "line_range": [ + 3, + 9 + ] + }, + { + "text": "Sample collection, to clear overflow indication, and reload overflowed counter(s) .", + "section": "Preamble > \"Smcdeleg/Ssccfg\" Counter Delegation Extensions, Version 1.0", + "line_range": [ + 11, + 14 + ] + }, + { + "text": "Context switch, between processes, threads, containers, or virtual machines", + "section": "Preamble > \"Smcdeleg/Ssccfg\" Counter Delegation Extensions, Version 1.0", + "line_range": [ + 11, + 14 + ] + }, + { + "text": "These extensions provide a means for M-mode to allow writing select counters and event selectors from S/HS-mode.", + "section": "Preamble > \"Smcdeleg/Ssccfg\" Counter Delegation Extensions, Version 1.0", + "line_range": [ + 16, + 20 + ] + }, + { + "text": "The purpose is to avert transitions to and from M-mode that add latency to these performance critical supervisor/hypervisor code sections.", + "section": "Preamble > \"Smcdeleg/Ssccfg\" Counter Delegation Extensions, Version 1.0", + "line_range": [ + 16, + 20 + ] + }, + { + "text": "These extensions also defines one new CSR, scountinhibit.", + "section": "Preamble > \"Smcdeleg/Ssccfg\" Counter Delegation Extensions, Version 1.0", + "line_range": [ + 16, + 20 + ] + }, + { + "text": "For a Machine-level environment, extension *Smcdeleg* (‘Sm’ for Privileged architecture and Machine-level extension, ‘cdeleg’ for Counter Delegation) encompasses all added CSRs and all behavior modifications for a hart, over all privilege levels.", + "section": "Preamble > \"Smcdeleg/Ssccfg\" Counter Delegation Extensions, Version 1.0", + "line_range": [ + 22, + 29 + ] + }, + { + "text": "For a Supervisor-level environment, extension *Ssccfg* (‘Ss’ for Privileged architecture and Supervisor-level extension, ‘ccfg’ for Counter Configuration) provides access to delegated counters, and to new supervisor-level state.For a RISC-V hardware platform, Smcdeleg and Ssccfg must always be implemented in tandem.", + "section": "Preamble > \"Smcdeleg/Ssccfg\" Counter Delegation Extensions, Version 1.0", + "line_range": [ + 22, + 29 + ] + }, + { + "text": "The Smcdeleg and Ssccfg extensions both depend on the Sscsrind extension.", + "section": "Preamble > \"Smcdeleg/Ssccfg\" Counter Delegation Extensions, Version 1.0", + "line_range": [ + 31, + 31 + ] + }, + { + "text": "The `mcounteren` register allows M-mode to provide the next-lower privilege mode with read access to select counters.", + "section": "Preamble > \"Smcdeleg/Ssccfg\" Counter Delegation Extensions, Version 1.0 > Counter Delegation", + "line_range": [ + 35, + 36 + ] + }, + { + "text": "When the Smcdeleg/Ssccfg extensions are enabled (`menvcfg`.CDE=1), it further allows M-mode to delegate select counters to S-mode.", + "section": "Preamble > \"Smcdeleg/Ssccfg\" Counter Delegation Extensions, Version 1.0 > Counter Delegation", + "line_range": [ + 35, + 36 + ] + }, + { + "text": "The `siselect` (and `vsiselect`) index range 0x40-0x5F is reserved for delegated counter access.", + "section": "Preamble > \"Smcdeleg/Ssccfg\" Counter Delegation Extensions, Version 1.0 > Counter Delegation", + "line_range": [ + 38, + 43 + ] + }, + { + "text": "When a counter i is delegated (`mcounteren`[i]=1 and `menvcfg`.CDE=1), the register state associated with counter i can be read or written via `sireg*`, while `siselect` holds 0x40+i.", + "section": "Preamble > \"Smcdeleg/Ssccfg\" Counter Delegation Extensions, Version 1.0 > Counter Delegation", + "line_range": [ + 38, + 43 + ] + }, + { + "text": "The counter state accessible via alias CSRs is shown in the table below.", + "section": "Preamble > \"Smcdeleg/Ssccfg\" Counter Delegation Extensions, Version 1.0 > Counter Delegation", + "line_range": [ + 38, + 43 + ] + }, + { + "text": ".Indirect HPM State Mappings [indirect-hpm-state-mappings] [width=\"100%\",cols=\"21%,20%,21%,18%,20%\",options=\"header\",] | |*`siselect` value* |*`sireg*` |*`sireg4`* |*`sireg2`* |*`sireg5`* |0x40 |`cycle`^1^ |`cycleh`^1^ |`cyclecfg`^14^ |`cyclecfgh`^14^ |0x41 4+^|See below |0x42 |`instret`^1^ |`instreth`^1^ |`instretcfg`^14^ |`instretcfgh`^14^ |0x43 |`hpmcounter3`^2^ |`hpmcounter3h`^2^ |`hpmevent3`^2^ |`hpmevent3h`^23^ |… |… |… |… |… |0x5F |`hpmcounter31`^2^ |`hpmcounter31h`^2^ |`hpmevent31`^2^ |`hpmevent31h`^23^ |", + "section": "Preamble > \"Smcdeleg/Ssccfg\" Counter Delegation Extensions, Version 1.0 > Counter Delegation", + "line_range": [ + 45, + 56 + ] + }, + { + "text": "^1^ Depends on Zicntr support + ^2^ Depends on Zihpm support + ^3^ Depends on Sscofpmf support + ^4^ Depends on Smcntrpmf support", + "section": "Preamble > \"Smcdeleg/Ssccfg\" Counter Delegation Extensions, Version 1.0 > Counter Delegation", + "line_range": [ + 58, + 61 + ] + }, + { + "text": "`hpmeventi` may represent a subset of the state accessed by the `mhpmeventi` register.", + "section": "Preamble > \"Smcdeleg/Ssccfg\" Counter Delegation Extensions, Version 1.0 > Counter Delegation", + "line_range": [ + 63, + 64 + ] + }, + { + "text": "Specifically, if Sscofpmf is implemented, event selector bit 62 (MINH) is read-only 0 when accessed through `sireg*`.", + "section": "Preamble > \"Smcdeleg/Ssccfg\" Counter Delegation Extensions, Version 1.0 > Counter Delegation", + "line_range": [ + 63, + 64 + ] + }, + { + "text": "Likewise, `cyclecfg` and `instretcfg` may represent a subset of the state accessed by the `mcyclecfg` and `minstretcfg` registers, respectively.", + "section": "Preamble > \"Smcdeleg/Ssccfg\" Counter Delegation Extensions, Version 1.0 > Counter Delegation", + "line_range": [ + 66, + 67 + ] + }, + { + "text": "If Smcntrpmf is implemented, counter configuration register bit 62 (MINH) is read-only 0 when accessed through `sireg*`.", + "section": "Preamble > \"Smcdeleg/Ssccfg\" Counter Delegation Extensions, Version 1.0 > Counter Delegation", + "line_range": [ + 66, + 67 + ] + }, + { + "text": "If extension Smstateen is implemented, refer to extensions Smcsrind/Sscsrind () for how setting bit 60 of CSR `mstateen0` to zero prevents access to registers `siselect`, `sireg*`, `vsiselect`, and `vsireg*` from privileged modes less privileged than M-mode, and likewise how setting bit 60 of `hstateen0` to zero prevents access to `siselect` and `sireg*` (really `vsiselect` and `vsireg*`) from VS-mode.", + "section": "Preamble > \"Smcdeleg/Ssccfg\" Counter Delegation Extensions, Version 1.0 > Counter Delegation", + "line_range": [ + 69, + 74 + ] + }, + { + "text": "The remaining rules of this section apply only when access to a CSR is not blocked by `mstateen0`[60] = 0 or `hstateen0`[60] = 0.", + "section": "Preamble > \"Smcdeleg/Ssccfg\" Counter Delegation Extensions, Version 1.0 > Counter Delegation", + "line_range": [ + 76, + 77 + ] + }, + { + "text": "While the privilege mode is M or S and `siselect` holds a value in the range 0x40-0x5F, illegal-instruction exceptions are raised for the following cases:", + "section": "Preamble > \"Smcdeleg/Ssccfg\" Counter Delegation Extensions, Version 1.0 > Counter Delegation", + "line_range": [ + 79, + 81 + ] + }, + { + "text": "attempts to access any `sireg*` when `menvcfg`.CDE = 0; * attempts to access `sireg3` or `sireg6`; * attempts to access `sireg4` or `sireg5` when XLEN = 64; * attempts to access `sireg*` when `siselect` = 0x41, or when the counter selected by `siselect` is not delegated to S-mode (the corresponding bit in `mcounteren` = 0).", + "section": "Preamble > \"Smcdeleg/Ssccfg\" Counter Delegation Extensions, Version 1.0 > Counter Delegation", + "line_range": [ + 83, + 88 + ] + }, + { + "text": "NOTE: The memory-mapped `mtime` register is not a performance monitoring counter to be managed by supervisor software, hence the special treatment of `siselect` value 0x41 described above.", + "section": "Preamble > \"Smcdeleg/Ssccfg\" Counter Delegation Extensions, Version 1.0 > Counter Delegation", + "line_range": [ + 90, + 92 + ] + }, + { + "text": "For each `siselect` and `sireg*` combination defined in , the table further indicates the extensions upon which the underlying counter state depends.", + "section": "Preamble > \"Smcdeleg/Ssccfg\" Counter Delegation Extensions, Version 1.0 > Counter Delegation", + "line_range": [ + 94, + 96 + ] + }, + { + "text": "If any extension upon which the underlying state depends is not implemented, an attempt from M or S mode to access the given state through `sireg*` raises an illegal-instruction exception.", + "section": "Preamble > \"Smcdeleg/Ssccfg\" Counter Delegation Extensions, Version 1.0 > Counter Delegation", + "line_range": [ + 94, + 96 + ] + }, + { + "text": "If the hypervisor (H) extension is also implemented, then as specified by extensions Smcsrind/Sscsrind, a virtual-instruction exception is raised for attempts from VS-mode or VU-mode to directly access `vsiselect` or `vsireg*`, or attempts from VU-mode to access `siselect` or `sireg*`.", + "section": "Preamble > \"Smcdeleg/Ssccfg\" Counter Delegation Extensions, Version 1.0 > Counter Delegation", + "line_range": [ + 98, + 102 + ] + }, + { + "text": "Furthermore, while `vsiselect` holds a value in the range 0x40-0x5F:", + "section": "Preamble > \"Smcdeleg/Ssccfg\" Counter Delegation Extensions, Version 1.0 > Counter Delegation", + "line_range": [ + 98, + 102 + ] + }, + { + "text": "An attempt to access any `vsireg*` from M or S mode raises an illegal-instruction exception. * An attempt from VS-mode to access any `sireg*` (really `vsireg*`) raises an illegal-instruction exception if `menvcfg`.CDE = 0, or a virtual-instruction exception if `menvcfg`.CDE = 1.", + "section": "Preamble > \"Smcdeleg/Ssccfg\" Counter Delegation Extensions, Version 1.0 > Counter Delegation", + "line_range": [ + 104, + 105 + ] + }, + { + "text": "Smcdeleg/Ssccfg defines a new `scountinhibit` register, a masked alias of `mcountinhibit`.", + "section": "Preamble > \"Smcdeleg/Ssccfg\" Counter Delegation Extensions, Version 1.0 > Counter Delegation > Supervisor Counter Inhibit (`scountinhibit`) Register", + "line_range": [ + 109, + 109 + ] + }, + { + "text": "For counters delegated to S-mode, the associated `mcountinhibit` bits can be accessed via `scountinhibit`.For counters not delegated to S-mode, the associated bits in `scountinhibit` are read-only zero.", + "section": "Preamble > \"Smcdeleg/Ssccfg\" Counter Delegation Extensions, Version 1.0 > Counter Delegation > Supervisor Counter Inhibit (`scountinhibit`) Register", + "line_range": [ + 109, + 109 + ] + }, + { + "text": "When `menvcfg`.CDE=0, attempts to access `scountinhibit` raise an illegal-instruction exception.", + "section": "Preamble > \"Smcdeleg/Ssccfg\" Counter Delegation Extensions, Version 1.0 > Counter Delegation > Supervisor Counter Inhibit (`scountinhibit`) Register", + "line_range": [ + 111, + 113 + ] + }, + { + "text": "When Supervisor Counter Delegation is enabled, attempts to access `scountinhibit` from VS-mode or VU-mode raise a virtual-instruction exception.", + "section": "Preamble > \"Smcdeleg/Ssccfg\" Counter Delegation Extensions, Version 1.0 > Counter Delegation > Supervisor Counter Inhibit (`scountinhibit`) Register", + "line_range": [ + 111, + 113 + ] + }, + { + "text": "For implementations that support Smcdeleg/Ssccfg, Sscofpmf, and the H extension, when `menvcfg`.CDE=1, attempts to read `scountovf` from VS-mode or VU-mode raise a virtual-instruction exception.", + "section": "Preamble > \"Smcdeleg/Ssccfg\" Counter Delegation Extensions, Version 1.0 > Counter Delegation > Virtualizing `scountovf`", + "line_range": [ + 118, + 121 + ] + }, + { + "text": "For implementations that support Smcdeleg, Sscofpmf, and Smaia, the local-counter-overflow interrupt (LCOFI) bit (bit 13) in each of CSRs `mvip` and `mvien` is implemented and writable.", + "section": "Preamble > \"Smcdeleg/Ssccfg\" Counter Delegation Extensions, Version 1.0 > Counter Delegation > Virtualizing Local-Counter-Overflow Interrupts", + "line_range": [ + 125, + 128 + ] + }, + { + "text": "For implementations that support Smcdeleg/Ssccfg, Sscofpmf, Smaia/Ssaia, and the H extension, the LCOFI bit (bit 13) in each of `hvip` and `hvien` is implemented and writable.", + "section": "Preamble > \"Smcdeleg/Ssccfg\" Counter Delegation Extensions, Version 1.0 > Counter Delegation > Virtualizing Local-Counter-Overflow Interrupts", + "line_range": [ + 130, + 133 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__priv__smcntrpmf.json b/tools/llm-extraction/data/output/raw_chunks/src__priv__smcntrpmf.json new file mode 100644 index 0000000000..44f67d3450 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__priv__smcntrpmf.json @@ -0,0 +1,198 @@ +{ + "source_file": "src/priv/smcntrpmf.adoc", + "total": 24, + "sentences": [ + { + "text": "The cycle and instret counters serve to support user mode self-profiling usages, wherein a user can read the counter(s) twice and compute the delta(s) to evaluate user software performance and behavior.", + "section": "Preamble > \"Smcntrpmf\" Cycle and Instret Privilege Mode Filtering, Version 1.0 > Introduction", + "line_range": [ + 6, + 6 + ] + }, + { + "text": "By default, these counters are not filtered by privilege mode, and thus they continue to increment while traps (e.g., page faults or interrupts) to more privileged code are handled.", + "section": "Preamble > \"Smcntrpmf\" Cycle and Instret Privilege Mode Filtering, Version 1.0 > Introduction", + "line_range": [ + 6, + 6 + ] + }, + { + "text": "It introduces unpredictable noise to the counter values observed by the user. * It leaks information about privileged software execution to user mode.", + "section": "Preamble > \"Smcntrpmf\" Cycle and Instret Privilege Mode Filtering, Version 1.0 > Introduction", + "line_range": [ + 8, + 9 + ] + }, + { + "text": "Smcntrpmf remedies these issues by introducing privilege mode filtering for the cycle and instret counters.", + "section": "Preamble > \"Smcntrpmf\" Cycle and Instret Privilege Mode Filtering, Version 1.0 > Introduction", + "line_range": [ + 11, + 11 + ] + }, + { + "text": "mcyclecfg and minstretcfg are 64-bit registers that configure privilege mode filtering for the cycle and instret counters, respectively.", + "section": "Preamble > \"Smcntrpmf\" Cycle and Instret Privilege Mode Filtering, Version 1.0 > Introduction > CSRs > Machine Counter Configuration (`mcyclecfg`, `minstretcfg`) Registers", + "line_range": [ + 17, + 17 + ] + }, + { + "text": "[cols=\"^1,^1,^1,^1,^1,^1,^5\",stripes=even,options=\"header\"] | |63 |62 |61 |60 |59 |58 |57:0 |0 |MINH |SINH |UINH |VSINH |VUINH |WPRI |", + "section": "Preamble > \"Smcntrpmf\" Cycle and Instret Privilege Mode Filtering, Version 1.0 > Introduction > CSRs > Machine Counter Configuration (`mcyclecfg`, `minstretcfg`) Registers", + "line_range": [ + 19, + 23 + ] + }, + { + "text": "[cols=\"15%,85%\",options=\"header\"] | | Field | Description | MINH |", + "section": "Preamble > \"Smcntrpmf\" Cycle and Instret Privilege Mode Filtering, Version 1.0 > Introduction > CSRs > Machine Counter Configuration (`mcyclecfg`, `minstretcfg`) Registers", + "line_range": [ + 25, + 33 + ] + }, + { + "text": "If set, then counting of events in M-mode is inhibited | SINH |", + "section": "Preamble > \"Smcntrpmf\" Cycle and Instret Privilege Mode Filtering, Version 1.0 > Introduction > CSRs > Machine Counter Configuration (`mcyclecfg`, `minstretcfg`) Registers", + "line_range": [ + 25, + 33 + ] + }, + { + "text": "If set, then counting of events in S/HS-mode is inhibited | UINH |", + "section": "Preamble > \"Smcntrpmf\" Cycle and Instret Privilege Mode Filtering, Version 1.0 > Introduction > CSRs > Machine Counter Configuration (`mcyclecfg`, `minstretcfg`) Registers", + "line_range": [ + 25, + 33 + ] + }, + { + "text": "If set, then counting of events in U-mode is inhibited | VSINH |", + "section": "Preamble > \"Smcntrpmf\" Cycle and Instret Privilege Mode Filtering, Version 1.0 > Introduction > CSRs > Machine Counter Configuration (`mcyclecfg`, `minstretcfg`) Registers", + "line_range": [ + 25, + 33 + ] + }, + { + "text": "If set, then counting of events in VS-mode is inhibited | VUINH |", + "section": "Preamble > \"Smcntrpmf\" Cycle and Instret Privilege Mode Filtering, Version 1.0 > Introduction > CSRs > Machine Counter Configuration (`mcyclecfg`, `minstretcfg`) Registers", + "line_range": [ + 25, + 33 + ] + }, + { + "text": "If set, then counting of events in VU-mode is inhibited |", + "section": "Preamble > \"Smcntrpmf\" Cycle and Instret Privilege Mode Filtering, Version 1.0 > Introduction > CSRs > Machine Counter Configuration (`mcyclecfg`, `minstretcfg`) Registers", + "line_range": [ + 25, + 33 + ] + }, + { + "text": "When all xINH bits are zero, event counting is enabled in all modes.", + "section": "Preamble > \"Smcntrpmf\" Cycle and Instret Privilege Mode Filtering, Version 1.0 > Introduction > CSRs > Machine Counter Configuration (`mcyclecfg`, `minstretcfg`) Registers", + "line_range": [ + 35, + 35 + ] + }, + { + "text": "For each bit in 61:58, if the associated privilege mode is not implemented, the bit is read-only zero.", + "section": "Preamble > \"Smcntrpmf\" Cycle and Instret Privilege Mode Filtering, Version 1.0 > Introduction > CSRs > Machine Counter Configuration (`mcyclecfg`, `minstretcfg`) Registers", + "line_range": [ + 37, + 37 + ] + }, + { + "text": "For RV32, bits 63:32 of mcyclecfg can be accessed via the mcyclecfgh CSR, and bits 63:32 of minstretcfg can be accessed via the minstretcfgh CSR.", + "section": "Preamble > \"Smcntrpmf\" Cycle and Instret Privilege Mode Filtering, Version 1.0 > Introduction > CSRs > Machine Counter Configuration (`mcyclecfg`, `minstretcfg`) Registers", + "line_range": [ + 39, + 39 + ] + }, + { + "text": "The content of these registers may be accessible from Supervisor level if the Smcdeleg/Ssccfg extensions are implemented.", + "section": "Preamble > \"Smcntrpmf\" Cycle and Instret Privilege Mode Filtering, Version 1.0 > Introduction > CSRs > Machine Counter Configuration (`mcyclecfg`, `minstretcfg`) Registers", + "line_range": [ + 41, + 41 + ] + }, + { + "text": "The fundamental behavior of cycle and instret is modified in that counting does not occur while executing in an inhibited privilege mode.", + "section": "Preamble > \"Smcntrpmf\" Cycle and Instret Privilege Mode Filtering, Version 1.0 > Introduction > Counter Behavior", + "line_range": [ + 45, + 46 + ] + }, + { + "text": "Further, the following defines how transitions between a non-inhibited privilege mode and an inhibited privilege mode are counted.", + "section": "Preamble > \"Smcntrpmf\" Cycle and Instret Privilege Mode Filtering, Version 1.0 > Introduction > Counter Behavior", + "line_range": [ + 45, + 46 + ] + }, + { + "text": "The cycle counter will simply count CPU cycles while the CPU is in a non-inhibited privilege mode.", + "section": "Preamble > \"Smcntrpmf\" Cycle and Instret Privilege Mode Filtering, Version 1.0 > Introduction > Counter Behavior", + "line_range": [ + 48, + 49 + ] + }, + { + "text": "Mode transition operations (traps and trap returns) may take multiple clock cycles, and the change of privilege mode may be reported as occurring in any one of those cycles (possibly different for each occurrence of a trap or trap return).", + "section": "Preamble > \"Smcntrpmf\" Cycle and Instret Privilege Mode Filtering, Version 1.0 > Introduction > Counter Behavior", + "line_range": [ + 48, + 49 + ] + }, + { + "text": "For the instret counter, most instructions do not affect mode transitions, so for those the behavior is clear: instructions that retire in a non-inhibited mode increment instret, and instructions that retire in an inhibited mode do not.", + "section": "Preamble > \"Smcntrpmf\" Cycle and Instret Privilege Mode Filtering, Version 1.0 > Introduction > Counter Behavior", + "line_range": [ + 51, + 52 + ] + }, + { + "text": "There are two types of instructions that can affect a privilege mode change: instructions that cause synchronous exceptions to a more privileged mode, and xRET instructions that return to a less privileged mode.", + "section": "Preamble > \"Smcntrpmf\" Cycle and Instret Privilege Mode Filtering, Version 1.0 > Introduction > Counter Behavior", + "line_range": [ + 51, + 52 + ] + }, + { + "text": "The former are not considered to retire, and hence do not increment instret.", + "section": "Preamble > \"Smcntrpmf\" Cycle and Instret Privilege Mode Filtering, Version 1.0 > Introduction > Counter Behavior", + "line_range": [ + 51, + 52 + ] + }, + { + "text": "The latter do retire, and should increment instret only if the originating privilege mode is not inhibited.", + "section": "Preamble > \"Smcntrpmf\" Cycle and Instret Privilege Mode Filtering, Version 1.0 > Introduction > Counter Behavior", + "line_range": [ + 51, + 52 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__priv__smcsrind.json b/tools/llm-extraction/data/output/raw_chunks/src__priv__smcsrind.json new file mode 100644 index 0000000000..4b51d7ef92 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__priv__smcsrind.json @@ -0,0 +1,470 @@ +{ + "source_file": "src/priv/smcsrind.adoc", + "total": 58, + "sentences": [ + { + "text": "Smcsrind/Sscsrind is an ISA extension that extends the indirect CSR access mechanism originally defined as part of the https://github.com/riscv/riscv-aia[[.underline]Smaia/Ssaia extensions], in order to make it available for use by other extensions without creating an unnecessary dependence on Smaia/Ssaia.", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction", + "line_range": [ + 5, + 9 + ] + }, + { + "text": "This extension confers two benefits:", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction", + "line_range": [ + 11, + 11 + ] + }, + { + "text": "It provides a means to access an array of registers via CSRs without requiring allocation of large chunks of the limited CSR address space.", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction", + "line_range": [ + 13, + 14 + ] + }, + { + "text": "It enables software to access each of an array of registers by index, without requiring a switch statement with a case for each register.", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction", + "line_range": [ + 16, + 17 + ] + }, + { + "text": "The machine-level extension *Smcsrind* encompasses all added CSRs and all behavior modifications for a hart, over all privilege levels.", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction", + "line_range": [ + 19, + 24 + ] + }, + { + "text": "For a supervisor-level environment, extension *Sscsrind* is essentially the same as Smcsrind except excluding the machine-level CSRs and behavior not directly visible to supervisor level.", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction", + "line_range": [ + 19, + 24 + ] + }, + { + "text": "[width=\"100%\",cols=\"15%,12%,12%,15%,46%\",options=\"header\",] | |*Number* |*Privilege* |*Width* |*Name* |*Description* |0x350 |MRW |XLEN |`miselect` |Machine indirect register select |0x351 |MRW |XLEN |`mireg` |Machine indirect register alias |0x352 |MRW |XLEN |`mireg2` |Machine indirect register alias 2 |0x353 |MRW |XLEN |`mireg3` |Machine indirect register alias 3 |0x355 |MRW |XLEN |`mireg4` |Machine indirect register alias 4 |0x356 |MRW |XLEN |`mireg5` |Machine indirect register alias 5 |0x357 |MRW |XLEN |`mireg6` |Machine indirect register alias 6 |", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Machine-level CSRs", + "line_range": [ + 29, + 39 + ] + }, + { + "text": "The CSRs listed in the table above provide a window for accessing register state indirectly.", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Machine-level CSRs", + "line_range": [ + 41, + 48 + ] + }, + { + "text": "The value of `miselect` determines which register is accessed upon read or write of each of the machine indirect alias CSRs (`mireg*`). `miselect` value ranges are allocated to dependent extensions, which specify the register state accessible via each `miregi` register, for each `miselect` value. `miselect` is a WARL register.", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Machine-level CSRs", + "line_range": [ + 41, + 48 + ] + }, + { + "text": "The `miselect` register implements at least enough bits to support all implemented `miselect` values (corresponding to the implemented extensions that utilize `miselect`/`mireg*` to indirectly access register state).", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Machine-level CSRs", + "line_range": [ + 50, + 54 + ] + }, + { + "text": "The `miselect` register may be read-only zero if there are no extensions implemented that utilize it.", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Machine-level CSRs", + "line_range": [ + 50, + 54 + ] + }, + { + "text": "Values of `miselect` with the most-significant bit set (bit XLEN - 1 = 1) are designated only for custom use, presumably for accessing custom registers through the alias CSRs.", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Machine-level CSRs", + "line_range": [ + 56, + 63 + ] + }, + { + "text": "Values of `miselect` with the most-significant bit clear are designated only for standard use and are reserved until allocated to a standard architecture extension.", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Machine-level CSRs", + "line_range": [ + 56, + 63 + ] + }, + { + "text": "If XLEN is changed, the most-significant bit of `miselect` moves to the new position, retaining its value from before.", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Machine-level CSRs", + "line_range": [ + 56, + 63 + ] + }, + { + "text": "The behavior upon accessing `mireg*` from M-mode, while `miselect` holds a value that is not implemented, is UNSPECIFIED.", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Machine-level CSRs", + "line_range": [ + 65, + 67 + ] + }, + { + "text": "Attempts to access `mireg*` while `miselect` holds a number in an allocated and implemented range results in a specific behavior that, for each combination of `miselect` and `miregi`, is defined by the extension to which the `miselect` value is allocated.", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Machine-level CSRs", + "line_range": [ + 69, + 74 + ] + }, + { + "text": "[width=\"100%\",cols=\"15%,12%,12%,15%,46%\",options=\"header\",] | |*Number* |*Privilege* |*Width* |*Name* |*Description* |0x150 |SRW |XLEN |`siselect` |Supervisor indirect register select |0x151 |SRW |XLEN |`sireg` |Supervisor indirect register alias |0x152 |SRW |XLEN |`sireg2` |Supervisor indirect register alias 2 |0x153 |SRW |XLEN |`sireg3` |Supervisor indirect register alias 3 |0x155 |SRW |XLEN |`sireg4` |Supervisor indirect register alias 4 |0x156 |SRW |XLEN |`sireg5` |Supervisor indirect register alias 5 |0x157 |SRW |XLEN |`sireg6` |Supervisor indirect register alias 6 |", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Supervisor-level CSRs", + "line_range": [ + 80, + 90 + ] + }, + { + "text": "The CSRs in the table above are required if S-mode is implemented.", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Supervisor-level CSRs", + "line_range": [ + 92, + 92 + ] + }, + { + "text": "The `siselect` register will support the value range 0..0xFFF at a minimum. A future extension may define a value range outside of this minimum range.", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Supervisor-level CSRs", + "line_range": [ + 94, + 97 + ] + }, + { + "text": "Only if such an extension is implemented will `siselect` be required to support larger values.", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Supervisor-level CSRs", + "line_range": [ + 94, + 97 + ] + }, + { + "text": "Values of `siselect` with the most-significant bit set (bit XLEN - 1 = 1) are designated only for custom use, presumably for accessing custom registers through the alias CSRs.", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Supervisor-level CSRs", + "line_range": [ + 99, + 107 + ] + }, + { + "text": "Values of `siselect` with the most-significant bit clear are designated only for standard use and are reserved until allocated to a standard architecture extension.", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Supervisor-level CSRs", + "line_range": [ + 99, + 107 + ] + }, + { + "text": "If XLEN is changed, the most-significant bit of `siselect` moves to the new position, retaining its value from before.", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Supervisor-level CSRs", + "line_range": [ + 99, + 107 + ] + }, + { + "text": "The behavior upon accessing `sireg*` from M-mode or S-mode, while `siselect` holds a value that is not implemented at supervisor level, is UNSPECIFIED.", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Supervisor-level CSRs", + "line_range": [ + 109, + 111 + ] + }, + { + "text": "Otherwise, attempts to access `sireg*` from M-mode or S-mode while `siselect` holds a number in a standard-defined and implemented range result in specific behavior that, for each combination of `siselect` and `siregi`, is defined by the extension to which the `siselect` value is allocated.", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Supervisor-level CSRs", + "line_range": [ + 113, + 120 + ] + }, + { + "text": "Note that the widths of `siselect` and `sireg*` are always the current XLEN rather than SXLEN.", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Supervisor-level CSRs", + "line_range": [ + 122, + 128 + ] + }, + { + "text": "Hence, for example, if MXLEN = 64 and SXLEN = 32, then these registers are 64 bits when the current privilege mode is M (running RV64 code) but 32 bits when the privilege mode is S (RV32 code).", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Supervisor-level CSRs", + "line_range": [ + 122, + 128 + ] + }, + { + "text": "[width=\"100%\",cols=\"15%,12%,12%,15%,46%\",options=\"header\",] | |*Number* |*Privilege* |*Width* |*Name* |*Description* |0x250 |HRW |XLEN |`vsiselect` |Virtual supervisor indirect register select", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Virtual Supervisor-level CSRs", + "line_range": [ + 132, + 136 + ] + }, + { + "text": "|0x251 |HRW |XLEN |`vsireg` |Virtual supervisor indirect register alias", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Virtual Supervisor-level CSRs", + "line_range": [ + 138, + 138 + ] + }, + { + "text": "|0x252 |HRW |XLEN |`vsireg2` |Virtual supervisor indirect register alias 2", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Virtual Supervisor-level CSRs", + "line_range": [ + 140, + 140 + ] + }, + { + "text": "|0x253 |HRW |XLEN |`vsireg3` |Virtual supervisor indirect register alias 3", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Virtual Supervisor-level CSRs", + "line_range": [ + 142, + 142 + ] + }, + { + "text": "|0x255 |HRW |XLEN |`vsireg4` |Virtual supervisor indirect register alias 4", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Virtual Supervisor-level CSRs", + "line_range": [ + 144, + 144 + ] + }, + { + "text": "|0x256 |HRW |XLEN |`vsireg5` |Virtual supervisor indirect register alias 5", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Virtual Supervisor-level CSRs", + "line_range": [ + 146, + 146 + ] + }, + { + "text": "|0x257 |HRW |XLEN |`vsireg6` |Virtual supervisor indirect register alias 6 |", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Virtual Supervisor-level CSRs", + "line_range": [ + 148, + 149 + ] + }, + { + "text": "The CSRs in the table above are required if the hypervisor extension is implemented.", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Virtual Supervisor-level CSRs", + "line_range": [ + 151, + 154 + ] + }, + { + "text": "These VS CSRs all match supervisor CSRs, and substitute for those supervisor CSRs when executing in a virtual machine (in VS-mode or VU-mode).", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Virtual Supervisor-level CSRs", + "line_range": [ + 151, + 154 + ] + }, + { + "text": "The `vsiselect` register will support the value range 0..0xFFF at a minimum. A future extension may define a value range outside of this minimum range.", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Virtual Supervisor-level CSRs", + "line_range": [ + 156, + 159 + ] + }, + { + "text": "Only if such an extension is implemented will `vsiselect` be required to support larger values.", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Virtual Supervisor-level CSRs", + "line_range": [ + 156, + 159 + ] + }, + { + "text": "Values of `vsiselect` with the most-significant bit set (bit XLEN - 1 = 1) are designated only for custom use, presumably for accessing custom registers through the alias CSRs.", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Virtual Supervisor-level CSRs", + "line_range": [ + 161, + 169 + ] + }, + { + "text": "Values of `vsiselect` with the most-significant bit clear are designated only for standard use and are reserved until allocated to a standard architecture extension.", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Virtual Supervisor-level CSRs", + "line_range": [ + 161, + 169 + ] + }, + { + "text": "If XLEN is changed, the most-significant bit of `vsiselect` moves to the new position, retaining its value from before.", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Virtual Supervisor-level CSRs", + "line_range": [ + 161, + 169 + ] + }, + { + "text": "For alias CSRs `sireg*` and `vsireg*`, the hypervisor extension’s usual rules for when to raise a virtual-instruction exception (based on whether an instruction is HS-qualified) are not applicable.", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Virtual Supervisor-level CSRs", + "line_range": [ + 171, + 177 + ] + }, + { + "text": "The rules given in this section for `sireg` and `vsireg` apply instead, unless overridden by the requirements specified in the section below, which take precedence over this section when extension Smstateen is also implemented.", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Virtual Supervisor-level CSRs", + "line_range": [ + 171, + 177 + ] + }, + { + "text": "A virtual-instruction exception is raised for attempts from VS-mode or VU-mode to directly access `vsiselect` or `vsireg*`, or attempts from VU-mode to access `siselect` or `sireg*`.", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Virtual Supervisor-level CSRs", + "line_range": [ + 179, + 180 + ] + }, + { + "text": "The behavior upon accessing `vsireg*` from M-mode or HS-mode, or accessing `sireg*` (really `vsireg*`) from VS-mode, while `vsiselect` holds a value that is not implemented at HS level, is UNSPECIFIED.", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Virtual Supervisor-level CSRs", + "line_range": [ + 182, + 182 + ] + }, + { + "text": "Otherwise, while `vsiselect` holds a number in a standard-defined and implemented range, attempts to access `vsireg*` from a sufficiently privileged mode, or to access `sireg*` (really `vsireg*`) from VS-mode, result in specific behavior that, for each combination of `vsiselect` and `vsiregi`, is defined by the extension to which the `vsiselect` value is allocated.", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Virtual Supervisor-level CSRs", + "line_range": [ + 184, + 191 + ] + }, + { + "text": "Like `siselect` and `sireg*`, the widths of `vsiselect` and `vsireg*` are always the current XLEN rather than VSXLEN.", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Virtual Supervisor-level CSRs", + "line_range": [ + 193, + 199 + ] + }, + { + "text": "Hence, for example, if HSXLEN = 64 and VSXLEN = 32, then these registers are 64 bits when accessed by a hypervisor in HS-mode (running RV64 code) but 32 bits for a guest OS in VS-mode (RV32 code).", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Virtual Supervisor-level CSRs", + "line_range": [ + 193, + 199 + ] + }, + { + "text": "If extension Smstateen is implemented together with Smcsrind, bit 60 of state-enable register `mstateen0` controls access to `siselect`, `sireg*`, `vsiselect`, and `vsireg*`.", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Access control by the state-enable CSRs", + "line_range": [ + 203, + 210 + ] + }, + { + "text": "When `mstateen0`[60]=0, an attempt to access one of these CSRs from a privilege mode less privileged than M-mode results in an illegal-instruction exception.", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Access control by the state-enable CSRs", + "line_range": [ + 203, + 210 + ] + }, + { + "text": "As always, the state-enable CSRs do not affect the accessibility of any state when in M-mode, only in less privileged modes.", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Access control by the state-enable CSRs", + "line_range": [ + 203, + 210 + ] + }, + { + "text": "For more explanation, see the documentation for extension Smstateen in .", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Access control by the state-enable CSRs", + "line_range": [ + 203, + 210 + ] + }, + { + "text": "Other extensions may specify that certain mstateen bits control access to registers accessed indirectly through `siselect` + `sireg*`, and/or `vsiselect` + `vsireg*`.", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Access control by the state-enable CSRs", + "line_range": [ + 212, + 218 + ] + }, + { + "text": "However, regardless of any other mstateen bits, if `mstateen0`[60] = 1, a virtual-instruction exception is raised as described in the previous section for all attempts from VS-mode or VU-mode to directly access `vsiselect` or `vsireg*`, and for all attempts from VU-mode to access `siselect` or `sireg*`.", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Access control by the state-enable CSRs", + "line_range": [ + 212, + 218 + ] + }, + { + "text": "If the hypervisor extension is implemented, the same bit is defined also in hypervisor CSR `hstateen0`, but controls access to only `siselect` and `sireg*` (really `vsiselect` and `vsireg*`), which is the state potentially accessible to a virtual machine executing in VS or VU-mode.", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Access control by the state-enable CSRs", + "line_range": [ + 220, + 228 + ] + }, + { + "text": "When `hstateen0`[60]=0 and `mstateen0`[60]=1, all attempts from VS or VU-mode to access `siselect` or `sireg*` raise a virtual-instruction exception, not an illegal-instruction exception, regardless of the value of `vsiselect` or any other mstateen bit.", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Access control by the state-enable CSRs", + "line_range": [ + 220, + 228 + ] + }, + { + "text": "Extension Ssstateen is defined as the supervisor-level view of Smstateen.", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Access control by the state-enable CSRs", + "line_range": [ + 230, + 233 + ] + }, + { + "text": "Therefore, the combination of Sscsrind and Ssstateen incorporates the bit defined above for `hstateen0` but not that for `mstateen0`, since machine-level CSRs are not visible to supervisor level.", + "section": "Preamble > \"Smcsrind/Sscsrind\" Indirect CSR Access, Version 1.0 > Introduction > Access control by the state-enable CSRs", + "line_range": [ + 230, + 233 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__priv__smctr.json b/tools/llm-extraction/data/output/raw_chunks/src__priv__smctr.json new file mode 100644 index 0000000000..9747907ca4 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__priv__smctr.json @@ -0,0 +1,2190 @@ +{ + "source_file": "src/priv/smctr.adoc", + "total": 273, + "sentences": [ + { + "text": "A method for recording control flow transfer history is valuable not only for performance profiling but also for debugging.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0", + "line_range": [ + 4, + 4 + ] + }, + { + "text": "Control flow transfers refer to jump instructions (including function calls and returns), taken branch instructions, traps, and trap returns.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0", + "line_range": [ + 4, + 4 + ] + }, + { + "text": "Profiling tools, such as Linux perf, collect control transfer history when sampling software execution, thereby enabling tools, like AutoFDO, to identify hot paths for optimization.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0", + "line_range": [ + 4, + 4 + ] + }, + { + "text": "Control flow trace capabilities offer very deep transfer history, but the volume of data produced can result in significant performance overheads due to memory bandwidth consumption, buffer management, and decoder overhead.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0", + "line_range": [ + 6, + 6 + ] + }, + { + "text": "The Control Transfer Records (CTR) extension provides a method to record a limited history in register-accessible internal chip storage, with the intent of dramatically reducing the performance overhead and complexity of collecting transfer history.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0", + "line_range": [ + 6, + 6 + ] + }, + { + "text": "CTR defines a circular (FIFO) buffer.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0", + "line_range": [ + 8, + 8 + ] + }, + { + "text": "Each buffer entry holds a record for a single recorded control flow transfer.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0", + "line_range": [ + 8, + 8 + ] + }, + { + "text": "The number of records that can be held in the buffer depends upon both the implementation (the maximum supported depth) and the CTR configuration (the software selected depth).", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0", + "line_range": [ + 8, + 8 + ] + }, + { + "text": "Only qualified transfers are recorded.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0", + "line_range": [ + 10, + 10 + ] + }, + { + "text": "Qualified transfers are those that meet the filtering criteria, which include the privilege mode and the transfer type.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0", + "line_range": [ + 10, + 10 + ] + }, + { + "text": "Recorded transfers are inserted at the write pointer, which is then incremented, while older recorded transfers may be overwritten once the buffer is full.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0", + "line_range": [ + 12, + 12 + ] + }, + { + "text": "Or the user can enable RAS (Return Address Stack) emulation mode, where only function calls are recorded, and function returns pop the last call record.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0", + "line_range": [ + 12, + 12 + ] + }, + { + "text": "The source PC, target PC, and some optional metadata (transfer type, elapsed cycles) are stored for each recorded transfer.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0", + "line_range": [ + 12, + 12 + ] + }, + { + "text": "The CTR buffer is accessible through an indirect CSR interface, such that software can specify which logical entry in the buffer it wishes to read or write.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0", + "line_range": [ + 14, + 14 + ] + }, + { + "text": "Logical entry 0 always corresponds to the youngest recorded transfer, followed by entry 1 as the next youngest, and so on.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0", + "line_range": [ + 14, + 14 + ] + }, + { + "text": "The machine-level extension, *Smctr*, encompasses all newly added Control Status Registers (CSRs), instructions, and behavior modifications for a hart across all privilege levels.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0", + "line_range": [ + 16, + 16 + ] + }, + { + "text": "The corresponding supervisor-level extension, *Ssctr*, is essentially identical to Smctr, except that it excludes machine-level CSRs and behaviors not intended to be directly accessible at the supervisor level.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0", + "line_range": [ + 16, + 16 + ] + }, + { + "text": "Smctr and Ssctr depend on both the implementation of S-mode and the Sscsrind extension.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0", + "line_range": [ + 18, + 18 + ] + }, + { + "text": "The `mctrctl` register is a 64-bit read/write register that enables and configures the CTR capability.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`)", + "line_range": [ + 24, + 24 + ] + }, + { + "text": ".Machine Control Transfer Records Control Register Format [wavedrom, , svg] .... {reg: [ {bits: 1, name: 'U'}, {bits: 1, name: 'S'}, {bits: 1, name: 'M'}, {bits: 4, name: 'WPRI'}, {bits: 1, name: 'RASEMU'}, {bits: 1, name: 'STE'}, {bits: 1, name: 'MTE'}, {bits: 1, name: 'WPRI'}, {bits: 1, name: 'BPFRZ'}, {bits: 1, name: 'LCOFIFRZ'}, {bits: 20, name: 'WPRI'}, {bits: 1, name: 'EXCINH'}, {bits: 1, name: 'INTRINH'}, {bits: 1, name: 'TRETINH'}, {bits: 1, name: 'NTBREN'}, {bits: 1, name: 'TKBRINH'}, {bits: 2, name: 'WPRI'}, {bits: 1, name: 'INDCALLINH'}, {bits: 1, name: 'DIRCALLINH'}, {bits: 1, name: 'INDJMPINH'}, {bits: 1, name: 'DIRJMPINH'}, {bits: 1, name: 'CORSWAPINH'}, {bits: 1, name: 'RETINH'}, {bits: 1, name: 'INDLJMPINH'}, {bits: 1, name: 'DIRLJMPINH'}, {bits: 12, name: 'WPRI'}, {bits: 4, name: 'Custom'}, ], config:{lanes: 8, hspace:1024}} ....", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`)", + "line_range": [ + 26, + 59 + ] + }, + { + "text": ".Machine Control Transfer Records Control Register Field Definitions [width=\"100%\",cols=\"20%,80%\",options=\"header\",] | |Field |Description |M, S, U |Enable transfer recording in the selected privileged mode(s).", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`)", + "line_range": [ + 61, + 66 + ] + }, + { + "text": "|RASEMU |Enables RAS (Return Address Stack) Emulation Mode.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`)", + "line_range": [ + 68, + 68 + ] + }, + { + "text": "|MTE |Enables recording of traps to M-mode when M=0.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`)", + "line_range": [ + 70, + 70 + ] + }, + { + "text": "|STE |Enables recording of traps to S-mode when S=0.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`)", + "line_range": [ + 72, + 72 + ] + }, + { + "text": "|BPFRZ |Set `sctrstatus`.FROZEN on a breakpoint exception that traps to M-mode or S-mode.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`)", + "line_range": [ + 74, + 74 + ] + }, + { + "text": "|LCOFIFRZ |Set `sctrstatus`.FROZEN on local-counter-overflow interrupt (LCOFI) that traps to M-mode or S-mode.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`)", + "line_range": [ + 76, + 76 + ] + }, + { + "text": "|EXCINH |Inhibit recording of exceptions.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`)", + "line_range": [ + 78, + 78 + ] + }, + { + "text": "|INTRINH |Inhibit recording of interrupts.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`)", + "line_range": [ + 80, + 80 + ] + }, + { + "text": "|TRETINH |Inhibit recording of trap returns.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`)", + "line_range": [ + 82, + 82 + ] + }, + { + "text": "|NTBREN |Enable recording of not-taken branches.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`)", + "line_range": [ + 84, + 84 + ] + }, + { + "text": "|TKBRINH |Inhibit recording of taken branches.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`)", + "line_range": [ + 86, + 86 + ] + }, + { + "text": "|INDCALLINH |Inhibit recording of indirect calls.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`)", + "line_range": [ + 88, + 88 + ] + }, + { + "text": "|DIRCALLINH |Inhibit recording of direct calls.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`)", + "line_range": [ + 90, + 90 + ] + }, + { + "text": "|INDJMPINH |Inhibit recording of indirect jumps (without linkage).", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`)", + "line_range": [ + 92, + 92 + ] + }, + { + "text": "|DIRJMPINH |Inhibit recording of direct jumps (without linkage).", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`)", + "line_range": [ + 94, + 94 + ] + }, + { + "text": "|CORSWAPINH |Inhibit recording of co-routine swaps.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`)", + "line_range": [ + 96, + 96 + ] + }, + { + "text": "|RETINH |Inhibit recording of function returns.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`)", + "line_range": [ + 98, + 98 + ] + }, + { + "text": "|INDLJMPINH |Inhibit recording of other indirect jumps (with linkage).", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`)", + "line_range": [ + 100, + 100 + ] + }, + { + "text": "|DIRLJMPINH |Inhibit recording of other direct jumps (with linkage).", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`)", + "line_range": [ + 102, + 104 + ] + }, + { + "text": "See . |Custom[3:0] | WARL bits designated for custom use.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`)", + "line_range": [ + 102, + 104 + ] + }, + { + "text": "The value 0 must correspond to standard behavior.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`)", + "line_range": [ + 102, + 104 + ] + }, + { + "text": "-- All fields are optional except for M, S, U, and BPFRZ.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`)", + "line_range": [ + 106, + 109 + ] + }, + { + "text": "All unimplemented fields are read-only 0, while all implemented fields are writable.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`)", + "line_range": [ + 106, + 109 + ] + }, + { + "text": "If the Sscofpmf extension is implemented, LCOFIFRZ must be writable. --", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`)", + "line_range": [ + 106, + 109 + ] + }, + { + "text": "The `sctrctl` register provides supervisor mode access to a subset of `mctrctl`.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Control Register (`sctrctl`)", + "line_range": [ + 113, + 113 + ] + }, + { + "text": "Bits 2 and 9 in `sctrctl` are read-only 0.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Control Register (`sctrctl`)", + "line_range": [ + 115, + 115 + ] + }, + { + "text": "As a result, the M and MTE fields in `mctrctl` are not accessible through `sctrctl`.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Control Register (`sctrctl`)", + "line_range": [ + 115, + 115 + ] + }, + { + "text": "All other `mctrctl` fields are accessible through `sctrctl`.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Control Register (`sctrctl`)", + "line_range": [ + 115, + 115 + ] + }, + { + "text": "If the H extension is implemented, the `vsctrctl` register is a 64-bit read/write register that is VS-mode's version of supervisor register `sctrctl`.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Virtual Supervisor Control Transfer Records Control Register (`vsctrctl`)", + "line_range": [ + 119, + 119 + ] + }, + { + "text": "When V=1, `vsctrctl` substitutes for the usual `sctrctl`, so instructions that normally read or modify `sctrctl` actually access `vsctrctl` instead.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Virtual Supervisor Control Transfer Records Control Register (`vsctrctl`)", + "line_range": [ + 119, + 119 + ] + }, + { + "text": ".Virtual Supervisor Control Transfer Records Control Register Format [wavedrom, , svg] .... {reg: [ {bits: 1, name: 'U'}, {bits: 1, name: 'S'}, {bits: 5, name: 'WPRI'}, {bits: 1, name: 'RASEMU'}, {bits: 1, name: 'STE'}, {bits: 2, name: 'WPRI'}, {bits: 1, name: 'BPFRZ'}, {bits: 1, name: 'LCOFIFRZ'}, {bits: 20, name: 'WPRI'}, {bits: 1, name: 'EXCINH'}, {bits: 1, name: 'INTRINH'}, {bits: 1, name: 'TRETINH'}, {bits: 1, name: 'NTBREN'}, {bits: 1, name: 'TKBRINH'}, {bits: 2, name: 'WPRI'}, {bits: 1, name: 'INDCALLINH'}, {bits: 1, name: 'DIRCALLINH'}, {bits: 1, name: 'INDJMPINH'}, {bits: 1, name: 'DIRJMPINH'}, {bits: 1, name: 'CORSWAPINH'}, {bits: 1, name: 'RETINH'}, {bits: 1, name: 'INDLJMPINH'}, {bits: 1, name: 'DIRLJMPINH'}, {bits: 12, name: 'WPRI'}, {bits: 4, name: 'Custom'}, ], config:{lanes: 8, hspace:1024}} ....", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Virtual Supervisor Control Transfer Records Control Register (`vsctrctl`)", + "line_range": [ + 121, + 152 + ] + }, + { + "text": ".Virtual Supervisor Control Transfer Records Control Register Field Definitions [width=\"100%\",cols=\"20%,80%\",options=\"header\",] | |Field |Description |S |Enable transfer recording in VS-mode. |U |Enable transfer recording in VU-mode. |STE |Enables recording of traps to VS-mode when S=0.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Virtual Supervisor Control Transfer Records Control Register (`vsctrctl`)", + "line_range": [ + 154, + 165 + ] + }, + { + "text": "See . |BPFRZ |Set `sctrstatus`.FROZEN on a breakpoint exception that traps to VS-mode.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Virtual Supervisor Control Transfer Records Control Register (`vsctrctl`)", + "line_range": [ + 154, + 165 + ] + }, + { + "text": "See . |LCOFIFRZ |Set `sctrstatus`.FROZEN on local-counter-overflow interrupt (LCOFI) that traps to VS-mode.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Virtual Supervisor Control Transfer Records Control Register (`vsctrctl`)", + "line_range": [ + 154, + 165 + ] + }, + { + "text": "See . 2+|Other field definitions match those of `sctrctl`.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Virtual Supervisor Control Transfer Records Control Register (`vsctrctl`)", + "line_range": [ + 154, + 165 + ] + }, + { + "text": "The optional fields implemented in `vsctrctl` should match those implemented in `sctrctl`. |", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Virtual Supervisor Control Transfer Records Control Register (`vsctrctl`)", + "line_range": [ + 154, + 165 + ] + }, + { + "text": "[NOTE] Unlike the CTR status register or the CTR entry registers, the CTR control register has a VS-mode version.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Virtual Supervisor Control Transfer Records Control Register (`vsctrctl`)", + "line_range": [ + 167, + 171 + ] + }, + { + "text": "This allows a guest to manage the CTR configuration directly, without requiring traps to HS-mode, while ensuring that the guest configuration (most notably the privilege mode enable bits) do not impact CTR behavior when V=0.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Virtual Supervisor Control Transfer Records Control Register (`vsctrctl`)", + "line_range": [ + 167, + 171 + ] + }, + { + "text": "The 32-bit `sctrdepth` register specifies the depth of the CTR buffer.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Depth Register (`sctrdepth`)", + "line_range": [ + 175, + 176 + ] + }, + { + "text": ".Supervisor Control Transfer Records Depth Register Format [wavedrom, , svg] .... {reg: [ {bits: 3, name: 'DEPTH'}, {bits: 29, name: 'WPRI'}, ], config:{lanes: 1, hspace:1024}} ....", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Depth Register (`sctrdepth`)", + "line_range": [ + 178, + 186 + ] + }, + { + "text": ".Supervisor Control Transfer Records Depth Register Field Definitions [width=\"100%\",cols=\"15%,85%\",options=\"header\",] | |Field |Description |DEPTH |WARL field that selects the depth of the CTR buffer.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Depth Register (`sctrdepth`)", + "line_range": [ + 188, + 193 + ] + }, + { + "text": "The depth of the CTR buffer dictates the number of entries to which the hardware records transfers.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Depth Register (`sctrdepth`)", + "line_range": [ + 207, + 207 + ] + }, + { + "text": "For a depth of N, the hardware records transfers to entries 0..N-1.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Depth Register (`sctrdepth`)", + "line_range": [ + 207, + 207 + ] + }, + { + "text": "All read as '0' and are read-only when the selected entry is in the range N to 255.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Depth Register (`sctrdepth`)", + "line_range": [ + 207, + 207 + ] + }, + { + "text": "When the depth is increased, the newly accessible entries contain unspecified but legal values.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Depth Register (`sctrdepth`)", + "line_range": [ + 207, + 207 + ] + }, + { + "text": "It is implementation-specific which DEPTH value(s) are supported. |", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Depth Register (`sctrdepth`)", + "line_range": [ + 209, + 210 + ] + }, + { + "text": "Attempts to access `sctrdepth` from VS-mode or VU-mode raise a virtual-instruction exception, unless CTR state enable access restrictions apply.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Depth Register (`sctrdepth`)", + "line_range": [ + 212, + 212 + ] + }, + { + "text": "[NOTE] It is expected that operating systems (OSs) will access `sctrdepth` only at boot, to select the maximum supported depth value.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Depth Register (`sctrdepth`)", + "line_range": [ + 214, + 217 + ] + }, + { + "text": "More frequent accesses may result in reduced performance in virtualization scenarios, as a result of traps from VS-mode incurred.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Depth Register (`sctrdepth`)", + "line_range": [ + 214, + 217 + ] + }, + { + "text": "There may be scenarios where software chooses to operate on only a subset of the entries, to reduce overhead.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Depth Register (`sctrdepth`)", + "line_range": [ + 219, + 219 + ] + }, + { + "text": "In such cases tools may choose to read only the lower entries, and OSs may choose to save/restore only on the lower entries while using SCTRCLR to clear the others.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Depth Register (`sctrdepth`)", + "line_range": [ + 219, + 219 + ] + }, + { + "text": "The value in configurable depth lies in supporting VM migration.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Depth Register (`sctrdepth`)", + "line_range": [ + 221, + 222 + ] + }, + { + "text": "It is expected that a platform spec may specify that one or more CTR depth values must be supported. A hypervisor may wish to restrict guests to using one of these required depths, in order to ensure that such guests can be migrated to any system that complies with the platform spec.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Depth Register (`sctrdepth`)", + "line_range": [ + 221, + 222 + ] + }, + { + "text": "The trapping behavior specified for VS-mode accesses to `sctrdepth` ensures that the hypervisor can impose such restrictions.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Depth Register (`sctrdepth`)", + "line_range": [ + 221, + 222 + ] + }, + { + "text": "The 32-bit `sctrstatus` register grants access to CTR status information and is updated by the hardware whenever CTR is active. CTR is active when the current privilege mode is enabled for recording and CTR is not frozen.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Status Register (`sctrstatus`)", + "line_range": [ + 226, + 226 + ] + }, + { + "text": ".Supervisor Control Transfer Records Status Register Format [wavedrom, , svg] .... {reg: [ {bits: 8, name: 'WRPTR'}, {bits: 23, name: 'WPRI'}, {bits: 1, name: 'FROZEN'}, ], config:{lanes: 2, hspace:1024}} ....", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Status Register (`sctrstatus`)", + "line_range": [ + 228, + 237 + ] + }, + { + "text": ".Supervisor Control Transfer Records Status Register Field Definitions [width=\"100%\",cols=\"15%,85%\",options=\"header\",] | |Field |Description |WRPTR |WARL field that indicates the physical CTR buffer entry to be written next.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Status Register (`sctrstatus`)", + "line_range": [ + 239, + 246 + ] + }, + { + "text": "It is incremented after new transfers are recorded (see ), though there are exceptions when `xctrctl`.RASEMU=1, see .", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Status Register (`sctrstatus`)", + "line_range": [ + 239, + 246 + ] + }, + { + "text": "For a given CTR depth (where depth = 2^(DEPTH+4)^), WRPTR wraps to 0 on an increment when the value matches depth-1, and to depth-1 on a decrement when the value is 0.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Status Register (`sctrstatus`)", + "line_range": [ + 239, + 246 + ] + }, + { + "text": "Bits above those needed to represent depth-1 (e.g., bits 7:4 for a depth of 16) are read-only 0.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Status Register (`sctrstatus`)", + "line_range": [ + 239, + 246 + ] + }, + { + "text": "On depth changes, WRPTR holds an unspecified but legal value. |FROZEN |Inhibit transfer recording.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Status Register (`sctrstatus`)", + "line_range": [ + 239, + 246 + ] + }, + { + "text": "Undefined bits in `sctrstatus` are WPRI.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Status Register (`sctrstatus`)", + "line_range": [ + 248, + 249 + ] + }, + { + "text": "Status fields may be added by future extensions, and software should ignore but preserve any fields that it does not recognize.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Status Register (`sctrstatus`)", + "line_range": [ + 248, + 249 + ] + }, + { + "text": "Undefined bits must be implemented as read-only 0, unless a custom extension is implemented and enabled (see ).", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Status Register (`sctrstatus`)", + "line_range": [ + 248, + 249 + ] + }, + { + "text": "[NOTE] Logical entry 0, accessed via `sireg*` when `siselect`=0x200, is always the physical buffer entry preceding the WRPTR entry.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Status Register (`sctrstatus`)", + "line_range": [ + 251, + 259 + ] + }, + { + "text": "More generally, the physical buffer entry Y associated with logical entry X (X < depth) can be determined using the formula Y = (WRPTR - X - 1) % depth, where depth = 2^(DEPTH+4)^.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Status Register (`sctrstatus`)", + "line_range": [ + 251, + 259 + ] + }, + { + "text": "Logical entries >= depth are read-only 0. [NOTE] Because the `sctrstatus` register is updated by hardware, writes should be performed with caution.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Status Register (`sctrstatus`)", + "line_range": [ + 251, + 259 + ] + }, + { + "text": "If a multi-instruction read-modify-write to `sctrstatus` is performed while CTR is active, and between the read and write a qualified transfer or trap that causes CTR freeze completes, a hardware update could be lost.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Status Register (`sctrstatus`)", + "line_range": [ + 251, + 259 + ] + }, + { + "text": "Software may wish to ensure that CTR is inactive before performing a read-modify-write, by ensuring that either `sctrstatus`.FROZEN=1, or that the current privilege mode is not enabled for recording.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Status Register (`sctrstatus`)", + "line_range": [ + 251, + 259 + ] + }, + { + "text": "When restoring CTR state, `sctrstatus` should be written before CTR entry state is restored.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Status Register (`sctrstatus`)", + "line_range": [ + 261, + 262 + ] + }, + { + "text": "This ensures that the software writes to logical CTR entries modify the proper physical entries.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Status Register (`sctrstatus`)", + "line_range": [ + 261, + 262 + ] + }, + { + "text": "[NOTE] Exposing the WRPTR provides a more efficient means for synthesizing CTR entries.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Status Register (`sctrstatus`)", + "line_range": [ + 264, + 267 + ] + }, + { + "text": "If a qualified control transfer is emulated, the emulator can simply increment the WRPTR, then write the synthesized record to logical entry 0.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Status Register (`sctrstatus`)", + "line_range": [ + 264, + 267 + ] + }, + { + "text": "If a qualified function return is emulated while RASEMU=1, the emulator can clear `ctrsource`.V for logical entry 0, then decrement the WRPTR.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Status Register (`sctrstatus`)", + "line_range": [ + 264, + 267 + ] + }, + { + "text": "Exposing the WRPTR may also allow support for Linux perf's https://lwn.net/Articles/802821[[.underline]stack stitching] capability.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Status Register (`sctrstatus`)", + "line_range": [ + 269, + 270 + ] + }, + { + "text": "[NOTE] Smctr/Ssctr depends upon implementation of S-mode because much of CTR state is accessible only through S-mode CSRs.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Status Register (`sctrstatus`)", + "line_range": [ + 272, + 276 + ] + }, + { + "text": "If, in the future, it becomes desirable to remove this dependency, an extension could add `mctrdepth` and `mctrstatus` CSRs that reflect the same state as `sctrdepth` and `sctrstatus`, respectively.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Status Register (`sctrstatus`)", + "line_range": [ + 272, + 276 + ] + }, + { + "text": "Further, such an extension should make CTR entries accessible via `miselect`/`mireg*`.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Machine Control Transfer Records Control Register (`mctrctl`) > Supervisor Control Transfer Records Status Register (`sctrstatus`)", + "line_range": [ + 272, + 276 + ] + }, + { + "text": "Control transfer records are stored in a CTR buffer, such that each buffer entry stores information about a single transfer.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers", + "line_range": [ + 280, + 280 + ] + }, + { + "text": "The CTR buffer entries are logically accessed via the indirect register access mechanism defined by the Sscsrind extension.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers", + "line_range": [ + 280, + 280 + ] + }, + { + "text": "The `siselect` index range 0x200 through 0x2FF is reserved for CTR logical entries 0 through 255.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers", + "line_range": [ + 280, + 280 + ] + }, + { + "text": "When `siselect` holds a value in this range, `sireg` provides access to `ctrsource`, `sireg2` provides access to `ctrtarget`, and `sireg3` provides access to `ctrdata`. `sireg4`, `sireg5`, and `sireg6` are read-only 0.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers", + "line_range": [ + 280, + 280 + ] + }, + { + "text": "When `vsiselect` holds a value in 0x200..0x2FF, the `vsireg*` registers provide access to the same CTR entry register state as the analogous `sireg*` registers.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers", + "line_range": [ + 282, + 282 + ] + }, + { + "text": "There is not a separate set of entry registers for V=1.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers", + "line_range": [ + 282, + 282 + ] + }, + { + "text": "See for cases where CTR accesses from S-mode and VS-mode may be restricted.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers", + "line_range": [ + 284, + 284 + ] + }, + { + "text": "The `ctrsource` register contains the source program counter, which is the `pc` of the recorded control transfer instruction, or the epc of the recorded trap.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers > Control Transfer Record Source Register (`ctrsource`)", + "line_range": [ + 288, + 288 + ] + }, + { + "text": "The valid (V) bit is set by the hardware when a transfer is recorded in the selected CTR buffer entry, and implies that data in `ctrsource`, `ctrtarget`, and `ctrdata` is valid for this entry.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers > Control Transfer Record Source Register (`ctrsource`)", + "line_range": [ + 288, + 288 + ] + }, + { + "text": "`ctrsource` is an MXLEN-bit WARL register that must be able to hold all valid virtual or physical addresses that can serve as a `pc`.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers > Control Transfer Record Source Register (`ctrsource`)", + "line_range": [ + 290, + 290 + ] + }, + { + "text": "It need not be able to hold any invalid addresses; implementations may convert an invalid address into a valid address that the register is capable of holding.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers > Control Transfer Record Source Register (`ctrsource`)", + "line_range": [ + 290, + 290 + ] + }, + { + "text": "When XLEN < MXLEN, both explicit writes (by software) and implicit writes (for recorded transfers) will be zero-extended.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers > Control Transfer Record Source Register (`ctrsource`)", + "line_range": [ + 290, + 290 + ] + }, + { + "text": ".Control Transfer Record Source Register Format for MXLEN=64 [wavedrom, , svg] .... {reg: [ {bits: 1, name: 'V'}, {bits: 63, name: 'PC[63:1]'}, ], config:{lanes: 1, hspace: 1024}} ....", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers > Control Transfer Record Source Register (`ctrsource`)", + "line_range": [ + 292, + 300 + ] + }, + { + "text": "[NOTE] CTR entry registers are defined as MXLEN, despite the `xireg*` CSRs used to access them being XLEN, to ensure that entries recorded in RV64 are not truncated, as a result of CSR Width Modulation, on a transition to RV32.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers > Control Transfer Record Source Register (`ctrsource`)", + "line_range": [ + 302, + 306 + ] + }, + { + "text": "The `ctrtarget` register contains the target (destination) program counter of the recorded transfer.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers > Control Transfer Record Target Register (`ctrtarget`)", + "line_range": [ + 310, + 316 + ] + }, + { + "text": "For a not-taken branch, `ctrtarget` holds the PC of the next sequential instruction following the branch.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers > Control Transfer Record Target Register (`ctrtarget`)", + "line_range": [ + 310, + 316 + ] + }, + { + "text": "The optional MISP bit is set by the hardware when the recorded transfer is an instruction whose target or taken/not-taken direction was mispredicted by the branch predictor. MISP is read-only 0 when not implemented.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers > Control Transfer Record Target Register (`ctrtarget`)", + "line_range": [ + 310, + 316 + ] + }, + { + "text": "`ctrtarget` is an MXLEN-bit WARL register that must be able to hold all valid virtual or physical addresses that can serve as a `pc`.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers > Control Transfer Record Target Register (`ctrtarget`)", + "line_range": [ + 318, + 318 + ] + }, + { + "text": "It need not be able to hold any invalid addresses; implementations may convert an invalid address into a valid address that the register is capable of holding.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers > Control Transfer Record Target Register (`ctrtarget`)", + "line_range": [ + 318, + 318 + ] + }, + { + "text": "When XLEN < MXLEN, both explicit writes (by software) and implicit writes (by recorded transfers) will be zero-extended.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers > Control Transfer Record Target Register (`ctrtarget`)", + "line_range": [ + 318, + 318 + ] + }, + { + "text": ".Control Transfer Record Target Register Format for MXLEN=64 [wavedrom, , svg] .... {reg: [ {bits: 1, name: 'MISP'}, {bits: 31, name: 'PC[31:1]'}, {bits: 32, name: 'PC[63:32]'}, ], config:{lanes: 2, hspace: 1024}} ....", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers > Control Transfer Record Target Register (`ctrtarget`)", + "line_range": [ + 320, + 329 + ] + }, + { + "text": "The `ctrdata` register contains metadata for the recorded transfer.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers > Control Transfer Record Metadata Register (`ctrdata`)", + "line_range": [ + 333, + 335 + ] + }, + { + "text": "This register must be implemented, though all fields within it are optional.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers > Control Transfer Record Metadata Register (`ctrdata`)", + "line_range": [ + 333, + 335 + ] + }, + { + "text": "Unimplemented fields are read-only 0. `ctrdata` is a 64-bit register.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers > Control Transfer Record Metadata Register (`ctrdata`)", + "line_range": [ + 333, + 335 + ] + }, + { + "text": ".Control Transfer Record Metadata Register Format [wavedrom, , svg] .... {reg: [ {bits: 4, name: 'TYPE'}, {bits: 11, name: 'WPRI'}, {bits: 1, name: 'CCV'}, {bits: 16, name: 'CC'}, {bits: 32, name: 'WPRI'}, ], config:{lanes: 2, hspace: 1024}} ....", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers > Control Transfer Record Metadata Register (`ctrdata`)", + "line_range": [ + 337, + 348 + ] + }, + { + "text": ".Control Transfer Record Metadata Register Field Definitions [width=\"100%\",cols=\"15%,75%,10%\",options=\"header\",] | |Field |Description |Access |TYPE[3:0] a| Identifies the type of the control flow transfer recorded in the entry, using the encodings listed in xref:transfer-type-defs[xrefstyle=short].", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers > Control Transfer Record Metadata Register (`ctrdata`)", + "line_range": [ + 350, + 357 + ] + }, + { + "text": "Implementations that do not support this field will report 0. |WARL", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers > Control Transfer Record Metadata Register (`ctrdata`)", + "line_range": [ + 350, + 357 + ] + }, + { + "text": "|CC[15:0] |Cycle Count, composed of the Cycle Count Exponent (CCE, in CC[15:12]) and Cycle Count Mantissa (CCM, in CC[11:0]).", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers > Control Transfer Record Metadata Register (`ctrdata`)", + "line_range": [ + 361, + 364 + ] + }, + { + "text": "Undefined bits in `ctrdata` are WPRI.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers > Control Transfer Record Metadata Register (`ctrdata`)", + "line_range": [ + 366, + 366 + ] + }, + { + "text": "Undefined bits must be implemented as read-only 0, unless a is implemented and enabled.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers > Control Transfer Record Metadata Register (`ctrdata`)", + "line_range": [ + 366, + 366 + ] + }, + { + "text": "[NOTE] Like the bits in `mctrctl`, the `ctrdata`.TYPE bits leverage the E-trace itype encodings.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Entry Registers > Control Transfer Record Metadata Register (`ctrdata`)", + "line_range": [ + 368, + 372 + ] + }, + { + "text": "[wavedrom, ,svg] .... {reg: [ {bits: 7, name: 'opcode', attr: ['7', 'SYSTEM'], type: 8}, {bits: 5, name: 'rd', attr: ['5', '0'], type: 2}, {bits: 3, name: 'funct3', attr: ['3', '0'], type: 8}, {bits: 5, name: 'rs1', attr: ['5', '0'], type: 4}, {bits: 12, name: 'func12', attr: ['12', 'SCTRCLR (0x104)'], type: 8}, ]} ....", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Instructions > Supervisor CTR Clear Instruction", + "line_range": [ + 377, + 386 + ] + }, + { + "text": "The SCTRCLR instruction performs the following operations:", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Instructions > Supervisor CTR Clear Instruction", + "line_range": [ + 388, + 388 + ] + }, + { + "text": "Zeroes all CTR , for all DEPTH values * Zeroes the CTR cycle counter and CCV (see )", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Instructions > Supervisor CTR Clear Instruction", + "line_range": [ + 390, + 391 + ] + }, + { + "text": "Any read of `ctrsource`, `ctrtarget`, or `ctrdata` that follows SCTRCLR, such that it precedes the next qualified control transfer, will return the value 0.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Instructions > Supervisor CTR Clear Instruction", + "line_range": [ + 393, + 393 + ] + }, + { + "text": "Further, the first recorded transfer following SCTRCLR will have `ctrdata`.CCV=0.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Instructions > Supervisor CTR Clear Instruction", + "line_range": [ + 393, + 393 + ] + }, + { + "text": "SCTRCLR raises an illegal-instruction exception in U-mode, and a virtual-instruction exception in VU-mode, unless CTR state enable access restrictions apply.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Instructions > Supervisor CTR Clear Instruction", + "line_range": [ + 395, + 395 + ] + }, + { + "text": "When Smstateen is implemented, the `mstateen0`.CTR bit controls access to CTR register state from privilege modes less privileged than M-mode.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > State Enable Access Control", + "line_range": [ + 399, + 399 + ] + }, + { + "text": "When `mstateen0`.CTR=1, accesses to CTR register state behave as described in and above, while SCTRCLR behaves as described in .", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > State Enable Access Control", + "line_range": [ + 399, + 399 + ] + }, + { + "text": "When `mstateen0`.CTR=0 and the privilege mode is less privileged than M-mode, the following operations raise an illegal-instruction exception:", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > State Enable Access Control", + "line_range": [ + 399, + 399 + ] + }, + { + "text": "Attempts to access `sctrctl`, `vsctrctl`, `sctrdepth`, or `sctrstatus` * Attempts to access `sireg*` when `siselect` is in 0x200..0x2FF, or `vsireg*` when `vsiselect` is in 0x200..0x2FF * Execution of the SCTRCLR instruction", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > State Enable Access Control", + "line_range": [ + 401, + 403 + ] + }, + { + "text": "When `mstateen0`.CTR=0, qualified control transfers executed in privilege modes less privileged than M-mode will continue to implicitly update entry registers and `sctrstatus`.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > State Enable Access Control", + "line_range": [ + 405, + 405 + ] + }, + { + "text": "If the H extension is implemented and `mstateen0`.CTR=1, the `hstateen0`.CTR bit controls access to supervisor CTR state when V=1.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > State Enable Access Control", + "line_range": [ + 407, + 407 + ] + }, + { + "text": "This state includes `sctrctl` (really `vsctrctl`), `sctrstatus`, and `sireg*` (really `vsireg*`) when `siselect` (really `vsiselect`) is in 0x200..0x2FF. `hstateen0`.CTR is read-only 0 when `mstateen0`.CTR=0.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > State Enable Access Control", + "line_range": [ + 407, + 407 + ] + }, + { + "text": "When `mstateen0`.CTR=1 and `hstateen0`.CTR=1, VS-mode accesses to supervisor CTR state behave as described in and above, while SCTRCLR behaves as described in .", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > State Enable Access Control", + "line_range": [ + 409, + 409 + ] + }, + { + "text": "When `mstateen0`.CTR=1 and `hstateen0`.CTR=0, both VS-mode accesses to supervisor CTR state and VS-mode execution of SCTRCLR raise a virtual-instruction exception.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > State Enable Access Control", + "line_range": [ + 409, + 409 + ] + }, + { + "text": "[NOTE] `sctrdepth` is not included in the above list of supervisor CTR state controlled by `hstateen0`.CTR since accesses to `sctrdepth` from VS-mode raise a virtual-instruction exception regardless of the value of `hstateen0`.CTR.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > State Enable Access Control", + "line_range": [ + 411, + 415 + ] + }, + { + "text": "When `hstateen0`.CTR=0, qualified control transfers executed while V=1 will continue to implicitly update entry registers and `sctrstatus`.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > State Enable Access Control", + "line_range": [ + 417, + 417 + ] + }, + { + "text": "[NOTE] See for how bit 60 in `mstateen0` and `hstateen0` can also restrict access to `sireg*`/`siselect` and `vsireg*`/`vsiselect` from privilege modes less privileged than M-mode.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > State Enable Access Control", + "line_range": [ + 419, + 423 + ] + }, + { + "text": "[NOTE] Implementations that support Smctr/Ssctr but not Smstateen/Ssstateen may observe reduced performance.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > State Enable Access Control", + "line_range": [ + 425, + 429 + ] + }, + { + "text": "Because Smctr/Ssctr introduces a significant number of new CSRs, it is desirable to avoid save/restore of CTR state when possible. A hypervisor is likely to leverage State Enable to trap on the initial guest access to CTR state, delegating CTR and enabling save/restore of guest CTR state only once the guest has begun to use it.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > State Enable Access Control", + "line_range": [ + 425, + 429 + ] + }, + { + "text": "Without Smstateen/Ssstateen, a hypervisor is required to save/restore guest CTR state on every context switch.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > State Enable Access Control", + "line_range": [ + 425, + 429 + ] + }, + { + "text": "CTR records qualified control transfers.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior", + "line_range": [ + 433, + 433 + ] + }, + { + "text": "Control transfers are qualified if they meet the following criteria:", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior", + "line_range": [ + 433, + 433 + ] + }, + { + "text": "The current privilege mode is enabled * The transfer type is not inhibited * `sctrstatus`.FROZEN is not set * The transfer completes/retires", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior", + "line_range": [ + 435, + 438 + ] + }, + { + "text": "Such qualified transfers update the at logical entry 0.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior", + "line_range": [ + 440, + 440 + ] + }, + { + "text": "As a result, older entries are pushed down the stack; the record previously in logical entry 0 moves to logical entry 1, the record in logical entry 1 moves to logical entry 2, and so on.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior", + "line_range": [ + 440, + 440 + ] + }, + { + "text": "If the CTR buffer is full, the oldest recorded entry (previously at entry depth-1) is lost.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior", + "line_range": [ + 440, + 440 + ] + }, + { + "text": "Recorded transfers will set the `ctrsource`.V bit to 1, and will update all implemented record fields.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior", + "line_range": [ + 442, + 442 + ] + }, + { + "text": "[NOTE] In order to collect accurate and representative performance profiles while using CTR, it is recommended that hardware recording of control transfers incurs no added performance overhead, e.g., in the form of retirement or instruction execution restrictions that are not present when CTR is not active.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior", + "line_range": [ + 444, + 448 + ] + }, + { + "text": "Transfers that change the privilege mode are a special case.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions", + "line_range": [ + 452, + 455 + ] + }, + { + "text": "What is recorded, if anything, depends on whether the source privilege mode and/or target privilege mode are enabled for recording, and on the transfer type (trap or trap return).", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions", + "line_range": [ + 452, + 455 + ] + }, + { + "text": "Traps between enabled privilege modes are recorded as normal.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions", + "line_range": [ + 457, + 457 + ] + }, + { + "text": "Traps from a disabled privilege mode to an enabled privilege mode are partially recorded, such that the `ctrsource`.PC is 0.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions", + "line_range": [ + 457, + 457 + ] + }, + { + "text": "Traps from an enabled mode to a disabled mode, known as external traps, are not recorded by default.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions", + "line_range": [ + 457, + 457 + ] + }, + { + "text": "See for how they can be recorded.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions", + "line_range": [ + 457, + 457 + ] + }, + { + "text": "Trap returns have similar treatment.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions", + "line_range": [ + 459, + 459 + ] + }, + { + "text": "Trap returns between enabled privilege modes are recorded as normal.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions", + "line_range": [ + 459, + 459 + ] + }, + { + "text": "Trap returns from an enabled mode back to a disabled mode are partially recorded, such that `ctrtarget`.PC is 0.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions", + "line_range": [ + 459, + 459 + ] + }, + { + "text": "Trap returns from a disabled mode to an enabled mode are not recorded.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions", + "line_range": [ + 459, + 459 + ] + }, + { + "text": "Recording in Debug Mode is always inhibited.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions", + "line_range": [ + 461, + 461 + ] + }, + { + "text": "Transfers into and out of Debug Mode are never recorded.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions", + "line_range": [ + 461, + 461 + ] + }, + { + "text": "The table below provides details on recording of privilege mode transitions.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions", + "line_range": [ + 463, + 463 + ] + }, + { + "text": "Standard dependencies on FROZEN and transfer type inhibits also apply, but are not covered by the table.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions", + "line_range": [ + 463, + 463 + ] + }, + { + "text": ".Trap and Trap Return Recording [width=\"100%\",cols=\"18%,17%,30%,35%\",] | .2+|*Transfer Type* .2+| *Source Mode* 2+|*Target Mode* |*Enabled* |*Disabled* .2+|*Trap* |*Enabled* |Recorded. | External trap.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions", + "line_range": [ + 465, + 471 + ] + }, + { + "text": "Not recorded by default, but see .", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions", + "line_range": [ + 465, + 471 + ] + }, + { + "text": "|*Disabled* |Recorded, `ctrsource`.PC is 0. |Not recorded.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions", + "line_range": [ + 473, + 473 + ] + }, + { + "text": ".2+|*Trap Return* |*Enabled* |Recorded. |Recorded, `ctrtarget`.PC is 0.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions", + "line_range": [ + 475, + 475 + ] + }, + { + "text": "|*Disabled* |Not recorded. |Not recorded. |", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions", + "line_range": [ + 477, + 478 + ] + }, + { + "text": "Transitions between VS/VU-mode and M/HS-mode are unique in that they effect a change in the active CTR control register, and hence the CTR configuration.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions > Virtualization Mode Transitions", + "line_range": [ + 482, + 482 + ] + }, + { + "text": "What is recorded, if anything, on these virtualization mode transitions depends upon fields from both `[ms]ctrctl` and `vsctrctl`.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions > Virtualization Mode Transitions", + "line_range": [ + 482, + 482 + ] + }, + { + "text": "`mctrctl`.M, `sctrctl`.S, and `vsctrctl`.{S,U} are used to determine whether the source and target modes are enabled; * `mctrctl`.MTE, `sctrctl`.STE, and `vsctrctl`.STE are used to determine whether an external trap is recorded (see ); * `sctrctl`.LCOFIFRZ and `sctrctl`.BPFRZ determine whether CTR becomes frozen (see ) * For all other `xctrctl` fields, the value in `vsctrctl` is used.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions > Virtualization Mode Transitions", + "line_range": [ + 484, + 487 + ] + }, + { + "text": "External traps are traps from a privilege mode enabled for CTR recording to a privilege mode that is not enabled for CTR recording.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions > External Traps", + "line_range": [ + 491, + 491 + ] + }, + { + "text": "By default external traps are not recorded, but privileged software running in the target mode of the trap can opt-in to allowing CTR to record external traps into that mode.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions > External Traps", + "line_range": [ + 491, + 491 + ] + }, + { + "text": "The `xctrctl`.xTE bits allow M-mode, S-mode, and VS-mode to opt-in separately.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions > External Traps", + "line_range": [ + 491, + 491 + ] + }, + { + "text": "External trap recording depends not only on the target mode, but on any intervening modes, which are modes that are more privileged than the source mode but less privileged than the target mode.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions > External Traps", + "line_range": [ + 493, + 493 + ] + }, + { + "text": "Not only must the external trap enable bit for the target mode be set, but the external trap enable bit(s) for any intervening modes must also be set.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions > External Traps", + "line_range": [ + 493, + 493 + ] + }, + { + "text": "See the table below for details.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions > External Traps", + "line_range": [ + 493, + 493 + ] + }, + { + "text": "[NOTE] Requiring intervening modes to be enabled for external traps simplifies software management of CTR.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions > External Traps", + "line_range": [ + 495, + 498 + ] + }, + { + "text": "Consider a scenario where S-mode software is configuring CTR for U-mode contexts A and B, such that external traps (to any mode) are enabled for A but not for B.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions > External Traps", + "line_range": [ + 495, + 498 + ] + }, + { + "text": "When switching between the two contexts, S-mode can simply toggle `sctrctl`.STE, rather than requiring a trap to M-mode to additionally toggle `mctrctl`.MTE.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions > External Traps", + "line_range": [ + 495, + 498 + ] + }, + { + "text": "This method does not provide the flexibility to record external traps to a more privileged mode but not to all intervening mode(s).", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions > External Traps", + "line_range": [ + 500, + 501 + ] + }, + { + "text": "Because it is expected that profiling tools generally wish to observe all external traps or none, this is not considered a meaningful limitation.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions > External Traps", + "line_range": [ + 500, + 501 + ] + }, + { + "text": ".External Trap Enable Requirements [options=\"header\", width=\"85%\", cols=\"23%,23%,54%\"] | |Source Mode |Target Mode |External Trap Enable(s) Required .2+|U-mode | S-mode | `sctrctl`.STE |M-mode | `mctrctl`.MTE, `sctrctl`.STE |S-mode | M-mode | `mctrctl`.MTE .3+|VU-mode | VS-mode | `vsctrctl`.STE | HS-mode | `sctrctl`.STE, `vsctrctl`.STE | M-mode | `mctrctl`.MTE, `sctrctl`.STE, `vsctrctl`.STE .2+| VS-mode | HS-mode | `sctrctl`.STE | M-mode | `mctrctl`.MTE, `sctrctl`.STE |", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions > External Traps", + "line_range": [ + 503, + 516 + ] + }, + { + "text": "In records for external traps, the `ctrtarget`.PC is 0.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions > External Traps", + "line_range": [ + 518, + 518 + ] + }, + { + "text": "[NOTE] No mechanism exists for recording external trap returns, because the external trap record includes all relevant information, and gives the trap handler (e.g., an emulator) the opportunity to modify the record.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions > External Traps", + "line_range": [ + 520, + 527 + ] + }, + { + "text": "[NOTE] Note that external trap recording does not depend on EXCINH/INTRINH.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions > External Traps", + "line_range": [ + 529, + 532 + ] + }, + { + "text": "Thus, when external traps are enabled, both external interrupts and external exceptions are recorded.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions > External Traps", + "line_range": [ + 529, + 532 + ] + }, + { + "text": "STE allows recording of traps from U-mode to S-mode as well as from VS/VU-mode to HS-mode.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions > External Traps", + "line_range": [ + 534, + 535 + ] + }, + { + "text": "The hypervisor can flip `sctrctl`.STE before entering a guest if it wants different behavior for U-to-S vs VS/VU-to-HS.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions > External Traps", + "line_range": [ + 534, + 535 + ] + }, + { + "text": "If external trap recording is implemented, `mctrctl`.MTE and `sctrctl`.STE must be implemented, while `vsctrctl`.STE must be implemented if the H extension is implemented.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Privilege Mode Transitions > External Traps", + "line_range": [ + 537, + 537 + ] + }, + { + "text": "Default CTR behavior, when all transfer type filter bits (`xctrctl`[47:32]) are unimplemented or 0, is to record all control transfers within enabled privileged modes.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Transfer Type Filtering", + "line_range": [ + 541, + 541 + ] + }, + { + "text": "By setting transfer type filter bits, software can opt out of recording select transfer types, or opt into recording non-default operations.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Transfer Type Filtering", + "line_range": [ + 541, + 541 + ] + }, + { + "text": "All transfer type filter bits are optional.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Transfer Type Filtering", + "line_range": [ + 541, + 541 + ] + }, + { + "text": "[NOTE] Because not-taken branches are not recorded by default, the polarity of the associated enable bit (NTBREN) is the opposite of other bits associated with transfer type filtering (TKBRINH, RETINH, etc).", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Transfer Type Filtering", + "line_range": [ + 543, + 547 + ] + }, + { + "text": "Non-default operations require opt-in rather than opt-out.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Transfer Type Filtering", + "line_range": [ + 543, + 547 + ] + }, + { + "text": "The transfer type filter bits leverage the type definitions specified in the https://github.com/riscv-non-isa/riscv-trace-spec/releases/download/v2.0rc2/riscv-trace-spec.pdf[[.underline]RISC-V Efficient Trace Spec v2.0] (Table 4.4 and Section 4.1.1).", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Transfer Type Filtering", + "line_range": [ + 549, + 551 + ] + }, + { + "text": "For completeness, the definitions are reproduced below.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Transfer Type Filtering", + "line_range": [ + 549, + 551 + ] + }, + { + "text": ".Control Transfer Type Definitions [transfer-type-defs] [width=\"60%\", cols=\"22%,78%\", options=\"header\",] | | Encoding | Transfer Type Name | 0 | Not used by CTR | 1 | Exception | 2 | Interrupt | 3 | Trap return | 4 | Not-taken branch | 5 | Taken branch | 6 | reserved | 7 | reserved | 8 | Indirect call | 9 | Direct call | 10 | Indirect jump (without linkage) | 11 | Direct jump (without linkage) | 12 | Co-routine swap | 13 | Function return | 14 | Other indirect jump (with linkage) | 15 | Other direct jump (with linkage) |", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Transfer Type Filtering", + "line_range": [ + 553, + 575 + ] + }, + { + "text": "Encodings 8 through 15 refer to various encodings of jump instructions.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Transfer Type Filtering", + "line_range": [ + 577, + 577 + ] + }, + { + "text": "The types are distinguished as described below.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Transfer Type Filtering", + "line_range": [ + 577, + 577 + ] + }, + { + "text": ".Control Transfer Type Definitions [cols=\"37%,63%\", options=\"header\",] | | Transfer Type Name | Associated Opcodes .3+| Indirect call | JALR x1, rs where rs != x5 | JALR x5, rs where rs != x1 | C.JALR rs1 where rs1 != x5 .4+| Direct call | JAL x1 | JAL x5 | C.JAL | CM.JALT index .2+| Indirect jump (without linkage) | JALR x0, rs where rs != (x1 or x5) | C.JR rs1 where rs1 != (x1 or x5) .3+| Direct jump (without linkage) | JAL x0 | C.J | CM.JT index .3+| Co-routine swap | JALR x1, x5 | JALR x5, x1 | C.JALR x5 .3+| Function return | JALR rd, rs where rs (x1 or x5) and rd != (x1 or x5) | C.JR rs1 where rs1 (x1 or x5) | CM.POPRET(Z) | Other indirect jump (with linkage) | JALR rd, rs where rs != (x1 or x5) and rd != (x0, x1, or x5) | Other direct jump (with linkage) | JAL rd where rd != (x0, x1, or x5) |", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Transfer Type Filtering", + "line_range": [ + 579, + 604 + ] + }, + { + "text": "If implementation of any transfer type filter bit results in reduced software performance, perhaps due to additional retirement restrictions, it is strongly recommended that this reduced performance apply only when the bit is set.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Transfer Type Filtering", + "line_range": [ + 606, + 610 + ] + }, + { + "text": "Alternatively, support for the bit may be omitted.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Transfer Type Filtering", + "line_range": [ + 606, + 610 + ] + }, + { + "text": "Maintaining software performance for the default CTR configuration, when all transfer type bits are cleared, is recommended.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Transfer Type Filtering", + "line_range": [ + 606, + 610 + ] + }, + { + "text": "The `ctrdata` register may optionally include a count of CPU cycles elapsed since the prior CTR record.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Cycle Counting", + "line_range": [ + 615, + 615 + ] + }, + { + "text": "The elapsed cycle count value is represented by the CC field, which has a 12-bit mantissa component (Cycle Count Mantissa, or CCM) and a 4-bit exponent component (Cycle Count Exponent, or CCE).", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Cycle Counting", + "line_range": [ + 615, + 615 + ] + }, + { + "text": "The elapsed cycle counter (CtrCycleCounter) increments at the same rate as the `mcycle` counter.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Cycle Counting", + "line_range": [ + 617, + 617 + ] + }, + { + "text": "Only cycles while CTR is active are counted, where active implies that the current privilege mode is enabled for recording and CTR is not frozen.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Cycle Counting", + "line_range": [ + 617, + 617 + ] + }, + { + "text": "The CC field is encoded such that CCE holds 0 if the CtrCycleCounter value is less than 4096, otherwise it holds the index of the most significant one bit in the CtrCycleCounter value, minus 11. CCM holds CtrCycleCounter bits CCE+10:CCE-1.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Cycle Counting", + "line_range": [ + 617, + 617 + ] + }, + { + "text": "The elapsed cycle count can then be calculated by software using the following formula:", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Cycle Counting", + "line_range": [ + 619, + 619 + ] + }, + { + "text": "[subs=\"specialchars,quotes\"] ---- if (CCE0): return CCM else: return (2^12^ + CCM) << CCE-1 endif ----", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Cycle Counting", + "line_range": [ + 621, + 629 + ] + }, + { + "text": "The CtrCycleCounter is reset on writes to `xctrctl`, and on execution of SCTRCLR, to ensure that any accumulated cycle counts do not persist across a context switch.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Cycle Counting", + "line_range": [ + 631, + 631 + ] + }, + { + "text": "An implementation that supports cycle counting must implement CCV and all CCM bits, but may implement 0..4 exponent bits in CCE.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Cycle Counting", + "line_range": [ + 633, + 638 + ] + }, + { + "text": "Unimplemented CCE bits are read-only 0.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Cycle Counting", + "line_range": [ + 633, + 638 + ] + }, + { + "text": "For implementations that support transfer type filtering, it is recommended to implement at least 3 exponent bits.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Cycle Counting", + "line_range": [ + 633, + 638 + ] + }, + { + "text": "This allows capturing the full latency of most functions, when recording only calls and returns.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Cycle Counting", + "line_range": [ + 633, + 638 + ] + }, + { + "text": "The size of the CtrCycleCounter required to support each CCE width is given in the table below.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Cycle Counting", + "line_range": [ + 640, + 640 + ] + }, + { + "text": ".Cycle Counter Size Options [width=\"70%\", cols=\"20%,38%,42%\", options=\"header\",] | | CCE bits | CtrCycleCounter bits | Max elapsed cycle value | 0 | 12 | 4095 | 1 | 13 | 8191 | 2 | 15 | 32764 | 3 | 19 | 524224 | 4 | 27 | 134201344 |", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Cycle Counting", + "line_range": [ + 642, + 652 + ] + }, + { + "text": "When CCE>1, the granularity of the reported cycle count is reduced.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Cycle Counting", + "line_range": [ + 654, + 657 + ] + }, + { + "text": "For example, when CCE=3, the bottom 2 bits of the cycle counter are not reported, and thus the reported value increments only every 4 cycles.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Cycle Counting", + "line_range": [ + 654, + 657 + ] + }, + { + "text": "As a result, the reported value represents an undercount of elapsed cycles for most cases (when the unreported bits are non-zero).", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Cycle Counting", + "line_range": [ + 654, + 657 + ] + }, + { + "text": "On average, the undercount will be (2^CCE-1^-1)/2.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Cycle Counting", + "line_range": [ + 654, + 657 + ] + }, + { + "text": "Software can reduce the average undercount to 0 by adding (2^CCE-1^-1)/2 to each computed cycle count value when CCE>1.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Cycle Counting", + "line_range": [ + 654, + 657 + ] + }, + { + "text": "Though this compressed method of representation results in some imprecision for larger cycle count values, it produces meaningful area savings, reducing storage per entry from 27 bits to 16.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Cycle Counting", + "line_range": [ + 659, + 660 + ] + }, + { + "text": "The CC value saturates when all implemented bits in CCM and CCE are 1.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Cycle Counting", + "line_range": [ + 662, + 662 + ] + }, + { + "text": "The CC value is valid only when the Cycle Count Valid (CCV) bit is set.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Cycle Counting", + "line_range": [ + 664, + 664 + ] + }, + { + "text": "If CCV=0, the CC value might not hold the correct count of elapsed active cycles since the last recorded transfer.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Cycle Counting", + "line_range": [ + 664, + 664 + ] + }, + { + "text": "The next record will have CCV=0 after a write to `xctrctl`, or execution of SCTRCLR, since CtrCycleCounter is reset. CCV should additionally be cleared after any other implementation-specific scenarios where active cycles might not be counted in CtrCycleCounter.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Cycle Counting", + "line_range": [ + 664, + 664 + ] + }, + { + "text": "When the optional `xctrctl`.RASEMU bit is implemented and set to 1, transfer recording behavior is altered to emulate the behavior of a return-address stack (RAS).", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > RAS (Return Address Stack) Emulation Mode", + "line_range": [ + 668, + 668 + ] + }, + { + "text": "Indirect and direct calls are recorded as normal * Function returns pop the most recent call, by decrementing the WRPTR then invalidating the WRPTR entry (by setting ctrsource.V=0).", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > RAS (Return Address Stack) Emulation Mode", + "line_range": [ + 670, + 675 + ] + }, + { + "text": "As a result, logical entry 0 is invalidated and moves to logical entry depth-1, while logical entries 1..depth-1 move to 0..depth-2. * Co-routine swaps affect both a return and a call.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > RAS (Return Address Stack) Emulation Mode", + "line_range": [ + 670, + 675 + ] + }, + { + "text": "Logical entry 0 is overwritten, and WRPTR is not modified. * Other transfer types are inhibited * Transfer type filtering bits (`xctrctl`[47:32]) and external trap enable bits (`xctrctl`.xTE) are ignored", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > RAS (Return Address Stack) Emulation Mode", + "line_range": [ + 670, + 675 + ] + }, + { + "text": "[NOTE] Profiling tools often collect call stacks along with each sample.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > RAS (Return Address Stack) Emulation Mode", + "line_range": [ + 677, + 684 + ] + }, + { + "text": "Stack walking, however, is a complex and often slow process that may require recompilation (e.g., -fno-omit-frame-pointer) to work reliably.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > RAS (Return Address Stack) Emulation Mode", + "line_range": [ + 677, + 684 + ] + }, + { + "text": "With RAS emulation, tools can ask CTR hardware to save call stacks even for unmodified code.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > RAS (Return Address Stack) Emulation Mode", + "line_range": [ + 677, + 684 + ] + }, + { + "text": "CTR RAS emulation has limitations.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > RAS (Return Address Stack) Emulation Mode", + "line_range": [ + 686, + 686 + ] + }, + { + "text": "The CTR buffer will contain only partial stacks in cases where the call stack depth was greater than the CTR depth, CTR recording was enabled at a lower point in the call stack than main(), or where the CTR buffer was cleared since main().", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > RAS (Return Address Stack) Emulation Mode", + "line_range": [ + 686, + 686 + ] + }, + { + "text": "The CTR stack may be corrupted in cases where calls and returns are not symmetric, such as with stack unwinding (e.g., setjmp/longjmp, C++ exceptions), where stale call entries may be left on the CTR stack, or user stack switching, where calls from multiple stacks may be intermixed.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > RAS (Return Address Stack) Emulation Mode", + "line_range": [ + 688, + 689 + ] + }, + { + "text": "[NOTE] As described in , when CCV=1, the CC field provides the elapsed cycles since the prior CTR entry was recorded.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > RAS (Return Address Stack) Emulation Mode", + "line_range": [ + 691, + 703 + ] + }, + { + "text": "This introduces implementation challenges when RASEMU=1 because, for each recorded call, there may have been several recorded calls (and returns which “popped” them) since the prior remaining call entry was recorded (see ).", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > RAS (Return Address Stack) Emulation Mode", + "line_range": [ + 691, + 703 + ] + }, + { + "text": "The implication is that returns that pop a call entry not only do not reset the cycle counter, but instead add the CC field from the popped entry to the counter.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > RAS (Return Address Stack) Emulation Mode", + "line_range": [ + 691, + 703 + ] + }, + { + "text": "For simplicity, an implementation may opt to record CCV=0 for all calls, or those whose parent call was popped, when RASEMU=1.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > RAS (Return Address Stack) Emulation Mode", + "line_range": [ + 691, + 703 + ] + }, + { + "text": "When `sctrstatus`.FROZEN=1, transfer recording is inhibited.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Freeze", + "line_range": [ + 707, + 707 + ] + }, + { + "text": "This bit can be set by hardware, as described below, or by software.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Freeze", + "line_range": [ + 707, + 707 + ] + }, + { + "text": "When `sctrctl`.LCOFIFRZ=1 and a local-counter-overflow interrupt (LCOFI) traps (as a result of an HPM counter overflow) to M-mode or to S-mode, `sctrstatus`.FROZEN is set by hardware.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Freeze", + "line_range": [ + 709, + 719 + ] + }, + { + "text": "This inhibits CTR recording until software clears FROZEN.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Freeze", + "line_range": [ + 709, + 719 + ] + }, + { + "text": "The LCOFI trap itself is not recorded. [NOTE] Freeze on LCOFI ensures that the execution path leading to the sampled instruction (`xepc`) is preserved, and that the local-counter-overflow interrupt (LCOFI) and associated Interrupt Service Routine (ISR) do not displace any recorded transfer history state.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Freeze", + "line_range": [ + 709, + 719 + ] + }, + { + "text": "It is the responsibility of the ISR to clear FROZEN before xRET, if continued control transfer recording is desired.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Freeze", + "line_range": [ + 709, + 719 + ] + }, + { + "text": "LCOFI refers only to architectural traps directly caused by a local counter overflow.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Freeze", + "line_range": [ + 721, + 723 + ] + }, + { + "text": "If a local-counter-overflow interrupt is recognized without a trap, FROZEN is not automatically set.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Freeze", + "line_range": [ + 721, + 723 + ] + }, + { + "text": "For instance, no freeze occurs if the LCOFI is pended while interrupts are masked, and software recognizes the LCOFI (perhaps by reading `stopi` or `sip`) and clears `sip`.LCOFIP before the trap is raised.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Freeze", + "line_range": [ + 721, + 723 + ] + }, + { + "text": "As a result, some or all CTR history may be overwritten while handling the LCOFI.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Freeze", + "line_range": [ + 721, + 723 + ] + }, + { + "text": "Such cases are expected to be very rare; for most usages (e.g., application profiling) privilege mode filtering is sufficient to ensure that CTR updates are inhibited while interrupts are handled in a more privileged mode.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Freeze", + "line_range": [ + 721, + 723 + ] + }, + { + "text": "Similarly, on a breakpoint exception that traps to M-mode or S-mode with `sctrctl`.BPFRZ=1, FROZEN is set by hardware.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Freeze", + "line_range": [ + 721, + 723 + ] + }, + { + "text": "The breakpoint exception itself is not recorded.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Freeze", + "line_range": [ + 721, + 723 + ] + }, + { + "text": "[NOTE] Breakpoint exception refers to synchronous exceptions with a cause value of Breakpoint (3), regardless of source (ebreak, c.ebreak, Sdtrig); it does not include entry into Debug Mode, even in cores where this is implemented as an exception.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Freeze", + "line_range": [ + 725, + 729 + ] + }, + { + "text": "If the H extension is implemented, freeze behavior for LCOFIs and breakpoint exceptions that trap to VS-mode is determined by the LCOFIFRZ and BPFRZ values, respectively, in `vsctrctl`.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Freeze", + "line_range": [ + 731, + 731 + ] + }, + { + "text": "This includes virtual LCOFIs pended by a hypervisor.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Freeze", + "line_range": [ + 731, + 731 + ] + }, + { + "text": "When a guest uses the SBI Supervisor Software Events (SSE) extension, the LCOFI will trap to HS-mode, which will then invoke a registered VS-mode LCOFI handler routine.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Freeze", + "line_range": [ + 733, + 737 + ] + }, + { + "text": "If `vsctrctl`.LCOFIFRZ=1, the HS-mode handler will need to emulate the freeze by setting `sctrstatus`.FROZEN=1 before invoking the registered handler routine.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Behavior > Freeze", + "line_range": [ + 733, + 737 + ] + }, + { + "text": "Any custom CTR extension must be associated with a non-zero value within the designated custom bits in `xctrctl`.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Custom Extensions", + "line_range": [ + 742, + 742 + ] + }, + { + "text": "When the custom bits hold a non-zero value that enables a custom extension, the extension may alter standard CTR behavior, and may define new custom status fields within `sctrstatus` or the CTR .", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Custom Extensions", + "line_range": [ + 742, + 742 + ] + }, + { + "text": "All custom status fields, and standard status fields whose behavior is altered by the custom extension, must revert to standard behavior when the custom bits hold zero.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Custom Extensions", + "line_range": [ + 742, + 742 + ] + }, + { + "text": "This includes read-only 0 behavior for any bits undefined by any implemented standard extensions.", + "section": "Preamble > \"Smctr\" Control Transfer Records Extension, Version 1.0 > CSRs > Custom Extensions", + "line_range": [ + 742, + 742 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__priv__smdbltrp.json b/tools/llm-extraction/data/output/raw_chunks/src__priv__smdbltrp.json new file mode 100644 index 0000000000..59f99bfbd8 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__priv__smdbltrp.json @@ -0,0 +1,62 @@ +{ + "source_file": "src/priv/smdbltrp.adoc", + "total": 7, + "sentences": [ + { + "text": "The Smdbltrp extension addresses a double trap (See ) in M-mode.", + "section": "Preamble > \"Smdbltrp\" Double Trap Extension, Version 1.0", + "line_range": [ + 3, + 9 + ] + }, + { + "text": "When the Smrnmi extension () is implemented, it enables invocation of the RNMI handler on a double trap in M-mode to handle the critical error.", + "section": "Preamble > \"Smdbltrp\" Double Trap Extension, Version 1.0", + "line_range": [ + 3, + 9 + ] + }, + { + "text": "If the Smrnmi extension is not implemented or if a double trap occurs during the RNMI handler's execution, this extension helps transition the hart to a critical error state and enables signaling the critical error to the platform.", + "section": "Preamble > \"Smdbltrp\" Double Trap Extension, Version 1.0", + "line_range": [ + 3, + 9 + ] + }, + { + "text": "To improve error diagnosis and resolution, this extension supports debugging harts in a critical error state.", + "section": "Preamble > \"Smdbltrp\" Double Trap Extension, Version 1.0", + "line_range": [ + 11, + 14 + ] + }, + { + "text": "The extension introduces a mechanism to enter Debug Mode instead of asserting a critical-error signal to the platform when the hart is in a critical error state.", + "section": "Preamble > \"Smdbltrp\" Double Trap Extension, Version 1.0", + "line_range": [ + 11, + 14 + ] + }, + { + "text": "See cite:[DEBUGSPEC] for details.", + "section": "Preamble > \"Smdbltrp\" Double Trap Extension, Version 1.0", + "line_range": [ + 11, + 14 + ] + }, + { + "text": "See for the operational details.", + "section": "Preamble > \"Smdbltrp\" Double Trap Extension, Version 1.0", + "line_range": [ + 16, + 16 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__priv__smepmp.json b/tools/llm-extraction/data/output/raw_chunks/src__priv__smepmp.json new file mode 100644 index 0000000000..4866908f9c --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__priv__smepmp.json @@ -0,0 +1,166 @@ +{ + "source_file": "src/priv/smepmp.adoc", + "total": 20, + "sentences": [ + { + "text": "Being able to access the memory of a process running at a high privileged execution mode, such as the Supervisor or Machine mode, from a lower privileged mode such as the User mode, introduces an obvious attack vector since it allows for an attacker to perform privilege escalation, and tamper with the code and/or data of that process. A less obvious attack vector exists when the reverse happens, in which case an attacker instead of tampering with code and/or data that belong to a high-privileged process, can tamper with the memory of an unprivileged / less-privileged process and trick the high-privileged process to use or execute it.", + "section": "Preamble > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode, Version 1.0", + "line_range": [ + 3, + 3 + ] + }, + { + "text": "Two mechanisms combine to prevent this attack vector.", + "section": "Preamble > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode, Version 1.0", + "line_range": [ + 5, + 11 + ] + }, + { + "text": "The first one prevents the OS from accessing the memory of an unprivileged process unless a specific code path is followed, and the second one prevents the OS from executing the memory of an unprivileged process at all times. RISC-V already includes support for the former through the ``sstatus.SUM`` bit, and for the latter by always denying supervisor execution of virtual memory pages marked with the U bit.", + "section": "Preamble > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode, Version 1.0", + "line_range": [ + 5, + 11 + ] + }, + { + "text": "The rationale that guided development of this extension is included in Section .", + "section": "Preamble > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode, Version 1.0 > Threat model", + "line_range": [ + 16, + 17 + ] + }, + { + "text": "Without the Smepmp extension, it is not possible for a PMP rule to be *enforced* only on non-Machine modes and *denied* on Machine mode, in order to allow access to a memory region solely by less-privileged modes.", + "section": "Preamble > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode, Version 1.0 > Threat model", + "line_range": [ + 19, + 19 + ] + }, + { + "text": "It is only possible to have a *locked* rule that will be *enforced* on all modes, or a rule that will be *enforced* on non-Machine modes and be *ignored* by Machine mode.", + "section": "Preamble > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode, Version 1.0 > Threat model", + "line_range": [ + 19, + 19 + ] + }, + { + "text": "So for any physical memory region which is not protected with a Locked rule, Machine mode has unlimited access, including the ability to execute it.", + "section": "Preamble > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode, Version 1.0 > Threat model", + "line_range": [ + 19, + 19 + ] + }, + { + "text": "Without being able to protect less-privileged modes from Machine mode, it is not possible to prevent the mentioned attack vector.", + "section": "Preamble > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode, Version 1.0 > Threat model", + "line_range": [ + 21, + 21 + ] + }, + { + "text": "This becomes even more important for RISC-V than on other architectures, since implementations are allowed where a hart only has Machine and User modes available, so the whole OS will run on Machine mode instead of the non-existent Supervisor mode.", + "section": "Preamble > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode, Version 1.0 > Threat model", + "line_range": [ + 21, + 21 + ] + }, + { + "text": "In such implementations the attack surface is greatly increased, and the same kind of attacks performed on Supervisor mode and mitigated through the virtual-memory system, can be performed on Machine mode without any available mitigations.", + "section": "Preamble > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode, Version 1.0 > Threat model", + "line_range": [ + 21, + 21 + ] + }, + { + "text": "Even on implementations with Supervisor mode present attacks are still possible against the Firmware and/or the Secure Monitor running on Machine mode.", + "section": "Preamble > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode, Version 1.0 > Threat model", + "line_range": [ + 21, + 21 + ] + }, + { + "text": "To address the threat model outlined in Section , this extension introduces the `RLB`, `MMWP`, and `MML` fields in the `mseccfg` CSR and their associated rules.", + "section": "Preamble > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode, Version 1.0 > Threat model > Smepmp Physical Memory Protection Rules", + "line_range": [ + 25, + 28 + ] + }, + { + "text": "See for the detailed specification of these fields and the corresponding rules.", + "section": "Preamble > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode, Version 1.0 > Threat model > Smepmp Physical Memory Protection Rules", + "line_range": [ + 25, + 28 + ] + }, + { + "text": "The physical memory protection rules when `mseccfg.MML` is set to 1 are summarized in the truth table below.", + "section": "Preamble > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode, Version 1.0 > Threat model > Smepmp Physical Memory Protection Rules", + "line_range": [ + 30, + 30 + ] + }, + { + "text": "[cols=\"^1,^1,^1,^1,^3,^3\",stripes=even,options=\"header\"] | 4+|Bits on pmpcfg register {set:cellbgcolor:green} 2+|Result |L|R|W|X|M Mode|S/U Mode |{set:cellbgcolor:!} 0|0|0|0 2+|Inaccessible region (Access Exception) |0|0|0|1|Access Exception|Execute-only region |0|0|1|0 2+|Shared data region: Read/write on M mode, read-only on S/U mode |0|0|1|1 2+|Shared data region: Read/write for both M and S/U mode |0|1|0|0|Access Exception|Read-only region |0|1|0|1|Access Exception|Read/Execute region |0|1|1|0|Access Exception|Read/Write region |0|1|1|1|Access Exception|Read/Write/Execute region |1|0|0|0 2+|Locked inaccessible region* (Access Exception) |1|0|0|1|Locked Execute-only region*|Access Exception |1|0|1|0 2+|Locked Shared code region: Execute only on both M and S/U mode.* |1|0|1|1 2+|Locked Shared code region: Execute only on S/U mode, read/execute on M mode.* |1|1|0|0|Locked Read-only region*|Access Exception |1|1|0|1|Locked Read/Execute region*|Access Exception |1|1|1|0|Locked Read/Write region*|Access Exception |1|1|1|1 2+|Locked Shared data region: Read only on both M and S/U mode.* |", + "section": "Preamble > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode, Version 1.0 > Threat model > Smepmp Physical Memory Protection Rules", + "line_range": [ + 32, + 52 + ] + }, + { + "text": "*: *Locked* rules cannot be removed or modified until a *PMP reset*, unless ``mseccfg.RLB`` is set.", + "section": "Preamble > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode, Version 1.0 > Threat model > Smepmp Physical Memory Protection Rules", + "line_range": [ + 54, + 54 + ] + }, + { + "text": "A visual representation of these rules is as follows:", + "section": "Preamble > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode, Version 1.0 > Threat model > Smepmp Physical Memory Protection Rules", + "line_range": [ + 56, + 56 + ] + }, + { + "text": "image::smepmp-visual-representation.png[]", + "section": "Preamble > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode, Version 1.0 > Threat model > Smepmp Physical Memory Protection Rules", + "line_range": [ + 58, + 58 + ] + }, + { + "text": "Since all fields defined in ``mseccfg`` as part of this extension are locked when set (``MMWP``/``MML``) or locked when cleared (``RLB``), software can't poll them for determining the presence of Smepmp.", + "section": "Preamble > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode, Version 1.0 > Threat model > Smepmp software discovery", + "line_range": [ + 62, + 62 + ] + }, + { + "text": "It is expected that BootROM will set ``mseccfg.MMWP`` and/or ``mseccfg.MML`` during early boot, before jumping to the firmware, so that the firmware will be able to determine the presence of Smepmp by reading ``mseccfg`` and checking the state of ``mseccfg.MMWP`` and ``mseccfg.MML``.", + "section": "Preamble > \"Smepmp\" Extension for PMP Enhancements for memory access and execution prevention in Machine mode, Version 1.0 > Threat model > Smepmp software discovery", + "line_range": [ + 62, + 62 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__priv__smrnmi.json b/tools/llm-extraction/data/output/raw_chunks/src__priv__smrnmi.json new file mode 100644 index 0000000000..eadf757c94 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__priv__smrnmi.json @@ -0,0 +1,406 @@ +{ + "source_file": "src/priv/smrnmi.adoc", + "total": 50, + "sentences": [ + { + "text": "The base machine-level architecture supports only unresumable non-maskable interrupts (UNMIs), where the NMI jumps to a handler in machine mode, overwriting the current `mepc` and `mcause` register values.", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0", + "line_range": [ + 3, + 8 + ] + }, + { + "text": "If the hart had been executing machine-mode code in a trap handler, the previous values in `mepc` and `mcause` would not be recoverable and so execution is not generally resumable.", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0", + "line_range": [ + 3, + 8 + ] + }, + { + "text": "The Smrnmi extension adds support for resumable non-maskable interrupts (RNMIs) to RISC-V.", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0", + "line_range": [ + 10, + 13 + ] + }, + { + "text": "The extension adds four new CSRs (`mnepc`, `mncause`, `mnstatus`, and `mnscratch`) to hold the interrupted state, and one new instruction, MNRET, to resume from the RNMI handler.", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0", + "line_range": [ + 10, + 13 + ] + }, + { + "text": "The `rnmi` interrupt signals are inputs to the hart.", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals", + "line_range": [ + 17, + 20 + ] + }, + { + "text": "These interrupts have higher priority than any other interrupt or exception on the hart and cannot be disabled by software.", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals", + "line_range": [ + 17, + 20 + ] + }, + { + "text": "Specifically, they are not disabled by clearing the `mstatus`.MIE register.", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals", + "line_range": [ + 17, + 20 + ] + }, + { + "text": "The RNMI interrupt trap handler address is implementation-defined.", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI Handler Addresses", + "line_range": [ + 24, + 24 + ] + }, + { + "text": "RNMI also has an associated exception trap handler address, which is implementation defined.", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI Handler Addresses", + "line_range": [ + 26, + 27 + ] + }, + { + "text": "NOTE: For example, some implementations might use the address specified in `mtvec` as the RNMI exception trap handler.", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI Handler Addresses", + "line_range": [ + 29, + 30 + ] + }, + { + "text": "This extension adds additional M-mode CSRs to enable a resumable non-maskable interrupt (RNMI).", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs", + "line_range": [ + 34, + 35 + ] + }, + { + "text": ".Resumable NMI scratch register `mnscratch` include::images/bytefield/mnscratch.edn[]", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs", + "line_range": [ + 37, + 38 + ] + }, + { + "text": "The `mnscratch` CSR holds an MXLEN-bit read-write register which enables the RNMI trap handler to save and restore the context that was interrupted.", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs", + "line_range": [ + 40, + 42 + ] + }, + { + "text": ".Resumable NMI program counter `mnepc`. include::images/bytefield/mnepc.edn[]", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs", + "line_range": [ + 44, + 45 + ] + }, + { + "text": "The `mnepc` CSR is an MXLEN-bit read-write register which on entry to the RNMI trap handler holds the PC of the instruction that took the interrupt.", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs", + "line_range": [ + 47, + 49 + ] + }, + { + "text": "The low bit of `mnepc` (`mnepc[0]`) is always zero.", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs", + "line_range": [ + 51, + 53 + ] + }, + { + "text": "On implementations that support only IALIGN=32, the two low bits (`mnepc[1:0]`) are always zero.", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs", + "line_range": [ + 51, + 53 + ] + }, + { + "text": "If an implementation allows IALIGN to be either 16 or 32 (by changing CSR `misa`, for example), then, whenever IALIGN=32, bit `mnepc[1]` is masked on reads so that it appears to be 0.", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs", + "line_range": [ + 55, + 59 + ] + }, + { + "text": "This masking occurs also for the implicit read by the MNRET instruction.", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs", + "line_range": [ + 55, + 59 + ] + }, + { + "text": "Though masked, `mnepc[1]` remains writable when IALIGN=32.", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs", + "line_range": [ + 55, + 59 + ] + }, + { + "text": "`mnepc` is a *WARL* register that must be able to hold all valid virtual addresses.", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs", + "line_range": [ + 61, + 65 + ] + }, + { + "text": "It need not be capable of holding all possible invalid addresses.", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs", + "line_range": [ + 61, + 65 + ] + }, + { + "text": "Prior to writing `mnepc`, implementations may convert an invalid address into some other invalid address that `mnepc` is capable of holding.", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs", + "line_range": [ + 61, + 65 + ] + }, + { + "text": ".Resumable NMI cause `mncause`. include::images/bytefield/mncause.edn[]", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs", + "line_range": [ + 67, + 69 + ] + }, + { + "text": "The `mncause` CSR holds the reason for the RNMI.", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs", + "line_range": [ + 71, + 79 + ] + }, + { + "text": "If the reason is an interrupt, bit MXLEN-1 is set to 1, and the RNMI cause is encoded in the least-significant bits.", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs", + "line_range": [ + 71, + 79 + ] + }, + { + "text": "If the reason is an interrupt and RNMI causes are not supported, bit MXLEN-1 is set to 1, and zero is written to the least-significant bits.", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs", + "line_range": [ + 71, + 79 + ] + }, + { + "text": "If the reason is an exception within M-mode that results in a double trap as specified in the Smdbltrp extension, bit MXLEN-1 is set to 0 and the least-significant bits are set to the cause code corresponding to the exception that precipitated the double trap.", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs", + "line_range": [ + 71, + 79 + ] + }, + { + "text": ".Resumable NMI status register `mnstatus`. include::images/bytefield/mnstatus.edn[]", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs", + "line_range": [ + 81, + 83 + ] + }, + { + "text": "The `mnstatus` CSR holds a two-bit field, MNPP, which on entry to the RNMI trap handler holds the privilege mode of the interrupted context, encoded in the same manner as `mstatus`.MPP.", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs", + "line_range": [ + 85, + 91 + ] + }, + { + "text": "If the H extension is also implemented, `mnstatus` also holds a one-bit field, MNPV, which on entry to the RNMI trap handler holds the virtualization mode of the interrupted context, encoded in the same manner as `mstatus`.MPV.", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs", + "line_range": [ + 85, + 91 + ] + }, + { + "text": "If the Zicfilp extension is implemented, `mnstatus` also holds the MNPELP field, which on entry to the RNMI trap handler holds the previous `ELP` state.", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs", + "line_range": [ + 93, + 95 + ] + }, + { + "text": "When an RNMI trap is taken, MNPELP is set to `ELP` and `ELP` is set to 0.", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs", + "line_range": [ + 93, + 95 + ] + }, + { + "text": "`mnstatus` also holds the NMIE bit.", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs", + "line_range": [ + 97, + 98 + ] + }, + { + "text": "When NMIE=1, non-maskable interrupts are enabled.", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs", + "line_range": [ + 97, + 98 + ] + }, + { + "text": "When NMIE=0, all interrupts are disabled.", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs", + "line_range": [ + 97, + 98 + ] + }, + { + "text": "When NMIE=0, the hart behaves as though `mstatus`.MPRV were clear, regardless of the current setting of `mstatus`.MPRV.", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs", + "line_range": [ + 100, + 101 + ] + }, + { + "text": "Upon reset, NMIE contains the value 0.", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs", + "line_range": [ + 103, + 103 + ] + }, + { + "text": "Software can set NMIE to 1, but attempts to clear NMIE have no effect.", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs", + "line_range": [ + 105, + 105 + ] + }, + { + "text": "For the purposes of the WFI instruction, NMIE is a global interrupt enable, meaning that the setting of NMIE does not affect the operation of the WFI instruction.", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs", + "line_range": [ + 107, + 109 + ] + }, + { + "text": "The other bits in `mnstatus` are reserved; software should write zeros and hardware implementations should return zeros.", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI CSRs", + "line_range": [ + 111, + 112 + ] + }, + { + "text": "MNRET is an M-mode-only instruction that uses the values in `mnepc` and `mnstatus` to return to the program counter, privilege mode, and virtualization mode of the interrupted context.", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > MNRET Instruction", + "line_range": [ + 116, + 121 + ] + }, + { + "text": "This instruction also sets `mnstatus`.NMIE.", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > MNRET Instruction", + "line_range": [ + 116, + 121 + ] + }, + { + "text": "If MNRET changes the privilege mode to a mode less privileged than M, it also sets `mstatus`.MPRV to 0.", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > MNRET Instruction", + "line_range": [ + 116, + 121 + ] + }, + { + "text": "If the Zicfilp extension is implemented, then if the new privileged mode is y, MNRET sets `ELP` to the logical AND of yLPE (see ) and `mnstatus`.MNPELP.", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > MNRET Instruction", + "line_range": [ + 116, + 121 + ] + }, + { + "text": "When an RNMI interrupt is detected, the interrupted PC is written to the `mnepc` CSR, the type of RNMI to the `mncause` CSR, and the privilege mode of the interrupted context to the `mnstatus` CSR.", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI Operation", + "line_range": [ + 125, + 128 + ] + }, + { + "text": "The `mnstatus`.NMIE bit is cleared, masking all interrupts.", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI Operation", + "line_range": [ + 125, + 128 + ] + }, + { + "text": "The hart then enters machine-mode and jumps to the RNMI trap handler address.", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI Operation", + "line_range": [ + 130, + 131 + ] + }, + { + "text": "The RNMI handler can resume original execution using the new MNRET instruction, which restores the PC from `mnepc`, the privilege mode from `mnstatus`, and also sets `mnstatus`.NMIE, which re-enables interrupts.", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI Operation", + "line_range": [ + 133, + 135 + ] + }, + { + "text": "If the hart encounters an exception while executing in M-mode with the `mnstatus`.NMIE bit clear, the actions taken are the same as if the exception had occurred while `mnstatus`.NMIE were set, except that the program counter is set to the RNMI exception trap handler address.", + "section": "Preamble > \"Smrnmi\" Extension for Resumable Non-Maskable Interrupts, Version 1.0 > RNMI Interrupt Signals > RNMI Operation", + "line_range": [ + 137, + 137 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__priv__smstateen.json b/tools/llm-extraction/data/output/raw_chunks/src__priv__smstateen.json new file mode 100644 index 0000000000..12450d8d64 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__priv__smstateen.json @@ -0,0 +1,758 @@ +{ + "source_file": "src/priv/smstateen.adoc", + "total": 94, + "sentences": [ + { + "text": "The implementation of optional RISC-V extensions has the potential to open covert channels between separate user threads, or between separate guest OSes running under a hypervisor.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0", + "line_range": [ + 3, + 9 + ] + }, + { + "text": "The problem occurs when an extension adds processor state -- usually explicit registers, but possibly other forms of state -- that the main OS or hypervisor is unaware of (and hence won't context-switch) but that can be modified/written by one user thread or guest OS and perceived/examined/read by another.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0", + "line_range": [ + 3, + 9 + ] + }, + { + "text": "For example, the Advanced Interrupt Architecture (AIA) for RISC-V adds to a hart as many as ten supervisor-level CSRs (`siselect`, `sireg`, `stopi`, `sseteipnum`, `sclreipnum`, `sseteienum`, `sclreienum`, `sclaimei`, `sieh`, and `siph`) and provides also the option for hardware to be backward-compatible with older, pre-AIA software.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0", + "line_range": [ + 11, + 20 + ] + }, + { + "text": "Because an older hypervisor that is oblivious to the AIA will not know to swap any of the AIA's new CSRs on context switches, the registers may then be used as a covert channel between multiple guest OSes that run atop this hypervisor.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0", + "line_range": [ + 11, + 20 + ] + }, + { + "text": "Although traditional practices might consider such a communication channel harmless, the intense focus on security today argues that a means be offered to plug such channels.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0", + "line_range": [ + 11, + 20 + ] + }, + { + "text": "The `f` registers of the RISC-V floating-point extensions and the `v` registers of the vector extension would similarly be potential covert channels between user threads, except for the existence of the FS and VS fields in the `sstatus` register.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0", + "line_range": [ + 22, + 28 + ] + }, + { + "text": "Even if an OS is unaware of, say, the vector extension and its `v` registers, access to those registers is blocked when the VS field is initialized to zero, either at machine level or by the OS itself initializing `sstatus`.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0", + "line_range": [ + 22, + 28 + ] + }, + { + "text": "Obviously, one way to prevent the use of new user-level CSRs as covert channels would be to add to `mstatus` or `sstatus` an \"XS\" field for each relevant extension, paralleling the V extension's VS field.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0", + "line_range": [ + 30, + 41 + ] + }, + { + "text": "However, this is not considered a general solution to the problem due to the number of potential future extensions that may add small amounts of state.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0", + "line_range": [ + 30, + 41 + ] + }, + { + "text": "Even with a 64-bit `sstatus` (necessitating adding `sstatush` for RV32), it is not certain there are enough remaining bits in `sstatus` to accommodate all future user-level extensions.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0", + "line_range": [ + 30, + 41 + ] + }, + { + "text": "In any event, there is no need to strain `sstatus` (and add `sstatush`) for this purpose.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0", + "line_range": [ + 30, + 41 + ] + }, + { + "text": "The \"enable\" flags that are needed to plug covert channels are not generally expected to require swapping on context switches of user threads, making them a less-than-compelling candidate for inclusion in `sstatus`.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0", + "line_range": [ + 30, + 41 + ] + }, + { + "text": "Hence, a new place is provided for them instead.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0", + "line_range": [ + 30, + 41 + ] + }, + { + "text": "The Smstateen and Ssstateen extensions collectively specify machine-mode and supervisor-mode features.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "line_range": [ + 45, + 49 + ] + }, + { + "text": "The Smstateen extension specification comprises the mstateen*, sstateen*, and hstateen* CSRs and their functionality.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "line_range": [ + 45, + 49 + ] + }, + { + "text": "The Ssstateen extension specification comprises only the sstateen* and hstateen* CSRs and their functionality.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "line_range": [ + 45, + 49 + ] + }, + { + "text": "For RV64 harts, this extension adds four new 64-bit CSRs at machine level: `mstateen0` (Machine State Enable 0), `mstateen1`, `mstateen2`, and `mstateen3`.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "line_range": [ + 51, + 53 + ] + }, + { + "text": "If supervisor mode is implemented, another four CSRs are defined at supervisor level: `sstateen0`, `sstateen1`, `sstateen2`, and `sstateen3`.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "line_range": [ + 55, + 58 + ] + }, + { + "text": "And if the hypervisor extension is implemented, another set of CSRs is added: `hstateen0`, `hstateen1`, `hstateen2`, and `hstateen3`.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "line_range": [ + 60, + 62 + ] + }, + { + "text": "For RV32, there are CSR addresses for accessing the upper 32 bits of corresponding machine-level and hypervisor CSRs: `mstateen0h`, `mstateen1h`, `mstateen2h`, `mstateen3h`, `hstateen0h`, `hstateen1h`, `hstateen2h`, and `hstateen3h`.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "line_range": [ + 64, + 68 + ] + }, + { + "text": "For the supervisor-level `sstateen` registers, high-half CSRs are not added at this time because it is expected the upper 32 bits of these registers will always be zeros, as explained later below.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "line_range": [ + 70, + 72 + ] + }, + { + "text": "Each bit of a `stateen` CSR controls less-privileged access to an extension's state, for an extension that was not deemed \"worthy\" of a full XS field in `sstatus` like the FS and VS fields for the F and V extensions.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "line_range": [ + 74, + 83 + ] + }, + { + "text": "The number of registers provided at each level is four because it is believed that 4 * 64 = 256 bits for machine and hypervisor levels, and 4 * 32 = 128 bits for supervisor level, will be adequate for many years to come, perhaps for as long as the RISC-V ISA is in use.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "line_range": [ + 74, + 83 + ] + }, + { + "text": "The exact number four is an attempted compromise between providing too few bits on the one hand and going overboard with CSRs that will never be used on the other. A possible future doubling of the number of `stateen` CSRs is covered later.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "line_range": [ + 74, + 83 + ] + }, + { + "text": "The `stateen` registers at each level control access to state at all less-privileged levels, but not at its own level.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "line_range": [ + 85, + 94 + ] + }, + { + "text": "This is analogous to how the existing `counteren` CSRs control access to performance counter registers.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "line_range": [ + 85, + 94 + ] + }, + { + "text": "Just as with the `counteren` CSRs, when a `stateen` CSR prevents access to state by less-privileged levels, an attempt in one of those privilege modes to execute an instruction that would read or write the protected state raises an illegal-instruction exception, or, if executing in VS or VU mode and the circumstances for a virtual-instruction exception apply, raises a virtual-instruction exception instead of an illegal-instruction exception.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "line_range": [ + 85, + 94 + ] + }, + { + "text": "When this extension is not implemented, all state added by an extension is accessible as defined by that extension.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "line_range": [ + 96, + 97 + ] + }, + { + "text": "When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute in that privilege mode an instruction that implicitly updates the state without reading it may or may not raise an illegal-instruction or virtual-instruction exception.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "line_range": [ + 99, + 104 + ] + }, + { + "text": "Such cases must be disambiguated by being explicitly specified one way or the other.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "line_range": [ + 99, + 104 + ] + }, + { + "text": "In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the ISA extensions that introduce the controlled state.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "line_range": [ + 106, + 107 + ] + }, + { + "text": "Each bit of a supervisor-level `sstateen` CSR controls user-level access (from U-mode or VU-mode) to an extension's state.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "line_range": [ + 109, + 112 + ] + }, + { + "text": "The intention is to allocate the bits of `sstateen` CSRs starting at the least-significant end, bit 0, through to bit 31, and then on to the next-higher-numbered `sstateen` CSR.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "line_range": [ + 109, + 112 + ] + }, + { + "text": "For every bit with a defined purpose in an `sstateen` CSR, the same bit is defined in the matching `mstateen` CSR to control access below machine level to the same state.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "line_range": [ + 114, + 126 + ] + }, + { + "text": "The upper 32 bits of an `mstateen` CSR (or for RV32, the corresponding high-half CSR) control access to state that is inherently inaccessible to user level, so no corresponding enable bits in the supervisor-level `sstateen` CSR are applicable.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "line_range": [ + 114, + 126 + ] + }, + { + "text": "The intention is to allocate bits for this purpose starting at the most-significant end, bit 63, through to bit 32, and then on to the next-higher `mstateen` CSR.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "line_range": [ + 114, + 126 + ] + }, + { + "text": "If the rate that bits are being allocated from the least-significant end for `sstateen` CSRs is sufficiently low, allocation from the most-significant end of `mstateen` CSRs may be allowed to encroach on the lower 32 bits before jumping to the next-higher `mstateen` CSR.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "line_range": [ + 114, + 126 + ] + }, + { + "text": "In that case, the bit positions of \"encroaching\" bits will remain forever read-only zeros in the matching `sstateen` CSRs.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "line_range": [ + 114, + 126 + ] + }, + { + "text": "With the hypervisor extension, the `hstateen` CSRs have identical encodings to the `mstateen` CSRs, except controlling accesses for a virtual machine (from VS and VU modes).", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "line_range": [ + 128, + 131 + ] + }, + { + "text": "Each standard-defined bit of a `stateen` CSR is WARL and may be read-only zero or one, subject to the following conditions.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "line_range": [ + 133, + 135 + ] + }, + { + "text": "Bits in any `stateen` CSR that are defined to control state that a hart doesn't implement are read-only zeros for that hart.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "line_range": [ + 137, + 145 + ] + }, + { + "text": "Likewise, all reserved bits not yet given a defined meaning are also read-only zeros.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "line_range": [ + 137, + 145 + ] + }, + { + "text": "For every bit in an `mstateen` CSR that is zero (whether read-only zero or set to zero), the same bit appears as read-only zero in the matching `hstateen` and `sstateen` CSRs.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "line_range": [ + 137, + 145 + ] + }, + { + "text": "For every bit in an `hstateen` CSR that is zero (whether read-only zero or set to zero), the same bit appears as read-only zero in `sstateen` when accessed in VS-mode.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "line_range": [ + 137, + 145 + ] + }, + { + "text": "A bit in a supervisor-level `sstateen` CSR cannot be read-only one unless the same bit is read-only one in the matching `mstateen` CSR and, if it exists, in the matching `hstateen` CSR. A bit in an `hstateen` CSR cannot be read-only one unless the same bit is read-only one in the matching `mstateen` CSR.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "line_range": [ + 147, + 150 + ] + }, + { + "text": "On reset, all writable `mstateen` bits are initialized by the hardware to zeros.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "line_range": [ + 152, + 159 + ] + }, + { + "text": "If machine-level software changes these values, it is responsible for initializing the corresponding writable bits of the `hstateen` and `sstateen` CSRs to zeros too.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "line_range": [ + 152, + 159 + ] + }, + { + "text": "Software at each privilege level should set its respective `stateen` CSRs to indicate the state it is prepared to allow less-privileged software to access.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "line_range": [ + 152, + 159 + ] + }, + { + "text": "For OSes and hypervisors, this usually means the state that the OS or hypervisor is prepared to swap on a context switch, or to manage in some other way.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "line_range": [ + 152, + 159 + ] + }, + { + "text": "For each `mstateen` CSR, bit 63 is defined to control access to the matching `sstateen` and `hstateen` CSRs.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "line_range": [ + 161, + 165 + ] + }, + { + "text": "That is, bit 63 of `mstateen0` controls access to `sstateen0` and `hstateen0`; bit 63 of `mstateen1` controls access to `sstateen1` and `hstateen1`; etc.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "line_range": [ + 161, + 165 + ] + }, + { + "text": "Likewise, bit 63 of each `hstateen` correspondingly controls access to the matching `sstateen` CSR.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "line_range": [ + 161, + 165 + ] + }, + { + "text": "A hypervisor may need this control over accesses to the `sstateen` CSRs if it ever must emulate for a virtual machine an extension that is supposed to be affected by a bit in an `sstateen` CSR.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "line_range": [ + 167, + 170 + ] + }, + { + "text": "Even if such emulation is uncommon, it should not be excluded.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "line_range": [ + 167, + 170 + ] + }, + { + "text": "Machine-level software needs identical control to be able to emulate the hypervisor extension.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "line_range": [ + 172, + 175 + ] + }, + { + "text": "That is, machine level needs control over accesses to the supervisor-level `sstateen` CSRs in order to emulate the `hstateen` CSRs, which have such control.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "line_range": [ + 172, + 175 + ] + }, + { + "text": "Bit 63 of each `mstateen` CSR may be read-only zero only if the hypervisor extension is not implemented and the matching supervisor-level `sstateen` CSR is all read-only zeros.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "line_range": [ + 177, + 182 + ] + }, + { + "text": "In that case, machine-level software should emulate attempts to access the affected `sstateen` CSR from S-mode, ignoring writes and returning zero for reads.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "line_range": [ + 177, + 182 + ] + }, + { + "text": "Bit 63 of each `hstateen` CSR is always writable (not read-only).", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions", + "line_range": [ + 177, + 182 + ] + }, + { + "text": ".Machine State Enable 0 Register (`mstateen0`) [wavedrom, ,svg] .... {reg: [ {bits: 1, name: 'C'}, {bits: 1, name: 'FCSR'}, {bits: 1, name: 'JVT'}, {bits: 51, name: 'WPRI'}, {bits: 1, name: 'CTR'}, {bits: 1, name: 'SRMCFG'}, {bits: 1, name: 'P1P13'}, {bits: 1, name: 'CONTEXT'}, {bits: 1, name: 'IMSIC'}, {bits: 1, name: 'AIA'}, {bits: 1, name: 'CSRIND'}, {bits: 1, name: 'WPRI'}, {bits: 1, name: 'ENVCFG'}, {bits: 1, name: 'SE0'}, ], config: {bits: 64, lanes: 4, hspace:1024}} ....", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions > State Enable 0 Registers", + "line_range": [ + 186, + 205 + ] + }, + { + "text": ".Hypervisor State Enable 0 Register (`hstateen0`) [wavedrom, ,svg] .... {reg: [ {bits: 1, name: 'C'}, {bits: 1, name: 'FCSR'}, {bits: 1, name: 'JVT'}, {bits: 51, name: 'WPRI'}, {bits: 1, name: 'CTR'}, {bits: 2, name: 'WPRI'}, {bits: 1, name: 'CONTEXT'}, {bits: 1, name: 'IMSIC'}, {bits: 1, name: 'AIA'}, {bits: 1, name: 'CSRIND'}, {bits: 1, name: 'WPRI'}, {bits: 1, name: 'ENVCFG'}, {bits: 1, name: 'SE0'}, ], config: {bits: 64, lanes: 4, hspace:1024}} ....", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions > State Enable 0 Registers", + "line_range": [ + 207, + 225 + ] + }, + { + "text": ".Supervisor State Enable 0 Register (`sstateen0`) [wavedrom, ,svg] .... {reg: [ {bits: 1, name: 'C'}, {bits: 1, name: 'FCSR'}, {bits: 1, name: 'JVT'}, {bits: 29, name: 'WPRI'} ], config:{bits: 32, lanes: 2, hspace:1024}} ....", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions > State Enable 0 Registers", + "line_range": [ + 227, + 236 + ] + }, + { + "text": "The C bit controls access to any and all custom state.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions > State Enable 0 Registers", + "line_range": [ + 238, + 241 + ] + }, + { + "text": "The C bit of these registers is not custom state itself; it is a standard field of a standard CSR, either `mstateen0`, `hstateen0`, or `sstateen0`.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions > State Enable 0 Registers", + "line_range": [ + 238, + 241 + ] + }, + { + "text": "The FCSR bit controls access to `fcsr` for the case when floating-point instructions operate on `x` registers instead of `f` registers as specified by the Zfinx and related extensions (Zdinx, etc.). [mstateen0fcsrroz]Whenever `misa.F` = 1, FCSR bit of `mstateen0` is read-only zero (and hence read-only zero in `hstateen0` and `sstateen0` too).", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions > State Enable 0 Registers", + "line_range": [ + 243, + 251 + ] + }, + { + "text": "For convenience, when the `stateen` CSRs are implemented and `misa.F` = 0, then if the FCSR bit of a controlling `stateen0` CSR is zero, all floating-point instructions cause an illegal-instruction exception (or virtual-instruction exception, if relevant), as though they all access `fcsr`, regardless of whether they really do.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions > State Enable 0 Registers", + "line_range": [ + 243, + 251 + ] + }, + { + "text": "The JVT bit controls access to the `jvt` CSR provided by the Zcmt extension.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions > State Enable 0 Registers", + "line_range": [ + 253, + 254 + ] + }, + { + "text": "The SE0 bit in `mstateen0` controls access to the `hstateen0`, `hstateen0h`, and the `sstateen0` CSRs.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions > State Enable 0 Registers", + "line_range": [ + 256, + 258 + ] + }, + { + "text": "The SE0 bit in `hstateen0` controls access to the `sstateen0` CSR.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions > State Enable 0 Registers", + "line_range": [ + 256, + 258 + ] + }, + { + "text": "The ENVCFG bit in `mstateen0` controls access to the `henvcfg`, `henvcfgh`, and the `senvcfg` CSRs.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions > State Enable 0 Registers", + "line_range": [ + 260, + 262 + ] + }, + { + "text": "The ENVCFG bit in `hstateen0` controls access to the `senvcfg` CSRs.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions > State Enable 0 Registers", + "line_range": [ + 260, + 262 + ] + }, + { + "text": "The CSRIND bit in `mstateen0` controls access to the `siselect`, `sireg*`, `vsiselect`, and the `vsireg*` CSRs provided by the Sscsrind extensions.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions > State Enable 0 Registers", + "line_range": [ + 264, + 268 + ] + }, + { + "text": "The CSRIND bit in `hstateen0` controls access to the `siselect` and the `sireg*`, (really `vsiselect` and `vsireg*`) CSRs provided by the Sscsrind extensions.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions > State Enable 0 Registers", + "line_range": [ + 264, + 268 + ] + }, + { + "text": "The IMSIC bit in `mstateen0` controls access to the IMSIC state, including CSRs `stopei` and `vstopei`, provided by the Ssaia extension.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions > State Enable 0 Registers", + "line_range": [ + 270, + 273 + ] + }, + { + "text": "The IMSIC bit in `hstateen0` controls access to the guest IMSIC state, including CSRs `stopei` (really `vstopei`), provided by the Ssaia extension.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions > State Enable 0 Registers", + "line_range": [ + 270, + 273 + ] + }, + { + "text": "The AIA bit in `mstateen0` controls access to all state introduced by the Ssaia extension and not controlled by either the CSRIND or the IMSIC bits.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions > State Enable 0 Registers", + "line_range": [ + 275, + 279 + ] + }, + { + "text": "The AIA bit in `hstateen0` controls access to all state introduced by the Ssaia extension and not controlled by either the CSRIND or the IMSIC bits of `hstateen0`.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions > State Enable 0 Registers", + "line_range": [ + 275, + 279 + ] + }, + { + "text": "The CONTEXT bit in `mstateen0` controls access to the `scontext` and `hcontext` CSRs provided by the Sdtrig extension.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions > State Enable 0 Registers", + "line_range": [ + 281, + 284 + ] + }, + { + "text": "The CONTEXT bit in `hstateen0` controls access to the `scontext` CSR provided by the Sdtrig extension.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions > State Enable 0 Registers", + "line_range": [ + 281, + 284 + ] + }, + { + "text": "The P1P13 bit in `mstateen0` controls access to the `hedelegh` introduced by Privileged Specification Version 1.13.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions > State Enable 0 Registers", + "line_range": [ + 286, + 288 + ] + }, + { + "text": "The SRMCFG bit in `mstateen0` controls access to the `srmcfg` CSR introduced by the Ssqosid extension.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions > State Enable 0 Registers", + "line_range": [ + 290, + 292 + ] + }, + { + "text": "After the writable bits of the machine-level `mstateen` CSRs are initialized to zeros on reset, machine-level software can set bits in these registers to enable less-privileged access to the controlled state.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions > Usage", + "line_range": [ + 296, + 304 + ] + }, + { + "text": "This may be either because machine-level software knows how to swap the state or, more likely, because machine-level software isn't swapping supervisor-level environments. (Recall that the main reason the `mstateen` CSRs must exist is so machine level can emulate the hypervisor extension.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions > Usage", + "line_range": [ + 296, + 304 + ] + }, + { + "text": "When machine level isn't emulating the hypervisor extension, it is likely there will be no need to keep any implemented `mstateen` bits zero.)", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions > Usage", + "line_range": [ + 296, + 304 + ] + }, + { + "text": "If machine level sets any writable `mstateen` bits to nonzero, it must initialize the matching `hstateen` CSRs, if they exist, by writing zeros to them.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions > Usage", + "line_range": [ + 306, + 311 + ] + }, + { + "text": "And if any `mstateen` bits that are set to one have matching bits in the `sstateen` CSRs, machine-level software must also initialize those `sstateen` CSRs by writing zeros to them.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions > Usage", + "line_range": [ + 306, + 311 + ] + }, + { + "text": "Ordinarily, machine-level software will want to set bit 63 of all `mstateen` CSRs, necessitating that it write zero to all `hstateen` CSRs.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions > Usage", + "line_range": [ + 306, + 311 + ] + }, + { + "text": "Software should ensure that all writable bits of `sstateen` CSRs are initialized to zeros when an OS at supervisor level is first entered.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions > Usage", + "line_range": [ + 313, + 316 + ] + }, + { + "text": "The OS can then set bits in these registers to enable user-level access to the controlled state, presumably because it knows how to context-swap the state.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions > Usage", + "line_range": [ + 313, + 316 + ] + }, + { + "text": "For the `sstateen` CSRs whose access by a guest OS is permitted by bit 63 of the corresponding `hstateen` CSRs, a hypervisor must include the `sstateen` CSRs in the context it swaps for a guest OS.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions > Usage", + "line_range": [ + 318, + 322 + ] + }, + { + "text": "When it starts a new guest OS, it must ensure the writable bits of those `sstateen` CSRs are initialized to zeros, and it must emulate accesses to any other `sstateen` CSRs.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions > Usage", + "line_range": [ + 318, + 322 + ] + }, + { + "text": "If software at any privilege level does not support multiple contexts for less-privilege levels, then it may choose to maximize less-privileged access to all state by writing a value of all ones to the `stateen` CSRs at its level (the `mstateen` CSRs for machine level, the `sstateen` CSRs for an OS, and the `hstateen` CSRs for a hypervisor), without knowing all the state to which it is granting access.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions > Usage", + "line_range": [ + 324, + 333 + ] + }, + { + "text": "This is justified because there is no risk of a covert channel between execution contexts at the less-privileged level when only one context exists at that level.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions > Usage", + "line_range": [ + 324, + 333 + ] + }, + { + "text": "This situation is expected to be common for machine level, and it might also arise, for example, for a type-1 hypervisor that hosts only a single guest virtual machine.", + "section": "Preamble > \"Smstateen/Ssstateen\" Extensions, Version 1.0 > State Enable Extensions > Usage", + "line_range": [ + 324, + 333 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__priv__ss.json b/tools/llm-extraction/data/output/raw_chunks/src__priv__ss.json new file mode 100644 index 0000000000..8531616718 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__priv__ss.json @@ -0,0 +1,22 @@ +{ + "source_file": "src/priv/ss.adoc", + "total": 2, + "sentences": [ + { + "text": "NOTE: This chapter is currently being restructured.", + "section": "Preamble > \"Ss\" Supervisor Extensions", + "line_range": [ + 3, + 4 + ] + }, + { + "text": "Its contents are normative, but the presentation might appear disjoint.", + "section": "Preamble > \"Ss\" Supervisor Extensions", + "line_range": [ + 3, + 4 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__priv__ssccptr.json b/tools/llm-extraction/data/output/raw_chunks/src__priv__ssccptr.json new file mode 100644 index 0000000000..57ad9d30f4 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__priv__ssccptr.json @@ -0,0 +1,14 @@ +{ + "source_file": "src/priv/ssccptr.adoc", + "total": 1, + "sentences": [ + { + "text": "If the Ssccptr extension is implemented, then main memory regions with both the cacheability and coherence PMAs must support hardware page-table reads.", + "section": "Preamble > Ssccptr Extension for Main Memory Page-Table Reads, Version 1.0", + "line_range": [ + 3, + 4 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__priv__sscofpmf.json b/tools/llm-extraction/data/output/raw_chunks/src__priv__sscofpmf.json new file mode 100644 index 0000000000..13ecd7260e --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__priv__sscofpmf.json @@ -0,0 +1,318 @@ +{ + "source_file": "src/priv/sscofpmf.adoc", + "total": 39, + "sentences": [ + { + "text": "The current Privileged specification defines mhpmevent CSRs to select and control event counting by the associated hpmcounter CSRs, but provides no standardization of any fields within these CSRs.", + "section": "Preamble > \"Sscofpmf\" Extension for Count Overflow and Mode-Based Filtering, Version 1.0", + "line_range": [ + 3, + 10 + ] + }, + { + "text": "For at least Linux-class rich-OS systems it is desirable to standardize certain basic features that are broadly desired (and have come up over the past year plus on RISC-V lists, as well as have been the subject of past proposals).", + "section": "Preamble > \"Sscofpmf\" Extension for Count Overflow and Mode-Based Filtering, Version 1.0", + "line_range": [ + 3, + 10 + ] + }, + { + "text": "This enables there to be standard upstream software support that eliminates the need for implementations to provide their own custom software support.", + "section": "Preamble > \"Sscofpmf\" Extension for Count Overflow and Mode-Based Filtering, Version 1.0", + "line_range": [ + 3, + 10 + ] + }, + { + "text": "This extension serves to accomplish exactly this within the existing mhpmevent CSRs (and correspondingly avoids the unnecessary creation of whole new sets of CSRs - past just one new CSR).", + "section": "Preamble > \"Sscofpmf\" Extension for Count Overflow and Mode-Based Filtering, Version 1.0", + "line_range": [ + 12, + 14 + ] + }, + { + "text": "This extension sticks to addressing two basic well-understood needs that have been requested by various people.", + "section": "Preamble > \"Sscofpmf\" Extension for Count Overflow and Mode-Based Filtering, Version 1.0", + "line_range": [ + 16, + 20 + ] + }, + { + "text": "To make it easy to understand the deltas from the current Priv 1.11/1.12 specs, this is written as the actual exact changes to be made to existing paragraphs of Priv spec text (or additional paragraphs within the existing text).", + "section": "Preamble > \"Sscofpmf\" Extension for Count Overflow and Mode-Based Filtering, Version 1.0", + "line_range": [ + 16, + 20 + ] + }, + { + "text": "The extension name is \"Sscofpmf\" ('Ss' for Privileged arch and Supervisor-level extensions, and 'cofpmf' for Count OverFlow and Privilege Mode Filtering).", + "section": "Preamble > \"Sscofpmf\" Extension for Count Overflow and Mode-Based Filtering, Version 1.0", + "line_range": [ + 22, + 23 + ] + }, + { + "text": "Note that the new count overflow interrupt will be treated as a standard local interrupt that is assigned to bit 13 in the mip/mie/sip/sie registers.", + "section": "Preamble > \"Sscofpmf\" Extension for Count Overflow and Mode-Based Filtering, Version 1.0", + "line_range": [ + 25, + 26 + ] + }, + { + "text": "The following bits are added to `mhpmevent`:", + "section": "Preamble > \"Sscofpmf\" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control", + "line_range": [ + 30, + 30 + ] + }, + { + "text": "[cols=\"^1,^1,^1,^1,^1,^1,^1,^1\",stripes=even,options=\"header\"] | |63 |62 |61 |60 |59 |58 |57 |56 |OF |MINH |SINH |UINH |VSINH |VUINH |WPRI |WPRI |", + "section": "Preamble > \"Sscofpmf\" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control", + "line_range": [ + 32, + 36 + ] + }, + { + "text": "[cols=\"15%,85%\",options=\"header\"] | | Field | Description | OF | Overflow status and interrupt disable bit that is set when counter overflows | MINH |", + "section": "Preamble > \"Sscofpmf\" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control", + "line_range": [ + 38, + 49 + ] + }, + { + "text": "If set, then counting of events in M-mode is inhibited | SINH |", + "section": "Preamble > \"Sscofpmf\" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control", + "line_range": [ + 38, + 49 + ] + }, + { + "text": "If set, then counting of events in S/HS-mode is inhibited | UINH |", + "section": "Preamble > \"Sscofpmf\" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control", + "line_range": [ + 38, + 49 + ] + }, + { + "text": "If set, then counting of events in U-mode is inhibited | VSINH |", + "section": "Preamble > \"Sscofpmf\" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control", + "line_range": [ + 38, + 49 + ] + }, + { + "text": "If set, then counting of events in VS-mode is inhibited | VUINH |", + "section": "Preamble > \"Sscofpmf\" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control", + "line_range": [ + 38, + 49 + ] + }, + { + "text": "If set, then counting of events in VU-mode is inhibited | WPRI | Reserved | WPRI | Reserved |", + "section": "Preamble > \"Sscofpmf\" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control", + "line_range": [ + 38, + 49 + ] + }, + { + "text": "For each ``x``INH bit, if the associated privilege mode is not implemented, the bit is read-only zero.", + "section": "Preamble > \"Sscofpmf\" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control", + "line_range": [ + 51, + 52 + ] + }, + { + "text": "Each of the five ``x``INH bits, when set, inhibit counting of events while in privilege mode ``x``.", + "section": "Preamble > \"Sscofpmf\" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control", + "line_range": [ + 54, + 57 + ] + }, + { + "text": "All-zeroes for these bits results in counting of events in all modes.", + "section": "Preamble > \"Sscofpmf\" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control", + "line_range": [ + 54, + 57 + ] + }, + { + "text": "The OF bit is set when the corresponding hpmcounter overflows, and remains set until written by software.", + "section": "Preamble > \"Sscofpmf\" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control", + "line_range": [ + 59, + 63 + ] + }, + { + "text": "Since hpmcounter values are unsigned values, overflow is defined as unsigned overflow of the implemented counter bits.", + "section": "Preamble > \"Sscofpmf\" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control", + "line_range": [ + 59, + 63 + ] + }, + { + "text": "Note that there is no loss of information after an overflow since the counter wraps around and keeps counting while the sticky OF bit remains set.", + "section": "Preamble > \"Sscofpmf\" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control", + "line_range": [ + 59, + 63 + ] + }, + { + "text": "If supervisor mode is implemented, the 32-bit scountovf register contains read-only shadow copies of the OF bits in all 29 mhpmevent registers.", + "section": "Preamble > \"Sscofpmf\" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control", + "line_range": [ + 65, + 66 + ] + }, + { + "text": "If an hpmcounter overflows while the associated OF bit is zero, then a \"count overflow interrupt request\" is generated.", + "section": "Preamble > \"Sscofpmf\" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control", + "line_range": [ + 68, + 72 + ] + }, + { + "text": "If the OF bit is one, then no interrupt request is generated.", + "section": "Preamble > \"Sscofpmf\" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control", + "line_range": [ + 68, + 72 + ] + }, + { + "text": "Consequently the OF bit also functions as a count overflow interrupt disable for the associated hpmcounter.", + "section": "Preamble > \"Sscofpmf\" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control", + "line_range": [ + 68, + 72 + ] + }, + { + "text": "Count overflow never results from writes to the mhpmcountern or mhpmeventn registers, only from hardware increments of counter registers.", + "section": "Preamble > \"Sscofpmf\" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control", + "line_range": [ + 74, + 76 + ] + }, + { + "text": "This count-overflow-interrupt-request signal is treated as a standard local interrupt that corresponds to bit 13 in the `mip`/`mie`/`sip`/`sie` registers.", + "section": "Preamble > \"Sscofpmf\" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control", + "line_range": [ + 78, + 82 + ] + }, + { + "text": "The `mip`/`sip` LCOFIP and `mie`/`sie` LCOFIE bits are, respectively, the interrupt-pending and interrupt-enable bits for this interrupt. ('LCOFI' represents 'Local Count Overflow Interrupt'.)", + "section": "Preamble > \"Sscofpmf\" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control", + "line_range": [ + 78, + 82 + ] + }, + { + "text": "Generation of a count-overflow-interrupt request by an `hpmcounter` sets the associated OF bit.", + "section": "Preamble > \"Sscofpmf\" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control", + "line_range": [ + 84, + 90 + ] + }, + { + "text": "When an OF bit is set, it eventually, but not necessarily immediately, sets the LCOFIP bit in the `mip`/`sip` registers.", + "section": "Preamble > \"Sscofpmf\" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control", + "line_range": [ + 84, + 90 + ] + }, + { + "text": "The LCOFIP bit is cleared by software before servicing the count overflow interrupt resulting from one or more count overflows.", + "section": "Preamble > \"Sscofpmf\" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control", + "line_range": [ + 84, + 90 + ] + }, + { + "text": "The `mideleg` register controls the delegation of this interrupt to S-mode versus M-mode.", + "section": "Preamble > \"Sscofpmf\" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control", + "line_range": [ + 84, + 90 + ] + }, + { + "text": "This extension adds the `scountovf` CSR, a 32-bit read-only register that contains shadow copies of the OF bits in the 29 mhpmevent CSRs (mhpmevent3 - mhpmevent31) - where scountovf bit X corresponds to mhpmeventX.", + "section": "Preamble > \"Sscofpmf\" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control > Supervisor Count Overflow (`scountovf`) Register", + "line_range": [ + 94, + 98 + ] + }, + { + "text": "This register enables supervisor-level overflow interrupt handler software to quickly and easily determine which counter(s) have overflowed (without needing to make an execution environment call or series of calls ultimately up to M-mode).", + "section": "Preamble > \"Sscofpmf\" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control > Supervisor Count Overflow (`scountovf`) Register", + "line_range": [ + 100, + 103 + ] + }, + { + "text": "Read access to bit X is subject to the same mcounteren (or mcounteren and hcounteren) CSRs that mediate access to the hpmcounter CSRs by S-mode (or VS-mode).", + "section": "Preamble > \"Sscofpmf\" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control > Supervisor Count Overflow (`scountovf`) Register", + "line_range": [ + 105, + 110 + ] + }, + { + "text": "In M-mode, scountovf bit X is always readable.", + "section": "Preamble > \"Sscofpmf\" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control > Supervisor Count Overflow (`scountovf`) Register", + "line_range": [ + 105, + 110 + ] + }, + { + "text": "In S/HS-mode, scountovf bit X is readable when mcounteren bit X is set, and otherwise reads as zero.", + "section": "Preamble > \"Sscofpmf\" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control > Supervisor Count Overflow (`scountovf`) Register", + "line_range": [ + 105, + 110 + ] + }, + { + "text": "Similarly, in VS mode, scountovf bit X is readable when mcounteren bit X and hcounteren bit X are both set, and otherwise reads as zero.", + "section": "Preamble > \"Sscofpmf\" Extension for Count Overflow and Mode-Based Filtering, Version 1.0 > Count Overflow Control > Supervisor Count Overflow (`scountovf`) Register", + "line_range": [ + 105, + 110 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__priv__sscounterenw.json b/tools/llm-extraction/data/output/raw_chunks/src__priv__sscounterenw.json new file mode 100644 index 0000000000..1017ebf352 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__priv__sscounterenw.json @@ -0,0 +1,14 @@ +{ + "source_file": "src/priv/sscounterenw.adoc", + "total": 1, + "sentences": [ + { + "text": "If the Sscounterenw extension is implemented, then for any `hpmcounter` that is not read-only zero, the corresponding bit in `scounteren` must be writable.", + "section": "Preamble > Sscounterenw Extension for Counter-Enable Writability, Version 1.0", + "line_range": [ + 3, + 4 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__priv__ssdbltrp.json b/tools/llm-extraction/data/output/raw_chunks/src__priv__ssdbltrp.json new file mode 100644 index 0000000000..c30145cf72 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__priv__ssdbltrp.json @@ -0,0 +1,54 @@ +{ + "source_file": "src/priv/ssdbltrp.adoc", + "total": 6, + "sentences": [ + { + "text": "The Ssdbltrp extension addresses a double trap (See ) privilege modes lower than M.", + "section": "Preamble > \"Ssdbltrp\" Double Trap Extension, Version 1.0", + "line_range": [ + 3, + 7 + ] + }, + { + "text": "It enables HS-mode to invoke a critical error handler in a virtual machine on a double trap in VS-mode.", + "section": "Preamble > \"Ssdbltrp\" Double Trap Extension, Version 1.0", + "line_range": [ + 3, + 7 + ] + }, + { + "text": "It also allows M-mode to invoke a critical error handler in the OS/Hypervisor on a double trap in S/HS-mode.", + "section": "Preamble > \"Ssdbltrp\" Double Trap Extension, Version 1.0", + "line_range": [ + 3, + 7 + ] + }, + { + "text": "The Ssdbltrp extension adds the `menvcfg`.DTE (See ) and the `sstatus`.SDT fields (See ).", + "section": "Preamble > \"Ssdbltrp\" Double Trap Extension, Version 1.0", + "line_range": [ + 9, + 12 + ] + }, + { + "text": "If the hypervisor extension is additionally implemented, then the extension adds the `henvcfg`.DTE (See ) and the `vsstatus`.SDT fields (See ).", + "section": "Preamble > \"Ssdbltrp\" Double Trap Extension, Version 1.0", + "line_range": [ + 9, + 12 + ] + }, + { + "text": "See for the operational details.", + "section": "Preamble > \"Ssdbltrp\" Double Trap Extension, Version 1.0", + "line_range": [ + 14, + 14 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__priv__ssqosid.json b/tools/llm-extraction/data/output/raw_chunks/src__priv__ssqosid.json new file mode 100644 index 0000000000..0db840cdd3 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__priv__ssqosid.json @@ -0,0 +1,230 @@ +{ + "source_file": "src/priv/ssqosid.adoc", + "total": 28, + "sentences": [ + { + "text": "Quality of Service (QoS) is defined as the minimal end-to-end performance guaranteed in advance by a service level agreement (SLA) to a workload.", + "section": "Preamble > \"Ssqosid\" Extension for Quality-of-Service (QoS) Identifiers, Version 1.0", + "line_range": [ + 3, + 6 + ] + }, + { + "text": "Performance metrics might include measures such as instructions per cycle (IPC), latency of service, etc.", + "section": "Preamble > \"Ssqosid\" Extension for Quality-of-Service (QoS) Identifiers, Version 1.0", + "line_range": [ + 3, + 6 + ] + }, + { + "text": "When multiple workloads execute concurrently on modern processors—equipped with large core counts, multiple cache hierarchies, and multiple memory controllers— the performance of any given workload becomes less deterministic, or even non-deterministic, due to shared resource contention.", + "section": "Preamble > \"Ssqosid\" Extension for Quality-of-Service (QoS) Identifiers, Version 1.0", + "line_range": [ + 8, + 11 + ] + }, + { + "text": "To manage performance variability, system software needs resource allocation and monitoring capabilities.", + "section": "Preamble > \"Ssqosid\" Extension for Quality-of-Service (QoS) Identifiers, Version 1.0", + "line_range": [ + 13, + 19 + ] + }, + { + "text": "These capabilities allow for the reservation of resources like cache and bandwidth, thus meeting individual performance targets while minimizing interference.", + "section": "Preamble > \"Ssqosid\" Extension for Quality-of-Service (QoS) Identifiers, Version 1.0", + "line_range": [ + 13, + 19 + ] + }, + { + "text": "For resource management, hardware should provide monitoring features that allow system software to profile workload resource consumption and allocate resources accordingly.", + "section": "Preamble > \"Ssqosid\" Extension for Quality-of-Service (QoS) Identifiers, Version 1.0", + "line_range": [ + 13, + 19 + ] + }, + { + "text": "To facilitate this, the QoS Identifiers extension (Ssqosid) introduces the `srmcfg` register, which configures a hart with two identifiers: a Resource Control ID (`RCID`) and a Monitoring Counter ID (`MCID`).", + "section": "Preamble > \"Ssqosid\" Extension for Quality-of-Service (QoS) Identifiers, Version 1.0", + "line_range": [ + 21, + 24 + ] + }, + { + "text": "These identifiers accompany each request issued by the hart to shared resource controllers.", + "section": "Preamble > \"Ssqosid\" Extension for Quality-of-Service (QoS) Identifiers, Version 1.0", + "line_range": [ + 21, + 24 + ] + }, + { + "text": "Additional metadata, like the nature of the memory access and the ID of the originating supervisor domain, can accompany `RCID` and `MCID`.", + "section": "Preamble > \"Ssqosid\" Extension for Quality-of-Service (QoS) Identifiers, Version 1.0", + "line_range": [ + 26, + 31 + ] + }, + { + "text": "Resource controllers may use this metadata for differentiated service such as a different capacity allocation for code storage vs. data storage.", + "section": "Preamble > \"Ssqosid\" Extension for Quality-of-Service (QoS) Identifiers, Version 1.0", + "line_range": [ + 26, + 31 + ] + }, + { + "text": "Resource controllers can use this data for security policies such as not exposing statistics of one security domain to another.", + "section": "Preamble > \"Ssqosid\" Extension for Quality-of-Service (QoS) Identifiers, Version 1.0", + "line_range": [ + 26, + 31 + ] + }, + { + "text": "These identifiers are crucial for the RISC-V Capacity and Bandwidth Controller QoS Register Interface (CBQRI) specification, which provides methods for setting resource usage limits and monitoring resource consumption.", + "section": "Preamble > \"Ssqosid\" Extension for Quality-of-Service (QoS) Identifiers, Version 1.0", + "line_range": [ + 33, + 37 + ] + }, + { + "text": "The `RCID` controls resource allocations, while the `MCID` is used for tracking resource usage.", + "section": "Preamble > \"Ssqosid\" Extension for Quality-of-Service (QoS) Identifiers, Version 1.0", + "line_range": [ + 33, + 37 + ] + }, + { + "text": "NOTE: The Ssqosid extension does not require that S-mode mode be implemented.", + "section": "Preamble > \"Ssqosid\" Extension for Quality-of-Service (QoS) Identifiers, Version 1.0", + "line_range": [ + 39, + 39 + ] + }, + { + "text": "The `srmcfg` register is an SXLEN-bit read/write register used to configure a Resource Control ID (`RCID`) and a Monitoring Counter ID (`MCID`).", + "section": "Preamble > \"Ssqosid\" Extension for Quality-of-Service (QoS) Identifiers, Version 1.0 > Supervisor Resource Management Configuration (`srmcfg`) register", + "line_range": [ + 44, + 47 + ] + }, + { + "text": "Both `RCID` and `MCID` are WARL fields.", + "section": "Preamble > \"Ssqosid\" Extension for Quality-of-Service (QoS) Identifiers, Version 1.0 > Supervisor Resource Management Configuration (`srmcfg`) register", + "line_range": [ + 44, + 47 + ] + }, + { + "text": "The register is formatted as shown in when SXLEN=64 and when SXLEN=32.", + "section": "Preamble > \"Ssqosid\" Extension for Quality-of-Service (QoS) Identifiers, Version 1.0 > Supervisor Resource Management Configuration (`srmcfg`) register", + "line_range": [ + 44, + 47 + ] + }, + { + "text": "The `RCID` and `MCID` accompany each request made by the hart to shared resource controllers.", + "section": "Preamble > \"Ssqosid\" Extension for Quality-of-Service (QoS) Identifiers, Version 1.0 > Supervisor Resource Management Configuration (`srmcfg`) register", + "line_range": [ + 49, + 52 + ] + }, + { + "text": "The `RCID` is used to determine the resource allocations (e.g., cache occupancy limits, memory bandwidth limits, etc.) to enforce.", + "section": "Preamble > \"Ssqosid\" Extension for Quality-of-Service (QoS) Identifiers, Version 1.0 > Supervisor Resource Management Configuration (`srmcfg`) register", + "line_range": [ + 49, + 52 + ] + }, + { + "text": "The `MCID` is used to identify a counter to monitor resource usage.", + "section": "Preamble > \"Ssqosid\" Extension for Quality-of-Service (QoS) Identifiers, Version 1.0 > Supervisor Resource Management Configuration (`srmcfg`) register", + "line_range": [ + 49, + 52 + ] + }, + { + "text": ".Supervisor Resource Management Configuration (`srmcfg`) register for SXLEN=64", + "section": "Preamble > \"Ssqosid\" Extension for Quality-of-Service (QoS) Identifiers, Version 1.0 > Supervisor Resource Management Configuration (`srmcfg`) register", + "line_range": [ + 54, + 55 + ] + }, + { + "text": "[wavedrom, , ] .... {reg: [ {bits: 12, name: 'RCID'}, {bits: 4, name: 'WPRI'}, {bits: 12, name: 'MCID'}, {bits: 36, name: 'WPRI'}, ], config:{lanes: 2, hspace:1024}} ....", + "section": "Preamble > \"Ssqosid\" Extension for Quality-of-Service (QoS) Identifiers, Version 1.0 > Supervisor Resource Management Configuration (`srmcfg`) register", + "line_range": [ + 57, + 65 + ] + }, + { + "text": ".Supervisor Resource Management Configuration (`srmcfg`) register for SXLEN=32", + "section": "Preamble > \"Ssqosid\" Extension for Quality-of-Service (QoS) Identifiers, Version 1.0 > Supervisor Resource Management Configuration (`srmcfg`) register", + "line_range": [ + 67, + 68 + ] + }, + { + "text": "[wavedrom, , ] .... {reg: [ {bits: 12, name: 'RCID'}, {bits: 4, name: 'WPRI'}, {bits: 12, name: 'MCID'}, {bits: 4, name: 'WPRI'}, ], config:{lanes: 1, hspace:1024}} ....", + "section": "Preamble > \"Ssqosid\" Extension for Quality-of-Service (QoS) Identifiers, Version 1.0 > Supervisor Resource Management Configuration (`srmcfg`) register", + "line_range": [ + 70, + 78 + ] + }, + { + "text": "The `RCID` and `MCID` configured in the `srmcfg` CSR apply to all privilege modes of software execution on that hart by default, but this behavior may be overridden by future extensions.", + "section": "Preamble > \"Ssqosid\" Extension for Quality-of-Service (QoS) Identifiers, Version 1.0 > Supervisor Resource Management Configuration (`srmcfg`) register", + "line_range": [ + 80, + 82 + ] + }, + { + "text": "If extension Smstateen is implemented together with Ssqosid, then Ssqosid also requires the SRMCFG bit in `mstateen0` to be implemented.", + "section": "Preamble > \"Ssqosid\" Extension for Quality-of-Service (QoS) Identifiers, Version 1.0 > Supervisor Resource Management Configuration (`srmcfg`) register", + "line_range": [ + 84, + 89 + ] + }, + { + "text": "If `mstateen0`.SRMCFG is 0, attempts to access `srmcfg` in privilege modes less privileged than M-mode raise an illegal-instruction exception.", + "section": "Preamble > \"Ssqosid\" Extension for Quality-of-Service (QoS) Identifiers, Version 1.0 > Supervisor Resource Management Configuration (`srmcfg`) register", + "line_range": [ + 84, + 89 + ] + }, + { + "text": "If `mstateen0`.SRMCFG is 1 or if extension Smstateen is not implemented, attempts to access `srmcfg` when `V=1` raise a virtual-instruction exception.", + "section": "Preamble > \"Ssqosid\" Extension for Quality-of-Service (QoS) Identifiers, Version 1.0 > Supervisor Resource Management Configuration (`srmcfg`) register", + "line_range": [ + 84, + 89 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__priv__ssstrict.json b/tools/llm-extraction/data/output/raw_chunks/src__priv__ssstrict.json new file mode 100644 index 0000000000..098c9654ef --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__priv__ssstrict.json @@ -0,0 +1,22 @@ +{ + "source_file": "src/priv/ssstrict.adoc", + "total": 2, + "sentences": [ + { + "text": "If the Ssstrict extension is implemented, then no non-conforming extensions are present.", + "section": "Preamble > Ssstrict Extension for Extension Conformance, Version 1.0", + "line_range": [ + 3, + 8 + ] + }, + { + "text": "Furthermore, attempts to execute unimplemented opcodes or access unimplemented CSRs in the standard or reserved encoding spaces raises an illegal instruction exception that results in a contained trap to the supervisor-mode trap handler.", + "section": "Preamble > Ssstrict Extension for Extension Conformance, Version 1.0", + "line_range": [ + 3, + 8 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__priv__sstc.json b/tools/llm-extraction/data/output/raw_chunks/src__priv__sstc.json new file mode 100644 index 0000000000..1e2e571893 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__priv__sstc.json @@ -0,0 +1,62 @@ +{ + "source_file": "src/priv/sstc.adoc", + "total": 7, + "sentences": [ + { + "text": "The current Privileged arch specification only defines a hardware mechanism for generating machine-mode timer interrupts (based on the mtime and mtimecmp registers).", + "section": "Preamble > \"Sstc\" Extension for Supervisor-mode Timer Interrupts, Version 1.0", + "line_range": [ + 3, + 10 + ] + }, + { + "text": "With the resultant requirement that timer services for S-mode/HS-mode (and for VS-mode) have to all be provided by M-mode - via SBI calls from S/HS-mode up to M-mode (or VS-mode calls to HS-mode and then to M-mode). M-mode software then multiplexes these multiple logical timers onto its one physical M-mode timer facility, and the M-mode timer interrupt handler passes timer interrupts back down to the appropriate lower privilege mode.", + "section": "Preamble > \"Sstc\" Extension for Supervisor-mode Timer Interrupts, Version 1.0", + "line_range": [ + 3, + 10 + ] + }, + { + "text": "This extension serves to provide supervisor mode with its own CSR-based timer interrupt facility that it can directly manage to provide its own timer service (in the form of having its own `stimecmp` register) - thus eliminating the large overheads for emulating S/HS-mode timers and timer interrupt generation up in M-mode.", + "section": "Preamble > \"Sstc\" Extension for Supervisor-mode Timer Interrupts, Version 1.0", + "line_range": [ + 12, + 17 + ] + }, + { + "text": "Further, this extension adds a similar facility to the Hypervisor extension for VS-mode.", + "section": "Preamble > \"Sstc\" Extension for Supervisor-mode Timer Interrupts, Version 1.0", + "line_range": [ + 12, + 17 + ] + }, + { + "text": "The extension name is \"Sstc\" ('Ss' for Privileged arch and Supervisor-level extensions, and 'tc' for timecmp).", + "section": "Preamble > \"Sstc\" Extension for Supervisor-mode Timer Interrupts, Version 1.0", + "line_range": [ + 19, + 23 + ] + }, + { + "text": "This extension adds the S-level `stimecmp` CSR () and the VS-level `vstimecmp` CSR ().", + "section": "Preamble > \"Sstc\" Extension for Supervisor-mode Timer Interrupts, Version 1.0", + "line_range": [ + 19, + 23 + ] + }, + { + "text": "This extension adds the `STCE` bit to the `menvcfg` () and `henvcfg` () CSRs.", + "section": "Preamble > \"Sstc\" Extension for Supervisor-mode Timer Interrupts, Version 1.0", + "line_range": [ + 19, + 23 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__priv__sstvala.json b/tools/llm-extraction/data/output/raw_chunks/src__priv__sstvala.json new file mode 100644 index 0000000000..072724e929 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__priv__sstvala.json @@ -0,0 +1,22 @@ +{ + "source_file": "src/priv/sstvala.adoc", + "total": 2, + "sentences": [ + { + "text": "If the Sstvala extension is implemented, then `stval` must be written with the faulting virtual address for load, store, and instruction page-fault, access-fault, and misaligned exceptions, and for breakpoint exceptions that are defined to write an address to stval, other than those caused by execution of the `EBREAK` or `C.EBREAK` instructions.", + "section": "Preamble > Sstvala Extension for Trap Value Reporting, Version 1.0", + "line_range": [ + 3, + 9 + ] + }, + { + "text": "For virtual-instruction and illegal-instruction exceptions, `stval` must be written with the faulting instruction.", + "section": "Preamble > Sstvala Extension for Trap Value Reporting, Version 1.0", + "line_range": [ + 3, + 9 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__priv__sstvecd.json b/tools/llm-extraction/data/output/raw_chunks/src__priv__sstvecd.json new file mode 100644 index 0000000000..dc91a90058 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__priv__sstvecd.json @@ -0,0 +1,22 @@ +{ + "source_file": "src/priv/sstvecd.adoc", + "total": 2, + "sentences": [ + { + "text": "If the Sstvecd extension is implemented, then `stvec.MODE` must be capable of holding the value 0 (Direct).", + "section": "Preamble > Sstvecd Extension for Direct Trap Vectoring, Version 1.0", + "line_range": [ + 3, + 6 + ] + }, + { + "text": "Furthermore, when `stvec.MODE=Direct`, `stvec.BASE` must be capable of holding any valid four-byte-aligned address.", + "section": "Preamble > Sstvecd Extension for Direct Trap Vectoring, Version 1.0", + "line_range": [ + 3, + 6 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__priv__ssu64xl.json b/tools/llm-extraction/data/output/raw_chunks/src__priv__ssu64xl.json new file mode 100644 index 0000000000..c40a58ea53 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__priv__ssu64xl.json @@ -0,0 +1,14 @@ +{ + "source_file": "src/priv/ssu64xl.adoc", + "total": 1, + "sentences": [ + { + "text": "If the Ssu64xl extension is implemented, then `sstatus.UXL` must be capable of holding the value 2 (i.e., UXLEN=64 must be supported).", + "section": "Preamble > Ssu64xl Extension for UXLEN=64 Support, Version 1.0", + "line_range": [ + 3, + 4 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__priv__supervisor.json b/tools/llm-extraction/data/output/raw_chunks/src__priv__supervisor.json new file mode 100644 index 0000000000..d0e4fffb89 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__priv__supervisor.json @@ -0,0 +1,3230 @@ +{ + "source_file": "src/priv/supervisor.adoc", + "total": 403, + "sentences": [ + { + "text": "This chapter describes the RISC-V supervisor-level architecture, which contains a common core that is used with various supervisor-level address translation and protection schemes.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13", + "line_range": [ + 3, + 5 + ] + }, + { + "text": "A number of CSRs are provided for the supervisor.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs", + "line_range": [ + 9, + 9 + ] + }, + { + "text": "The `sstatus` register is an SXLEN-bit read/write register formatted as shown in when SXLEN=32 and when SXLEN=64.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register", + "line_range": [ + 14, + 18 + ] + }, + { + "text": "The `sstatus` register keeps track of the processor's current operating state.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register", + "line_range": [ + 14, + 18 + ] + }, + { + "text": ".Supervisor-mode status (`sstatus`) register when SXLEN=32. [wavedrom, ,svg] .... {reg: [ {bits: 1, name: 'WPRI'}, {bits: 1, name: 'SIE'}, {bits: 3, name: 'WPRI'}, {bits: 1, name: 'SPIE'}, {bits: 1, name: 'UBE'}, {bits: 1, name: 'WPRI'}, {bits: 1, name: 'SPP'}, {bits: 2, name: 'VS[1:0]'}, {bits: 2, name: 'WPRI'}, {bits: 2, name: 'FS[1:0]'}, {bits: 2, name: 'XS[1:0]'}, {bits: 1, name: 'WPRI'}, {bits: 1, name: 'SUM'}, {bits: 1, name: 'MXR'}, {bits: 3, name: 'WPRI'}, {bits: 1, name: 'SPELP'}, {bits: 1, name: 'SDT'}, {bits: 6, name: 'WPRI'}, {bits: 1, name: 'SD'}, ], config:{lanes: 2, hspace:1024}} ....", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register", + "line_range": [ + 20, + 45 + ] + }, + { + "text": ".Supervisor-mode status (`sstatus`) register when SXLEN=64. [wavedrom, ,svg] .... {reg: [ {bits: 1, name: 'WPRI'}, {bits: 1, name: 'SIE'}, {bits: 3, name: 'WPRI'}, {bits: 1, name: 'SPIE'}, {bits: 1, name: 'UBE'}, {bits: 1, name: 'WPRI'}, {bits: 1, name: 'SPP'}, {bits: 2, name: 'VS[1:0]'}, {bits: 2, name: 'WPRI'}, {bits: 2, name: 'FS[1:0]'}, {bits: 2, name: 'XS[1:0]'}, {bits: 1, name: 'WPRI'}, {bits: 1, name: 'SUM'}, {bits: 1, name: 'MXR'}, {bits: 3, name: 'WPRI'}, {bits: 1, name: 'SPELP'}, {bits: 1, name: 'SDT'}, {bits: 7, name: 'WPRI'}, {bits: 2, name: 'UXL[1:0]'}, {bits: 29, name: 'WPRI'}, {bits: 1, name: 'SD'}, ], config:{lanes: 4, hspace:1024}} ....", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register", + "line_range": [ + 47, + 74 + ] + }, + { + "text": "The SPP bit indicates the privilege level at which a hart was executing before entering supervisor mode.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register", + "line_range": [ + 76, + 83 + ] + }, + { + "text": "When a trap is taken, SPP is set to 0 if the trap originated from user mode, or 1 otherwise.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register", + "line_range": [ + 76, + 83 + ] + }, + { + "text": "When an SRET instruction (see ) is executed to return from the trap handler, the privilege level is set to user mode if the SPP bit is 0, or supervisor mode if the SPP bit is 1; SPP is then set to 0.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register", + "line_range": [ + 76, + 83 + ] + }, + { + "text": "The SIE bit enables or disables all interrupts in supervisor mode.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register", + "line_range": [ + 85, + 90 + ] + }, + { + "text": "When SIE is clear, interrupts are not taken while in supervisor mode.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register", + "line_range": [ + 85, + 90 + ] + }, + { + "text": "When the hart is running in user-mode, the value in SIE is ignored, and supervisor-level interrupts are enabled.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register", + "line_range": [ + 85, + 90 + ] + }, + { + "text": "The supervisor can disable individual interrupt sources using the `sie` CSR.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register", + "line_range": [ + 85, + 90 + ] + }, + { + "text": "The SPIE bit indicates whether supervisor interrupts were enabled prior to trapping into supervisor mode.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register", + "line_range": [ + 92, + 96 + ] + }, + { + "text": "When a trap is taken into supervisor mode, SPIE is set to SIE, and SIE is set to 0.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register", + "line_range": [ + 92, + 96 + ] + }, + { + "text": "When an SRET instruction is executed, SIE is set to SPIE, then SPIE is set to 1.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register", + "line_range": [ + 92, + 96 + ] + }, + { + "text": "The `sstatus` register is a subset of the `mstatus` register.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register", + "line_range": [ + 98, + 98 + ] + }, + { + "text": "The UXL field controls the value of XLEN for U-mode, termed UXLEN, which may differ from the value of XLEN for S-mode, termed SXLEN.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Base ISA Control in `sstatus` Register", + "line_range": [ + 102, + 106 + ] + }, + { + "text": "The encoding of UXL is the same as that of the MXL field of `misa`, shown in .", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Base ISA Control in `sstatus` Register", + "line_range": [ + 102, + 106 + ] + }, + { + "text": "When SXLEN=32, the UXL field does not exist, and UXLEN=32.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Base ISA Control in `sstatus` Register", + "line_range": [ + 108, + 112 + ] + }, + { + "text": "When SXLEN=64, it is a *WARL* field that encodes the current value of UXLEN.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Base ISA Control in `sstatus` Register", + "line_range": [ + 108, + 112 + ] + }, + { + "text": "In particular, an implementation may make UXL be a read-only field whose value always ensures that UXLEN=SXLEN.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Base ISA Control in `sstatus` Register", + "line_range": [ + 108, + 112 + ] + }, + { + "text": "If UXLEN!=SXLEN, instructions executed in the narrower mode must ignore source register operand bits above the configured XLEN, and must sign-extend results to fill the widest supported XLEN in the destination register.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Base ISA Control in `sstatus` Register", + "line_range": [ + 114, + 118 + ] + }, + { + "text": "If UXLEN < SXLEN, user-mode instruction-fetch addresses and load and store effective addresses are taken modulo 2^UXLEN^.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Base ISA Control in `sstatus` Register", + "line_range": [ + 120, + 123 + ] + }, + { + "text": "For example, when UXLEN=32 and SXLEN=64, user-mode memory accesses reference the lowest 4 GiB of the address space.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Base ISA Control in `sstatus` Register", + "line_range": [ + 120, + 123 + ] + }, + { + "text": "Some HINT instructions are encoded as integer computational instructions that overwrite their destination register with its current value, e.g., `c.addi x8, 0`.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Base ISA Control in `sstatus` Register", + "line_range": [ + 125, + 132 + ] + }, + { + "text": "When such a HINT is executed with XLEN < SXLEN and bits SXLEN..XLEN of the destination register not all equal to bit XLEN-1, it is implementation-defined whether bits SXLEN..XLEN of the destination register are unchanged or are overwritten with copies of bit XLEN-1.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Base ISA Control in `sstatus` Register", + "line_range": [ + 125, + 132 + ] + }, + { + "text": "NOTE: This definition allows implementations to elide register write-back for some HINTs, while allowing them to execute other HINTs in the same manner as other integer computational instructions.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Base ISA Control in `sstatus` Register", + "line_range": [ + 134, + 138 + ] + }, + { + "text": "The implementation choice is observable only by S-mode with SXLEN > UXLEN; it is invisible to U-mode.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Base ISA Control in `sstatus` Register", + "line_range": [ + 134, + 138 + ] + }, + { + "text": "The MXR (Make eXecutable Readable) bit modifies the privilege with which loads access virtual memory.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Memory Privilege in `sstatus` Register", + "line_range": [ + 143, + 149 + ] + }, + { + "text": "When MXR=0, only loads from pages marked readable (R=1 in ) will succeed.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Memory Privilege in `sstatus` Register", + "line_range": [ + 143, + 149 + ] + }, + { + "text": "When MXR=1, loads from pages marked either readable or executable (R=1 or X=1) will succeed. MXR has no effect when page-based virtual memory is not in effect.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Memory Privilege in `sstatus` Register", + "line_range": [ + 143, + 149 + ] + }, + { + "text": "The SUM (permit Supervisor User Memory access) bit modifies the privilege with which S-mode loads and stores access virtual memory.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Memory Privilege in `sstatus` Register", + "line_range": [ + 151, + 159 + ] + }, + { + "text": "When SUM=0, S-mode memory accesses to pages that are accessible by U-mode (U=1 in ) will fault.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Memory Privilege in `sstatus` Register", + "line_range": [ + 151, + 159 + ] + }, + { + "text": "When SUM=1, these accesses are permitted. SUM has no effect when page-based virtual memory is not in effect, nor when executing in U-mode.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Memory Privilege in `sstatus` Register", + "line_range": [ + 151, + 159 + ] + }, + { + "text": "Note that S-mode can never execute instructions from user pages, regardless of the state of SUM.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Memory Privilege in `sstatus` Register", + "line_range": [ + 151, + 159 + ] + }, + { + "text": "SUM is read-only 0 if `satp`.MODE is read-only 0.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Memory Privilege in `sstatus` Register", + "line_range": [ + 161, + 162 + ] + }, + { + "text": "The UBE bit is a *WARL* field that controls the endianness of explicit memory accesses made from U-mode, which may differ from the endianness of memory accesses in S-mode.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Endianness Control in `sstatus` Register", + "line_range": [ + 166, + 170 + ] + }, + { + "text": "An implementation may make UBE be a read-only field that always specifies the same endianness as for S-mode.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Endianness Control in `sstatus` Register", + "line_range": [ + 166, + 170 + ] + }, + { + "text": "UBE controls whether explicit load and store memory accesses made from U-mode are little-endian (UBE=0) or big-endian (UBE=1).", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Endianness Control in `sstatus` Register", + "line_range": [ + 172, + 173 + ] + }, + { + "text": "UBE has no effect on instruction fetches, which are implicit memory accesses that are always little-endian.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Endianness Control in `sstatus` Register", + "line_range": [ + 175, + 177 + ] + }, + { + "text": "For implicit accesses to supervisor-level memory management data structures, such as page tables, S-mode endianness always applies and UBE is ignored.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Endianness Control in `sstatus` Register", + "line_range": [ + 179, + 181 + ] + }, + { + "text": "Access to the `SPELP` field, added by Zicfilp, accesses the homonymous fields of `mstatus` when `V=0`, and the homonymous fields of `vsstatus` when `V=1`.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Previous Expected Landing Pad (ELP) State in `sstatus` Register", + "line_range": [ + 185, + 188 + ] + }, + { + "text": "The S-mode-disable-trap (`SDT`) bit is a WARL field introduced by the Ssdbltrp extension to address double trap (See ) at privilege modes lower than M.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Double Trap Control in `sstatus` Register", + "line_range": [ + 193, + 196 + ] + }, + { + "text": "When the `SDT` bit is set to 1 by an explicit CSR write, the `SIE` (Supervisor Interrupt Enable) bit is cleared to 0.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Double Trap Control in `sstatus` Register", + "line_range": [ + 198, + 203 + ] + }, + { + "text": "This clearing occurs regardless of the value written, if any, to the `SIE` bit by the same write.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Double Trap Control in `sstatus` Register", + "line_range": [ + 198, + 203 + ] + }, + { + "text": "The `SIE` bit can only be set to 1 by an explicit CSR write if the `SDT` bit is being set to 0 by the same write or is already 0.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Double Trap Control in `sstatus` Register", + "line_range": [ + 198, + 203 + ] + }, + { + "text": "When a trap is to be taken into S-mode, if the `SDT` bit is currently 0, it is then set to 1, and the trap is delivered as expected.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Double Trap Control in `sstatus` Register", + "line_range": [ + 205, + 214 + ] + }, + { + "text": "However, if `SDT` is already set to 1, then this is an unexpected trap.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Double Trap Control in `sstatus` Register", + "line_range": [ + 205, + 214 + ] + }, + { + "text": "In the event of an unexpected trap, a double-trap exception trap is delivered into M-mode.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Double Trap Control in `sstatus` Register", + "line_range": [ + 205, + 214 + ] + }, + { + "text": "To deliver this trap, the hart writes registers, except `mcause` and `mtval2`, with the same information that the unexpected trap would have written if it was taken into M-mode.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Double Trap Control in `sstatus` Register", + "line_range": [ + 205, + 214 + ] + }, + { + "text": "The `mtval2` register is then set to what would be otherwise written into the `mcause` register by the unexpected trap.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Double Trap Control in `sstatus` Register", + "line_range": [ + 205, + 214 + ] + }, + { + "text": "The `mcause` register is set to 16, the double-trap exception code.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Double Trap Control in `sstatus` Register", + "line_range": [ + 205, + 214 + ] + }, + { + "text": "An `SRET` instruction sets the `SDT` bit to 0.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Status (`sstatus`) Register > Double Trap Control in `sstatus` Register", + "line_range": [ + 216, + 217 + ] + }, + { + "text": "The `stvec` register is an SXLEN-bit read/write register that holds trap vector configuration, consisting of a vector base address (BASE) and a vector mode (MODE).", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Vector Base Address (`stvec`) Register", + "line_range": [ + 221, + 224 + ] + }, + { + "text": ".Supervisor trap vector base address (`stvec`) register. include::images/bytefield/stvec.edn[]", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Vector Base Address (`stvec`) Register", + "line_range": [ + 226, + 228 + ] + }, + { + "text": "The BASE field in `stvec` is a field that can hold any valid virtual or physical address, subject to the following alignment constraints: the address must be 4-byte aligned, and MODE settings other than Direct might impose additional alignment constraints on the value in the BASE field.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Vector Base Address (`stvec`) Register", + "line_range": [ + 230, + 239 + ] + }, + { + "text": "Note that the CSR contains only bits XLEN-1 through 2 of the address BASE.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Vector Base Address (`stvec`) Register", + "line_range": [ + 230, + 239 + ] + }, + { + "text": "When used as an address, the lower two bits are filled with zeroes to obtain an XLEN-bit address that is always aligned on a 4-byte boundary.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Vector Base Address (`stvec`) Register", + "line_range": [ + 230, + 239 + ] + }, + { + "text": ".Encoding of `stvec` MODE field. | |Value |Name |Description |0 + 1 + {ge}2 |Direct + Vectored |All exceptions set `pc` to BASE. + Asynchronous interrupts set `pc` to BASE+4{times}cause. + Reserved |", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Vector Base Address (`stvec`) Register", + "line_range": [ + 241, + 254 + ] + }, + { + "text": "The encoding of the MODE field is shown in .", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Vector Base Address (`stvec`) Register", + "line_range": [ + 256, + 265 + ] + }, + { + "text": "When MODE=Direct, all traps into supervisor mode cause the `pc` to be set to the address in the BASE field.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Vector Base Address (`stvec`) Register", + "line_range": [ + 256, + 265 + ] + }, + { + "text": "When MODE=Vectored, all synchronous exceptions into supervisor mode cause the `pc` to be set to the address in the BASE field, whereas interrupts cause the `pc` to be set to the address in the BASE field plus four times the interrupt cause number.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Vector Base Address (`stvec`) Register", + "line_range": [ + 256, + 265 + ] + }, + { + "text": "For example, a supervisor-mode timer interrupt (see ) causes the `pc` to be set to BASE+`0x14`.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Vector Base Address (`stvec`) Register", + "line_range": [ + 256, + 265 + ] + }, + { + "text": "Setting MODE=Vectored may impose a stricter alignment constraint on BASE.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Vector Base Address (`stvec`) Register", + "line_range": [ + 256, + 265 + ] + }, + { + "text": "The `sip` register is an SXLEN-bit read/write register containing information on pending interrupts, while `sie` is the corresponding SXLEN-bit read/write register containing interrupt enable bits.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers", + "line_range": [ + 269, + 276 + ] + }, + { + "text": "Interrupt cause number i (as reported in CSR `scause`, ) corresponds with bit i in both `sip` and `sie`.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers", + "line_range": [ + 269, + 276 + ] + }, + { + "text": "Bits 15:0 are allocated to standard interrupt causes only, while bits 16 and above are designated for platform use.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers", + "line_range": [ + 269, + 276 + ] + }, + { + "text": ".Supervisor interrupt-pending register (`sip`). include::images/bytefield/sip.edn[]", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers", + "line_range": [ + 278, + 279 + ] + }, + { + "text": ".Supervisor interrupt-enable register (`sie`). include::images/bytefield/sie.edn[]", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers", + "line_range": [ + 281, + 282 + ] + }, + { + "text": "An interrupt i will trap to S-mode if both of the following are true: (a) either the current privilege mode is S and the SIE bit in the `sstatus` register is set, or the current privilege mode has less privilege than S-mode; and (b) bit i is set in both `sip` and `sie`.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers", + "line_range": [ + 284, + 288 + ] + }, + { + "text": "These conditions for an interrupt trap to occur must be evaluated in a bounded amount of time from when an interrupt becomes, or ceases to be, pending in `sip`, and must also be evaluated immediately following the execution of an SRET instruction or an explicit write to a CSR on which these interrupt trap conditions expressly depend (including `sip`, `sie` and `sstatus`).", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers", + "line_range": [ + 290, + 296 + ] + }, + { + "text": "Interrupts to S-mode take priority over any interrupts to lower privilege modes.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers", + "line_range": [ + 298, + 300 + ] + }, + { + "text": "Each individual bit in register `sip` may be writable or may be read-only.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers", + "line_range": [ + 302, + 307 + ] + }, + { + "text": "When bit i in `sip` is writable, a pending interrupt i can be cleared by writing 0 to this bit.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers", + "line_range": [ + 302, + 307 + ] + }, + { + "text": "If interrupt i can become pending but bit i in `sip` is read-only, the implementation must provide some other mechanism for clearing the pending interrupt (which may involve a call to the execution environment).", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers", + "line_range": [ + 302, + 307 + ] + }, + { + "text": "A bit in `sie` must be writable if the corresponding interrupt can ever become pending.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers", + "line_range": [ + 309, + 310 + ] + }, + { + "text": "Bits of `sie` that are not writable are read-only zero.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers", + "line_range": [ + 309, + 310 + ] + }, + { + "text": "The standard portions (bits 15:0) of registers `sip` and `sie` are formatted as shown in Figures and respectively.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers", + "line_range": [ + 312, + 315 + ] + }, + { + "text": ".Standard portion (bits 15:0) of `sip`. include::images/bytefield/sipreg-standard.edn[]", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers", + "line_range": [ + 317, + 319 + ] + }, + { + "text": ".Standard portion (bits 15:0) of `sie`. include::images/bytefield/siereg-standard.edn[]", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers", + "line_range": [ + 321, + 323 + ] + }, + { + "text": "Bits `sip`.SEIP and `sie`.SEIE are the interrupt-pending and interrupt-enable bits for supervisor-level external interrupts.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers", + "line_range": [ + 325, + 330 + ] + }, + { + "text": "If implemented, SEIP is read-only in `sip`, and is set and cleared by the execution environment, typically through a platform-specific interrupt controller.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers", + "line_range": [ + 325, + 330 + ] + }, + { + "text": "Bits `sip`.STIP and `sie`.STIE are the interrupt-pending and interrupt-enable bits for supervisor-level timer interrupts.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers", + "line_range": [ + 332, + 340 + ] + }, + { + "text": "If implemented, STIP is read-only in `sip`.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers", + "line_range": [ + 332, + 340 + ] + }, + { + "text": "When the Sstc extension is not implemented, STIP is set and cleared by the execution environment.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers", + "line_range": [ + 332, + 340 + ] + }, + { + "text": "When the Sstc extension is implemented, STIP reflects the timer interrupt signal resulting from `stimecmp`.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers", + "line_range": [ + 332, + 340 + ] + }, + { + "text": "The `sip`.STIP bit, in response to timer interrupts generated by `stimecmp`, is set by writing `stimecmp` with a value that is less than or equal to `time`, and is cleared by writing `stimecmp` with a value greater than `time`.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers", + "line_range": [ + 332, + 340 + ] + }, + { + "text": "Bits `sip`.SSIP and `sie`.SSIE are the interrupt-pending and interrupt-enable bits for supervisor-level software interrupts.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers", + "line_range": [ + 342, + 346 + ] + }, + { + "text": "If implemented, SSIP is writable in `sip` and may also be set to 1 by a platform-specific interrupt controller.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers", + "line_range": [ + 342, + 346 + ] + }, + { + "text": "If the Sscofpmf extension is implemented, bits `sip`.LCOFIP and `sie`.LCOFIE are the interrupt-pending and interrupt-enable bits for local-counter-overflow interrupts. LCOFIP is read-write in `sip` and reflects the occurrence of a local counter-overflow overflow interrupt request resulting from any of the `mhpmeventn`.OF bits being set.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers", + "line_range": [ + 348, + 356 + ] + }, + { + "text": "If the Sscofpmf extension is not implemented, `sip`.LCOFIP and `sie`.LCOFIE are read-only zeros.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers", + "line_range": [ + 348, + 356 + ] + }, + { + "text": "Each standard interrupt type (SEI, STI, SSI, or LCOFI) may not be implemented, in which case the corresponding interrupt-pending and interrupt-enable bits are read-only zeros.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers", + "line_range": [ + 358, + 363 + ] + }, + { + "text": "All bits in `sip` and `sie` are *WARL* fields.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers", + "line_range": [ + 358, + 363 + ] + }, + { + "text": "The implemented interrupts may be found by writing one to every bit location in `sie`, then reading back to see which bit positions hold a one.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers", + "line_range": [ + 358, + 363 + ] + }, + { + "text": "Multiple simultaneous interrupts destined for supervisor mode are handled in the following decreasing priority order: SEI, SSI, STI, LCOFI.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Interrupt (`sip` and `sie`) Registers", + "line_range": [ + 365, + 367 + ] + }, + { + "text": "Supervisor software uses the same hardware performance monitoring facility as user-mode software, including the `time`, `cycle`, and `instret` CSRs.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Timers and Performance Counters", + "line_range": [ + 372, + 375 + ] + }, + { + "text": "The implementation should provide a mechanism to modify the counter values.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Timers and Performance Counters", + "line_range": [ + 372, + 375 + ] + }, + { + "text": "The implementation must provide a facility for scheduling timer interrupts in terms of the real-time counter, `time`.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Timers and Performance Counters", + "line_range": [ + 377, + 379 + ] + }, + { + "text": ".Counter-enable (`scounteren`) register include::images/bytefield/scounteren.edn[]", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Counter-Enable (`scounteren`) Register", + "line_range": [ + 383, + 384 + ] + }, + { + "text": "The counter-enable (`scounteren`) CSR is a 32-bit register that controls the availability of the hardware performance monitoring counters to U-mode.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Counter-Enable (`scounteren`) Register", + "line_range": [ + 386, + 389 + ] + }, + { + "text": "When the CY, TM, IR, or HPMn bit in the `scounteren` register is clear, attempts to read the `cycle`, `time`, `instret`, or `hpmcountern` register while executing in U-mode will cause an illegal-instruction exception.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Counter-Enable (`scounteren`) Register", + "line_range": [ + 391, + 396 + ] + }, + { + "text": "When one of these bits is set, access to the corresponding register is permitted.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Counter-Enable (`scounteren`) Register", + "line_range": [ + 391, + 396 + ] + }, + { + "text": "`scounteren` must be implemented.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Counter-Enable (`scounteren`) Register", + "line_range": [ + 398, + 402 + ] + }, + { + "text": "However, any of the bits may be read-only zero, indicating reads to the corresponding counter will cause an exception when executing in U-mode.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Counter-Enable (`scounteren`) Register", + "line_range": [ + 398, + 402 + ] + }, + { + "text": "Hence, they are effectively *WARL* fields.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Counter-Enable (`scounteren`) Register", + "line_range": [ + 398, + 402 + ] + }, + { + "text": "The `sscratch` CSR is an SXLEN-bit read/write register, dedicated for use by the supervisor.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Scratch (`sscratch`) Register", + "line_range": [ + 406, + 413 + ] + }, + { + "text": "Typically, `sscratch` is used to hold a pointer to the hart-local supervisor context while the hart is executing user code.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Scratch (`sscratch`) Register", + "line_range": [ + 406, + 413 + ] + }, + { + "text": "At the beginning of a trap handler, software normally uses a CSRRW instruction to swap `sscratch` with an integer register to obtain an initial working register.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Scratch (`sscratch`) Register", + "line_range": [ + 406, + 413 + ] + }, + { + "text": ".Supervisor Scratch Register include::images/bytefield/sscratch.edn[]", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Scratch (`sscratch`) Register", + "line_range": [ + 415, + 416 + ] + }, + { + "text": "`sepc` is an SXLEN-bit read/write CSR formatted as shown in .", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Exception Program Counter (`sepc`) Register", + "line_range": [ + 420, + 422 + ] + }, + { + "text": "The low bit of `sepc` (`sepc[0]`) is always zero.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Exception Program Counter (`sepc`) Register", + "line_range": [ + 420, + 422 + ] + }, + { + "text": "On implementations that support only IALIGN=32, the two low bits (`sepc[1:0]`) are always zero.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Exception Program Counter (`sepc`) Register", + "line_range": [ + 420, + 422 + ] + }, + { + "text": "If an implementation allows IALIGN to be either 16 or 32 (by changing CSR `misa`, for example), then, whenever IALIGN=32, bit `sepc[1]` is masked on reads so that it appears to be 0.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Exception Program Counter (`sepc`) Register", + "line_range": [ + 424, + 429 + ] + }, + { + "text": "This masking occurs also for the implicit read by the SRET instruction.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Exception Program Counter (`sepc`) Register", + "line_range": [ + 424, + 429 + ] + }, + { + "text": "Though masked, `sepc[1]` remains writable when IALIGN=32.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Exception Program Counter (`sepc`) Register", + "line_range": [ + 424, + 429 + ] + }, + { + "text": "`sepc` is a *WARL* register that must be able to hold all valid virtual addresses.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Exception Program Counter (`sepc`) Register", + "line_range": [ + 431, + 436 + ] + }, + { + "text": "It need not be capable of holding all possible invalid addresses.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Exception Program Counter (`sepc`) Register", + "line_range": [ + 431, + 436 + ] + }, + { + "text": "Prior to writing `sepc`, implementations may convert an invalid address into some other invalid address that `sepc` is capable of holding.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Exception Program Counter (`sepc`) Register", + "line_range": [ + 431, + 436 + ] + }, + { + "text": "When a trap is taken into S-mode, `sepc` is written with the virtual address of the instruction that was interrupted or that encountered the exception.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Exception Program Counter (`sepc`) Register", + "line_range": [ + 438, + 442 + ] + }, + { + "text": "Otherwise, `sepc` is never written by the implementation, though it may be explicitly written by software.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Exception Program Counter (`sepc`) Register", + "line_range": [ + 438, + 442 + ] + }, + { + "text": ".Supervisor exception program counter register. include::images/bytefield/epcreg.edn[]", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Exception Program Counter (`sepc`) Register", + "line_range": [ + 444, + 446 + ] + }, + { + "text": "The `scause` CSR is an SXLEN-bit read-write register formatted as shown in .", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Cause (`scause`) Register", + "line_range": [ + 451, + 456 + ] + }, + { + "text": "When a trap is taken into S-mode, `scause` is written with a code indicating the event that caused the trap.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Cause (`scause`) Register", + "line_range": [ + 451, + 456 + ] + }, + { + "text": "Otherwise, `scause` is never written by the implementation, though it may be explicitly written by software.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Cause (`scause`) Register", + "line_range": [ + 451, + 456 + ] + }, + { + "text": "The Interrupt bit in the `scause` register is set if the trap was caused by an interrupt.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Cause (`scause`) Register", + "line_range": [ + 458, + 465 + ] + }, + { + "text": "The Exception Code field contains a code identifying the last exception or interrupt. lists the possible exception codes for the current supervisor ISAs.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Cause (`scause`) Register", + "line_range": [ + 458, + 465 + ] + }, + { + "text": "The Exception Code is a *WLRL* field.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Cause (`scause`) Register", + "line_range": [ + 458, + 465 + ] + }, + { + "text": "It is required to hold the values 0–31 (i.e., bits 4–0 must be implemented), but otherwise it is only guaranteed to hold supported exception codes.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Cause (`scause`) Register", + "line_range": [ + 458, + 465 + ] + }, + { + "text": ".Supervisor Cause (`scause`) register. include::images/bytefield/scausereg.edn[]", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Cause (`scause`) Register", + "line_range": [ + 467, + 469 + ] + }, + { + "text": ".Supervisor cause (`scause`) register values after trap.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Cause (`scause`) Register", + "line_range": [ + 471, + 505 + ] + }, + { + "text": "Synchronous exception priorities are given by . | |Interrupt |Exception Code |Description |1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 |0 + 1 + 2-4 + 5 + 6-8 + 9 + 10-12 + 13 + 14-15 + {ge}16 |Reserved + Supervisor software interrupt + Reserved + Supervisor timer interrupt + Reserved + Supervisor external interrupt + Reserved + Counter-overflow interrupt + Reserved + Designated for platform use", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Cause (`scause`) Register", + "line_range": [ + 471, + 505 + ] + }, + { + "text": "|0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 |0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10-11 + 12 + 13 + 14 + 15 + 16-17 + 18 + 19 + 20-23 + 24-31 + 32-47 + 48-63 + {ge}64 |Instruction address misaligned + Instruction access fault + Illegal instruction + Breakpoint + Load address misaligned + Load access fault + Store/AMO address misaligned + Store/AMO access fault + Environment call from U-mode + Environment call from S-mode + Reserved + Instruction page fault + Load page fault + Reserved + Store/AMO page fault + Reserved + Software check + Hardware error + Reserved + Designated for custom use + Reserved + Designated for custom use + Reserved |", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Cause (`scause`) Register", + "line_range": [ + 507, + 576 + ] + }, + { + "text": "The `stval` CSR is an SXLEN-bit read-write register formatted as shown in .", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Value (`stval`) Register", + "line_range": [ + 580, + 589 + ] + }, + { + "text": "When a trap is taken into S-mode, `stval` is written with exception-specific information to assist software in handling the trap.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Value (`stval`) Register", + "line_range": [ + 580, + 589 + ] + }, + { + "text": "Otherwise, `stval` is never written by the implementation, though it may be explicitly written by software.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Value (`stval`) Register", + "line_range": [ + 580, + 589 + ] + }, + { + "text": "The hardware platform will specify which exceptions must set `stval` informatively, which may unconditionally set it to zero, and which may exhibit either behavior, depending on the underlying event that caused the exception.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Value (`stval`) Register", + "line_range": [ + 580, + 589 + ] + }, + { + "text": "If `stval` is written with a nonzero value when a breakpoint, address-misaligned, access-fault, page-fault, or hardware-error exception occurs on an instruction fetch, load, or store, then `stval` will contain the faulting virtual address.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Value (`stval`) Register", + "line_range": [ + 591, + 596 + ] + }, + { + "text": "On a breakpoint exception raised by an EBREAK or C.EBREAK instruction, `stval` is written with either zero or the virtual address of the instruction.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Value (`stval`) Register", + "line_range": [ + 598, + 600 + ] + }, + { + "text": ".Supervisor Trap Value register. include::images/bytefield/stvalreg.edn[]", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Value (`stval`) Register", + "line_range": [ + 602, + 604 + ] + }, + { + "text": "If `stval` is written with a nonzero value when a misaligned load or store causes an access-fault, page-fault, or hardware-error exception, then `stval` will contain the virtual address of the portion of the access that caused the fault.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Value (`stval`) Register", + "line_range": [ + 606, + 611 + ] + }, + { + "text": "If `stval` is written with a nonzero value when an instruction access-fault, page-fault, or hardware-error exception occurs on a hart with variable-length instructions, then `stval` will contain the virtual address of the portion of the instruction that caused the fault, while `sepc` will point to the beginning of the instruction.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Value (`stval`) Register", + "line_range": [ + 613, + 618 + ] + }, + { + "text": "The `stval` register can optionally also be used to return the faulting instruction bits on an illegal-instruction exception (`sepc` points to the faulting instruction in memory).", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Value (`stval`) Register", + "line_range": [ + 620, + 625 + ] + }, + { + "text": "If `stval` is written with a nonzero value when an illegal-instruction exception occurs, then `stval` will contain the shortest of:", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Value (`stval`) Register", + "line_range": [ + 620, + 625 + ] + }, + { + "text": "the actual faulting instruction * the first ILEN bits of the faulting instruction * the first SXLEN bits of the faulting instruction", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Value (`stval`) Register", + "line_range": [ + 627, + 629 + ] + }, + { + "text": "The value loaded into `stval` on an illegal-instruction exception is right-justified and all unused upper bits are cleared to zero.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Value (`stval`) Register", + "line_range": [ + 631, + 633 + ] + }, + { + "text": "On a trap caused by a software-check exception, the `stval` register holds the cause for the exception.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Value (`stval`) Register", + "line_range": [ + 635, + 637 + ] + }, + { + "text": "The following encodings are defined:", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Value (`stval`) Register", + "line_range": [ + 635, + 637 + ] + }, + { + "text": "0 - No information provided. * 2 - Landing Pad Fault.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Value (`stval`) Register", + "line_range": [ + 639, + 641 + ] + }, + { + "text": "Defined by the Zicfilp extension (). * 3 - Shadow Stack Fault.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Value (`stval`) Register", + "line_range": [ + 639, + 641 + ] + }, + { + "text": "Defined by the Zicfiss extension ().", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Value (`stval`) Register", + "line_range": [ + 639, + 641 + ] + }, + { + "text": "For other traps, `stval` is set to zero, but a future standard may redefine `stval`’s setting for other traps.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Value (`stval`) Register", + "line_range": [ + 643, + 645 + ] + }, + { + "text": "`stval` is a *WARL* register that must be able to hold all valid virtual addresses and the value 0.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Value (`stval`) Register", + "line_range": [ + 647, + 655 + ] + }, + { + "text": "It need not be capable of holding all possible invalid addresses.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Value (`stval`) Register", + "line_range": [ + 647, + 655 + ] + }, + { + "text": "Prior to writing `stval`, implementations may convert an invalid address into some other invalid address that `stval` is capable of holding.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Value (`stval`) Register", + "line_range": [ + 647, + 655 + ] + }, + { + "text": "If the feature to return the faulting instruction bits is implemented, `stval` must also be able to hold all values less than 2^N^, where N is the smaller of SXLEN and ILEN.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Trap Value (`stval`) Register", + "line_range": [ + 647, + 655 + ] + }, + { + "text": "The `senvcfg` CSR is an SXLEN-bit read/write register, formatted as shown in , that controls certain characteristics of the U-mode execution environment.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register", + "line_range": [ + 660, + 663 + ] + }, + { + "text": ".Supervisor environment configuration register (`senvcfg`) for RV64. [wavedrom, ,svg] .... {reg: [ {bits: 1, name: 'FIOM'}, {bits: 1, name: 'WPRI'}, {bits: 1, name: 'LPE'}, {bits: 1, name: 'SSE'}, {bits: 2, name: 'CBIE'}, {bits: 1, name: 'CBCFE'}, {bits: 1, name: 'CBZE'}, {bits: 24, name: 'WPRI'}, {bits: 2, name: 'PMM'}, {bits: 30, name: 'WPRI'}, ], config:{lanes: 4, hspace:1024}} ....", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register", + "line_range": [ + 665, + 681 + ] + }, + { + "text": ".Supervisor environment configuration register (`senvcfg`) for RV32. [wavedrom, ,svg] .... {reg: [ {bits: 1, name: 'FIOM'}, {bits: 1, name: 'WPRI'}, {bits: 1, name: 'LPE'}, {bits: 1, name: 'SSE'}, {bits: 2, name: 'CBIE'}, {bits: 1, name: 'CBCFE'}, {bits: 1, name: 'CBZE'}, {bits: 24, name: 'WPRI'}, ], config:{lanes: 2, hspace:1024}} ....", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register", + "line_range": [ + 683, + 696 + ] + }, + { + "text": "If bit FIOM (Fence of I/O implies Memory) is set to one in `senvcfg`, FENCE instructions executed in U-mode are modified so the requirement to order accesses to device I/O implies also the requirement to order main memory accesses. details the modified interpretation of FENCE instruction bits PI, PO, SI, and SO in U-mode when FIOM=1.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register", + "line_range": [ + 698, + 704 + ] + }, + { + "text": "Similarly, for U-mode when FIOM=1, if an atomic instruction that accesses a region ordered as device I/O has its aq and/or rl bit set, then that instruction is ordered as though it accesses both device I/O and memory.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register", + "line_range": [ + 706, + 710 + ] + }, + { + "text": "If `satp`.MODE is read-only zero (always Bare), the implementation may make FIOM read-only zero.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register", + "line_range": [ + 712, + 714 + ] + }, + { + "text": ".Modified interpretation of FENCE predecessor and successor sets in U-mode when FIOM=1. | |Instruction bit |Meaning when set |PI + PO |Predecessor device input and memory reads (PR implied) + Predecessor device output and memory writes (PW implied) |SI + SO |Successor device input and memory reads (SR implied) + Successor device output and memory writes (SW implied) |", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register", + "line_range": [ + 716, + 729 + ] + }, + { + "text": "The Zicboz extension adds the `CBZE` (Cache Block Zero instruction enable) field to `senvcfg`.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register", + "line_range": [ + 731, + 737 + ] + }, + { + "text": "The `CBZE` field controls execution of the cache block zero instruction (`CBO.ZERO`) in U-mode.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register", + "line_range": [ + 731, + 737 + ] + }, + { + "text": "Execution of `CBO.ZERO` in U-mode is enabled only if execution of the instruction is enabled for use in S-mode and `CBZE` is set to 1; otherwise, an illegal-instruction exception is raised.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register", + "line_range": [ + 731, + 737 + ] + }, + { + "text": "When the Zicboz extension is not implemented, `CBZE` is read-only zero.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register", + "line_range": [ + 731, + 737 + ] + }, + { + "text": "The Zicbom extension adds the `CBCFE` (Cache Block Clean and Flush instruction Enable) field to `senvcfg` to control execution of the `CBO.CLEAN` and `CBO.FLUSH` instructions in U-mode.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register", + "line_range": [ + 739, + 745 + ] + }, + { + "text": "Execution of these instructions in U-mode is enabled only if execution of these instructions is enabled for use in S-mode and `CBCFE` is set to 1; otherwise, an illegal-instruction exception is raised.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register", + "line_range": [ + 739, + 745 + ] + }, + { + "text": "When the Zicbom extension is not implemented, `CBCFE` is read-only zero.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register", + "line_range": [ + 739, + 745 + ] + }, + { + "text": "The Zicbom extension adds the `CBIE` (Cache Block Invalidate instruction Enable) WARL field to `senvcfg` to control execution of the `CBO.INVAL` instruction in U-mode.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register", + "line_range": [ + 747, + 754 + ] + }, + { + "text": "The encoding `10b` is reserved.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register", + "line_range": [ + 747, + 754 + ] + }, + { + "text": "When the Zicbom extension is not implemented, `CBIE` is read-only zero.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register", + "line_range": [ + 747, + 754 + ] + }, + { + "text": "Execution of `CBO.INVAL` in U-mode is enabled only if execution of the instruction is enabled for use in S-mode and `CBIE` is set to `01b` or `11b`; otherwise, an illegal-instruction exception is raised.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register", + "line_range": [ + 747, + 754 + ] + }, + { + "text": "If `CBO.INVAL` is enabled in S-mode to perform a flush operation, then when the instruction is enabled in U-mode it performs a flush operation, even if `CBIE` is set to `11b`.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register", + "line_range": [ + 756, + 759 + ] + }, + { + "text": "Otherwise, the instruction behaves as follows, depending on the `CBIE` encoding:", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register", + "line_range": [ + 756, + 759 + ] + }, + { + "text": "`01b` -- The instruction is executed and performs a flush operation. * `11b` -- The instruction is executed and performs an invalidate operation.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register", + "line_range": [ + 761, + 762 + ] + }, + { + "text": "If the Ssnpm extension is implemented, the `PMM` field enables or disables pointer masking (see ) for the next-lower privilege mode (U/VU), according to the values in .", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register", + "line_range": [ + 764, + 769 + ] + }, + { + "text": "If Ssnpm is not implemented, `PMM` is read-only zero.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register", + "line_range": [ + 764, + 769 + ] + }, + { + "text": "The `PMM` field is read-only zero for RV32.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register", + "line_range": [ + 764, + 769 + ] + }, + { + "text": ".Legal values of `PMM` WARL field | |Value|Description |00|Pointer masking is disabled (PMLEN = 0) |01|Reserved |10|Pointer masking is enabled with PMLEN = XLEN - 57 (PMLEN = 7 on RV64) |11|Pointer masking is enabled with PMLEN = XLEN - 48 (PMLEN = 16 on RV64) |", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register", + "line_range": [ + 773, + 781 + ] + }, + { + "text": "The Zicfilp extension adds the `LPE` field in `senvcfg`.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register", + "line_range": [ + 783, + 787 + ] + }, + { + "text": "When the `LPE` field is set to 1, the Zicfilp extension is enabled in VU/U-mode.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register", + "line_range": [ + 783, + 787 + ] + }, + { + "text": "When the `LPE` field is 0, the Zicfilp extension is not enabled in VU/U-mode and the following rules apply to VU/U-mode:", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register", + "line_range": [ + 783, + 787 + ] + }, + { + "text": "The hart does not update the `ELP` state; it remains as `NOLPEXPECTED`. * The `LPAD` instruction operates as a no-op.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register", + "line_range": [ + 789, + 790 + ] + }, + { + "text": "The Zicfiss extension adds the `SSE` field in `senvcfg`.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register", + "line_range": [ + 792, + 796 + ] + }, + { + "text": "When the `SSE` field is set to 1, the Zicfiss extension is activated in VU/U-mode.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register", + "line_range": [ + 792, + 796 + ] + }, + { + "text": "When the `SSE` field is 0, the Zicfiss extension remains inactive in VU/U-mode, and the following rules apply:", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register", + "line_range": [ + 792, + 796 + ] + }, + { + "text": "32-bit Zicfiss instructions will revert to their behavior as defined by Zimop. * 16-bit Zicfiss instructions will revert to their behavior as defined by Zcmop. *", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register", + "line_range": [ + 798, + 801 + ] + }, + { + "text": "When `menvcfg.SSE` is one, `SSAMOSWAP.W/D` raises an illegal-instruction exception in U-mode and a virtual-instruction exception in VU-mode.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Environment Configuration (`senvcfg`) Register", + "line_range": [ + 798, + 801 + ] + }, + { + "text": "The `satp` CSR is an SXLEN-bit read/write register, formatted as shown in for SXLEN=32 and for SXLEN=64, which controls supervisor-mode address translation and protection.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Address Translation and Protection (`satp`) Register", + "line_range": [ + 806, + 816 + ] + }, + { + "text": "This register holds the physical page number (PPN) of the root page table, i.e., its supervisor physical address divided by 4 KiB; an address space identifier (ASID), which facilitates address-translation fences on a per-address-space basis; and the MODE field, which selects the current address-translation scheme.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Address Translation and Protection (`satp`) Register", + "line_range": [ + 806, + 816 + ] + }, + { + "text": "Further details on the access to this register are described in .", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Address Translation and Protection (`satp`) Register", + "line_range": [ + 806, + 816 + ] + }, + { + "text": ".Supervisor address translation and protection (`satp`) register when SXLEN=32. include::images/bytefield/rv32satp.edn[]", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Address Translation and Protection (`satp`) Register", + "line_range": [ + 818, + 820 + ] + }, + { + "text": ".Supervisor address translation and protection (`satp`) register when SXLEN=64, for MODE values Bare, Sv39, Sv48, and Sv57. include::images/bytefield/rv64satp.edn[]", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Address Translation and Protection (`satp`) Register", + "line_range": [ + 822, + 824 + ] + }, + { + "text": "shows the encodings of the MODE field when SXLEN=32 and SXLEN=64.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Address Translation and Protection (`satp`) Register", + "line_range": [ + 826, + 836 + ] + }, + { + "text": "When MODE=Bare, supervisor virtual addresses are equal to supervisor physical addresses, and there is no additional memory protection beyond the physical memory protection scheme described in .", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Address Translation and Protection (`satp`) Register", + "line_range": [ + 826, + 836 + ] + }, + { + "text": "To select MODE=Bare, software must write zero to the remaining fields of `satp` (bits 30–0 when SXLEN=32, or bits 59–0 when SXLEN=64).", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Address Translation and Protection (`satp`) Register", + "line_range": [ + 826, + 836 + ] + }, + { + "text": "Attempting to select MODE=Bare with a nonzero pattern in the remaining fields has an UNSPECIFIED effect on the value that the remaining fields assume and an UNSPECIFIED effect on address translation and protection behavior.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Address Translation and Protection (`satp`) Register", + "line_range": [ + 826, + 836 + ] + }, + { + "text": "When SXLEN=32, the `satp` encodings corresponding to MODE=Bare and ASID[8:7]=3 are designated for custom use, whereas the encodings corresponding to MODE=Bare and ASID[8:7]!=3 are reserved for future standard use.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Address Translation and Protection (`satp`) Register", + "line_range": [ + 838, + 842 + ] + }, + { + "text": "When SXLEN=64, all `satp` encodings corresponding to MODE=Bare are reserved for future standard use.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Address Translation and Protection (`satp`) Register", + "line_range": [ + 838, + 842 + ] + }, + { + "text": "If an implementation supports the Svbare extension, then the `satp` register's MODE field must be capable of holding the value Bare.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Address Translation and Protection (`satp`) Register", + "line_range": [ + 844, + 846 + ] + }, + { + "text": "When SXLEN=32, the only other valid setting for MODE is Sv32, a paged virtual-memory scheme described in .", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Address Translation and Protection (`satp`) Register", + "line_range": [ + 848, + 850 + ] + }, + { + "text": "When SXLEN=64, three paged virtual-memory schemes are defined: Sv39, Sv48, and Sv57, described in , , and , respectively.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Address Translation and Protection (`satp`) Register", + "line_range": [ + 852, + 858 + ] + }, + { + "text": "One additional scheme, Sv64, will be defined in a later version of this specification.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Address Translation and Protection (`satp`) Register", + "line_range": [ + 852, + 858 + ] + }, + { + "text": "The remaining MODE settings are reserved for future use and may define different interpretations of the other fields in `satp`.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Address Translation and Protection (`satp`) Register", + "line_range": [ + 852, + 858 + ] + }, + { + "text": "Implementations are not required to support all MODE settings, and if `satp` is written with an unsupported MODE, the entire write has no effect; no fields in `satp` are modified.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Address Translation and Protection (`satp`) Register", + "line_range": [ + 860, + 863 + ] + }, + { + "text": "The number of ASID bits is UNSPECIFIED and may be zero.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Address Translation and Protection (`satp`) Register", + "line_range": [ + 865, + 873 + ] + }, + { + "text": "The number of implemented ASID bits, termed ASIDLEN, may be determined by writing one to every bit position in the ASID field, then reading back the value in `satp` to see which bit positions in the ASID field hold a one.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Address Translation and Protection (`satp`) Register", + "line_range": [ + 865, + 873 + ] + }, + { + "text": "The least-significant bits of ASID are implemented first: that is, if ASIDLEN > 0, ASID[ASIDLEN-1:0] is writable.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Address Translation and Protection (`satp`) Register", + "line_range": [ + 865, + 873 + ] + }, + { + "text": "The maximal value of ASIDLEN, termed ASIDMAX, is 9 for Sv32 or 16 for Sv39, Sv48, and Sv57.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Address Translation and Protection (`satp`) Register", + "line_range": [ + 865, + 873 + ] + }, + { + "text": ".Encoding of `satp` MODE field. | 3+|SXLEN=32 |Value |Name |Description |0 + 1 |Bare + Sv32 |No translation or protection. + Page-based 32-bit virtual addressing (see ). 3+|*SXLEN=64* |Value |Name |Description |0 + 1-7 + 8 + 9 + 10 + 11 + 12-13 + 14-15 |Bare + - + Sv39 + Sv48 + Sv57 + Sv64 + - + - |No translation or protection. + Reserved for standard use + Page-based 39-bit virtual addressing (see ). + Page-based 48-bit virtual addressing (see ). + Page-based 57-bit virtual addressing (see ). + Reserved for page-based 64-bit virtual addressing. + Reserved for standard use + Designated for custom use |", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Address Translation and Protection (`satp`) Register", + "line_range": [ + 877, + 915 + ] + }, + { + "text": "The `satp` CSR is considered active when the effective privilege mode is S-mode or U-mode.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Address Translation and Protection (`satp`) Register", + "line_range": [ + 917, + 921 + ] + }, + { + "text": "Executions of the address-translation algorithm may only begin using a given value of `satp` when `satp` is active.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Address Translation and Protection (`satp`) Register", + "line_range": [ + 917, + 921 + ] + }, + { + "text": "Note that writing `satp` does not imply any ordering constraints between page-table updates and subsequent address translations, nor does it imply any invalidation of address-translation caches.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Address Translation and Protection (`satp`) Register", + "line_range": [ + 923, + 930 + ] + }, + { + "text": "If the new address space’s page tables have been modified, or if an ASID is reused, it may be necessary to execute an SFENCE.VMA instruction (see ) after, or in some cases before, writing `satp`.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Address Translation and Protection (`satp`) Register", + "line_range": [ + 923, + 930 + ] + }, + { + "text": "The `stimecmp` CSR is a 64-bit register and has 64-bit precision on all RV32 and RV64 systems.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Timer (`stimecmp`) Register", + "line_range": [ + 935, + 938 + ] + }, + { + "text": "In RV32 only, accesses to the `stimecmp` CSR access the low 32 bits, while accesses to the `stimecmph` CSR access the high 32 bits of `stimecmp`.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Timer (`stimecmp`) Register", + "line_range": [ + 935, + 938 + ] + }, + { + "text": "A supervisor timer interrupt becomes pending, as reflected in the STIP bit in the `mip` and `sip` registers whenever `time` contains a value greater than or equal to `stimecmp`, treating the values as unsigned integers.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Timer (`stimecmp`) Register", + "line_range": [ + 940, + 949 + ] + }, + { + "text": "If the result of this comparison changes, it is guaranteed to be reflected in STIP eventually, but not necessarily immediately.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Timer (`stimecmp`) Register", + "line_range": [ + 940, + 949 + ] + }, + { + "text": "The interrupt remains posted until `stimecmp` becomes greater than `time`, typically as a result of writing `stimecmp`.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Timer (`stimecmp`) Register", + "line_range": [ + 940, + 949 + ] + }, + { + "text": "The interrupt will be taken based on the standard interrupt enable and delegation rules.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor CSRs > Supervisor Timer (`stimecmp`) Register", + "line_range": [ + 940, + 949 + ] + }, + { + "text": "In addition to the SRET instruction defined in , one new supervisor-level instruction is provided.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor Instructions", + "line_range": [ + 953, + 953 + ] + }, + { + "text": "The supervisor memory-management fence instruction SFENCE.VMA is used to synchronize updates to in-memory memory-management data structures with current execution.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction", + "line_range": [ + 960, + 972 + ] + }, + { + "text": "Instruction execution causes implicit reads and writes to these data structures; however, these implicit references are ordinarily not ordered with respect to explicit loads and stores.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction", + "line_range": [ + 960, + 972 + ] + }, + { + "text": "Executing an SFENCE.VMA instruction guarantees that any previous stores already visible to the current RISC-V hart are ordered before certain implicit references by subsequent instructions in that hart to the memory-management data structures.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction", + "line_range": [ + 960, + 972 + ] + }, + { + "text": "The specific set of operations ordered by SFENCE.VMA is determined by rs1 and rs2, as described below. SFENCE.VMA is also used to invalidate entries in the address-translation cache associated with a hart (see ).", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction", + "line_range": [ + 960, + 972 + ] + }, + { + "text": "Further details on the behavior of this instruction are described in and .", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction", + "line_range": [ + 960, + 972 + ] + }, + { + "text": "SFENCE.VMA orders only the local hart’s implicit references to the memory-management data structures.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction", + "line_range": [ + 974, + 975 + ] + }, + { + "text": "For the common case that the translation data structures have only been modified for a single address mapping (i.e., one page or superpage), rs1 can specify a virtual address within that mapping to effect a translation fence for that mapping only.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction", + "line_range": [ + 977, + 983 + ] + }, + { + "text": "Furthermore, for the common case that the translation data structures have only been modified for a single address-space identifier, rs2 can specify the address space.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction", + "line_range": [ + 977, + 983 + ] + }, + { + "text": "The behavior of SFENCE.VMA depends on rs1 and rs2 as follows:", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction", + "line_range": [ + 977, + 983 + ] + }, + { + "text": "If rs1=`x0` and rs2=`x0`, the fence orders all reads and writes made to any level of the page tables, for all address spaces.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction", + "line_range": [ + 985, + 988 + ] + }, + { + "text": "The fence also invalidates all address-translation cache entries, for all address spaces.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction", + "line_range": [ + 985, + 988 + ] + }, + { + "text": "If rs1=`x0` and rs2{ne}``x0``, the fence orders all reads and writes made to any level of the page tables, but only for the address space identified by integer register rs2.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction", + "line_range": [ + 990, + 996 + ] + }, + { + "text": "Accesses to global mappings (see ) are not ordered.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction", + "line_range": [ + 990, + 996 + ] + }, + { + "text": "The fence also invalidates all address-translation cache entries matching the address space identified by integer register rs2, except for entries containing global mappings.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction", + "line_range": [ + 990, + 996 + ] + }, + { + "text": "If rs1{ne}``x0`` and rs2=`x0`, the fence orders only reads and writes made to leaf page table entries corresponding to the virtual address in rs1, for all address spaces.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction", + "line_range": [ + 998, + 1003 + ] + }, + { + "text": "The fence also invalidates all address-translation cache entries that contain leaf page table entries corresponding to the virtual address in rs1, for all address spaces.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction", + "line_range": [ + 998, + 1003 + ] + }, + { + "text": "If rs1{ne}``x0`` and rs2{ne}``x0``, the fence orders only reads and writes made to leaf page table entries corresponding to the virtual address in rs1, for the address space identified by integer register rs2.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction", + "line_range": [ + 1005, + 1012 + ] + }, + { + "text": "Accesses to global mappings are not ordered.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction", + "line_range": [ + 1005, + 1012 + ] + }, + { + "text": "The fence also invalidates all address-translation cache entries that contain leaf page table entries corresponding to the virtual address in rs1 and that match the address space identified by integer register rs2, except for entries containing global mappings.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction", + "line_range": [ + 1005, + 1012 + ] + }, + { + "text": "If the value held in rs1 is not a valid virtual address, then the SFENCE.VMA instruction has no effect.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction", + "line_range": [ + 1014, + 1017 + ] + }, + { + "text": "No exception is raised in this case.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction", + "line_range": [ + 1014, + 1017 + ] + }, + { + "text": "When rs2{ne}``x0``, bits SXLEN-1:ASIDMAX of the value held in rs2 are reserved for future standard use.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction", + "line_range": [ + 1019, + 1025 + ] + }, + { + "text": "Until their use is defined by a standard extension, they should be zeroed by software and ignored by current implementations.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction", + "line_range": [ + 1019, + 1025 + ] + }, + { + "text": "Furthermore, if ASIDLEN Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction", + "line_range": [ + 1019, + 1025 + ] + }, + { + "text": "An implicit read of the memory-management data structures may return any translation for an address that was valid at any time since the most recent SFENCE.VMA that subsumes that address.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction", + "line_range": [ + 1027, + 1040 + ] + }, + { + "text": "The ordering implied by SFENCE.VMA does not place implicit reads and writes to the memory-management data structures into the global memory order in a way that interacts cleanly with the standard RVWMO ordering rules.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction", + "line_range": [ + 1027, + 1040 + ] + }, + { + "text": "In particular, even though an SFENCE.VMA orders prior explicit accesses before subsequent implicit accesses, and those implicit accesses are ordered before their associated explicit accesses, SFENCE.VMA does not necessarily place prior explicit accesses before subsequent explicit accesses in the global memory order.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction", + "line_range": [ + 1027, + 1040 + ] + }, + { + "text": "These implicit loads also need not otherwise obey normal program order semantics with respect to prior loads or stores to the same address.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction", + "line_range": [ + 1027, + 1040 + ] + }, + { + "text": "Implementations must only perform implicit reads of the translation data structures pointed to by the current contents of the `satp` register or a subsequent valid (V=1) translation data structure entry, and must only raise exceptions for implicit accesses that are generated as a result of instruction execution, not those that are performed speculatively.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction", + "line_range": [ + 1042, + 1047 + ] + }, + { + "text": "Changes to the `sstatus` fields SUM and MXR take effect immediately, without the need to execute an SFENCE.VMA instruction.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction", + "line_range": [ + 1049, + 1054 + ] + }, + { + "text": "Changing `satp`.MODE from Bare to other modes and vice versa also takes effect immediately, without the need to execute an SFENCE.VMA instruction.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction", + "line_range": [ + 1049, + 1054 + ] + }, + { + "text": "Likewise, changes to `satp`.ASID take effect immediately.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction", + "line_range": [ + 1049, + 1054 + ] + }, + { + "text": "If a hart employs an address-translation cache, that cache must appear to be private to that hart.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction", + "line_range": [ + 1056, + 1060 + ] + }, + { + "text": "In particular, the meaning of an ASID is local to a hart; software may choose to use the same ASID to refer to different address spaces on different harts.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction", + "line_range": [ + 1056, + 1060 + ] + }, + { + "text": "For implementations that make `satp`.MODE read-only zero (always Bare), attempts to execute an SFENCE.VMA instruction might raise an illegal-instruction exception.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction", + "line_range": [ + 1062, + 1065 + ] + }, + { + "text": "No SFENCE.VMA is required after enabling or disabling pointer masking (see ), as pointer masking applies to the effective address only and does not affect any memory-management data structures.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Supervisor Instructions > Supervisor Memory-Management Fence Instruction", + "line_range": [ + 1067, + 1069 + ] + }, + { + "text": "When Sv32 is written to the MODE field in the `satp` register (see ), the supervisor operates in a 32-bit paged virtual-memory system.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems", + "line_range": [ + 1075, + 1081 + ] + }, + { + "text": "In this mode, supervisor and user virtual addresses are translated into supervisor physical addresses by traversing a radix-tree page table.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems", + "line_range": [ + 1075, + 1081 + ] + }, + { + "text": "Sv32 is supported when SXLEN=32 and is designed to include mechanisms sufficient for supporting modern Unix-based operating systems.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems", + "line_range": [ + 1075, + 1081 + ] + }, + { + "text": "Sv32 implementations support a 32-bit virtual address space, divided into 4 KiB pages.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "line_range": [ + 1086, + 1098 + ] + }, + { + "text": "An Sv32 virtual address is partitioned into a virtual page number (VPN) and page offset, as shown in .", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "line_range": [ + 1086, + 1098 + ] + }, + { + "text": "When Sv32 virtual memory mode is selected in the MODE field of the `satp` register, supervisor virtual addresses are translated into supervisor physical addresses via a two-level page table.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "line_range": [ + 1086, + 1098 + ] + }, + { + "text": "The 20-bit VPN is translated into a 22-bit physical page number (PPN), while the 12-bit page offset is untranslated.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "line_range": [ + 1086, + 1098 + ] + }, + { + "text": "The resulting supervisor-level physical addresses are then checked using any physical memory protection structures (), before being directly converted to machine-level physical addresses.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "line_range": [ + 1086, + 1098 + ] + }, + { + "text": "If necessary, supervisor-level physical addresses are zero-extended to the number of physical address bits found in the implementation.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "line_range": [ + 1086, + 1098 + ] + }, + { + "text": ".Sv32 virtual address. include::images/bytefield/sv32va.edn[]", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "line_range": [ + 1100, + 1102 + ] + }, + { + "text": "Sv32 page tables consist of 2^10^ page-table entries (PTEs), each of four bytes. A page table is exactly the size of a page and must always be aligned to a page boundary.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "line_range": [ + 1104, + 1107 + ] + }, + { + "text": "The physical page number of the root page table is stored in the `satp` register.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "line_range": [ + 1104, + 1107 + ] + }, + { + "text": ".SV32 physical address. include::images/bytefield/sv32pa.edn[]", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "line_range": [ + 1109, + 1111 + ] + }, + { + "text": ".Sv32 page table entry. include::images/bytefield/sv32pte.edn[]", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "line_range": [ + 1113, + 1115 + ] + }, + { + "text": "The PTE format for Sv32 is shown in .", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "line_range": [ + 1117, + 1125 + ] + }, + { + "text": "The V bit indicates whether the PTE is valid; if it is 0, all other bits in the PTE are don’t-cares and may be used freely by software.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "line_range": [ + 1117, + 1125 + ] + }, + { + "text": "The permission bits, R, W, and X, indicate whether the page is readable, writable, and executable, respectively.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "line_range": [ + 1117, + 1125 + ] + }, + { + "text": "When all three are zero, the PTE is a pointer to the next level of the page table; otherwise, it is a leaf PTE.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "line_range": [ + 1117, + 1125 + ] + }, + { + "text": "Writable pages must also be marked readable; the contrary combinations are reserved for future use. summarizes the encoding of the permission bits.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "line_range": [ + 1117, + 1125 + ] + }, + { + "text": ".Encoding of PTE R/W/X fields. | |X |W |R |Meaning |0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 |0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 |0 + 1 + 0 + 1 + 0 + 1 + 0 + 1 |Pointer to next level of page table. + Read-only page. + Reserved for future use. + Read-write page. + Execute-only page. + Read-execute page. + Reserved for future use. + Read-write-execute page. |", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "line_range": [ + 1127, + 1164 + ] + }, + { + "text": "Attempting to fetch an instruction from a page that does not have execute permissions raises a fetch page-fault exception.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "line_range": [ + 1166, + 1173 + ] + }, + { + "text": "Attempting to execute a load, load-reserved, or cache-block management instruction whose effective address lies within a page without read permissions raises a load page-fault exception.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "line_range": [ + 1166, + 1173 + ] + }, + { + "text": "Attempting to execute a store, store-conditional, AMO, or cache-block zero instruction instruction whose effective address lies within a page without write permissions raises a store page-fault exception.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "line_range": [ + 1166, + 1173 + ] + }, + { + "text": "The U bit indicates whether the page is accessible to user mode. U-mode software may only access the page when U=1.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "line_range": [ + 1175, + 1181 + ] + }, + { + "text": "If the SUM bit in the `sstatus` register is set, supervisor mode software may also access pages with U=1.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "line_range": [ + 1175, + 1181 + ] + }, + { + "text": "However, supervisor code normally operates with the SUM bit clear, in which case, supervisor code will fault on accesses to user-mode pages.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "line_range": [ + 1175, + 1181 + ] + }, + { + "text": "Irrespective of SUM, the supervisor may not execute code on pages with U=1.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "line_range": [ + 1175, + 1181 + ] + }, + { + "text": "The G bit designates a global mapping.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "line_range": [ + 1183, + 1190 + ] + }, + { + "text": "Global mappings are those that exist in all address spaces.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "line_range": [ + 1183, + 1190 + ] + }, + { + "text": "For non-leaf PTEs, the global setting implies that all mappings in the subsequent levels of the page table are global.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "line_range": [ + 1183, + 1190 + ] + }, + { + "text": "Note that failing to mark a global mapping as global merely reduces performance, whereas marking a non-global mapping as global is a software bug that, after switching to an address space with a different non-global mapping for that address range, can unpredictably result in either mapping being used.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "line_range": [ + 1183, + 1190 + ] + }, + { + "text": "The RSW field is reserved for use by supervisor software; the implementation shall ignore this field.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "line_range": [ + 1192, + 1193 + ] + }, + { + "text": "Each leaf PTE contains an accessed (A) and dirty (D) bit.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "line_range": [ + 1195, + 1198 + ] + }, + { + "text": "The A bit indicates the virtual page has been read, written, or fetched from since the last time the A bit was cleared.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "line_range": [ + 1195, + 1198 + ] + }, + { + "text": "The D bit indicates the virtual page has been written since the last time the D bit was cleared.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "line_range": [ + 1195, + 1198 + ] + }, + { + "text": "Two schemes to manage the A and D bits are defined:", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "line_range": [ + 1200, + 1200 + ] + }, + { + "text": "* The Svade extension: when a virtual page is accessed and the A bit is clear, or is written and the D bit is clear, a page-fault exception is raised.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "line_range": [ + 1202, + 1205 + ] + }, + { + "text": "When the Svade extension is not implemented, the following scheme applies. + +", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "line_range": [ + 1207, + 1249 + ] + }, + { + "text": "When a virtual page is accessed and the A bit is clear, the PTE is updated to set the A bit.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "line_range": [ + 1207, + 1249 + ] + }, + { + "text": "When the virtual page is written and the D bit is clear, the PTE is updated to set the D bit.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "line_range": [ + 1207, + 1249 + ] + }, + { + "text": "When G-stage address translation is in use and is not Bare, the G-stage virtual pages may be accessed or written by implicit accesses to VS-level memory management data structures, such as page tables. + +", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "line_range": [ + 1207, + 1249 + ] + }, + { + "text": "When two-stage address translation is in use, an explicit access may cause both VS-stage and G-stage PTEs to be updated.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "line_range": [ + 1207, + 1249 + ] + }, + { + "text": "The following rules apply to all PTE updates caused by an explicit or an implicit memory accesses. + + The PTE update must be atomic with respect to other accesses to the PTE, and must atomically perform all page-table walk checks for that leaf PTE as part of, and before, conditionally updating the PTE value.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "line_range": [ + 1207, + 1249 + ] + }, + { + "text": "Updates of the A bit may be performed as a result of speculation, even if the associated memory access ultimately is not performed architecturally.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "line_range": [ + 1207, + 1249 + ] + }, + { + "text": "However, updates to the D bit, resulting from an explicit store, must be exact (i.e., non-speculative), and observed in program order by the local hart.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "line_range": [ + 1207, + 1249 + ] + }, + { + "text": "When two-stage address translation is active, updates to the D bit in G-stage PTEs may be performed by an implicit access to a VS-stage PTE, if the G-stage PTE provides write permission, before any speculative access to the VS-stage PTE. + + The PTE update must appear in the global memory order before the memory access that caused the PTE update and before any subsequent explicit memory access to that virtual page by the local hart.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "line_range": [ + 1207, + 1249 + ] + }, + { + "text": "The ordering on loads and stores provided by FENCE instructions and the acquire/release bits on atomic instructions also orders the PTE updates associated with those loads and stores as observed by remote harts. + + The PTE update is not required to be atomic with respect to the memory access that caused the update and a trap may occur between the PTE update and the memory access that caused the PTE update.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "line_range": [ + 1207, + 1249 + ] + }, + { + "text": "If a trap occurs then the A and/or D bit may be updated but the memory access that caused the PTE update might not occur.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "line_range": [ + 1207, + 1249 + ] + }, + { + "text": "The hart must not perform the memory access that caused the PTE update before the PTE update is globally visible. + + The page tables must be located in memory with hardware page-table write access and RsrvEventual PMA.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "line_range": [ + 1207, + 1249 + ] + }, + { + "text": "All harts in a system must employ the same PTE-update scheme as each other.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "line_range": [ + 1251, + 1252 + ] + }, + { + "text": "Any level of PTE may be a leaf PTE, so in addition to 4 KiB pages, Sv32 supports 4 MiB megapages. A megapage must be virtually and physically aligned to a 4 MiB boundary; a page-fault exception is raised if the physical address is insufficiently aligned.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "line_range": [ + 1254, + 1257 + ] + }, + { + "text": "For non-leaf PTEs, the D, A, and U bits are reserved for future standard use.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "line_range": [ + 1259, + 1261 + ] + }, + { + "text": "Until their use is defined by a standard extension, they must be cleared by software for forward compatibility.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "line_range": [ + 1259, + 1261 + ] + }, + { + "text": "For implementations with both page-based virtual memory and the \"A\" standard extension, the LR/SC reservation set must lie completely within a single base physical page (i.e., a naturally aligned 4 KiB physical-memory region).", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "line_range": [ + 1263, + 1266 + ] + }, + { + "text": "On some implementations, misaligned loads, stores, and instruction fetches may also be decomposed into multiple accesses, some of which may succeed before a page-fault exception occurs.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "line_range": [ + 1268, + 1274 + ] + }, + { + "text": "In particular, a portion of a misaligned store that passes the exception check may become visible, even if another portion fails the exception check.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "line_range": [ + 1268, + 1274 + ] + }, + { + "text": "The same behavior may manifest for stores wider than XLEN bits (e.g., the FSD instruction in RV32D), even when the store address is naturally aligned.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Addressing and Memory Protection", + "line_range": [ + 1268, + 1274 + ] + }, + { + "text": "A virtual address va is translated into a physical address pa as follows:", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process", + "line_range": [ + 1281, + 1281 + ] + }, + { + "text": "Let a be ``satp``.ppn×PAGESIZE, and let i=LEVELS-1. (For Sv32, PAGESIZE=2^12^ and LEVELS=2.) The `satp` register must be active, i.e., the effective privilege mode must be S-mode or U-mode.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process", + "line_range": [ + 1283, + 1284 + ] + }, + { + "text": "Let pte be the value of the PTE at address a+va.vpn[i]×PTESIZE. (For Sv32, PTESIZE=4.)", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process", + "line_range": [ + 1286, + 1286 + ] + }, + { + "text": "If accessing pte violates a PMA or PMP check, raise an access-fault exception corresponding to the original access type.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process", + "line_range": [ + 1286, + 1286 + ] + }, + { + "text": "If pte.v=0, or if pte.r=0 and pte.w=1, or if any bits or encodings that are reserved for future standard use are set within pte, stop and raise a page-fault exception corresponding to the original access type.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process", + "line_range": [ + 1288, + 1288 + ] + }, + { + "text": "Otherwise, the PTE is valid.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process", + "line_range": [ + 1290, + 1291 + ] + }, + { + "text": "If pte.r=1 or pte.x=1, go to step 5.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process", + "line_range": [ + 1290, + 1291 + ] + }, + { + "text": "Otherwise, this PTE is a pointer to the next level of the page table.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process", + "line_range": [ + 1290, + 1291 + ] + }, + { + "text": "If i<0, stop and raise a page-fault exception corresponding to the original access type.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process", + "line_range": [ + 1290, + 1291 + ] + }, + { + "text": "Otherwise, let a=pte.ppn×PAGESIZE and go to step 2.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process", + "line_range": [ + 1290, + 1291 + ] + }, + { + "text": ". A leaf PTE has been reached.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process", + "line_range": [ + 1293, + 1293 + ] + }, + { + "text": "If i>0 and pte.ppn[i-1:0] != 0, this is a misaligned superpage; stop and raise a page-fault exception corresponding to the original access type.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process", + "line_range": [ + 1293, + 1293 + ] + }, + { + "text": "Determine if the requested memory access is allowed by the pte.u bit, given the current privilege mode and the value of the SUM and MXR fields of the *mstatus* register.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process", + "line_range": [ + 1295, + 1295 + ] + }, + { + "text": "If not, stop and raise a page-fault exception corresponding to the original access type.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process", + "line_range": [ + 1295, + 1295 + ] + }, + { + "text": "Determine if the requested memory access is allowed by the pte.r, pte.w, and pte.x bits, given the Shadow Stack Memory Protection rules.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process", + "line_range": [ + 1297, + 1297 + ] + }, + { + "text": "If not, stop and raise an access-fault exception.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process", + "line_range": [ + 1297, + 1297 + ] + }, + { + "text": "Determine if the requested memory access is allowed by the pte.r, pte.w, and pte.x bits.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process", + "line_range": [ + 1299, + 1299 + ] + }, + { + "text": "If not, stop and raise a page-fault exception corresponding to the original access type.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process", + "line_range": [ + 1299, + 1299 + ] + }, + { + "text": "If pte.a=0, or if the original memory access is a store and pte.d=0:", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process", + "line_range": [ + 1301, + 1301 + ] + }, + { + "text": "If the Svade extension is implemented, stop and raise a page-fault exception corresponding to the original access type. *", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process", + "line_range": [ + 1303, + 1311 + ] + }, + { + "text": "If a store to the PTE at address a+va.vpn[i]×PTESIZE would violate a PMA or PMP check, raise an access-fault exception corresponding to the original access type. * Perform the following steps atomically: ** Compare pte to the value of the PTE at address a+va.vpn[i]×PTESIZE. **", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process", + "line_range": [ + 1303, + 1311 + ] + }, + { + "text": "If the values match, set pte.a to 1 and, if the original memory access is a store, also set pte.d to 1.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process", + "line_range": [ + 1303, + 1311 + ] + }, + { + "text": "Then store pte to the PTE at address a+va.vpn[i]×PTESIZE. **", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process", + "line_range": [ + 1303, + 1311 + ] + }, + { + "text": "If the comparison fails, return to step 2.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process", + "line_range": [ + 1303, + 1311 + ] + }, + { + "text": "The translation is successful.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process", + "line_range": [ + 1313, + 1317 + ] + }, + { + "text": "The translated physical address is given as follows: * pa.pgoff = va.pgoff. *", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process", + "line_range": [ + 1313, + 1317 + ] + }, + { + "text": "If i>0, then this is a superpage translation and pa.ppn[i-1:0] = va.vpn[i-1:0]. * pa.ppn[LEVELS-1:i] = pte.ppn[LEVELS-1:i].", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process", + "line_range": [ + 1313, + 1317 + ] + }, + { + "text": "All implicit accesses to the address-translation data structures in this algorithm are performed using width PTESIZE.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process", + "line_range": [ + 1319, + 1320 + ] + }, + { + "text": "The results of implicit address-translation reads in step 2 may be held in a read-only, incoherent address-translation cache but not shared with other harts.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process", + "line_range": [ + 1322, + 1331 + ] + }, + { + "text": "The address-translation cache may hold an arbitrary number of entries, including an arbitrary number of entries for the same address and ASID.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process", + "line_range": [ + 1322, + 1331 + ] + }, + { + "text": "Entries in the address-translation cache may then satisfy subsequent step 2 reads if the ASID associated with the entry matches the ASID loaded in step 0 or if the entry is associated with a global mapping.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process", + "line_range": [ + 1322, + 1331 + ] + }, + { + "text": "To ensure that implicit reads observe writes to the same memory locations, an SFENCE.VMA instruction must be executed after the writes to flush the relevant cached translations.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process", + "line_range": [ + 1322, + 1331 + ] + }, + { + "text": "The address-translation cache cannot be used in step 9; accessed and dirty bits may only be updated in memory directly.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process", + "line_range": [ + 1333, + 1339 + ] + }, + { + "text": "Implementations may also execute the address-translation algorithm speculatively at any time, for any virtual address, as long as `satp` is active (as defined in ).", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process", + "line_range": [ + 1333, + 1339 + ] + }, + { + "text": "Such speculative executions have the effect of pre-populating the address-translation cache.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process", + "line_range": [ + 1333, + 1339 + ] + }, + { + "text": "Speculative executions of the address-translation algorithm behave as non-speculative executions of the algorithm do, except that they must not set the dirty bit for a PTE, they must not trigger an exception, and they must not create address-translation cache entries if those entries would have been invalidated by any SFENCE.VMA instruction executed by the hart since the speculative execution of the algorithm began.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv32: Page-Based 32-bit Virtual-Memory Systems > Virtual Address Translation Process", + "line_range": [ + 1341, + 1346 + ] + }, + { + "text": "This section describes a simple paged virtual-memory system for SXLEN=64, which supports 39-bit virtual address spaces.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv39: Page-Based 39-bit Virtual-Memory System", + "line_range": [ + 1351, + 1354 + ] + }, + { + "text": "The design of Sv39 follows the overall scheme of Sv32, and this section details only the differences between the schemes.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv39: Page-Based 39-bit Virtual-Memory System", + "line_range": [ + 1351, + 1354 + ] + }, + { + "text": "Sv39 implementations support a 39-bit virtual address space, divided into 4 KiB pages.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv39: Page-Based 39-bit Virtual-Memory System > Addressing and Memory Protection", + "line_range": [ + 1359, + 1368 + ] + }, + { + "text": "An Sv39 address is partitioned as shown in .", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv39: Page-Based 39-bit Virtual-Memory System > Addressing and Memory Protection", + "line_range": [ + 1359, + 1368 + ] + }, + { + "text": "Instruction fetch addresses and load and store effective addresses, which are 64 bits, must have bits 63–39 all equal to bit 38, or else a page-fault exception will occur.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv39: Page-Based 39-bit Virtual-Memory System > Addressing and Memory Protection", + "line_range": [ + 1359, + 1368 + ] + }, + { + "text": "The 27-bit VPN is translated into a 44-bit PPN via a three-level page table, while the 12-bit page offset is untranslated.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv39: Page-Based 39-bit Virtual-Memory System > Addressing and Memory Protection", + "line_range": [ + 1359, + 1368 + ] + }, + { + "text": ".Sv39 virtual address. include::images/bytefield/sv39va.edn[]", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv39: Page-Based 39-bit Virtual-Memory System > Addressing and Memory Protection", + "line_range": [ + 1370, + 1372 + ] + }, + { + "text": ".Sv39 physical address. include::images/bytefield/sv39pa.edn[]", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv39: Page-Based 39-bit Virtual-Memory System > Addressing and Memory Protection", + "line_range": [ + 1374, + 1376 + ] + }, + { + "text": ".Sv39 page table entry. include::images/bytefield/sv39pte.edn[]", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv39: Page-Based 39-bit Virtual-Memory System > Addressing and Memory Protection", + "line_range": [ + 1378, + 1380 + ] + }, + { + "text": "Sv39 page tables contain 2^9^ page table entries (PTEs), eight bytes each. A page table is exactly the size of a page and must always be aligned to a page boundary.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv39: Page-Based 39-bit Virtual-Memory System > Addressing and Memory Protection", + "line_range": [ + 1382, + 1387 + ] + }, + { + "text": "The physical page number of the root page table is stored in the `satp` register's PPN field.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv39: Page-Based 39-bit Virtual-Memory System > Addressing and Memory Protection", + "line_range": [ + 1382, + 1387 + ] + }, + { + "text": "The PTE format for Sv39 is shown in .", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv39: Page-Based 39-bit Virtual-Memory System > Addressing and Memory Protection", + "line_range": [ + 1389, + 1403 + ] + }, + { + "text": "Bits 9-0 have the same meaning as for Sv32.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv39: Page-Based 39-bit Virtual-Memory System > Addressing and Memory Protection", + "line_range": [ + 1389, + 1403 + ] + }, + { + "text": "Bit 63 is reserved for use by the Svnapot extension in .", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv39: Page-Based 39-bit Virtual-Memory System > Addressing and Memory Protection", + "line_range": [ + 1389, + 1403 + ] + }, + { + "text": "If Svnapot is not implemented, bit 63 remains reserved and must be zeroed by software for forward compatibility, or else a page-fault exception is raised.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv39: Page-Based 39-bit Virtual-Memory System > Addressing and Memory Protection", + "line_range": [ + 1389, + 1403 + ] + }, + { + "text": "Bits 62-61 are reserved for use by the Svpbmt extension in .", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv39: Page-Based 39-bit Virtual-Memory System > Addressing and Memory Protection", + "line_range": [ + 1389, + 1403 + ] + }, + { + "text": "If Svpbmt is not implemented, bits 62-61 remain reserved and must be zeroed by software for forward compatibility, or else a page-fault exception is raised.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv39: Page-Based 39-bit Virtual-Memory System > Addressing and Memory Protection", + "line_range": [ + 1389, + 1403 + ] + }, + { + "text": "Bits 60-54 are reserved for future standard use and, until their use is defined by some standard extension, must be zeroed by software for forward compatibility.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv39: Page-Based 39-bit Virtual-Memory System > Addressing and Memory Protection", + "line_range": [ + 1389, + 1403 + ] + }, + { + "text": "If any of these bits are set, a page-fault exception is raised.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv39: Page-Based 39-bit Virtual-Memory System > Addressing and Memory Protection", + "line_range": [ + 1389, + 1403 + ] + }, + { + "text": "Any level of PTE may be a leaf PTE, so in addition to 4 KiB pages, Sv39 supports 2 MiB megapages and 1 GiB gigapages, each of which must be virtually and physically aligned to a boundary equal to its size. A page-fault exception is raised if the physical address is insufficiently aligned.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv39: Page-Based 39-bit Virtual-Memory System > Addressing and Memory Protection", + "line_range": [ + 1405, + 1411 + ] + }, + { + "text": "The algorithm for virtual-to-physical address translation is the same as in , except LEVELS equals 3 and PTESIZE equals 8.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv39: Page-Based 39-bit Virtual-Memory System > Addressing and Memory Protection", + "line_range": [ + 1413, + 1416 + ] + }, + { + "text": "This section describes a simple paged virtual-memory system for SXLEN=64, which supports 48-bit virtual address spaces.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv48: Page-Based 48-bit Virtual-Memory System", + "line_range": [ + 1421, + 1427 + ] + }, + { + "text": "Sv48 is intended for systems for which a 39-bit virtual address space is insufficient.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv48: Page-Based 48-bit Virtual-Memory System", + "line_range": [ + 1421, + 1427 + ] + }, + { + "text": "It closely follows the design of Sv39, simply adding an additional level of page table, and so this chapter only details the differences between the two schemes.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv48: Page-Based 48-bit Virtual-Memory System", + "line_range": [ + 1421, + 1427 + ] + }, + { + "text": "Implementations that support Sv48 must also support Sv39.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv48: Page-Based 48-bit Virtual-Memory System", + "line_range": [ + 1429, + 1430 + ] + }, + { + "text": "Sv48 implementations support a 48-bit virtual address space, divided into 4 KiB pages.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv48: Page-Based 48-bit Virtual-Memory System > Addressing and Memory Protection", + "line_range": [ + 1435, + 1444 + ] + }, + { + "text": "An Sv48 address is partitioned as shown in .", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv48: Page-Based 48-bit Virtual-Memory System > Addressing and Memory Protection", + "line_range": [ + 1435, + 1444 + ] + }, + { + "text": "Instruction fetch addresses and load and store effective addresses, which are 64 bits, must have bits 63–48 all equal to bit 47, or else a page-fault exception will occur.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv48: Page-Based 48-bit Virtual-Memory System > Addressing and Memory Protection", + "line_range": [ + 1435, + 1444 + ] + }, + { + "text": "The 36-bit VPN is translated into a 44-bit PPN via a four-level page table, while the 12-bit page offset is untranslated.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv48: Page-Based 48-bit Virtual-Memory System > Addressing and Memory Protection", + "line_range": [ + 1435, + 1444 + ] + }, + { + "text": ".Sv48 virtual address. include::images/bytefield/sv48va.edn[]", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv48: Page-Based 48-bit Virtual-Memory System > Addressing and Memory Protection", + "line_range": [ + 1446, + 1448 + ] + }, + { + "text": ".Sv48 physical address. include::images/bytefield/sv48pa.edn[]", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv48: Page-Based 48-bit Virtual-Memory System > Addressing and Memory Protection", + "line_range": [ + 1450, + 1452 + ] + }, + { + "text": ".Sv48 page table entry. include::images/bytefield/sv48pte.edn[]", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv48: Page-Based 48-bit Virtual-Memory System > Addressing and Memory Protection", + "line_range": [ + 1454, + 1456 + ] + }, + { + "text": "The PTE format for Sv48 is shown in .", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv48: Page-Based 48-bit Virtual-Memory System > Addressing and Memory Protection", + "line_range": [ + 1458, + 1467 + ] + }, + { + "text": "Bits 63-54 and 9-0 have the same meaning as for Sv39.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv48: Page-Based 48-bit Virtual-Memory System > Addressing and Memory Protection", + "line_range": [ + 1458, + 1467 + ] + }, + { + "text": "Any level of PTE may be a leaf PTE, so in addition to 4 KiB pages, Sv48 supports 2 MiB megapages, 1 GiB gigapages, and 512 GiB terapages, each of which must be virtually and physically aligned to a boundary equal to its size. A page-fault exception is raised if the physical address is insufficiently aligned.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv48: Page-Based 48-bit Virtual-Memory System > Addressing and Memory Protection", + "line_range": [ + 1458, + 1467 + ] + }, + { + "text": "The algorithm for virtual-to-physical address translation is the same as in , except LEVELS equals 4 and PTESIZE equals 8.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv48: Page-Based 48-bit Virtual-Memory System > Addressing and Memory Protection", + "line_range": [ + 1469, + 1472 + ] + }, + { + "text": "This section describes a simple paged virtual-memory system designed for RV64 systems, which supports 57-bit virtual address spaces.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv57: Page-Based 57-bit Virtual-Memory System", + "line_range": [ + 1478, + 1484 + ] + }, + { + "text": "Sv57 is intended for systems for which a 48-bit virtual address space is insufficient.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv57: Page-Based 57-bit Virtual-Memory System", + "line_range": [ + 1478, + 1484 + ] + }, + { + "text": "It closely follows the design of Sv48, simply adding an additional level of page table, and so this chapter only details the differences between the two schemes.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv57: Page-Based 57-bit Virtual-Memory System", + "line_range": [ + 1478, + 1484 + ] + }, + { + "text": "Implementations that support Sv57 must also support Sv48.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv57: Page-Based 57-bit Virtual-Memory System", + "line_range": [ + 1486, + 1487 + ] + }, + { + "text": "Sv57 implementations support a 57-bit virtual address space, divided into 4 KiB pages.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv57: Page-Based 57-bit Virtual-Memory System > Addressing and Memory Protection", + "line_range": [ + 1492, + 1501 + ] + }, + { + "text": "An Sv57 address is partitioned as shown in .", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv57: Page-Based 57-bit Virtual-Memory System > Addressing and Memory Protection", + "line_range": [ + 1492, + 1501 + ] + }, + { + "text": "Instruction fetch addresses and load and store effective addresses, which are 64 bits, must have bits 63–57 all equal to bit 56, or else a page-fault exception will occur.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv57: Page-Based 57-bit Virtual-Memory System > Addressing and Memory Protection", + "line_range": [ + 1492, + 1501 + ] + }, + { + "text": "The 45-bit VPN is translated into a 44-bit PPN via a five-level page table, while the 12-bit page offset is untranslated.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv57: Page-Based 57-bit Virtual-Memory System > Addressing and Memory Protection", + "line_range": [ + 1492, + 1501 + ] + }, + { + "text": ".Sv57 virtual address. include::images/bytefield/sv57va.edn[]", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv57: Page-Based 57-bit Virtual-Memory System > Addressing and Memory Protection", + "line_range": [ + 1503, + 1505 + ] + }, + { + "text": ".Sv57 physical address. include::images/bytefield/sv57pa.edn[]", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv57: Page-Based 57-bit Virtual-Memory System > Addressing and Memory Protection", + "line_range": [ + 1507, + 1509 + ] + }, + { + "text": ".Sv57 page table entry. include::images/bytefield/sv57pte.edn[]", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv57: Page-Based 57-bit Virtual-Memory System > Addressing and Memory Protection", + "line_range": [ + 1511, + 1513 + ] + }, + { + "text": "The PTE format for Sv57 is shown in .", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv57: Page-Based 57-bit Virtual-Memory System > Addressing and Memory Protection", + "line_range": [ + 1515, + 1524 + ] + }, + { + "text": "Bits 63–54 and 9–0 have the same meaning as for Sv39.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv57: Page-Based 57-bit Virtual-Memory System > Addressing and Memory Protection", + "line_range": [ + 1515, + 1524 + ] + }, + { + "text": "Any level of PTE may be a leaf PTE, so in addition to 4 KiB pages, Sv57 supports 2 MiB megapages, 1 GiB gigapages, 512 GiB terapages, and 256 TiB petapages, each of which must be virtually and physically aligned to a boundary equal to its size. A page-fault exception is raised if the physical address is insufficiently aligned.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv57: Page-Based 57-bit Virtual-Memory System > Addressing and Memory Protection", + "line_range": [ + 1515, + 1524 + ] + }, + { + "text": "The algorithm for virtual-to-physical address translation is the same as in , except LEVELS equals 5 and PTESIZE equals 8.", + "section": "Preamble > Supervisor-Level ISA, Version 1.13 > Sv57: Page-Based 57-bit Virtual-Memory System > Addressing and Memory Protection", + "line_range": [ + 1526, + 1529 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__priv__sv.json b/tools/llm-extraction/data/output/raw_chunks/src__priv__sv.json new file mode 100644 index 0000000000..769f3defed --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__priv__sv.json @@ -0,0 +1,22 @@ +{ + "source_file": "src/priv/sv.adoc", + "total": 2, + "sentences": [ + { + "text": "NOTE: This chapter is currently being restructured.", + "section": "Preamble > \"Sv\" Supervisor Virtual-Memory Extensions", + "line_range": [ + 3, + 4 + ] + }, + { + "text": "Its contents are normative, but the presentation might appear disjoint.", + "section": "Preamble > \"Sv\" Supervisor Virtual-Memory Extensions", + "line_range": [ + 3, + 4 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__priv__svadu.json b/tools/llm-extraction/data/output/raw_chunks/src__priv__svadu.json new file mode 100644 index 0000000000..629e44fe85 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__priv__svadu.json @@ -0,0 +1,62 @@ +{ + "source_file": "src/priv/svadu.adoc", + "total": 7, + "sentences": [ + { + "text": "The Svadu extension adds support and CSR controls for hardware updating of PTE A/D bits.", + "section": "Preamble > \"Svadu\" Extension for Hardware Updating of A/D Bits, Version 1.0", + "line_range": [ + 3, + 3 + ] + }, + { + "text": "If the Svadu extension is implemented, the `menvcfg`.ADUE field is writable.", + "section": "Preamble > \"Svadu\" Extension for Hardware Updating of A/D Bits, Version 1.0", + "line_range": [ + 5, + 8 + ] + }, + { + "text": "If the hypervisor extension is additionally implemented, the `henvcfg`.ADUE field is also writable.", + "section": "Preamble > \"Svadu\" Extension for Hardware Updating of A/D Bits, Version 1.0", + "line_range": [ + 5, + 8 + ] + }, + { + "text": "See and for the definitions of those fields.", + "section": "Preamble > \"Svadu\" Extension for Hardware Updating of A/D Bits, Version 1.0", + "line_range": [ + 5, + 8 + ] + }, + { + "text": "defines the semantics of hardware updating of A/D bits.", + "section": "Preamble > \"Svadu\" Extension for Hardware Updating of A/D Bits, Version 1.0", + "line_range": [ + 10, + 13 + ] + }, + { + "text": "When hardware updating of A/D bits is disabled, the Svade extension, which mandates exceptions when A/D bits need be set, instead takes effect.", + "section": "Preamble > \"Svadu\" Extension for Hardware Updating of A/D Bits, Version 1.0", + "line_range": [ + 10, + 13 + ] + }, + { + "text": "The Svade extension is also defined in .", + "section": "Preamble > \"Svadu\" Extension for Hardware Updating of A/D Bits, Version 1.0", + "line_range": [ + 10, + 13 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__priv__svinval.json b/tools/llm-extraction/data/output/raw_chunks/src__priv__svinval.json new file mode 100644 index 0000000000..4487c9738a --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__priv__svinval.json @@ -0,0 +1,142 @@ +{ + "source_file": "src/priv/svinval.adoc", + "total": 17, + "sentences": [ + { + "text": "The Svinval extension splits SFENCE.VMA, HFENCE.VVMA, and HFENCE.GVMA instructions into finer-grained invalidation and ordering operations that can be more efficiently batched or pipelined on certain classes of high-performance implementation.", + "section": "Preamble > \"Svinval\" Extension for Fine-Grained Address-Translation Cache Invalidation, Version 1.0", + "line_range": [ + 3, + 6 + ] + }, + { + "text": "The SINVAL.VMA instruction invalidates any address-translation cache entries that an SFENCE.VMA instruction with the same values of rs1 and rs2 would invalidate.", + "section": "Preamble > \"Svinval\" Extension for Fine-Grained Address-Translation Cache Invalidation, Version 1.0", + "line_range": [ + 10, + 15 + ] + }, + { + "text": "However, unlike SFENCE.VMA, SINVAL.VMA instructions are only ordered with respect to SFENCE.VMA, SFENCE.W.INVAL, and SFENCE.INVAL.IR instructions as defined below.", + "section": "Preamble > \"Svinval\" Extension for Fine-Grained Address-Translation Cache Invalidation, Version 1.0", + "line_range": [ + 10, + 15 + ] + }, + { + "text": "The SFENCE.W.INVAL instruction guarantees that any previous stores already visible to the current RISC-V hart are ordered before subsequent SINVAL.VMA instructions executed by the same hart.", + "section": "Preamble > \"Svinval\" Extension for Fine-Grained Address-Translation Cache Invalidation, Version 1.0", + "line_range": [ + 21, + 27 + ] + }, + { + "text": "The SFENCE.INVAL.IR instruction guarantees that any previous SINVAL.VMA instructions executed by the current hart are ordered before subsequent implicit references by that hart to the memory-management data structures.", + "section": "Preamble > \"Svinval\" Extension for Fine-Grained Address-Translation Cache Invalidation, Version 1.0", + "line_range": [ + 21, + 27 + ] + }, + { + "text": "When executed in order (but not necessarily consecutively) by a single hart, the sequence SFENCE.W.INVAL, SINVAL.VMA, and SFENCE.INVAL.IR has the same effect as a hypothetical SFENCE.VMA instruction in which:", + "section": "Preamble > \"Svinval\" Extension for Fine-Grained Address-Translation Cache Invalidation, Version 1.0", + "line_range": [ + 29, + 31 + ] + }, + { + "text": "the values of rs1 and rs2 for the SFENCE.VMA are the same as those used in the SINVAL.VMA, * reads and writes prior to the SFENCE.W.INVAL are considered to be those prior to the SFENCE.VMA, and * reads and writes following the SFENCE.INVAL.IR are considered to be those subsequent to the SFENCE.VMA.", + "section": "Preamble > \"Svinval\" Extension for Fine-Grained Address-Translation Cache Invalidation, Version 1.0", + "line_range": [ + 33, + 38 + ] + }, + { + "text": "If the hypervisor extension is implemented, the Svinval extension also provides two additional instructions: HINVAL.VVMA and HINVAL.GVMA.", + "section": "Preamble > \"Svinval\" Extension for Fine-Grained Address-Translation Cache Invalidation, Version 1.0", + "line_range": [ + 44, + 49 + ] + }, + { + "text": "These have the same semantics as SINVAL.VMA, except that they combine with SFENCE.W.INVAL and SFENCE.INVAL.IR to replace HFENCE.VVMA and HFENCE.GVMA, respectively, instead of SFENCE.VMA.", + "section": "Preamble > \"Svinval\" Extension for Fine-Grained Address-Translation Cache Invalidation, Version 1.0", + "line_range": [ + 44, + 49 + ] + }, + { + "text": "In addition, HINVAL.GVMA uses VMIDs instead of ASIDs.", + "section": "Preamble > \"Svinval\" Extension for Fine-Grained Address-Translation Cache Invalidation, Version 1.0", + "line_range": [ + 44, + 49 + ] + }, + { + "text": "SINVAL.VMA, HINVAL.VVMA, and HINVAL.GVMA require the same permissions and raise the same exceptions as SFENCE.VMA, HFENCE.VVMA, and HFENCE.GVMA, respectively.", + "section": "Preamble > \"Svinval\" Extension for Fine-Grained Address-Translation Cache Invalidation, Version 1.0", + "line_range": [ + 51, + 62 + ] + }, + { + "text": "In particular, an attempt to execute any of these instructions in U-mode always raises an illegal-instruction exception.", + "section": "Preamble > \"Svinval\" Extension for Fine-Grained Address-Translation Cache Invalidation, Version 1.0", + "line_range": [ + 51, + 62 + ] + }, + { + "text": "An attempt to execute SINVAL.VMA or HINVAL.GVMA in S-mode or HS-mode when `mstatus`.TVM=1 also raises an illegal-instruction exception.", + "section": "Preamble > \"Svinval\" Extension for Fine-Grained Address-Translation Cache Invalidation, Version 1.0", + "line_range": [ + 51, + 62 + ] + }, + { + "text": "An attempt to execute HINVAL.VVMA or HINVAL.GVMA in VS-mode or VU-mode, or to execute SINVAL.VMA in VU-mode, raises a virtual-instruction exception.", + "section": "Preamble > \"Svinval\" Extension for Fine-Grained Address-Translation Cache Invalidation, Version 1.0", + "line_range": [ + 51, + 62 + ] + }, + { + "text": "When `hstatus`.VTVM=1, an attempt to execute SINVAL.VMA in VS-mode also raises a virtual-instruction exception.", + "section": "Preamble > \"Svinval\" Extension for Fine-Grained Address-Translation Cache Invalidation, Version 1.0", + "line_range": [ + 51, + 62 + ] + }, + { + "text": "Attempting to execute SFENCE.W.INVAL or SFENCE.INVAL.IR in U-mode raises an illegal-instruction exception.", + "section": "Preamble > \"Svinval\" Extension for Fine-Grained Address-Translation Cache Invalidation, Version 1.0", + "line_range": [ + 64, + 68 + ] + }, + { + "text": "Doing so in VU-mode raises a virtual-instruction exception. SFENCE.W.INVAL and SFENCE.INVAL.IR are unaffected by the `mstatus`.TVM and `hstatus`.VTVM fields and hence are always permitted in S-mode and VS-mode.", + "section": "Preamble > \"Svinval\" Extension for Fine-Grained Address-Translation Cache Invalidation, Version 1.0", + "line_range": [ + 64, + 68 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__priv__svnapot.json b/tools/llm-extraction/data/output/raw_chunks/src__priv__svnapot.json new file mode 100644 index 0000000000..8a5e5f76f3 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__priv__svnapot.json @@ -0,0 +1,78 @@ +{ + "source_file": "src/priv/svnapot.adoc", + "total": 9, + "sentences": [ + { + "text": "In Sv39, Sv48, and Sv57, when a PTE has N=1, the PTE represents a translation that is part of a range of contiguous virtual-to-physical translations with the same values for PTE bits 5–0.", + "section": "Preamble > \"Svnapot\" Extension for NAPOT Translation Contiguity, Version 1.0", + "line_range": [ + 3, + 8 + ] + }, + { + "text": "Such ranges must be of a naturally aligned power-of-2 (NAPOT) granularity larger than the base page size.", + "section": "Preamble > \"Svnapot\" Extension for NAPOT Translation Contiguity, Version 1.0", + "line_range": [ + 3, + 8 + ] + }, + { + "text": "The Svnapot extension depends on the Sv39 extension.", + "section": "Preamble > \"Svnapot\" Extension for NAPOT Translation Contiguity, Version 1.0", + "line_range": [ + 10, + 11 + ] + }, + { + "text": ".Page table entry encodings when pte.N=1 | |i |pte.ppn[i] |Description |pte.napotbits |0 + 0 + 0 + 0 + 0 + {ge}1 |`x xxxx xxx1` + `x xxxx xx1x` + `x xxxx x1xx` + `x xxxx 1000` + `x xxxx 0xxx` + `x xxxx xxxx` |Reserved + Reserved + Reserved + 64 KiB contiguous region + Reserved + Reserved | - + - + - + 4 + - + - |", + "section": "Preamble > \"Svnapot\" Extension for NAPOT Translation Contiguity, Version 1.0", + "line_range": [ + 13, + 42 + ] + }, + { + "text": "NAPOT PTEs behave identically to non-NAPOT PTEs within the address-translation algorithm in , except that:", + "section": "Preamble > \"Svnapot\" Extension for NAPOT Translation Contiguity, Version 1.0", + "line_range": [ + 44, + 46 + ] + }, + { + "text": "If the encoding in pte is valid according to , then instead of returning the original value of pte, implicit reads of a NAPOT PTE return a copy of pte in which pte.ppn[i][pte.napotbits-1:0] is replaced by vpn[i][pte.napotbits-1:0].", + "section": "Preamble > \"Svnapot\" Extension for NAPOT Translation Contiguity, Version 1.0", + "line_range": [ + 48, + 56 + ] + }, + { + "text": "If the encoding in pte is reserved according to , then a page-fault exception must be raised.", + "section": "Preamble > \"Svnapot\" Extension for NAPOT Translation Contiguity, Version 1.0", + "line_range": [ + 48, + 56 + ] + }, + { + "text": "Implicit reads of NAPOT page table entries may create address-translation cache entries mapping a + j×PTESIZE to a copy of pte in which pte.ppn[i][pte.napotbits-1:0] is replaced by vpn[i][pte.napotbits-1:0], for any or all j such that j >> napotbits = vpn[i] >> napotbits, all for the address space identified in satp as loaded by step 1.", + "section": "Preamble > \"Svnapot\" Extension for NAPOT Translation Contiguity, Version 1.0", + "line_range": [ + 58, + 64 + ] + }, + { + "text": "If the hypervisor extension is also implemented, Svnapot is also supported in G-stage translation.", + "section": "Preamble > \"Svnapot\" Extension for NAPOT Translation Contiguity, Version 1.0", + "line_range": [ + 66, + 68 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__priv__svpbmt.json b/tools/llm-extraction/data/output/raw_chunks/src__priv__svpbmt.json new file mode 100644 index 0000000000..35c6b5fd5f --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__priv__svpbmt.json @@ -0,0 +1,238 @@ +{ + "source_file": "src/priv/svpbmt.adoc", + "total": 29, + "sentences": [ + { + "text": "In Sv39, Sv48, and Sv57, bits 62-61 of a leaf page table entry indicate the use of page-based memory types that override the PMA(s) for the associated memory pages.", + "section": "Preamble > \"Svpbmt\" Extension for Page-Based Memory Types, Version 1.0", + "line_range": [ + 3, + 6 + ] + }, + { + "text": "The encoding for the PBMT bits is captured in .", + "section": "Preamble > \"Svpbmt\" Extension for Page-Based Memory Types, Version 1.0", + "line_range": [ + 3, + 6 + ] + }, + { + "text": "The Svpbmt extension depends on the Sv39 extension.", + "section": "Preamble > \"Svpbmt\" Extension for Page-Based Memory Types, Version 1.0", + "line_range": [ + 8, + 8 + ] + }, + { + "text": ".Encodings for PBMT field in Sv39, Sv48, and Sv57 PTEs. | |Mode |Value |Requested Memory Attributes |PMA + NC + IO + - |0 + 1 + 2 + 3 |None + Non-cacheable, idempotent, weakly-ordered (RVWMO), main memory + Non-cacheable, non-idempotent, strongly-ordered (I/O ordering), I/O + Reserved for future standard use |", + "section": "Preamble > \"Svpbmt\" Extension for Page-Based Memory Types, Version 1.0", + "line_range": [ + 10, + 27 + ] + }, + { + "text": "Implementations may override additional PMAs not explicitly listed in .", + "section": "Preamble > \"Svpbmt\" Extension for Page-Based Memory Types, Version 1.0", + "line_range": [ + 29, + 34 + ] + }, + { + "text": "For example, to be consistent with the characteristics of a typical I/O region, a misaligned memory access to a page with PBMT=IO might raise an exception, even if the underlying region were main memory and the same access would have succeeded for PBMT=PMA.", + "section": "Preamble > \"Svpbmt\" Extension for Page-Based Memory Types, Version 1.0", + "line_range": [ + 29, + 34 + ] + }, + { + "text": "For non-leaf PTEs, bits 62-61 are reserved for future standard use.", + "section": "Preamble > \"Svpbmt\" Extension for Page-Based Memory Types, Version 1.0", + "line_range": [ + 36, + 39 + ] + }, + { + "text": "Until their use is defined by a standard extension, they must be cleared by software for forward compatibility, or else a page-fault exception is raised.", + "section": "Preamble > \"Svpbmt\" Extension for Page-Based Memory Types, Version 1.0", + "line_range": [ + 36, + 39 + ] + }, + { + "text": "For leaf PTEs, setting bits 62-61 to the value 3 is reserved for future standard use.", + "section": "Preamble > \"Svpbmt\" Extension for Page-Based Memory Types, Version 1.0", + "line_range": [ + 41, + 44 + ] + }, + { + "text": "Until this value is defined by a standard extension, using this reserved value in a leaf PTE raises a page-fault exception.", + "section": "Preamble > \"Svpbmt\" Extension for Page-Based Memory Types, Version 1.0", + "line_range": [ + 41, + 44 + ] + }, + { + "text": "When PBMT settings override a main memory page into I/O or vice versa, memory accesses to such pages obey the memory ordering rules of the final effective attribute, as follows.", + "section": "Preamble > \"Svpbmt\" Extension for Page-Based Memory Types, Version 1.0", + "line_range": [ + 46, + 48 + ] + }, + { + "text": "If the underlying physical memory attribute for a page is I/O, and the page has PBMT=NC, then accesses to that page obey RVWMO.", + "section": "Preamble > \"Svpbmt\" Extension for Page-Based Memory Types, Version 1.0", + "line_range": [ + 50, + 54 + ] + }, + { + "text": "However, accesses to such pages are considered to be both I/O and main memory accesses for the purposes of FENCE, .aq, and .rl.", + "section": "Preamble > \"Svpbmt\" Extension for Page-Based Memory Types, Version 1.0", + "line_range": [ + 50, + 54 + ] + }, + { + "text": "If the underlying physical memory attribute for a page is main memory, and the page has PBMT=IO, then accesses to that page obey strong channel 0 I/O ordering rules.", + "section": "Preamble > \"Svpbmt\" Extension for Page-Based Memory Types, Version 1.0", + "line_range": [ + 56, + 62 + ] + }, + { + "text": "However, accesses to such pages are considered to be both I/O and main memory accesses for the purposes of FENCE, .aq, and .rl.", + "section": "Preamble > \"Svpbmt\" Extension for Page-Based Memory Types, Version 1.0", + "line_range": [ + 56, + 62 + ] + }, + { + "text": "When Svpbmt is used with non-zero PBMT encodings, it is possible for multiple virtual aliases of the same physical page to exist simultaneously with different memory attributes.", + "section": "Preamble > \"Svpbmt\" Extension for Page-Based Memory Types, Version 1.0", + "line_range": [ + 64, + 72 + ] + }, + { + "text": "It is also possible for a U-mode or S-mode mapping through a PTE with Svpbmt enabled to observe different memory attributes for a given region of physical memory than a concurrent access to the same page performed by M-mode or when MODE=Bare.", + "section": "Preamble > \"Svpbmt\" Extension for Page-Based Memory Types, Version 1.0", + "line_range": [ + 64, + 72 + ] + }, + { + "text": "In such cases, the behaviors dictated by the attributes (including coherence, which is otherwise unaffected) may be violated.", + "section": "Preamble > \"Svpbmt\" Extension for Page-Based Memory Types, Version 1.0", + "line_range": [ + 64, + 72 + ] + }, + { + "text": "Accessing the same location using different attributes that are both non-cacheable (e.g., NC and IO) does not cause loss of coherence, but might result in weaker memory ordering than the stricter attribute ordinarily guarantees.", + "section": "Preamble > \"Svpbmt\" Extension for Page-Based Memory Types, Version 1.0", + "line_range": [ + 74, + 80 + ] + }, + { + "text": "Executing a `fence iorw, iorw` instruction between such accesses suffices to prevent loss of memory ordering.", + "section": "Preamble > \"Svpbmt\" Extension for Page-Based Memory Types, Version 1.0", + "line_range": [ + 74, + 80 + ] + }, + { + "text": "Accessing the same location using different cacheability attributes may cause loss of coherence.", + "section": "Preamble > \"Svpbmt\" Extension for Page-Based Memory Types, Version 1.0", + "line_range": [ + 82, + 88 + ] + }, + { + "text": "Executing the following sequence between such accesses prevents both loss of coherence and loss of memory ordering: `fence iorw, iorw`, followed by `cbo.flush` to an address of that location, followed by a `fence iorw, iorw`.", + "section": "Preamble > \"Svpbmt\" Extension for Page-Based Memory Types, Version 1.0", + "line_range": [ + 82, + 88 + ] + }, + { + "text": "When two-stage address translation is enabled within the H extension, the page-based memory types are also applied in two stages.", + "section": "Preamble > \"Svpbmt\" Extension for Page-Based Memory Types, Version 1.0", + "line_range": [ + 90, + 99 + ] + }, + { + "text": "First, if `hgatp`.MODE is not equal to zero, non-zero G-stage PTE PBMT bits override the attributes in the PMA to produce an intermediate set of attributes.", + "section": "Preamble > \"Svpbmt\" Extension for Page-Based Memory Types, Version 1.0", + "line_range": [ + 90, + 99 + ] + }, + { + "text": "Otherwise, the PMAs serve as the intermediate attributes.", + "section": "Preamble > \"Svpbmt\" Extension for Page-Based Memory Types, Version 1.0", + "line_range": [ + 90, + 99 + ] + }, + { + "text": "Second, if `vsatp`.MODE is not equal to zero, non-zero VS-stage PTE PBMT bits override the intermediate attributes to produce the final set of attributes used by accesses to the page in question.", + "section": "Preamble > \"Svpbmt\" Extension for Page-Based Memory Types, Version 1.0", + "line_range": [ + 90, + 99 + ] + }, + { + "text": "Otherwise, the intermediate attributes are used as the final set of attributes.", + "section": "Preamble > \"Svpbmt\" Extension for Page-Based Memory Types, Version 1.0", + "line_range": [ + 90, + 99 + ] + }, + { + "text": "NOTE: These final attributes apply to implicit and explicit accesses that are subject to both stages of address translation.", + "section": "Preamble > \"Svpbmt\" Extension for Page-Based Memory Types, Version 1.0", + "line_range": [ + 101, + 104 + ] + }, + { + "text": "For accesses that are not subject to the first stage of address translation, e.g. VS-stage page-table accesses, the intermediate attributes apply instead.", + "section": "Preamble > \"Svpbmt\" Extension for Page-Based Memory Types, Version 1.0", + "line_range": [ + 101, + 104 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__priv__svrsw60t59b.json b/tools/llm-extraction/data/output/raw_chunks/src__priv__svrsw60t59b.json new file mode 100644 index 0000000000..d7c546d96b --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__priv__svrsw60t59b.json @@ -0,0 +1,30 @@ +{ + "source_file": "src/priv/svrsw60t59b.adoc", + "total": 3, + "sentences": [ + { + "text": "If the Svrsw60t59b extension is implemented, then bits 60-59 of the page table entries (PTEs) are reserved for use by supervisor software and are ignored by the implementation.", + "section": "Preamble > \"Svrsw60t59b\" Extension for PTE Reserved-for-Software Bits 60-59, Version 1.0", + "line_range": [ + 3, + 5 + ] + }, + { + "text": "If the Hypervisor (H) extension is also implemented, then bits 60-59 of the G-stage PTEs are reserved for use by supervisor software and are ignored by the implementation.", + "section": "Preamble > \"Svrsw60t59b\" Extension for PTE Reserved-for-Software Bits 60-59, Version 1.0", + "line_range": [ + 7, + 9 + ] + }, + { + "text": "The Svrsw60t59b extension depends on Sv39.", + "section": "Preamble > \"Svrsw60t59b\" Extension for PTE Reserved-for-Software Bits 60-59, Version 1.0", + "line_range": [ + 11, + 11 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__priv__svvptc.json b/tools/llm-extraction/data/output/raw_chunks/src__priv__svvptc.json new file mode 100644 index 0000000000..c3a401ffe2 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__priv__svvptc.json @@ -0,0 +1,14 @@ +{ + "source_file": "src/priv/svvptc.adoc", + "total": 1, + "sentences": [ + { + "text": "When the Svvptc extension is implemented, explicit stores by a hart that update the Valid bit of leaf and/or non-leaf PTEs from 0 to 1 and are visible to a hart will eventually become visible within a bounded timeframe to subsequent implicit accesses by that hart to such PTEs.", + "section": "Preamble > \"Svvptc\" Extension for Obviating Memory-Management Instructions after Marking PTEs Valid, Version 1.0", + "line_range": [ + 3, + 6 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__priv__zpm.json b/tools/llm-extraction/data/output/raw_chunks/src__priv__zpm.json new file mode 100644 index 0000000000..9748a7c708 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__priv__zpm.json @@ -0,0 +1,878 @@ +{ + "source_file": "src/priv/zpm.adoc", + "total": 109, + "sentences": [ + { + "text": "RISC-V Pointer Masking (PM) is a feature that, when enabled, causes the CPU to ignore the upper bits of the effective address (these terms will be defined more precisely in the Background section).", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction", + "line_range": [ + 5, + 5 + ] + }, + { + "text": "This allows these bits to be used in whichever way the application chooses.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction", + "line_range": [ + 5, + 5 + ] + }, + { + "text": "The version of the extension being described here specifically targets **tag checks**:", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction", + "line_range": [ + 5, + 5 + ] + }, + { + "text": "When an address is accessed, the tag stored in the masked bits can be compared against a range-based tag.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction", + "line_range": [ + 5, + 5 + ] + }, + { + "text": "This is used for dynamic safety checkers such as HWASAN cite:[HWASAN].", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction", + "line_range": [ + 5, + 5 + ] + }, + { + "text": "Such tools can be applied in all privilege modes (U, S, and M).", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction", + "line_range": [ + 5, + 5 + ] + }, + { + "text": "HWASAN leverages tags in the upper bits of the address to identify memory errors such as use-after-free or buffer overflow errors.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction", + "line_range": [ + 7, + 7 + ] + }, + { + "text": "By storing a *pointer tag* in the upper bits of the address and checking it against a *memory tag* stored in a side table, it can identify whether a pointer is pointing to a valid location.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction", + "line_range": [ + 7, + 7 + ] + }, + { + "text": "Doing this without hardware support introduces significant overheads since the pointer tag needs to be manually removed for every conventional memory operation.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction", + "line_range": [ + 7, + 7 + ] + }, + { + "text": "Pointer masking support reduces these overheads.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction", + "line_range": [ + 7, + 7 + ] + }, + { + "text": "Pointer masking only adds the ability to ignore pointer tags during regular memory accesses.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction", + "line_range": [ + 9, + 9 + ] + }, + { + "text": "The tag checks themselves can be implemented in software or hardware.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction", + "line_range": [ + 9, + 9 + ] + }, + { + "text": "If implemented in software, pointer masking still provides performance benefits since non-checked accesses do not need to transform the address before every memory access.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction", + "line_range": [ + 9, + 9 + ] + }, + { + "text": "Hardware implementations are expected to provide even larger benefits due to performing tag checks out-of-band and hardening security guarantees derived from these checks.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction", + "line_range": [ + 9, + 9 + ] + }, + { + "text": "We anticipate that future extensions may build on pointer masking to support this functionality in hardware.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction", + "line_range": [ + 9, + 9 + ] + }, + { + "text": "It is worth mentioning that while HWASAN is the primary use-case for the current pointer masking extension, a number of other hardware/software features may be implemented leveraging Pointer Masking.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction", + "line_range": [ + 11, + 11 + ] + }, + { + "text": "Some of these use cases include sandboxing, object type checks and garbage collection bits in runtime systems.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction", + "line_range": [ + 11, + 11 + ] + }, + { + "text": "Note that the current version of the spec does not explicitly address these use cases, but future extensions may build on it to do so.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction", + "line_range": [ + 11, + 11 + ] + }, + { + "text": "While we describe the high-level concepts of pointer masking as if it was a single extension, it is, in reality, a family of extensions that implementations or profiles may choose to individually include or exclude (see ).", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction", + "line_range": [ + 13, + 13 + ] + }, + { + "text": "We now define basic terms.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Definitions", + "line_range": [ + 19, + 19 + ] + }, + { + "text": "Note that these rely on the definition of an “ignore” transformation, which is defined in .", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Definitions", + "line_range": [ + 19, + 19 + ] + }, + { + "text": "**Effective address (as defined in the RISC-V Base ISA):** A load/store effective address sent to the memory subsystem (e.g., as generated during the execution of load/store instructions).", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Definitions", + "line_range": [ + 21, + 21 + ] + }, + { + "text": "This does not include addresses corresponding to implicit accesses, such as page-table walks.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Definitions", + "line_range": [ + 21, + 21 + ] + }, + { + "text": "**Masked bits:** The upper PMLEN bits of an address, where PMLEN is a configurable parameter.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Definitions", + "line_range": [ + 23, + 23 + ] + }, + { + "text": "We will use PMLEN consistently throughout this chapter to refer to this parameter.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Definitions", + "line_range": [ + 23, + 23 + ] + }, + { + "text": "**Transformed address:** An effective address after the ignore transformation has been applied.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Definitions", + "line_range": [ + 25, + 25 + ] + }, + { + "text": "**Address translation mode:** The MODE of the currently active address translation scheme as defined in the RISC-V privileged specification.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Definitions", + "line_range": [ + 27, + 27 + ] + }, + { + "text": "This could, for example, refer to Bare, Sv39, Sv48, and Sv57.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Definitions", + "line_range": [ + 27, + 27 + ] + }, + { + "text": "In accordance with the privileged specification, non-Bare translation modes are referred to as virtual-memory schemes.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Definitions", + "line_range": [ + 27, + 27 + ] + }, + { + "text": "For the purpose of this specification, M-mode translation is treated as equivalent to Bare.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Definitions", + "line_range": [ + 27, + 27 + ] + }, + { + "text": "**Address validity:** The RISC-V privileged spec defines validity of addresses based on the address translation mode that is currently in use (e.g., Sv57, Sv48, Sv39, etc.).", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Definitions", + "line_range": [ + 29, + 29 + ] + }, + { + "text": "For a virtual address to be valid, all bits in the unused portion of the address must be the same as the Most Significant Bit (MSB) of the used portion.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Definitions", + "line_range": [ + 29, + 29 + ] + }, + { + "text": "For example, when page-based 48-bit virtual memory (Sv48) is used, load/store effective addresses, which are 64 bits, must have bits 63–48 all set to bit 47, or else a page-fault exception will occur.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Definitions", + "line_range": [ + 29, + 29 + ] + }, + { + "text": "For physical addresses, validity means that bits XLEN-1 to PABITS are zero, where PABITS is the number of physical address bits supported by the processor.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Definitions", + "line_range": [ + 29, + 29 + ] + }, + { + "text": "**NVBITS:** The upper bits within a virtual address that have no effect on addressing memory and are only used for validity checks.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Definitions", + "line_range": [ + 31, + 31 + ] + }, + { + "text": "These bits depend on the currently active address translation mode.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Definitions", + "line_range": [ + 31, + 31 + ] + }, + { + "text": "For example, in Sv48, these are bits 63-48.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Definitions", + "line_range": [ + 31, + 31 + ] + }, + { + "text": "**VBITS:** The bits within a virtual address that affect which memory is addressed.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Definitions", + "line_range": [ + 33, + 33 + ] + }, + { + "text": "These are the bits of an address which are used to index into page tables.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Definitions", + "line_range": [ + 33, + 33 + ] + }, + { + "text": "The ignore transformation differs depending on whether it applies to a virtual or physical address.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > The “Ignore” Transformation", + "line_range": [ + 38, + 38 + ] + }, + { + "text": "For virtual addresses, it replaces the upper PMLEN bits with the sign extension of the PMLEN+1st bit.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > The “Ignore” Transformation", + "line_range": [ + 38, + 38 + ] + }, + { + "text": "[source] .\"Ignore\" Transformation for virtual addresses, expressed in Verilog code. ---- transformedeffectiveaddress = {{PMLEN{effectiveaddress[XLEN-PMLEN-1]}}, effectiveaddress[XLEN-PMLEN-1:0]} ----", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > The “Ignore” Transformation", + "line_range": [ + 40, + 45 + ] + }, + { + "text": "When applied to a physical address, including guest-physical addresses (i.e., all cases except when the active satp register's MODE field != Bare), the ignore transformation replaces the upper PMLEN bits with 0.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > The “Ignore” Transformation", + "line_range": [ + 47, + 47 + ] + }, + { + "text": "This includes both the case of running in M-mode and running in other privilege modes with Bare address translation mode.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > The “Ignore” Transformation", + "line_range": [ + 47, + 47 + ] + }, + { + "text": "[source] .\"Ignore\" Transformation for physical addresses, expressed in Verilog code. ---- transformedeffectiveaddress = {{PMLEN{0}}, effectiveaddress[XLEN-PMLEN-1:0]} ----", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > The “Ignore” Transformation", + "line_range": [ + 49, + 54 + ] + }, + { + "text": "When pointer masking is enabled, the ignore transformation will be applied to every explicit memory access (e.g., loads/stores, atomics operations, and floating point loads/stores).", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > The “Ignore” Transformation", + "line_range": [ + 56, + 56 + ] + }, + { + "text": "The transformation *does not* apply to implicit accesses such as page-table walks or instruction fetches.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > The “Ignore” Transformation", + "line_range": [ + 56, + 56 + ] + }, + { + "text": "The set of accesses that pointer masking applies to is described in .", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > The “Ignore” Transformation", + "line_range": [ + 56, + 56 + ] + }, + { + "text": "[WARNING] Pointer masking does not change the underlying address generation logic or permission checks.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > The “Ignore” Transformation", + "line_range": [ + 58, + 61 + ] + }, + { + "text": "Under a fixed address translation mode, it is semantically equivalent to replacing a subset of instructions (e.g., loads and stores) with an instruction sequence that applies the ignore operation to the target address of this instruction and then applies the instruction to the transformed address.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > The “Ignore” Transformation", + "line_range": [ + 58, + 61 + ] + }, + { + "text": "References to address translation and other implementation details in the text are primarily to explain design decisions and common implementation patterns.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > The “Ignore” Transformation", + "line_range": [ + 58, + 61 + ] + }, + { + "text": "Note that pointer masking is purely an arithmetic operation on the address that makes no assumption about the meaning of the addresses it is applied to.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > The “Ignore” Transformation", + "line_range": [ + 63, + 63 + ] + }, + { + "text": "Pointer masking with the same value of PMLEN always has the same effect for the same type of address (virtual or physical).", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > The “Ignore” Transformation", + "line_range": [ + 63, + 63 + ] + }, + { + "text": "This ensures that code that relies on pointer masking does not need to be aware of the environment it runs in once pointer masking has been enabled, as long as the value of PMLEN is known, and whether or not addresses are virtual or physical.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > The “Ignore” Transformation", + "line_range": [ + 63, + 63 + ] + }, + { + "text": "For example, the same application or library code can run in user mode, supervisor mode or M-mode (with different address translation modes) without modification.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > The “Ignore” Transformation", + "line_range": [ + 63, + 63 + ] + }, + { + "text": "shows an example of the pointer masking transformation on a virtual address when PM is enabled for RV64 under Sv57 (PMLEN=7).", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Example", + "line_range": [ + 67, + 67 + ] + }, + { + "text": ".Example of PM address translation for RV64 under Sv57 | |Page-based profile|Sv57 on RV64 |Effective Address |0xABFFFFFF12345678 + NVBITS[1010101] VBITS[11111111111111111111111110001...000] |PMLEN|7 |Mask|0x01FFFFFFFFFFFFFF + NVBITS[0000000] VBITS[11111111111111111111111111111...111] |PMLEN+1st bit from the top (i.e., bit XLEN-PMLEN-1)|1 |Transformed effective address |0xFFFFFFFF12345678 + NVBITS[1111111] VBITS[11111111111111111111111110001...000]", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Example", + "line_range": [ + 71, + 82 + ] + }, + { + "text": "If the address was a physical address rather than a virtual address with Sv57, the transformed address with PMLEN=7 would be 0x1FFFFFF12345678.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Example", + "line_range": [ + 86, + 86 + ] + }, + { + "text": "From an implementation perspective, ignoring bits is deeply connected to the maximum virtual and physical address space supported by the processor (e.g., Bare, Sv48, Sv57).", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Determining the Value of PMLEN", + "line_range": [ + 90, + 90 + ] + }, + { + "text": "In particular, applying the above transformation is cheap if it covers only bits that are not used by **any** supported address translation mode (as it is equivalent to switching off validity checks).", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Determining the Value of PMLEN", + "line_range": [ + 90, + 90 + ] + }, + { + "text": "Masking NVBITS beyond those bits is more expensive as it requires ignoring them in the TLB tag, and even more expensive if the masked bits extend into the VBITS portion of the address (as it requires performing the actual sign extension).", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Determining the Value of PMLEN", + "line_range": [ + 90, + 90 + ] + }, + { + "text": "Similarly, when running in Bare or M mode, it is common for implementations to not use a particular number of bits at the top of the physical address range and fix them to zero.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Determining the Value of PMLEN", + "line_range": [ + 90, + 90 + ] + }, + { + "text": "Applying the ignore transformation to those bits is cheap as well, since it will result in a valid physical address with all the upper bits fixed to 0.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Determining the Value of PMLEN", + "line_range": [ + 90, + 90 + ] + }, + { + "text": "The current standard only supports PMLEN=XLEN-48 (i.e., PMLEN=16 in RV64) and PMLEN=XLEN-57 (i.e., PMLEN=7 in RV64). A setting has been reserved to potentially support other values of PMLEN in future standards.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Determining the Value of PMLEN", + "line_range": [ + 92, + 92 + ] + }, + { + "text": "In such future standards, different supported values of PMLEN may be defined for each privilege mode (U/VU, S/HS, and M).", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Determining the Value of PMLEN", + "line_range": [ + 92, + 92 + ] + }, + { + "text": "Pointer masking is controlled separately for different privilege modes.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Pointer Masking and Privilege Modes", + "line_range": [ + 96, + 96 + ] + }, + { + "text": "The subset of supported privilege modes is determined by the set of supported pointer masking extensions.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Pointer Masking and Privilege Modes", + "line_range": [ + 96, + 96 + ] + }, + { + "text": "Different privilege modes may have different pointer masking settings active simultaneously and the hardware will automatically apply the pointer masking settings of the currently active privilege mode. A privilege mode's pointer masking setting is configured by bits in configuration registers of the next-higher privilege mode.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Pointer Masking and Privilege Modes", + "line_range": [ + 96, + 96 + ] + }, + { + "text": "Note that the pointer masking setting that is applied only depends on the active privilege mode, not on the address that is being masked.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Pointer Masking and Privilege Modes", + "line_range": [ + 98, + 98 + ] + }, + { + "text": "Some operating systems (e.g., Linux) may use certain bits in the address to disambiguate between different types of addresses (e.g., kernel and user-mode addresses).", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Pointer Masking and Privilege Modes", + "line_range": [ + 98, + 98 + ] + }, + { + "text": "Pointer masking does not take these semantics into account and is purely an arithmetic operation on the address it is given.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Pointer Masking and Privilege Modes", + "line_range": [ + 98, + 98 + ] + }, + { + "text": "Pointer masking applies to all explicit memory accesses.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Memory Accesses Subject to Pointer Masking", + "line_range": [ + 102, + 102 + ] + }, + { + "text": "Currently, in the Base and Privileged ISAs, these are:", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Memory Accesses Subject to Pointer Masking", + "line_range": [ + 102, + 102 + ] + }, + { + "text": "**Base Instruction Set**: LB, LH, LW, LBU, LHU, LWU, LD, SB, SH, SW, SD. * **Atomics**: All instructions in RV32A and RV64A. * **Floating Point**: FLW, FLD, FLQ, FSW, FSD, FSQ. * **Compressed**: All instructions mapping to any of the above, and C.LWSP, C.LDSP, C.FLWSP, C.FLDSP, C.SWSP, C.SDSP, C.FSWSP, C.FSDSP. * **Hypervisor Extension**: HLV.\\*, HSV.* (in some cases; see ). * **Cache Management Operations**: All instructions in Zicbom, Zicbop and Zicboz. * **Vector Extension**: All vector load and store instructions in the ratified RVV 1.0 spec. * **Zicfiss Extension**: SSPUSH, C.SSPUSH, SSPOPCHK, C.SSPOPCHK, SSAMOSWAP.W/D. * **Assorted**: FENCE, FENCE.I (if the currently unused address fields become enabled in the future).", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Memory Accesses Subject to Pointer Masking", + "line_range": [ + 104, + 112 + ] + }, + { + "text": "For other extensions, pointer masking applies to all explicit memory accesses by default.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Memory Accesses Subject to Pointer Masking", + "line_range": [ + 114, + 114 + ] + }, + { + "text": "Future extensions may add specific language to indicate whether particular accesses are or are not included in pointer masking.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Memory Accesses Subject to Pointer Masking", + "line_range": [ + 114, + 114 + ] + }, + { + "text": "MPRV and SPVP affect pointer masking as well, causing the pointer masking settings of the effective privilege mode to be applied.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Memory Accesses Subject to Pointer Masking", + "line_range": [ + 116, + 116 + ] + }, + { + "text": "When MXR is in effect at the effective privilege mode where explicit memory access is performed, pointer masking does not apply.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Memory Accesses Subject to Pointer Masking", + "line_range": [ + 116, + 116 + ] + }, + { + "text": "Pointer masking only applies to accesses generated by instructions on the CPU (including CPU extensions such as an FPU). E.g., it does not apply to accesses generated by page-table walks, the IOMMU, or devices.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Memory Accesses Subject to Pointer Masking", + "line_range": [ + 118, + 118 + ] + }, + { + "text": "Misaligned accesses are supported, subject to the same limitations as in the absence of pointer masking.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Memory Accesses Subject to Pointer Masking", + "line_range": [ + 120, + 120 + ] + }, + { + "text": "The behavior is identical to applying the pointer masking transformation to every constituent aligned memory access.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Memory Accesses Subject to Pointer Masking", + "line_range": [ + 120, + 120 + ] + }, + { + "text": "In other words, the accessed bytes should be identical to the bytes that would be accessed if the pointer masking transformation was individually applied to every byte of the access without pointer masking.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Memory Accesses Subject to Pointer Masking", + "line_range": [ + 120, + 120 + ] + }, + { + "text": "This ensures that both hardware implementations and emulation of misaligned accesses in M-mode behave the same way, and that the M-mode implementation is identical whether or not pointer masking is enabled (e.g., such an implementation may leverage MPRV to apply the correct privilege mode's pointer masking setting).", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Memory Accesses Subject to Pointer Masking", + "line_range": [ + 120, + 120 + ] + }, + { + "text": "No pointer masking operations are applied when software reads/writes to CSRs, including those meant to hold addresses.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Memory Accesses Subject to Pointer Masking", + "line_range": [ + 122, + 122 + ] + }, + { + "text": "If software stores tagged addresses into such CSRs, data load or data store operations based on those addresses are subject to pointer masking only if they are explicit () and pointer masking is enabled for the privilege mode that performs the access.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Memory Accesses Subject to Pointer Masking", + "line_range": [ + 122, + 122 + ] + }, + { + "text": "The implemented WARL width of CSRs is unaffected by pointer masking (e.g., if a CSR supports 52 bits of valid addresses and pointer masking is supported with PMLEN=16, the necessary number of WARL bits remains 52 independently of whether pointer masking is enabled or disabled).", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Memory Accesses Subject to Pointer Masking", + "line_range": [ + 122, + 122 + ] + }, + { + "text": "In contrast to software writes, pointer masking, when applicable, **is applied** for hardware writes to a CSR (e.g., when the hardware writes the transformed address to `stval` when taking an exception).", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Memory Accesses Subject to Pointer Masking", + "line_range": [ + 124, + 124 + ] + }, + { + "text": "Pointer masking is also applied, when applicable, to the memory access address when matching address triggers in debug.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Memory Accesses Subject to Pointer Masking", + "line_range": [ + 124, + 124 + ] + }, + { + "text": "For example, software is free to write a tagged or untagged address to `stvec`, but on trap delivery (e.g., due to an exception or interrupt), pointer masking **will not be applied** to the address of the trap handler.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Memory Accesses Subject to Pointer Masking", + "line_range": [ + 126, + 126 + ] + }, + { + "text": "However, when delivering an exception, the hardware applies pointer masking to any address written into `stval` if pointer masking is applicable to that address.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Memory Accesses Subject to Pointer Masking", + "line_range": [ + 126, + 126 + ] + }, + { + "text": "Pointer masking refers to a number of separate extensions, all of which are privileged.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Pointer Masking Extensions", + "line_range": [ + 131, + 131 + ] + }, + { + "text": "This approach is used to capture optionality of pointer masking features.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Pointer Masking Extensions", + "line_range": [ + 131, + 131 + ] + }, + { + "text": "Profiles and implementations may choose to support an arbitrary subset of these extensions and must define valid ranges for their corresponding values of PMLEN.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Pointer Masking Extensions", + "line_range": [ + 131, + 131 + ] + }, + { + "text": "**Ssnpm**: A supervisor-level extension that provides pointer masking for the next lower privilege mode (U-mode), and for VS- and VU-modes if the H extension is present.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Pointer Masking Extensions", + "line_range": [ + 135, + 137 + ] + }, + { + "text": "See , , , and . * **Smnpm**: A machine-level extension that provides pointer masking for the next lower privilege mode (S/HS if S-mode is implemented, or U-mode otherwise).", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Pointer Masking Extensions", + "line_range": [ + 135, + 137 + ] + }, + { + "text": "See . * **Smmpm**: A machine-level extension that provides pointer masking for M-mode.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Pointer Masking Extensions", + "line_range": [ + 135, + 137 + ] + }, + { + "text": "In addition, the pointer masking standard defines two extensions that describe an execution environment but have no bearing on hardware implementations.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Pointer Masking Extensions", + "line_range": [ + 139, + 139 + ] + }, + { + "text": "These extensions are intended to be used in profile specifications where a User profile or a Supervisor profile can only reference User level or Supervisor level pointer masking functionality, and not the associated CSR controls that exist at a higher privilege level (i.e., in the execution environment).", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Pointer Masking Extensions", + "line_range": [ + 139, + 139 + ] + }, + { + "text": "**Sspm**: An extension that indicates that there is pointer-masking support available in supervisor mode, with some facility provided in the supervisor execution environment to control pointer masking. * **Supm**: An extension that indicates that there is pointer-masking support available in user mode, with some facility provided in the application execution environment to control pointer masking.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Pointer Masking Extensions", + "line_range": [ + 141, + 142 + ] + }, + { + "text": "The precise nature of these facilities is left to the respective execution environment.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Pointer Masking Extensions", + "line_range": [ + 144, + 144 + ] + }, + { + "text": "Pointer masking only applies to RV64.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Pointer Masking Extensions", + "line_range": [ + 146, + 146 + ] + }, + { + "text": "In RV32, trying to enable pointer masking will result in an illegal WARL write and not update the pointer masking configuration bits (see , , , and for details).", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Pointer Masking Extensions", + "line_range": [ + 146, + 146 + ] + }, + { + "text": "The same is the case on RV64 or larger systems when UXL/SXL/MXL is set to 1 for the corresponding privilege mode.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Pointer Masking Extensions", + "line_range": [ + 146, + 146 + ] + }, + { + "text": "Note that in RV32, the CSR bits introduced by pointer masking are still present, for compatibility between RV32 and larger systems with UXL/SXL/MXL set to 1.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Pointer Masking Extensions", + "line_range": [ + 146, + 146 + ] + }, + { + "text": "Setting UXL/SXL/MXL to 1 will clear the corresponding pointer masking configuration bits.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Pointer Masking Extensions", + "line_range": [ + 146, + 146 + ] + }, + { + "text": "As described in , the supported values of PMLEN may depend on the effective privilege mode.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Number of Masked Bits", + "line_range": [ + 150, + 150 + ] + }, + { + "text": "The current standard only defines PMLEN=XLEN-48 and PMLEN=XLEN-57, but this assumption may be relaxed in future extensions and profiles.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Number of Masked Bits", + "line_range": [ + 150, + 150 + ] + }, + { + "text": "Trying to enable pointer masking in an unsupported scenario represents an illegal write to the corresponding pointer masking enable bit and follows WARL semantics.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Number of Masked Bits", + "line_range": [ + 150, + 150 + ] + }, + { + "text": "Future profiles may choose to define certain combinations of privilege modes and supported values of PMLEN as mandatory.", + "section": "Preamble > Pointer Masking Extensions, Version 1.0.0 > Introduction > Background > Number of Masked Bits", + "line_range": [ + 150, + 150 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__profiles__intro.json b/tools/llm-extraction/data/output/raw_chunks/src__profiles__intro.json new file mode 100644 index 0000000000..ac39de7cf8 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__profiles__intro.json @@ -0,0 +1,934 @@ +{ + "source_file": "src/profiles/intro.adoc", + "total": 116, + "sentences": [ + { + "text": "RISC-V was designed to provide a highly modular and extensible instruction set, and includes a large and growing set of standard extensions.", + "section": "Preamble > Introduction", + "line_range": [ + 2, + 12 + ] + }, + { + "text": "In addition, users may add their own custom extensions.", + "section": "Preamble > Introduction", + "line_range": [ + 2, + 12 + ] + }, + { + "text": "This flexibility can be used to highly optimize a specialized design by including only the exact set of ISA features required for an application, but the same flexibility also leads to a combinatorial explosion in possible ISA choices.", + "section": "Preamble > Introduction", + "line_range": [ + 2, + 12 + ] + }, + { + "text": "Profiles specify a much smaller common set of ISA choices that capture the most value for most users, and which thereby enable the software community to focus resources on building a rich software ecosystem with application and operating system portability across different implementations.", + "section": "Preamble > Introduction", + "line_range": [ + 2, + 12 + ] + }, + { + "text": "NOTE: Another pragmatic concern is the long and unwieldy ISA strings required to encode common sets of extensions, which will continue to grow as new extensions are defined.", + "section": "Preamble > Introduction", + "line_range": [ + 14, + 16 + ] + }, + { + "text": "Each profile is built on a standard base ISA plus a set of mandatory ISA extensions, and provides a small set of standard ISA options to extend the mandatory components.", + "section": "Preamble > Introduction", + "line_range": [ + 18, + 29 + ] + }, + { + "text": "Profiles provide a convenient shorthand for describing the ISA portions of hardware and software platforms, and also guide the development of common software toolchains shared by different platforms that use the same profile.", + "section": "Preamble > Introduction", + "line_range": [ + 18, + 29 + ] + }, + { + "text": "The intent is that the software ecosystem focus on supporting the profiles' mandatory base and standard options, instead of attempting to support every possible combination of individual extensions.", + "section": "Preamble > Introduction", + "line_range": [ + 18, + 29 + ] + }, + { + "text": "Similarly, hardware vendors should aim to structure their offerings around standard profiles to increase the likelihood their designs will have mainstream software support.", + "section": "Preamble > Introduction", + "line_range": [ + 18, + 29 + ] + }, + { + "text": "NOTE: Profiles are not intended to prohibit the use of combinations of individual ISA extensions or the addition of custom extensions, which can continue to be used for more specialized applications albeit without the expectation of widespread software support or portability between hardware platforms.", + "section": "Preamble > Introduction", + "line_range": [ + 31, + 35 + ] + }, + { + "text": "NOTE: As RISC-V evolves over time, the set of ISA features will grow, and new platforms will be added that may need different profiles.", + "section": "Preamble > Introduction", + "line_range": [ + 37, + 43 + ] + }, + { + "text": "To manage this evolution, RISC-V is adopting a model of regular annual releases of new ISA profiles, following an ISA roadmap managed by the RISC-V Technical Steering Committee.", + "section": "Preamble > Introduction", + "line_range": [ + 37, + 43 + ] + }, + { + "text": "The architecture profiles will also be used for branding and to advertise compatibility with the RISC-V standard.", + "section": "Preamble > Introduction", + "line_range": [ + 37, + 43 + ] + }, + { + "text": "This volume describes the general structure of RISC-V architecture profiles and also the specifics of the officially defined profiles.", + "section": "Preamble > Introduction", + "line_range": [ + 45, + 46 + ] + }, + { + "text": "Profiles only describe ISA features, not a complete execution environment.", + "section": "Preamble > Introduction > Profiles versus Platforms", + "line_range": [ + 50, + 51 + ] + }, + { + "text": "A software platform is a specification for an execution environment, in which software targeted for that software platform can run.", + "section": "Preamble > Introduction > Profiles versus Platforms", + "line_range": [ + 53, + 55 + ] + }, + { + "text": "A hardware platform is a specification for a hardware system (which can be viewed as a physical realization of an execution environment).", + "section": "Preamble > Introduction > Profiles versus Platforms", + "line_range": [ + 57, + 59 + ] + }, + { + "text": "Both software and hardware platforms include specifications for many features beyond details of the ISA used by RISC-V harts in the platform (e.g., boot process, calling convention, behavior of environment calls, discovery mechanism, presence of certain memory-mapped hardware devices, etc.).", + "section": "Preamble > Introduction > Profiles versus Platforms", + "line_range": [ + 61, + 69 + ] + }, + { + "text": "Architecture profiles factor out ISA-specific definitions from platform definitions to allow ISA profiles to be reused across different platforms, and to be used by tools (e.g., compilers) that are common across many different platforms.", + "section": "Preamble > Introduction > Profiles versus Platforms", + "line_range": [ + 61, + 69 + ] + }, + { + "text": "A platform can add additional constraints on top of those in a profile.", + "section": "Preamble > Introduction > Profiles versus Platforms", + "line_range": [ + 71, + 75 + ] + }, + { + "text": "For example, mandating an extension that is a standard option in the underlying profile, or constraining some implementation-specific parameter in the profile to lie within a certain range.", + "section": "Preamble > Introduction > Profiles versus Platforms", + "line_range": [ + 71, + 75 + ] + }, + { + "text": "A platform cannot remove mandates or reduce other requirements in a profile.", + "section": "Preamble > Introduction > Profiles versus Platforms", + "line_range": [ + 77, + 78 + ] + }, + { + "text": "NOTE: A new profile should be proposed if existing profiles do not match the needs of a new platform.", + "section": "Preamble > Introduction > Profiles versus Platforms", + "line_range": [ + 80, + 81 + ] + }, + { + "text": "Every profile is a member of a profile family. A profile family is a set of profiles that share the same base ISA but which vary in highest-supported privilege mode.", + "section": "Preamble > Introduction > Components of a Profile > Profile Family", + "line_range": [ + 87, + 90 + ] + }, + { + "text": "The profile families defined in this volume are:", + "section": "Preamble > Introduction > Components of a Profile > Profile Family", + "line_range": [ + 87, + 90 + ] + }, + { + "text": "Generic unprivileged instructions (I) - Application processors running rich operating systems with binary software ecosystems (A) - Application processors running rich operating systems with rooms for customization (B)", + "section": "Preamble > Introduction > Components of a Profile > Profile Family", + "line_range": [ + 92, + 96 + ] + }, + { + "text": "NOTE: More profile families may be added over time.", + "section": "Preamble > Introduction > Components of a Profile > Profile Family", + "line_range": [ + 98, + 98 + ] + }, + { + "text": "A profile family may be updated no more than annually, and the release calendar year is treated as part of the profile family name.", + "section": "Preamble > Introduction > Components of a Profile > Profile Family", + "line_range": [ + 100, + 101 + ] + }, + { + "text": "Each profile family is described in more detail below.", + "section": "Preamble > Introduction > Components of a Profile > Profile Family", + "line_range": [ + 103, + 103 + ] + }, + { + "text": "RISC-V has a layered architecture supporting multiple privilege modes, and most RISC-V platforms support more than one privilege mode.", + "section": "Preamble > Introduction > Components of a Profile > Profile Privilege Mode", + "line_range": [ + 107, + 112 + ] + }, + { + "text": "Software is usually written assuming a particular privilege mode during execution.", + "section": "Preamble > Introduction > Components of a Profile > Profile Privilege Mode", + "line_range": [ + 107, + 112 + ] + }, + { + "text": "For example, application code is written assuming it will be run in user mode, and kernel code is written assuming it will be run in supervisor mode.", + "section": "Preamble > Introduction > Components of a Profile > Profile Privilege Mode", + "line_range": [ + 107, + 112 + ] + }, + { + "text": "NOTE: Software can be run in a mode different than the one for which it was written.", + "section": "Preamble > Introduction > Components of a Profile > Profile Privilege Mode", + "line_range": [ + 114, + 120 + ] + }, + { + "text": "For example, privileged code using privileged ISA features can be run in a user-mode execution environment, but will then cause traps into the enclosing execution environment when privileged instructions are executed.", + "section": "Preamble > Introduction > Components of a Profile > Profile Privilege Mode", + "line_range": [ + 114, + 120 + ] + }, + { + "text": "This behavior might be exploited, for example, to emulate a privileged execution environment using a user-mode execution environment.", + "section": "Preamble > Introduction > Components of a Profile > Profile Privilege Mode", + "line_range": [ + 114, + 120 + ] + }, + { + "text": "The profile for a privilege mode describes the ISA features for an execution environment that has the eponymous privilege mode as the most-privileged mode available, but also includes all supported lower-privilege modes.", + "section": "Preamble > Introduction > Components of a Profile > Profile Privilege Mode", + "line_range": [ + 122, + 132 + ] + }, + { + "text": "In general, available instructions vary by privilege mode, and the behavior of RISC-V instructions can depend on the current privilege mode.", + "section": "Preamble > Introduction > Components of a Profile > Profile Privilege Mode", + "line_range": [ + 122, + 132 + ] + }, + { + "text": "For example, an S-mode profile includes U-mode as well as S-mode and describes the behavior of instructions when running in different modes in an S-mode execution environment, such as how an `ecall` instruction in U-mode causes a contained trap into an S-mode handler whereas an `ecall` in S-mode causes a requested trap out to the execution environment.", + "section": "Preamble > Introduction > Components of a Profile > Profile Privilege Mode", + "line_range": [ + 122, + 132 + ] + }, + { + "text": "A profile may specify that certain conditions will cause a requested trap (such as an `ecall` made in the highest-supported privilege mode) or fatal trap to the enclosing execution environment.", + "section": "Preamble > Introduction > Components of a Profile > Profile Privilege Mode", + "line_range": [ + 134, + 138 + ] + }, + { + "text": "The profile does not specify the behavior of the enclosing execution environment in handling requested or fatal traps.", + "section": "Preamble > Introduction > Components of a Profile > Profile Privilege Mode", + "line_range": [ + 134, + 138 + ] + }, + { + "text": "NOTE: In particular, a profile does not specify the set of ECALLs available in the outer execution environment.", + "section": "Preamble > Introduction > Components of a Profile > Profile Privilege Mode", + "line_range": [ + 140, + 143 + ] + }, + { + "text": "This should be documented in the appropriate binary interface to the outer execution environment (e.g., Linux user ABI, or RISC-V SEE).", + "section": "Preamble > Introduction > Components of a Profile > Profile Privilege Mode", + "line_range": [ + 140, + 143 + ] + }, + { + "text": "NOTE: In general, a profile can be implemented by an execution environment using any hardware or software technique that provides compatible functionality, including pure software emulation.", + "section": "Preamble > Introduction > Components of a Profile > Profile Privilege Mode", + "line_range": [ + 145, + 147 + ] + }, + { + "text": "A profile does not specify any invisible traps.", + "section": "Preamble > Introduction > Components of a Profile > Profile Privilege Mode", + "line_range": [ + 149, + 149 + ] + }, + { + "text": "NOTE: In particular, a profile does not constrain how invisible traps to a more-privileged mode can be used to emulate profile features.", + "section": "Preamble > Introduction > Components of a Profile > Profile Privilege Mode", + "line_range": [ + 151, + 152 + ] + }, + { + "text": "A more-privileged profile can always support running software to implement a less-privileged profile from the same profile family.", + "section": "Preamble > Introduction > Components of a Profile > Profile Privilege Mode", + "line_range": [ + 154, + 158 + ] + }, + { + "text": "For example, a platform supporting the S-mode profile can run a supervisor-mode operating system that provides user-mode execution environments supporting the U-mode profile.", + "section": "Preamble > Introduction > Components of a Profile > Profile Privilege Mode", + "line_range": [ + 154, + 158 + ] + }, + { + "text": "NOTE: Instructions in a U-mode profile, which are all executed in user mode, have potentially different behaviors than instructions executed in user mode in an S-mode profile.", + "section": "Preamble > Introduction > Components of a Profile > Profile Privilege Mode", + "line_range": [ + 160, + 163 + ] + }, + { + "text": "For this reason, a U-mode profile cannot be considered a subset of an S-mode profile.", + "section": "Preamble > Introduction > Components of a Profile > Profile Privilege Mode", + "line_range": [ + 160, + 163 + ] + }, + { + "text": "An architecture profile has a mandatory ratified base instruction set (RV32I or RV64I for the current profiles).", + "section": "Preamble > Introduction > Components of a Profile > Profile ISA Features", + "line_range": [ + 167, + 169 + ] + }, + { + "text": "The profile also includes ratified ISA extensions placed into two categories:", + "section": "Preamble > Introduction > Components of a Profile > Profile ISA Features", + "line_range": [ + 167, + 169 + ] + }, + { + "text": "As the name implies, Mandatory ISA extensions are a required part of the profile.", + "section": "Preamble > Introduction > Components of a Profile > Profile ISA Features", + "line_range": [ + 174, + 178 + ] + }, + { + "text": "Implementations of the profile must provide these.", + "section": "Preamble > Introduction > Components of a Profile > Profile ISA Features", + "line_range": [ + 174, + 178 + ] + }, + { + "text": "The combination of the profile base ISA plus the mandatory ISA extensions are termed the profile mandates, and software using the profile can assume these always exist.", + "section": "Preamble > Introduction > Components of a Profile > Profile ISA Features", + "line_range": [ + 174, + 178 + ] + }, + { + "text": "The Optional category (also known as options) contains extensions that may be added as options, and which are expected to be generally supported as options by the software ecosystem for this profile.", + "section": "Preamble > Introduction > Components of a Profile > Profile ISA Features", + "line_range": [ + 180, + 182 + ] + }, + { + "text": "NOTE: The level of \"support\" for an Optional extension will likely vary greatly among different software components supporting a profile.", + "section": "Preamble > Introduction > Components of a Profile > Profile ISA Features", + "line_range": [ + 184, + 189 + ] + }, + { + "text": "Users would expect that software claiming compatibility with a profile would make use of any available supported options, but as a bare minimum software should not report errors or warnings when supported options are present in a system.", + "section": "Preamble > Introduction > Components of a Profile > Profile ISA Features", + "line_range": [ + 184, + 189 + ] + }, + { + "text": "An optional extension may comprise many individually named and ratified extensions but a profile option requires all constituent extensions are present.", + "section": "Preamble > Introduction > Components of a Profile > Profile ISA Features", + "line_range": [ + 191, + 197 + ] + }, + { + "text": "In particular, unless explicitly listed as a profile option, individual extensions are not by themselves a profile option even when required as part of a profile option.", + "section": "Preamble > Introduction > Components of a Profile > Profile ISA Features", + "line_range": [ + 191, + 197 + ] + }, + { + "text": "For example, the Zbkb extension is not by itself a profile option even though it is a required component of the Zkn option.", + "section": "Preamble > Introduction > Components of a Profile > Profile ISA Features", + "line_range": [ + 191, + 197 + ] + }, + { + "text": "NOTE: Profile optional extensions are intended to capture the granularity at which the broad software ecosystem is expected to cope with combinations of extensions.", + "section": "Preamble > Introduction > Components of a Profile > Profile ISA Features", + "line_range": [ + 199, + 201 + ] + }, + { + "text": "All components of a ratified profile must themselves have been ratified.", + "section": "Preamble > Introduction > Components of a Profile > Profile ISA Features", + "line_range": [ + 203, + 204 + ] + }, + { + "text": "Platforms may provide a discovery mechanism to determine what optional extensions are present.", + "section": "Preamble > Introduction > Components of a Profile > Profile ISA Features", + "line_range": [ + 206, + 207 + ] + }, + { + "text": "Extensions that are not explicitly listed in the mandatory or optional categories are termed non-profile extensions, and are not considered parts of the profile.", + "section": "Preamble > Introduction > Components of a Profile > Profile ISA Features", + "line_range": [ + 209, + 218 + ] + }, + { + "text": "Some non-profile extensions can be added to an implementation without conflicting with the mandatory or optional components of a profile.", + "section": "Preamble > Introduction > Components of a Profile > Profile ISA Features", + "line_range": [ + 209, + 218 + ] + }, + { + "text": "In this case, the implementation is still compatible with the profile even though additional non-profile extensions are present.", + "section": "Preamble > Introduction > Components of a Profile > Profile ISA Features", + "line_range": [ + 209, + 218 + ] + }, + { + "text": "Other non-profile extensions added to an implementation might alter or conflict with the behavior of the mandatory or optional extensions in a profile, in which case the implementation would not be compatible with the profile.", + "section": "Preamble > Introduction > Components of a Profile > Profile ISA Features", + "line_range": [ + 209, + 218 + ] + }, + { + "text": "NOTE: Extensions that are released after a given profile is released are by definition non-profile extensions.", + "section": "Preamble > Introduction > Components of a Profile > Profile ISA Features", + "line_range": [ + 220, + 223 + ] + }, + { + "text": "For example, mandatory or optional profile extensions for a new profile might be prototyped as non-profile extensions on an earlier profile.", + "section": "Preamble > Introduction > Components of a Profile > Profile ISA Features", + "line_range": [ + 220, + 223 + ] + }, + { + "text": "A profile name is a string comprised of, in order:", + "section": "Preamble > Introduction > Components of a Profile > Profile Naming Convention", + "line_range": [ + 227, + 227 + ] + }, + { + "text": "Prefix *RV* for RISC-V. . A specific profile family name string.", + "section": "Preamble > Introduction > Components of a Profile > Profile Naming Convention", + "line_range": [ + 229, + 237 + ] + }, + { + "text": "Currently a single letter (*I*, *A*, or *B*), but later profiles may have longer family name strings. . A numeric string giving the first complete calendar year for which the profile is ratified, represented as number of years after year 2000, i.e., *20* for profiles built on specifications ratified during 2019.", + "section": "Preamble > Introduction > Components of a Profile > Profile Naming Convention", + "line_range": [ + 229, + 237 + ] + }, + { + "text": "The year string will be longer than two digits in the next century. . A privilege mode (*U*, *S*, *M*).", + "section": "Preamble > Introduction > Components of a Profile > Profile Naming Convention", + "line_range": [ + 229, + 237 + ] + }, + { + "text": "Hypervisor support is treated as an option. . A base ISA XLEN specifier (*32*, *64*).", + "section": "Preamble > Introduction > Components of a Profile > Profile Naming Convention", + "line_range": [ + 229, + 237 + ] + }, + { + "text": "The initial profiles based on specifications ratified in 2019 are:", + "section": "Preamble > Introduction > Components of a Profile > Profile Naming Convention", + "line_range": [ + 239, + 239 + ] + }, + { + "text": "RVI20U32 basic unprivileged instructions for RV32I - RVI20U64 basic unprivileged instructions for RV64I - RVA20U64, RVA20S64 64-bit application-processor profiles", + "section": "Preamble > Introduction > Components of a Profile > Profile Naming Convention", + "line_range": [ + 241, + 243 + ] + }, + { + "text": "NOTE: Profile names are embeddable into RISC-V ISA naming strings.", + "section": "Preamble > Introduction > Components of a Profile > Profile Naming Convention", + "line_range": [ + 245, + 249 + ] + }, + { + "text": "This implies that there will be no standard ISA extension with a name that matches the profile naming convention.", + "section": "Preamble > Introduction > Components of a Profile > Profile Naming Convention", + "line_range": [ + 245, + 249 + ] + }, + { + "text": "This allows tools that process the RISC-V ISA naming string to parse and/or process a combined string.", + "section": "Preamble > Introduction > Components of a Profile > Profile Naming Convention", + "line_range": [ + 245, + 249 + ] + }, + { + "text": "RISC-V was designed to provide a highly modular and extensible instruction set and includes a large and growing set of standard extensions, where each standard extension is a bundle of instruction-set features.", + "section": "Preamble > Introduction > Components of a Profile > RVA Profiles Rationale", + "line_range": [ + 253, + 266 + ] + }, + { + "text": "This is no different than other industry ISAs that continue to add new ISA features.", + "section": "Preamble > Introduction > Components of a Profile > RVA Profiles Rationale", + "line_range": [ + 253, + 266 + ] + }, + { + "text": "Unlike other ISAs, however, RISC-V has a broad set of contributors and implementers, and also allows users to add their own custom extensions.", + "section": "Preamble > Introduction > Components of a Profile > RVA Profiles Rationale", + "line_range": [ + 253, + 266 + ] + }, + { + "text": "For some deep embedded markets, highly customized processor configurations are desirable for efficiency, and all software is compiled, ported, and/or developed in-house by the same organization for that specific processor configuration.", + "section": "Preamble > Introduction > Components of a Profile > RVA Profiles Rationale", + "line_range": [ + 253, + 266 + ] + }, + { + "text": "However, for other markets that expect a substantial fraction of software to be delivered to end-customers in binary form, compatibility across multiple implementations from different RISC-V vendors is required.", + "section": "Preamble > Introduction > Components of a Profile > RVA Profiles Rationale", + "line_range": [ + 253, + 266 + ] + }, + { + "text": "The RISC-V International ISA extension ratification process ensures that all processor vendors have agreed to the specification of a standard extension if present.", + "section": "Preamble > Introduction > Components of a Profile > RVA Profiles Rationale", + "line_range": [ + 268, + 272 + ] + }, + { + "text": "However, by themselves, the ISA extension specifications do not guarantee that a certain set of standard extensions will be present in all implementations.", + "section": "Preamble > Introduction > Components of a Profile > RVA Profiles Rationale", + "line_range": [ + 268, + 272 + ] + }, + { + "text": "*The primary goal of the RVA profiles is to align processor vendors targeting binary software markets, so software can rely on the existence of a certain set of ISA features in a particular generation of RISC-V implementations.*", + "section": "Preamble > Introduction > Components of a Profile > RVA Profiles Rationale", + "line_range": [ + 274, + 277 + ] + }, + { + "text": "Alignment is not only for compatibility, but also to ensure RISC-V is competitive in these markets.", + "section": "Preamble > Introduction > Components of a Profile > RVA Profiles Rationale", + "line_range": [ + 279, + 294 + ] + }, + { + "text": "The binary app markets are also generally those with the most competitive performance requirements (e.g., mobile, client, server). RISC-V International cannot mandate the ISA features that a RISC-V binary software ecosystem should use, as each ecosystem will typically select the lowest-common denominator they empirically observe in the deployed devices in their target markets.", + "section": "Preamble > Introduction > Components of a Profile > RVA Profiles Rationale", + "line_range": [ + 279, + 294 + ] + }, + { + "text": "But we can align hardware vendors to support a common set of features in each generation through the RVA profiles.", + "section": "Preamble > Introduction > Components of a Profile > RVA Profiles Rationale", + "line_range": [ + 279, + 294 + ] + }, + { + "text": "Without proactive alignment through RVA profiles, RISC-V will be uncompetitive, as even if a particular vendor implements a certain feature, if other vendors do not, then binary distributions will not generally use that feature and all implementations will suffer.", + "section": "Preamble > Introduction > Components of a Profile > RVA Profiles Rationale", + "line_range": [ + 279, + 294 + ] + }, + { + "text": "While certain features may be discoverable, and alternate code provided in case of presence/absence of a feature, the added cost to support such options is only justified for certain limited cases, and binary app markets will not support a wide range of optional features, particularly for the nascent RISC-V binary app ecosystems.", + "section": "Preamble > Introduction > Components of a Profile > RVA Profiles Rationale", + "line_range": [ + 279, + 294 + ] + }, + { + "text": "To maintain alignment and increase RISC-V competitiveness over time, the mandatory set of extensions must increase over time in successive generations of RVA profile. (RVA profiles may eventually have to deprecate previously mandatory instructions, but that is unlikely in the near future.) Note that the RISC-V ISA will continue to evolve, regardless of whether a given software ecosystem settles on a certain generation of profile as the baseline for their ecosystem for many years or even decades.", + "section": "Preamble > Introduction > Components of a Profile > RVA Profiles Rationale", + "line_range": [ + 296, + 309 + ] + }, + { + "text": "There are many existing binary software ecosystems, which will migrate to RISC-V and evolve at different rates, and more new ones will doubtless be created over the hopefully long lifetime of RISC-V.", + "section": "Preamble > Introduction > Components of a Profile > RVA Profiles Rationale", + "line_range": [ + 296, + 309 + ] + }, + { + "text": "High-performance application processors require considerable investment, and no single binary app ecosystem can justify the development costs of these processors, especially for RISC-V in its early stage of adoption.", + "section": "Preamble > Introduction > Components of a Profile > RVA Profiles Rationale", + "line_range": [ + 296, + 309 + ] + }, + { + "text": "While the heart of the profile is the set of mandatory extensions, there are several kinds of optional extension that serve important roles in the profile.", + "section": "Preamble > Introduction > Components of a Profile > RVA Profiles Rationale", + "line_range": [ + 311, + 313 + ] + }, + { + "text": "The first kind are localized options, whose presence or use necessarily differs along geo-political and/or jurisdictional boundaries, with crypto being the obvious example.", + "section": "Preamble > Introduction > Components of a Profile > RVA Profiles Rationale", + "line_range": [ + 315, + 321 + ] + }, + { + "text": "These will always be optional.", + "section": "Preamble > Introduction > Components of a Profile > RVA Profiles Rationale", + "line_range": [ + 315, + 321 + ] + }, + { + "text": "At least for crypto, discovery has been found to be perfectly acceptable to handle this optionality on other architectures, as the use of the extensions is well contained in certain libraries.", + "section": "Preamble > Introduction > Components of a Profile > RVA Profiles Rationale", + "line_range": [ + 315, + 321 + ] + }, + { + "text": "The second kind of optional extension is a development option, which represents a new ISA extension in an early part of its lifecycle but which is intended to become mandatory in a later generation of the RVA profile.", + "section": "Preamble > Introduction > Components of a Profile > RVA Profiles Rationale", + "line_range": [ + 323, + 333 + ] + }, + { + "text": "Processor vendors and software toolchain providers will have varying development schedules, and providing an optional phase in a new extension's lifecycle provides some flexibility while maintaining overall alignment, and is particularly appropriate when hardware or software development for the extension is complex.", + "section": "Preamble > Introduction > Components of a Profile > RVA Profiles Rationale", + "line_range": [ + 323, + 333 + ] + }, + { + "text": "Denoting an extension as a development option signals to the community that development should be prioritized for such extensions as they will become mandatory.", + "section": "Preamble > Introduction > Components of a Profile > RVA Profiles Rationale", + "line_range": [ + 323, + 333 + ] + }, + { + "text": "The third kind of optional extension are expansion options, which are those that may have a large implementation cost but are not always needed in a particular platform, and which can be readily handled by discovery.", + "section": "Preamble > Introduction > Components of a Profile > RVA Profiles Rationale", + "line_range": [ + 335, + 345 + ] + }, + { + "text": "These are also intended to remain available as expansion options in future versions of the profile.", + "section": "Preamble > Introduction > Components of a Profile > RVA Profiles Rationale", + "line_range": [ + 335, + 345 + ] + }, + { + "text": "Several supervisor-mode extensions fall into this category, e.g., Sv57, which has a notable PPA impact over Sv48 and is not needed on smaller platforms.", + "section": "Preamble > Introduction > Components of a Profile > RVA Profiles Rationale", + "line_range": [ + 335, + 345 + ] + }, + { + "text": "Some unprivileged extensions that may fall into this category are possible future matrix extensions.", + "section": "Preamble > Introduction > Components of a Profile > RVA Profiles Rationale", + "line_range": [ + 335, + 345 + ] + }, + { + "text": "These have large implementation costs, and use of matrix instructions can be readily supported with discovery and alternate math libraries.", + "section": "Preamble > Introduction > Components of a Profile > RVA Profiles Rationale", + "line_range": [ + 335, + 345 + ] + }, + { + "text": "The fourth kind of optional extensions are transitory options, where it is not clear if the extension will change to a mandatory, localized, or expansion option, or be possibly dropped over time.", + "section": "Preamble > Introduction > Components of a Profile > RVA Profiles Rationale", + "line_range": [ + 347, + 359 + ] + }, + { + "text": "Cryptography provides some examples where earlier cyphers have been broken and are now deprecated.", + "section": "Preamble > Introduction > Components of a Profile > RVA Profiles Rationale", + "line_range": [ + 347, + 359 + ] + }, + { + "text": "We used this mechanism to enable scalar crypto until vector crypto was ready.", + "section": "Preamble > Introduction > Components of a Profile > RVA Profiles Rationale", + "line_range": [ + 347, + 359 + ] + }, + { + "text": "Software security features may also be in this category, with examples of deprecated security features occuring in other architectures.", + "section": "Preamble > Introduction > Components of a Profile > RVA Profiles Rationale", + "line_range": [ + 347, + 359 + ] + }, + { + "text": "As another example, the recent avalanche of new numeric datatypes for AI/ML may eventually subside with a few survivors actually being used longer term.", + "section": "Preamble > Introduction > Components of a Profile > RVA Profiles Rationale", + "line_range": [ + 347, + 359 + ] + }, + { + "text": "Denoting an option as transitory signals to the community that this extension may be removed in a future profile, though the time scale may span many years.", + "section": "Preamble > Introduction > Components of a Profile > RVA Profiles Rationale", + "line_range": [ + 347, + 359 + ] + }, + { + "text": "Except for the localized options, it could be argued that other three kinds of option could be left out of profiles.", + "section": "Preamble > Introduction > Components of a Profile > RVA Profiles Rationale", + "line_range": [ + 361, + 370 + ] + }, + { + "text": "Binary distributions of applications willing to invest in discovery can use an optional extension, and customers compiling their own applications can take advantage of the feature on a particular implementation, even when that system is mostly running binary distributions that ignore the new extension.", + "section": "Preamble > Introduction > Components of a Profile > RVA Profiles Rationale", + "line_range": [ + 361, + 370 + ] + }, + { + "text": "However, there is value in providing guidance to align hardware vendors and software developers around what extensions are worth implementing and worth discovering, by designating only a few important features as profile options and limiting their granularity.", + "section": "Preamble > Introduction > Components of a Profile > RVA Profiles Rationale", + "line_range": [ + 361, + 370 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__profiles__preface.json b/tools/llm-extraction/data/output/raw_chunks/src__profiles__preface.json new file mode 100644 index 0000000000..69b8cbd17a --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__profiles__preface.json @@ -0,0 +1,78 @@ +{ + "source_file": "src/profiles/preface.adoc", + "total": 9, + "sentences": [ + { + "text": "This document describes the RISC-V architecture profiles.", + "section": "Preamble > Preface", + "line_range": [ + 3, + 5 + ] + }, + { + "text": "It contains the following profiles, all of which have been ratified:", + "section": "Preamble > Preface", + "line_range": [ + 3, + 5 + ] + }, + { + "text": "| |Profile |*RVI20U32* |*RVI20U64* |*RVA20U64* |*RVA20S64* |*RVA22U64* |*RVA22S64* |*RVA23U64* |*RVA23S64* |*RVB23U64* |*RVB23S64* |", + "section": "Preamble > Preface", + "line_range": [ + 7, + 20 + ] + }, + { + "text": "[.big]*Changes made since ratification of RVA23 and RVB23 profiles*", + "section": "Preamble > Preface", + "line_range": [ + 22, + 22 + ] + }, + { + "text": "Removed outdated text in existing profiles - Removed duplicated definitions of Sha", + "section": "Preamble > Preface", + "line_range": [ + 24, + 25 + ] + }, + { + "text": "[.big]*Changes made since ratification of RVA22 profiles*", + "section": "Preamble > Preface", + "line_range": [ + 27, + 27 + ] + }, + { + "text": "Clarified that Zihpm was optional in RVA20U64 and became mandatory in RVA22U64", + "section": "Preamble > Preface", + "line_range": [ + 29, + 29 + ] + }, + { + "text": "[.big]*Changes made since public review of RVA22 profiles*", + "section": "Preamble > Preface", + "line_range": [ + 31, + 31 + ] + }, + { + "text": "Clarified that profile name can be used as ISA base string - Renamed Ssptead to Svade - Fixed Ssu64xl to make supporting UXL=64 mandatory - Added section listing new extension names in profiles document - Added new extension name Sscounterenw - Removed outdated text on Zicntr/Zihpm ratification plan", + "section": "Preamble > Preface", + "line_range": [ + 33, + 38 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__profiles__profiles.json b/tools/llm-extraction/data/output/raw_chunks/src__profiles__profiles.json new file mode 100644 index 0000000000..ce17099c46 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__profiles__profiles.json @@ -0,0 +1,5 @@ +{ + "source_file": "src/profiles/profiles.adoc", + "total": 0, + "sentences": [] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__profiles__rva20.json b/tools/llm-extraction/data/output/raw_chunks/src__profiles__rva20.json new file mode 100644 index 0000000000..06ca0712f6 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__profiles__rva20.json @@ -0,0 +1,486 @@ +{ + "source_file": "src/profiles/rva20.adoc", + "total": 60, + "sentences": [ + { + "text": "The RVA20 profiles are intended to be used for 64-bit application processors running rich OS stacks.", + "section": "Preamble > RVA20 Profiles", + "line_range": [ + 2, + 4 + ] + }, + { + "text": "Only user-mode (RVA20U64) and supervisor-mode (RVA20S64) profiles are specified in this family.", + "section": "Preamble > RVA20 Profiles", + "line_range": [ + 2, + 4 + ] + }, + { + "text": "NOTE: There is no machine-mode profile currently defined for application processor families. A machine-mode profile for application processors would only be used in specifying platforms for portable machine-mode software.", + "section": "Preamble > RVA20 Profiles", + "line_range": [ + 6, + 13 + ] + }, + { + "text": "Given the relatively low volume of portable M-mode software in this domain, the wide variety of potential M-mode code, and the very specific needs of each type of M-mode software, we are not specifying individual M-mode ISA requirements in the A-family profiles.", + "section": "Preamble > RVA20 Profiles", + "line_range": [ + 6, + 13 + ] + }, + { + "text": "NOTE: Only XLEN=64 application processor profiles are currently defined.", + "section": "Preamble > RVA20 Profiles", + "line_range": [ + 15, + 17 + ] + }, + { + "text": "It would be possible to also define very similar XLEN=32 variants.", + "section": "Preamble > RVA20 Profiles", + "line_range": [ + 15, + 17 + ] + }, + { + "text": "The RVA20U64 profile specifies the ISA features available to user-mode execution environments in 64-bit applications processors.", + "section": "Preamble > RVA20 Profiles > RVA20U64 Profile", + "line_range": [ + 21, + 24 + ] + }, + { + "text": "This is the most important profile within the application processor family in terms of the amount of software that targets this profile.", + "section": "Preamble > RVA20 Profiles > RVA20U64 Profile", + "line_range": [ + 21, + 24 + ] + }, + { + "text": "RVA20U64 has one optional extension (Zihpm).", + "section": "Preamble > RVA20 Profiles > RVA20U64 Profile", + "line_range": [ + 26, + 26 + ] + }, + { + "text": "RV64I is the mandatory base ISA for RVA20U64, and is little-endian.", + "section": "Preamble > RVA20 Profiles > RVA20U64 Profile > RVA20U64 Mandatory Base", + "line_range": [ + 30, + 30 + ] + }, + { + "text": "As per the unprivileged architecture specification, the `ecall` instruction causes a requested trap to the execution environment.", + "section": "Preamble > RVA20 Profiles > RVA20U64 Profile > RVA20U64 Mandatory Base", + "line_range": [ + 32, + 33 + ] + }, + { + "text": "The `fence.tso` instruction is mandatory.", + "section": "Preamble > RVA20 Profiles > RVA20U64 Profile > RVA20U64 Mandatory Base", + "line_range": [ + 35, + 35 + ] + }, + { + "text": "NOTE: The `fence.tso` instruction was incorrectly described as optional in the 2019 ratified specifications.", + "section": "Preamble > RVA20 Profiles > RVA20U64 Profile > RVA20U64 Mandatory Base", + "line_range": [ + 37, + 39 + ] + }, + { + "text": "Later versions of correctly indicate that the instruction is mandatory.", + "section": "Preamble > RVA20 Profiles > RVA20U64 Profile > RVA20U64 Mandatory Base", + "line_range": [ + 37, + 39 + ] + }, + { + "text": "extlink:m[] Integer multiplication and division. - extlink:a[] Atomic instructions. - Single-precision floating-point instructions. - Double-precision floating-point instructions. - extlink:c[] Compressed Instructions. - extlink:zicsr[] CSR instructions.", + "section": "Preamble > RVA20 Profiles > RVA20U64 Profile > RVA20U64 Mandatory Extensions", + "line_range": [ + 43, + 49 + ] + }, + { + "text": "These are implied by presence of Zicntr or F. - Basic counters.", + "section": "Preamble > RVA20 Profiles > RVA20U64 Profile > RVA20U64 Mandatory Extensions", + "line_range": [ + 43, + 49 + ] + }, + { + "text": "Main memory regions with both the cacheability and coherence PMAs must support instruction fetch, and any instruction fetches of naturally aligned power-of-2 sizes up to min(ILEN,XLEN) (i.e., 32 bits for RVA20) are atomic.", + "section": "Preamble > RVA20 Profiles > RVA20U64 Profile > RVA20U64 Mandatory Extensions", + "line_range": [ + 51, + 54 + ] + }, + { + "text": "NOTE: The fetch atomicity requirement facilitates runtime patching of aligned instructions.", + "section": "Preamble > RVA20 Profiles > RVA20U64 Profile > RVA20U64 Mandatory Extensions", + "line_range": [ + 56, + 57 + ] + }, + { + "text": "Main memory regions with both the cacheability and coherence PMAs must support RsrvEventual.", + "section": "Preamble > RVA20 Profiles > RVA20U64 Profile > RVA20U64 Mandatory Extensions", + "line_range": [ + 59, + 60 + ] + }, + { + "text": "Main memory regions with both the cacheability and coherence PMAs must support AMOArithmetic.", + "section": "Preamble > RVA20 Profiles > RVA20U64 Profile > RVA20U64 Mandatory Extensions", + "line_range": [ + 62, + 63 + ] + }, + { + "text": "Reservation sets must be contiguous, naturally aligned, and at most 128 bytes in size.", + "section": "Preamble > RVA20 Profiles > RVA20U64 Profile > RVA20U64 Mandatory Extensions", + "line_range": [ + 65, + 66 + ] + }, + { + "text": "NOTE: The minimum reservation set size is effectively determined by the size of atomic accesses in the A extension.", + "section": "Preamble > RVA20 Profiles > RVA20U64 Profile > RVA20U64 Mandatory Extensions", + "line_range": [ + 68, + 69 + ] + }, + { + "text": "Misaligned loads and stores to main memory regions with both the cacheability and coherence PMAs must be supported.", + "section": "Preamble > RVA20 Profiles > RVA20U64 Profile > RVA20U64 Mandatory Extensions", + "line_range": [ + 71, + 72 + ] + }, + { + "text": "NOTE: This requires misaligned support for all regular load and store instructions (including scalar and vector) but not AMOs or other specialized forms of memory access.", + "section": "Preamble > RVA20 Profiles > RVA20U64 Profile > RVA20U64 Mandatory Extensions", + "line_range": [ + 74, + 78 + ] + }, + { + "text": "Even though mandated, misaligned loads and stores might execute extremely slowly.", + "section": "Preamble > RVA20 Profiles > RVA20U64 Profile > RVA20U64 Mandatory Extensions", + "line_range": [ + 74, + 78 + ] + }, + { + "text": "Standard software distributions should assume their existence only for correctness, not for performance.", + "section": "Preamble > RVA20 Profiles > RVA20U64 Profile > RVA20U64 Mandatory Extensions", + "line_range": [ + 74, + 78 + ] + }, + { + "text": "Hardware performance counters.", + "section": "Preamble > RVA20 Profiles > RVA20U64 Profile > RVA20U64 Optional Extensions", + "line_range": [ + 82, + 82 + ] + }, + { + "text": "NOTE: Hardware performance counters are a supported option in RVA20.", + "section": "Preamble > RVA20 Profiles > RVA20U64 Profile > RVA20U64 Optional Extensions", + "line_range": [ + 84, + 85 + ] + }, + { + "text": "The number of counters is platform-specific.", + "section": "Preamble > RVA20 Profiles > RVA20U64 Profile > RVA20U64 Optional Extensions", + "line_range": [ + 84, + 85 + ] + }, + { + "text": "NOTE: The rationale to not make Q an optional extension is that quad-precision floating-point is unlikely to be implemented in hardware, and so we do not require or expect A-profile software to expend effort optimizing use of Q instructions in case they are present.", + "section": "Preamble > RVA20 Profiles > RVA20U64 Profile > RVA20U64 Optional Extensions", + "line_range": [ + 87, + 91 + ] + }, + { + "text": "NOTE: Zifencei is not classed as a supported option in the user-mode profile because it is not sufficient by itself to produce the desired effect in a multiprogrammed multiprocessor environment without OS support, and so the instruction cache flush should always be performed using an OS call rather than using the `fence.i` instruction. `fence.i` semantics can be expensive to implement for some hardware memory hierarchy designs, and so alternative non-standard instruction-cache coherence mechanisms can be used behind the OS abstraction. A separate extension is being developed for more general and efficient instruction cache coherence.", + "section": "Preamble > RVA20 Profiles > RVA20U64 Profile > RVA20U64 Optional Extensions", + "line_range": [ + 93, + 102 + ] + }, + { + "text": "NOTE: The execution environment must provide a means to synchronize writes to instruction memory with instruction fetches, the implementation of which likely relies on the Zifencei extension.", + "section": "Preamble > RVA20 Profiles > RVA20U64 Profile > RVA20U64 Optional Extensions", + "line_range": [ + 104, + 108 + ] + }, + { + "text": "For example, RISC-V Linux supplies the `riscvflushicache` system call and a corresponding vDSO call.", + "section": "Preamble > RVA20 Profiles > RVA20U64 Profile > RVA20U64 Optional Extensions", + "line_range": [ + 104, + 108 + ] + }, + { + "text": "Recommendations are not strictly mandated but are included to guide implementers making design choices.", + "section": "Preamble > RVA20 Profiles > RVA20U64 Profile > RVA20U64 Recommendations", + "line_range": [ + 112, + 113 + ] + }, + { + "text": "Implementations are strongly recommended to raise illegal-instruction exceptions on attempts to execute unimplemented opcodes.", + "section": "Preamble > RVA20 Profiles > RVA20U64 Profile > RVA20U64 Recommendations", + "line_range": [ + 115, + 116 + ] + }, + { + "text": "The RVA20S64 profile specifies the ISA features available to a supervisor-mode execution environment in 64-bit applications processors. RVA20S64 is based on privileged architecture version 1.11.", + "section": "Preamble > RVA20 Profiles > RVA20S64 Profile", + "line_range": [ + 120, + 123 + ] + }, + { + "text": "RVA20S64 has one unprivileged option (Zihpm) and one privileged option (Sv48).", + "section": "Preamble > RVA20 Profiles > RVA20S64 Profile", + "line_range": [ + 125, + 126 + ] + }, + { + "text": "RV64I is the mandatory base ISA for RVA20S64, and is little-endian.", + "section": "Preamble > RVA20 Profiles > RVA20S64 Profile > RVA20S64 Mandatory Base", + "line_range": [ + 130, + 130 + ] + }, + { + "text": "The `ecall` instruction operates as per the unprivileged architecture specification.", + "section": "Preamble > RVA20 Profiles > RVA20S64 Profile > RVA20S64 Mandatory Base", + "line_range": [ + 132, + 135 + ] + }, + { + "text": "An `ecall` in user mode causes a contained trap to supervisor mode.", + "section": "Preamble > RVA20 Profiles > RVA20S64 Profile > RVA20S64 Mandatory Base", + "line_range": [ + 132, + 135 + ] + }, + { + "text": "An `ecall` in supervisor mode causes a requested trap to the execution environment.", + "section": "Preamble > RVA20 Profiles > RVA20S64 Profile > RVA20S64 Mandatory Base", + "line_range": [ + 132, + 135 + ] + }, + { + "text": "The following unprivileged extensions are mandatory:", + "section": "Preamble > RVA20 Profiles > RVA20S64 Profile > RVA20S64 Mandatory Extensions", + "line_range": [ + 139, + 139 + ] + }, + { + "text": "The RVA20S64 mandatory unprivileged extensions include all the mandatory unprivileged extensions in RVA20U64.", + "section": "Preamble > RVA20 Profiles > RVA20S64 Profile > RVA20S64 Mandatory Extensions", + "line_range": [ + 141, + 142 + ] + }, + { + "text": "NOTE: Zifencei is mandated as it is the only standard way to support instruction-cache coherence in RVA20 application processors. A new instruction-cache coherence mechanism is under development which might be added as an option in the future.", + "section": "Preamble > RVA20 Profiles > RVA20S64 Profile > RVA20S64 Mandatory Extensions", + "line_range": [ + 146, + 149 + ] + }, + { + "text": "The following privileged extensions are mandatory:", + "section": "Preamble > RVA20 Profiles > RVA20S64 Profile > RVA20S64 Mandatory Extensions", + "line_range": [ + 151, + 151 + ] + }, + { + "text": "*Ss1p11* Privileged Architecture version 1.11.", + "section": "Preamble > RVA20 Profiles > RVA20S64 Profile > RVA20S64 Mandatory Extensions", + "line_range": [ + 153, + 153 + ] + }, + { + "text": "The `satp` mode Bare must be supported.", + "section": "Preamble > RVA20 Profiles > RVA20S64 Profile > RVA20S64 Mandatory Extensions", + "line_range": [ + 155, + 155 + ] + }, + { + "text": "Page-Based 39-bit Virtual-Memory System.", + "section": "Preamble > RVA20 Profiles > RVA20S64 Profile > RVA20S64 Mandatory Extensions", + "line_range": [ + 157, + 157 + ] + }, + { + "text": "Page-fault exceptions are raised when a page is accessed when A bit is clear, or written when D bit is clear.", + "section": "Preamble > RVA20 Profiles > RVA20S64 Profile > RVA20S64 Mandatory Extensions", + "line_range": [ + 159, + 160 + ] + }, + { + "text": "Main memory regions with both the cacheability and coherence PMAs must support hardware page-table reads.", + "section": "Preamble > RVA20 Profiles > RVA20S64 Profile > RVA20S64 Mandatory Extensions", + "line_range": [ + 162, + 163 + ] + }, + { + "text": "`stvec.MODE` must be capable of holding the value 0 (Direct).", + "section": "Preamble > RVA20 Profiles > RVA20S64 Profile > RVA20S64 Mandatory Extensions", + "line_range": [ + 165, + 167 + ] + }, + { + "text": "When `stvec.MODE=Direct`, `stvec.BASE` must be capable of holding any valid four-byte-aligned address.", + "section": "Preamble > RVA20 Profiles > RVA20S64 Profile > RVA20S64 Mandatory Extensions", + "line_range": [ + 165, + 167 + ] + }, + { + "text": "`stval` must be written with the faulting virtual address for load, store, and instruction page-fault, access-fault, and misaligned exceptions, and for breakpoint exceptions that are defined to write an address to stval, other than those caused by execution of the `EBREAK` or `C.EBREAK` instructions.", + "section": "Preamble > RVA20 Profiles > RVA20S64 Profile > RVA20S64 Mandatory Extensions", + "line_range": [ + 169, + 174 + ] + }, + { + "text": "For virtual-instruction and illegal-instruction exceptions, `stval` must be written with the faulting instruction.", + "section": "Preamble > RVA20 Profiles > RVA20S64 Profile > RVA20S64 Mandatory Extensions", + "line_range": [ + 169, + 174 + ] + }, + { + "text": "RVA20S64 has one unprivileged option.", + "section": "Preamble > RVA20 Profiles > RVA20S64 Profile > RVA20S64 Optional Extensions", + "line_range": [ + 178, + 178 + ] + }, + { + "text": "Hardware performance counters.", + "section": "Preamble > RVA20 Profiles > RVA20S64 Profile > RVA20S64 Optional Extensions", + "line_range": [ + 180, + 180 + ] + }, + { + "text": "NOTE: The number of counters is platform-specific.", + "section": "Preamble > RVA20 Profiles > RVA20S64 Profile > RVA20S64 Optional Extensions", + "line_range": [ + 182, + 182 + ] + }, + { + "text": "RVA20S64 has the following privileged options:", + "section": "Preamble > RVA20 Profiles > RVA20S64 Profile > RVA20S64 Optional Extensions", + "line_range": [ + 184, + 184 + ] + }, + { + "text": "Page-Based 48-bit Virtual-Memory System.", + "section": "Preamble > RVA20 Profiles > RVA20S64 Profile > RVA20S64 Optional Extensions", + "line_range": [ + 186, + 186 + ] + }, + { + "text": "`sstatus.UXL` must be capable of holding the value 2 (i.e., UXLEN=64 must be supported).", + "section": "Preamble > RVA20 Profiles > RVA20S64 Profile > RVA20S64 Optional Extensions", + "line_range": [ + 188, + 189 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__profiles__rva22.json b/tools/llm-extraction/data/output/raw_chunks/src__profiles__rva22.json new file mode 100644 index 0000000000..dc3779a0f1 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__profiles__rva22.json @@ -0,0 +1,702 @@ +{ + "source_file": "src/profiles/rva22.adoc", + "total": 87, + "sentences": [ + { + "text": "The RVA22 profiles are intended to be used for 64-bit application processors running rich OS stacks.", + "section": "Preamble > RVA22 Profiles", + "line_range": [ + 2, + 4 + ] + }, + { + "text": "Only user-mode (RVA22U64) and supervisor-mode (RVA22S64) profiles are specified in this family.", + "section": "Preamble > RVA22 Profiles", + "line_range": [ + 2, + 4 + ] + }, + { + "text": "The RVA22U64 profile specifies the ISA features available to user-mode execution environments in 64-bit applications processors.", + "section": "Preamble > RVA22 Profiles > RVA22U64 Profile", + "line_range": [ + 8, + 11 + ] + }, + { + "text": "This is the most important profile within the application processor family in terms of the amount of software that targets this profile.", + "section": "Preamble > RVA22 Profiles > RVA22U64 Profile", + "line_range": [ + 8, + 11 + ] + }, + { + "text": "RV64I is the mandatory base ISA for RVA22U64 and is little-endian.", + "section": "Preamble > RVA22 Profiles > RVA22U64 Profile > RVA22U64 Mandatory Base", + "line_range": [ + 15, + 15 + ] + }, + { + "text": "As per the unprivileged architecture specification, the `ecall` instruction causes a requested trap to the execution environment.", + "section": "Preamble > RVA22 Profiles > RVA22U64 Profile > RVA22U64 Mandatory Base", + "line_range": [ + 17, + 18 + ] + }, + { + "text": "The following mandatory extensions were present in RVA20U64.", + "section": "Preamble > RVA22 Profiles > RVA22U64 Profile > RVA22U64 Mandatory Extensions", + "line_range": [ + 22, + 22 + ] + }, + { + "text": "extlink:m[] Integer multiplication and division. - extlink:a[] Atomic instructions. - Single-precision floating-point instructions. - Double-precision floating-point instructions. - extlink:c[] Compressed Instructions. - extlink:zicsr[] CSR instructions.", + "section": "Preamble > RVA22 Profiles > RVA22U64 Profile > RVA22U64 Mandatory Extensions", + "line_range": [ + 24, + 30 + ] + }, + { + "text": "These are implied by presence of F. - Base counters and timers.", + "section": "Preamble > RVA22 Profiles > RVA22U64 Profile > RVA22U64 Mandatory Extensions", + "line_range": [ + 24, + 30 + ] + }, + { + "text": "Main memory regions with both the cacheability and coherence PMAs must support instruction fetch, and any instruction fetches of naturally aligned power-of-2 sizes up to min(ILEN,XLEN) (i.e., 32 bits for RVA22) are atomic.", + "section": "Preamble > RVA22 Profiles > RVA22U64 Profile > RVA22U64 Mandatory Extensions", + "line_range": [ + 32, + 35 + ] + }, + { + "text": "Main memory regions with both the cacheability and coherence PMAs must support RsrvEventual.", + "section": "Preamble > RVA22 Profiles > RVA22U64 Profile > RVA22U64 Mandatory Extensions", + "line_range": [ + 37, + 38 + ] + }, + { + "text": "Main memory regions with both the cacheability and coherence PMAs must support AMOArithmetic.", + "section": "Preamble > RVA22 Profiles > RVA22U64 Profile > RVA22U64 Mandatory Extensions", + "line_range": [ + 40, + 41 + ] + }, + { + "text": "Misaligned loads and stores to main memory regions with both the cacheability and coherence PMAs must be supported.", + "section": "Preamble > RVA22 Profiles > RVA22U64 Profile > RVA22U64 Mandatory Extensions", + "line_range": [ + 43, + 44 + ] + }, + { + "text": "NOTE: Even though mandated, misaligned loads and stores might execute extremely slowly.", + "section": "Preamble > RVA22 Profiles > RVA22U64 Profile > RVA22U64 Mandatory Extensions", + "line_range": [ + 46, + 48 + ] + }, + { + "text": "Standard software distributions should assume their existence only for correctness, not for performance.", + "section": "Preamble > RVA22 Profiles > RVA22U64 Profile > RVA22U64 Mandatory Extensions", + "line_range": [ + 46, + 48 + ] + }, + { + "text": "The following mandatory feature was further restricted in RVA22U64:", + "section": "Preamble > RVA22 Profiles > RVA22U64 Profile > RVA22U64 Mandatory Extensions", + "line_range": [ + 50, + 50 + ] + }, + { + "text": "Reservation sets are contiguous, naturally aligned, and a maximum of 64 bytes.", + "section": "Preamble > RVA22 Profiles > RVA22U64 Profile > RVA22U64 Mandatory Extensions", + "line_range": [ + 52, + 53 + ] + }, + { + "text": "NOTE: The maximum reservation size has been reduced to match the required cache block size.", + "section": "Preamble > RVA22 Profiles > RVA22U64 Profile > RVA22U64 Mandatory Extensions", + "line_range": [ + 55, + 57 + ] + }, + { + "text": "The minimum reservation size is effectively set by the instructions in the mandatory A extension.", + "section": "Preamble > RVA22 Profiles > RVA22U64 Profile > RVA22U64 Mandatory Extensions", + "line_range": [ + 55, + 57 + ] + }, + { + "text": "The following mandatory extensions are new for RVA22U64.", + "section": "Preamble > RVA22 Profiles > RVA22U64 Profile > RVA22U64 Mandatory Extensions", + "line_range": [ + 59, + 59 + ] + }, + { + "text": "Bit-manipulation instructions.", + "section": "Preamble > RVA22 Profiles > RVA22U64 Profile > RVA22U64 Mandatory Extensions", + "line_range": [ + 61, + 61 + ] + }, + { + "text": "Hardware performance counters.", + "section": "Preamble > RVA22 Profiles > RVA22U64 Profile > RVA22U64 Mandatory Extensions", + "line_range": [ + 63, + 63 + ] + }, + { + "text": "NOTE: Zihpm was optional in RVA20U64.", + "section": "Preamble > RVA22 Profiles > RVA22U64 Profile > RVA22U64 Mandatory Extensions", + "line_range": [ + 65, + 65 + ] + }, + { + "text": "NOTE: While the `pause` instruction is a HINT can be implemented as a NOP and hence trivially supported by hardware implementers, its inclusion in the mandatory extension list signifies that software should use the instruction whenever it would make sense and that implementors are expected to exploit this information to optimize hardware execution.", + "section": "Preamble > RVA22 Profiles > RVA22U64 Profile > RVA22U64 Mandatory Extensions", + "line_range": [ + 69, + 74 + ] + }, + { + "text": "Cache blocks must be 64 bytes in size, naturally aligned in the address space.", + "section": "Preamble > RVA22 Profiles > RVA22U64 Profile > RVA22U64 Mandatory Extensions", + "line_range": [ + 76, + 77 + ] + }, + { + "text": "NOTE: While the general RISC-V specifications are agnostic to cache block size, selecting a common cache block size simplifies the specification and use of the following cache-block extensions within the application processor profile.", + "section": "Preamble > RVA22 Profiles > RVA22U64 Profile > RVA22U64 Mandatory Extensions", + "line_range": [ + 79, + 87 + ] + }, + { + "text": "Software does not have to query a discovery mechanism and/or provide dynamic dispatch to the appropriate code.", + "section": "Preamble > RVA22 Profiles > RVA22U64 Profile > RVA22U64 Mandatory Extensions", + "line_range": [ + 79, + 87 + ] + }, + { + "text": "We choose 64 bytes at it is effectively an industry standard.", + "section": "Preamble > RVA22 Profiles > RVA22U64 Profile > RVA22U64 Mandatory Extensions", + "line_range": [ + 79, + 87 + ] + }, + { + "text": "Implementations may use longer cache blocks to reduce tag cost provided they use 64-byte sub-blocks to remain compatible.", + "section": "Preamble > RVA22 Profiles > RVA22U64 Profile > RVA22U64 Mandatory Extensions", + "line_range": [ + 79, + 87 + ] + }, + { + "text": "Implementations may use shorter cache blocks provided they sequence cache operations across the multiple cache blocks comprising a 64-byte block to remain compatible.", + "section": "Preamble > RVA22 Profiles > RVA22U64 Profile > RVA22U64 Mandatory Extensions", + "line_range": [ + 79, + 87 + ] + }, + { + "text": "Cache-Block Management Operations. - Cache-Block Prefetch Operations.", + "section": "Preamble > RVA22 Profiles > RVA22U64 Profile > RVA22U64 Mandatory Extensions", + "line_range": [ + 89, + 90 + ] + }, + { + "text": "NOTE: As with other HINTS, the inclusion of prefetches in the mandatory set of extensions indicates that software should generate these instructions where they are expected to be useful, and hardware is expected to exploit that information.", + "section": "Preamble > RVA22 Profiles > RVA22U64 Profile > RVA22U64 Mandatory Extensions", + "line_range": [ + 92, + 95 + ] + }, + { + "text": "Cache-Block Zero Operations.", + "section": "Preamble > RVA22 Profiles > RVA22U64 Profile > RVA22U64 Mandatory Extensions", + "line_range": [ + 97, + 97 + ] + }, + { + "text": "ext:zfhmin[] Half-Precision Floating-point transfer and convert.", + "section": "Preamble > RVA22 Profiles > RVA22U64 Profile > RVA22U64 Mandatory Extensions", + "line_range": [ + 99, + 99 + ] + }, + { + "text": "NOTE: The hardware cost for Zfhmin is low, and mandating it avoids adding an option to the profile.", + "section": "Preamble > RVA22 Profiles > RVA22U64 Profile > RVA22U64 Mandatory Extensions", + "line_range": [ + 101, + 102 + ] + }, + { + "text": "Data-independent execution time.", + "section": "Preamble > RVA22 Profiles > RVA22U64 Profile > RVA22U64 Mandatory Extensions", + "line_range": [ + 104, + 104 + ] + }, + { + "text": "NOTE: Mandating Zkt enables portable libraries for safe basic cryptographic operations.", + "section": "Preamble > RVA22 Profiles > RVA22U64 Profile > RVA22U64 Mandatory Extensions", + "line_range": [ + 106, + 109 + ] + }, + { + "text": "It is expected that application processors will naturally have this property and so implementation cost is low, if not zero, in most systems that would support RVA22.", + "section": "Preamble > RVA22 Profiles > RVA22U64 Profile > RVA22U64 Mandatory Extensions", + "line_range": [ + 106, + 109 + ] + }, + { + "text": "RVA22U64 has four profile options (Zfh, V, Zkn, Zks):", + "section": "Preamble > RVA22 Profiles > RVA22U64 Profile > RVA22U64 Optional Extensions", + "line_range": [ + 113, + 113 + ] + }, + { + "text": "Half-Precision Floating-Point.", + "section": "Preamble > RVA22 Profiles > RVA22U64 Profile > RVA22U64 Optional Extensions", + "line_range": [ + 115, + 115 + ] + }, + { + "text": "NOTE: A future profile might mandate Zfh.", + "section": "Preamble > RVA22 Profiles > RVA22U64 Profile > RVA22U64 Optional Extensions", + "line_range": [ + 117, + 117 + ] + }, + { + "text": "NOTE: The smaller vector extensions (Zve32f, Zve32x, Zve64d, Zve64f, Zve64x) are not provided as separately supported profile options.", + "section": "Preamble > RVA22 Profiles > RVA22U64 Profile > RVA22U64 Optional Extensions", + "line_range": [ + 121, + 123 + ] + }, + { + "text": "The full V extension is specified as the only supported profile option.", + "section": "Preamble > RVA22 Profiles > RVA22U64 Profile > RVA22U64 Optional Extensions", + "line_range": [ + 121, + 123 + ] + }, + { + "text": "Scalar Crypto NIST Algorithms. - Scalar Crypto ShangMi Algorithms.", + "section": "Preamble > RVA22 Profiles > RVA22U64 Profile > RVA22U64 Optional Extensions", + "line_range": [ + 125, + 126 + ] + }, + { + "text": "NOTE: The smaller component scalar crypto extensions (Zbc, Zbkb, Zbkc, Zbkx, Zknd, Zkne, Zknh, Zksed, Zksh) are not provided as separate options in the profile.", + "section": "Preamble > RVA22 Profiles > RVA22U64 Profile > RVA22U64 Optional Extensions", + "line_range": [ + 128, + 132 + ] + }, + { + "text": "Profile implementers should provide all of the instructions in a given algorithm suite as part of the Zkn or Zks supported options.", + "section": "Preamble > RVA22 Profiles > RVA22U64 Profile > RVA22U64 Optional Extensions", + "line_range": [ + 128, + 132 + ] + }, + { + "text": "NOTE: Access to the entropy source (Zkr) in a system is usually carefully controlled.", + "section": "Preamble > RVA22 Profiles > RVA22U64 Profile > RVA22U64 Optional Extensions", + "line_range": [ + 134, + 138 + ] + }, + { + "text": "While the design supports unprivileged access to the entropy source, this is unlikely to be commonly used in an application processor, and so Zkr was not added as a profile option.", + "section": "Preamble > RVA22 Profiles > RVA22U64 Profile > RVA22U64 Optional Extensions", + "line_range": [ + 134, + 138 + ] + }, + { + "text": "This also means the roll-up Zk was not added as a profile option.", + "section": "Preamble > RVA22 Profiles > RVA22U64 Profile > RVA22U64 Optional Extensions", + "line_range": [ + 134, + 138 + ] + }, + { + "text": "NOTE: The Zfinx, Zdinx, Zhinx, Zhinxmin extensions are incompatible with the profile mandates to support the F and D extensions.", + "section": "Preamble > RVA22 Profiles > RVA22U64 Profile > RVA22U64 Optional Extensions", + "line_range": [ + 140, + 141 + ] + }, + { + "text": "Recommendations are not strictly mandated but are included to guide implementers making design choices.", + "section": "Preamble > RVA22 Profiles > RVA22U64 Profile > RVA22U64 Recommendations", + "line_range": [ + 145, + 146 + ] + }, + { + "text": "Implementations are strongly recommended to raise illegal-instruction exceptions on attempts to execute unimplemented opcodes.", + "section": "Preamble > RVA22 Profiles > RVA22U64 Profile > RVA22U64 Recommendations", + "line_range": [ + 148, + 149 + ] + }, + { + "text": "The RVA22S64 profile specifies the ISA features available to a supervisor-mode execution environment in 64-bit applications processors. RVA22S64 is based on privileged architecture version 1.12.", + "section": "Preamble > RVA22 Profiles > RVA22S64 Profile", + "line_range": [ + 153, + 156 + ] + }, + { + "text": "RV64I is the mandatory base ISA for RVA22S64 and is little-endian.", + "section": "Preamble > RVA22 Profiles > RVA22S64 Profile > RVA22S64 Mandatory Base", + "line_range": [ + 160, + 160 + ] + }, + { + "text": "The `ecall` instruction operates as per the unprivileged architecture specification.", + "section": "Preamble > RVA22 Profiles > RVA22S64 Profile > RVA22S64 Mandatory Base", + "line_range": [ + 162, + 165 + ] + }, + { + "text": "An `ecall` in user mode causes a contained trap to supervisor mode.", + "section": "Preamble > RVA22 Profiles > RVA22S64 Profile > RVA22S64 Mandatory Base", + "line_range": [ + 162, + 165 + ] + }, + { + "text": "An `ecall` in supervisor mode causes a requested trap to the execution environment.", + "section": "Preamble > RVA22 Profiles > RVA22S64 Profile > RVA22S64 Mandatory Base", + "line_range": [ + 162, + 165 + ] + }, + { + "text": "The following unprivileged extensions are mandatory:", + "section": "Preamble > RVA22 Profiles > RVA22S64 Profile > RVA22S64 Mandatory Extensions", + "line_range": [ + 169, + 169 + ] + }, + { + "text": "The RVA22S64 mandatory unprivileged extensions include all the mandatory unprivileged extensions in RVA22U64.", + "section": "Preamble > RVA22 Profiles > RVA22S64 Profile > RVA22S64 Mandatory Extensions", + "line_range": [ + 171, + 172 + ] + }, + { + "text": "NOTE: Zifencei is mandated as it is the only standard way to support instruction-cache coherence in RVA22 application processors. A new instruction-cache coherence mechanism is under development which might be added as an option in the future.", + "section": "Preamble > RVA22 Profiles > RVA22S64 Profile > RVA22S64 Mandatory Extensions", + "line_range": [ + 176, + 179 + ] + }, + { + "text": "The following privileged extensions are mandatory:", + "section": "Preamble > RVA22 Profiles > RVA22S64 Profile > RVA22S64 Mandatory Extensions", + "line_range": [ + 181, + 181 + ] + }, + { + "text": "*Ss1p12* Privileged Architecture version 1.12.", + "section": "Preamble > RVA22 Profiles > RVA22S64 Profile > RVA22S64 Mandatory Extensions", + "line_range": [ + 183, + 183 + ] + }, + { + "text": "NOTE: Ss1p12 supersedes Ss1p11.", + "section": "Preamble > RVA22 Profiles > RVA22S64 Profile > RVA22S64 Mandatory Extensions", + "line_range": [ + 185, + 185 + ] + }, + { + "text": "The `satp` mode Bare must be supported.", + "section": "Preamble > RVA22 Profiles > RVA22S64 Profile > RVA22S64 Mandatory Extensions", + "line_range": [ + 187, + 187 + ] + }, + { + "text": "Page-Based 39-bit Virtual-Memory System.", + "section": "Preamble > RVA22 Profiles > RVA22S64 Profile > RVA22S64 Mandatory Extensions", + "line_range": [ + 189, + 189 + ] + }, + { + "text": "Page-fault exceptions are raised when a page is accessed when A bit is clear, or written when D bit is clear.", + "section": "Preamble > RVA22 Profiles > RVA22S64 Profile > RVA22S64 Mandatory Extensions", + "line_range": [ + 191, + 192 + ] + }, + { + "text": "Main memory regions with both the cacheability and coherence PMAs must support hardware page-table reads.", + "section": "Preamble > RVA22 Profiles > RVA22S64 Profile > RVA22S64 Mandatory Extensions", + "line_range": [ + 194, + 195 + ] + }, + { + "text": "`stvec.MODE` must be capable of holding the value 0 (Direct).", + "section": "Preamble > RVA22 Profiles > RVA22S64 Profile > RVA22S64 Mandatory Extensions", + "line_range": [ + 197, + 199 + ] + }, + { + "text": "When `stvec.MODE=Direct`, `stvec.BASE` must be capable of holding any valid four-byte-aligned address.", + "section": "Preamble > RVA22 Profiles > RVA22S64 Profile > RVA22S64 Mandatory Extensions", + "line_range": [ + 197, + 199 + ] + }, + { + "text": "stval must be written with the faulting virtual address for load, store, and instruction page-fault, access-fault, and misaligned exceptions, and for breakpoint exceptions other than those caused by execution of the EBREAK or C.EBREAK instructions.", + "section": "Preamble > RVA22 Profiles > RVA22S64 Profile > RVA22S64 Mandatory Extensions", + "line_range": [ + 201, + 206 + ] + }, + { + "text": "For virtual-instruction and illegal-instruction exceptions, stval must be written with the faulting instruction.", + "section": "Preamble > RVA22 Profiles > RVA22S64 Profile > RVA22S64 Mandatory Extensions", + "line_range": [ + 201, + 206 + ] + }, + { + "text": "For any hpmcounter that is not read-only zero, the corresponding bit in scounteren must be writable.", + "section": "Preamble > RVA22 Profiles > RVA22S64 Profile > RVA22S64 Mandatory Extensions", + "line_range": [ + 208, + 209 + ] + }, + { + "text": "Fine-Grained Address-Translation Cache Invalidation", + "section": "Preamble > RVA22 Profiles > RVA22S64 Profile > RVA22S64 Mandatory Extensions", + "line_range": [ + 213, + 213 + ] + }, + { + "text": "RVA22S64 has four unprivileged options (Zfh, V, Zkn, Zks) from RVA22U64, and eight privileged options (Sv48, Sv57, Svnapot, Ssu64xl, Sstc, Sscofpmf, Zkr, H).", + "section": "Preamble > RVA22 Profiles > RVA22S64 Profile > RVA22S64 Optional Extensions", + "line_range": [ + 217, + 218 + ] + }, + { + "text": "The privileged optional extensions are:", + "section": "Preamble > RVA22 Profiles > RVA22S64 Profile > RVA22S64 Optional Extensions", + "line_range": [ + 220, + 220 + ] + }, + { + "text": "Page-Based 48-bit Virtual-Memory System.", + "section": "Preamble > RVA22 Profiles > RVA22S64 Profile > RVA22S64 Optional Extensions", + "line_range": [ + 222, + 222 + ] + }, + { + "text": "Page-Based 57-bit Virtual-Memory System.", + "section": "Preamble > RVA22 Profiles > RVA22S64 Profile > RVA22S64 Optional Extensions", + "line_range": [ + 224, + 224 + ] + }, + { + "text": "NAPOT Translation Contiguity", + "section": "Preamble > RVA22 Profiles > RVA22S64 Profile > RVA22S64 Optional Extensions", + "line_range": [ + 226, + 226 + ] + }, + { + "text": "`sstatus.UXL` must be capable of holding the value 2 (i.e., UXLEN=64 must be supported).", + "section": "Preamble > RVA22 Profiles > RVA22S64 Profile > RVA22S64 Optional Extensions", + "line_range": [ + 228, + 229 + ] + }, + { + "text": "supervisor-mode timer interrupts.", + "section": "Preamble > RVA22 Profiles > RVA22S64 Profile > RVA22S64 Optional Extensions", + "line_range": [ + 231, + 231 + ] + }, + { + "text": "NOTE: Sstc was not made mandatory in RVA22S64 as it is a more disruptive change affecting system-level architecture, and will take longer for implementations to adopt.", + "section": "Preamble > RVA22 Profiles > RVA22S64 Profile > RVA22S64 Optional Extensions", + "line_range": [ + 233, + 235 + ] + }, + { + "text": "Count Overflow and Mode-Based Filtering.", + "section": "Preamble > RVA22 Profiles > RVA22S64 Profile > RVA22S64 Optional Extensions", + "line_range": [ + 237, + 237 + ] + }, + { + "text": "NOTE: Platforms may choose to mandate the presence of Sscofpmf.", + "section": "Preamble > RVA22 Profiles > RVA22S64 Profile > RVA22S64 Optional Extensions", + "line_range": [ + 239, + 239 + ] + }, + { + "text": "NOTE: Technically, Zk is also a privileged-mode option capturing that Zkr, Zkn, and Zkt are all implemented.", + "section": "Preamble > RVA22 Profiles > RVA22S64 Profile > RVA22S64 Optional Extensions", + "line_range": [ + 243, + 245 + ] + }, + { + "text": "However, the Zk rollup is less descriptive than specifying the individual extensions explicitly.", + "section": "Preamble > RVA22 Profiles > RVA22S64 Profile > RVA22S64 Optional Extensions", + "line_range": [ + 243, + 245 + ] + }, + { + "text": "The augmented hypervisor extension.", + "section": "Preamble > RVA22 Profiles > RVA22S64 Profile > RVA22S64 Optional Extensions", + "line_range": [ + 247, + 247 + ] + }, + { + "text": "Implementations are strongly recommended to raise illegal-instruction exceptions when attempting to execute unimplemented opcodes.", + "section": "Preamble > RVA22 Profiles > RVA22S64 Profile > RVA22S64 Recommendations", + "line_range": [ + 251, + 252 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__profiles__rva23.json b/tools/llm-extraction/data/output/raw_chunks/src__profiles__rva23.json new file mode 100644 index 0000000000..cd0c09cdd6 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__profiles__rva23.json @@ -0,0 +1,766 @@ +{ + "source_file": "src/profiles/rva23.adoc", + "total": 95, + "sentences": [ + { + "text": "The RVA23 profiles are intended to align implementations of RISC-V 64-bit application processors to allow binary software ecosystems to rely on a large set of guaranteed extensions and a small number of discoverable coarse-grain options.", + "section": "Preamble > RVA23 Profiles", + "line_range": [ + 2, + 8 + ] + }, + { + "text": "It is explicitly a non-goal of RVA23 to allow more hardware implementation flexibility by supporting only a minimal set of features and a large number of fine-grain extensions.", + "section": "Preamble > RVA23 Profiles", + "line_range": [ + 2, + 8 + ] + }, + { + "text": "Only user-mode (RVA23U64) and supervisor-mode (RVA23S64) profiles are specified in this family.", + "section": "Preamble > RVA23 Profiles", + "line_range": [ + 10, + 11 + ] + }, + { + "text": "The RVA23U64 profile specifies the ISA features available to user-mode execution environments in 64-bit applications processors.", + "section": "Preamble > RVA23 Profiles > RVA23U64 Profile", + "line_range": [ + 15, + 18 + ] + }, + { + "text": "This is the most important profile within the application processor family in terms of the amount of software that targets this profile.", + "section": "Preamble > RVA23 Profiles > RVA23U64 Profile", + "line_range": [ + 15, + 18 + ] + }, + { + "text": "RV64I is the mandatory base ISA for RVA23U64 and is little-endian.", + "section": "Preamble > RVA23 Profiles > RVA23U64 Profile > RVA23U64 Mandatory Base", + "line_range": [ + 22, + 24 + ] + }, + { + "text": "As per the unprivileged architecture specification, the `ECALL` instruction causes a requested trap to the execution environment.", + "section": "Preamble > RVA23 Profiles > RVA23U64 Profile > RVA23U64 Mandatory Base", + "line_range": [ + 22, + 24 + ] + }, + { + "text": "The following mandatory extensions were present in RVA22U64.", + "section": "Preamble > RVA23 Profiles > RVA23U64 Profile > RVA23U64 Mandatory Extensions", + "line_range": [ + 28, + 28 + ] + }, + { + "text": "extlink:m[] Integer multiplication and division. - extlink:a[] Atomic instructions. - Single-precision floating-point instructions. - Double-precision floating-point instructions. - extlink:c[] Compressed instructions. - Bit-manipulation instructions. - extlink:zicsr[] CSR instructions.", + "section": "Preamble > RVA23 Profiles > RVA23U64 Profile > RVA23U64 Mandatory Extensions", + "line_range": [ + 30, + 58 + ] + }, + { + "text": "These are implied by presence of F. - Base counters and timers. - Hardware performance counters. - Main memory regions with both the cacheability and coherence PMAs must support instruction fetch, and any instruction fetches of naturally aligned power-of-2 sizes up to min(ILEN,XLEN) (i.e., 32 bits for RVA23) are atomic. - Main memory regions with both the cacheability and coherence PMAs must support RsrvEventual. - Main memory regions with both the cacheability and coherence PMAs must support all atomics in the Zaamo extension. - Misaligned loads and stores to main memory regions with both the cacheability and coherence PMAs must be supported. - Reservation sets are contiguous, naturally aligned, and a maximum of 64 bytes. - Pause hint. - Cache blocks must be 64 bytes in size, naturally aligned in the address space. - Cache-block management instructions. - Cache-block prefetch instructions. - Cache-Block Zero Instructions. - ext:zfhmin[] Half-precision floating-point. - Data-independent execution latency.", + "section": "Preamble > RVA23 Profiles > RVA23U64 Profile > RVA23U64 Mandatory Extensions", + "line_range": [ + 30, + 58 + ] + }, + { + "text": "The following mandatory extensions are new in RVA23U64:", + "section": "Preamble > RVA23 Profiles > RVA23U64 Profile > RVA23U64 Mandatory Extensions", + "line_range": [ + 60, + 60 + ] + }, + { + "text": "NOTE: V was optional in RVA22U64.", + "section": "Preamble > RVA23 Profiles > RVA23U64 Profile > RVA23U64 Mandatory Extensions", + "line_range": [ + 64, + 64 + ] + }, + { + "text": "Vector minimal half-precision floating-point.", + "section": "Preamble > RVA23 Profiles > RVA23U64 Profile > RVA23U64 Mandatory Extensions", + "line_range": [ + 66, + 66 + ] + }, + { + "text": "Vector basic bit-manipulation instructions.", + "section": "Preamble > RVA23 Profiles > RVA23U64 Profile > RVA23U64 Mandatory Extensions", + "line_range": [ + 68, + 68 + ] + }, + { + "text": "Vector data-independent execution latency.", + "section": "Preamble > RVA23 Profiles > RVA23U64 Profile > RVA23U64 Mandatory Extensions", + "line_range": [ + 70, + 70 + ] + }, + { + "text": "Non-temporal locality hints.", + "section": "Preamble > RVA23 Profiles > RVA23U64 Profile > RVA23U64 Mandatory Extensions", + "line_range": [ + 72, + 72 + ] + }, + { + "text": "Integer conditional operations.", + "section": "Preamble > RVA23 Profiles > RVA23U64 Profile > RVA23U64 Mandatory Extensions", + "line_range": [ + 74, + 74 + ] + }, + { + "text": "ext:zimop[] may-be-operations.", + "section": "Preamble > RVA23 Profiles > RVA23U64 Profile > RVA23U64 Mandatory Extensions", + "line_range": [ + 76, + 76 + ] + }, + { + "text": "ext:zcmop[] Compressed may-be-operations.", + "section": "Preamble > RVA23 Profiles > RVA23U64 Profile > RVA23U64 Mandatory Extensions", + "line_range": [ + 78, + 78 + ] + }, + { + "text": "ext:zcb[] Additional compressed instructions.", + "section": "Preamble > RVA23 Profiles > RVA23U64 Profile > RVA23U64 Mandatory Extensions", + "line_range": [ + 80, + 80 + ] + }, + { + "text": "Additional floating-Point instructions.", + "section": "Preamble > RVA23 Profiles > RVA23U64 Profile > RVA23U64 Mandatory Extensions", + "line_range": [ + 82, + 82 + ] + }, + { + "text": "Wait-on-reservation-set instructions.", + "section": "Preamble > RVA23 Profiles > RVA23U64 Profile > RVA23U64 Mandatory Extensions", + "line_range": [ + 84, + 84 + ] + }, + { + "text": "Pointer masking, with the execution environment providing a means to select PMLEN=0 and PMLEN=7 at minimum.", + "section": "Preamble > RVA23 Profiles > RVA23U64 Profile > RVA23U64 Mandatory Extensions", + "line_range": [ + 86, + 87 + ] + }, + { + "text": "The following localized options are new in RVA23U64:", + "section": "Preamble > RVA23 Profiles > RVA23U64 Profile > RVA23U64 Optional Extensions > Localized Options", + "line_range": [ + 93, + 93 + ] + }, + { + "text": "Vector crypto NIST algorithms with GCM. - Vector crypto ShangMi algorithms with GCM.", + "section": "Preamble > RVA23 Profiles > RVA23U64 Profile > RVA23U64 Optional Extensions > Localized Options", + "line_range": [ + 95, + 96 + ] + }, + { + "text": "NOTE: The scalar crypto extensions Zkn and Zks that were options in RVA22 are not options in RVA23.", + "section": "Preamble > RVA23 Profiles > RVA23U64 Profile > RVA23U64 Optional Extensions > Localized Options", + "line_range": [ + 98, + 102 + ] + }, + { + "text": "The goal is for both hardware and software vendors to move to use vector crypto, as vectors are now mandatory and vector crypto is substantially faster than scalar crypto.", + "section": "Preamble > RVA23 Profiles > RVA23U64 Profile > RVA23U64 Optional Extensions > Localized Options", + "line_range": [ + 98, + 102 + ] + }, + { + "text": "NOTE: We have included only the Zvkng/Zvksg options with GCM to standardize on a higher performance crypto alternative.", + "section": "Preamble > RVA23 Profiles > RVA23U64 Profile > RVA23U64 Optional Extensions > Localized Options", + "line_range": [ + 104, + 108 + ] + }, + { + "text": "Zvbc is listed as a development option for use in other algorithms, and will become mandatory.", + "section": "Preamble > RVA23 Profiles > RVA23U64 Profile > RVA23U64 Optional Extensions > Localized Options", + "line_range": [ + 104, + 108 + ] + }, + { + "text": "Scalar Zbc is now listed as an expansion option, i.e., it will probably not become mandatory.", + "section": "Preamble > RVA23 Profiles > RVA23U64 Profile > RVA23U64 Optional Extensions > Localized Options", + "line_range": [ + 104, + 108 + ] + }, + { + "text": "The following are new development options intended to become mandatory in a future RVA profile.", + "section": "Preamble > RVA23 Profiles > RVA23U64 Profile > RVA23U64 Optional Extensions > Development Options", + "line_range": [ + 112, + 113 + ] + }, + { + "text": "Byte and halfword atomic memory operations. - Compare-and-Swap instructions. - Main memory regions with both the coherence and cacheability PMAs must provide `AMOCASQ` level PMA support.", + "section": "Preamble > RVA23 Profiles > RVA23U64 Profile > RVA23U64 Optional Extensions > Development Options", + "line_range": [ + 115, + 118 + ] + }, + { + "text": "NOTE: Ziccamoc ensures Compare and Swap instructions are properly supported in main memory regions.", + "section": "Preamble > RVA23 Profiles > RVA23U64 Profile > RVA23U64 Optional Extensions > Development Options", + "line_range": [ + 120, + 121 + ] + }, + { + "text": "Vector carryless multiplication. - Misaligned loads, stores, and AMOs to main memory regions that do not cross a naturally aligned 16-byte boundary are atomic.", + "section": "Preamble > RVA23 Profiles > RVA23U64 Profile > RVA23U64 Optional Extensions > Development Options", + "line_range": [ + 123, + 125 + ] + }, + { + "text": "NOTE: Zama16b represents the presence of the new Misaligned Atomicity Granule feature added in Sm1p13.", + "section": "Preamble > RVA23 Profiles > RVA23U64 Profile > RVA23U64 Optional Extensions > Development Options", + "line_range": [ + 127, + 128 + ] + }, + { + "text": "The following expansion options were also present in RVA22U64:", + "section": "Preamble > RVA23 Profiles > RVA23U64 Profile > RVA23U64 Optional Extensions > Expansion Options", + "line_range": [ + 132, + 132 + ] + }, + { + "text": "Scalar half-precision floating-point.", + "section": "Preamble > RVA23 Profiles > RVA23U64 Profile > RVA23U64 Optional Extensions > Expansion Options", + "line_range": [ + 134, + 134 + ] + }, + { + "text": "The following are new expansion options in RVA23U64:", + "section": "Preamble > RVA23 Profiles > RVA23U64 Profile > RVA23U64 Optional Extensions > Expansion Options", + "line_range": [ + 136, + 136 + ] + }, + { + "text": "Scalar carryless multiply. - Landing Pads. - Shadow Stack. - Vector half-precision floating-point. - Scalar BF16 converts. - Vector BF16 converts. - Vector BF16 widening mul-add.", + "section": "Preamble > RVA23 Profiles > RVA23U64 Profile > RVA23U64 Optional Extensions > Expansion Options", + "line_range": [ + 138, + 144 + ] + }, + { + "text": "There are no transitory options in RVA23U64.", + "section": "Preamble > RVA23 Profiles > RVA23U64 Profile > RVA23U64 Optional Extensions > Transitory Options", + "line_range": [ + 148, + 148 + ] + }, + { + "text": "NOTE: Scalar crypto is no longer an option in RVA23U64, though the Zbc extension has now been exposed as an expansion option.", + "section": "Preamble > RVA23 Profiles > RVA23U64 Profile > RVA23U64 Optional Extensions > Transitory Options", + "line_range": [ + 150, + 151 + ] + }, + { + "text": "Implementations are strongly recommended to raise illegal-instruction exceptions on attempts to execute unimplemented opcodes.", + "section": "Preamble > RVA23 Profiles > RVA23U64 Profile > RVA23U64 Recommendations", + "line_range": [ + 155, + 156 + ] + }, + { + "text": "The RVA23S64 profile specifies the ISA features available to a supervisor-mode execution environment in 64-bit applications processors. RVA23S64 is based on privileged architecture version 1.13.", + "section": "Preamble > RVA23 Profiles > RVA23S64 Profile", + "line_range": [ + 160, + 163 + ] + }, + { + "text": "RV64I is the mandatory base ISA for RVA23S64 and is little-endian.", + "section": "Preamble > RVA23 Profiles > RVA23S64 Profile > RVA23S64 Mandatory Base", + "line_range": [ + 167, + 171 + ] + }, + { + "text": "The `ECALL` instruction operates as per the unprivileged architecture specification.", + "section": "Preamble > RVA23 Profiles > RVA23S64 Profile > RVA23S64 Mandatory Base", + "line_range": [ + 167, + 171 + ] + }, + { + "text": "An `ECALL` in user mode causes a contained trap to supervisor mode.", + "section": "Preamble > RVA23 Profiles > RVA23S64 Profile > RVA23S64 Mandatory Base", + "line_range": [ + 167, + 171 + ] + }, + { + "text": "An `ECALL` in supervisor mode causes a requested trap to the execution environment.", + "section": "Preamble > RVA23 Profiles > RVA23S64 Profile > RVA23S64 Mandatory Base", + "line_range": [ + 167, + 171 + ] + }, + { + "text": "The following unprivileged extensions are mandatory:", + "section": "Preamble > RVA23 Profiles > RVA23S64 Profile > RVA23S64 Mandatory Extensions", + "line_range": [ + 175, + 175 + ] + }, + { + "text": "The RVA23S64 mandatory unprivileged extensions include all the mandatory unprivileged extensions in RVA23U64.", + "section": "Preamble > RVA23 Profiles > RVA23S64 Profile > RVA23S64 Mandatory Extensions", + "line_range": [ + 177, + 178 + ] + }, + { + "text": "NOTE: Zifencei is mandated as it is the only standard way to support instruction-cache coherence in RVA23 application processors. A new instruction-cache coherence mechanism is under development (tentatively named Zjid) which might be added as an option in the future.", + "section": "Preamble > RVA23 Profiles > RVA23S64 Profile > RVA23S64 Mandatory Extensions", + "line_range": [ + 182, + 186 + ] + }, + { + "text": "The following privileged extensions are mandatory:", + "section": "Preamble > RVA23 Profiles > RVA23S64 Profile > RVA23S64 Mandatory Extensions", + "line_range": [ + 188, + 188 + ] + }, + { + "text": "*Ss1p13* Supervisor architecture version 1.13.", + "section": "Preamble > RVA23 Profiles > RVA23S64 Profile > RVA23S64 Mandatory Extensions", + "line_range": [ + 190, + 190 + ] + }, + { + "text": "NOTE: Ss1p13 supersedes Ss1p12.", + "section": "Preamble > RVA23 Profiles > RVA23S64 Profile > RVA23S64 Mandatory Extensions", + "line_range": [ + 192, + 192 + ] + }, + { + "text": "The following privileged extensions were also mandatory in RVA22S64:", + "section": "Preamble > RVA23 Profiles > RVA23S64 Profile > RVA23S64 Mandatory Extensions", + "line_range": [ + 194, + 194 + ] + }, + { + "text": "The `satp` mode Bare must be supported.", + "section": "Preamble > RVA23 Profiles > RVA23S64 Profile > RVA23S64 Mandatory Extensions", + "line_range": [ + 196, + 196 + ] + }, + { + "text": "Page-based 39-bit virtual-Memory system.", + "section": "Preamble > RVA23 Profiles > RVA23S64 Profile > RVA23S64 Mandatory Extensions", + "line_range": [ + 198, + 198 + ] + }, + { + "text": "Page-fault exceptions are raised when a page is accessed when A bit is clear, or written when D bit is clear.", + "section": "Preamble > RVA23 Profiles > RVA23S64 Profile > RVA23S64 Mandatory Extensions", + "line_range": [ + 200, + 201 + ] + }, + { + "text": "Main memory regions with both the cacheability and coherence PMAs must support hardware page-table reads.", + "section": "Preamble > RVA23 Profiles > RVA23S64 Profile > RVA23S64 Mandatory Extensions", + "line_range": [ + 203, + 204 + ] + }, + { + "text": "`stvec.MODE` must be capable of holding the value 0 (Direct).", + "section": "Preamble > RVA23 Profiles > RVA23S64 Profile > RVA23S64 Mandatory Extensions", + "line_range": [ + 206, + 208 + ] + }, + { + "text": "When `stvec.MODE=Direct`, `stvec.BASE` must be capable of holding any valid four-byte-aligned address.", + "section": "Preamble > RVA23 Profiles > RVA23S64 Profile > RVA23S64 Mandatory Extensions", + "line_range": [ + 206, + 208 + ] + }, + { + "text": "`stval` must be written with the faulting virtual address for load, store, and instruction page-fault, access-fault, and misaligned exceptions, and for breakpoint exceptions that are defined to write an address to stval, other than those caused by execution of the `EBREAK` or `C.EBREAK` instructions.", + "section": "Preamble > RVA23 Profiles > RVA23S64 Profile > RVA23S64 Mandatory Extensions", + "line_range": [ + 210, + 216 + ] + }, + { + "text": "For virtual-instruction and illegal-instruction exceptions, `stval` must be written with the faulting instruction.", + "section": "Preamble > RVA23 Profiles > RVA23S64 Profile > RVA23S64 Mandatory Extensions", + "line_range": [ + 210, + 216 + ] + }, + { + "text": "For any `hpmcounter` that is not read-only zero, the corresponding bit in `scounteren` must be writable.", + "section": "Preamble > RVA23 Profiles > RVA23S64 Profile > RVA23S64 Mandatory Extensions", + "line_range": [ + 218, + 219 + ] + }, + { + "text": "Fine-grained address-translation cache invalidation.", + "section": "Preamble > RVA23 Profiles > RVA23S64 Profile > RVA23S64 Mandatory Extensions", + "line_range": [ + 223, + 223 + ] + }, + { + "text": "The following are new mandatory extensions:", + "section": "Preamble > RVA23 Profiles > RVA23S64 Profile > RVA23S64 Mandatory Extensions", + "line_range": [ + 225, + 225 + ] + }, + { + "text": "NAPOT translation contiguity.", + "section": "Preamble > RVA23 Profiles > RVA23S64 Profile > RVA23S64 Mandatory Extensions", + "line_range": [ + 227, + 227 + ] + }, + { + "text": "NOTE: Svnapot was optional in RVA22.", + "section": "Preamble > RVA23 Profiles > RVA23S64 Profile > RVA23S64 Mandatory Extensions", + "line_range": [ + 229, + 229 + ] + }, + { + "text": "supervisor-mode timer interrupts.", + "section": "Preamble > RVA23 Profiles > RVA23S64 Profile > RVA23S64 Mandatory Extensions", + "line_range": [ + 231, + 231 + ] + }, + { + "text": "NOTE: Sstc was optional in RVA22.", + "section": "Preamble > RVA23 Profiles > RVA23S64 Profile > RVA23S64 Mandatory Extensions", + "line_range": [ + 233, + 233 + ] + }, + { + "text": "count overflow and mode-based filtering.", + "section": "Preamble > RVA23 Profiles > RVA23S64 Profile > RVA23S64 Mandatory Extensions", + "line_range": [ + 235, + 235 + ] + }, + { + "text": "Pointer masking, with `senvcfg.PMM` and `henvcfg.PMM` supporting, at minimum, settings PMLEN=0 and PMLEN=7.", + "section": "Preamble > RVA23 Profiles > RVA23S64 Profile > RVA23S64 Mandatory Extensions", + "line_range": [ + 237, + 238 + ] + }, + { + "text": "`sstatus.UXL` must be capable of holding the value 2 (i.e., UXLEN=64 must be supported).", + "section": "Preamble > RVA23 Profiles > RVA23S64 Profile > RVA23S64 Mandatory Extensions", + "line_range": [ + 240, + 241 + ] + }, + { + "text": "NOTE: Ssu64xl was optional in RVA22.", + "section": "Preamble > RVA23 Profiles > RVA23S64 Profile > RVA23S64 Mandatory Extensions", + "line_range": [ + 243, + 243 + ] + }, + { + "text": "The augmented hypervisor extension.", + "section": "Preamble > RVA23 Profiles > RVA23S64 Profile > RVA23S64 Mandatory Extensions", + "line_range": [ + 245, + 245 + ] + }, + { + "text": "NOTE: Sha was optional in RVA22.", + "section": "Preamble > RVA23 Profiles > RVA23S64 Profile > RVA23S64 Mandatory Extensions", + "line_range": [ + 247, + 247 + ] + }, + { + "text": "RVA23S64 has the same unprivileged options as RVA23U64.", + "section": "Preamble > RVA23 Profiles > RVA23S64 Profile > RVA23S64 Optional Extensions", + "line_range": [ + 251, + 251 + ] + }, + { + "text": "The privileged options in RVA23S64 are listed in the following sections.", + "section": "Preamble > RVA23 Profiles > RVA23S64 Profile > RVA23S64 Optional Extensions", + "line_range": [ + 253, + 254 + ] + }, + { + "text": "There are no privileged localized options in RVA23S64.", + "section": "Preamble > RVA23 Profiles > RVA23S64 Profile > RVA23S64 Optional Extensions > Localized Options", + "line_range": [ + 258, + 258 + ] + }, + { + "text": "There are no privileged development options in RVA23S64.", + "section": "Preamble > RVA23 Profiles > RVA23S64 Profile > RVA23S64 Optional Extensions > Development Options", + "line_range": [ + 262, + 262 + ] + }, + { + "text": "The following privileged expansion options were present in RVA22S64:", + "section": "Preamble > RVA23 Profiles > RVA23S64 Profile > RVA23S64 Optional Extensions > Expansion Options", + "line_range": [ + 266, + 266 + ] + }, + { + "text": "Page-based 48-bit virtual-memory system.", + "section": "Preamble > RVA23 Profiles > RVA23S64 Profile > RVA23S64 Optional Extensions > Expansion Options", + "line_range": [ + 268, + 268 + ] + }, + { + "text": "Page-based 57-bit virtual-memory system.", + "section": "Preamble > RVA23 Profiles > RVA23S64 Profile > RVA23S64 Optional Extensions > Expansion Options", + "line_range": [ + 270, + 270 + ] + }, + { + "text": "The following are new privileged expansion options in RVA23S64", + "section": "Preamble > RVA23 Profiles > RVA23S64 Profile > RVA23S64 Optional Extensions > Expansion Options", + "line_range": [ + 274, + 274 + ] + }, + { + "text": "No non-conforming extensions are present.", + "section": "Preamble > RVA23 Profiles > RVA23S64 Profile > RVA23S64 Optional Extensions > Expansion Options", + "line_range": [ + 280, + 283 + ] + }, + { + "text": "Attempts to execute unimplemented opcodes or access unimplemented CSRs in the standard or reserved encoding spaces raises an illegal instruction exception that results in a contained trap to the supervisor-mode trap handler.", + "section": "Preamble > RVA23 Profiles > RVA23S64 Profile > RVA23S64 Optional Extensions > Expansion Options", + "line_range": [ + 280, + 283 + ] + }, + { + "text": "NOTE: Ssstrict does not prescribe behavior for the custom encoding spaces or CSRs.", + "section": "Preamble > RVA23 Profiles > RVA23S64 Profile > RVA23S64 Optional Extensions > Expansion Options", + "line_range": [ + 285, + 286 + ] + }, + { + "text": "NOTE: Ssstrict definition applies to the execution environment claiming to be RVA23S64-compatible, which must have the hypervisor extension.", + "section": "Preamble > RVA23 Profiles > RVA23S64 Profile > RVA23S64 Optional Extensions > Expansion Options", + "line_range": [ + 288, + 298 + ] + }, + { + "text": "That execution environment will take a contained trap to supervisor-mode (however that trap is implemented, including, but not limited to, emulation/delegation in the outer execution environment).", + "section": "Preamble > RVA23 Profiles > RVA23S64 Profile > RVA23S64 Optional Extensions > Expansion Options", + "line_range": [ + 288, + 298 + ] + }, + { + "text": "Ssstrict (and all the other RVA23S64 mandates and options) does not apply to any guest VMs run by a hypervisor.", + "section": "Preamble > RVA23 Profiles > RVA23S64 Profile > RVA23S64 Optional Extensions > Expansion Options", + "line_range": [ + 288, + 298 + ] + }, + { + "text": "An RVA23S64 hypervisor can provide guest VMs that are also RVA23S64-compatible but with an expanded set of emulated standard instructions.", + "section": "Preamble > RVA23 Profiles > RVA23S64 Profile > RVA23S64 Optional Extensions > Expansion Options", + "line_range": [ + 288, + 298 + ] + }, + { + "text": "An RVA23S64 hypervisor can also choose to implement guest VMs that are not RVA23S64 compatible (e.g., lacking H, or only RVA20S64).", + "section": "Preamble > RVA23 Profiles > RVA23S64 Profile > RVA23S64 Optional Extensions > Expansion Options", + "line_range": [ + 288, + 298 + ] + }, + { + "text": "Transitions from invalid to valid PTEs will be visible in bounded time without an explicit memory-management fence.", + "section": "Preamble > RVA23 Profiles > RVA23S64 Profile > RVA23S64 Optional Extensions > Expansion Options", + "line_range": [ + 300, + 301 + ] + }, + { + "text": "Supervisor-mode pointer masking, with the supervisor execution environment providing a means to select PMLEN=0 and PMLEN=7 at minimum.", + "section": "Preamble > RVA23 Profiles > RVA23S64 Profile > RVA23S64 Optional Extensions > Expansion Options", + "line_range": [ + 303, + 305 + ] + }, + { + "text": "There are no privileged transitory options in RVA23S64.", + "section": "Preamble > RVA23 Profiles > RVA23S64 Profile > RVA23S64 Optional Extensions > Transitory Options", + "line_range": [ + 309, + 309 + ] + }, + { + "text": "Implementations are strongly recommended to raise illegal-instruction exceptions when attempting to execute unimplemented opcodes or access unimplemented CSRs.", + "section": "Preamble > RVA23 Profiles > RVA23S64 Profile > RVA23S64 Recommendations", + "line_range": [ + 313, + 315 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__profiles__rvb23.json b/tools/llm-extraction/data/output/raw_chunks/src__profiles__rvb23.json new file mode 100644 index 0000000000..6d59d99b9c --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__profiles__rvb23.json @@ -0,0 +1,678 @@ +{ + "source_file": "src/profiles/rvb23.adoc", + "total": 84, + "sentences": [ + { + "text": "This chapter specifies the RVB23 profile family. RVB23 is the first major release of the RVB series of RISC-V Application Processor Profile.", + "section": "Preamble > RVB23 Profiles", + "line_range": [ + 2, + 4 + ] + }, + { + "text": "RVB profiles are intended to be used for customized 64-bit application processors that will run rich OS stacks, but usually as a custom build of standard OS source-code distributions.", + "section": "Preamble > RVB23 Profiles", + "line_range": [ + 6, + 11 + ] + }, + { + "text": "The approach is to provide a large guaranteed set of relatively inexpensive and/or widely beneficial features but allow optionality for more expensive and/or more targeted extensions.", + "section": "Preamble > RVB23 Profiles", + "line_range": [ + 6, + 11 + ] + }, + { + "text": "Unlike the RVA profiles, it is explicitly a non-goal of RVB profiles to provide a single standard ISA interface supporting a wide variety of binary kernel and binary application software distributions.", + "section": "Preamble > RVB23 Profiles", + "line_range": [ + 13, + 17 + ] + }, + { + "text": "However, individual software ecosystems may build upon RVB profiles to produce a more targeted standard interface for a certain market.", + "section": "Preamble > RVB23 Profiles", + "line_range": [ + 13, + 17 + ] + }, + { + "text": "Only user-mode (RVB23U64) and supervisor-mode (RVB23S64) profiles are specified in this family.", + "section": "Preamble > RVB23 Profiles", + "line_range": [ + 19, + 20 + ] + }, + { + "text": "The RVB23U64 profile specifies the ISA features available to user-mode execution environments in 64-bit RVB applications processors.", + "section": "Preamble > RVB23 Profiles > RVB23U64 Profile", + "line_range": [ + 24, + 25 + ] + }, + { + "text": "RV64I is the mandatory base ISA for RVB23U64 and is little-endian.", + "section": "Preamble > RVB23 Profiles > RVB23U64 Profile > RVB23U64 Mandatory Base", + "line_range": [ + 29, + 31 + ] + }, + { + "text": "As per the unprivileged architecture specification, the `ECALL` instruction causes a requested trap to the execution environment.", + "section": "Preamble > RVB23 Profiles > RVB23U64 Profile > RVB23U64 Mandatory Base", + "line_range": [ + 29, + 31 + ] + }, + { + "text": "The following mandatory extensions in RVB23U64 were also mandatory in RVA22U64.", + "section": "Preamble > RVB23 Profiles > RVB23U64 Profile > RVB23U64 Mandatory Extensions", + "line_range": [ + 35, + 36 + ] + }, + { + "text": "extlink:m[] Integer multiplication and division. - extlink:a[] Atomic instructions. - Single-precision floating-point instructions. - Double-precision floating-point instructions. - extlink:c[] Compressed instructions. - Bit-manipulation instructions. - extlink:zicsr[] CSR instructions.", + "section": "Preamble > RVB23 Profiles > RVB23U64 Profile > RVB23U64 Mandatory Extensions", + "line_range": [ + 38, + 65 + ] + }, + { + "text": "These are implied by presence of F. - Base counters and timers. - Hardware performance counters. - Main memory regions with both the cacheability and coherence PMAs must support instruction fetch, and any instruction fetches of naturally aligned power-of-2 sizes up to min(ILEN,XLEN) (i.e., 32 bits for RVB23) are atomic. - Main memory regions with both the cacheability and coherence PMAs must support RsrvEventual. - Main memory regions with both the cacheability and coherence PMAs must support all atomics in the Zaamo extension. - Misaligned loads and stores to main memory regions with both the cacheability and coherence PMAs must be supported. - Reservation sets are contiguous, naturally aligned, and a maximum of 64 bytes. - Pause hint. - Cache blocks must be 64 bytes in size, naturally aligned in the address space. - Cache-block management instructions. - Cache-block prefetch instructions. - Cache-block zero instructions. - Data-independent execution latency.", + "section": "Preamble > RVB23 Profiles > RVB23U64 Profile > RVB23U64 Mandatory Extensions", + "line_range": [ + 38, + 65 + ] + }, + { + "text": "The following mandatory extensions are also present in RVA23U64:", + "section": "Preamble > RVB23 Profiles > RVB23U64 Profile > RVB23U64 Mandatory Extensions", + "line_range": [ + 67, + 67 + ] + }, + { + "text": "Non-temporal locality hints. - Integer conditional operations. - ext:zimop[] May-be-operations. - ext:zcmop[] Compressed may-be-operations. - ext:zcb[] Additional compressed instructions. - Additional floating-point instructions. - Wait-on-reservation-set instructions.", + "section": "Preamble > RVB23 Profiles > RVB23U64 Profile > RVB23U64 Mandatory Extensions", + "line_range": [ + 69, + 75 + ] + }, + { + "text": "RVB23U64 has 18 profile options listed below.", + "section": "Preamble > RVB23 Profiles > RVB23U64 Profile > RVB23U64 Optional Extensions", + "line_range": [ + 79, + 79 + ] + }, + { + "text": "The following extensions are localized options in both RVA23U64 and RVB23U64:", + "section": "Preamble > RVB23 Profiles > RVB23U64 Profile > RVB23U64 Optional Extensions > Localized Options", + "line_range": [ + 83, + 83 + ] + }, + { + "text": "Vector crypto NIST Algorithms with GCM. - Vector crypto ShangMi Algorithms with GCM.", + "section": "Preamble > RVB23 Profiles > RVB23U64 Profile > RVB23U64 Optional Extensions > Localized Options", + "line_range": [ + 85, + 86 + ] + }, + { + "text": "The following extensions options are localized options in RVB23U64 but are not present in RVA23U64:", + "section": "Preamble > RVB23 Profiles > RVB23U64 Profile > RVB23U64 Optional Extensions > Localized Options", + "line_range": [ + 88, + 89 + ] + }, + { + "text": "Vector GCM/GMAC instructions. - Vector crypto NIST algorithms with carryless multiply. - Vector crypto ShangMi algorithms with carryless multiply.", + "section": "Preamble > RVB23 Profiles > RVB23U64 Profile > RVB23U64 Optional Extensions > Localized Options", + "line_range": [ + 91, + 93 + ] + }, + { + "text": "NOTE: RVA profiles mandate the higher-performing but more expensive GHASH options when adding vector crypto.", + "section": "Preamble > RVB23 Profiles > RVB23U64 Profile > RVB23U64 Optional Extensions > Localized Options", + "line_range": [ + 95, + 98 + ] + }, + { + "text": "To reduce implementation cost, RVB profiles also allow these carryless multiply options (Zvknc and Zvksc) to implement GCM efficiently, with GHASH available as a separate option.", + "section": "Preamble > RVB23 Profiles > RVB23U64 Profile > RVB23U64 Optional Extensions > Localized Options", + "line_range": [ + 95, + 98 + ] + }, + { + "text": "Scalar crypto NIST algorithms. - Scalar crypto ShangMi algorithms.", + "section": "Preamble > RVB23 Profiles > RVB23U64 Profile > RVB23U64 Optional Extensions > Localized Options", + "line_range": [ + 100, + 101 + ] + }, + { + "text": "NOTE: RVA23 profiles drop support for scalar crypto as an option, as the vector extension is now mandatory in RVA23. RVB23 profiles support scalar crypto, as the vector extension is optional in RVB23.", + "section": "Preamble > RVB23 Profiles > RVB23U64 Profile > RVB23U64 Optional Extensions > Localized Options", + "line_range": [ + 103, + 105 + ] + }, + { + "text": "The following are new development options intended to become mandatory in a later RVB profile:", + "section": "Preamble > RVB23 Profiles > RVB23U64 Profile > RVB23U64 Optional Extensions > Development Options", + "line_range": [ + 109, + 110 + ] + }, + { + "text": "Byte and halfword atomic memory operations. - Compare-and-Swap instructions. - Main memory regions with both the cacheability and coherence PMAs must provide `AMOCASQ` level PMA support. - Misaligned loads, stores, and AMOs to main memory regions that do not cross a naturally aligned 16-byte boundary are atomic.", + "section": "Preamble > RVB23 Profiles > RVB23U64 Profile > RVB23U64 Optional Extensions > Development Options", + "line_range": [ + 112, + 117 + ] + }, + { + "text": "The following are expansion options in RVB23U64, but are mandatory in RVA23U64.", + "section": "Preamble > RVB23 Profiles > RVB23U64 Profile > RVB23U64 Optional Extensions > Expansion Options", + "line_range": [ + 121, + 121 + ] + }, + { + "text": "ext:zfhmin[] Half-precision floating-point.", + "section": "Preamble > RVB23 Profiles > RVB23U64 Profile > RVB23U64 Optional Extensions > Expansion Options", + "line_range": [ + 123, + 123 + ] + }, + { + "text": "NOTE: Unclear if other Zve* extensions should also be supported in RVB.", + "section": "Preamble > RVB23 Profiles > RVB23U64 Profile > RVB23U64 Optional Extensions > Expansion Options", + "line_range": [ + 127, + 127 + ] + }, + { + "text": "Vector minimal half-precision floating-point. - Vector basic bit-manipulation instructions. - Vector data-independent execution latency. - Pointer masking, with the execution environment providing a means to select PMLEN=0 and PMLEN=7 at minimum.", + "section": "Preamble > RVB23 Profiles > RVB23U64 Profile > RVB23U64 Optional Extensions > Expansion Options", + "line_range": [ + 129, + 133 + ] + }, + { + "text": "The following extensions are expansion options in both RVA23U64 and RVB23U64:", + "section": "Preamble > RVB23 Profiles > RVB23U64 Profile > RVB23U64 Optional Extensions > Expansion Options", + "line_range": [ + 135, + 135 + ] + }, + { + "text": "Scalar half-precision floating-point. - Scalar carryless multiplication. - Landing Pads. - Shadow Stack. - Vector half-precision floating-point. - Scalar BF16 converts. - Vector BF16 converts. - Vector BF16 widening mul-add.", + "section": "Preamble > RVB23 Profiles > RVB23U64 Profile > RVB23U64 Optional Extensions > Expansion Options", + "line_range": [ + 137, + 144 + ] + }, + { + "text": "The following are expansion options for RVB23U64 as they are not intended to be made mandatory in future RVB profiles, but are listed as RVA23U64 development options as they are intended to become mandatory in future RVA profiles.", + "section": "Preamble > RVB23 Profiles > RVB23U64 Profile > RVB23U64 Optional Extensions > Expansion Options", + "line_range": [ + 146, + 148 + ] + }, + { + "text": "Vector carryless multiplication.", + "section": "Preamble > RVB23 Profiles > RVB23U64 Profile > RVB23U64 Optional Extensions > Expansion Options", + "line_range": [ + 150, + 150 + ] + }, + { + "text": "There are no transitory options in RVB23U64.", + "section": "Preamble > RVB23 Profiles > RVB23U64 Profile > RVB23U64 Optional Extensions > Transitory Options", + "line_range": [ + 154, + 154 + ] + }, + { + "text": "Implementations are strongly recommended to raise illegal-instruction exceptions on attempts to execute unimplemented opcodes.", + "section": "Preamble > RVB23 Profiles > RVB23U64 Profile > RVB23U64 Recommendations", + "line_range": [ + 158, + 159 + ] + }, + { + "text": "The RVB23S64 profile specifies the ISA features available to a supervisor-mode execution environment in 64-bit applications processors. RVB23S64 is based on privileged architecture version 1.13.", + "section": "Preamble > RVB23 Profiles > RVB23S64 Profile", + "line_range": [ + 163, + 165 + ] + }, + { + "text": "RV64I is the mandatory base ISA for RVB23S64 and is little-endian.", + "section": "Preamble > RVB23 Profiles > RVB23S64 Profile > RVB23S64 Mandatory Base", + "line_range": [ + 169, + 173 + ] + }, + { + "text": "The `ECALL` instruction operates as per the unprivileged architecture specification.", + "section": "Preamble > RVB23 Profiles > RVB23S64 Profile > RVB23S64 Mandatory Base", + "line_range": [ + 169, + 173 + ] + }, + { + "text": "An `ECALL` in user mode causes a contained trap to supervisor mode.", + "section": "Preamble > RVB23 Profiles > RVB23S64 Profile > RVB23S64 Mandatory Base", + "line_range": [ + 169, + 173 + ] + }, + { + "text": "An `ECALL` in supervisor mode causes a requested trap to the execution environment.", + "section": "Preamble > RVB23 Profiles > RVB23S64 Profile > RVB23S64 Mandatory Base", + "line_range": [ + 169, + 173 + ] + }, + { + "text": "The following unprivileged extensions are mandatory:", + "section": "Preamble > RVB23 Profiles > RVB23S64 Profile > RVB23S64 Mandatory Extensions", + "line_range": [ + 177, + 177 + ] + }, + { + "text": "The RVB23S64 mandatory unprivileged extensions include all the mandatory unprivileged extensions in RVB23U64.", + "section": "Preamble > RVB23 Profiles > RVB23S64 Profile > RVB23S64 Mandatory Extensions", + "line_range": [ + 179, + 180 + ] + }, + { + "text": "NOTE: Zifencei is mandated as it is the only standard way to support instruction-cache coherence in RVB23 application processors. A new instruction-cache coherence mechanism is under development (tentatively named Zjid) which might be added as an option in the future.", + "section": "Preamble > RVB23 Profiles > RVB23S64 Profile > RVB23S64 Mandatory Extensions", + "line_range": [ + 184, + 188 + ] + }, + { + "text": "The following privileged extensions are mandatory, and are also mandatory in RVA23S64.", + "section": "Preamble > RVB23 Profiles > RVB23S64 Profile > RVB23S64 Mandatory Extensions", + "line_range": [ + 190, + 191 + ] + }, + { + "text": "*Ss1p13* Supervisor architecture version 1.13.", + "section": "Preamble > RVB23 Profiles > RVB23S64 Profile > RVB23S64 Mandatory Extensions", + "line_range": [ + 193, + 193 + ] + }, + { + "text": "NOTE: Ss1p13 supersedes Ss1p12.", + "section": "Preamble > RVB23 Profiles > RVB23S64 Profile > RVB23S64 Mandatory Extensions", + "line_range": [ + 195, + 195 + ] + }, + { + "text": "NAPOT translation contiguity.", + "section": "Preamble > RVB23 Profiles > RVB23S64 Profile > RVB23S64 Mandatory Extensions", + "line_range": [ + 197, + 197 + ] + }, + { + "text": "NOTE: Svnapot is very low cost to provide, so is made mandatory even in RVB.", + "section": "Preamble > RVB23 Profiles > RVB23S64 Profile > RVB23S64 Mandatory Extensions", + "line_range": [ + 199, + 200 + ] + }, + { + "text": "The `satp` mode Bare must be supported.", + "section": "Preamble > RVB23 Profiles > RVB23S64 Profile > RVB23S64 Mandatory Extensions", + "line_range": [ + 202, + 202 + ] + }, + { + "text": "Page-Based 39-bit Virtual-Memory System.", + "section": "Preamble > RVB23 Profiles > RVB23S64 Profile > RVB23S64 Mandatory Extensions", + "line_range": [ + 204, + 204 + ] + }, + { + "text": "Page-fault exceptions are raised when a page is accessed when A bit is clear, or written when D bit is clear.", + "section": "Preamble > RVB23 Profiles > RVB23S64 Profile > RVB23S64 Mandatory Extensions", + "line_range": [ + 206, + 207 + ] + }, + { + "text": "Main memory regions with both the cacheability and coherence PMAs must support hardware page-table reads.", + "section": "Preamble > RVB23 Profiles > RVB23S64 Profile > RVB23S64 Mandatory Extensions", + "line_range": [ + 209, + 210 + ] + }, + { + "text": "`stvec.MODE` must be capable of holding the value 0 (Direct).", + "section": "Preamble > RVB23 Profiles > RVB23S64 Profile > RVB23S64 Mandatory Extensions", + "line_range": [ + 212, + 214 + ] + }, + { + "text": "When `stvec.MODE=Direct`, `stvec.BASE` must be capable of holding any valid four-byte-aligned address.", + "section": "Preamble > RVB23 Profiles > RVB23S64 Profile > RVB23S64 Mandatory Extensions", + "line_range": [ + 212, + 214 + ] + }, + { + "text": "`stval` must be written with the faulting virtual address for load, store, and instruction page-fault, access-fault, and misaligned exceptions, and for breakpoint exceptions that are defined to write an address to stval, other than those caused by execution of the `EBREAK` or `C.EBREAK` instructions.", + "section": "Preamble > RVB23 Profiles > RVB23S64 Profile > RVB23S64 Mandatory Extensions", + "line_range": [ + 216, + 222 + ] + }, + { + "text": "For virtual-instruction and illegal-instruction exceptions, `stval` must be written with the faulting instruction.", + "section": "Preamble > RVB23 Profiles > RVB23S64 Profile > RVB23S64 Mandatory Extensions", + "line_range": [ + 216, + 222 + ] + }, + { + "text": "For any `hpmcounter` that is not read-only zero, the corresponding bit in `scounteren` must be writable.", + "section": "Preamble > RVB23 Profiles > RVB23S64 Profile > RVB23S64 Mandatory Extensions", + "line_range": [ + 224, + 225 + ] + }, + { + "text": "Fine-grained address-translation cache invalidation.", + "section": "Preamble > RVB23 Profiles > RVB23S64 Profile > RVB23S64 Mandatory Extensions", + "line_range": [ + 229, + 229 + ] + }, + { + "text": "supervisor-mode timer interrupts.", + "section": "Preamble > RVB23 Profiles > RVB23S64 Profile > RVB23S64 Mandatory Extensions", + "line_range": [ + 231, + 231 + ] + }, + { + "text": "Count overflow and mode-based filtering.", + "section": "Preamble > RVB23 Profiles > RVB23S64 Profile > RVB23S64 Mandatory Extensions", + "line_range": [ + 233, + 233 + ] + }, + { + "text": "`sstatus.UXL` must be capable of holding the value 2 (i.e., UXLEN=64 must be supported).", + "section": "Preamble > RVB23 Profiles > RVB23S64 Profile > RVB23S64 Mandatory Extensions", + "line_range": [ + 235, + 236 + ] + }, + { + "text": "RVB23S64 has the same unprivileged options as RVB23U64.", + "section": "Preamble > RVB23 Profiles > RVB23S64 Profile > RVB23S64 Optional Extensions", + "line_range": [ + 240, + 240 + ] + }, + { + "text": "The privileged options in RVB23S64 are listed in the following sections.", + "section": "Preamble > RVB23 Profiles > RVB23S64 Profile > RVB23S64 Optional Extensions", + "line_range": [ + 242, + 242 + ] + }, + { + "text": "There are no privileged localized options in RVB23S64.", + "section": "Preamble > RVB23 Profiles > RVB23S64 Profile > RVB23S64 Optional Extensions > Localized Options", + "line_range": [ + 246, + 246 + ] + }, + { + "text": "There are no privileged development options in RVB23S64.", + "section": "Preamble > RVB23 Profiles > RVB23S64 Profile > RVB23S64 Optional Extensions > Development Options", + "line_range": [ + 250, + 250 + ] + }, + { + "text": "The following are privileged expansion options in RVB23S64, but are mandatory in RVA23S64:", + "section": "Preamble > RVB23 Profiles > RVB23S64 Profile > RVB23S64 Optional Extensions > Expansion Options", + "line_range": [ + 254, + 255 + ] + }, + { + "text": "Pointer masking, with `senvcfg.PMM` supporting at minimum, settings PMLEN=0 and PMLEN=7.", + "section": "Preamble > RVB23 Profiles > RVB23S64 Profile > RVB23S64 Optional Extensions > Expansion Options", + "line_range": [ + 257, + 258 + ] + }, + { + "text": "The augmented hypervisor extension.", + "section": "Preamble > RVB23 Profiles > RVB23S64 Profile > RVB23S64 Optional Extensions > Expansion Options", + "line_range": [ + 260, + 260 + ] + }, + { + "text": "When the hypervisor extension is implemented, the following are also mandatory:", + "section": "Preamble > RVB23 Profiles > RVB23S64 Profile > RVB23S64 Optional Extensions > Expansion Options", + "line_range": [ + 262, + 262 + ] + }, + { + "text": "If the hypervisor extension is implemented and pointer masking (Ssnpm) is supported then `henvcfg.PMM` must support at minimum, settings PMLEN=0 and PMLEN=7.", + "section": "Preamble > RVB23 Profiles > RVB23S64 Profile > RVB23S64 Optional Extensions > Expansion Options", + "line_range": [ + 264, + 266 + ] + }, + { + "text": "The following are privileged expansion options in RVB23S64 that are also privileged expansion options in RVA23S64:", + "section": "Preamble > RVB23 Profiles > RVB23S64 Profile > RVB23S64 Optional Extensions > Expansion Options", + "line_range": [ + 268, + 269 + ] + }, + { + "text": "Page-based 48-bit virtual-memory system.", + "section": "Preamble > RVB23 Profiles > RVB23S64 Profile > RVB23S64 Optional Extensions > Expansion Options", + "line_range": [ + 271, + 271 + ] + }, + { + "text": "Page-based 57-bit virtual-memory system.", + "section": "Preamble > RVB23 Profiles > RVB23S64 Profile > RVB23S64 Optional Extensions > Expansion Options", + "line_range": [ + 273, + 273 + ] + }, + { + "text": "No non-conforming extensions are present.", + "section": "Preamble > RVB23 Profiles > RVB23S64 Profile > RVB23S64 Optional Extensions > Expansion Options", + "line_range": [ + 281, + 284 + ] + }, + { + "text": "Attempts to execute unimplemented opcodes or access unimplemented CSRs in the standard or reserved encoding spaces raises an illegal instruction exception that results in a contained trap to the supervisor-mode trap handler.", + "section": "Preamble > RVB23 Profiles > RVB23S64 Profile > RVB23S64 Optional Extensions > Expansion Options", + "line_range": [ + 281, + 284 + ] + }, + { + "text": "NOTE: Ssstrict does not prescribe behavior for the custom encoding spaces or CSRs.", + "section": "Preamble > RVB23 Profiles > RVB23S64 Profile > RVB23S64 Optional Extensions > Expansion Options", + "line_range": [ + 286, + 287 + ] + }, + { + "text": "NOTE: Ssstrict definition applies to the execution environment claiming to be RVB23S64-compatible.", + "section": "Preamble > RVB23 Profiles > RVB23S64 Profile > RVB23S64 Optional Extensions > Expansion Options", + "line_range": [ + 289, + 299 + ] + }, + { + "text": "That execution environment will take a contained trap to supervisor-mode (however that trap is implemented, including, but not limited to, emulation/delegation in the outer execution environment).", + "section": "Preamble > RVB23 Profiles > RVB23S64 Profile > RVB23S64 Optional Extensions > Expansion Options", + "line_range": [ + 289, + 299 + ] + }, + { + "text": "Ssstrict (and all the other RVB23S64 mandates and options) does not apply to any guest VMs run by a hypervisor.", + "section": "Preamble > RVB23 Profiles > RVB23S64 Profile > RVB23S64 Optional Extensions > Expansion Options", + "line_range": [ + 289, + 299 + ] + }, + { + "text": "An RVB23S64 hypervisor can provide guest VMs that are also RVB23S64-compatible but with an expanded set of emulated standard instructions.", + "section": "Preamble > RVB23 Profiles > RVB23S64 Profile > RVB23S64 Optional Extensions > Expansion Options", + "line_range": [ + 289, + 299 + ] + }, + { + "text": "An RVB23S64 hypervisor can also choose to implement guest VMs that are not RVB23S64 compatible (e.g., only RVA20S64).", + "section": "Preamble > RVB23 Profiles > RVB23S64 Profile > RVB23S64 Optional Extensions > Expansion Options", + "line_range": [ + 289, + 299 + ] + }, + { + "text": "Transitions from invalid to valid PTEs will be visible in bounded time without an explicit memory-management fence.", + "section": "Preamble > RVB23 Profiles > RVB23S64 Profile > RVB23S64 Optional Extensions > Expansion Options", + "line_range": [ + 301, + 302 + ] + }, + { + "text": "Supervisor-mode pointer masking, with the supervisor execution environment providing a means to select PMLEN=0 and PMLEN=7 at minimum.", + "section": "Preamble > RVB23 Profiles > RVB23S64 Profile > RVB23S64 Optional Extensions > Expansion Options", + "line_range": [ + 304, + 306 + ] + }, + { + "text": "Implementations are strongly recommended to raise illegal-instruction exceptions when attempting to execute unimplemented opcodes.", + "section": "Preamble > RVB23 Profiles > RVB23S64 Profile > RVB23S64 Recommendations", + "line_range": [ + 310, + 311 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__profiles__rvi20.json b/tools/llm-extraction/data/output/raw_chunks/src__profiles__rvi20.json new file mode 100644 index 0000000000..a2ef8f8d95 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__profiles__rvi20.json @@ -0,0 +1,350 @@ +{ + "source_file": "src/profiles/rvi20.adoc", + "total": 43, + "sentences": [ + { + "text": "The RVI20 profiles document the initial set of unprivileged instructions.", + "section": "Preamble > RVI20 Profiles", + "line_range": [ + 2, + 6 + ] + }, + { + "text": "These provide a generic target for software toolchains and represent the minimum level of compatibility with RISC-V ratified standards.", + "section": "Preamble > RVI20 Profiles", + "line_range": [ + 2, + 6 + ] + }, + { + "text": "The two profiles RVI20U32 and RVI20U64 correspond to the RV32I and RV64I base ISAs respectively.", + "section": "Preamble > RVI20 Profiles", + "line_range": [ + 2, + 6 + ] + }, + { + "text": "NOTE: These are designed as unprivileged profiles as opposed to user-mode profiles.", + "section": "Preamble > RVI20 Profiles", + "line_range": [ + 8, + 12 + ] + }, + { + "text": "Code using this profile can run in any privilege mode, and so requested and fatal traps may be horizontal traps into an execution environment running in the same privilege mode.", + "section": "Preamble > RVI20 Profiles", + "line_range": [ + 8, + 12 + ] + }, + { + "text": "RVI20U32 specifies the ISA features available to generic unprivileged execution environments.", + "section": "Preamble > RVI20 Profiles > RVI20U32 Profile", + "line_range": [ + 16, + 17 + ] + }, + { + "text": "RV32I is the mandatory base ISA for RVI20U32, and is little-endian.", + "section": "Preamble > RVI20 Profiles > RVI20U32 Profile > RVI20U32 Mandatory Base", + "line_range": [ + 21, + 21 + ] + }, + { + "text": "As per the unprivileged architecture specification, the `ecall` instruction causes a requested trap to the execution environment.", + "section": "Preamble > RVI20 Profiles > RVI20U32 Profile > RVI20U32 Mandatory Base", + "line_range": [ + 23, + 24 + ] + }, + { + "text": "Misaligned loads and stores might not be supported.", + "section": "Preamble > RVI20 Profiles > RVI20U32 Profile > RVI20U32 Mandatory Base", + "line_range": [ + 26, + 26 + ] + }, + { + "text": "The `fence.tso` instruction is mandatory.", + "section": "Preamble > RVI20 Profiles > RVI20U32 Profile > RVI20U32 Mandatory Base", + "line_range": [ + 28, + 28 + ] + }, + { + "text": "NOTE: The `fence.tso` instruction was incorrectly described as optional in the 2019 ratified specifications.", + "section": "Preamble > RVI20 Profiles > RVI20U32 Profile > RVI20U32 Mandatory Base", + "line_range": [ + 30, + 32 + ] + }, + { + "text": "Later versions of correctly indicate that the instruction is mandatory.", + "section": "Preamble > RVI20 Profiles > RVI20U32 Profile > RVI20U32 Mandatory Base", + "line_range": [ + 30, + 32 + ] + }, + { + "text": "There are no mandatory extensions for RVI20U32.", + "section": "Preamble > RVI20 Profiles > RVI20U32 Profile > RVI20U32 Mandatory Extensions", + "line_range": [ + 36, + 36 + ] + }, + { + "text": "extlink:m[] Integer multiplication and division.", + "section": "Preamble > RVI20 Profiles > RVI20U32 Profile > RVI20U32 Optional Extensions", + "line_range": [ + 40, + 40 + ] + }, + { + "text": "extlink:a[] Atomic instructions.", + "section": "Preamble > RVI20 Profiles > RVI20U32 Profile > RVI20U32 Optional Extensions", + "line_range": [ + 42, + 42 + ] + }, + { + "text": "Single-precision floating-point instructions.", + "section": "Preamble > RVI20 Profiles > RVI20U32 Profile > RVI20U32 Optional Extensions", + "line_range": [ + 44, + 44 + ] + }, + { + "text": "Double-precision floating-point instructions.", + "section": "Preamble > RVI20 Profiles > RVI20U32 Profile > RVI20U32 Optional Extensions", + "line_range": [ + 46, + 46 + ] + }, + { + "text": "NOTE: The rationale to not include Q as an optional extension is that quad-precision floating-point is unlikely to be implemented in hardware, and so we do not require or expect software to expend effort optimizing use of Q instructions in case they are present.", + "section": "Preamble > RVI20 Profiles > RVI20U32 Profile > RVI20U32 Optional Extensions", + "line_range": [ + 48, + 51 + ] + }, + { + "text": "extlink:c[] Compressed Instructions.", + "section": "Preamble > RVI20 Profiles > RVI20U32 Profile > RVI20U32 Optional Extensions", + "line_range": [ + 53, + 53 + ] + }, + { + "text": "Instruction-fetch fence instruction.", + "section": "Preamble > RVI20 Profiles > RVI20U32 Profile > RVI20U32 Optional Extensions", + "line_range": [ + 55, + 55 + ] + }, + { + "text": "Misaligned loads and stores may be supported.", + "section": "Preamble > RVI20 Profiles > RVI20U32 Profile > RVI20U32 Optional Extensions", + "line_range": [ + 57, + 57 + ] + }, + { + "text": "NOTE: The Zicsr extension is not supported independent of the Zicntr or F extensions.", + "section": "Preamble > RVI20 Profiles > RVI20U32 Profile > RVI20U32 Optional Extensions", + "line_range": [ + 61, + 62 + ] + }, + { + "text": "Hardware performance counters.", + "section": "Preamble > RVI20 Profiles > RVI20U32 Profile > RVI20U32 Optional Extensions", + "line_range": [ + 64, + 64 + ] + }, + { + "text": "RVI20U64 specifies the ISA features available to generic unprivileged execution environments.", + "section": "Preamble > RVI20 Profiles > RVI20U64 Profile", + "line_range": [ + 68, + 69 + ] + }, + { + "text": "RV64I is the mandatory base ISA for RVI20U64, and is little-endian.", + "section": "Preamble > RVI20 Profiles > RVI20U64 Profile > RVI20U64 Mandatory Base", + "line_range": [ + 73, + 73 + ] + }, + { + "text": "As per the unprivileged architecture specification, the `ecall` instruction causes a requested trap to the execution environment.", + "section": "Preamble > RVI20 Profiles > RVI20U64 Profile > RVI20U64 Mandatory Base", + "line_range": [ + 75, + 76 + ] + }, + { + "text": "Misaligned loads and stores might not be supported.", + "section": "Preamble > RVI20 Profiles > RVI20U64 Profile > RVI20U64 Mandatory Base", + "line_range": [ + 78, + 78 + ] + }, + { + "text": "The `fence.tso` instruction is mandatory.", + "section": "Preamble > RVI20 Profiles > RVI20U64 Profile > RVI20U64 Mandatory Base", + "line_range": [ + 80, + 80 + ] + }, + { + "text": "NOTE: The `fence.tso` instruction was incorrectly described as optional in the 2019 ratified specifications.", + "section": "Preamble > RVI20 Profiles > RVI20U64 Profile > RVI20U64 Mandatory Base", + "line_range": [ + 82, + 90 + ] + }, + { + "text": "However, `fence.tso` is encoded within the standard `fence` encoding such that implementations must treat it as a simple global fence if they do not natively support TSO-ordering optimizations.", + "section": "Preamble > RVI20 Profiles > RVI20U64 Profile > RVI20U64 Mandatory Base", + "line_range": [ + 82, + 90 + ] + }, + { + "text": "As software can always assume without any penalty that `fence.tso` is being exploited by a hardware implementation, there is no advantage to making the instruction a profile option.", + "section": "Preamble > RVI20 Profiles > RVI20U64 Profile > RVI20U64 Mandatory Base", + "line_range": [ + 82, + 90 + ] + }, + { + "text": "Later versions of the unprivileged ISA specifications correctly indicate that `fence.tso` is mandatory.", + "section": "Preamble > RVI20 Profiles > RVI20U64 Profile > RVI20U64 Mandatory Base", + "line_range": [ + 82, + 90 + ] + }, + { + "text": "There are no mandatory extensions for RVI20U64.", + "section": "Preamble > RVI20 Profiles > RVI20U64 Profile > RVI20U64 Mandatory Extensions", + "line_range": [ + 94, + 94 + ] + }, + { + "text": "extlink:m[] Integer multiplication and division.", + "section": "Preamble > RVI20 Profiles > RVI20U64 Profile > RVI20U64 Optional Extensions", + "line_range": [ + 98, + 98 + ] + }, + { + "text": "extlink:a[] Atomic instructions.", + "section": "Preamble > RVI20 Profiles > RVI20U64 Profile > RVI20U64 Optional Extensions", + "line_range": [ + 100, + 100 + ] + }, + { + "text": "Single-precision floating-point instructions.", + "section": "Preamble > RVI20 Profiles > RVI20U64 Profile > RVI20U64 Optional Extensions", + "line_range": [ + 102, + 102 + ] + }, + { + "text": "Double-precision floating-point instructions.", + "section": "Preamble > RVI20 Profiles > RVI20U64 Profile > RVI20U64 Optional Extensions", + "line_range": [ + 104, + 104 + ] + }, + { + "text": "NOTE: The rationale to not include Q as a profile option is that quad-precision floating-point is unlikely to be implemented in hardware, and so we do not require or expect software to expend effort optimizing use of Q instructions in case they are present.", + "section": "Preamble > RVI20 Profiles > RVI20U64 Profile > RVI20U64 Optional Extensions", + "line_range": [ + 106, + 109 + ] + }, + { + "text": "extlink:c[] Compressed Instructions.", + "section": "Preamble > RVI20 Profiles > RVI20U64 Profile > RVI20U64 Optional Extensions", + "line_range": [ + 111, + 111 + ] + }, + { + "text": "Instruction-fetch fence instruction.", + "section": "Preamble > RVI20 Profiles > RVI20U64 Profile > RVI20U64 Optional Extensions", + "line_range": [ + 113, + 113 + ] + }, + { + "text": "Misaligned loads and stores may be supported.", + "section": "Preamble > RVI20 Profiles > RVI20U64 Profile > RVI20U64 Optional Extensions", + "line_range": [ + 115, + 115 + ] + }, + { + "text": "NOTE: The Zicsr extension is not supported independent of the Zicntr or F extensions.", + "section": "Preamble > RVI20 Profiles > RVI20U64 Profile > RVI20U64 Optional Extensions", + "line_range": [ + 119, + 120 + ] + }, + { + "text": "Hardware performance counters.", + "section": "Preamble > RVI20 Profiles > RVI20U64 Profile > RVI20U64 Optional Extensions", + "line_range": [ + 122, + 122 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__rv32.json b/tools/llm-extraction/data/output/raw_chunks/src__rv32.json new file mode 100644 index 0000000000..a166dc1c2a --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__rv32.json @@ -0,0 +1,1222 @@ +{ + "source_file": "src/rv32.adoc", + "total": 152, + "sentences": [ + { + "text": "This chapter describes the RV32I base integer instruction set.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1", + "line_range": [ + 3, + 3 + ] + }, + { + "text": "shows the unprivileged state for the base integer ISA.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Programmers' Model for Base Integer ISA", + "line_range": [ + 7, + 12 + ] + }, + { + "text": "For RV32I, the 32 `x` registers are each 32 bits wide, i.e., `XLEN=32`.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Programmers' Model for Base Integer ISA", + "line_range": [ + 7, + 12 + ] + }, + { + "text": "Register `x0` is hardwired with all bits equal to 0.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Programmers' Model for Base Integer ISA", + "line_range": [ + 7, + 12 + ] + }, + { + "text": "General purpose registers `x1-x31` hold values that various instructions interpret as a collection of Boolean values, or as two's complement signed binary integers or unsigned binary integers.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Programmers' Model for Base Integer ISA", + "line_range": [ + 7, + 12 + ] + }, + { + "text": "There is one additional unprivileged register: the program counter `pc` holds the address of the current instruction.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Programmers' Model for Base Integer ISA", + "line_range": [ + 14, + 16 + ] + }, + { + "text": ".RISC-V base unprivileged integer register state. [cols=\"<,^,>\",options=\"header\",width=\"50%\",align=\"center\",grid=\"rows\"] | <| [.small]XLEN-1| >| [.small]0 3+^| [.small]x0/zero 3+^| [.small]x1 3+^| [.small]x2 3+^| [.small]x3 3+^| [.small]x4 3+^| [.small]x5 3+^| [.small]x6 3+^| [.small]x7 3+^| [.small]x8 3+^| [.small]x9 3+^| [.small]x10 3+^| [.small]x11 3+^| [.small]x12 3+^| [.small]x13 3+^| [.small]x14 3+^| [.small]x15 3+^| [.small]x16 3+^| [.small]x17 3+^| [.small]x18 3+^| [.small]x19 3+^| [.small]x20 3+^| [.small]x21 3+^| [.small]x22 3+^| [.small]x23 3+^| [.small]x24 3+^| [.small]x25 3+^| [.small]x26 3+^| [.small]x27 3+^| [.small]x28 3+^| [.small]x29 3+^| [.small]x30 3+^| [.small]x31 3+^| [.small]pc |", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Programmers' Model for Base Integer ISA", + "line_range": [ + 18, + 56 + ] + }, + { + "text": "In the base RV32I ISA, there are four core instruction formats (R/I/S/U), as shown in .", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Base Instruction Formats", + "line_range": [ + 59, + 66 + ] + }, + { + "text": "All are a fixed 32 bits in length.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Base Instruction Formats", + "line_range": [ + 59, + 66 + ] + }, + { + "text": "The base ISA has `IALIGN=32`, meaning that instructions must be aligned on a four-byte boundary in memory.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Base Instruction Formats", + "line_range": [ + 59, + 66 + ] + }, + { + "text": "An instruction-address-misaligned exception is generated on a taken branch or unconditional jump if the target address is not `IALIGN-bit` aligned.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Base Instruction Formats", + "line_range": [ + 59, + 66 + ] + }, + { + "text": "This exception is reported on the branch or jump instruction, not on the target instruction.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Base Instruction Formats", + "line_range": [ + 59, + 66 + ] + }, + { + "text": "No instruction-address-misaligned exception is generated for a conditional branch that is not taken.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Base Instruction Formats", + "line_range": [ + 59, + 66 + ] + }, + { + "text": "The behavior upon decoding a reserved instruction is UNSPECIFIED.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Base Instruction Formats", + "line_range": [ + 68, + 68 + ] + }, + { + "text": "The RISC-V ISA keeps the source (rs1 and rs2) and destination (rd) registers at the same position in all formats to simplify decoding.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Base Instruction Formats", + "line_range": [ + 70, + 77 + ] + }, + { + "text": "Except for the 5-bit immediates used in , immediates are always sign-extended, and are generally packed towards the leftmost available bits in the instruction and have been allocated to reduce hardware complexity.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Base Instruction Formats", + "line_range": [ + 70, + 77 + ] + }, + { + "text": "In particular, the sign bit for all immediates is always in bit 31 of the instruction to speed sign-extension circuitry.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Base Instruction Formats", + "line_range": [ + 70, + 77 + ] + }, + { + "text": "There are a further two variants of the instruction formats (B/J) based on the handling of immediates, as shown in .", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Immediate Encoding Variants", + "line_range": [ + 84, + 85 + ] + }, + { + "text": "The only difference between the S and B formats is that the 12-bit immediate field is used to encode branch offsets in multiples of 2 in the B format.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Immediate Encoding Variants", + "line_range": [ + 91, + 96 + ] + }, + { + "text": "Instead of shifting all bits in the instruction-encoded immediate left by one in hardware as is conventionally done, the middle bits (imm[10:1]) and sign bit stay in fixed positions, while the lowest bit in S format (inst[7]) encodes a high-order bit in B format.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Immediate Encoding Variants", + "line_range": [ + 91, + 96 + ] + }, + { + "text": "Similarly, the only difference between the U and J formats is that the 20-bit immediate is shifted left by 12 bits to form U immediates and by 1 bit to form J immediates.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Immediate Encoding Variants", + "line_range": [ + 98, + 102 + ] + }, + { + "text": "The location of instruction bits in the U and J format immediates is chosen to maximize overlap with the other formats and with each other.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Immediate Encoding Variants", + "line_range": [ + 98, + 102 + ] + }, + { + "text": "shows the immediates produced by each of the base instruction formats, and is labeled to show which instruction bit (inst[y]) produces each bit of the immediate value.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Immediate Encoding Variants", + "line_range": [ + 104, + 106 + ] + }, + { + "text": "include::images/wavedrom/i-immediate.edn[]", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Immediate Encoding Variants", + "line_range": [ + 108, + 109 + ] + }, + { + "text": ".Types of immediate produced by RISC-V instructions. include::images/wavedrom/j-immediate.edn[]", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Immediate Encoding Variants", + "line_range": [ + 117, + 118 + ] + }, + { + "text": "The fields are labeled with the instruction bits used to construct their value.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Immediate Encoding Variants", + "line_range": [ + 120, + 120 + ] + }, + { + "text": "Sign extensions always uses inst[31].", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Immediate Encoding Variants", + "line_range": [ + 120, + 120 + ] + }, + { + "text": "Most integer computational instructions operate on `XLEN` bits of values held in the integer register file.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions", + "line_range": [ + 126, + 132 + ] + }, + { + "text": "Integer computational instructions are either encoded as register-immediate operations using the I-type format or as register-register operations using the R-type format.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions", + "line_range": [ + 126, + 132 + ] + }, + { + "text": "The destination is register rd for both register-immediate and register-register instructions.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions", + "line_range": [ + 126, + 132 + ] + }, + { + "text": "No integer computational instructions cause arithmetic exceptions.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions", + "line_range": [ + 126, + 132 + ] + }, + { + "text": "ADDI adds the sign-extended 12-bit immediate to register rs1.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Immediate Instructions", + "line_range": [ + 139, + 141 + ] + }, + { + "text": "Arithmetic overflow is ignored and the result is simply the low XLEN bits of the result. ADDI rd, rs1, 0 is used to implement the MV rd, rs1 assembler pseudoinstruction.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Immediate Instructions", + "line_range": [ + 139, + 141 + ] + }, + { + "text": "SLTI (set less than immediate) places the value 1 in register rd if register rs1 is less than the sign-extended immediate when both are treated as signed numbers, else 0 is written to rd. SLTIU is similar but compares the values as unsigned numbers (i.e., the immediate is first sign-extended to XLEN bits then treated as an unsigned number).", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Immediate Instructions", + "line_range": [ + 143, + 149 + ] + }, + { + "text": "Note, SLTIU rd, rs1, 1 sets rd to 1 if rs1 equals zero, otherwise sets rd to 0 (assembler pseudoinstruction SEQZ rd, rs).", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Immediate Instructions", + "line_range": [ + 143, + 149 + ] + }, + { + "text": "ANDI, ORI, XORI are logical operations that perform bitwise AND, OR, and XOR on register rs1 and the sign-extended 12-bit immediate and place the result in rd.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Immediate Instructions", + "line_range": [ + 151, + 154 + ] + }, + { + "text": "Note, XORI rd, rs1, -1 performs a bitwise logical inversion of register rs1 (assembler pseudoinstruction NOT rd, rs).", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Immediate Instructions", + "line_range": [ + 151, + 154 + ] + }, + { + "text": "Shifts by a constant are encoded as a specialization of the I-type format.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Immediate Instructions", + "line_range": [ + 160, + 166 + ] + }, + { + "text": "The operand to be shifted is in rs1, and the shift amount is encoded in the lower 5 bits of the I-immediate field.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Immediate Instructions", + "line_range": [ + 160, + 166 + ] + }, + { + "text": "The right-shift type is encoded in bit 30. SLLI is a logical left shift (zeros are shifted into the lower bits); SRLI is a logical right shift (zeros are shifted into the upper bits); and SRAI is an arithmetic right shift (the original sign bit is copied into the vacated upper bits).", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Immediate Instructions", + "line_range": [ + 160, + 166 + ] + }, + { + "text": "LUI (load upper immediate) is used to build 32-bit constants and uses the U-type format. LUI places the 32-bit U-immediate value into the destination register rd, filling in the lowest 12 bits with zeros.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Immediate Instructions", + "line_range": [ + 172, + 174 + ] + }, + { + "text": "AUIPC (add upper immediate to `pc`) is used to build `pc`-relative addresses and uses the U-type format. AUIPC forms a 32-bit offset from the U-immediate, filling in the lowest 12 bits with zeros, adds this offset to the address of the AUIPC instruction, then places the result in register rd.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Immediate Instructions", + "line_range": [ + 176, + 181 + ] + }, + { + "text": "RV32I defines several arithmetic R-type operations.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Register Instructions", + "line_range": [ + 185, + 187 + ] + }, + { + "text": "All operations read the rs1 and rs2 registers as source operands and write the result into register rd.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Register Instructions", + "line_range": [ + 185, + 187 + ] + }, + { + "text": "The funct7 and funct3 fields select the type of operation.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Register Instructions", + "line_range": [ + 185, + 187 + ] + }, + { + "text": "ADD performs the addition of rs1 and rs2. SUB performs the subtraction of rs2 from rs1.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Register Instructions", + "line_range": [ + 193, + 200 + ] + }, + { + "text": "Overflows are ignored and the low XLEN bits of results are written to the destination rd. SLT and SLTU perform signed and unsigned compares respectively, writing 1 to rd if rs1 < rs2, 0 otherwise.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Register Instructions", + "line_range": [ + 193, + 200 + ] + }, + { + "text": "Note, SLTU rd, x0, rs2 sets rd to 1 if rs2 is not equal to zero, otherwise sets rd to zero (assembler pseudoinstruction SNEZ rd, rs). AND, OR, and XOR perform bitwise logical operations.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Register Instructions", + "line_range": [ + 193, + 200 + ] + }, + { + "text": "SLL, SRL, and SRA perform logical left, logical right, and arithmetic right shifts on the value in register rs1 by the shift amount held in the lower 5 bits of register rs2.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Register Instructions", + "line_range": [ + 202, + 204 + ] + }, + { + "text": "The NOP instruction does not change any architecturally visible state, except for advancing the `pc` and incrementing any applicable performance counters. NOP is encoded as ADDI x0, x0, 0.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > NOP Instruction", + "line_range": [ + 212, + 214 + ] + }, + { + "text": "RV32I provides two types of control transfer instructions: unconditional jumps and conditional branches.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Control Transfer Instructions", + "line_range": [ + 218, + 221 + ] + }, + { + "text": "Control transfer instructions in RV32I do not have architecturally visible delay slots.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Control Transfer Instructions", + "line_range": [ + 218, + 221 + ] + }, + { + "text": "If an instruction access-fault or instruction page-fault exception occurs on the target of a jump or taken branch, the exception is reported on the target instruction, not on the jump or branch instruction.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Control Transfer Instructions", + "line_range": [ + 223, + 225 + ] + }, + { + "text": "The jump and link (JAL) instruction uses the J-type format, where the J-immediate encodes a signed offset in multiples of 2 bytes.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Control Transfer Instructions > Unconditional Jumps", + "line_range": [ + 228, + 235 + ] + }, + { + "text": "The offset is sign-extended and added to the address of the jump instruction to form the jump target address.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Control Transfer Instructions > Unconditional Jumps", + "line_range": [ + 228, + 235 + ] + }, + { + "text": "Jumps can therefore target a {pm}1 MiB range. JAL stores the address of the instruction following the jump (`pc`+4) into register rd.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Control Transfer Instructions > Unconditional Jumps", + "line_range": [ + 228, + 235 + ] + }, + { + "text": "The standard software calling convention uses `x1` as the return address register and `x5` as an alternate link register.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Control Transfer Instructions > Unconditional Jumps", + "line_range": [ + 228, + 235 + ] + }, + { + "text": "Plain unconditional jumps (assembler pseudoinstruction J) are encoded as a JAL with rd=`x0`.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Control Transfer Instructions > Unconditional Jumps", + "line_range": [ + 237, + 238 + ] + }, + { + "text": "The indirect jump instruction JALR (jump and link register) uses the I-type encoding.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Control Transfer Instructions > Unconditional Jumps", + "line_range": [ + 244, + 251 + ] + }, + { + "text": "The target address is obtained by adding the sign-extended 12-bit I-immediate to the register rs1, then setting the least-significant bit of the result to zero.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Control Transfer Instructions > Unconditional Jumps", + "line_range": [ + 244, + 251 + ] + }, + { + "text": "The address of the instruction following the jump (`pc`+4) is written to register rd.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Control Transfer Instructions > Unconditional Jumps", + "line_range": [ + 244, + 251 + ] + }, + { + "text": "Register `x0` can be used as the destination if the result is not required.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Control Transfer Instructions > Unconditional Jumps", + "line_range": [ + 244, + 251 + ] + }, + { + "text": "Plain unconditional indirect jumps (assembler pseudoinstruction JR) are encoded as a JALR with rd=`x0`.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Control Transfer Instructions > Unconditional Jumps", + "line_range": [ + 253, + 257 + ] + }, + { + "text": "Procedure returns in the standard calling convention (assembler pseudoinstruction RET) are encoded as a JALR with rd=`x0`, rs1=`x1`, and imm=0.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Control Transfer Instructions > Unconditional Jumps", + "line_range": [ + 253, + 257 + ] + }, + { + "text": "The JAL and JALR instructions will generate an instruction-address-misaligned exception if the target address is not aligned to a four-byte boundary.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Control Transfer Instructions > Unconditional Jumps", + "line_range": [ + 263, + 266 + ] + }, + { + "text": "Return-address prediction stacks are a common feature of high-performance instruction-fetch units, but require accurate detection of instructions used for procedure calls and returns to be effective.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Control Transfer Instructions > Unconditional Jumps", + "line_range": [ + 268, + 274 + ] + }, + { + "text": "For RISC-V, hints as to the instructions' usage are encoded implicitly via the register numbers used. A JAL instruction should push the return address onto a return-address stack (RAS) only when rd is `x1` or `x5`. JALR instructions should push/pop a RAS as shown in .", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Control Transfer Instructions > Unconditional Jumps", + "line_range": [ + 268, + 274 + ] + }, + { + "text": ".Return-address stack prediction hints encoded in the register operands of a JALR instruction. | |rd is x1/x5 |rs1 is x1/x5 |rd=rs1 |RAS action", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Control Transfer Instructions > Unconditional Jumps", + "line_range": [ + 276, + 280 + ] + }, + { + "text": "|Yes |Yes |No |Pop, then push", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Control Transfer Instructions > Unconditional Jumps", + "line_range": [ + 288, + 288 + ] + }, + { + "text": "All branch instructions use the B-type instruction format.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Control Transfer Instructions > Conditional Branches", + "line_range": [ + 295, + 298 + ] + }, + { + "text": "The 12-bit B-immediate encodes signed offsets in multiples of 2 bytes.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Control Transfer Instructions > Conditional Branches", + "line_range": [ + 295, + 298 + ] + }, + { + "text": "The offset is sign-extended and added to the address of the branch instruction to give the target address.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Control Transfer Instructions > Conditional Branches", + "line_range": [ + 295, + 298 + ] + }, + { + "text": "The conditional branch range is {pm}4 KiB.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Control Transfer Instructions > Conditional Branches", + "line_range": [ + 295, + 298 + ] + }, + { + "text": "Branch instructions compare two registers. BEQ and BNE take the branch if registers rs1 and rs2 are equal or unequal respectively. BLT and BLTU take the branch if rs1 is less than rs2, using signed and unsigned comparison respectively. BGE and BGEU take the branch if rs1 is greater than or equal to rs2, using signed and unsigned comparison respectively.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Control Transfer Instructions > Conditional Branches", + "line_range": [ + 304, + 311 + ] + }, + { + "text": "Note, BGT, BGTU, BLE, and BLEU can be synthesized by reversing the operands to BLT, BLTU, BGE, and BGEU, respectively.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Control Transfer Instructions > Conditional Branches", + "line_range": [ + 304, + 311 + ] + }, + { + "text": "Software should be optimized such that the sequential code path is the most common path, with less-frequently taken code paths placed out of line.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Control Transfer Instructions > Conditional Branches", + "line_range": [ + 313, + 318 + ] + }, + { + "text": "Software should also assume that backward branches will be predicted taken and forward branches as not taken, at least the first time they are encountered.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Control Transfer Instructions > Conditional Branches", + "line_range": [ + 313, + 318 + ] + }, + { + "text": "Dynamic predictors should quickly learn any predictable branch behavior.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Control Transfer Instructions > Conditional Branches", + "line_range": [ + 313, + 318 + ] + }, + { + "text": "Unlike some other architectures, the RISC-V jump (JAL with rd=`x0`) instruction should always be used for unconditional branches instead of a conditional branch instruction with an always-true condition. RISC-V jumps are also PC-relative and support a much wider offset range than branches, and will not pollute conditional-branch prediction tables.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Control Transfer Instructions > Conditional Branches", + "line_range": [ + 320, + 324 + ] + }, + { + "text": "The conditional branch instructions will generate an instruction-address-misaligned exception if the target address is not aligned to a four-byte boundary and the branch condition evaluates to true.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Control Transfer Instructions > Conditional Branches", + "line_range": [ + 326, + 330 + ] + }, + { + "text": "If the branch condition evaluates to false, the instruction-address-misaligned exception will not be raised.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Control Transfer Instructions > Conditional Branches", + "line_range": [ + 326, + 330 + ] + }, + { + "text": "RV32I is a load-store architecture, where only load and store instructions access memory and arithmetic instructions only operate on CPU registers. RV32I provides a 32-bit address space that is byte-addressed.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Load and Store Instructions", + "line_range": [ + 335, + 343 + ] + }, + { + "text": "The EEI will define what portions of the address space are legal to access with which instructions (e.g., some addresses might be read only, or support word access only).", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Load and Store Instructions", + "line_range": [ + 335, + 343 + ] + }, + { + "text": "Loads with a destination of `x0` must still raise any exceptions and cause any other side effects even though the load value is discarded.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Load and Store Instructions", + "line_range": [ + 335, + 343 + ] + }, + { + "text": "The EEI will define whether the memory system is little-endian or big-endian.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Load and Store Instructions", + "line_range": [ + 345, + 346 + ] + }, + { + "text": "In RISC-V, endianness is byte-address invariant.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Load and Store Instructions", + "line_range": [ + 345, + 346 + ] + }, + { + "text": "Load and store instructions transfer a value between the registers and memory.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Load and Store Instructions", + "line_range": [ + 352, + 357 + ] + }, + { + "text": "Loads are encoded in the I-type format and stores are S-type.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Load and Store Instructions", + "line_range": [ + 352, + 357 + ] + }, + { + "text": "The effective address is obtained by adding register rs1 to the sign-extended 12-bit offset.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Load and Store Instructions", + "line_range": [ + 352, + 357 + ] + }, + { + "text": "Loads copy a value from memory to register rd.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Load and Store Instructions", + "line_range": [ + 352, + 357 + ] + }, + { + "text": "Stores copy the value in register rs2 to memory.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Load and Store Instructions", + "line_range": [ + 352, + 357 + ] + }, + { + "text": "The LW instruction loads a 32-bit value from memory into rd. LH loads a 16-bit value from memory, then sign-extends to 32-bits before storing in rd. LHU loads a 16-bit value from memory but then zero extends to 32-bits before storing in rd. LB and LBU are defined analogously for 8-bit values.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Load and Store Instructions", + "line_range": [ + 359, + 366 + ] + }, + { + "text": "The SW, SH, and SB instructions store 32-bit, 16-bit, and 8-bit values from the low bits of register rs2 to memory.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Load and Store Instructions", + "line_range": [ + 359, + 366 + ] + }, + { + "text": "Regardless of EEI, loads and stores whose effective addresses are naturally aligned shall not raise an address-misaligned exception.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Load and Store Instructions", + "line_range": [ + 368, + 372 + ] + }, + { + "text": "Loads and stores whose effective address is not naturally aligned to the referenced datatype (i.e., the effective address is not divisible by the size of the access in bytes) have behavior dependent on the EEI.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Load and Store Instructions", + "line_range": [ + 368, + 372 + ] + }, + { + "text": "An EEI may guarantee that misaligned loads and stores are fully supported, and so the software running inside the execution environment will never experience a contained or fatal address-misaligned trap.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Load and Store Instructions", + "line_range": [ + 374, + 379 + ] + }, + { + "text": "In this case, the misaligned loads and stores can be handled in hardware, or via an invisible trap into the execution environment implementation, or possibly a combination of hardware and invisible trap depending on address.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Load and Store Instructions", + "line_range": [ + 374, + 379 + ] + }, + { + "text": "An EEI may not guarantee misaligned loads and stores are handled invisibly.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Load and Store Instructions", + "line_range": [ + 381, + 394 + ] + }, + { + "text": "In this case, loads and stores that are not naturally aligned may either complete execution successfully or raise an exception.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Load and Store Instructions", + "line_range": [ + 381, + 394 + ] + }, + { + "text": "The exception raised can be either an address-misaligned exception or an access-fault exception.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Load and Store Instructions", + "line_range": [ + 381, + 394 + ] + }, + { + "text": "For a memory access that would otherwise be able to complete except for the misalignment, an access-fault exception can be raised instead of an address-misaligned exception if the misaligned access should not be emulated, e.g., if accesses to the memory region have side effects.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Load and Store Instructions", + "line_range": [ + 381, + 394 + ] + }, + { + "text": "When an EEI does not guarantee misaligned loads and stores are handled invisibly, the EEI must define if exceptions caused by address misalignment result in a contained trap (allowing software running inside the execution environment to handle the trap) or a fatal trap (terminating execution).", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Load and Store Instructions", + "line_range": [ + 381, + 394 + ] + }, + { + "text": "Even when misaligned loads and stores complete successfully, these accesses might run extremely slowly depending on the implementation (e.g., when implemented via an invisible trap).", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Load and Store Instructions", + "line_range": [ + 396, + 402 + ] + }, + { + "text": "Furthermore, whereas naturally aligned loads and stores are guaranteed to execute atomically, misaligned loads and stores might not, and hence require additional synchronization to ensure atomicity.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Load and Store Instructions", + "line_range": [ + 396, + 402 + ] + }, + { + "text": "FENCE instructions are used to order device I/O and memory accesses as viewed by other RISC-V harts and external devices or coprocessors.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Memory Ordering Instructions", + "line_range": [ + 410, + 418 + ] + }, + { + "text": "Any combination of device input (I), device output (O), memory reads \\(R), and memory writes (W) may be ordered with respect to any combination of the same.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Memory Ordering Instructions", + "line_range": [ + 410, + 418 + ] + }, + { + "text": "Informally, no other RISC-V hart or external device can observe any operation in the successor set following a FENCE before any operation in the predecessor set preceding the FENCE. provides a precise description of the RISC-V memory consistency model.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Memory Ordering Instructions", + "line_range": [ + 410, + 418 + ] + }, + { + "text": "FENCE instructions also order memory reads and writes made by the hart as observed by memory reads and writes made by an external device.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Memory Ordering Instructions", + "line_range": [ + 420, + 423 + ] + }, + { + "text": "However, FENCE instructions do not order observations of events made by an external device using any other signaling mechanism.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Memory Ordering Instructions", + "line_range": [ + 420, + 423 + ] + }, + { + "text": "The EEI will define what I/O operations are possible, and in particular, which memory addresses when accessed by load and store instructions will be treated and ordered as device input and device output operations respectively rather than memory reads and writes.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Memory Ordering Instructions", + "line_range": [ + 425, + 433 + ] + }, + { + "text": "For example, memory-mapped I/O devices will typically be accessed with uncached loads and stores that are ordered using the I and O bits rather than the R and W bits.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Memory Ordering Instructions", + "line_range": [ + 425, + 433 + ] + }, + { + "text": "Instruction-set extensions might also describe new I/O instructions that will also be ordered using the I and O bits in a FENCE instruction.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Memory Ordering Instructions", + "line_range": [ + 425, + 433 + ] + }, + { + "text": "[float=\"center\",align=\"center\",cols=\"^1,^1,<3\",options=\"header\"] .Fence mode encoding | |fm field |Mnemonic suffix|Meaning |0000 |none |Normal Fence |1000 |.TSO |With `FENCE RW,RW`: exclude write-to-read ordering; otherwise: Reserved for future use. |other|other |Reserved for future use. |", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Memory Ordering Instructions", + "line_range": [ + 435, + 443 + ] + }, + { + "text": "The FENCE mode field fm defines the semantics of the FENCE instruction. A `FENCE` (with fm=`0000`) orders all memory operations in its predecessor set before all memory operations in its successor set.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Memory Ordering Instructions", + "line_range": [ + 445, + 448 + ] + }, + { + "text": "A `FENCE.TSO` instruction is encoded as a FENCE instruction with fm=`1000`, predecessor=`RW`, and successor=`RW`. `FENCE.TSO` orders all load operations in its predecessor set before all memory operations in its successor set, and all store operations in its predecessor set before all store operations in its successor set.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Memory Ordering Instructions", + "line_range": [ + 450, + 457 + ] + }, + { + "text": "This leaves `non-AMO` store operations in the `FENCE.TSO's` predecessor set unordered with `non-AMO` loads in its successor set.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Memory Ordering Instructions", + "line_range": [ + 450, + 457 + ] + }, + { + "text": "The unused fields in the FENCE instructions--rs1 and rd--are reserved for finer-grain fences in future extensions.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Memory Ordering Instructions", + "line_range": [ + 459, + 467 + ] + }, + { + "text": "For forward compatibility, base implementations shall ignore these fields, and standard software shall zero these fields.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Memory Ordering Instructions", + "line_range": [ + 459, + 467 + ] + }, + { + "text": "Likewise, many fm and predecessor/successor set settings are also reserved for future use.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Memory Ordering Instructions", + "line_range": [ + 459, + 467 + ] + }, + { + "text": "Base implementations shall treat all such reserved configurations as `FENCE` instructions (with fm=`0000`), and standard software shall use only non-reserved configurations.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Memory Ordering Instructions", + "line_range": [ + 459, + 467 + ] + }, + { + "text": "`SYSTEM` instructions are used to access system functionality that might require privileged access and are encoded using the I-type instruction format.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Environment Call and Breakpoints", + "line_range": [ + 472, + 478 + ] + }, + { + "text": "These can be divided into two main classes: those that atomically read-modify-write control and status registers (CSRs), and all other potentially privileged instructions. CSR instructions are described in , and the base unprivileged instructions are described in the following section.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Environment Call and Breakpoints", + "line_range": [ + 472, + 478 + ] + }, + { + "text": "These two instructions cause a precise requested trap to the supporting execution environment.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Environment Call and Breakpoints", + "line_range": [ + 484, + 485 + ] + }, + { + "text": "The `ECALL` instruction is used to make a service request to the execution environment.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Environment Call and Breakpoints", + "line_range": [ + 487, + 490 + ] + }, + { + "text": "The `EEI` will define how parameters for the service request are passed, but usually these will be in defined locations in the integer register file.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Environment Call and Breakpoints", + "line_range": [ + 487, + 490 + ] + }, + { + "text": "The `EBREAK` instruction is used to return control to a debugging environment.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > Environment Call and Breakpoints", + "line_range": [ + 492, + 492 + ] + }, + { + "text": "RV32I reserves a large encoding space for HINT instructions, which are usually used to communicate performance hints to the microarchitecture.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > HINT Instructions", + "line_range": [ + 500, + 505 + ] + }, + { + "text": "Like the NOP instruction, HINTs do not change any architecturally visible state, except for advancing the `pc` and any applicable performance counters.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > HINT Instructions", + "line_range": [ + 500, + 505 + ] + }, + { + "text": "Implementations are always allowed to ignore the encoded hints.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > HINT Instructions", + "line_range": [ + 500, + 505 + ] + }, + { + "text": "Most RV32I HINTs are encoded as integer computational instructions with rd=`x0`.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > HINT Instructions", + "line_range": [ + 507, + 509 + ] + }, + { + "text": "The other RV32I HINTs are encoded as FENCE instructions with a null predecessor or successor set and with fm=0.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > HINT Instructions", + "line_range": [ + 507, + 509 + ] + }, + { + "text": "lists all RV32I HINT code points. 91% of the HINT space is reserved for standard HINTs.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > HINT Instructions", + "line_range": [ + 511, + 514 + ] + }, + { + "text": "The remainder of the HINT space is designated for custom HINTs: no standard HINTs will ever be defined in this subspace.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > HINT Instructions", + "line_range": [ + 511, + 514 + ] + }, + { + "text": ".RV32I HINT instructions. [float=\"center\",align=\"center\",cols=\"<,<,^,<\",options=\"header\"] | |Instruction |Constraints |Code Points |Purpose", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > HINT Instructions", + "line_range": [ + 518, + 522 + ] + }, + { + "text": "|LUI |rd=`x0` |2^20^ .8+<.^m|Designated for future standard use", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > HINT Instructions", + "line_range": [ + 524, + 524 + ] + }, + { + "text": "|ADDI |rd=`x0`, and either rs1{ne}``x0`` or imm{ne}0 |2^17^−1", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > HINT Instructions", + "line_range": [ + 528, + 528 + ] + }, + { + "text": "|ADD |rd=`x0`, rs1{ne}``x0`` |2^10^−32", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > HINT Instructions", + "line_range": [ + 536, + 536 + ] + }, + { + "text": "|ADD |rd=`x0`, rs1=`x0`, rs2{ne}``x2-x5`` | 28", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > HINT Instructions", + "line_range": [ + 538, + 538 + ] + }, + { + "text": "|ADD |rd=`x0`, rs1=`x0`, rs2=`x2-x5` |4|(rs2=`x2`) NTL.P1 + (rs2=`x3`) NTL.PALL + (rs2=`x4`) NTL.S1 + (rs2=`x5`) NTL.ALL", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > HINT Instructions", + "line_range": [ + 540, + 543 + ] + }, + { + "text": "|SLLI |rd=`x0`, rs1=`x0`, shamt=31 |1|Semihosting entry marker", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > HINT Instructions", + "line_range": [ + 545, + 545 + ] + }, + { + "text": "|SRAI |rd=`x0`, rs1=`x0`, shamt=7 |1|Semihosting exit marker", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > HINT Instructions", + "line_range": [ + 547, + 547 + ] + }, + { + "text": "|SUB |rd=`x0` |2^10^ .11+<.^m|Designated for future standard use", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > HINT Instructions", + "line_range": [ + 549, + 549 + ] + }, + { + "text": "|FENCE |rd=`x0`, rs1{ne}``x0``, fm=0, and either pred=0 or succ=0| 2^10^−63", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > HINT Instructions", + "line_range": [ + 563, + 563 + ] + }, + { + "text": "|FENCE |rd{ne}``x0``, rs1=`x0`, fm=0, and either pred=0 or succ=0| 2^10^−63", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > HINT Instructions", + "line_range": [ + 565, + 565 + ] + }, + { + "text": "|FENCE |rd=rs1=`x0`, fm=0, pred=0, succ{ne}0 |15", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > HINT Instructions", + "line_range": [ + 567, + 567 + ] + }, + { + "text": "|FENCE |rd=rs1=`x0`, fm=0, pred{ne}W, succ=0 |15", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > HINT Instructions", + "line_range": [ + 569, + 569 + ] + }, + { + "text": "|FENCE |rd=rs1=`x0`, fm=0, pred=W, succ=0 |1 |PAUSE", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > HINT Instructions", + "line_range": [ + 571, + 571 + ] + }, + { + "text": "|SLTI |rd=`x0` |2^17^ .7+<.^m|Designated for custom use", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > HINT Instructions", + "line_range": [ + 575, + 575 + ] + }, + { + "text": "|SLLI |rd=`x0`, and either rs1{ne}``x0`` or shamt{ne}31 |2^10^−1", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > HINT Instructions", + "line_range": [ + 579, + 579 + ] + }, + { + "text": "|SRAI |rd=`x0`, and either rs1{ne}``x0`` or shamt{ne}7 |2^10^−1", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > HINT Instructions", + "line_range": [ + 583, + 583 + ] + }, + { + "text": "NOTE: `slli x0, x0, 0x1f` and `srai x0, x0, 7` were previously designated as custom HINTs, but they have been appropriated for use in semihosting calls, as described in .", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > HINT Instructions", + "line_range": [ + 590, + 594 + ] + }, + { + "text": "To reflect their usage in practice, the base ISA spec has been changed to designate them as standard HINTs.", + "section": "Preamble > RV32I Base Integer Instruction Set, Version 2.1 > HINT Instructions", + "line_range": [ + 590, + 594 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__rv32e.json b/tools/llm-extraction/data/output/raw_chunks/src__rv32e.json new file mode 100644 index 0000000000..f861cc0811 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__rv32e.json @@ -0,0 +1,46 @@ +{ + "source_file": "src/rv32e.adoc", + "total": 5, + "sentences": [ + { + "text": "This chapter describes the RV32E and RV64E base integer instruction sets, designed for microcontrollers in embedded systems. RV32E and RV64E are reduced versions of RV32I and RV64I, respectively: the only change is to reduce the number of integer registers to 16.", + "section": "Preamble > RV32E and RV64E Base Integer Instruction Sets, Version 2.0", + "line_range": [ + 3, + 9 + ] + }, + { + "text": "This chapter only outlines the differences between RV32E/RV64E and RV32I/RV64I, and so should be read after and .", + "section": "Preamble > RV32E and RV64E Base Integer Instruction Sets, Version 2.0", + "line_range": [ + 3, + 9 + ] + }, + { + "text": "RV32E and RV64E reduce the integer register count to 16 general-purpose registers, (`x0-x15`), where `x0` is a dedicated zero register.", + "section": "Preamble > RV32E and RV64E Base Integer Instruction Sets, Version 2.0 > RV32E and RV64E Programmers’ Model", + "line_range": [ + 11, + 12 + ] + }, + { + "text": "RV32E and RV64E use the same instruction-set encoding as RV32I and RV64I respectively, except that only registers `x0-x15` are provided.", + "section": "Preamble > RV32E and RV64E Base Integer Instruction Sets, Version 2.0 > RV32E and RV64E Instruction Set Encoding", + "line_range": [ + 15, + 19 + ] + }, + { + "text": "All encodings specifying the other registers `x16-x31` are reserved.", + "section": "Preamble > RV32E and RV64E Base Integer Instruction Sets, Version 2.0 > RV32E and RV64E Instruction Set Encoding", + "line_range": [ + 15, + 19 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__rv64.json b/tools/llm-extraction/data/output/raw_chunks/src__rv64.json new file mode 100644 index 0000000000..8008a66ef0 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__rv64.json @@ -0,0 +1,406 @@ +{ + "source_file": "src/rv64.adoc", + "total": 50, + "sentences": [ + { + "text": "This chapter describes the RV64I base integer instruction set, which builds upon the RV32I variant described in .", + "section": "Preamble > RV64I Base Integer Instruction Set, Version 2.1", + "line_range": [ + 3, + 6 + ] + }, + { + "text": "This chapter presents only the differences with RV32I, so should be read in conjunction with the earlier chapter.", + "section": "Preamble > RV64I Base Integer Instruction Set, Version 2.1", + "line_range": [ + 3, + 6 + ] + }, + { + "text": "RV64I widens the integer registers and supported user address space to 64 bits (XLEN=64 in ).", + "section": "Preamble > RV64I Base Integer Instruction Set, Version 2.1 > Register State", + "line_range": [ + 10, + 11 + ] + }, + { + "text": "Most integer computational instructions operate on XLEN-bit values.", + "section": "Preamble > RV64I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions", + "line_range": [ + 15, + 20 + ] + }, + { + "text": "Additional instruction variants are provided to manipulate 32-bit values in RV64I, indicated by a 'W' suffix to the opcode.", + "section": "Preamble > RV64I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions", + "line_range": [ + 15, + 20 + ] + }, + { + "text": "These \"*W\" instructions ignore the upper 32 bits of their inputs and always produce 32-bit signed values, sign-extending them to 64 bits, i.e. bits XLEN-1 through 31 are equal.", + "section": "Preamble > RV64I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions", + "line_range": [ + 15, + 20 + ] + }, + { + "text": "ADDIW is an RV64I instruction that adds the sign-extended 12-bit immediate to register rs1 and produces the proper sign extension of a 32-bit result in rd.", + "section": "Preamble > RV64I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Immediate Instructions", + "line_range": [ + 31, + 36 + ] + }, + { + "text": "Overflows are ignored and the result is the low 32 bits of the result sign-extended to 64 bits.", + "section": "Preamble > RV64I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Immediate Instructions", + "line_range": [ + 31, + 36 + ] + }, + { + "text": "Note, ADDIW rd, rs1, 0 writes the sign extension of the lower 32 bits of register rs1 into register rd (assembler pseudoinstruction SEXT.W).", + "section": "Preamble > RV64I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Immediate Instructions", + "line_range": [ + 31, + 36 + ] + }, + { + "text": "Shifts by a constant are encoded as a specialization of the I-type format using the same instruction opcode as RV32I.", + "section": "Preamble > RV64I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Immediate Instructions", + "line_range": [ + 42, + 53 + ] + }, + { + "text": "The operand to be shifted is in rs1, and the shift amount is encoded in the lower 6 bits of the I-immediate field for RV64I.", + "section": "Preamble > RV64I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Immediate Instructions", + "line_range": [ + 42, + 53 + ] + }, + { + "text": "The right-shift type is encoded in bit 30. SLLI is a logical left shift (zeros are shifted into the lower bits); SRLI is a logical right shift (zeros are shifted into the upper bits); and SRAI is an arithmetic right shift (the original sign bit is copied into the vacated upper bits).", + "section": "Preamble > RV64I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Immediate Instructions", + "line_range": [ + 42, + 53 + ] + }, + { + "text": "SLLIW, SRLIW, and SRAIW are RV64I-only instructions that are analogously defined but operate on 32-bit values and sign-extend their 32-bit results to 64 bits. SLLIW, SRLIW, and SRAIW encodings with imm[5] {ne} 0 are reserved.", + "section": "Preamble > RV64I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Immediate Instructions", + "line_range": [ + 58, + 61 + ] + }, + { + "text": "LUI (load upper immediate) uses the same opcode as RV32I. LUI places the 32-bit U-immediate into register rd, filling in the lowest 12 bits with zeros.", + "section": "Preamble > RV64I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Immediate Instructions", + "line_range": [ + 67, + 71 + ] + }, + { + "text": "The 32-bit result is sign-extended to 64 bits.", + "section": "Preamble > RV64I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Immediate Instructions", + "line_range": [ + 67, + 71 + ] + }, + { + "text": "AUIPC (add upper immediate to `pc`) uses the same opcode as RV32I. AUIPC is used to build `pc`-relative addresses and uses the U-type format. AUIPC forms a 32-bit offset from the U-immediate, filling in the lowest 12 bits with zeros, sign-extends the result to 64 bits, adds it to the address of the AUIPC instruction, then places the result in register rd.", + "section": "Preamble > RV64I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Immediate Instructions", + "line_range": [ + 73, + 77 + ] + }, + { + "text": "ADDW and SUBW are RV64I-only instructions that are defined analogously to ADD and SUB but operate on 32-bit values and produce signed 32-bit results.", + "section": "Preamble > RV64I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Register Operations", + "line_range": [ + 86, + 91 + ] + }, + { + "text": "Overflows are ignored, and the low 32-bits of the result is sign-extended to 64-bits and written to the destination register.", + "section": "Preamble > RV64I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Register Operations", + "line_range": [ + 86, + 91 + ] + }, + { + "text": "SLL, SRL, and SRA perform logical left, logical right, and arithmetic right shifts on the value in register rs1 by the shift amount held in register rs2.", + "section": "Preamble > RV64I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Register Operations", + "line_range": [ + 93, + 96 + ] + }, + { + "text": "In RV64I, only the low 6 bits of rs2 are considered for the shift amount.", + "section": "Preamble > RV64I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Register Operations", + "line_range": [ + 93, + 96 + ] + }, + { + "text": "SLLW, SRLW, and SRAW are RV64I-only instructions that are analogously defined but operate on 32-bit values and sign-extend their 32-bit results to 64 bits.", + "section": "Preamble > RV64I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Register Operations", + "line_range": [ + 98, + 103 + ] + }, + { + "text": "The shift amount is given by rs2[4:0].", + "section": "Preamble > RV64I Base Integer Instruction Set, Version 2.1 > Integer Computational Instructions > Integer Register-Register Operations", + "line_range": [ + 98, + 103 + ] + }, + { + "text": "RV64I extends the address space to 64 bits.", + "section": "Preamble > RV64I Base Integer Instruction Set, Version 2.1 > Load and Store Instructions", + "line_range": [ + 107, + 108 + ] + }, + { + "text": "The execution environment will define what portions of the address space are legal to access.", + "section": "Preamble > RV64I Base Integer Instruction Set, Version 2.1 > Load and Store Instructions", + "line_range": [ + 107, + 108 + ] + }, + { + "text": "The LD instruction loads a 64-bit value from memory into register rd for RV64I.", + "section": "Preamble > RV64I Base Integer Instruction Set, Version 2.1 > Load and Store Instructions", + "line_range": [ + 114, + 116 + ] + }, + { + "text": "The LW instruction loads a 32-bit value from memory and sign-extends this to 64 bits before storing it in register rd for RV64I.", + "section": "Preamble > RV64I Base Integer Instruction Set, Version 2.1 > Load and Store Instructions", + "line_range": [ + 118, + 124 + ] + }, + { + "text": "The LWU instruction, on the other hand, zero-extends the 32-bit value from memory for RV64I. LH and LHU are defined analogously for 16-bit values, as are LB and LBU for 8-bit values.", + "section": "Preamble > RV64I Base Integer Instruction Set, Version 2.1 > Load and Store Instructions", + "line_range": [ + 118, + 124 + ] + }, + { + "text": "The SD, SW, SH, and SB instructions store 64-bit, 32-bit, 16-bit, and 8-bit values from the low bits of register rs2 to memory respectively.", + "section": "Preamble > RV64I Base Integer Instruction Set, Version 2.1 > Load and Store Instructions", + "line_range": [ + 118, + 124 + ] + }, + { + "text": "All instructions that are microarchitectural HINTs in RV32I (see ) are also HINTs in RV64I.", + "section": "Preamble > RV64I Base Integer Instruction Set, Version 2.1 > HINT Instructions", + "line_range": [ + 129, + 133 + ] + }, + { + "text": "The additional computational instructions in RV64I expand both the standard and custom HINT encoding spaces.", + "section": "Preamble > RV64I Base Integer Instruction Set, Version 2.1 > HINT Instructions", + "line_range": [ + 129, + 133 + ] + }, + { + "text": "lists all RV64I HINT code points. 91% of the HINT space is reserved for standard HINTs.", + "section": "Preamble > RV64I Base Integer Instruction Set, Version 2.1 > HINT Instructions", + "line_range": [ + 135, + 138 + ] + }, + { + "text": "The remainder of the HINT space is designated for custom HINTs; no standard HINTs will ever be defined in this subspace.", + "section": "Preamble > RV64I Base Integer Instruction Set, Version 2.1 > HINT Instructions", + "line_range": [ + 135, + 138 + ] + }, + { + "text": ".RV64I HINT instructions. [float=\"center\",align=\"center\",cols=\"<,<,^,<\", options=\"header\", grid=\"all\"] | |Instruction |Constraints |Code Points |Purpose |LUI |rd=`x0` |2^20^ .9+.^|Designated for future standard use", + "section": "Preamble > RV64I Base Integer Instruction Set, Version 2.1 > HINT Instructions", + "line_range": [ + 140, + 145 + ] + }, + { + "text": "|ADDI |rd=`x0`, and either rs1{ne}`x0` or imm{ne}0 |2^17^−1", + "section": "Preamble > RV64I Base Integer Instruction Set, Version 2.1 > HINT Instructions", + "line_range": [ + 149, + 149 + ] + }, + { + "text": "|ADD |rd=`x0`, rs1{ne}`x0` |2^10^−32", + "section": "Preamble > RV64I Base Integer Instruction Set, Version 2.1 > HINT Instructions", + "line_range": [ + 159, + 159 + ] + }, + { + "text": "|ADD |rd=`x0`, rs1=`x0`, rs2{ne}x2-x5 | 28", + "section": "Preamble > RV64I Base Integer Instruction Set, Version 2.1 > HINT Instructions", + "line_range": [ + 161, + 161 + ] + }, + { + "text": "|ADD |rd=`x0`, rs1=`x0`, rs2=x2-x5| 4 | (rs2=x2) NTL.P1 + (rs2=x3) NTL.PALL + (rs2=x4) NTL.S1 + (rs2=x5) NTL.ALL", + "section": "Preamble > RV64I Base Integer Instruction Set, Version 2.1 > HINT Instructions", + "line_range": [ + 163, + 166 + ] + }, + { + "text": "|SLLI |rd=`x0`, rs1=`x0`, shamt=31 |1|Semihosting entry marker", + "section": "Preamble > RV64I Base Integer Instruction Set, Version 2.1 > HINT Instructions", + "line_range": [ + 168, + 168 + ] + }, + { + "text": "|SRAI |rd=`x0`, rs1=`x0`, shamt=7 |1|Semihosting exit marker", + "section": "Preamble > RV64I Base Integer Instruction Set, Version 2.1 > HINT Instructions", + "line_range": [ + 170, + 170 + ] + }, + { + "text": "|SUB |rd=`x0` |2^10^ .16+.^| Designated for future standard use", + "section": "Preamble > RV64I Base Integer Instruction Set, Version 2.1 > HINT Instructions", + "line_range": [ + 172, + 172 + ] + }, + { + "text": "|FENCE |rd=`x0`, rs1{ne}``x0``, fm=0, and either pred=0 or succ=0| 2^10^−63", + "section": "Preamble > RV64I Base Integer Instruction Set, Version 2.1 > HINT Instructions", + "line_range": [ + 196, + 196 + ] + }, + { + "text": "|FENCE |rd{ne}``x0``, rs1=`x0`, fm=0, and either pred=0 or succ=0| 2^10^−63", + "section": "Preamble > RV64I Base Integer Instruction Set, Version 2.1 > HINT Instructions", + "line_range": [ + 198, + 198 + ] + }, + { + "text": "|FENCE |rd=rs1=`x0`, fm=0, pred=0, succ{ne}0 |15", + "section": "Preamble > RV64I Base Integer Instruction Set, Version 2.1 > HINT Instructions", + "line_range": [ + 200, + 200 + ] + }, + { + "text": "|FENCE |rd=rs1=`x0`, fm=0, pred{ne}W, succ=0 |15", + "section": "Preamble > RV64I Base Integer Instruction Set, Version 2.1 > HINT Instructions", + "line_range": [ + 202, + 202 + ] + }, + { + "text": "|FENCE |rd=rs1=`x0`, fm=0, pred=W, succ=0 |1 |PAUSE", + "section": "Preamble > RV64I Base Integer Instruction Set, Version 2.1 > HINT Instructions", + "line_range": [ + 204, + 204 + ] + }, + { + "text": "|SLTI |rd=`x0` |2^17^ .10+.^|Designated for custom use", + "section": "Preamble > RV64I Base Integer Instruction Set, Version 2.1 > HINT Instructions", + "line_range": [ + 206, + 206 + ] + }, + { + "text": "|SLLI |rd=`x0`, and either rs1{ne}``x0`` or shamt{ne}31 |2^11^−1", + "section": "Preamble > RV64I Base Integer Instruction Set, Version 2.1 > HINT Instructions", + "line_range": [ + 210, + 210 + ] + }, + { + "text": "|SRAI |rd=`x0`, and either rs1{ne}``x0`` or shamt{ne}7 |2^11^−1", + "section": "Preamble > RV64I Base Integer Instruction Set, Version 2.1 > HINT Instructions", + "line_range": [ + 214, + 214 + ] + }, + { + "text": "NOTE: `slli x0, x0, 0x1f` and `srai x0, x0, 7` were previously designated as custom HINTs, but they have been appropriated for use in semihosting calls, as described in .", + "section": "Preamble > RV64I Base Integer Instruction Set, Version 2.1 > HINT Instructions", + "line_range": [ + 227, + 231 + ] + }, + { + "text": "To reflect their usage in practice, the base ISA spec has been changed to designate them as standard HINTs.", + "section": "Preamble > RV64I Base Integer Instruction Set, Version 2.1 > HINT Instructions", + "line_range": [ + 227, + 231 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__scalar-crypto.json b/tools/llm-extraction/data/output/raw_chunks/src__scalar-crypto.json new file mode 100644 index 0000000000..e114738c44 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__scalar-crypto.json @@ -0,0 +1,8606 @@ +{ + "source_file": "src/scalar-crypto.adoc", + "total": 1075, + "sentences": [ + { + "text": "This chapter describes the scalar cryptography extension for RISC-V.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Introduction", + "line_range": [ + 6, + 13 + ] + }, + { + "text": "All instructions described herein use the general-purpose `X` registers, and obey the 2-read-1-write register access constraint.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Introduction", + "line_range": [ + 6, + 13 + ] + }, + { + "text": "These instructions are designed to be lightweight and suitable for `32` and `64` bit base architectures; from embedded IoT class cores to large, application class cores which do not implement a vector unit.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Introduction", + "line_range": [ + 6, + 13 + ] + }, + { + "text": "This chapter also describes the architectural interface to an Entropy Source, which can be used to generate cryptographic secrets.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Introduction", + "line_range": [ + 15, + 17 + ] + }, + { + "text": "It also contains a mechanism allowing core implementers to provide \"Constant Time Execution\" guarantees in .", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Introduction", + "line_range": [ + 19, + 20 + ] + }, + { + "text": "Cryptography is a specialised subject, requiring people with many different backgrounds to cooperate in its secure and efficient implementation.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Introduction > Intended Audience", + "line_range": [ + 25, + 30 + ] + }, + { + "text": "Where possible, we have written this specification to be understandable by all, though we recognise that the motivations and references to algorithms or other specifications and standards may be unfamiliar to those who are not domain experts.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Introduction > Intended Audience", + "line_range": [ + 25, + 30 + ] + }, + { + "text": "This specification anticipates being read and acted on by various people with different backgrounds.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Introduction > Intended Audience", + "line_range": [ + 32, + 39 + ] + }, + { + "text": "We have tried to capture these backgrounds here, with a brief explanation of what we expect them to know, and how it relates to the specification.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Introduction > Intended Audience", + "line_range": [ + 32, + 39 + ] + }, + { + "text": "We hope this aids people's understanding of which aspects of the specification are particularly relevant to them, and which they may (safely!) ignore or pass to a colleague.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Introduction > Intended Audience", + "line_range": [ + 32, + 39 + ] + }, + { + "text": "Cryptographers and cryptographic software developers:: These are the people we expect to write code using the instructions in this specification.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Introduction > Intended Audience", + "line_range": [ + 41, + 51 + ] + }, + { + "text": "They should understand fairly obviously the motivations for the instructions we include, and be familiar with most of the algorithms and outside standards to which we refer.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Introduction > Intended Audience", + "line_range": [ + 41, + 51 + ] + }, + { + "text": "We expect the sections on constant time execution () and the entropy source () to be chiefly understood with their help.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Introduction > Intended Audience", + "line_range": [ + 41, + 51 + ] + }, + { + "text": "Computer architects:: We do not expect architects to have a cryptography background.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Introduction > Intended Audience", + "line_range": [ + 53, + 58 + ] + }, + { + "text": "We nonetheless expect architects to be able to examine our instructions for implementation issues, understand how the instructions will be used in context, and advise on how best to fit the functionality the cryptographers want to the ISA interface.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Introduction > Intended Audience", + "line_range": [ + 53, + 58 + ] + }, + { + "text": "Digital design engineers & micro-architects:: These are the people who will implement the specification inside a core.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Introduction > Intended Audience", + "line_range": [ + 60, + 67 + ] + }, + { + "text": "Again, no cryptography expertise is assumed, but we expect them to interpret the specification and anticipate any hardware implementation issues, e.g., where high-frequency design considerations apply, or where latency/area tradeoffs exist etc.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Introduction > Intended Audience", + "line_range": [ + 60, + 67 + ] + }, + { + "text": "In particular, they should be aware of the literature around efficiently implementing AES and SM4 SBoxes in hardware.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Introduction > Intended Audience", + "line_range": [ + 60, + 67 + ] + }, + { + "text": "Verification engineers:: Responsible for ensuring the correct implementation of the extension in hardware.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Introduction > Intended Audience", + "line_range": [ + 69, + 79 + ] + }, + { + "text": "No cryptography background is assumed.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Introduction > Intended Audience", + "line_range": [ + 69, + 79 + ] + }, + { + "text": "We expect them to identify interesting test cases from the specification.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Introduction > Intended Audience", + "line_range": [ + 69, + 79 + ] + }, + { + "text": "An understanding of their real-world usage will help with this.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Introduction > Intended Audience", + "line_range": [ + 69, + 79 + ] + }, + { + "text": "We do not expect verification engineers in this sense to be experts in entropy source design or certification, since this is a very specialised area.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Introduction > Intended Audience", + "line_range": [ + 69, + 79 + ] + }, + { + "text": "We do expect them however to identify all of the architectural test cases around the entropy source interface.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Introduction > Intended Audience", + "line_range": [ + 69, + 79 + ] + }, + { + "text": "These are by no means the only people concerned with the specification, but they are the ones we considered most while writing it.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Introduction > Intended Audience", + "line_range": [ + 81, + 82 + ] + }, + { + "text": "RISC-V maintains a link:https://github.com/riscv/sail-riscv[formal model] of the ISA specification, implemented in the Sail ISA specification language cite:[sail].", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Introduction > Sail Specifications", + "line_range": [ + 87, + 97 + ] + }, + { + "text": "Note that Sail refers to the specification language itself, and that there is a model of RISC-V, written using Sail.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Introduction > Sail Specifications", + "line_range": [ + 87, + 97 + ] + }, + { + "text": "It is not correct to refer to \"the Sail model\".", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Introduction > Sail Specifications", + "line_range": [ + 87, + 97 + ] + }, + { + "text": "This is ambiguous, given there are many models of different ISAs implemented using Sail.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Introduction > Sail Specifications", + "line_range": [ + 87, + 97 + ] + }, + { + "text": "We refer to the Sail implementation of RISC-V as \"the RISC-V Sail model\".", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Introduction > Sail Specifications", + "line_range": [ + 87, + 97 + ] + }, + { + "text": "The Cryptography extension uses inline Sail code snippets from the actual model to give canonical descriptions of instruction functionality.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Introduction > Sail Specifications", + "line_range": [ + 99, + 109 + ] + }, + { + "text": "Each instruction is accompanied by its expression in Sail, and includes calls to supporting functions which are too verbose to include directly in the specification.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Introduction > Sail Specifications", + "line_range": [ + 99, + 109 + ] + }, + { + "text": "This supporting code is listed in .", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Introduction > Sail Specifications", + "line_range": [ + 99, + 109 + ] + }, + { + "text": "The link:https://alasdair.github.io/manual.html[Sail Manual] is recommended reading in order to best understand the code snippets.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Introduction > Sail Specifications", + "line_range": [ + 99, + 109 + ] + }, + { + "text": "Note that this chapter contains only a subset of the formal model: refer to the formal model GitHub link:https://github.com/riscv/sail-riscv[repository] for the complete model.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Introduction > Sail Specifications", + "line_range": [ + 111, + 114 + ] + }, + { + "text": "In creating this proposal, we tried to adhere to the following policies:", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Introduction > Policies", + "line_range": [ + 119, + 120 + ] + }, + { + "text": "Where there is a choice between: . supporting diverse implementation strategies for an algorithm or . supporting a single implementation style which is more performant / less expensive; the crypto extension will pick the more constrained but performant option.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Introduction > Policies", + "line_range": [ + 122, + 132 + ] + }, + { + "text": "This fits a common pattern in other parts of the RISC-V specification, where recommended (but not required) instruction sequences for performing particular tasks are given as an example, such that both hardware and software implementers can optimise for only a single use-case.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Introduction > Policies", + "line_range": [ + 122, + 132 + ] + }, + { + "text": "The extension will be designed to support existing standardised cryptographic constructs well.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Introduction > Policies", + "line_range": [ + 134, + 143 + ] + }, + { + "text": "It will not try to support proposed standards, or cryptographic constructs which exist only in academia.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Introduction > Policies", + "line_range": [ + 134, + 143 + ] + }, + { + "text": "Cryptographic standards which are settled upon concurrently with or after the RISC-V cryptographic extension standardisation will be dealt with by future additions to, or versions of, the RISC-V cryptographic standard extension.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Introduction > Policies", + "line_range": [ + 134, + 143 + ] + }, + { + "text": "It is anticipated that the NIST Lightweight Cryptography contest and the NIST Post-Quantum Cryptography contest may be dealt with this way, depending on timescales.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Introduction > Policies", + "line_range": [ + 134, + 143 + ] + }, + { + "text": "Historically, there has been some discussion cite:[LSYRR:04] on how newly supported operations in general-purpose computing might enable new bases for cryptographic algorithms.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Introduction > Policies", + "line_range": [ + 145, + 151 + ] + }, + { + "text": "The standard will not try to anticipate new useful low-level operations which may be useful as building blocks for future cryptographic constructs.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Introduction > Policies", + "line_range": [ + 145, + 151 + ] + }, + { + "text": "Regarding side-channel countermeasures: Where relevant, proposed instructions must aim to remove the possibility of any timing side-channels.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Introduction > Policies", + "line_range": [ + 153, + 160 + ] + }, + { + "text": "For side-channels based on power or electro-magnetic (EM) measurements, the extension will not aim to support countermeasures which are implemented above the ISA abstraction layer.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Introduction > Policies", + "line_range": [ + 153, + 160 + ] + }, + { + "text": "Recommendations will be given where relevant on how micro-architectures can implement instructions in a power/EM side-channel resistant way.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Introduction > Policies", + "line_range": [ + 153, + 160 + ] + }, + { + "text": "The group of extensions introduced by the Scalar Cryptography Instruction Set Extension is listed here.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Extensions Overview", + "line_range": [ + 165, + 166 + ] + }, + { + "text": "Detection of individual cryptography extensions uses the unified software-based RISC-V discovery method.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Extensions Overview", + "line_range": [ + 168, + 169 + ] + }, + { + "text": ".A note on extension rationale [NOTE, caption=\"SH\"] Specialist encryption and decryption instructions are separated into different functional groups because some use cases (e.g., Galois/Counter Mode in TLS 1.3) do not require decryption functionality.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Extensions Overview", + "line_range": [ + 171, + 176 + ] + }, + { + "text": "The NIST and ShangMi algorithms suites are separated because their usefulness is heavily dependent on the countries a device is expected to operate in. NIST ciphers are a part of most standardised internet protocols, while ShangMi ciphers are required for use in China.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Extensions Overview", + "line_range": [ + 178, + 182 + ] + }, + { + "text": "This extension contains bit-manipulation instructions that are particularly useful for cryptography, most of which are also in the `Zbb` extension.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Extensions Overview > `Zbkb` - Bitmanip instructions for Cryptography", + "line_range": [ + 187, + 189 + ] + }, + { + "text": "Constant time carry-less multiply for Galois/Counter Mode.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Extensions Overview > `Zbkc` - Carry-less multiply instructions", + "line_range": [ + 194, + 197 + ] + }, + { + "text": "These are separated from the because they have a considerable implementation overhead which cannot be amortised across other instructions.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Extensions Overview > `Zbkc` - Carry-less multiply instructions", + "line_range": [ + 194, + 197 + ] + }, + { + "text": "These instructions are useful for implementing SBoxes in constant time, and potentially with DPA protections.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Extensions Overview > `Zbkx` - Crossbar permutation instructions", + "line_range": [ + 204, + 208 + ] + }, + { + "text": "These are separated from the because they have an implementation overhead which cannot be amortised across other instructions.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Extensions Overview > `Zbkx` - Crossbar permutation instructions", + "line_range": [ + 204, + 208 + ] + }, + { + "text": "Instructions for accelerating the decryption and key-schedule functions of the AES block cipher.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Extensions Overview > `Zknd` - NIST Suite: AES Decryption", + "line_range": [ + 215, + 216 + ] + }, + { + "text": "| |RV32 |RV64 |Mnemonic |Instruction", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Extensions Overview > `Zknd` - NIST Suite: AES Decryption", + "line_range": [ + 218, + 223 + ] + }, + { + "text": "| {check} | | aes32dsi | | {check} | | aes32dsmi | | | {check} | aes64ds | | | {check} | aes64dsm | | | {check} | aes64im | | | {check} | aes64ks1i | | | {check} | aes64ks2 | |", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Extensions Overview > `Zknd` - NIST Suite: AES Decryption", + "line_range": [ + 225, + 232 + ] + }, + { + "text": "NOTE: The and instructions are present in both the and extensions.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Extensions Overview > `Zknd` - NIST Suite: AES Decryption", + "line_range": [ + 234, + 235 + ] + }, + { + "text": "Instructions for accelerating the encryption and key-schedule functions of the AES block cipher.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Extensions Overview > `Zkne` - NIST Suite: AES Encryption", + "line_range": [ + 240, + 241 + ] + }, + { + "text": "| |RV32 |RV64 |Mnemonic |Instruction", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Extensions Overview > `Zkne` - NIST Suite: AES Encryption", + "line_range": [ + 243, + 248 + ] + }, + { + "text": "| {check} | | aes32esi | | {check} | | aes32esmi | | | {check} | aes64es | | | {check} | aes64esm | | | {check} | aes64ks1i | | | {check} | aes64ks2 | |", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Extensions Overview > `Zkne` - NIST Suite: AES Encryption", + "line_range": [ + 250, + 256 + ] + }, + { + "text": "NOTE: The and instructions are present in both the and extensions.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Extensions Overview > `Zkne` - NIST Suite: AES Encryption", + "line_range": [ + 258, + 262 + ] + }, + { + "text": "Instructions for accelerating the SHA2 family of cryptographic hash functions, as specified in cite:[nist:fips:180:4].", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Extensions Overview > `Zknh` - NIST Suite: Hash Function Instructions", + "line_range": [ + 267, + 268 + ] + }, + { + "text": "| |RV32 |RV64 |Mnemonic |Instruction", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Extensions Overview > `Zknh` - NIST Suite: Hash Function Instructions", + "line_range": [ + 270, + 275 + ] + }, + { + "text": "| {check} | {check} | sha256sig0 | | {check} | {check} | sha256sig1 | | {check} | {check} | sha256sum0 | | {check} | {check} | sha256sum1 | | {check} | | sha512sig0h | | {check} | | sha512sig0l | | {check} | | sha512sig1h | | {check} | | sha512sig1l | | {check} | | sha512sum0r | | {check} | | sha512sum1r | | | {check} | sha512sig0 | | | {check} | sha512sig1 | | | {check} | sha512sum0 | | | {check} | sha512sum1 | |", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Extensions Overview > `Zknh` - NIST Suite: Hash Function Instructions", + "line_range": [ + 277, + 291 + ] + }, + { + "text": "Instructions for accelerating the SM4 Block Cipher.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Extensions Overview > `Zksed` - ShangMi Suite: SM4 Block Cipher Instructions", + "line_range": [ + 296, + 299 + ] + }, + { + "text": "Note that unlike AES, this cipher uses the same core operation for encryption and decryption, hence there is only one extension for it.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Extensions Overview > `Zksed` - ShangMi Suite: SM4 Block Cipher Instructions", + "line_range": [ + 296, + 299 + ] + }, + { + "text": "| |RV32 |RV64 |Mnemonic |Instruction", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Extensions Overview > `Zksed` - ShangMi Suite: SM4 Block Cipher Instructions", + "line_range": [ + 301, + 306 + ] + }, + { + "text": "| {check} | {check} | sm4ed | | {check} | {check} | sm4ks | |", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Extensions Overview > `Zksed` - ShangMi Suite: SM4 Block Cipher Instructions", + "line_range": [ + 308, + 310 + ] + }, + { + "text": "Instructions for accelerating the SM3 hash function.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Extensions Overview > `Zksh` - ShangMi Suite: SM3 Hash Function Instructions", + "line_range": [ + 315, + 315 + ] + }, + { + "text": "| |RV32 |RV64 |Mnemonic |Instruction", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Extensions Overview > `Zksh` - ShangMi Suite: SM3 Hash Function Instructions", + "line_range": [ + 317, + 322 + ] + }, + { + "text": "| {check} | {check} | sm3p0 | | {check} | {check} | sm3p1 | |", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Extensions Overview > `Zksh` - ShangMi Suite: SM3 Hash Function Instructions", + "line_range": [ + 324, + 326 + ] + }, + { + "text": "The entropy source extension defines the `seed` CSR at address `0x015`.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Extensions Overview > `Zkr` - Entropy Source Extension", + "line_range": [ + 331, + 334 + ] + }, + { + "text": "This CSR provides up to 16 physical `entropy` bits that can be used to seed cryptographic random bit generators.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Extensions Overview > `Zkr` - Entropy Source Extension", + "line_range": [ + 331, + 334 + ] + }, + { + "text": "See for the normative specification and access control notes. contains design rationale and further recommendations to implementers.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Extensions Overview > `Zkr` - Entropy Source Extension", + "line_range": [ + 336, + 338 + ] + }, + { + "text": "This extension is shorthand for the following set of other extensions:", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Extensions Overview > `Zkn` - NIST Algorithm Suite", + "line_range": [ + 343, + 343 + ] + }, + { + "text": "| |Included Extension |Description", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Extensions Overview > `Zkn` - NIST Algorithm Suite", + "line_range": [ + 345, + 348 + ] + }, + { + "text": "| | Bitmanipulation instructions for cryptography. | | Carry-less multiply instructions. | | Cross-bar Permutation instructions. | | AES encryption instructions. | | AES decryption instructions. | | SHA2 hash function instructions. |", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Extensions Overview > `Zkn` - NIST Algorithm Suite", + "line_range": [ + 350, + 356 + ] + }, + { + "text": "A core which implements `Zkn` must implement all of the above extensions.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Extensions Overview > `Zkn` - NIST Algorithm Suite", + "line_range": [ + 358, + 359 + ] + }, + { + "text": "This extension is shorthand for the following set of other extensions:", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Extensions Overview > `Zks` - ShangMi Algorithm Suite", + "line_range": [ + 364, + 364 + ] + }, + { + "text": "| |Included Extension |Description", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Extensions Overview > `Zks` - ShangMi Algorithm Suite", + "line_range": [ + 366, + 369 + ] + }, + { + "text": "| | Bitmanipulation instructions for cryptography. | | Carry-less multiply instructions. | | Cross-bar Permutation instructions. | | SM4 block cipher instructions. | | SM3 hash function instructions. |", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Extensions Overview > `Zks` - ShangMi Algorithm Suite", + "line_range": [ + 371, + 376 + ] + }, + { + "text": "A core which implements `Zks` must implement all of the above extensions.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Extensions Overview > `Zks` - ShangMi Algorithm Suite", + "line_range": [ + 378, + 379 + ] + }, + { + "text": "This extension is shorthand for the following set of other extensions:", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Extensions Overview > `Zk` - Standard scalar cryptography extension", + "line_range": [ + 384, + 384 + ] + }, + { + "text": "| |Included Extension |Description", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Extensions Overview > `Zk` - Standard scalar cryptography extension", + "line_range": [ + 386, + 389 + ] + }, + { + "text": "| | NIST Algorithm suite extension. | | Entropy Source extension. | | Data independent execution latency extension. |", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Extensions Overview > `Zk` - Standard scalar cryptography extension", + "line_range": [ + 391, + 394 + ] + }, + { + "text": "A core which implements `Zk` must implement all of the above extensions.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Extensions Overview > `Zk` - Standard scalar cryptography extension", + "line_range": [ + 396, + 397 + ] + }, + { + "text": "This extension allows CPU implementers to indicate to cryptographic software developers that a subset of RISC-V instructions are guaranteed to be implemented such that their execution latency is independent of the data values they operate on. A complete description of this extension is found in .", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Extensions Overview > `Zkt` - Data Independent Execution Latency", + "line_range": [ + 401, + 406 + ] + }, + { + "text": "[insns-aes32dsi, reftext=\"AES final round decrypt (RV32)\"]", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions", + "line_range": [ + 413, + 413 + ] + }, + { + "text": "Synopsis:: AES final round decryption instruction for RV32.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes32dsi", + "line_range": [ + 416, + 417 + ] + }, + { + "text": "Mnemonic:: aes32dsi rd, rs1, rs2, bs", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes32dsi", + "line_range": [ + 419, + 420 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 0x33}, {bits: 5, name: 'rd'}, {bits: 3, name: 0x0}, {bits: 5, name: 'rs1'}, {bits: 5, name: 'rs2'}, {bits: 5, name: 0x15}, {bits: 2, name: 'bs'}, ]} ....", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes32dsi", + "line_range": [ + 422, + 435 + ] + }, + { + "text": "Description:: This instruction sources a single byte from `rs2` according to `bs`.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes32dsi", + "line_range": [ + 437, + 442 + ] + }, + { + "text": "To this it applies the inverse AES SBox operation, and XOR's the result with `rs1`.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes32dsi", + "line_range": [ + 437, + 442 + ] + }, + { + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated on.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes32dsi", + "line_range": [ + 437, + 442 + ] + }, + { + "text": "Operation:: [source,sail] -- function clause execute (AES32DSI (bs,rs2,rs1,rd)) = { let shamt : bits( 5) = bs @ 0b000; let si : bits( 8) = (X(rs2)[31..0] >> shamt)[7..0]; let so : bits(32) = 0x000000 @ aessboxinv(si); let result : bits(32) = X(rs1)[31..0] ^ rol32(so, unsigned(shamt)); X(rd) = EXTS(result); RETIRESUCCESS } --", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes32dsi", + "line_range": [ + 444, + 455 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes32dsi", + "line_range": [ + 457, + 462 + ] + }, + { + "text": "| (RV32) | v1.0.0 | Ratified | (RV32) | v1.0.0 | Ratified | (RV32) | v1.0.0 | Ratified |", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes32dsi", + "line_range": [ + 464, + 473 + ] + }, + { + "text": "[insns-aes32dsmi, reftext=\"AES middle round decrypt (RV32)\"]", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes32dsi", + "line_range": [ + 477, + 477 + ] + }, + { + "text": "Synopsis:: AES middle round decryption instruction for RV32.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes32dsmi", + "line_range": [ + 480, + 481 + ] + }, + { + "text": "Mnemonic:: aes32dsmi rd, rs1, rs2, bs", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes32dsmi", + "line_range": [ + 483, + 484 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 0x33}, {bits: 5, name: 'rd'}, {bits: 3, name: 0x0}, {bits: 5, name: 'rs1'}, {bits: 5, name: 'rs2'}, {bits: 5, name: 0x17}, {bits: 2, name: 'bs'}, ]} ....", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes32dsmi", + "line_range": [ + 486, + 499 + ] + }, + { + "text": "Description:: This instruction sources a single byte from `rs2` according to `bs`.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes32dsmi", + "line_range": [ + 501, + 506 + ] + }, + { + "text": "To this it applies the inverse AES SBox operation, and a partial inverse MixColumn, before XOR'ing the result with `rs1`.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes32dsmi", + "line_range": [ + 501, + 506 + ] + }, + { + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated on.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes32dsmi", + "line_range": [ + 501, + 506 + ] + }, + { + "text": "Operation:: [source,sail] -- function clause execute (AES32DSMI (bs,rs2,rs1,rd)) = { let shamt : bits( 5) = bs @ 0b000; let si : bits( 8) = (X(rs2)[31..0] >> shamt)[7..0]; let so : bits( 8) = aessboxinv(si); let mixed : bits(32) = aesmixcolumnbyteinv(so); let result : bits(32) = X(rs1)[31..0] ^ rol32(mixed, unsigned(shamt)); X(rd) = EXTS(result); RETIRESUCCESS } --", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes32dsmi", + "line_range": [ + 508, + 520 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes32dsmi", + "line_range": [ + 522, + 527 + ] + }, + { + "text": "| (RV32) | v1.0.0 | Ratified | (RV32) | v1.0.0 | Ratified | (RV32) | v1.0.0 | Ratified |", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes32dsmi", + "line_range": [ + 529, + 538 + ] + }, + { + "text": "[insns-aes32esi, reftext=\"AES final round encrypt (RV32)\"]", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes32dsmi", + "line_range": [ + 542, + 542 + ] + }, + { + "text": "Synopsis:: AES final round encryption instruction for RV32.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes32esi", + "line_range": [ + 545, + 546 + ] + }, + { + "text": "Mnemonic:: aes32esi rd, rs1, rs2, bs", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes32esi", + "line_range": [ + 548, + 549 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 0x33}, {bits: 5, name: 'rd'}, {bits: 3, name: 0x0}, {bits: 5, name: 'rs1'}, {bits: 5, name: 'rs2'}, {bits: 5, name: 0x11}, {bits: 2, name: 'bs'}, ]} ....", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes32esi", + "line_range": [ + 551, + 564 + ] + }, + { + "text": "Description:: This instruction sources a single byte from `rs2` according to `bs`.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes32esi", + "line_range": [ + 566, + 571 + ] + }, + { + "text": "To this it applies the forward AES SBox operation, before XOR'ing the result with `rs1`.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes32esi", + "line_range": [ + 566, + 571 + ] + }, + { + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated on.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes32esi", + "line_range": [ + 566, + 571 + ] + }, + { + "text": "Operation:: [source,sail] -- function clause execute (AES32ESI (bs,rs2,rs1,rd)) = { let shamt : bits( 5) = bs @ 0b000; let si : bits( 8) = (X(rs2)[31..0] >> shamt)[7..0]; let so : bits(32) = 0x000000 @ aessboxfwd(si); let result : bits(32) = X(rs1)[31..0] ^ rol32(so, unsigned(shamt)); X(rd) = EXTS(result); RETIRESUCCESS } --", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes32esi", + "line_range": [ + 573, + 584 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes32esi", + "line_range": [ + 586, + 591 + ] + }, + { + "text": "| (RV32) | v1.0.0 | Ratified | (RV32) | v1.0.0 | Ratified | (RV32) | v1.0.0 | Ratified |", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes32esi", + "line_range": [ + 593, + 602 + ] + }, + { + "text": "[insns-aes32esmi, reftext=\"AES middle round encrypt (RV32)\"]", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes32esi", + "line_range": [ + 606, + 606 + ] + }, + { + "text": "Synopsis:: AES middle round encryption instruction for RV32.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes32esmi", + "line_range": [ + 609, + 610 + ] + }, + { + "text": "Mnemonic:: aes32esmi rd, rs1, rs2, bs", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes32esmi", + "line_range": [ + 612, + 613 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 0x33}, {bits: 5, name: 'rd'}, {bits: 3, name: 0x0}, {bits: 5, name: 'rs1'}, {bits: 5, name: 'rs2'}, {bits: 5, name: 0x13}, {bits: 2, name: 'bs'}, ]} ....", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes32esmi", + "line_range": [ + 615, + 628 + ] + }, + { + "text": "Description:: This instruction sources a single byte from `rs2` according to `bs`.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes32esmi", + "line_range": [ + 630, + 635 + ] + }, + { + "text": "To this it applies the forward AES SBox operation, and a partial forward MixColumn, before XOR'ing the result with `rs1`.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes32esmi", + "line_range": [ + 630, + 635 + ] + }, + { + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated on.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes32esmi", + "line_range": [ + 630, + 635 + ] + }, + { + "text": "Operation:: [source,sail] -- function clause execute (AES32ESMI (bs,rs2,rs1,rd)) = { let shamt : bits( 5) = bs @ 0b000; let si : bits( 8) = (X(rs2)[31..0] >> shamt)[7..0]; let so : bits( 8) = aessboxfwd(si); let mixed : bits(32) = aesmixcolumnbytefwd(so); let result : bits(32) = X(rs1)[31..0] ^ rol32(mixed, unsigned(shamt)); X(rd) = EXTS(result); RETIRESUCCESS } --", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes32esmi", + "line_range": [ + 637, + 649 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes32esmi", + "line_range": [ + 651, + 656 + ] + }, + { + "text": "| (RV32) | v1.0.0 | Ratified | (RV32) | v1.0.0 | Ratified | (RV32) | v1.0.0 | Ratified |", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes32esmi", + "line_range": [ + 658, + 667 + ] + }, + { + "text": "[insns-aes64ds, reftext=\"AES decrypt final round (RV64)\"]", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes32esmi", + "line_range": [ + 671, + 671 + ] + }, + { + "text": "Synopsis:: AES final round decryption instruction for RV64.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64ds", + "line_range": [ + 674, + 675 + ] + }, + { + "text": "Mnemonic:: aes64ds rd, rs1, rs2", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64ds", + "line_range": [ + 677, + 678 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 0x33}, {bits: 5, name: 'rd'}, {bits: 3, name: 0x0}, {bits: 5, name: 'rs1'}, {bits: 5, name: 'rs2'}, {bits: 5, name: 0x1d}, {bits: 2, name: 0x0}, ]} ....", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64ds", + "line_range": [ + 680, + 693 + ] + }, + { + "text": "Description:: Uses the two 64-bit source registers to represent the entire AES state, and produces half of the next round output, applying the Inverse ShiftRows and SubBytes steps.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64ds", + "line_range": [ + 695, + 700 + ] + }, + { + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated on.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64ds", + "line_range": [ + 695, + 700 + ] + }, + { + "text": ".Note To Software Developers [NOTE,caption=\"SH\"] The following code snippet shows the final round of the AES block decryption. `t0` and `t1` hold the current round state. `t2` and `t3` hold the next round state.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64ds", + "line_range": [ + 702, + 707 + ] + }, + { + "text": "aes64ds t2, t0, t1 aes64ds t3, t1, t0", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64ds", + "line_range": [ + 709, + 710 + ] + }, + { + "text": "Note the reversed register order of the second instruction.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64ds", + "line_range": [ + 712, + 713 + ] + }, + { + "text": "Operation:: [source,sail] -- function clause execute (AES64DS(rs2, rs1, rd)) = { let sr : bits(64) = aesrv64shiftrowsinv(X(rs2)[63..0], X(rs1)[63..0]); let wd : bits(64) = sr[63..0]; X(rd) = aesapplyinvsboxtoeachbyte(wd); RETIRESUCCESS } --", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64ds", + "line_range": [ + 715, + 725 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64ds", + "line_range": [ + 727, + 732 + ] + }, + { + "text": "| (RV64) | v1.0.0 | Ratified | (RV64) | v1.0.0 | Ratified | (RV64) | v1.0.0 | Ratified |", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64ds", + "line_range": [ + 734, + 743 + ] + }, + { + "text": "[insns-aes64dsm, reftext=\"AES decrypt middle round (RV64)\"]", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64ds", + "line_range": [ + 747, + 747 + ] + }, + { + "text": "Synopsis:: AES middle round decryption instruction for RV64.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64dsm", + "line_range": [ + 750, + 751 + ] + }, + { + "text": "Mnemonic:: aes64dsm rd, rs1, rs2", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64dsm", + "line_range": [ + 753, + 754 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 0x33}, {bits: 5, name: 'rd'}, {bits: 3, name: 0x0}, {bits: 5, name: 'rs1'}, {bits: 5, name: 'rs2'}, {bits: 5, name: 0x1f}, {bits: 2, name: 0x0}, ]} ....", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64dsm", + "line_range": [ + 756, + 769 + ] + }, + { + "text": "Description:: Uses the two 64-bit source registers to represent the entire AES state, and produces half of the next round output, applying the Inverse ShiftRows, SubBytes and MixColumns steps.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64dsm", + "line_range": [ + 771, + 776 + ] + }, + { + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated on.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64dsm", + "line_range": [ + 771, + 776 + ] + }, + { + "text": ".Note To Software Developers [NOTE,caption=\"SH\"] The following code snippet shows one middle round of the AES block decryption. `t0` and `t1` hold the current round state. `t2` and `t3` hold the next round state.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64dsm", + "line_range": [ + 778, + 783 + ] + }, + { + "text": "aes64dsm t2, t0, t1 aes64dsm t3, t1, t0", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64dsm", + "line_range": [ + 785, + 786 + ] + }, + { + "text": "Note the reversed register order of the second instruction.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64dsm", + "line_range": [ + 788, + 789 + ] + }, + { + "text": "Operation:: [source,sail] -- function clause execute (AES64DSM(rs2, rs1, rd)) = { let sr : bits(64) = aesrv64shiftrowsinv(X(rs2)[63..0], X(rs1)[63..0]); let wd : bits(64) = sr[63..0]; let sb : bits(64) = aesapplyinvsboxtoeachbyte(wd); X(rd) = aesmixcolumninv(sb[63..32]) @ aesmixcolumninv(sb[31..0]); RETIRESUCCESS } --", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64dsm", + "line_range": [ + 791, + 802 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64dsm", + "line_range": [ + 804, + 809 + ] + }, + { + "text": "| (RV64) | v1.0.0 | Ratified | (RV64) | v1.0.0 | Ratified | (RV64) | v1.0.0 | Ratified |", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64dsm", + "line_range": [ + 811, + 820 + ] + }, + { + "text": "[insns-aes64es, reftext=\"AES encrypt final round instruction (RV64)\"]", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64dsm", + "line_range": [ + 824, + 824 + ] + }, + { + "text": "Synopsis:: AES final round encryption instruction for RV64.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64es", + "line_range": [ + 827, + 828 + ] + }, + { + "text": "Mnemonic:: aes64es rd, rs1, rs2", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64es", + "line_range": [ + 830, + 831 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 0x33}, {bits: 5, name: 'rd'}, {bits: 3, name: 0x0}, {bits: 5, name: 'rs1'}, {bits: 5, name: 'rs2'}, {bits: 5, name: 0x19}, {bits: 2, name: 0x0}, ]} ....", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64es", + "line_range": [ + 833, + 846 + ] + }, + { + "text": "Description:: Uses the two 64-bit source registers to represent the entire AES state, and produces half of the next round output, applying the ShiftRows and SubBytes steps.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64es", + "line_range": [ + 848, + 853 + ] + }, + { + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated on.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64es", + "line_range": [ + 848, + 853 + ] + }, + { + "text": ".Note To Software Developers [NOTE,caption=\"SH\"] The following code snippet shows the final round of the AES block encryption. `t0` and `t1` hold the current round state. `t2` and `t3` hold the next round state.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64es", + "line_range": [ + 855, + 860 + ] + }, + { + "text": "aes64es t2, t0, t1 aes64es t3, t1, t0", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64es", + "line_range": [ + 862, + 863 + ] + }, + { + "text": "Note the reversed register order of the second instruction.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64es", + "line_range": [ + 865, + 866 + ] + }, + { + "text": "Operation:: [source,sail] -- function clause execute (AES64ES(rs2, rs1, rd)) = { let sr : bits(64) = aesrv64shiftrowsfwd(X(rs2)[63..0], X(rs1)[63..0]); let wd : bits(64) = sr[63..0]; X(rd) = aesapplyfwdsboxtoeachbyte(wd); RETIRESUCCESS } --", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64es", + "line_range": [ + 868, + 878 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64es", + "line_range": [ + 880, + 885 + ] + }, + { + "text": "| (RV64) | v1.0.0 | Ratified | (RV64) | v1.0.0 | Ratified | (RV64) | v1.0.0 | Ratified |", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64es", + "line_range": [ + 887, + 896 + ] + }, + { + "text": "[insns-aes64esm, reftext=\"AES encrypt middle round instruction (RV64)\"]", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64es", + "line_range": [ + 900, + 900 + ] + }, + { + "text": "Synopsis:: AES middle round encryption instruction for RV64.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64esm", + "line_range": [ + 903, + 904 + ] + }, + { + "text": "Mnemonic:: aes64esm rd, rs1, rs2", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64esm", + "line_range": [ + 906, + 907 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 0x33}, {bits: 5, name: 'rd'}, {bits: 3, name: 0x0}, {bits: 5, name: 'rs1'}, {bits: 5, name: 'rs2'}, {bits: 5, name: 0x1b}, {bits: 2, name: 0x0}, ]} ....", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64esm", + "line_range": [ + 909, + 922 + ] + }, + { + "text": "Description:: Uses the two 64-bit source registers to represent the entire AES state, and produces half of the next round output, applying the ShiftRows, SubBytes and MixColumns steps.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64esm", + "line_range": [ + 924, + 929 + ] + }, + { + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated on.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64esm", + "line_range": [ + 924, + 929 + ] + }, + { + "text": ".Note To Software Developers [NOTE,caption=\"SH\"] The following code snippet shows one middle round of the AES block encryption. `t0` and `t1` hold the current round state. `t2` and `t3` hold the next round state.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64esm", + "line_range": [ + 931, + 936 + ] + }, + { + "text": "aes64esm t2, t0, t1 aes64esm t3, t1, t0", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64esm", + "line_range": [ + 938, + 939 + ] + }, + { + "text": "Note the reversed register order of the second instruction.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64esm", + "line_range": [ + 941, + 942 + ] + }, + { + "text": "Operation:: [source,sail] -- function clause execute (AES64ESM(rs2, rs1, rd)) = { let sr : bits(64) = aesrv64shiftrowsfwd(X(rs2)[63..0], X(rs1)[63..0]); let wd : bits(64) = sr[63..0]; let sb : bits(64) = aesapplyfwdsboxtoeachbyte(wd); X(rd) = aesmixcolumnfwd(sb[63..32]) @ aesmixcolumnfwd(sb[31..0]); RETIRESUCCESS } --", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64esm", + "line_range": [ + 944, + 955 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64esm", + "line_range": [ + 957, + 962 + ] + }, + { + "text": "| (RV64) | v1.0.0 | Ratified | (RV64) | v1.0.0 | Ratified | (RV64) | v1.0.0 | Ratified |", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64esm", + "line_range": [ + 964, + 973 + ] + }, + { + "text": "[insns-aes64im, reftext=\"AES Decrypt KeySchedule MixColumns (RV64)\"]", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64esm", + "line_range": [ + 977, + 977 + ] + }, + { + "text": "Synopsis:: This instruction accelerates the inverse MixColumns step of the AES Block Cipher, and is used to aid creation of the decryption KeySchedule.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64im", + "line_range": [ + 980, + 982 + ] + }, + { + "text": "Mnemonic:: aes64im rd, rs1", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64im", + "line_range": [ + 984, + 985 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 0x13}, {bits: 5, name: 'rd'}, {bits: 3, name: 0x1}, {bits: 5, name: 'rs1'}, {bits: 5, name: 0x0}, {bits: 5, name: 0x18}, {bits: 2, name: 0x0}, ]} ....", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64im", + "line_range": [ + 987, + 1000 + ] + }, + { + "text": "Description:: The instruction applies the inverse MixColumns transformation to two columns of the state array, packed into a single 64-bit register.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64im", + "line_range": [ + 1002, + 1010 + ] + }, + { + "text": "It is used to create the inverse cipher KeySchedule, according to the equivalent inverse cipher construction in cite:[nist:fips:197] (Page 23, Section 5.3.5).", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64im", + "line_range": [ + 1002, + 1010 + ] + }, + { + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated on.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64im", + "line_range": [ + 1002, + 1010 + ] + }, + { + "text": "Operation:: [source,sail] -- function clause execute (AES64IM(rs1, rd)) = { let w0 : bits(32) = aesmixcolumninv(X(rs1)[31.. 0]); let w1 : bits(32) = aesmixcolumninv(X(rs1)[63..32]); X(rd) = w1 @ w0; RETIRESUCCESS } --", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64im", + "line_range": [ + 1012, + 1022 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64im", + "line_range": [ + 1024, + 1029 + ] + }, + { + "text": "| (RV64) | v1.0.0 | Ratified | (RV64) | v1.0.0 | Ratified | (RV64) | v1.0.0 | Ratified |", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64im", + "line_range": [ + 1031, + 1040 + ] + }, + { + "text": "[insns-aes64ks1i, reftext=\"AES Key Schedule Instruction 1 (RV64)\"]", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64im", + "line_range": [ + 1044, + 1044 + ] + }, + { + "text": "Synopsis:: This instruction implements part of the KeySchedule operation for the AES Block cipher involving the SBox operation.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64ks1i", + "line_range": [ + 1047, + 1049 + ] + }, + { + "text": "Mnemonic:: aes64ks1i rd, rs1, rnum", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64ks1i", + "line_range": [ + 1051, + 1052 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 0x13}, {bits: 5, name: 'rd'}, {bits: 3, name: 0x1}, {bits: 5, name: 'rs1'}, {bits: 4, name: 'rnum'}, {bits: 1, name: 0x1}, {bits: 5, name: 0x18}, {bits: 2, name: 0}, ]} ....", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64ks1i", + "line_range": [ + 1054, + 1068 + ] + }, + { + "text": "Description:: This instruction implements the rotation, SubBytes and Round Constant addition steps of the AES block cipher Key Schedule.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64ks1i", + "line_range": [ + 1070, + 1076 + ] + }, + { + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated on.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64ks1i", + "line_range": [ + 1070, + 1076 + ] + }, + { + "text": "Note that `rnum` must be in the range `0x0..0xA`.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64ks1i", + "line_range": [ + 1070, + 1076 + ] + }, + { + "text": "The values `0xB..0xF` are reserved.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64ks1i", + "line_range": [ + 1070, + 1076 + ] + }, + { + "text": "Operation:: [source,sail] -- function clause execute (AES64KS1I(rnum, rs1, rd)) = { if(unsigned(rnum) > 10) then { handleillegal(); RETIRESUCCESS } else { let tmp1 : bits(32) = X(rs1)[63..32]; let rc : bits(32) = aesdecodercon(rnum); let tmp2 : bits(32) = if (rnum 0xA) then tmp1 else ror32(tmp1, 8); let tmp3 : bits(32) = aessubwordfwd(tmp2); let result : bits(64) = (tmp3 ^ rc) @ (tmp3 ^ rc); X(rd) = EXTZ(result); RETIRESUCCESS } } --", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64ks1i", + "line_range": [ + 1078, + 1095 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64ks1i", + "line_range": [ + 1097, + 1102 + ] + }, + { + "text": "| (RV64) | v1.0.0 | Ratified | (RV64) | v1.0.0 | Ratified | (RV64) | v1.0.0 | Ratified | (RV64) | v1.0.0 | Ratified |", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64ks1i", + "line_range": [ + 1104, + 1116 + ] + }, + { + "text": "[insns-aes64ks2, reftext=\"AES Key Schedule Instruction 2 (RV64)\"]", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64ks1i", + "line_range": [ + 1120, + 1120 + ] + }, + { + "text": "Synopsis:: This instruction implements part of the KeySchedule operation for the AES Block cipher.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64ks2", + "line_range": [ + 1123, + 1125 + ] + }, + { + "text": "Mnemonic:: aes64ks2 rd, rs1, rs2", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64ks2", + "line_range": [ + 1127, + 1128 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 0x33}, {bits: 5, name: 'rd'}, {bits: 3, name: 0x0}, {bits: 5, name: 'rs1'}, {bits: 5, name: 'rs2'}, {bits: 5, name: 0x1f}, {bits: 2, name: 0x1}, ]} ....", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64ks2", + "line_range": [ + 1130, + 1143 + ] + }, + { + "text": "Description:: This instruction implements the additional XOR'ing of key words as part of the AES block cipher Key Schedule.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64ks2", + "line_range": [ + 1145, + 1149 + ] + }, + { + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated on.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64ks2", + "line_range": [ + 1145, + 1149 + ] + }, + { + "text": "Operation:: [source,sail] -- function clause execute (AES64KS2(rs2, rs1, rd)) = { let w0 : bits(32) = X(rs1)[63..32] ^ X(rs2)[31..0]; let w1 : bits(32) = X(rs1)[63..32] ^ X(rs2)[31..0] ^ X(rs2)[63..32]; X(rd) = w1 @ w0; RETIRESUCCESS } --", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64ks2", + "line_range": [ + 1151, + 1161 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64ks2", + "line_range": [ + 1163, + 1168 + ] + }, + { + "text": "| (RV64) | v1.0.0 | Ratified | (RV64) | v1.0.0 | Ratified | (RV64) | v1.0.0 | Ratified | (RV64) | v1.0.0 | Ratified |", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64ks2", + "line_range": [ + 1170, + 1182 + ] + }, + { + "text": "[insns-andn-sc,reftext=\"AND with inverted operand\"]", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > aes64ks2", + "line_range": [ + 1186, + 1186 + ] + }, + { + "text": "Synopsis:: AND with inverted operand", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > andn", + "line_range": [ + 1189, + 1190 + ] + }, + { + "text": "Mnemonic:: andn rd, rs1, rs2", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > andn", + "line_range": [ + 1192, + 1193 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0x33, attr: ['OP'] }, { bits: 5, name: 'rd' }, { bits: 3, name: 0x7, attr: ['ANDN']}, { bits: 5, name: 'rs1' }, { bits: 5, name: 'rs2' }, { bits: 7, name: 0x20, attr: ['ANDN'] }, ]} ....", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > andn", + "line_range": [ + 1195, + 1206 + ] + }, + { + "text": "Description:: This instruction performs the bitwise logical AND operation between rs1 and the bitwise inversion of rs2.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > andn", + "line_range": [ + 1208, + 1209 + ] + }, + { + "text": "Operation:: [source,sail] -- X(rd) = X(rs1) & ~X(rs2); --", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > andn", + "line_range": [ + 1211, + 1215 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > andn", + "line_range": [ + 1217, + 1222 + ] + }, + { + "text": "|Zbb (ext:zbb[]) |1.0.0 |Ratified", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > andn", + "line_range": [ + 1224, + 1226 + ] + }, + { + "text": "|Zbkb () |v1.0.0-rc4 |Ratified |", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > andn", + "line_range": [ + 1228, + 1231 + ] + }, + { + "text": "[insns-brev8-sc,reftext=\"Reverse bits in bytes\"]", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > andn", + "line_range": [ + 1235, + 1235 + ] + }, + { + "text": "Synopsis:: Reverse the bits in each byte of a source register.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > brev8", + "line_range": [ + 1238, + 1239 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0x13, attr: ['OP-IMM'] }, { bits: 5, name: 'rd' }, { bits: 3, name: 0x5 }, { bits: 5, name: 'rs' }, { bits: 12, name: 0x687 } ]} ....", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > brev8", + "line_range": [ + 1244, + 1254 + ] + }, + { + "text": "Description:: This instruction reverses the order of the bits in every byte of a register.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > brev8", + "line_range": [ + 1256, + 1257 + ] + }, + { + "text": "Operation:: [source,sail] -- result : xlenbits = EXTZ(0b0); foreach (i from 0 to sizeof(xlen) by 8) { result[i+7..i] = reversebitsinbyte(X(rs1)[i+7..i]); }; X(rd) = result; --", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > brev8", + "line_range": [ + 1259, + 1267 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > brev8", + "line_range": [ + 1269, + 1274 + ] + }, + { + "text": "|Zbkb () |v1.0.0-rc4 |Ratified |", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > brev8", + "line_range": [ + 1276, + 1279 + ] + }, + { + "text": "[insns-clmul-sc,reftext=\"Carry-less multiply (low-part)\"]", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > brev8", + "line_range": [ + 1283, + 1283 + ] + }, + { + "text": "Synopsis:: Carry-less multiply (low-part)", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > clmul", + "line_range": [ + 1286, + 1287 + ] + }, + { + "text": "Mnemonic:: clmul rd, rs1, rs2", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > clmul", + "line_range": [ + 1289, + 1290 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0x33, attr: ['OP'] }, { bits: 5, name: 'rd' }, { bits: 3, name: 0x1, attr: ['CLMUL'] }, { bits: 5, name: 'rs1' }, { bits: 5, name: 'rs2' }, { bits: 7, name: 0x5, attr: ['MINMAX/CLMUL'] }, ]} ....", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > clmul", + "line_range": [ + 1292, + 1303 + ] + }, + { + "text": "Description:: clmul produces the lower half of the 2·XLEN carry-less product.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > clmul", + "line_range": [ + 1305, + 1306 + ] + }, + { + "text": "Operation:: [source,sail] -- let rs1val = X(rs1); let rs2val = X(rs2); let output : xlenbits = 0;", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > clmul", + "line_range": [ + 1308, + 1313 + ] + }, + { + "text": "foreach (i from 0 to (xlen - 1) by 1) { output = if ((rs2val >> i) & 1) then output ^ (rs1val << i); else output; }", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > clmul", + "line_range": [ + 1315, + 1319 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > clmul", + "line_range": [ + 1324, + 1329 + ] + }, + { + "text": "|Zbkc () |v1.0.0-rc4 |Ratified |", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > clmul", + "line_range": [ + 1335, + 1338 + ] + }, + { + "text": "[insns-clmulh-sc,reftext=\"Carry-less multiply (high-part)\"]", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > clmul", + "line_range": [ + 1342, + 1342 + ] + }, + { + "text": "Synopsis:: Carry-less multiply (high-part)", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > clmulh", + "line_range": [ + 1345, + 1346 + ] + }, + { + "text": "Mnemonic:: clmulh rd, rs1, rs2", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > clmulh", + "line_range": [ + 1348, + 1349 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0x33, attr: ['OP'] }, { bits: 5, name: 'rd' }, { bits: 3, name: 0x3, attr: ['CLMULH'] }, { bits: 5, name: 'rs1' }, { bits: 5, name: 'rs2' }, { bits: 7, name: 0x5, attr: ['MINMAX/CLMUL'] }, ]} ....", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > clmulh", + "line_range": [ + 1351, + 1362 + ] + }, + { + "text": "Description:: clmulh produces the upper half of the 2·XLEN carry-less product.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > clmulh", + "line_range": [ + 1364, + 1365 + ] + }, + { + "text": "Operation:: [source,sail] -- let rs1val = X(rs1); let rs2val = X(rs2); let output : xlenbits = 0;", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > clmulh", + "line_range": [ + 1367, + 1372 + ] + }, + { + "text": "foreach (i from 1 to xlen by 1) { output = if ((rs2val >> i) & 1) then output ^ (rs1val >> (xlen - i)); else output; }", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > clmulh", + "line_range": [ + 1374, + 1378 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > clmulh", + "line_range": [ + 1383, + 1388 + ] + }, + { + "text": "|Zbkc () |v1.0.0-rc4 |Ratified |", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > clmulh", + "line_range": [ + 1394, + 1397 + ] + }, + { + "text": "[insns-orn-sc,reftext=\"OR with inverted operand\"]", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > clmulh", + "line_range": [ + 1401, + 1401 + ] + }, + { + "text": "Synopsis:: OR with inverted operand", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > orn", + "line_range": [ + 1404, + 1405 + ] + }, + { + "text": "Mnemonic:: orn rd, rs1, rs2", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > orn", + "line_range": [ + 1407, + 1408 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0x33, attr: ['OP'] }, { bits: 5, name: 'rd' }, { bits: 3, name: 0x6, attr: ['ORN']}, { bits: 5, name: 'rs1' }, { bits: 5, name: 'rs2' }, { bits: 7, name: 0x20, attr: ['ORN'] }, ]} ....", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > orn", + "line_range": [ + 1410, + 1421 + ] + }, + { + "text": "Description:: This instruction performs the bitwise logical OR operation between rs1 and the bitwise inversion of rs2.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > orn", + "line_range": [ + 1423, + 1424 + ] + }, + { + "text": "Operation:: [source,sail] -- X(rd) = X(rs1) | ~X(rs2); --", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > orn", + "line_range": [ + 1426, + 1430 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > orn", + "line_range": [ + 1432, + 1437 + ] + }, + { + "text": "|Zbb (ext:zbb[]) |v1.0.0 |Ratified", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > orn", + "line_range": [ + 1439, + 1441 + ] + }, + { + "text": "|Zbkb () |v1.0.0-rc4 |Ratified |", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > orn", + "line_range": [ + 1443, + 1446 + ] + }, + { + "text": "[insns-pack-sc,reftext=\"Pack low halves of registers\"]", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > orn", + "line_range": [ + 1450, + 1450 + ] + }, + { + "text": "Synopsis:: Pack the low halves of rs1 and rs2 into rd.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > pack", + "line_range": [ + 1453, + 1454 + ] + }, + { + "text": "Mnemonic:: pack rd, rs1, rs2", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > pack", + "line_range": [ + 1456, + 1457 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 0x33, attr: ['OP'] }, {bits: 5, name: 'rd'}, {bits: 3, name: 0x4, attr:['PACK']}, {bits: 5, name: 'rs1'}, {bits: 5, name: 'rs2'}, {bits: 7, name: 0x4, attr:['PACK']}, ]} ....", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > pack", + "line_range": [ + 1459, + 1470 + ] + }, + { + "text": "Description:: The pack instruction packs the XLEN/2-bit lower halves of rs1 and rs2 into rd, with rs1 in the lower half and rs2 in the upper half.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > pack", + "line_range": [ + 1472, + 1474 + ] + }, + { + "text": "Operation:: [source,sail] -- let lohalf : bits(xlen/2) = X(rs1)[xlen/2-1..0]; let hihalf : bits(xlen/2) = X(rs2)[xlen/2-1..0]; X(rd) = EXTZ(hihalf @ lohalf); --", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > pack", + "line_range": [ + 1476, + 1482 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > pack", + "line_range": [ + 1484, + 1489 + ] + }, + { + "text": "|Zbkb () |v1.0.0-rc4 |Ratified |", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > pack", + "line_range": [ + 1491, + 1494 + ] + }, + { + "text": "[insns-packh-sc,reftext=\"Pack low bytes of registers\"]", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > pack", + "line_range": [ + 1498, + 1498 + ] + }, + { + "text": "Synopsis:: Pack the low bytes of rs1 and rs2 into rd.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > packh", + "line_range": [ + 1501, + 1502 + ] + }, + { + "text": "Mnemonic:: packh rd, rs1, rs2", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > packh", + "line_range": [ + 1504, + 1505 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 0x33, attr: ['OP'] }, {bits: 5, name: 'rd'}, {bits: 3, name: 0x7, attr: ['PACKH']}, {bits: 5, name: 'rs1'}, {bits: 5, name: 'rs2'}, {bits: 7, name: 0x4, attr: ['PACKH']}, ]} ....", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > packh", + "line_range": [ + 1507, + 1518 + ] + }, + { + "text": "Description:: And the packh instruction packs the least-significant bytes of rs1 and rs2 into the 16 least-significant bits of rd, zero extending the rest of rd.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > packh", + "line_range": [ + 1520, + 1523 + ] + }, + { + "text": "Operation:: [source,sail] -- let lohalf : bits(8) = X(rs1)[7..0]; let hihalf : bits(8) = X(rs2)[7..0]; X(rd) = EXTZ(hihalf @ lohalf); --", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > packh", + "line_range": [ + 1525, + 1531 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > packh", + "line_range": [ + 1533, + 1538 + ] + }, + { + "text": "|Zbkb () |v1.0.0-rc4 |Ratified |", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > packh", + "line_range": [ + 1540, + 1543 + ] + }, + { + "text": "[insns-packw-sc,reftext=\"Pack low 16-bits of registers (RV64)\"]", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > packh", + "line_range": [ + 1547, + 1547 + ] + }, + { + "text": "Synopsis:: Pack the low 16-bits of rs1 and rs2 into rd on RV64.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > packw", + "line_range": [ + 1550, + 1551 + ] + }, + { + "text": "Mnemonic:: packw rd, rs1, rs2", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > packw", + "line_range": [ + 1553, + 1554 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ {bits: 2, name: 0x3}, {bits: 5, name: 0xe}, {bits: 5, name: 'rd'}, {bits: 3, name: 0x4}, {bits: 5, name: 'rs1'}, {bits: 5, name: 'rs2'}, {bits: 7, name: 0x4}, ]} ....", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > packw", + "line_range": [ + 1556, + 1568 + ] + }, + { + "text": "Description:: This instruction packs the low 16 bits of rs1 and rs2 into the 32 least-significant bits of rd, sign extending the 32-bit result to the rest of rd.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > packw", + "line_range": [ + 1570, + 1574 + ] + }, + { + "text": "This instruction only exists on RV64 based systems.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > packw", + "line_range": [ + 1570, + 1574 + ] + }, + { + "text": "Operation:: [source,sail] -- let lohalf : bits(16) = X(rs1)[15..0]; let hihalf : bits(16) = X(rs2)[15..0]; X(rd) = EXTS(hihalf @ lohalf); --", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > packw", + "line_range": [ + 1576, + 1582 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > packw", + "line_range": [ + 1584, + 1589 + ] + }, + { + "text": "|Zbkb () |v1.0.0-rc4 |Ratified |", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > packw", + "line_range": [ + 1591, + 1594 + ] + }, + { + "text": "[insns-rev8-sc,reftext=\"Byte-reverse register\"]", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > packw", + "line_range": [ + 1598, + 1598 + ] + }, + { + "text": "Synopsis:: Byte-reverse register", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > rev8", + "line_range": [ + 1601, + 1602 + ] + }, + { + "text": "Encoding (RV32):: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0x13, attr: ['OP-IMM'] }, { bits: 5, name: 'rd' }, { bits: 3, name: 0x5 }, { bits: 5, name: 'rs' }, { bits: 12, name: 0x698 } ]} ....", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > rev8", + "line_range": [ + 1607, + 1617 + ] + }, + { + "text": "Encoding (RV64):: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0x13, attr: ['OP-IMM'] }, { bits: 5, name: 'rd' }, { bits: 3, name: 0x5 }, { bits: 5, name: 'rs' }, { bits: 12, name: 0x6b8 } ]} ....", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > rev8", + "line_range": [ + 1619, + 1629 + ] + }, + { + "text": "Description:: This instruction reverses the order of the bytes in rs.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > rev8", + "line_range": [ + 1631, + 1632 + ] + }, + { + "text": "Operation:: [source,sail] -- let input = X(rs); let output : xlenbits = 0; let j = xlen - 1;", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > rev8", + "line_range": [ + 1634, + 1639 + ] + }, + { + "text": "foreach (i from 0 to (xlen - 8) by 8) { output[i..(i + 7)] = input[(j - 7)..j]; j = j - 8; }", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > rev8", + "line_range": [ + 1641, + 1644 + ] + }, + { + "text": ".Note [NOTE, caption=\"A\" ] The *rev8* mnemonic corresponds to different instruction encodings in RV32 and RV64.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > rev8", + "line_range": [ + 1649, + 1653 + ] + }, + { + "text": ".Software Hint [NOTE, caption=\"SH\" ] The byte-reverse operation is only available for the full register width.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > rev8", + "line_range": [ + 1655, + 1662 + ] + }, + { + "text": "To emulate word-sized and halfword-sized byte-reversal, perform a `rev8 rd,rs` followed by a `srai rd,rd,K`, where K is XLEN-32 and XLEN-16, respectively.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > rev8", + "line_range": [ + 1655, + 1662 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > rev8", + "line_range": [ + 1664, + 1669 + ] + }, + { + "text": "|Zbb (ext:zbb[]) |v1.0.0 |Ratified", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > rev8", + "line_range": [ + 1671, + 1673 + ] + }, + { + "text": "|Zbkb () |v1.0.0-rc4 |Ratified |", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > rev8", + "line_range": [ + 1675, + 1678 + ] + }, + { + "text": "[insns-rol-sc,reftext=\"Rotate left (Register)\"]", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > rev8", + "line_range": [ + 1682, + 1682 + ] + }, + { + "text": "Synopsis:: Rotate Left (Register)", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > rol", + "line_range": [ + 1685, + 1686 + ] + }, + { + "text": "Mnemonic:: rol rd, rs1, rs2", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > rol", + "line_range": [ + 1688, + 1689 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0x33, attr: ['OP'] }, { bits: 5, name: 'rd' }, { bits: 3, name: 0x1, attr: ['ROL']}, { bits: 5, name: 'rs1' }, { bits: 5, name: 'rs2' }, { bits: 7, name: 0x30, attr: ['ROL'] }, ]} ....", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > rol", + "line_range": [ + 1691, + 1702 + ] + }, + { + "text": "Description:: This instruction performs a rotate left of rs1 by the amount in least-significant log2(XLEN) bits of rs2.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > rol", + "line_range": [ + 1704, + 1705 + ] + }, + { + "text": "Operation:: [source,sail] -- let shamt = if xlen 32 then X(rs2)[4..0] else X(rs2)[5..0]; let result = (X(rs1) (xlen - shamt));", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > rol", + "line_range": [ + 1707, + 1713 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > rol", + "line_range": [ + 1718, + 1723 + ] + }, + { + "text": "|Zbb (ext:zbb[]) |v1.0.0 |Ratified", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > rol", + "line_range": [ + 1725, + 1727 + ] + }, + { + "text": "|Zbkb () |v1.0.0-rc4 |Ratified |", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > rol", + "line_range": [ + 1729, + 1732 + ] + }, + { + "text": "[insns-rolw-sc,reftext=\"Rotate Left Word (Register)\"]", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > rol", + "line_range": [ + 1736, + 1736 + ] + }, + { + "text": "Synopsis:: Rotate Left Word (Register)", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > rolw", + "line_range": [ + 1739, + 1740 + ] + }, + { + "text": "Mnemonic:: rolw rd, rs1, rs2", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > rolw", + "line_range": [ + 1742, + 1743 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0x3b, attr: ['OP-32'] }, { bits: 5, name: 'rd' }, { bits: 3, name: 0x1, attr: ['ROLW']}, { bits: 5, name: 'rs1' }, { bits: 5, name: 'rs2' }, { bits: 7, name: 0x30, attr: ['ROLW'] }, ]} ....", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > rolw", + "line_range": [ + 1745, + 1756 + ] + }, + { + "text": "Description:: This instruction performs a rotate left on the least-significant word of rs1 by the amount in least-significant 5 bits of rs2.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > rolw", + "line_range": [ + 1758, + 1760 + ] + }, + { + "text": "The resulting word value is sign-extended by copying bit 31 to all of the more-significant bits.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > rolw", + "line_range": [ + 1758, + 1760 + ] + }, + { + "text": "Operation:: [source,sail] -- let rs1 = EXTZ(X(rs1)[31..0]) let shamt = X(rs2)[4..0]; let result = (rs1 (32 - shamt)); X(rd) = EXTS(result[31..0]); --", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > rolw", + "line_range": [ + 1762, + 1769 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > rolw", + "line_range": [ + 1771, + 1776 + ] + }, + { + "text": "|Zbb (ext:zbb[]) |v1.0.0 |Ratified", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > rolw", + "line_range": [ + 1778, + 1780 + ] + }, + { + "text": "|Zbkb () |v1.0.0-rc4 |Ratified |", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > rolw", + "line_range": [ + 1782, + 1785 + ] + }, + { + "text": "[insns-ror-sc, reftext=\"Rotate right (Register)\"]", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > rolw", + "line_range": [ + 1789, + 1789 + ] + }, + { + "text": "Mnemonic:: ror rd, rs1, rs2", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > ror", + "line_range": [ + 1795, + 1796 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0x33, attr: ['OP'] }, { bits: 5, name: 'rd' }, { bits: 3, name: 0x5, attr: ['ROR']}, { bits: 5, name: 'rs1' }, { bits: 5, name: 'rs2' }, { bits: 7, name: 0x30, attr: ['ROR'] }, ]} ....", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > ror", + "line_range": [ + 1798, + 1809 + ] + }, + { + "text": "Description:: This instruction performs a rotate right of rs1 by the amount in least-significant log2(XLEN) bits of rs2.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > ror", + "line_range": [ + 1811, + 1812 + ] + }, + { + "text": "Operation:: [source,sail] -- let shamt = if xlen 32 then X(rs2)[4..0] else X(rs2)[5..0]; let result = (X(rs1) >> shamt) | (X(rs1) << (xlen - shamt));", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > ror", + "line_range": [ + 1814, + 1820 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > ror", + "line_range": [ + 1825, + 1830 + ] + }, + { + "text": "|Zbb (ext:zbb[]) |v1.0.0 |Ratified", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > ror", + "line_range": [ + 1832, + 1834 + ] + }, + { + "text": "|Zbkb () |v1.0.0-rc4 |Ratified |", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > ror", + "line_range": [ + 1836, + 1839 + ] + }, + { + "text": "[insns-rori-sc,reftext=\"Rotate right (Immediate)\"]", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > ror", + "line_range": [ + 1843, + 1843 + ] + }, + { + "text": "Synopsis:: Rotate Right (Immediate)", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > rori", + "line_range": [ + 1846, + 1847 + ] + }, + { + "text": "Mnemonic:: rori rd, rs1, shamt", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > rori", + "line_range": [ + 1849, + 1850 + ] + }, + { + "text": "Encoding (RV32):: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0x13, attr: ['OP-IMM'] }, { bits: 5, name: 'rd' }, { bits: 3, name: 0x5, attr: ['RORI']}, { bits: 5, name: 'rs1' }, { bits: 5, name: 'shamt' }, { bits: 7, name: 0x30, attr: ['RORI'] }, ]} ....", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > rori", + "line_range": [ + 1852, + 1863 + ] + }, + { + "text": "Encoding (RV64):: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0x13, attr: ['OP-IMM'] }, { bits: 5, name: 'rd' }, { bits: 3, name: 0x5, attr: ['RORI']}, { bits: 5, name: 'rs1' }, { bits: 6, name: 'shamt' }, { bits: 6, name: 0x18, attr: ['RORI'] }, ]} ....", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > rori", + "line_range": [ + 1865, + 1876 + ] + }, + { + "text": "Description:: This instruction performs a rotate right of rs1 by the amount in the least-significant log2(XLEN) bits of shamt.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > rori", + "line_range": [ + 1878, + 1880 + ] + }, + { + "text": "For RV32, the encodings corresponding to shamt[5]=1 are reserved.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > rori", + "line_range": [ + 1878, + 1880 + ] + }, + { + "text": "Operation:: [source,sail] -- let shamt = if xlen 32 then shamt[4..0] else shamt[5..0]; let result = (X(rs1) >> shamt) | (X(rs1) << (xlen - shamt));", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > rori", + "line_range": [ + 1882, + 1888 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > rori", + "line_range": [ + 1893, + 1898 + ] + }, + { + "text": "|Zbb (ext:zbb[]) |v1.0.0 |Ratified", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > rori", + "line_range": [ + 1900, + 1902 + ] + }, + { + "text": "|Zbkb () |v1.0.0-rc4 |Ratified |", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > rori", + "line_range": [ + 1904, + 1907 + ] + }, + { + "text": "[insns-roriw-sc,reftext=\"Rotate right Word (Immediate)\"]", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > rori", + "line_range": [ + 1911, + 1911 + ] + }, + { + "text": "Synopsis:: Rotate Right Word by Immediate", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > roriw", + "line_range": [ + 1914, + 1915 + ] + }, + { + "text": "Mnemonic:: roriw rd, rs1, shamt", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > roriw", + "line_range": [ + 1917, + 1918 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0x1b, attr: ['OP-IMM-32'] }, { bits: 5, name: 'rd' }, { bits: 3, name: 0x5, attr: ['RORIW']}, { bits: 5, name: 'rs1' }, { bits: 5, name: 'shamt' }, { bits: 7, name: 0x30, attr: ['RORIW'] }, ]} ....", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > roriw", + "line_range": [ + 1920, + 1931 + ] + }, + { + "text": "Description:: This instruction performs a rotate right on the least-significant word of rs1 by the amount in the least-significant log2(XLEN) bits of shamt.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > roriw", + "line_range": [ + 1933, + 1938 + ] + }, + { + "text": "The resulting word value is sign-extended by copying bit 31 to all of the more-significant bits.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > roriw", + "line_range": [ + 1933, + 1938 + ] + }, + { + "text": "Operation:: [source,sail] -- let rs1data = EXTZ(X(rs1)[31..0]; let result = (rs1data >> shamt) | (rs1data << (32 - shamt)); X(rd) = EXTS(result[31..0]); --", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > roriw", + "line_range": [ + 1940, + 1946 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > roriw", + "line_range": [ + 1948, + 1953 + ] + }, + { + "text": "|Zbb (ext:zbb[]) |v1.0.0 |Ratified", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > roriw", + "line_range": [ + 1955, + 1957 + ] + }, + { + "text": "|Zbkb () |v1.0.0-rc4 |Ratified |", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > roriw", + "line_range": [ + 1959, + 1962 + ] + }, + { + "text": "[insns-rorw-sc,reftext=\"Rotate right Word (Register)\"]", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > roriw", + "line_range": [ + 1966, + 1966 + ] + }, + { + "text": "Synopsis:: Rotate Right Word (Register)", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > rorw", + "line_range": [ + 1970, + 1971 + ] + }, + { + "text": "Mnemonic:: rorw rd, rs1, rs2", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > rorw", + "line_range": [ + 1973, + 1974 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0x3b, attr: ['OP-32'] }, { bits: 5, name: 'rd' }, { bits: 3, name: 0x5, attr: ['RORW']}, { bits: 5, name: 'rs1' }, { bits: 5, name: 'rs2' }, { bits: 7, name: 0x30, attr: ['RORW'] }, ]} ....", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > rorw", + "line_range": [ + 1976, + 1987 + ] + }, + { + "text": "Description:: This instruction performs a rotate right on the least-significant word of rs1 by the amount in least-significant 5 bits of rs2.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > rorw", + "line_range": [ + 1989, + 1991 + ] + }, + { + "text": "The resultant word is sign-extended by copying bit 31 to all of the more-significant bits.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > rorw", + "line_range": [ + 1989, + 1991 + ] + }, + { + "text": "Operation:: [source,sail] -- let rs1 = EXTZ(X(rs1)[31..0]) let shamt = X(rs2)[4..0]; let result = (rs1 >> shamt) | (rs1 << (32 - shamt)); X(rd) = EXTS(result); --", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > rorw", + "line_range": [ + 1993, + 2000 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > rorw", + "line_range": [ + 2002, + 2007 + ] + }, + { + "text": "|Zbb (ext:zbb[]) |v1.0.0 |Ratified", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > rorw", + "line_range": [ + 2009, + 2011 + ] + }, + { + "text": "|Zbkb () |v1.0.0-rc4 |Ratified |", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > rorw", + "line_range": [ + 2013, + 2016 + ] + }, + { + "text": "[insns-sha256sig0, reftext=\"SHA2-256 Sigma0 instruction\"]", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > rorw", + "line_range": [ + 2020, + 2020 + ] + }, + { + "text": "Synopsis:: Implements the Sigma0 transformation function as used in the SHA2-256 hash function cite:[nist:fips:180:4].", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha256sig0", + "line_range": [ + 2023, + 2025 + ] + }, + { + "text": "Mnemonic:: sha256sig0 rd, rs1", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha256sig0", + "line_range": [ + 2027, + 2028 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 0x13}, {bits: 5, name: 'rd'}, {bits: 3, name: 0x1}, {bits: 5, name: 'rs1'}, {bits: 5, name: 0x2}, {bits: 5, name: 0x8}, {bits: 2, name: 0x0}, ]} ....", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha256sig0", + "line_range": [ + 2030, + 2043 + ] + }, + { + "text": "Description:: This instruction is supported for both RV32 and RV64 base architectures.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha256sig0", + "line_range": [ + 2045, + 2054 + ] + }, + { + "text": "For RV32, the entire `XLEN` source register is operated on.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha256sig0", + "line_range": [ + 2045, + 2054 + ] + }, + { + "text": "For RV64, the low `32` bits of the source register are operated on, and the result sign extended to `XLEN` bits.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha256sig0", + "line_range": [ + 2045, + 2054 + ] + }, + { + "text": "Though named for SHA2-256, the instruction works for both the SHA2-224 and SHA2-256 parameterizations as described in cite:[nist:fips:180:4].", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha256sig0", + "line_range": [ + 2045, + 2054 + ] + }, + { + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated on.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha256sig0", + "line_range": [ + 2045, + 2054 + ] + }, + { + "text": "Operation:: [source,sail] -- function clause execute (SHA256SIG0(rs1,rd)) = { let inb : bits(32) = X(rs1)[31..0]; let result : bits(32) = ror32(inb, 7) ^ ror32(inb, 18) ^ (inb >> 3); X(rd) = EXTS(result); RETIRESUCCESS } --", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha256sig0", + "line_range": [ + 2056, + 2066 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha256sig0", + "line_range": [ + 2068, + 2073 + ] + }, + { + "text": "| | v1.0.0 | Ratified | | v1.0.0 | Ratified | | v1.0.0 | Ratified |", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha256sig0", + "line_range": [ + 2075, + 2084 + ] + }, + { + "text": "[insns-sha256sig1, reftext=\"SHA2-256 Sigma1 instruction\"]", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha256sig0", + "line_range": [ + 2088, + 2088 + ] + }, + { + "text": "Synopsis:: Implements the Sigma1 transformation function as used in the SHA2-256 hash function cite:[nist:fips:180:4].", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha256sig1", + "line_range": [ + 2091, + 2093 + ] + }, + { + "text": "Mnemonic:: sha256sig1 rd, rs1", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha256sig1", + "line_range": [ + 2095, + 2096 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 0x13}, {bits: 5, name: 'rd'}, {bits: 3, name: 0x1}, {bits: 5, name: 'rs1'}, {bits: 5, name: 0x3}, {bits: 5, name: 0x8}, {bits: 2, name: 0x0}, ]} ....", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha256sig1", + "line_range": [ + 2098, + 2111 + ] + }, + { + "text": "Description:: This instruction is supported for both RV32 and RV64 base architectures.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha256sig1", + "line_range": [ + 2113, + 2122 + ] + }, + { + "text": "For RV32, the entire `XLEN` source register is operated on.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha256sig1", + "line_range": [ + 2113, + 2122 + ] + }, + { + "text": "For RV64, the low `32` bits of the source register are operated on, and the result sign extended to `XLEN` bits.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha256sig1", + "line_range": [ + 2113, + 2122 + ] + }, + { + "text": "Though named for SHA2-256, the instruction works for both the SHA2-224 and SHA2-256 parameterizations as described in cite:[nist:fips:180:4].", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha256sig1", + "line_range": [ + 2113, + 2122 + ] + }, + { + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated on.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha256sig1", + "line_range": [ + 2113, + 2122 + ] + }, + { + "text": "Operation:: [source,sail] -- function clause execute (SHA256SIG1(rs1,rd)) = { let inb : bits(32) = X(rs1)[31..0]; let result : bits(32) = ror32(inb, 17) ^ ror32(inb, 19) ^ (inb >> 10); X(rd) = EXTS(result); RETIRESUCCESS } --", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha256sig1", + "line_range": [ + 2124, + 2134 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha256sig1", + "line_range": [ + 2136, + 2141 + ] + }, + { + "text": "| | v1.0.0 | Ratified | | v1.0.0 | Ratified | | v1.0.0 | Ratified |", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha256sig1", + "line_range": [ + 2143, + 2152 + ] + }, + { + "text": "[insns-sha256sum0, reftext=\"SHA2-256 Sum0 instruction\"]", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha256sig1", + "line_range": [ + 2156, + 2156 + ] + }, + { + "text": "Synopsis:: Implements the Sum0 transformation function as used in the SHA2-256 hash function cite:[nist:fips:180:4].", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha256sum0", + "line_range": [ + 2159, + 2161 + ] + }, + { + "text": "Mnemonic:: sha256sum0 rd, rs1", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha256sum0", + "line_range": [ + 2163, + 2164 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 0x13}, {bits: 5, name: 'rd'}, {bits: 3, name: 0x1}, {bits: 5, name: 'rs1'}, {bits: 5, name: 0x0}, {bits: 5, name: 0x8}, {bits: 2, name: 0x0}, ]} ....", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha256sum0", + "line_range": [ + 2166, + 2179 + ] + }, + { + "text": "Description:: This instruction is supported for both RV32 and RV64 base architectures.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha256sum0", + "line_range": [ + 2181, + 2190 + ] + }, + { + "text": "For RV32, the entire `XLEN` source register is operated on.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha256sum0", + "line_range": [ + 2181, + 2190 + ] + }, + { + "text": "For RV64, the low `32` bits of the source register are operated on, and the result sign extended to `XLEN` bits.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha256sum0", + "line_range": [ + 2181, + 2190 + ] + }, + { + "text": "Though named for SHA2-256, the instruction works for both the SHA2-224 and SHA2-256 parameterizations as described in cite:[nist:fips:180:4].", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha256sum0", + "line_range": [ + 2181, + 2190 + ] + }, + { + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated on.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha256sum0", + "line_range": [ + 2181, + 2190 + ] + }, + { + "text": "Operation:: [source,sail] -- function clause execute (SHA256SUM0(rs1,rd)) = { let inb : bits(32) = X(rs1)[31..0]; let result : bits(32) = ror32(inb, 2) ^ ror32(inb, 13) ^ ror32(inb, 22); X(rd) = EXTS(result); RETIRESUCCESS } --", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha256sum0", + "line_range": [ + 2192, + 2202 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha256sum0", + "line_range": [ + 2204, + 2209 + ] + }, + { + "text": "| | v1.0.0 | Ratified | | v1.0.0 | Ratified | | v1.0.0 | Ratified |", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha256sum0", + "line_range": [ + 2211, + 2220 + ] + }, + { + "text": "[insns-sha256sum1, reftext=\"SHA2-256 Sum1 instruction\"]", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha256sum0", + "line_range": [ + 2224, + 2224 + ] + }, + { + "text": "Synopsis:: Implements the Sum1 transformation function as used in the SHA2-256 hash function cite:[nist:fips:180:4].", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha256sum1", + "line_range": [ + 2227, + 2229 + ] + }, + { + "text": "Mnemonic:: sha256sum1 rd, rs1", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha256sum1", + "line_range": [ + 2231, + 2232 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 0x13}, {bits: 5, name: 'rd'}, {bits: 3, name: 0x1}, {bits: 5, name: 'rs1'}, {bits: 5, name: 0x1}, {bits: 5, name: 0x8}, {bits: 2, name: 0x0}, ]} ....", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha256sum1", + "line_range": [ + 2234, + 2247 + ] + }, + { + "text": "Description:: This instruction is supported for both RV32 and RV64 base architectures.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha256sum1", + "line_range": [ + 2249, + 2258 + ] + }, + { + "text": "For RV32, the entire `XLEN` source register is operated on.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha256sum1", + "line_range": [ + 2249, + 2258 + ] + }, + { + "text": "For RV64, the low `32` bits of the source register are operated on, and the result sign extended to `XLEN` bits.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha256sum1", + "line_range": [ + 2249, + 2258 + ] + }, + { + "text": "Though named for SHA2-256, the instruction works for both the SHA2-224 and SHA2-256 parameterizations as described in cite:[nist:fips:180:4].", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha256sum1", + "line_range": [ + 2249, + 2258 + ] + }, + { + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated on.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha256sum1", + "line_range": [ + 2249, + 2258 + ] + }, + { + "text": "Operation:: [source,sail] -- function clause execute (SHA256SUM1(rs1,rd)) = { let inb : bits(32) = X(rs1)[31..0]; let result : bits(32) = ror32(inb, 6) ^ ror32(inb, 11) ^ ror32(inb, 25); X(rd) = EXTS(result); RETIRESUCCESS } --", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha256sum1", + "line_range": [ + 2260, + 2270 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha256sum1", + "line_range": [ + 2272, + 2277 + ] + }, + { + "text": "| | v1.0.0 | Ratified | | v1.0.0 | Ratified | | v1.0.0 | Ratified |", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha256sum1", + "line_range": [ + 2279, + 2288 + ] + }, + { + "text": "[insns-sha512sig0h, reftext=\"SHA2-512 Sigma0 high (RV32)\"]", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha256sum1", + "line_range": [ + 2292, + 2292 + ] + }, + { + "text": "Synopsis:: Implements the high half of the Sigma0 transformation, as used in the SHA2-512 hash function cite:[nist:fips:180:4].", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig0h", + "line_range": [ + 2295, + 2297 + ] + }, + { + "text": "Mnemonic:: sha512sig0h rd, rs1, rs2", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig0h", + "line_range": [ + 2299, + 2300 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 0x33}, {bits: 5, name: 'rd'}, {bits: 3, name: 0x0}, {bits: 5, name: 'rs1'}, {bits: 5, name: 'rs2'}, {bits: 5, name: 0xe}, {bits: 2, name: 0x1}, ]} ....", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig0h", + "line_range": [ + 2302, + 2315 + ] + }, + { + "text": "Description:: This instruction is implemented on RV32 only.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig0h", + "line_range": [ + 2317, + 2324 + ] + }, + { + "text": "Used to compute the Sigma0 transform of the SHA2-512 hash function in conjunction with the instruction.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig0h", + "line_range": [ + 2317, + 2324 + ] + }, + { + "text": "The transform is a 64-bit to 64-bit function, so the input and output are each represented by two 32-bit registers.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig0h", + "line_range": [ + 2317, + 2324 + ] + }, + { + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated on.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig0h", + "line_range": [ + 2317, + 2324 + ] + }, + { + "text": "[NOTE] .Note to software developers The entire Sigma0 transform for SHA2-512 may be computed on RV32 using the following instruction sequence:", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig0h", + "line_range": [ + 2326, + 2330 + ] + }, + { + "text": "sha512sig0l t0, a0, a1 sha512sig0h t1, a1, a0", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig0h", + "line_range": [ + 2332, + 2333 + ] + }, + { + "text": "Operation:: [source,sail] -- function clause execute (SHA512SIG0H(rs2, rs1, rd)) = { X(rd) = EXTS((X(rs1) >> 1) ^ (X(rs1) >> 7) ^ (X(rs1) >> 8) ^ (X(rs2) << 31) ^ (X(rs2) << 24) ); RETIRESUCCESS } --", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig0h", + "line_range": [ + 2337, + 2346 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig0h", + "line_range": [ + 2348, + 2353 + ] + }, + { + "text": "| (RV32) | v1.0.0 | Ratified | (RV32) | v1.0.0 | Ratified | (RV32) | v1.0.0 | Ratified |", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig0h", + "line_range": [ + 2355, + 2364 + ] + }, + { + "text": "[insns-sha512sig0l, reftext=\"SHA2-512 Sigma0 low (RV32)\"]", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig0h", + "line_range": [ + 2368, + 2368 + ] + }, + { + "text": "Synopsis:: Implements the low half of the Sigma0 transformation, as used in the SHA2-512 hash function cite:[nist:fips:180:4].", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig0l", + "line_range": [ + 2371, + 2373 + ] + }, + { + "text": "Mnemonic:: sha512sig0l rd, rs1, rs2", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig0l", + "line_range": [ + 2375, + 2376 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 0x33}, {bits: 5, name: 'rd'}, {bits: 3, name: 0x0}, {bits: 5, name: 'rs1'}, {bits: 5, name: 'rs2'}, {bits: 5, name: 0xa}, {bits: 2, name: 0x1}, ]} ....", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig0l", + "line_range": [ + 2378, + 2391 + ] + }, + { + "text": "Description:: This instruction is implemented on RV32 only.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig0l", + "line_range": [ + 2393, + 2400 + ] + }, + { + "text": "Used to compute the Sigma0 transform of the SHA2-512 hash function in conjunction with the instruction.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig0l", + "line_range": [ + 2393, + 2400 + ] + }, + { + "text": "The transform is a 64-bit to 64-bit function, so the input and output are each represented by two 32-bit registers.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig0l", + "line_range": [ + 2393, + 2400 + ] + }, + { + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated on.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig0l", + "line_range": [ + 2393, + 2400 + ] + }, + { + "text": "[NOTE] .Note to software developers The entire Sigma0 transform for SHA2-512 may be computed on RV32 using the following instruction sequence:", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig0l", + "line_range": [ + 2402, + 2406 + ] + }, + { + "text": "sha512sig0l t0, a0, a1 sha512sig0h t1, a1, a0", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig0l", + "line_range": [ + 2408, + 2409 + ] + }, + { + "text": "Operation:: [source,sail] -- function clause execute (SHA512SIG0L(rs2, rs1, rd)) = { X(rd) = EXTS((X(rs1) >> 1) ^ (X(rs1) >> 7) ^ (X(rs1) >> 8) ^ (X(rs2) << 31) ^ (X(rs2) << 25) ^ (X(rs2) << 24) ); RETIRESUCCESS } --", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig0l", + "line_range": [ + 2413, + 2422 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig0l", + "line_range": [ + 2424, + 2429 + ] + }, + { + "text": "| (RV32) | v1.0.0 | Ratified | (RV32) | v1.0.0 | Ratified | (RV32) | v1.0.0 | Ratified |", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig0l", + "line_range": [ + 2431, + 2440 + ] + }, + { + "text": "[insns-sha512sig1h, reftext=\"SHA2-512 Sigma1 high (RV32)\"]", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig0l", + "line_range": [ + 2444, + 2444 + ] + }, + { + "text": "Synopsis:: Implements the high half of the Sigma1 transformation, as used in the SHA2-512 hash function cite:[nist:fips:180:4].", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig1h", + "line_range": [ + 2447, + 2449 + ] + }, + { + "text": "Mnemonic:: sha512sig1h rd, rs1, rs2", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig1h", + "line_range": [ + 2451, + 2452 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 0x33}, {bits: 5, name: 'rd'}, {bits: 3, name: 0x0}, {bits: 5, name: 'rs1'}, {bits: 5, name: 'rs2'}, {bits: 5, name: 0xf}, {bits: 2, name: 0x1}, ]} ....", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig1h", + "line_range": [ + 2454, + 2467 + ] + }, + { + "text": "Description:: This instruction is implemented on RV32 only.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig1h", + "line_range": [ + 2469, + 2476 + ] + }, + { + "text": "Used to compute the Sigma1 transform of the SHA2-512 hash function in conjunction with the instruction.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig1h", + "line_range": [ + 2469, + 2476 + ] + }, + { + "text": "The transform is a 64-bit to 64-bit function, so the input and output are each represented by two 32-bit registers.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig1h", + "line_range": [ + 2469, + 2476 + ] + }, + { + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated on.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig1h", + "line_range": [ + 2469, + 2476 + ] + }, + { + "text": "[NOTE] .Note to software developers The entire Sigma1 transform for SHA2-512 may be computed on RV32 using the following instruction sequence:", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig1h", + "line_range": [ + 2478, + 2482 + ] + }, + { + "text": "sha512sig1l t0, a0, a1 sha512sig1h t1, a1, a0", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig1h", + "line_range": [ + 2484, + 2485 + ] + }, + { + "text": "Operation:: [source,sail] -- function clause execute (SHA512SIG1H(rs2, rs1, rd)) = { X(rd) = EXTS((X(rs1) 6) ^ (X(rs1) >> 19) ^ (X(rs2) >> 29) ^ (X(rs2) << 13) ); RETIRESUCCESS } --", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig1h", + "line_range": [ + 2489, + 2498 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig1h", + "line_range": [ + 2500, + 2505 + ] + }, + { + "text": "| (RV32) | v1.0.0 | Ratified | (RV32) | v1.0.0 | Ratified | (RV32) | v1.0.0 | Ratified |", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig1h", + "line_range": [ + 2507, + 2516 + ] + }, + { + "text": "[insns-sha512sig1l, reftext=\"SHA2-512 Sigma1 low (RV32)\"]", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig1h", + "line_range": [ + 2520, + 2520 + ] + }, + { + "text": "Synopsis:: Implements the low half of the Sigma1 transformation, as used in the SHA2-512 hash function cite:[nist:fips:180:4].", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig1l", + "line_range": [ + 2523, + 2525 + ] + }, + { + "text": "Mnemonic:: sha512sig1l rd, rs1, rs2", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig1l", + "line_range": [ + 2527, + 2528 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 0x33}, {bits: 5, name: 'rd'}, {bits: 3, name: 0x0}, {bits: 5, name: 'rs1'}, {bits: 5, name: 'rs2'}, {bits: 5, name: 0xb}, {bits: 2, name: 0x1}, ]} ....", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig1l", + "line_range": [ + 2530, + 2543 + ] + }, + { + "text": "Description:: This instruction is implemented on RV32 only.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig1l", + "line_range": [ + 2545, + 2552 + ] + }, + { + "text": "Used to compute the Sigma1 transform of the SHA2-512 hash function in conjunction with the instruction.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig1l", + "line_range": [ + 2545, + 2552 + ] + }, + { + "text": "The transform is a 64-bit to 64-bit function, so the input and output are each represented by two 32-bit registers.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig1l", + "line_range": [ + 2545, + 2552 + ] + }, + { + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated on.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig1l", + "line_range": [ + 2545, + 2552 + ] + }, + { + "text": "[NOTE] .Note to software developers The entire Sigma1 transform for SHA2-512 may be computed on RV32 using the following instruction sequence:", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig1l", + "line_range": [ + 2554, + 2558 + ] + }, + { + "text": "sha512sig1l t0, a0, a1 sha512sig1h t1, a1, a0", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig1l", + "line_range": [ + 2560, + 2561 + ] + }, + { + "text": "Operation:: [source,sail] -- function clause execute (SHA512SIG1L(rs2, rs1, rd)) = { X(rd) = EXTS((X(rs1) 6) ^ (X(rs1) >> 19) ^ (X(rs2) >> 29) ^ (X(rs2) << 26) ^ (X(rs2) << 13) ); RETIRESUCCESS } --", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig1l", + "line_range": [ + 2565, + 2574 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig1l", + "line_range": [ + 2576, + 2581 + ] + }, + { + "text": "| (RV32) | v1.0.0 | Ratified | (RV32) | v1.0.0 | Ratified | (RV32) | v1.0.0 | Ratified |", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig1l", + "line_range": [ + 2583, + 2592 + ] + }, + { + "text": "[insns-sha512sum0r, reftext=\"SHA2-512 Sum0 (RV32)\"]", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig1l", + "line_range": [ + 2596, + 2596 + ] + }, + { + "text": "Synopsis:: Implements the Sum0 transformation, as used in the SHA2-512 hash function cite:[nist:fips:180:4].", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sum0r", + "line_range": [ + 2599, + 2601 + ] + }, + { + "text": "Mnemonic:: sha512sum0r rd, rs1, rs2", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sum0r", + "line_range": [ + 2603, + 2604 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 0x33}, {bits: 5, name: 'rd'}, {bits: 3, name: 0x0}, {bits: 5, name: 'rs1'}, {bits: 5, name: 'rs2'}, {bits: 5, name: 0x8}, {bits: 2, name: 0x1}, ]} ....", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sum0r", + "line_range": [ + 2606, + 2619 + ] + }, + { + "text": "Description:: This instruction is implemented on RV32 only.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sum0r", + "line_range": [ + 2621, + 2627 + ] + }, + { + "text": "Used to compute the Sum0 transform of the SHA2-512 hash function.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sum0r", + "line_range": [ + 2621, + 2627 + ] + }, + { + "text": "The transform is a 64-bit to 64-bit function, so the input and output is represented by two 32-bit registers.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sum0r", + "line_range": [ + 2621, + 2627 + ] + }, + { + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated on.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sum0r", + "line_range": [ + 2621, + 2627 + ] + }, + { + "text": "[NOTE] .Note to software developers The entire Sum0 transform for SHA2-512 may be computed on RV32 using the following instruction sequence:", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sum0r", + "line_range": [ + 2629, + 2633 + ] + }, + { + "text": "sha512sum0r t0, a0, a1 sha512sum0r t1, a1, a0", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sum0r", + "line_range": [ + 2635, + 2636 + ] + }, + { + "text": "Note the reversed source register ordering.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sum0r", + "line_range": [ + 2638, + 2639 + ] + }, + { + "text": "Operation:: [source,sail] -- function clause execute (SHA512SUM0R(rs2, rs1, rd)) = { X(rd) = EXTS((X(rs1) 28) ^ (X(rs2) >> 7) ^ (X(rs2) >> 2) ^ (X(rs2) << 4) ); RETIRESUCCESS } --", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sum0r", + "line_range": [ + 2641, + 2650 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sum0r", + "line_range": [ + 2652, + 2657 + ] + }, + { + "text": "| (RV32) | v1.0.0 | Ratified | (RV32) | v1.0.0 | Ratified | (RV32) | v1.0.0 | Ratified |", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sum0r", + "line_range": [ + 2659, + 2668 + ] + }, + { + "text": "[insns-sha512sum1r, reftext=\"SHA2-512 Sum1 (RV32)\"]", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sum0r", + "line_range": [ + 2672, + 2672 + ] + }, + { + "text": "Synopsis:: Implements the Sum1 transformation, as used in the SHA2-512 hash function cite:[nist:fips:180:4].", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sum1r", + "line_range": [ + 2675, + 2677 + ] + }, + { + "text": "Mnemonic:: sha512sum1r rd, rs1, rs2", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sum1r", + "line_range": [ + 2679, + 2680 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 0x33}, {bits: 5, name: 'rd'}, {bits: 3, name: 0x0}, {bits: 5, name: 'rs1'}, {bits: 5, name: 'rs2'}, {bits: 5, name: 0x9}, {bits: 2, name: 0x1}, ]} ....", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sum1r", + "line_range": [ + 2682, + 2695 + ] + }, + { + "text": "Description:: This instruction is implemented on RV32 only.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sum1r", + "line_range": [ + 2697, + 2703 + ] + }, + { + "text": "Used to compute the Sum1 transform of the SHA2-512 hash function.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sum1r", + "line_range": [ + 2697, + 2703 + ] + }, + { + "text": "The transform is a 64-bit to 64-bit function, so the input and output is represented by two 32-bit registers.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sum1r", + "line_range": [ + 2697, + 2703 + ] + }, + { + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated on.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sum1r", + "line_range": [ + 2697, + 2703 + ] + }, + { + "text": "[NOTE] .Note to software developers The entire Sum1 transform for SHA2-512 may be computed on RV32 using the following instruction sequence:", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sum1r", + "line_range": [ + 2705, + 2709 + ] + }, + { + "text": "sha512sum1r t0, a0, a1 sha512sum1r t1, a1, a0", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sum1r", + "line_range": [ + 2711, + 2712 + ] + }, + { + "text": "Note the reversed source register ordering.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sum1r", + "line_range": [ + 2714, + 2715 + ] + }, + { + "text": "Operation:: [source,sail] -- function clause execute (SHA512SUM1R(rs2, rs1, rd)) = { X(rd) = EXTS((X(rs1) 14) ^ (X(rs1) >> 18) ^ (X(rs2) >> 9) ^ (X(rs2) << 18) ^ (X(rs2) << 14) ); RETIRESUCCESS } --", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sum1r", + "line_range": [ + 2717, + 2726 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sum1r", + "line_range": [ + 2728, + 2733 + ] + }, + { + "text": "| (RV32) | v1.0.0 | Ratified | (RV32) | v1.0.0 | Ratified | (RV32) | v1.0.0 | Ratified |", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sum1r", + "line_range": [ + 2735, + 2744 + ] + }, + { + "text": "[insns-sha512sig0, reftext=\"SHA2-512 Sigma0 instruction (RV64)\"]", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sum1r", + "line_range": [ + 2748, + 2748 + ] + }, + { + "text": "Synopsis:: Implements the Sigma0 transformation function as used in the SHA2-512 hash function cite:[nist:fips:180:4].", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig0", + "line_range": [ + 2751, + 2753 + ] + }, + { + "text": "Mnemonic:: sha512sig0 rd, rs1", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig0", + "line_range": [ + 2755, + 2756 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 0x13}, {bits: 5, name: 'rd'}, {bits: 3, name: 0x1}, {bits: 5, name: 'rs1'}, {bits: 5, name: 0x6}, {bits: 5, name: 0x8}, {bits: 2, name: 0x0}, ]} ....", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig0", + "line_range": [ + 2758, + 2771 + ] + }, + { + "text": "Description:: This instruction is supported for the RV64 base architecture.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig0", + "line_range": [ + 2773, + 2778 + ] + }, + { + "text": "It implements the Sigma0 transform of the SHA2-512 hash function. cite:[nist:fips:180:4].", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig0", + "line_range": [ + 2773, + 2778 + ] + }, + { + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated on.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig0", + "line_range": [ + 2773, + 2778 + ] + }, + { + "text": "Operation:: [source,sail] -- function clause execute (SHA512SIG0(rs1, rd)) = { X(rd) = ror64(X(rs1), 1) ^ ror64(X(rs1), 8) ^ (X(rs1) >> 7); RETIRESUCCESS } --", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig0", + "line_range": [ + 2780, + 2788 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig0", + "line_range": [ + 2790, + 2795 + ] + }, + { + "text": "| (RV64) | v1.0.0 | Ratified | (RV64) | v1.0.0 | Ratified | (RV64) | v1.0.0 | Ratified |", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig0", + "line_range": [ + 2797, + 2806 + ] + }, + { + "text": "[insns-sha512sig1, reftext=\"SHA2-512 Sigma1 instruction (RV64)\"]", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig0", + "line_range": [ + 2810, + 2810 + ] + }, + { + "text": "Synopsis:: Implements the Sigma1 transformation function as used in the SHA2-512 hash function cite:[nist:fips:180:4].", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig1", + "line_range": [ + 2813, + 2815 + ] + }, + { + "text": "Mnemonic:: sha512sig1 rd, rs1", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig1", + "line_range": [ + 2817, + 2818 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 0x13}, {bits: 5, name: 'rd'}, {bits: 3, name: 0x1}, {bits: 5, name: 'rs1'}, {bits: 5, name: 0x7}, {bits: 5, name: 0x8}, {bits: 2, name: 0x0}, ]} ....", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig1", + "line_range": [ + 2820, + 2833 + ] + }, + { + "text": "Description:: This instruction is supported for the RV64 base architecture.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig1", + "line_range": [ + 2835, + 2840 + ] + }, + { + "text": "It implements the Sigma1 transform of the SHA2-512 hash function. cite:[nist:fips:180:4].", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig1", + "line_range": [ + 2835, + 2840 + ] + }, + { + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated on.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig1", + "line_range": [ + 2835, + 2840 + ] + }, + { + "text": "Operation:: [source,sail] -- function clause execute (SHA512SIG1(rs1, rd)) = { X(rd) = ror64(X(rs1), 19) ^ ror64(X(rs1), 61) ^ (X(rs1) >> 6); RETIRESUCCESS } --", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig1", + "line_range": [ + 2842, + 2850 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig1", + "line_range": [ + 2852, + 2857 + ] + }, + { + "text": "| (RV64) | v1.0.0 | Ratified | (RV64) | v1.0.0 | Ratified | (RV64) | v1.0.0 | Ratified |", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig1", + "line_range": [ + 2859, + 2868 + ] + }, + { + "text": "[insns-sha512sum0, reftext=\"SHA2-512 Sum0 instruction (RV64)\"]", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sig1", + "line_range": [ + 2872, + 2872 + ] + }, + { + "text": "Synopsis:: Implements the Sum0 transformation function as used in the SHA2-512 hash function cite:[nist:fips:180:4].", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sum0", + "line_range": [ + 2875, + 2877 + ] + }, + { + "text": "Mnemonic:: sha512sum0 rd, rs1", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sum0", + "line_range": [ + 2879, + 2880 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 0x13}, {bits: 5, name: 'rd'}, {bits: 3, name: 0x1}, {bits: 5, name: 'rs1'}, {bits: 5, name: 0x4}, {bits: 5, name: 0x8}, {bits: 2, name: 0x0}, ]} ....", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sum0", + "line_range": [ + 2882, + 2895 + ] + }, + { + "text": "Description:: This instruction is supported for the RV64 base architecture.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sum0", + "line_range": [ + 2897, + 2902 + ] + }, + { + "text": "It implements the Sum0 transform of the SHA2-512 hash function. cite:[nist:fips:180:4].", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sum0", + "line_range": [ + 2897, + 2902 + ] + }, + { + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated on.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sum0", + "line_range": [ + 2897, + 2902 + ] + }, + { + "text": "Operation:: [source,sail] -- function clause execute (SHA512SUM0(rs1, rd)) = { X(rd) = ror64(X(rs1), 28) ^ ror64(X(rs1), 34) ^ ror64(X(rs1) ,39); RETIRESUCCESS } --", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sum0", + "line_range": [ + 2904, + 2912 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sum0", + "line_range": [ + 2914, + 2919 + ] + }, + { + "text": "| (RV64) | v1.0.0 | Ratified | (RV64) | v1.0.0 | Ratified | (RV64) | v1.0.0 | Ratified |", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sum0", + "line_range": [ + 2921, + 2930 + ] + }, + { + "text": "[insns-sha512sum1, reftext=\"SHA2-512 Sum1 instruction (RV64)\"]", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sum0", + "line_range": [ + 2934, + 2934 + ] + }, + { + "text": "Synopsis:: Implements the Sum1 transformation function as used in the SHA2-512 hash function cite:[nist:fips:180:4].", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sum1", + "line_range": [ + 2937, + 2939 + ] + }, + { + "text": "Mnemonic:: sha512sum1 rd, rs1", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sum1", + "line_range": [ + 2941, + 2942 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 0x13}, {bits: 5, name: 'rd'}, {bits: 3, name: 0x1}, {bits: 5, name: 'rs1'}, {bits: 5, name: 0x5}, {bits: 5, name: 0x8}, {bits: 2, name: 0x0}, ]} ....", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sum1", + "line_range": [ + 2944, + 2957 + ] + }, + { + "text": "Description:: This instruction is supported for the RV64 base architecture.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sum1", + "line_range": [ + 2959, + 2964 + ] + }, + { + "text": "It implements the Sum1 transform of the SHA2-512 hash function. cite:[nist:fips:180:4].", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sum1", + "line_range": [ + 2959, + 2964 + ] + }, + { + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated on.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sum1", + "line_range": [ + 2959, + 2964 + ] + }, + { + "text": "Operation:: [source,sail] -- function clause execute (SHA512SUM1(rs1, rd)) = { X(rd) = ror64(X(rs1), 14) ^ ror64(X(rs1), 18) ^ ror64(X(rs1) ,41); RETIRESUCCESS } --", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sum1", + "line_range": [ + 2966, + 2974 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sum1", + "line_range": [ + 2976, + 2981 + ] + }, + { + "text": "| (RV64) | v1.0.0 | Ratified | (RV64) | v1.0.0 | Ratified | (RV64) | v1.0.0 | Ratified |", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sum1", + "line_range": [ + 2983, + 2992 + ] + }, + { + "text": "[insns-sm3p0, reftext=\"SM3 P0 transform\"]", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sha512sum1", + "line_range": [ + 2996, + 2996 + ] + }, + { + "text": "Synopsis:: Implements the P0 transformation function as used in the SM3 hash function cite:[gbt:sm3,iso:sm3].", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sm3p0", + "line_range": [ + 2999, + 3001 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 0x13}, {bits: 5, name: 'rd'}, {bits: 3, name: 0x1}, {bits: 5, name: 'rs1'}, {bits: 5, name: 0x8}, {bits: 5, name: 0x8}, {bits: 2, name: 0x0}, ]} ....", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sm3p0", + "line_range": [ + 3006, + 3019 + ] + }, + { + "text": "Description:: This instruction is supported for the RV32 and RV64 base architectures.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sm3p0", + "line_range": [ + 3021, + 3025 + ] + }, + { + "text": "It implements the P0 transform of the SM3 hash function cite:[gbt:sm3,iso:sm3].", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sm3p0", + "line_range": [ + 3021, + 3025 + ] + }, + { + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated on.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sm3p0", + "line_range": [ + 3021, + 3025 + ] + }, + { + "text": ".Supporting Material Operation:: [source,sail] -- function clause execute (SM3P0(rs1, rd)) = { let r1 : bits(32) = X(rs1)[31..0]; let result : bits(32) = r1 ^ rol32(r1, 9) ^ rol32(r1, 17); X(rd) = EXTS(result); RETIRESUCCESS } --", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sm3p0", + "line_range": [ + 3027, + 3038 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sm3p0", + "line_range": [ + 3040, + 3045 + ] + }, + { + "text": "| | v1.0.0 | Ratified | | v1.0.0 | Ratified |", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sm3p0", + "line_range": [ + 3047, + 3053 + ] + }, + { + "text": "[insns-sm3p1, reftext=\"SM3 P1 transform\"]", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sm3p0", + "line_range": [ + 3057, + 3057 + ] + }, + { + "text": "Synopsis:: Implements the P1 transformation function as used in the SM3 hash function cite:[gbt:sm3,iso:sm3].", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sm3p1", + "line_range": [ + 3060, + 3062 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 0x13}, {bits: 5, name: 'rd'}, {bits: 3, name: 0x1}, {bits: 5, name: 'rs1'}, {bits: 5, name: 0x9}, {bits: 5, name: 0x8}, {bits: 2, name: 0x0}, ]} ....", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sm3p1", + "line_range": [ + 3067, + 3080 + ] + }, + { + "text": "Description:: This instruction is supported for the RV32 and RV64 base architectures.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sm3p1", + "line_range": [ + 3082, + 3086 + ] + }, + { + "text": "It implements the P1 transform of the SM3 hash function cite:[gbt:sm3,iso:sm3].", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sm3p1", + "line_range": [ + 3082, + 3086 + ] + }, + { + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated on.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sm3p1", + "line_range": [ + 3082, + 3086 + ] + }, + { + "text": ".Supporting Material Operation:: [source,sail] -- function clause execute (SM3P1(rs1, rd)) = { let r1 : bits(32) = X(rs1)[31..0]; let result : bits(32) = r1 ^ rol32(r1, 15) ^ rol32(r1, 23); X(rd) = EXTS(result); RETIRESUCCESS } --", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sm3p1", + "line_range": [ + 3088, + 3099 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sm3p1", + "line_range": [ + 3101, + 3106 + ] + }, + { + "text": "| | v1.0.0 | Ratified | | v1.0.0 | Ratified |", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sm3p1", + "line_range": [ + 3108, + 3114 + ] + }, + { + "text": "[insns-sm4ed, reftext=\"SM4 Encrypt/Decrypt Instruction\"]", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sm3p1", + "line_range": [ + 3118, + 3118 + ] + }, + { + "text": "Synopsis:: Accelerates the block encrypt/decrypt operation of the SM4 block cipher cite:[gbt:sm4, iso:sm4].", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sm4ed", + "line_range": [ + 3121, + 3123 + ] + }, + { + "text": "Mnemonic:: sm4ed rd, rs1, rs2, bs", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sm4ed", + "line_range": [ + 3125, + 3126 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 0x33}, {bits: 5, name: 'rd'}, {bits: 3, name: 0x0}, {bits: 5, name: 'rs1'}, {bits: 5, name: 'rs2'}, {bits: 5, name: 0x18}, {bits: 2, name: 'bs'}, ]} ....", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sm4ed", + "line_range": [ + 3128, + 3141 + ] + }, + { + "text": "Description:: Implements a T-tables in hardware style approach to accelerating the SM4 round function. A byte is extracted from `rs2` based on `bs`, to which the SBox and linear layer transforms are applied, before the result is XOR'd with `rs1` and written back to `rd`.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sm4ed", + "line_range": [ + 3143, + 3152 + ] + }, + { + "text": "This instruction exists on RV32 and RV64 base architectures.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sm4ed", + "line_range": [ + 3143, + 3152 + ] + }, + { + "text": "On RV64, the 32-bit result is sign extended to XLEN bits.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sm4ed", + "line_range": [ + 3143, + 3152 + ] + }, + { + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated on.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sm4ed", + "line_range": [ + 3143, + 3152 + ] + }, + { + "text": "Operation:: [source,sail] -- function clause execute (SM4ED (bs,rs2,rs1,rd)) = { let shamt : bits(5) = bs @ 0b000; let sbin : bits(8) = (X(rs2)[31..0] >> shamt)[7..0]; let x : bits(32) = 0x000000 @ sm4sbox(sbin); let y : bits(32) = x ^ (x << 8) ^ ( x << 2) ^ (x << 18) ^ ((x & 0x0000003F) << 26) ^ ((x & 0x000000C0) << 10); let z : bits(32) = rol32(y, unsigned(shamt)); let result: bits(32) = z ^ X(rs1)[31..0]; X(rd) = EXTS(result); RETIRESUCCESS } --", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sm4ed", + "line_range": [ + 3154, + 3170 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sm4ed", + "line_range": [ + 3172, + 3177 + ] + }, + { + "text": "| | v1.0.0 | Ratified | | v1.0.0 | Ratified |", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sm4ed", + "line_range": [ + 3179, + 3185 + ] + }, + { + "text": "[insns-sm4ks, reftext=\"SM4 Key Schedule Instruction\"]", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sm4ed", + "line_range": [ + 3189, + 3189 + ] + }, + { + "text": "Synopsis:: Accelerates the Key Schedule operation of the SM4 block cipher cite:[gbt:sm4, iso:sm4].", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sm4ks", + "line_range": [ + 3192, + 3194 + ] + }, + { + "text": "Mnemonic:: sm4ks rd, rs1, rs2, bs", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sm4ks", + "line_range": [ + 3196, + 3197 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 0x33}, {bits: 5, name: 'rd'}, {bits: 3, name: 0x0}, {bits: 5, name: 'rs1'}, {bits: 5, name: 'rs2'}, {bits: 5, name: 0x1a}, {bits: 2, name: 'bs'}, ]} ....", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sm4ks", + "line_range": [ + 3199, + 3212 + ] + }, + { + "text": "Description:: Implements a T-tables in hardware style approach to accelerating the SM4 Key Schedule. A byte is extracted from `rs2` based on `bs`, to which the SBox and linear layer transforms are applied, before the result is XOR'd with `rs1` and written back to `rd`.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sm4ks", + "line_range": [ + 3214, + 3223 + ] + }, + { + "text": "This instruction exists on RV32 and RV64 base architectures.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sm4ks", + "line_range": [ + 3214, + 3223 + ] + }, + { + "text": "On RV64, the 32-bit result is sign extended to XLEN bits.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sm4ks", + "line_range": [ + 3214, + 3223 + ] + }, + { + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated on.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sm4ks", + "line_range": [ + 3214, + 3223 + ] + }, + { + "text": "Operation:: [source,sail] -- function clause execute (SM4KS (bs,rs2,rs1,rd)) = { let shamt : bits(5) = (bs @ 0b000); let sbin : bits(8) = (X(rs2)[31..0] >> shamt)[7..0]; let x : bits(32) = 0x000000 @ sm4sbox(sbin); let y : bits(32) = x ^ ((x & 0x00000007) << 29) ^ ((x & 0x000000FE) << 7) ^ ((x & 0x00000001) << 23) ^ ((x & 0x000000F8) << 13) ; let z : bits(32) = rol32(y, unsigned(shamt)); let result: bits(32) = z ^ X(rs1)[31..0]; X(rd) = EXTS(result); RETIRESUCCESS } --", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sm4ks", + "line_range": [ + 3225, + 3240 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sm4ks", + "line_range": [ + 3242, + 3247 + ] + }, + { + "text": "| | v1.0.0 | Ratified | | v1.0.0 | Ratified |", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sm4ks", + "line_range": [ + 3249, + 3255 + ] + }, + { + "text": "[insns-unzip-sc,reftext=\"Bit deinterleave\"]", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > sm4ks", + "line_range": [ + 3259, + 3259 + ] + }, + { + "text": "Synopsis:: Place odd and even bits of the source register into upper and lower halves of the destination register, respectively.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > unzip", + "line_range": [ + 3262, + 3264 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ {bits: 2, name: 0x3}, {bits: 5, name: 0x4}, {bits: 5, name: 'rd'}, {bits: 3, name: 0x5}, {bits: 5, name: 'rs1'}, {bits: 5, name: 0xf}, {bits: 7, name: 0x4}, ]} ....", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > unzip", + "line_range": [ + 3269, + 3281 + ] + }, + { + "text": "Description:: This instruction scatters all of the odd and even bits of a source word into the high and low halves of a destination word.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > unzip", + "line_range": [ + 3283, + 3287 + ] + }, + { + "text": "It is the inverse of the instruction.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > unzip", + "line_range": [ + 3283, + 3287 + ] + }, + { + "text": "This instruction is available only on RV32.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > unzip", + "line_range": [ + 3283, + 3287 + ] + }, + { + "text": "Operation:: [source,sail] -- foreach (i from 0 to xlen/2-1) { X(rd)[i] = X(rs1)[2*i] X(rd)[i+xlen/2] = X(rs1)[2*i+1] } --", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > unzip", + "line_range": [ + 3289, + 3296 + ] + }, + { + "text": ".Software Hint [NOTE, caption=\"SH\" ] This instruction is useful for implementing the SHA3 cryptographic hash function on a 32-bit architecture, as it implements the bit-interleaving operation used to speed up the 64-bit rotations directly.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > unzip", + "line_range": [ + 3298, + 3305 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > unzip", + "line_range": [ + 3307, + 3312 + ] + }, + { + "text": "|Zbkb () (RV32) |v1.0.0-rc4 |Ratified |", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > unzip", + "line_range": [ + 3314, + 3317 + ] + }, + { + "text": "[insns-xnor-sc,reftext=\"Exclusive NOR\"]", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > unzip", + "line_range": [ + 3321, + 3321 + ] + }, + { + "text": "Mnemonic:: xnor rd, rs1, rs2", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > xnor", + "line_range": [ + 3327, + 3328 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0x33, attr: ['OP'] }, { bits: 5, name: 'rd' }, { bits: 3, name: 0x4, attr: ['XNOR']}, { bits: 5, name: 'rs1' }, { bits: 5, name: 'rs2' }, { bits: 7, name: 0x20, attr: ['XNOR'] }, ]} ....", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > xnor", + "line_range": [ + 3330, + 3341 + ] + }, + { + "text": "Description:: This instruction performs the bit-wise exclusive-NOR operation on rs1 and rs2.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > xnor", + "line_range": [ + 3343, + 3344 + ] + }, + { + "text": "Operation:: [source,sail] -- X(rd) = ~(X(rs1) ^ X(rs2)); --", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > xnor", + "line_range": [ + 3346, + 3350 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > xnor", + "line_range": [ + 3352, + 3357 + ] + }, + { + "text": "|Zbb (ext:zbb[]) |v1.0.0 |Ratified", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > xnor", + "line_range": [ + 3359, + 3361 + ] + }, + { + "text": "|Zbkb () |v1.0.0-rc4 |Ratified |", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > xnor", + "line_range": [ + 3363, + 3366 + ] + }, + { + "text": "<<< [insns-xperm8-sc,reftext=\"Crossbar permutation (bytes)\"]", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > xnor", + "line_range": [ + 3368, + 3369 + ] + }, + { + "text": "Synopsis:: Byte-wise lookup of indices into a vector in registers.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > xperm8", + "line_range": [ + 3372, + 3373 + ] + }, + { + "text": "Mnemonic:: xperm8 rd, rs1, rs2", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > xperm8", + "line_range": [ + 3375, + 3376 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ {bits: 2, name: 0x3}, {bits: 5, name: 0xc}, {bits: 5, name: 'rd'}, {bits: 3, name: 0x4}, {bits: 5, name: 'rs1'}, {bits: 5, name: 'rs2'}, {bits: 7, name: 0x14}, ]} ....", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > xperm8", + "line_range": [ + 3378, + 3390 + ] + }, + { + "text": "Description:: The xperm8 instruction operates on bytes.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > xperm8", + "line_range": [ + 3392, + 3397 + ] + }, + { + "text": "The rs1 register contains a vector of XLEN/8 8-bit elements.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > xperm8", + "line_range": [ + 3392, + 3397 + ] + }, + { + "text": "The rs2 register contains a vector of XLEN/8 8-bit indexes.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > xperm8", + "line_range": [ + 3392, + 3397 + ] + }, + { + "text": "The result is each element in rs2 replaced by the indexed element in rs1, or zero if the index into rs2 is out of bounds.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > xperm8", + "line_range": [ + 3392, + 3397 + ] + }, + { + "text": "Operation:: [source,sail] -- val xperm8lookup : (bits(8), xlenbits) -> bits(8) function xperm8lookup (idx, lut) = { (lut >> (idx @ 0b000))[7..0] }", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > xperm8", + "line_range": [ + 3399, + 3405 + ] + }, + { + "text": "function clause execute ( XPERM8 (rs2,rs1,rd)) = { result : xlenbits = EXTZ(0b0); foreach(i from 0 to xlen by 8) { result[i+7..i] = xperm8lookup(X(rs2)[i+7..i], X(rs1)); }; X(rd) = result; RETIRESUCCESS } --", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > xperm8", + "line_range": [ + 3407, + 3415 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > xperm8", + "line_range": [ + 3417, + 3422 + ] + }, + { + "text": "|Zbkx () |v1.0 |Ratified |", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > xperm8", + "line_range": [ + 3424, + 3427 + ] + }, + { + "text": "[insns-xperm4-sc,reftext=\"Crossbar permutation (nibbles)\"]", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > xperm8", + "line_range": [ + 3431, + 3431 + ] + }, + { + "text": "Synopsis:: Nibble-wise lookup of indices into a vector.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > xperm4", + "line_range": [ + 3434, + 3435 + ] + }, + { + "text": "Mnemonic:: xperm4 rd, rs1, rs2", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > xperm4", + "line_range": [ + 3437, + 3438 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ {bits: 2, name: 0x3}, {bits: 5, name: 0xc}, {bits: 5, name: 'rd'}, {bits: 3, name: 0x2}, {bits: 5, name: 'rs1'}, {bits: 5, name: 'rs2'}, {bits: 7, name: 0x14}, ]} ....", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > xperm4", + "line_range": [ + 3440, + 3452 + ] + }, + { + "text": "Description:: The xperm4 instruction operates on nibbles.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > xperm4", + "line_range": [ + 3454, + 3459 + ] + }, + { + "text": "The rs1 register contains a vector of XLEN/4 4-bit elements.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > xperm4", + "line_range": [ + 3454, + 3459 + ] + }, + { + "text": "The rs2 register contains a vector of XLEN/4 4-bit indexes.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > xperm4", + "line_range": [ + 3454, + 3459 + ] + }, + { + "text": "The result is each element in rs2 replaced by the indexed element in rs1, or zero if the index into rs2 is out of bounds.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > xperm4", + "line_range": [ + 3454, + 3459 + ] + }, + { + "text": "Operation:: [source,sail] -- val xperm4lookup : (bits(4), xlenbits) -> bits(4) function xperm4lookup (idx, lut) = { (lut >> (idx @ 0b00))[3..0] }", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > xperm4", + "line_range": [ + 3461, + 3467 + ] + }, + { + "text": "function clause execute ( XPERM4 (rs2,rs1,rd)) = { result : xlenbits = EXTZ(0b0); foreach(i from 0 to xlen by 4) { result[i+3..i] = xperm4lookup(X(rs2)[i+3..i], X(rs1)); }; X(rd) = result; RETIRESUCCESS } --", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > xperm4", + "line_range": [ + 3469, + 3477 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > xperm4", + "line_range": [ + 3479, + 3484 + ] + }, + { + "text": "|Zbkx () |v1.0 |Ratified |", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > xperm4", + "line_range": [ + 3486, + 3489 + ] + }, + { + "text": "[insns-zip-sc,reftext=\"Bit interleave\"]", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > xperm4", + "line_range": [ + 3493, + 3493 + ] + }, + { + "text": "Synopsis:: Interleave upper and lower halves of the source register into odd and even bits of the destination register, respectively.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > zip", + "line_range": [ + 3496, + 3498 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ {bits: 2, name: 0x3}, {bits: 5, name: 0x4}, {bits: 5, name: 'rd'}, {bits: 3, name: 0x1}, {bits: 5, name: 'rs1'}, {bits: 5, name: 0xf}, {bits: 7, name: 0x4}, ]} ....", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > zip", + "line_range": [ + 3503, + 3515 + ] + }, + { + "text": "Description:: This instruction gathers bits from the high and low halves of the source word into odd/even bit positions in the destination word.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > zip", + "line_range": [ + 3517, + 3521 + ] + }, + { + "text": "It is the inverse of the instruction.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > zip", + "line_range": [ + 3517, + 3521 + ] + }, + { + "text": "This instruction is available only on RV32.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > zip", + "line_range": [ + 3517, + 3521 + ] + }, + { + "text": "Operation:: [source,sail] -- foreach (i from 0 to xlen/2-1) { X(rd)[2*i] = X(rs1)[i] X(rd)[2*i+1] = X(rs1)[i+xlen/2] } --", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > zip", + "line_range": [ + 3523, + 3530 + ] + }, + { + "text": ".Software Hint [NOTE, caption=\"SH\" ] This instruction is useful for implementing the SHA3 cryptographic hash function on a 32-bit architecture, as it implements the bit-interleaving operation used to speed up the 64-bit rotations directly.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > zip", + "line_range": [ + 3532, + 3539 + ] + }, + { + "text": "Included in:: | |Extension |Minimum version |Lifecycle state", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > zip", + "line_range": [ + 3541, + 3546 + ] + }, + { + "text": "|Zbkb () (RV32) |v1.0.0-rc4 |Ratified |", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instructions > zip", + "line_range": [ + 3548, + 3551 + ] + }, + { + "text": "The `seed` CSR provides an interface to a NIST SP 800-90B cite:[TuBaKe:18] or BSI AIS-31 cite:[KiSc11] compliant physical Entropy Source (ES).", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source", + "line_range": [ + 3558, + 3559 + ] + }, + { + "text": "An entropy source, by itself, is not a cryptographically secure Random Bit Generator (RBG), but can be used to build standard (and nonstandard) RBGs of many types with the help of symmetric cryptography.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source", + "line_range": [ + 3561, + 3571 + ] + }, + { + "text": "Expected usage is to condition (typically with SHA-2/3) the output from an entropy source and use it to seed a cryptographically secure Deterministic Random Bit Generator (DRBG) such as AES-based `CTRDRBG` cite:[BaKe15].", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source", + "line_range": [ + 3561, + 3571 + ] + }, + { + "text": "The combination of an Entropy Source, Conditioning, and a DRBG can be used to create random bits securely cite:[BaKeMc:25].", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source", + "line_range": [ + 3561, + 3571 + ] + }, + { + "text": "See for a non-normative description of a certification and self-certification procedures, design rationale, and more detailed suggestions on how the entropy source output can be used.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source", + "line_range": [ + 3561, + 3571 + ] + }, + { + "text": "`seed` is an unprivileged CSR located at address `0x015`.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR", + "line_range": [ + 3576, + 3577 + ] + }, + { + "text": "The 32-bit contents of `seed` are as follows:", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR", + "line_range": [ + 3576, + 3577 + ] + }, + { + "text": "| |Bits |Name |Description", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR", + "line_range": [ + 3579, + 3581 + ] + }, + { + "text": "|`31:30` |`OPST` |Status: `BIST` (00), `WAIT` (01), `ES16` (10), `DEAD` (11).", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR", + "line_range": [ + 3583, + 3584 + ] + }, + { + "text": "|`29:24` |reserved |For future use by the RISC-V specification.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR", + "line_range": [ + 3586, + 3586 + ] + }, + { + "text": "|`23:16` |custom |Designated for custom and experimental use.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR", + "line_range": [ + 3588, + 3588 + ] + }, + { + "text": "|`15: 0` |`entropy` |16 bits of randomness, only when `OPST=ES16`. |", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR", + "line_range": [ + 3590, + 3591 + ] + }, + { + "text": "Attempts to access the `seed` CSR using a read-only CSR-access instruction (`CSRRS`/`CSRRC` with rs1=`x0` or `CSRRSI`/`CSRRCI` with uimm=0) raise an illegal-instruction exception; any other CSR-access instruction may be used to access `seed`.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR", + "line_range": [ + 3593, + 3598 + ] + }, + { + "text": "The write value (in `rs1` or `uimm`) must be ignored by implementations.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR", + "line_range": [ + 3593, + 3598 + ] + }, + { + "text": "The purpose of the write is to signal polling and flushing.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR", + "line_range": [ + 3593, + 3598 + ] + }, + { + "text": "Software normally uses the instruction `csrrw rd, seed, x0` to read the `seed` CSR.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR", + "line_range": [ + 3600, + 3601 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 0x73, attr: \"SYSTEM\"}, {bits: 5, name: 'rd'}, {bits: 3, name: 0x1, attr: \"CSRRW\"}, {bits: 5, name: 0x0, attr: \"x0\"}, {bits: 12, name: 0x15, attr: \"seed = 0x015\"}, ]} ....", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR", + "line_range": [ + 3603, + 3613 + ] + }, + { + "text": "The `seed` CSR is also access controlled by execution mode, and attempted read or write access will raise an illegal-instruction exception outside M mode unless access is explicitly granted.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR", + "line_range": [ + 3615, + 3618 + ] + }, + { + "text": "The status bits `seed[31:30]` = `OPST` may be `ES16` (10), indicating successful polling, or one of three entropy polling failure statuses `BIST` (00), `WAIT` (01), or `DEAD` (11), discussed below.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR", + "line_range": [ + 3620, + 3622 + ] + }, + { + "text": "Each returned `seed[15:0]` = `entropy` value represents unique randomness when `OPST`=`ES16` (`seed[31:30]` = `10`), even if its numerical value is the same as that of a previously polled `entropy` value.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR", + "line_range": [ + 3624, + 3629 + ] + }, + { + "text": "The implementation requirements of `entropy` bits are defined in .", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR", + "line_range": [ + 3624, + 3629 + ] + }, + { + "text": "When `OPST` is not `ES16`, `entropy` must be set to 0.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR", + "line_range": [ + 3624, + 3629 + ] + }, + { + "text": "An implementation may safely set reserved and custom bits to zeros.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR", + "line_range": [ + 3624, + 3629 + ] + }, + { + "text": "For security reasons, the interface guarantees that secret `entropy` words are not made available multiple times.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR", + "line_range": [ + 3631, + 3636 + ] + }, + { + "text": "Hence polling (reading) must also have the side effect of clearing (wipe-on-read) the `entropy` contents and changing the state to `WAIT` (unless there is `entropy` immediately available for `ES16`).", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR", + "line_range": [ + 3631, + 3636 + ] + }, + { + "text": "Other states (`BIST`, `WAIT`, and `DEAD`) may be unaffected by polling.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR", + "line_range": [ + 3631, + 3636 + ] + }, + { + "text": "The Status Bits returned in `seed[31:30]`=`OPST`:", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR", + "line_range": [ + 3638, + 3638 + ] + }, + { + "text": "`00` - `BIST` indicates that Built-In Self-Test \"on-demand\" (BIST) testing is being performed.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR", + "line_range": [ + 3640, + 3646 + ] + }, + { + "text": "If `OPST` returns temporarily to `BIST` from any other state, this signals a non-fatal self-test alarm, which is non-actionable, apart from being logged.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR", + "line_range": [ + 3640, + 3646 + ] + }, + { + "text": "Such a `BIST` alarm must be latched until polled at least once to enable software to record its occurrence.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR", + "line_range": [ + 3640, + 3646 + ] + }, + { + "text": "`01` - `WAIT` means that a sufficient amount of entropy is not yet available.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR", + "line_range": [ + 3648, + 3651 + ] + }, + { + "text": "This is not an error condition and may (in fact) be more frequent than ES16 since physical entropy sources often have low bandwidth.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR", + "line_range": [ + 3648, + 3651 + ] + }, + { + "text": "`10` - `ES16` indicates success; the low bits `seed[15:0]` will have 16 bits of randomness (`entropy`), which is guaranteed to meet certain minimum entropy requirements, regardless of implementation.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR", + "line_range": [ + 3653, + 3656 + ] + }, + { + "text": "`11` - `DEAD` is an unrecoverable self-test error.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR", + "line_range": [ + 3658, + 3663 + ] + }, + { + "text": "This may indicate a hardware fault, a security issue, or (extremely rarely) a type-1 statistical false positive in the continuous testing procedures.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR", + "line_range": [ + 3658, + 3663 + ] + }, + { + "text": "In case of a fatal failure, an immediate lockdown may also be an appropriate response in dedicated security devices.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR", + "line_range": [ + 3658, + 3663 + ] + }, + { + "text": "**Example.** `0x8000ABCD` is a valid `ES16` status output, with `0xABCD` being the `entropy` value. `0xFFFFFFFF` is an invalid output (`DEAD`) with no `entropy` value.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR", + "line_range": [ + 3665, + 3667 + ] + }, + { + "text": "image::esstate.svg[title=\"Entropy Source state transition diagram.\", align=\"center\",scaledwidth=40%] Normally the operational state alternates between WAIT (no data) and ES16, which means that 16 bits of randomness (`entropy`) have been polled. BIST (Built-in Self-Test) only occurs after reset or to signal a non-fatal self-test alarm (if reached after WAIT or ES16). DEAD is an unrecoverable error state.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > The `seed` CSR", + "line_range": [ + 3669, + 3677 + ] + }, + { + "text": "The output `entropy` (`seed[15:0]` in ES16 state) is not necessarily fully conditioned randomness due to hardware and energy limitations of smaller, low-powered implementations.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements", + "line_range": [ + 3682, + 3689 + ] + }, + { + "text": "However, minimum requirements are defined.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements", + "line_range": [ + 3682, + 3689 + ] + }, + { + "text": "The main requirement is that 2-to-1 cryptographic post-processing in 256-bit input blocks will yield 128-bit \"full entropy\" output blocks.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements", + "line_range": [ + 3682, + 3689 + ] + }, + { + "text": "Entropy source users may make this conservative assumption but are not prohibited from using more than twice the number of seed bits relative to the desired resulting entropy.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements", + "line_range": [ + 3682, + 3689 + ] + }, + { + "text": "An implementation of the entropy source should meet at least one of the following requirements sets in order to be considered a secure and safe design:", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements", + "line_range": [ + 3691, + 3693 + ] + }, + { + "text": ": A physical entropy source meeting NIST SP 800-90B cite:[TuBaKe:18] criteria with evaluated min-entropy of 192 bits for each 256 output bits (min-entropy rate 0.75).", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements", + "line_range": [ + 3695, + 3697 + ] + }, + { + "text": ": A physical entropy source meeting the AIS-31 PTG.2 cite:[KiSc11] criteria, implying average Shannon entropy rate 0.997.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements", + "line_range": [ + 3699, + 3702 + ] + }, + { + "text": "The source must also meet the NIST 800-90B min-entropy rate 192/256 = 0.75.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements", + "line_range": [ + 3699, + 3702 + ] + }, + { + "text": ": A virtual entropy source is a DRBG seeded from a physical entropy source.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements", + "line_range": [ + 3704, + 3706 + ] + }, + { + "text": "It must have at least a 256-bit (Post-Quantum Category 5) internal security level.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements", + "line_range": [ + 3704, + 3706 + ] + }, + { + "text": "All implementations must signal initialization, test mode, and health alarms as required by respective standards.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements", + "line_range": [ + 3708, + 3711 + ] + }, + { + "text": "This may require the implementer to add non-standard (custom) test interfaces in a secure and safe manner, an example of which is described in", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements", + "line_range": [ + 3708, + 3711 + ] + }, + { + "text": "All NIST SP 800-90B cite:[TuBaKe:18] required components and health test mechanisms must be implemented.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements > NIST SP 800-90B / FIPS 140-3 Requirements", + "line_range": [ + 3717, + 3718 + ] + }, + { + "text": "The entropy requirement is satisfied if 128 bits of full entropy can be obtained from each 256-bit (16*16 -bit) successful, but possibly non-consecutive `entropy` (ES16) output sequence using a vetted conditioning algorithm such as a cryptographic hash (See Section 3.1.5.1.1, SP 800-90B cite:[TuBaKe:18]).", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements > NIST SP 800-90B / FIPS 140-3 Requirements", + "line_range": [ + 3720, + 3725 + ] + }, + { + "text": "In practice, a min-entropy rate of 0.75 or larger is required for this.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements > NIST SP 800-90B / FIPS 140-3 Requirements", + "line_range": [ + 3720, + 3725 + ] + }, + { + "text": "Note that 128 bits of estimated input min-entropy does not yield 128 bits of conditioned, full entropy in SP 800-90B/C evaluation.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements > NIST SP 800-90B / FIPS 140-3 Requirements", + "line_range": [ + 3727, + 3733 + ] + }, + { + "text": "Instead, the implication is that every 256-bit sequence should have min-entropy of at least 128+64 = 192 bits, as discussed in SP 800-90C cite:[BaKeMc:25]; the likelihood of successfully \"guessing\" an individual 256-bit output sequence should not be higher than 2^-192^ even with (almost) unconstrained amount of entropy source data and computational power.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements > NIST SP 800-90B / FIPS 140-3 Requirements", + "line_range": [ + 3727, + 3733 + ] + }, + { + "text": "Rather than attempting to define all the mathematical and architectural properties that the entropy source must satisfy, we define that the physical entropy source be strong and robust enough to pass the equivalent of NIST SP 800-90 evaluation and certification for full entropy when conditioned cryptographically in ratio 2:1 with 128-bit output blocks.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements > NIST SP 800-90B / FIPS 140-3 Requirements", + "line_range": [ + 3735, + 3739 + ] + }, + { + "text": "Even though the requirement is defined in terms of 128-bit full entropy blocks, we recommend 256-bit security.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements > NIST SP 800-90B / FIPS 140-3 Requirements", + "line_range": [ + 3741, + 3743 + ] + }, + { + "text": "This can be accomplished by using at least 512 `entropy` bits to initialize a DRBG that has 256-bit security.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements > NIST SP 800-90B / FIPS 140-3 Requirements", + "line_range": [ + 3741, + 3743 + ] + }, + { + "text": "For alternative Common Criteria certification (or self-certification), AIS 31 PTG.2 class cite:[KiSc11] (Sect. 4.3.) required hardware components and mechanisms must be implemented.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements > BSI AIS-31 PTG.2 / Common Criteria Requirements", + "line_range": [ + 3748, + 3755 + ] + }, + { + "text": "In addition to AIS-31 PTG.2 randomness requirements (Shannon entropy rate of 0.997 as evaluated in that standard), the overall min-entropy requirement of remains, as discussed in .", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements > BSI AIS-31 PTG.2 / Common Criteria Requirements", + "line_range": [ + 3748, + 3755 + ] + }, + { + "text": "Note that 800-90B min-entropy can be significantly lower than AIS-31 Shannon entropy.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements > BSI AIS-31 PTG.2 / Common Criteria Requirements", + "line_range": [ + 3748, + 3755 + ] + }, + { + "text": "These two metrics should not be equated or confused with each other.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements > BSI AIS-31 PTG.2 / Common Criteria Requirements", + "line_range": [ + 3748, + 3755 + ] + }, + { + "text": "NOTE: A virtual source is not an ISA compliance requirement.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements > Virtual Sources: Security Requirement", + "line_range": [ + 3761, + 3763 + ] + }, + { + "text": "It is defined for the benefit of the RISC-V security ecosystem so that virtual systems may have a consistent level of security.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements > Virtual Sources: Security Requirement", + "line_range": [ + 3761, + 3763 + ] + }, + { + "text": "A virtual source is not a physical entropy source but provides additional protection against covert channels, depletion attacks, and host identification in operating environments that can not be entirely trusted with direct access to a hardware resource.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements > Virtual Sources: Security Requirement", + "line_range": [ + 3765, + 3770 + ] + }, + { + "text": "Despite limited trust, implementers should try to guarantee that even such environments have sufficient entropy available for secure cryptographic operations.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements > Virtual Sources: Security Requirement", + "line_range": [ + 3765, + 3770 + ] + }, + { + "text": "A virtual source traps access to the `seed` CSR, emulates it, or otherwise implements it, possibly without direct access to a physical entropy source.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements > Virtual Sources: Security Requirement", + "line_range": [ + 3772, + 3777 + ] + }, + { + "text": "The output can be cryptographically secure pseudorandomness instead of real entropy, but must have at least 256-bit security, as defined below. A virtual source is intended especially for guest operating systems, sandboxes, emulators, and similar use cases.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements > Virtual Sources: Security Requirement", + "line_range": [ + 3772, + 3777 + ] + }, + { + "text": "As a technical definition, a random-distinguishing attack against the output should require computational resources comparable or greater than those required for exhaustive key search on a secure block cipher with a 256-bit key (e.g., AES 256).", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements > Virtual Sources: Security Requirement", + "line_range": [ + 3779, + 3785 + ] + }, + { + "text": "This applies to both classical and quantum computing models, but only classical information flows.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements > Virtual Sources: Security Requirement", + "line_range": [ + 3779, + 3785 + ] + }, + { + "text": "The virtual source security requirement maps to Post-Quantum Security Category 5 cite:[NI16].", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements > Virtual Sources: Security Requirement", + "line_range": [ + 3779, + 3785 + ] + }, + { + "text": "Any implementation of the `seed` CSR that limits the security strength shall not reduce it to less than 256 bits.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements > Virtual Sources: Security Requirement", + "line_range": [ + 3787, + 3789 + ] + }, + { + "text": "If the security level is under 256 bits, then the interface must not be available.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements > Virtual Sources: Security Requirement", + "line_range": [ + 3787, + 3789 + ] + }, + { + "text": "A virtual entropy source does not need to implement `WAIT` or `BIST` states.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements > Virtual Sources: Security Requirement", + "line_range": [ + 3791, + 3793 + ] + }, + { + "text": "It should fail (`DEAD`) if the host DRBG or entropy source fails and there is insufficient seeding material for the host DRBG.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Entropy Source Requirements > Virtual Sources: Security Requirement", + "line_range": [ + 3791, + 3793 + ] + }, + { + "text": "The Zkr extension adds the `SSEED` and `USEED` fields to the `mseccfg` CSR to control access to the `seed` CSR from U, S, or HS modes (see Privileged ISA specification).", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Access Control to `seed`", + "line_range": [ + 3799, + 3801 + ] + }, + { + "text": "Systems should implement carefully considered access control policies from lower privilege modes to physical entropy sources.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Access Control to `seed`", + "line_range": [ + 3803, + 3811 + ] + }, + { + "text": "The system can trap attempted access to `seed` and feed a less privileged client virtual entropy source data () instead of invoking an SP 800-90B () or PTG.2 () physical entropy source.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Access Control to `seed`", + "line_range": [ + 3803, + 3811 + ] + }, + { + "text": "Emulated `seed` data generation is made with an appropriately seeded, secure software DRBG.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Access Control to `seed`", + "line_range": [ + 3803, + 3811 + ] + }, + { + "text": "See for security considerations related to direct access to entropy sources.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Access Control to `seed`", + "line_range": [ + 3803, + 3811 + ] + }, + { + "text": "Implementations may implement `mseccfg` such that `[s,u]seed` is a read-only constant value `0`.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Access Control to `seed`", + "line_range": [ + 3813, + 3816 + ] + }, + { + "text": "Software may discover if access to the `seed` CSR can be enabled in U and S mode by writing a `1` to `[s,u]seed` and reading back the result.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source > Access Control to `seed`", + "line_range": [ + 3813, + 3816 + ] + }, + { + "text": "The Zkt extension attests that the machine has data-independent execution time for a safe subset of instructions.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt", + "line_range": [ + 3822, + 3824 + ] + }, + { + "text": "This property is commonly called \"constant-time\" although should not be taken with that literal meaning.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt", + "line_range": [ + 3822, + 3824 + ] + }, + { + "text": "All currently defined cryptographic instructions (Zk* and Zbk* extensions) are on this list, together with a set of relevant supporting instructions from I, M, C, and B extensions.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt", + "line_range": [ + 3826, + 3828 + ] + }, + { + "text": ".Note to software developers [NOTE,caption=\"SH\"] Failure to prevent leakage of sensitive parameters via the direct timing channel is considered a serious security vulnerability and will typically result in a CERT CVE security advisory.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt", + "line_range": [ + 3830, + 3836 + ] + }, + { + "text": "An \"ISA contract\" is made between a programmer and the RISC-V implementation that Zkt instructions do not leak information about processed secret data (plaintext, keying information, or other \"sensitive security parameters\" -- FIPS 140-3 term) through differences in execution latency.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt > Scope and Goal", + "line_range": [ + 3841, + 3846 + ] + }, + { + "text": "Zkt does not define a set of instructions available in the core; it just restricts the behaviour of certain instructions if those are implemented.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt > Scope and Goal", + "line_range": [ + 3841, + 3846 + ] + }, + { + "text": "Currently, the scope of this chapter is within scalar RV32/RV64 processors.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt > Scope and Goal", + "line_range": [ + 3848, + 3851 + ] + }, + { + "text": "Vector cryptography instructions (and appropriate vector support instructions) will be added later, as will other security-related functions that wish to assert leakage-free execution latency properties.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt > Scope and Goal", + "line_range": [ + 3848, + 3851 + ] + }, + { + "text": "Loads, stores, conditional branches are excluded, along with a set of instructions that are rarely necessary to process secret data.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt > Scope and Goal", + "line_range": [ + 3853, + 3856 + ] + }, + { + "text": "Also excluded are instructions for which workarounds exist in standard cryptographic middleware due to the limitations of other ISA processors.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt > Scope and Goal", + "line_range": [ + 3853, + 3856 + ] + }, + { + "text": "The stated goal is that OpenSSL, BoringSSL (Android), the Linux Kernel, and similar trusted software will not have directly observable timing side channels when compiled and running on a Zkt-enabled RISC-V target.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt > Scope and Goal", + "line_range": [ + 3858, + 3862 + ] + }, + { + "text": "The Zkt extension explicitly states many of the common latency assumptions made by cryptography developers.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt > Scope and Goal", + "line_range": [ + 3858, + 3862 + ] + }, + { + "text": "Vendors do not have to implement all of the list's instructions to be Zkt compliant; however, if they claim to have Zkt and implement any of the listed instructions, it must have data-independent latency.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt > Scope and Goal", + "line_range": [ + 3864, + 3865 + ] + }, + { + "text": "For example, many simple RV32I and RV64I cores (without Multiply, Compressed, Bitmanip, or Cryptographic extensions) are technically compliant with Zkt. A constant-time AES can be implemented on them using \"bit-slice\" techniques, but it will be excruciatingly slow when compared to implementation with AES instructions.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt > Scope and Goal", + "line_range": [ + 3867, + 3873 + ] + }, + { + "text": "There are no guarantees that even a bit-sliced cipher implementation (largely based on boolean logic instructions) is secure on a core without Zkt attestation.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt > Scope and Goal", + "line_range": [ + 3867, + 3873 + ] + }, + { + "text": "Out-of-order implementations adhering to Zkt are still free to fuse, crack, change or even ignore sequences of instructions, so long as the optimisations are applied deterministically, and not based on operand data.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt > Scope and Goal", + "line_range": [ + 3875, + 3879 + ] + }, + { + "text": "The guiding principle should be that no information about the data being operated on should be leaked based on the execution latency.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt > Scope and Goal", + "line_range": [ + 3875, + 3879 + ] + }, + { + "text": ".Note to software developers [WARNING,caption=\"SH\"] Programming techniques can only mitigate leakage directly caused by arithmetic, caches, and branches.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt > Scope and Goal", + "line_range": [ + 3881, + 3889 + ] + }, + { + "text": "Other ISAs have had micro-architectural issues such as Spectre, Meltdown, Speculative Store Bypass, Rogue System Register Read, Lazy FP State Restore, Bounds Check Bypass Store, TLBleed, and L1TF/Foreshadow, etc.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt > Scope and Goal", + "line_range": [ + 3881, + 3889 + ] + }, + { + "text": "See e.g. link:https://github.com/nsacyber/Hardware-and-Firmware-Security-Guidance[NSA Hardware and Firmware Security Guidance]", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt > Scope and Goal", + "line_range": [ + 3881, + 3889 + ] + }, + { + "text": "It is not within the remit of this proposal to mitigate these micro-architectural leakages.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt > Scope and Goal", + "line_range": [ + 3891, + 3893 + ] + }, + { + "text": "Timing attacks are much more powerful than was realised before the 2010s, which has led to a significant mitigation effort in current cryptographic code-bases. * Cryptography developers use static and dynamic security testing tools to trace the handling of secret information and detect occasions where it influences a branch or is used for a table lookup. * Architectural testing for Zkt can be pragmatic and semi-formal; security by design against basic timing attacks can usually be achieved via conscious implementation (of relevant iterative multi-cycle instructions or instructions composed of micro-ops) in way that avoids data-dependent latency. * Laboratory testing may utilize statistical timing attack leakage analysis techniques such as those described in ISO/IEC 17825 cite:[IS16]. * Binary executables should not contain secrets in the instruction encodings (Kerckhoffs's principle), so instruction timing may leak information about immediates, ordering of input registers, etc.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt > Background", + "line_range": [ + 3897, + 3924 + ] + }, + { + "text": "There may be an exception to this in systems where a binary loader modifies the executable for purposes of relocation -- and it is desirable to keep the execution location (PC) secret.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt > Background", + "line_range": [ + 3897, + 3924 + ] + }, + { + "text": "This is why instructions such as LUI, AUIPC, and ADDI are on the list. * The rules used by audit tools are relatively simple to understand.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt > Background", + "line_range": [ + 3897, + 3924 + ] + }, + { + "text": "Very briefly; we call the plaintext, secret keys, expanded keys, nonces, and other such variables \"secrets\". A secret variable (arithmetically) modifying any other variable/register turns that into a secret too.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt > Background", + "line_range": [ + 3897, + 3924 + ] + }, + { + "text": "If a secret ends up in address calculation affecting a load or store, that is a violation.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt > Background", + "line_range": [ + 3897, + 3924 + ] + }, + { + "text": "If a secret affects a branch's condition, that is also a violation. A secret variable location or register becomes a non-secret via specific zeroization/sanitisation or by being declared ciphertext (or otherwise no-longer-secret information).", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt > Background", + "line_range": [ + 3897, + 3924 + ] + }, + { + "text": "In essence, secrets can only \"touch\" instructions on the Zkt list while they are secrets.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt > Background", + "line_range": [ + 3897, + 3924 + ] + }, + { + "text": "HINT instruction forms (typically encodings with rd=`x0`) are excluded from the data-independent time requirement. * Floating point (F, D, Q, L extensions) are currently excluded from the constant-time requirement as they have very few applications in standardised cryptography.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt > Specific Instruction Rationale", + "line_range": [ + 3928, + 3940 + ] + }, + { + "text": "We may consider adding floating point add, sub, multiply as a constant time requirement for some floating point extension in case a specific algorithm (such as the PQC Signature algorithm Falcon) becomes critical. * Cryptographers typically assume division to be variable-time (while multiplication is constant time) and implement their Montgomery reduction routines with that assumption. * Zicsr, Zifencei are excluded. * Some instructions are on the list simply because we see no harm in including them in testing scope.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt > Specific Instruction Rationale", + "line_range": [ + 3928, + 3940 + ] + }, + { + "text": "For background information on secure programming \"models\", see:", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt > Programming Information", + "line_range": [ + 3945, + 3945 + ] + }, + { + "text": "Thomas Pornin: \"Why Constant-Time Crypto?\" (A great introduction to timing assumptions.) https://www.bearssl.org/constanttime.html * Jean-Philippe Aumasson: \"Guidelines for low-level cryptography software.\" (A list of recommendations.) https://github.com/veorq/cryptocoding * Peter Schwabe: \"Timing Attacks and Countermeasures.\" (Lecture slides -- nice references.) https://summerschool-croatia.cs.ru.nl/2016/slides/PeterSchwabe.pdf * Adam Langley: \"ctgrind.\" (This is from 2010 but is still relevant.) https://www.imperialviolet.org/2010/04/01/ctgrind.html * Kris Kwiatkowski: \"Constant-time code verification with Memory Sanitizer.\" https://www.amongbytes.com/post/20210709-testing-constant-time/ * For early examples of timing attack vulnerabilities, see https://www.kb.cert.org/vuls/id/997481 and related academic papers.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt > Programming Information", + "line_range": [ + 3947, + 3958 + ] + }, + { + "text": "The following instructions are included in the `Zkt` subset They are listed here grouped by their original parent extension.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt > Zkt listings", + "line_range": [ + 3964, + 3965 + ] + }, + { + "text": ".Note to implementers [NOTE, caption=\"SH\"] You do not need to implement all of these instructions to implement `Zkt`.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt > Zkt listings", + "line_range": [ + 3967, + 3973 + ] + }, + { + "text": "Rather, every one of these instructions that the core does implement must adhere to the requirements of `Zkt`.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt > Zkt listings", + "line_range": [ + 3967, + 3973 + ] + }, + { + "text": "Only basic arithmetic and `slt*` (for carry computations) are included.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt > Zkt listings > RVI (Base Instruction Set)", + "line_range": [ + 3977, + 3979 + ] + }, + { + "text": "The data-independent timing requirement does not apply to HINT instruction encoding forms of these instructions.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt > Zkt listings > RVI (Base Instruction Set)", + "line_range": [ + 3977, + 3979 + ] + }, + { + "text": "| {check} | {check} | lui rd, imm | {check} | {check} | auipc rd, imm | {check} | {check} | addi rd, rs1, imm | {check} | {check} | slti rd, rs1, imm | {check} | {check} | sltiu rd, rs1, imm | {check} | {check} | xori rd, rs1, imm | {check} | {check} | ori rd, rs1, imm | {check} | {check} | andi rd, rs1, imm | {check} | {check} | slli rd, rs1, imm | {check} | {check} | srli rd, rs1, imm | {check} | {check} | srai rd, rs1, imm | {check} | {check} | add rd, rs1, rs2 | {check} | {check} | sub rd, rs1, rs2 | {check} | {check} | sll rd, rs1, rs2 | {check} | {check} | slt rd, rs1, rs2 | {check} | {check} | sltu rd, rs1, rs2 | {check} | {check} | xor rd, rs1, rs2 | {check} | {check} | srl rd, rs1, rs2 | {check} | {check} | sra rd, rs1, rs2 | {check} | {check} | or rd, rs1, rs2 | {check} | {check} | and rd, rs1, rs2 | | {check} | addiw rd, rs1, imm | | {check} | slliw rd, rs1, imm | | {check} | srliw rd, rs1, imm | | {check} | sraiw rd, rs1, imm | | {check} | addw rd, rs1, rs2 | | {check} | subw rd, rs1, rs2 | | {check} | sllw rd, rs1, rs2 | | {check} | srlw rd, rs1, rs2 | | {check} | sraw rd, rs1, rs2 |", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt > Zkt listings > RVI (Base Instruction Set)", + "line_range": [ + 3987, + 4017 + ] + }, + { + "text": "All instructions are included.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt > Zkt listings > Zicond (Conditional Zero)", + "line_range": [ + 4021, + 4021 + ] + }, + { + "text": "| {check} | {check} | czero.eqz rd, rs1, rs2 | {check} | {check} | czero.nez rd, rs1, rs2 |", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt > Zkt listings > Zicond (Conditional Zero)", + "line_range": [ + 4029, + 4031 + ] + }, + { + "text": "Multiplication is included; division and remaindering excluded.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt > Zkt listings > RVM (Multiply)", + "line_range": [ + 4035, + 4035 + ] + }, + { + "text": "| {check} | {check} | mul rd, rs1, rs2 | {check} | {check} | mulh rd, rs1, rs2 | {check} | {check} | mulhsu rd, rs1, rs2 | {check} | {check} | mulhu rd, rs1, rs2 | | {check} | mulw rd, rs1, rs2 |", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt > Zkt listings > RVM (Multiply)", + "line_range": [ + 4043, + 4048 + ] + }, + { + "text": "| {check} | {check} | c.nop | {check} | {check} | c.addi | | {check} | c.addiw | {check} | {check} | c.lui | {check} | {check} | c.srli | {check} | {check} | c.srai | {check} | {check} | c.andi | {check} | {check} | c.sub | {check} | {check} | c.xor | {check} | {check} | c.or | {check} | {check} | c.and | | {check} | c.subw | | {check} | c.addw | {check} | {check} | c.slli | {check} | {check} | c.mv | {check} | {check} | c.add |", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt > Zkt listings > ext:zca[] (Compressed)", + "line_range": [ + 4060, + 4076 + ] + }, + { + "text": "These instructions are compressed versions of I and M instructions that are included in Zkt.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt > Zkt listings > Zcb Extension", + "line_range": [ + 4080, + 4081 + ] + }, + { + "text": "| |RV32 |RV64 |Mnemonic |Instruction", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt > Zkt listings > Zcb Extension", + "line_range": [ + 4083, + 4088 + ] + }, + { + "text": "| {check} | {check} | c.mul | | {check} | {check} | c.not | | {check} | {check} | c.zext.b | |", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt > Zkt listings > Zcb Extension", + "line_range": [ + 4090, + 4093 + ] + }, + { + "text": "All K-specific instructions are included.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt > Zkt listings > RVK (Scalar Cryptography)", + "line_range": [ + 4097, + 4100 + ] + }, + { + "text": "Additionally, `seed` CSR latency should be independent of `ES16` state output `entropy` bits, as that is a sensitive security parameter.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt > Zkt listings > RVK (Scalar Cryptography)", + "line_range": [ + 4097, + 4100 + ] + }, + { + "text": "| |RV32 |RV64 |Mnemonic |Instruction", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt > Zkt listings > RVK (Scalar Cryptography)", + "line_range": [ + 4102, + 4107 + ] + }, + { + "text": "| {check} | | aes32dsi | | {check} | | aes32dsmi | | {check} | | aes32esi | | {check} | | aes32esmi | | | {check} | aes64ds | | | {check} | aes64dsm | | | {check} | aes64es | | | {check} | aes64esm | | | {check} | aes64im | | | {check} | aes64ks1i | | | {check} | aes64ks2 | | {check} | {check} | sha256sig0 | | {check} | {check} | sha256sig1 | | {check} | {check} | sha256sum0 | | {check} | {check} | sha256sum1 | | {check} | | sha512sig0h | | {check} | | sha512sig0l | | {check} | | sha512sig1h | | {check} | | sha512sig1l | | {check} | | sha512sum0r | | {check} | | sha512sum1r | | | {check} | sha512sig0 | | | {check} | sha512sig1 | | | {check} | sha512sum0 | | | {check} | sha512sum1 | | {check} | {check} | sm3p0 | | {check} | {check} | sm3p1 | | {check} | {check} | sm4ed | | {check} | {check} | sm4ks | |", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt > Zkt listings > RVK (Scalar Cryptography)", + "line_range": [ + 4109, + 4138 + ] + }, + { + "text": "The , and extensions are included in their entirety.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt > Zkt listings > RVB (Bitmanip)", + "line_range": [ + 4143, + 4143 + ] + }, + { + "text": "| |RV32 |RV64 |Mnemonic |Instruction", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt > Zkt listings > RVB (Bitmanip)", + "line_range": [ + 4145, + 4150 + ] + }, + { + "text": "| {check} | {check} | clmul | | {check} | {check} | clmulh | | {check} | {check} | xperm4 | | {check} | {check} | xperm8 | | {check} | {check} | ror | | {check} | {check} | rol | | {check} | {check} | rori | | | {check} | rorw | | | {check} | rolw | | | {check} | roriw | | {check} | {check} | andn | | {check} | {check} | orn | | {check} | {check} | xnor | | {check} | {check} | pack | | {check} | {check} | packh | | | {check} | packw | | {check} | {check} | brev8 | | {check} | {check} | rev8 | | {check} | | zip | | {check} | | unzip | |", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Data Independent Execution Latency Subset: Zkt > Zkt listings > RVB (Bitmanip)", + "line_range": [ + 4152, + 4172 + ] + }, + { + "text": "This section contains various rationale, design notes and usage recommendations for the instructions in the scalar cryptography extension.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instruction Rationale", + "line_range": [ + 4177, + 4180 + ] + }, + { + "text": "It also tries to record how the designs of instructions were derived, or where they were contributed from.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instruction Rationale", + "line_range": [ + 4177, + 4180 + ] + }, + { + "text": "The 32-bit instructions were derived from work in cite:[MJS:LWAES:20] and contributed to the RISC-V cryptography extension.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instruction Rationale > AES Instructions", + "line_range": [ + 4184, + 4187 + ] + }, + { + "text": "The 64-bit instructions were developed collaboratively by task group members on our mailing list.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instruction Rationale > AES Instructions", + "line_range": [ + 4184, + 4187 + ] + }, + { + "text": "Supporting material, including rationale and a design space exploration for all of the AES instructions in the specification can be found in the paper \"link:https://doi.org/10.46586/tches.v2021.i1.109-136[The design of scalar AES Instruction Set Extensions for RISC-V]\" cite:[MNPSW:20].", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instruction Rationale > AES Instructions", + "line_range": [ + 4189, + 4191 + ] + }, + { + "text": "These instructions were developed based on academic work at the University of Bristol as part of the XCrypto project cite:[MPP:19], and contributed to the RISC-V cryptography extension.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instruction Rationale > SHA2 Instructions", + "line_range": [ + 4196, + 4198 + ] + }, + { + "text": "The RV32 SHA2-512 instructions were based on this work, and developed in cite:[MJS:LWSHA:20], before being contributed in the same way.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instruction Rationale > SHA2 Instructions", + "line_range": [ + 4200, + 4201 + ] + }, + { + "text": "The SM4 instructions were derived from work in cite:[MJS:LWAES:20], and are hence very similar to the RV32 AES instructions.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instruction Rationale > SM3 and SM4 Instructions", + "line_range": [ + 4205, + 4206 + ] + }, + { + "text": "The SM3 instructions were inspired by the SHA2 instructions, and based on development work done in cite:[MJS:LWSHA:20], before being contributed to the RISC-V cryptography extension.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instruction Rationale > SM3 and SM4 Instructions", + "line_range": [ + 4208, + 4210 + ] + }, + { + "text": "Many of the primitive operations used in symmetric key cryptography and cryptographic hash functions are well supported by the RISC-V Bitmanip extensions (see ).", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instruction Rationale > Bitmanip Instructions for Cryptography", + "line_range": [ + 4215, + 4217 + ] + }, + { + "text": "NOTE: This section repeats much of the information in , and , but includes more rationale.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instruction Rationale > Bitmanip Instructions for Cryptography", + "line_range": [ + 4219, + 4224 + ] + }, + { + "text": "We proposed that the scalar cryptographic extension reuse a subset of the instructions from the Bitmanip extensions `Zb[abc]` directly.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instruction Rationale > Bitmanip Instructions for Cryptography", + "line_range": [ + 4226, + 4236 + ] + }, + { + "text": "Specifically, this would mean that a core implementing either the scalar cryptographic extensions, or the `Zb[abc]`, or both, would be required to implement these instructions.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instruction Rationale > Bitmanip Instructions for Cryptography", + "line_range": [ + 4226, + 4236 + ] + }, + { + "text": "---- RV32, RV64: RV64 only: ror rd, rs1, rs2 rorw rd, rs1, rs2 rol rd, rs1, rs2 rolw rd, rs1, rs2 rori rd, rs1, imm roriw rd, rs1, imm ----", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instruction Rationale > Bitmanip Instructions for Cryptography > Rotations", + "line_range": [ + 4240, + 4245 + ] + }, + { + "text": "See for details of these instructions.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instruction Rationale > Bitmanip Instructions for Cryptography > Rotations", + "line_range": [ + 4247, + 4247 + ] + }, + { + "text": ".Notes to software developers [NOTE,caption=\"SH\"] Standard bitwise rotation is a primitive operation in many block ciphers and hash functions; it features particularly in the ARX (Add, Rotate, Xor) class of block ciphers and stream ciphers.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instruction Rationale > Bitmanip Instructions for Cryptography > Rotations", + "line_range": [ + 4249, + 4254 + ] + }, + { + "text": "Algorithms making use of 32-bit rotations: SHA256, AES (Shift Rows), ChaCha20, SM3. * Algorithms making use of 64-bit rotations: SHA512, SHA3.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instruction Rationale > Bitmanip Instructions for Cryptography > Rotations", + "line_range": [ + 4256, + 4260 + ] + }, + { + "text": "---- RV32, RV64: brev8 rd, rs1 rev8 rd, rs1 ----", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instruction Rationale > Bitmanip Instructions for Cryptography > Bit & Byte Permutations", + "line_range": [ + 4264, + 4268 + ] + }, + { + "text": "See for details of these instructions.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instruction Rationale > Bitmanip Instructions for Cryptography > Bit & Byte Permutations", + "line_range": [ + 4270, + 4270 + ] + }, + { + "text": ".Notes to software developers [NOTE,caption=\"SH\"] Reversing bytes in words is very common in cryptography when setting a standard endianness for input and output data.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instruction Rationale > Bitmanip Instructions for Cryptography > Bit & Byte Permutations", + "line_range": [ + 4272, + 4279 + ] + }, + { + "text": "Bit reversal within bytes is used for implementing the GHASH component of Galois/Counter Mode (GCM) cite:[nist:gcm].", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instruction Rationale > Bitmanip Instructions for Cryptography > Bit & Byte Permutations", + "line_range": [ + 4272, + 4279 + ] + }, + { + "text": "---- RV32: zip rd, rs1 unzip rd, rs1 ----", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instruction Rationale > Bitmanip Instructions for Cryptography > Bit & Byte Permutations", + "line_range": [ + 4281, + 4285 + ] + }, + { + "text": "See for details of these instructions.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instruction Rationale > Bitmanip Instructions for Cryptography > Bit & Byte Permutations", + "line_range": [ + 4287, + 4287 + ] + }, + { + "text": ".Notes to software developers [NOTE,caption=\"SH\"] These instructions perform a bit-interleave (or de-interleave) operation, and are useful for implementing the 64-bit rotations in the SHA3 cite:[nist:fips:202] algorithm on a 32-bit architecture.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instruction Rationale > Bitmanip Instructions for Cryptography > Bit & Byte Permutations", + "line_range": [ + 4289, + 4298 + ] + }, + { + "text": "On RV64, the relevant operations in SHA3 can be done natively using rotation instructions, so `zip` and `unzip` are not required.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instruction Rationale > Bitmanip Instructions for Cryptography > Bit & Byte Permutations", + "line_range": [ + 4289, + 4298 + ] + }, + { + "text": "---- RV32, RV64: clmul rd, rs1, rs2 clmulh rd, rs1, rs2 ----", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instruction Rationale > Bitmanip Instructions for Cryptography > Carry-less Multiply", + "line_range": [ + 4302, + 4306 + ] + }, + { + "text": "See for details of these instructions.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instruction Rationale > Bitmanip Instructions for Cryptography > Carry-less Multiply", + "line_range": [ + 4308, + 4311 + ] + }, + { + "text": "See for additional implementation requirements for these instructions, related to data independent execution latency.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instruction Rationale > Bitmanip Instructions for Cryptography > Carry-less Multiply", + "line_range": [ + 4308, + 4311 + ] + }, + { + "text": ".Notes to software developers [NOTE,caption=\"SH\"] As is mentioned there, obvious cryptographic use-cases for carry-less multiply are for Galois Counter Mode (GCM) block cipher operations. GCM is recommended by NIST as a block cipher mode of operation cite:[nist:gcm], and is the only required mode for the TLS 1.3 protocol.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instruction Rationale > Bitmanip Instructions for Cryptography > Carry-less Multiply", + "line_range": [ + 4313, + 4321 + ] + }, + { + "text": "---- RV32, RV64: andn rd, rs1, rs2 orn rd, rs1, rs2 xnor rd, rs1, rs2 ----", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instruction Rationale > Bitmanip Instructions for Cryptography > Logic With Negate", + "line_range": [ + 4325, + 4330 + ] + }, + { + "text": "See for details of these instructions.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instruction Rationale > Bitmanip Instructions for Cryptography > Logic With Negate", + "line_range": [ + 4332, + 4336 + ] + }, + { + "text": "These instructions are useful inside hash functions, block ciphers and for implementing software based side-channel countermeasures like masking.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instruction Rationale > Bitmanip Instructions for Cryptography > Logic With Negate", + "line_range": [ + 4332, + 4336 + ] + }, + { + "text": "The `andn` instruction is also useful for constant time word-select in systems without the ternary Bitmanip `cmov` instruction.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instruction Rationale > Bitmanip Instructions for Cryptography > Logic With Negate", + "line_range": [ + 4332, + 4336 + ] + }, + { + "text": ".Notes to software developers [NOTE,caption=\"SH\"] In the context of Cryptography, these instructions are useful for: SHA3/Keccak Chi step, Bit-sliced function implementations, Software based power/EM side-channel countermeasures based on masking.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instruction Rationale > Bitmanip Instructions for Cryptography > Logic With Negate", + "line_range": [ + 4338, + 4345 + ] + }, + { + "text": "---- RV32, RV64: RV64: pack rd, rs1, rs2 packw rd, rs1, rs2 packh rd, rs1, rs2 ----", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instruction Rationale > Bitmanip Instructions for Cryptography > Packing", + "line_range": [ + 4349, + 4353 + ] + }, + { + "text": "See for details of these instructions.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instruction Rationale > Bitmanip Instructions for Cryptography > Packing", + "line_range": [ + 4355, + 4355 + ] + }, + { + "text": ".Notes to software developers [NOTE,caption=\"SH\"] The `pack*` instructions are useful for re-arranging halfwords within words, and generally getting data into the right shape prior to applying transforms.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instruction Rationale > Bitmanip Instructions for Cryptography > Packing", + "line_range": [ + 4357, + 4368 + ] + }, + { + "text": "This is particularly useful for cryptographic algorithms which pass inputs around as (potentially unaligned) byte strings, but can operate on words made out of those byte strings.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instruction Rationale > Bitmanip Instructions for Cryptography > Packing", + "line_range": [ + 4357, + 4368 + ] + }, + { + "text": "This occurs (for example) in AES when loading blocks and keys (which may not be word aligned) into registers to perform the round functions.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instruction Rationale > Bitmanip Instructions for Cryptography > Packing", + "line_range": [ + 4357, + 4368 + ] + }, + { + "text": "---- RV32, RV64: xperm4 rd, rs1, rs2 xperm8 rd, rs1, rs2 ----", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instruction Rationale > Bitmanip Instructions for Cryptography > Crossbar Permutation Instructions", + "line_range": [ + 4372, + 4376 + ] + }, + { + "text": "See for a complete description of these instructions.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instruction Rationale > Bitmanip Instructions for Cryptography > Crossbar Permutation Instructions", + "line_range": [ + 4378, + 4378 + ] + }, + { + "text": "The `xperm4` instruction operates on nibbles. `GPR[rs1]` contains a vector of `XLEN/4` 4-bit elements. `GPR[rs2]` contains a vector of `XLEN/4` 4-bit indexes.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instruction Rationale > Bitmanip Instructions for Cryptography > Crossbar Permutation Instructions", + "line_range": [ + 4380, + 4384 + ] + }, + { + "text": "The result is each element in `GPR[rs2]` replaced by the indexed element in `GPR[rs1]`, or zero if the index into `GPR[rs2]` is out of bounds.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instruction Rationale > Bitmanip Instructions for Cryptography > Crossbar Permutation Instructions", + "line_range": [ + 4380, + 4384 + ] + }, + { + "text": "The `xperm8` instruction operates on bytes. `GPR[rs1]` contains a vector of `XLEN/8` 8-bit elements. `GPR[rs2]` contains a vector of `XLEN/8` 8-bit indexes.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instruction Rationale > Bitmanip Instructions for Cryptography > Crossbar Permutation Instructions", + "line_range": [ + 4386, + 4390 + ] + }, + { + "text": "The result is each element in `GPR[rs2]` replaced by the indexed element in `GPR[rs1]`, or zero if the index into `GPR[rs2]` is out of bounds.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instruction Rationale > Bitmanip Instructions for Cryptography > Crossbar Permutation Instructions", + "line_range": [ + 4386, + 4390 + ] + }, + { + "text": ".Notes to software developers [NOTE,caption=\"SH\"] The instruction can be used to implement arbitrary bit permutations.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instruction Rationale > Bitmanip Instructions for Cryptography > Crossbar Permutation Instructions", + "line_range": [ + 4392, + 4399 + ] + }, + { + "text": "For cryptography, they can accelerate bit-sliced implementations, permutation layers of block ciphers, masking based countermeasures and SBox operations.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instruction Rationale > Bitmanip Instructions for Cryptography > Crossbar Permutation Instructions", + "line_range": [ + 4392, + 4399 + ] + }, + { + "text": "Lightweight block ciphers using 4-bit SBoxes include: PRESENT cite:[block:present], Rectangle cite:[block:rectangle], GIFT cite:[block:gift], Twine cite:[block:twine], Skinny, MANTIS cite:[block:skinny], Midori cite:[block:midori].", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instruction Rationale > Bitmanip Instructions for Cryptography > Crossbar Permutation Instructions", + "line_range": [ + 4401, + 4407 + ] + }, + { + "text": "National ciphers using 8-bit SBoxes include: Camellia cite:[block:camellia] (Japan), Aria cite:[block:aria] (Korea), AES cite:[nist:fips:197] (USA, Belgium), SM4 cite:[gbt:sm4] (China) Kuznyechik (Russia).", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instruction Rationale > Bitmanip Instructions for Cryptography > Crossbar Permutation Instructions", + "line_range": [ + 4409, + 4414 + ] + }, + { + "text": "All of these SBoxes can be implemented efficiently, in constant time, using the `xperm8` instruction footnote:l[link:http://svn.clairexen.net/handicraft/2020/lut4perm/demo02.cc[]].", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instruction Rationale > Bitmanip Instructions for Cryptography > Crossbar Permutation Instructions", + "line_range": [ + 4416, + 4421 + ] + }, + { + "text": "Note that this technique is also suitable for masking based side-channel countermeasures.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Instruction Rationale > Bitmanip Instructions for Cryptography > Crossbar Permutation Instructions", + "line_range": [ + 4416, + 4421 + ] + }, + { + "text": "This *non-normative* appendix focuses on the rationale, security, self-certification, and implementation aspects of entropy sources.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations", + "line_range": [ + 4427, + 4430 + ] + }, + { + "text": "Hence we also discuss non-ISA system features that may be needed for cryptographic standards compliance and security testing.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations", + "line_range": [ + 4427, + 4430 + ] + }, + { + "text": "The security of cryptographic systems is based on secret bits and keys.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Checklists for Design and Self-Certification", + "line_range": [ + 4434, + 4437 + ] + }, + { + "text": "These bits need to be random and originate from cryptographically secure Random Bit Generators (RBGs).", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Checklists for Design and Self-Certification", + "line_range": [ + 4434, + 4437 + ] + }, + { + "text": "An Entropy Source (ES) is required to construct secure RBGs.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Checklists for Design and Self-Certification", + "line_range": [ + 4434, + 4437 + ] + }, + { + "text": "While entropy source implementations do not have to be certified designs, RISC-V expects that they behave in a compatible manner and do not create unnecessary security risks to users.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Checklists for Design and Self-Certification", + "line_range": [ + 4439, + 4442 + ] + }, + { + "text": "Self-evaluation and testing following appropriate security standards is usually needed to achieve this.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Checklists for Design and Self-Certification", + "line_range": [ + 4439, + 4442 + ] + }, + { + "text": "*ISA Architectural Tests.* Verify, to the extent possible, that RISC-V ISA requirements in this specification are correctly implemented.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Checklists for Design and Self-Certification", + "line_range": [ + 4444, + 4482 + ] + }, + { + "text": "This includes the state transitions ( and ), access control (), and that `seed` ES16 `entropy` words can only be read destructively.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Checklists for Design and Self-Certification", + "line_range": [ + 4444, + 4482 + ] + }, + { + "text": "The scope of RISC-V ISA architectural tests are those behaviors that are independent of the physical entropy source details. A smoke test ES module may be helpful in design phase. * *Technical justification for entropy.* This may take the form of a stochastic model or a heuristic argument that explains why the noise source output is from a random, rather than pseudorandom (deterministic) process, and is not easily predictable or externally observable. A complete physical model is not necessary; research literature can be cited.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Checklists for Design and Self-Certification", + "line_range": [ + 4444, + 4482 + ] + }, + { + "text": "For example, one can show that a good ring oscillator noise derives an amount of physical entropy from local, spontaneously occurring Johnson-Nyquist thermal noise cite:[Sa21], and is therefore not merely \"random-looking\". * *Entropy Source Design Review.* An entropy source is more than a noise source, and must have features such as health tests (), a conditioner (), and a security boundary with clearly defined interfaces.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Checklists for Design and Self-Certification", + "line_range": [ + 4444, + 4482 + ] + }, + { + "text": "One may tabulate the SHALL statements of SP 800-90B cite:[TuBaKe:18], FIPS 140-3 Implementation Guidance cite:[NICC21], AIS-31 cite:[KiSc11] or other standards being used.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Checklists for Design and Self-Certification", + "line_range": [ + 4444, + 4482 + ] + }, + { + "text": "Official and non-official checklist tables are available: https://github.com/usnistgov/90B-Shall-Statements * *Experimental Tests.* The raw noise source is subjected to entropy estimation as defined in NIST 800-90B, Section 3 cite:[TuBaKe:18].", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Checklists for Design and Self-Certification", + "line_range": [ + 4444, + 4482 + ] + }, + { + "text": "The interface described in can used be to record datasets for this purpose.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Checklists for Design and Self-Certification", + "line_range": [ + 4444, + 4482 + ] + }, + { + "text": "One also needs to show experimentally that the conditioner and health test components work appropriately to meet the ES16 output entropy requirements of .", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Checklists for Design and Self-Certification", + "line_range": [ + 4444, + 4482 + ] + }, + { + "text": "For SP 800-90B, NIST has made a min-entropy estimation package freely available: https://github.com/usnistgov/SP800-90BEntropyAssessment * **Resilience.** Above physical engineering steps should consider the operational environment of the device, which may be unexpected or hostile (actively attempting to exploit vulnerabilities in the design).", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Checklists for Design and Self-Certification", + "line_range": [ + 4444, + 4482 + ] + }, + { + "text": "See for a discussion of various implementation options.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Checklists for Design and Self-Certification", + "line_range": [ + 4484, + 4485 + ] + }, + { + "text": "NOTE: It is one of the goals of the RISC-V Entropy Source specification that a standard 90B Entropy Source Module or AIS-31 RNG IP may be licensed from a third party and integrated with a RISC-V processor design.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Checklists for Design and Self-Certification", + "line_range": [ + 4487, + 4493 + ] + }, + { + "text": "Compared to older (FIPS 140-2) RNG and DRBG modules, an entropy source module may have a relatively small area (just a few thousand NAND2 gate equivalent). CMVP is introducing an \"Entropy Source Validation Scope\" which potentially allows 90B validations to be reused for different (FIPS 140-3) modules.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Checklists for Design and Self-Certification", + "line_range": [ + 4487, + 4493 + ] + }, + { + "text": "As a fundamental security function, the generation of random numbers is governed by numerous standards and technical evaluation methods, the main ones being FIPS 140-3 cite:[NI19,NICC21] required for U.S.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Standards and Terminology", + "line_range": [ + 4497, + 4501 + ] + }, + { + "text": "Federal use, and Common Criteria Methodology cite:[Cr17] used in high-security evaluations internationally.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Standards and Terminology", + "line_range": [ + 4497, + 4501 + ] + }, + { + "text": "Note that FIPS 140-3 is a significantly updated standard compared to its predecessor FIPS 140-2 and is only coming into use in the 2020s.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Standards and Terminology", + "line_range": [ + 4503, + 4504 + ] + }, + { + "text": "These standards set many of the technical requirements for the RISC-V entropy source design, and we use their terminology if possible.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Standards and Terminology", + "line_range": [ + 4506, + 4507 + ] + }, + { + "text": "image::esdataflow.svg[align=\"center\",scaledwidth=50%] The `seed` CSR provides an Entropy Source (ES) interface, not a stateful random number generator.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Standards and Terminology", + "line_range": [ + 4509, + 4517 + ] + }, + { + "text": "As a result, it can support arbitrary security levels.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Standards and Terminology", + "line_range": [ + 4509, + 4517 + ] + }, + { + "text": "Cryptographic (AES, SHA-2/3) ISA Extensions can be used to construct high-speed DRBGs that are seeded from the entropy source.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Standards and Terminology", + "line_range": [ + 4509, + 4517 + ] + }, + { + "text": "Entropy sources are built by sampling and processing data from a noise source ().", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Standards and Terminology > Entropy Source (ES)", + "line_range": [ + 4523, + 4528 + ] + }, + { + "text": "We will only consider physical sources of true randomness in this work.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Standards and Terminology > Entropy Source (ES)", + "line_range": [ + 4523, + 4528 + ] + }, + { + "text": "Since these are directly based on natural phenomena and are subject to environmental conditions (which may be adversarial), they require features that monitor the \"health\" and quality of those sources.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Standards and Terminology > Entropy Source (ES)", + "line_range": [ + 4523, + 4528 + ] + }, + { + "text": "The requirements for physical entropy sources are specified in NIST SP 800-90B cite:[TuBaKe:18] () for U.S.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Standards and Terminology > Entropy Source (ES)", + "line_range": [ + 4530, + 4536 + ] + }, + { + "text": "Federal FIPS 140-3 cite:[NI19] evaluations and in BSI AIS-31 cite:[KiSc01,KiSc11] () for high-security Common Criteria evaluations.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Standards and Terminology > Entropy Source (ES)", + "line_range": [ + 4530, + 4536 + ] + }, + { + "text": "There is some divergence in the types of health tests and entropy metrics mandated in these standards, and RISC-V enables support for both alternatives.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Standards and Terminology > Entropy Source (ES)", + "line_range": [ + 4530, + 4536 + ] + }, + { + "text": "Raw physical randomness (noise) sources are rarely statistically perfect, and some generate very large amounts of bits, which need to be \"debiased\" and reduced to a smaller number of bits.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Standards and Terminology > Conditioning: Cryptographic and Non-Cryptographic", + "line_range": [ + 4541, + 4547 + ] + }, + { + "text": "This process is called conditioning. A secure hash function is an example of a cryptographic conditioner.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Standards and Terminology > Conditioning: Cryptographic and Non-Cryptographic", + "line_range": [ + 4541, + 4547 + ] + }, + { + "text": "It is important to note that even though hashing may make any data look random, it does not increase its entropy content.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Standards and Terminology > Conditioning: Cryptographic and Non-Cryptographic", + "line_range": [ + 4541, + 4547 + ] + }, + { + "text": "Non-cryptographic conditioners and extractors such as von Neumann's \"debiased coin tossing\" cite:[Ne51] are easier to implement efficiently but may reduce entropy content (in individual bits removed) more than cryptographic hashes, which mix the input entropy very efficiently.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Standards and Terminology > Conditioning: Cryptographic and Non-Cryptographic", + "line_range": [ + 4549, + 4556 + ] + }, + { + "text": "However, they do not require cryptanalytic or computational hardness assumptions and are therefore inherently more future-proof.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Standards and Terminology > Conditioning: Cryptographic and Non-Cryptographic", + "line_range": [ + 4549, + 4556 + ] + }, + { + "text": "See for a more detailed discussion.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Standards and Terminology > Conditioning: Cryptographic and Non-Cryptographic", + "line_range": [ + 4549, + 4556 + ] + }, + { + "text": "Pseudorandom Number Generators (PRNGs) use deterministic mathematical formulas to create abundant random numbers from a smaller amount of \"seed\" randomness. PRNGs are also divided into cryptographic and non-cryptographic ones.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Standards and Terminology > Pseudorandom Number Generator (PRNG)", + "line_range": [ + 4561, + 4564 + ] + }, + { + "text": "Non-cryptographic PRNGs, such as LFSRs and the linear-congruential generators found in many programming libraries, may generate statistically satisfactory random numbers but must never be used for cryptographic keying.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Standards and Terminology > Pseudorandom Number Generator (PRNG)", + "line_range": [ + 4566, + 4573 + ] + }, + { + "text": "This is because they are not designed to resist cryptanalysis; it is usually possible to take some output and mathematically derive the \"seed\" or the internal state of the PRNG from it.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Standards and Terminology > Pseudorandom Number Generator (PRNG)", + "line_range": [ + 4566, + 4573 + ] + }, + { + "text": "This is a security problem since knowledge of the state allows the attacker to compute future or past outputs.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Standards and Terminology > Pseudorandom Number Generator (PRNG)", + "line_range": [ + 4566, + 4573 + ] + }, + { + "text": "Cryptographic PRNGs are also known as Deterministic Random Bit Generators (DRBGs), a term used by SP 800-90A cite:[BaKe15]. A strong cryptographic algorithm such as AES cite:[nist:fips:197] or SHA-2/3 cite:[nist:fips:202,nist:fips:180:4] is used to produce random bits from a seed.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Standards and Terminology > Deterministic Random Bit Generator (DRBG)", + "line_range": [ + 4578, + 4587 + ] + }, + { + "text": "The secret seed material is like a cryptographic key; determining the seed from the DRBG output is as hard as breaking AES or a strong hash function.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Standards and Terminology > Deterministic Random Bit Generator (DRBG)", + "line_range": [ + 4578, + 4587 + ] + }, + { + "text": "This also illustrates that the seed/key needs to be long enough and come from a trusted Entropy Source.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Standards and Terminology > Deterministic Random Bit Generator (DRBG)", + "line_range": [ + 4578, + 4587 + ] + }, + { + "text": "The DRBG should still be frequently refreshed (reseeded) for forward and backward security.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Standards and Terminology > Deterministic Random Bit Generator (DRBG)", + "line_range": [ + 4578, + 4587 + ] + }, + { + "text": "The interface was designed to be simple so that a vendor- and device-independent driver component (e.g., in Linux kernel, embedded firmware, or a cryptographic library) may use `seed` to generate truly random bits.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > The `seed` CSR", + "line_range": [ + 4595, + 4598 + ] + }, + { + "text": "An entropy source does not require a high-bandwidth interface; a single DRBG source initialization only requires 512 bits (256 bits of entropy), and DRBG output can be shared by any number of callers.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > The `seed` CSR", + "line_range": [ + 4600, + 4604 + ] + }, + { + "text": "Once initiated, a DRBG requires new entropy only to mitigate the risk of state compromise.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > The `seed` CSR", + "line_range": [ + 4600, + 4604 + ] + }, + { + "text": "From a security perspective, it is essential that the side effect of flushing the secret entropy bits occurs upon reading.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > The `seed` CSR", + "line_range": [ + 4606, + 4608 + ] + }, + { + "text": "Hence we mandate a write operation on this particular CSR.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > The `seed` CSR", + "line_range": [ + 4606, + 4608 + ] + }, + { + "text": "A blocking instruction may have been easier to use, but most users should be querying a (D)RBG instead of an entropy source.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > The `seed` CSR", + "line_range": [ + 4610, + 4615 + ] + }, + { + "text": "Without a polling-style mechanism, the entropy source could hang for thousands of cycles under some circumstances. A `wfi` or `pause` mechanism (at least potentially) allows energy-saving sleep on MCUs and context switching on higher-end CPUs.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > The `seed` CSR", + "line_range": [ + 4610, + 4615 + ] + }, + { + "text": "The reason for the particular `OPST = seed[31:0]` two-bit mechanism is to provide redundancy.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > The `seed` CSR", + "line_range": [ + 4617, + 4620 + ] + }, + { + "text": "The \"fault\" bit combinations `11` (`DEAD`) and `00` (`BIST`) are more likely for electrical reasons if feature discovery fails and the entropy source is actually not available.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > The `seed` CSR", + "line_range": [ + 4617, + 4620 + ] + }, + { + "text": "The 16-bit bandwidth was a compromise motivated by the desire to provide redundancy in the return value, some protection against potential Power/EM leakage (further alleviated by the 2:1 cryptographic conditioning discussed in ), and the desire to have all of the bits \"in the same place\" on both RV32 and RV64 architectures for programming convenience.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > The `seed` CSR", + "line_range": [ + 4622, + 4627 + ] + }, + { + "text": "SP 800-90C cite:[BaKeMc:25] states that each conditioned block of n bits is required to have n+64 bits of input entropy to attain full entropy.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > NIST SP 800-90B", + "line_range": [ + 4633, + 4643 + ] + }, + { + "text": "Hence NIST SP 800-90B cite:[TuBaKe:18] min-entropy assessment must guarantee at least 128 + 64 = 192 bits input entropy per 256-bit block (cite:[BaKeMc:25], Sections 4.1. and 4.3.2).", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > NIST SP 800-90B", + "line_range": [ + 4633, + 4643 + ] + }, + { + "text": "Only then a hashing of 16 * 16 = 256 bits from the entropy source will produce the desired 128 bits of full entropy.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > NIST SP 800-90B", + "line_range": [ + 4633, + 4643 + ] + }, + { + "text": "This follows from the specific requirements, threat model, and distinguishability proof contained in SP 800-90C cite:[BaKeMc:25], Appendix A.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > NIST SP 800-90B", + "line_range": [ + 4633, + 4643 + ] + }, + { + "text": "The implied min-entropy rate is 192/256=12/16=0.75.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > NIST SP 800-90B", + "line_range": [ + 4633, + 4643 + ] + }, + { + "text": "The expected Shannon entropy is much larger.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > NIST SP 800-90B", + "line_range": [ + 4633, + 4643 + ] + }, + { + "text": "In FIPS 140-3 / SP 800-90 classification, an RBG2(P) construction is a cryptographically secure RBG with continuous access to a physical entropy source (`seed`) and output generated by a fully seeded, secure DRBG.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > NIST SP 800-90B", + "line_range": [ + 4645, + 4650 + ] + }, + { + "text": "The entropy source can also be used to build RBG3 full entropy sources cite:[BaKeMc:25].", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > NIST SP 800-90B", + "line_range": [ + 4645, + 4650 + ] + }, + { + "text": "The concatenation of output words corresponds to the `Getentropybitstring` function.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > NIST SP 800-90B", + "line_range": [ + 4645, + 4650 + ] + }, + { + "text": "The 128-bit output block size was selected because that is the output size of the CBC-MAC conditioner specified in Appendix F of cite:[TuBaKe:18] and also the smallest key size we expect to see in applications.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > NIST SP 800-90B", + "line_range": [ + 4652, + 4654 + ] + }, + { + "text": "If NIST SP 800-90B certification is chosen, the entropy source should implement at least the health tests defined in Section 4.4 of cite:[TuBaKe:18]: the repetition count test and adaptive proportion test, or show that the same flaws will be detected by vendor-defined tests.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > NIST SP 800-90B", + "line_range": [ + 4656, + 4660 + ] + }, + { + "text": "PTG.2 is one of the security and functionality classes defined in BSI AIS 20/31 cite:[KiSc11].", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > BSI AIS-31", + "line_range": [ + 4666, + 4669 + ] + }, + { + "text": "The PTG.2 source requirements work as a building block for other types of BSI generators (e.g., DRBGs, or PTG.3 TRNG with appropriate software post-processing).", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > BSI AIS-31", + "line_range": [ + 4666, + 4669 + ] + }, + { + "text": "For validation purposes, the PTG.2 requirements may be mapped to security controls T1-3 () and the interface as follows:", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > BSI AIS-31", + "line_range": [ + 4671, + 4673 + ] + }, + { + "text": "P1 *[PTG.2.1]* Start-up tests map to T1 and reset-triggered (on-demand) `BIST` tests. * P2 *[PTG.2.2]* Continuous testing total failure maps to T2 and the `DEAD` state. * P3 *[PTG.2.3]* Online tests are continuous tests of T2 – entropy output is prevented in the `BIST` state. * P4 *[PTG.2.4]* Is related to the design of effective entropy source health tests, which we encourage. * P5 *[PTG.2.5]* Raw random sequence may be checked via the GetNoise interface (). * P6 *[PTG.2.6]* Test Procedure A cite:[KiSc11] (Sect 2.4.4.1) is a part of the evaluation process, and we suggest self-evaluation using these tests even if AIS-31 certification is not sought. * P7 *[PTG.2.7]* Average Shannon entropy of \"internal random bits\" exceeds 0.997.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > BSI AIS-31", + "line_range": [ + 4675, + 4689 + ] + }, + { + "text": "Note how P7 concerns Shannon entropy, not min-entropy as with NIST sources.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > BSI AIS-31", + "line_range": [ + 4691, + 4695 + ] + }, + { + "text": "Hence the min-entropy requirement needs to be also stated. PTG.2 modules built and certified to the AIS-31 standard can also meet the \"full entropy\" condition after 2:1 cryptographic conditioning, but not necessarily so.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > BSI AIS-31", + "line_range": [ + 4691, + 4695 + ] + }, + { + "text": "The technical validation process is somewhat different.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > BSI AIS-31", + "line_range": [ + 4691, + 4695 + ] + }, + { + "text": "All sources that are not direct physical sources (meeting the SP 800-90B or the AIS-31 PTG.2 requirements) need to meet the security requirements of virtual entropy sources.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > Virtual Sources", + "line_range": [ + 4701, + 4704 + ] + }, + { + "text": "It is assumed that a virtual entropy source is not a limiting, shared bandwidth resource (but a software DRBG).", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > Virtual Sources", + "line_range": [ + 4701, + 4704 + ] + }, + { + "text": "DRBGs can be used to feed other (virtual) DRBGs, but that does not increase the absolute amount of entropy in the system.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > Virtual Sources", + "line_range": [ + 4706, + 4712 + ] + }, + { + "text": "The entropy source must be able to support current and future security standards and applications.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > Virtual Sources", + "line_range": [ + 4706, + 4712 + ] + }, + { + "text": "The 256-bit requirement maps to \"Category 5\" of NIST Post-Quantum Cryptography (4.A.5 \"Security Strength Categories\" in cite:[NI16]) and TOP SECRET schemes in Suite B and the newer U.S.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > Virtual Sources", + "line_range": [ + 4706, + 4712 + ] + }, + { + "text": "Government CNSA Suite cite:[NS15].", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > Virtual Sources", + "line_range": [ + 4706, + 4712 + ] + }, + { + "text": "The ISA implementation and system design must try to ensure that the hardware-software interface minimizes avenues for adversarial information flow even if not explicitly forbidden in the specification.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > Security Considerations for Direct Hardware Access", + "line_range": [ + 4719, + 4721 + ] + }, + { + "text": "For security, virtualization requires both conditioning and DRBG processing of physical entropy output.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > Security Considerations for Direct Hardware Access", + "line_range": [ + 4723, + 4727 + ] + }, + { + "text": "It is recommended if a single physical entropy source is shared between multiple different virtual machines or if the guest OS is untrusted. A virtual entropy source is significantly more resistant to depletion attacks and also lessens the risk from covert channels.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > Security Considerations for Direct Hardware Access", + "line_range": [ + 4723, + 4727 + ] + }, + { + "text": "The direct `mseccfg.[s,u]seed` option allows one to draw a security boundary around a component in relation to Sensitive Security Parameter (SSP) flows, even if that component is not in M mode.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > Security Considerations for Direct Hardware Access", + "line_range": [ + 4729, + 4735 + ] + }, + { + "text": "This is helpful when implementing trusted enclaves.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > Security Considerations for Direct Hardware Access", + "line_range": [ + 4729, + 4735 + ] + }, + { + "text": "Such modules can enforce the entire key lifecycle from birth (in the entropy source) to death (zeroization) to occur without the key being passed across the boundary to external code.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > Security Considerations for Direct Hardware Access", + "line_range": [ + 4729, + 4735 + ] + }, + { + "text": "*Depletion.* Active polling may deny the entropy source to another simultaneously running consumer.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > Security Considerations for Direct Hardware Access", + "line_range": [ + 4737, + 4740 + ] + }, + { + "text": "This can (for example) delay the instantiation of that virtual machine if it requires entropy to initialize fully.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > Security Considerations for Direct Hardware Access", + "line_range": [ + 4737, + 4740 + ] + }, + { + "text": "*Covert Channels.* Direct access to a component such as the entropy source can be used to establish communication channels across security boundaries.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > Security Considerations for Direct Hardware Access", + "line_range": [ + 4742, + 4747 + ] + }, + { + "text": "Active polling from one consumer makes the resource unavailable WAIT instead of ES16 to another (which is polling infrequently).", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > Security Considerations for Direct Hardware Access", + "line_range": [ + 4742, + 4747 + ] + }, + { + "text": "Such interactions can be used to establish low-bandwidth channels.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > Security Considerations for Direct Hardware Access", + "line_range": [ + 4742, + 4747 + ] + }, + { + "text": "*Hardware Fingerprinting.* An entropy source (and its noise source circuits) may have a uniquely identifiable hardware \"signature.\" This can be harmless or even useful in some applications (as random sources may exhibit Physically Un-clonable Function (PUF) -like features) but highly undesirable in others (anonymized virtualized environments and enclaves). A DRBG masks such statistical features.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > Security Considerations for Direct Hardware Access", + "line_range": [ + 4749, + 4755 + ] + }, + { + "text": "*Side Channels.* Some of the most devastating practical attacks against real-life cryptosystems have used inconsequential-looking additional information, such as padding error messages cite:[BaFoKa:12] or timing information cite:[MoSuEi:20].", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > Security Considerations for Direct Hardware Access", + "line_range": [ + 4757, + 4761 + ] + }, + { + "text": "We urge implementers against creating unnecessary information flows via status or custom bits or to allow any other mechanism to disable or affect the entropy source output.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > Security Considerations for Direct Hardware Access", + "line_range": [ + 4763, + 4767 + ] + }, + { + "text": "All information flows and interaction mechanisms must be considered from an adversarial viewpoint: the fewer the better.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > Security Considerations for Direct Hardware Access", + "line_range": [ + 4763, + 4767 + ] + }, + { + "text": "As an example of side-channel analysis, we note that the entropy polling interface is typically not \"constant time.\" One needs to analyze what kind of information is revealed via the timing oracle; one way of doing it is to model `seed` as a rejection sampler.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > Security Considerations for Direct Hardware Access", + "line_range": [ + 4769, + 4776 + ] + }, + { + "text": "Such a timing oracle can reveal information about the noise source type and entropy source usage, but not about the random output `entropy` bits themselves.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > Security Considerations for Direct Hardware Access", + "line_range": [ + 4769, + 4776 + ] + }, + { + "text": "If it does, additional countermeasures are necessary.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Specific Rationale and Considerations > Security Considerations for Direct Hardware Access", + "line_range": [ + 4769, + 4776 + ] + }, + { + "text": "The primary purpose of a cryptographic entropy source is to produce secret keying material.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests", + "line_range": [ + 4781, + 4786 + ] + }, + { + "text": "In almost all cases, a hardware entropy source must implement appropriate security controls to guarantee unpredictability, prevent leakage, detect attacks, and deny adversarial control over the entropy output or ts generation mechanism.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests", + "line_range": [ + 4781, + 4786 + ] + }, + { + "text": "Explicit security controls are required for security testing and certification.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests", + "line_range": [ + 4781, + 4786 + ] + }, + { + "text": "Many of the security controls built into the device are called \"health checks.\" Health checks can take the form of integrity checks, start-up tests, and on-demand tests.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests", + "line_range": [ + 4788, + 4795 + ] + }, + { + "text": "These tests can be implemented in hardware or firmware, typically both.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests", + "line_range": [ + 4788, + 4795 + ] + }, + { + "text": "Several are mandated by standards such as NIST SP 800-90B cite:[NI19].", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests", + "line_range": [ + 4788, + 4795 + ] + }, + { + "text": "The choice of appropriate health tests depends on the certification target, system architecture, threat model, entropy source type, and other factors.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests", + "line_range": [ + 4788, + 4795 + ] + }, + { + "text": "Health checks are not intended for hardware diagnostics but for detecting security issues.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests", + "line_range": [ + 4797, + 4800 + ] + }, + { + "text": "Hence the default action in case of a failure should be aimed at damage control: Limiting further output and preventing weak crypto keys from being generated.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests", + "line_range": [ + 4797, + 4800 + ] + }, + { + "text": "We discuss three specific testing requirements T1-T3.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests", + "line_range": [ + 4802, + 4804 + ] + }, + { + "text": "The testing requirement follows from the definition of an Entropy Source; without it, the module is simply a noise source and can't be trusted to safely generate keying material.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests", + "line_range": [ + 4802, + 4804 + ] + }, + { + "text": "A sequence of simple tests is invoked via resetting, rebooting, or powering up the hardware (not an ISA signal).", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests > T1: On-demand testing", + "line_range": [ + 4808, + 4813 + ] + }, + { + "text": "The implementation will simply return `BIST` during the initial start-up self-test period; in any case, the driver must wait for them to finish before starting cryptographic operations.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests > T1: On-demand testing", + "line_range": [ + 4808, + 4813 + ] + }, + { + "text": "Upon failure, the entropy source will enter a no-output `DEAD` state.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests > T1: On-demand testing", + "line_range": [ + 4808, + 4813 + ] + }, + { + "text": "*Rationale.* Interaction with hardware self-test mechanisms from the software side should be minimal; the term \"on-demand\" does not mean that the end-user or application program should be able to invoke them in the field (the term is a throwback to an age of discrete, non-autonomous crypto devices with human operators).", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests > T1: On-demand testing", + "line_range": [ + 4815, + 4820 + ] + }, + { + "text": "If an error is detected in continuous tests or environmental sensors, the entropy source will enter a no-output state.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests > T2: Continuous checks", + "line_range": [ + 4824, + 4831 + ] + }, + { + "text": "We define that a non-critical alarm is signaled if the entropy source returns to `BIST` state from live (`WAIT` or `ES16`) states.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests > T2: Continuous checks", + "line_range": [ + 4824, + 4831 + ] + }, + { + "text": "Critical failures will result in `DEAD` state immediately. A hardware-based continuous testing mechanism must not make statistical information externally available, and it must be zeroized periodically or upon demand via reset, power-up, or similar signal.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests > T2: Continuous checks", + "line_range": [ + 4824, + 4831 + ] + }, + { + "text": "*Rationale.* Physical attacks can occur while the device is running.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests > T2: Continuous checks", + "line_range": [ + 4833, + 4838 + ] + }, + { + "text": "The design should avoid guiding such active attacks by revealing detailed status information.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests > T2: Continuous checks", + "line_range": [ + 4833, + 4838 + ] + }, + { + "text": "Upon detection of an attack, the default action should be aimed at damage control -- to prevent weak crypto keys from being generated.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests > T2: Continuous checks", + "line_range": [ + 4833, + 4838 + ] + }, + { + "text": "The statistical nature of some tests makes \"type-1\" false positives a possibility.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests > T2: Continuous checks", + "line_range": [ + 4840, + 4846 + ] + }, + { + "text": "There may also be requirements for signaling of non-fatal alarms; AIS 31 specifies \"noise alarms\" that can go off with non-negligible probability even if the device is functioning correctly; these can be signaled with `BIST`.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests > T2: Continuous checks", + "line_range": [ + 4840, + 4846 + ] + }, + { + "text": "There rarely is anything that can or should be done about a non-fatal alarm condition in an operator-free, autonomous system.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests > T2: Continuous checks", + "line_range": [ + 4840, + 4846 + ] + }, + { + "text": "The state of statistical runtime health checks (such as counters) is potentially correlated with some secret keying material, hence the zeroization requirement.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests > T2: Continuous checks", + "line_range": [ + 4848, + 4850 + ] + }, + { + "text": "Since the security of most cryptographic operations depends on the entropy source, a system-wide \"default deny\" security policy approach is appropriate for most entropy source failures. A hardware test failure should at least result in the `DEAD` state and possibly reset/halt.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests > T3: Fatal error states", + "line_range": [ + 4854, + 4860 + ] + }, + { + "text": "It’s a show stopper: The entropy source (or its cryptographic client application) must not be allowed to run if its secure operation can’t be guaranteed.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests > T3: Fatal error states", + "line_range": [ + 4854, + 4860 + ] + }, + { + "text": "*Rationale.* These tests can complement other integrity and tamper resistance mechanisms (See Chapter 18 of cite:[An20] for examples).", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests > T3: Fatal error states", + "line_range": [ + 4862, + 4864 + ] + }, + { + "text": "Some hardware random generators are, by their physical construction, exposed to relatively non-adversarial environmental and manufacturing issues.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests > T3: Fatal error states", + "line_range": [ + 4866, + 4870 + ] + }, + { + "text": "However, even such \"innocent\" failure modes may indicate a fault attack cite:[KaScVe13] and therefore should be addressed as a system integrity failure rather than as a diagnostic issue.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests > T3: Fatal error states", + "line_range": [ + 4866, + 4870 + ] + }, + { + "text": "Security architects will understand to use permanent or hard-to-recover \"security-fuse\" lockdowns only if the threshold of a test is such that the probability of false-positive is negligible over the entire device lifetime.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests > T3: Fatal error states", + "line_range": [ + 4872, + 4875 + ] + }, + { + "text": "Some of the most devastating practical attacks against real-life cryptosystems have used inconsequential-looking additional information, such as padding error messages cite:[BaFoKa:12] or timing information cite:[MoSuEi:20].", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests > Information Flows", + "line_range": [ + 4879, + 4883 + ] + }, + { + "text": "In cryptography, such out-of-band information sources are called \"oracles.\"", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests > Information Flows", + "line_range": [ + 4879, + 4883 + ] + }, + { + "text": "To guarantee that no sensitive data is read twice and that different callers don’t get correlated output, it is required that hardware implements wipe-on-read on the randomness pathway during each read (successful poll).", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests > Information Flows", + "line_range": [ + 4885, + 4890 + ] + }, + { + "text": "For the same reasons, only complete and fully processed random words shall be made available via `entropy` (ES16 status of `seed`).", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests > Information Flows", + "line_range": [ + 4885, + 4890 + ] + }, + { + "text": "This also applies to the raw noise source.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests > Information Flows", + "line_range": [ + 4892, + 4895 + ] + }, + { + "text": "The raw source interface has been delegated to an optional vendor-specific test interface.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests > Information Flows", + "line_range": [ + 4892, + 4895 + ] + }, + { + "text": "Importantly the test interface and the main interface should not be operational at the same time.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests > Information Flows", + "line_range": [ + 4892, + 4895 + ] + }, + { + "text": "[quote, NIST SP 800-90B, Noise Source Requirements] The noise source state shall be protected from adversarial knowledge or influence to the greatest extent possible.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests > Information Flows", + "line_range": [ + 4897, + 4902 + ] + }, + { + "text": "The methods used for this shall be documented, including a description of the (conceptual) security boundary's role in protecting the noise source from adversarial observation or influence.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests > Information Flows", + "line_range": [ + 4897, + 4902 + ] + }, + { + "text": "An entropy source is a singular resource, subject to depletion and also covert channels cite:[EvPo16].", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests > Information Flows", + "line_range": [ + 4904, + 4909 + ] + }, + { + "text": "Observation of the entropy can be the same as the observation of the noise source output, as cryptographic conditioning is mandatory only as a post-processing step. SP 800-90B and other security standards mandate protection of noise bits from observation and also influence.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Security Controls and Health Tests > Information Flows", + "line_range": [ + 4904, + 4909 + ] + }, + { + "text": "As a general rule, RISC-V specifies the ISA only.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies", + "line_range": [ + 4914, + 4918 + ] + }, + { + "text": "We provide some additional suggestions so that portable, vendor-independent middleware and kernel components can be created.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies", + "line_range": [ + 4914, + 4918 + ] + }, + { + "text": "The actual hardware implementation and certification are left to vendors and circuit designers; the discussion in this Section is purely informational.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies", + "line_range": [ + 4914, + 4918 + ] + }, + { + "text": "When considering implementation options and trade-offs, one must look at the entire information flow.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies", + "line_range": [ + 4920, + 4921 + ] + }, + { + "text": ". *A Noise Source* generates private, unpredictable signals from stable and well-understood physical random events. . *Sampling* digitizes the noise signal into a raw stream of bits.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies", + "line_range": [ + 4923, + 4935 + ] + }, + { + "text": "This raw data also needs to be protected by the design. . *Continuous health tests* ensure that the noise source and its environment meet their operational parameters. . *Non-cryptographic conditioners* remove much of the bias and correlation in input noise. . *Cryptographic conditioners* produce full entropy output, completely indistinguishable from ideal random. . *DRBG* takes in `>=256` bits of seed entropy as keying material and uses a \"one way\" cryptographic process to rapidly generate bits on demand (without revealing the seed/state).", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies", + "line_range": [ + 4923, + 4935 + ] + }, + { + "text": "Steps 1-4 (possibly 5) are considered to be part of the Entropy Source (ES) and provided by the `seed` CSR.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies", + "line_range": [ + 4937, + 4940 + ] + }, + { + "text": "Adding the software-side cryptographic steps 5-6 and control logic complements it into a True Random Number Generator (TRNG).", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies", + "line_range": [ + 4937, + 4940 + ] + }, + { + "text": "We will give some examples of common noise sources that can be implemented in the processor itself (using standard cells).", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Ring Oscillators", + "line_range": [ + 4945, + 4946 + ] + }, + { + "text": "The most common entropy source type in production use today is based on \"free running\" ring oscillators and their timing jitter.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Ring Oscillators", + "line_range": [ + 4948, + 4954 + ] + }, + { + "text": "Here, an odd number of inverters is connected into a loop from which noise source bits are sampled in relation to a reference clock cite:[BaLuMi:11].", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Ring Oscillators", + "line_range": [ + 4948, + 4954 + ] + }, + { + "text": "The sampled bit sequence may be expected to be relatively uncorrelated (close to IID) if the sample rate is suitably low cite:[KiSc11].", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Ring Oscillators", + "line_range": [ + 4948, + 4954 + ] + }, + { + "text": "However, further processing is usually required.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Ring Oscillators", + "line_range": [ + 4948, + 4954 + ] + }, + { + "text": "AMD cite:[AM17], ARM cite:[AR17], and IBM cite:[LiBaBo:13] are examples of ring oscillator TRNGs intended for high-security applications.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Ring Oscillators", + "line_range": [ + 4956, + 4958 + ] + }, + { + "text": "There are related metastability-based generator designs such as Transition Effect Ring Oscillator (TERO) cite:[VaDr10].", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Ring Oscillators", + "line_range": [ + 4960, + 4964 + ] + }, + { + "text": "The differential/feedback Intel construction cite:[HaKoMa12] is slightly different but also falls into the same general metastable oscillator-based category.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Ring Oscillators", + "line_range": [ + 4960, + 4964 + ] + }, + { + "text": "The main benefits of ring oscillators are: (1) They can be implemented with standard cell libraries without external components -- and even on FPGAs cite:[VaFiAu:10], (2) there is an established theory for their behavior cite:[HaLe98,HaLiLe99,BaLuMi:11], and (3) ample precedent exists for testing and certifying them at the highest security levels.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Ring Oscillators", + "line_range": [ + 4966, + 4971 + ] + }, + { + "text": "Ring oscillators also have well-known implementation pitfalls.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Ring Oscillators", + "line_range": [ + 4973, + 4983 + ] + }, + { + "text": "Their output is sometimes highly dependent on temperature, which must be taken into account in testing and modeling.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Ring Oscillators", + "line_range": [ + 4973, + 4983 + ] + }, + { + "text": "If the ring oscillator construction is parallelized, it is important that the number of stages and/or inverters in each chain is suitable to avoid entropy reduction due to harmonic \"Huyghens synchronization\" cite:[Ba86].", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Ring Oscillators", + "line_range": [ + 4973, + 4983 + ] + }, + { + "text": "Such harmonics can also be inserted maliciously in a frequency injection attack, which can have devastating results cite:[MaMo09].", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Ring Oscillators", + "line_range": [ + 4973, + 4983 + ] + }, + { + "text": "Countermeasures are related to circuit design; environmental sensors, electrical filters, and usage of a differential oscillator may help.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Ring Oscillators", + "line_range": [ + 4973, + 4983 + ] + }, + { + "text": "A category of random sources consisting of discrete events and modeled as a Poisson process is called \"shot noise.\" There's a long-established precedent of certifying them; the AIS 31 document cite:[KiSc11] itself offers reference designs based on noisy diodes.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Shot Noise", + "line_range": [ + 4987, + 4995 + ] + }, + { + "text": "Shot noise sources are often more resistant to temperature changes than ring oscillators.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Shot Noise", + "line_range": [ + 4987, + 4995 + ] + }, + { + "text": "Some of these generators can also be fully implemented with standard cells (The Rambus / Inside Secure generic TRNG IP cite:[Ra20] is described as a Shot Noise generator).", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Shot Noise", + "line_range": [ + 4987, + 4995 + ] + }, + { + "text": "It may be possible to certify more exotic noise sources and designs, although their stochastic model needs to be equally well understood, and their CPU interfaces must be secure.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Other types of noise", + "line_range": [ + 4999, + 5003 + ] + }, + { + "text": "See for a discussion of Quantum entropy sources.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Other types of noise", + "line_range": [ + 4999, + 5003 + ] + }, + { + "text": "Health monitoring requires some state information related to the noise source to be maintained.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Continuous Health Tests", + "line_range": [ + 5008, + 5013 + ] + }, + { + "text": "The tests should be designed in a way that a specific number of samples guarantees a state flush (no hung states).", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Continuous Health Tests", + "line_range": [ + 5008, + 5013 + ] + }, + { + "text": "We suggest flush size `W =< 1024` to match with the NIST SP 800-90B required tests (See Section 4.4 in cite:[TuBaKe:18]).", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Continuous Health Tests", + "line_range": [ + 5008, + 5013 + ] + }, + { + "text": "The state is also fully zeroized in a system reset.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Continuous Health Tests", + "line_range": [ + 5008, + 5013 + ] + }, + { + "text": "The two mandatory tests can be built with minimal circuitry.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Continuous Health Tests", + "line_range": [ + 5015, + 5025 + ] + }, + { + "text": "Full histograms are not required, only simple counter registers: repetition count, window count, and sample count.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Continuous Health Tests", + "line_range": [ + 5015, + 5025 + ] + }, + { + "text": "Repetition count is reset every time the output sample value changes; if the count reaches a certain cutoff limit, a noise alarm (`BIST`) or failure (`DEAD`) is signaled.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Continuous Health Tests", + "line_range": [ + 5015, + 5025 + ] + }, + { + "text": "The window counter is used to save every W'th output (typically `W` in { 512, 1024 }).", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Continuous Health Tests", + "line_range": [ + 5015, + 5025 + ] + }, + { + "text": "The frequency of this reference sample in the following window is counted; cutoff values are defined in the standard.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Continuous Health Tests", + "line_range": [ + 5015, + 5025 + ] + }, + { + "text": "We see that the structure of the mandatory tests is such that, if well implemented, no information is carried beyond a limit of `W` samples.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Continuous Health Tests", + "line_range": [ + 5015, + 5025 + ] + }, + { + "text": "Section 4.5 of cite:[TuBaKe:18] explicitly permits additional developer-defined tests, and several more were defined in early versions of FIPS 140-1 before being \"crossed out.\" The choice of additional tests depends on the nature and implementation of the physical source.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Continuous Health Tests", + "line_range": [ + 5027, + 5031 + ] + }, + { + "text": "Especially if a non-cryptographic conditioner is used in hardware, it is possible that the AIS 31 cite:[KiSc11] online tests are implemented by driver software.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Continuous Health Tests", + "line_range": [ + 5033, + 5040 + ] + }, + { + "text": "They can also be implemented in hardware.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Continuous Health Tests", + "line_range": [ + 5033, + 5040 + ] + }, + { + "text": "For some security profiles, AIS 31 mandates that their tolerances are set in a way that the probability of an alarm is at least 10^-6^ yearly under \"normal usage.\" Such requirements are problematic in modern applications since their probability is too high for critical systems.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Continuous Health Tests", + "line_range": [ + 5033, + 5040 + ] + }, + { + "text": "There rarely is anything that can or should be done about a non-fatal alarm condition in an operator-free, autonomous system.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Continuous Health Tests", + "line_range": [ + 5042, + 5050 + ] + }, + { + "text": "However, AIS 31 allows the DRBG component to keep running despite a failure in its Entropy Source, so we suggest re-entering a temporary `BIST` state () to signal a non-fatal statistical error if such (non-actionable) signaling is necessary.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Continuous Health Tests", + "line_range": [ + 5042, + 5050 + ] + }, + { + "text": "Drivers and applications can react to this appropriately (or simply log it), but it will not directly affect the availability of the TRNG. A permanent error condition should result in `DEAD` state.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Continuous Health Tests", + "line_range": [ + 5042, + 5050 + ] + }, + { + "text": "As noted in , physical randomness sources generally require a post-processing step called conditioning to meet the desired quality requirements, which are outlined in .", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Non-cryptographic Conditioners", + "line_range": [ + 5055, + 5058 + ] + }, + { + "text": "The approach taken in this interface is to allow a combination of non-cryptographic and cryptographic filtering to take place.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Non-cryptographic Conditioners", + "line_range": [ + 5060, + 5063 + ] + }, + { + "text": "The first stage (hardware) merely needs to be able to distill the entropy comfortably above the necessary level.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Non-cryptographic Conditioners", + "line_range": [ + 5060, + 5063 + ] + }, + { + "text": "One may take a set of bits from a noise source and XOR them together to produce a less biased (and more independent) bit.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Non-cryptographic Conditioners", + "line_range": [ + 5065, + 5079 + ] + }, + { + "text": "However, such an XOR may introduce \"pseudorandomness\" and make the output difficult to analyze. * The von Neumann extractor cite:[Ne51] looks at consecutive pairs of bits, rejects 00 and 11, and outputs 0 or 1 for 01 and 10, respectively.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Non-cryptographic Conditioners", + "line_range": [ + 5065, + 5079 + ] + }, + { + "text": "It will reduce the number of bits to less than 25% of the original, but the output is provably unbiased (assuming independence). * Blum's extractor cite:[Bl86] can be used on sources whose behavior resembles N-state Markov chains.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Non-cryptographic Conditioners", + "line_range": [ + 5065, + 5079 + ] + }, + { + "text": "If its assumptions hold, it also removes dependencies, creating an independent and identically distributed (IID) source. * Other linear and non-linear correctors such as those discussed by Dichtl and Lacharme cite:[La08].", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Non-cryptographic Conditioners", + "line_range": [ + 5065, + 5079 + ] + }, + { + "text": "Note that the hardware may also implement a full cryptographic conditioner in the entropy source, even though the software driver still needs a cryptographic conditioner, too ().", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Non-cryptographic Conditioners", + "line_range": [ + 5081, + 5083 + ] + }, + { + "text": "*Rationale:* The main advantage of non-cryptographic extractors is in their energy efficiency, relative simplicity, and amenability to mathematical analysis.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Non-cryptographic Conditioners", + "line_range": [ + 5085, + 5090 + ] + }, + { + "text": "If well designed, they can be evaluated in conjunction with a stochastic model of the noise source itself.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Non-cryptographic Conditioners", + "line_range": [ + 5085, + 5090 + ] + }, + { + "text": "They do not require computational hardness assumptions.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Non-cryptographic Conditioners", + "line_range": [ + 5085, + 5090 + ] + }, + { + "text": "For secure use, cryptographic conditioners are always required on the software side of the ISA boundary.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Cryptographic Conditioners", + "line_range": [ + 5095, + 5099 + ] + }, + { + "text": "They may also be implemented on the hardware side if necessary.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Cryptographic Conditioners", + "line_range": [ + 5095, + 5099 + ] + }, + { + "text": "In any case, the `entropy` ES16 output must always be compressed 2:1 (or more) before being used as keying material or considered \"full entropy.\"", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Cryptographic Conditioners", + "line_range": [ + 5095, + 5099 + ] + }, + { + "text": "Examples of cryptographic conditioners include the random pool of the Linux operating system, secure hash functions (SHA-2/3, SHAKE cite:[nist:fips:202,nist:fips:180:4]), and the AES / CBC-MAC construction in Appendix F, SP 800-90B cite:[TuBaKe:18].", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Cryptographic Conditioners", + "line_range": [ + 5101, + 5104 + ] + }, + { + "text": "In some constructions, such as the Linux RNG and SHA-3/SHAKE cite:[nist:fips:202] based generators, the cryptographic conditioning and output (DRBG) generation are provided by the same component.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Cryptographic Conditioners", + "line_range": [ + 5106, + 5108 + ] + }, + { + "text": "*Rationale:* For many low-power targets constructions the type of hardware AES CBC-MAC conditioner used by Intel cite:[Me18] and AMD cite:[AM17] would be too complex and energy-hungry to implement solely to serve the `seed` CSR.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Cryptographic Conditioners", + "line_range": [ + 5110, + 5118 + ] + }, + { + "text": "On the other hand, simpler non-cryptographic conditioners may be too wasteful on input entropy if high-quality random output is required -- (ARM TrustZone TRBG cite:[AR17] outputs only 10Kbit/sec at 200 MHz.) Hence a resource-saving compromise is made between hardware and software generation.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Cryptographic Conditioners", + "line_range": [ + 5110, + 5118 + ] + }, + { + "text": "All random bits reaching end users and applications must come from a cryptographic DRBG.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > The Final Random: DRBGs", + "line_range": [ + 5123, + 5127 + ] + }, + { + "text": "These are generally implemented by the driver component in software.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > The Final Random: DRBGs", + "line_range": [ + 5123, + 5127 + ] + }, + { + "text": "The RISC-V AES and SHA instruction set extensions should be used if available since they offer additional security features such as timing attack resistance.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > The Final Random: DRBGs", + "line_range": [ + 5123, + 5127 + ] + }, + { + "text": "Currently recommended DRBGs are defined in NIST SP 800-90A (Rev 1) cite:[BaKe15]: `CTRDRBG`, `HashDRBG`, and `HMACDRBG`.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > The Final Random: DRBGs", + "line_range": [ + 5129, + 5136 + ] + }, + { + "text": "Certification often requires known answer tests (KATs) for the symmetric components and the DRBG as a whole.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > The Final Random: DRBGs", + "line_range": [ + 5129, + 5136 + ] + }, + { + "text": "These are significantly easier to implement in software than in hardware.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > The Final Random: DRBGs", + "line_range": [ + 5129, + 5136 + ] + }, + { + "text": "In addition to the directly certifiable SP 800-90A DRBGs, a Linux-style random pool construction based on ChaCha20 cite:[Mu20] can be used, or an appropriate construction based on SHAKE256 cite:[nist:fips:202].", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > The Final Random: DRBGs", + "line_range": [ + 5129, + 5136 + ] + }, + { + "text": "These are just recommendations; programmers can adjust the usage of the CPU Entropy Source to meet future requirements.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > The Final Random: DRBGs", + "line_range": [ + 5138, + 5139 + ] + }, + { + "text": "[quote,U.K. NCSC QRNG Guidance, March 2020] The NCSC believes that classical RNGs will continue to meet our needs for government and military applications for the foreseeable future.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Quantum vs. Classical Random", + "line_range": [ + 5144, + 5147 + ] + }, + { + "text": "A Quantum Random Number Generator (QRNG) is a TRNG whose source of randomness can be unambiguously identified to be a specific quantum phenomenon such as quantum state superposition, quantum state entanglement, Heisenberg uncertainty, quantum tunneling, spontaneous emission, or radioactive decay cite:[IT19].", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Quantum vs. Classical Random", + "line_range": [ + 5149, + 5153 + ] + }, + { + "text": "Direct quantum entropy is theoretically the best possible kind of entropy. A typical TRNG based on electronic noise is also largely based on quantum phenomena and is equally unpredictable - the difference is that the relative amount of quantum and classical physics involved is difficult to quantify for a classical TRNG.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Quantum vs. Classical Random", + "line_range": [ + 5155, + 5159 + ] + }, + { + "text": "QRNGs are designed in a way that allows the amount of quantum-origin entropy to be modeled and estimated.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Quantum vs. Classical Random", + "line_range": [ + 5161, + 5166 + ] + }, + { + "text": "This distinction is important in the security model used by QKD (Quantum Key Distribution) security mechanisms which can be used to protect the physical layer (such as fiber optic cables) against interception by using quantum mechanical effects directly.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Quantum vs. Classical Random", + "line_range": [ + 5161, + 5166 + ] + }, + { + "text": "This security model means that many of the available QRNG devices do not use cryptographic conditioning and may fail cryptographic statistical requirements cite:[HuHe20].", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Quantum vs. Classical Random", + "line_range": [ + 5168, + 5171 + ] + }, + { + "text": "Many implementers may consider them to be entropy sources instead.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Quantum vs. Classical Random", + "line_range": [ + 5168, + 5171 + ] + }, + { + "text": "Relatively little research has gone into QRNG implementation security, but many QRNG designs are arguably more susceptible to leakage than classical generators (such as ring oscillators) as they tend to employ external components and mixed materials.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Quantum vs. Classical Random", + "line_range": [ + 5173, + 5178 + ] + }, + { + "text": "As an example, amplification of a photon detector signal may be observable in power analysis, which classical noise-based sources are designed to resist.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Quantum vs. Classical Random", + "line_range": [ + 5173, + 5178 + ] + }, + { + "text": "PQC public-key cryptography standards cite:[NI16] do not require quantum-origin randomness, just sufficiently secure keying material.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Post-Quantum Cryptography", + "line_range": [ + 5182, + 5186 + ] + }, + { + "text": "Recall that cryptography aims to protect the confidentiality and integrity of data itself and does not place any requirements on the physical communication channel (like QKD).", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Post-Quantum Cryptography", + "line_range": [ + 5182, + 5186 + ] + }, + { + "text": "Classical good-quality TRNGs are perfectly suitable for generating the secret keys for PQC protocols that are hard for quantum computers to break but implementable on classical computers.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Post-Quantum Cryptography", + "line_range": [ + 5188, + 5192 + ] + }, + { + "text": "What matters in cryptography is that the secret keys have enough true randomness (entropy) and that they are generated and stored securely.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Post-Quantum Cryptography", + "line_range": [ + 5188, + 5192 + ] + }, + { + "text": "Of course, one must avoid DRBGs that are based on problems that are easily solvable with quantum computers, such as factoring cite:[Sh94] in the case of the Blum-Blum-Shub generator cite:[BlBlSh86].", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Post-Quantum Cryptography", + "line_range": [ + 5194, + 5198 + ] + }, + { + "text": "Most symmetric algorithms are not affected as the best quantum attacks are still exponential to key size cite:[Gr96].", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Post-Quantum Cryptography", + "line_range": [ + 5194, + 5198 + ] + }, + { + "text": "As an example, the original Intel RNG cite:[Me18], whose output generation is based on AES-128, can be attacked using Grover's algorithm with approximately square-root effort cite:[JaNaRo:20].", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Post-Quantum Cryptography", + "line_range": [ + 5200, + 5209 + ] + }, + { + "text": "While even \"64-bit\" quantum security is extremely difficult to break, many applications specify a higher security requirement. NIST cite:[NI16] defines AES-128 to be \"Category 1\" equivalent post-quantum security, while AES-256 is \"Category 5\" (highest).", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Post-Quantum Cryptography", + "line_range": [ + 5200, + 5209 + ] + }, + { + "text": "We avoid this possible future issue by exposing direct access to the entropy source which can derive its security from information-theoretic assumptions only.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Implementation Strategies > Post-Quantum Cryptography", + "line_range": [ + 5200, + 5209 + ] + }, + { + "text": "Compliance testing, characterization, and configuration of entropy sources require access to raw, unconditioned noise samples.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Suggested GetNoise Test Interface", + "line_range": [ + 5214, + 5217 + ] + }, + { + "text": "This conceptual test interface is named GetNoise in Section 2.3.2 of NIST SP 800-90B cite:[TuBaKe:18].", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Suggested GetNoise Test Interface", + "line_range": [ + 5214, + 5217 + ] + }, + { + "text": "Since this type of interface is both necessary for security testing and also constitutes a potential backdoor to the cryptographic key generation process, we define a safety behavior that compliant implementations can have for temporarily disabling the entropy source `seed` CSR interface during test.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Suggested GetNoise Test Interface", + "line_range": [ + 5219, + 5223 + ] + }, + { + "text": "In order for shared RISC-V self-certification scripts (and drivers) to accommodate the test interface in a secure fashion, we suggest that it is implemented as a custom, M-mode only CSR, denoted here as `mnoise`.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Suggested GetNoise Test Interface", + "line_range": [ + 5225, + 5227 + ] + }, + { + "text": "This non-normative interface is not intended to be used as a source of randomness or for other production use.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Suggested GetNoise Test Interface", + "line_range": [ + 5229, + 5233 + ] + }, + { + "text": "We define the semantics for single bit for this interface, `mnoise[31]`, which is named `NOISETEST`, which will affect the behavior of `seed` if implemented.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Suggested GetNoise Test Interface", + "line_range": [ + 5229, + 5233 + ] + }, + { + "text": "When `NOISETEST = 1` in `mnoise`, the `seed` CSR must not return anything via `ES16`; it should be in `BIST` state unless the source is `DEAD`.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Suggested GetNoise Test Interface", + "line_range": [ + 5235, + 5239 + ] + }, + { + "text": "When `NOISETEST` is again disabled, the entropy source shall return from `BIST` via an appropriate zeroization and self-test mechanism.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Suggested GetNoise Test Interface", + "line_range": [ + 5235, + 5239 + ] + }, + { + "text": "The behavior of other input and output bits is largely left to the vendor (as they depend on the technical details of the physical entropy source), as is the address of the custom `mnoise` CSR.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Suggested GetNoise Test Interface", + "line_range": [ + 5241, + 5245 + ] + }, + { + "text": "Other contents and behavior of the CSR only can be interpreted in the context of `mvendorid`, `marchid`, and `mimpid` CSR identifiers.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Suggested GetNoise Test Interface", + "line_range": [ + 5241, + 5245 + ] + }, + { + "text": "When not implemented (e.g., in virtual machines), `mnoise` can permanently read zero (`0x00000000`) and ignore writes.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Suggested GetNoise Test Interface", + "line_range": [ + 5247, + 5250 + ] + }, + { + "text": "When available, but `NOISETEST = 0`, `mnoise` can return a nonzero constant (e.g. `0x00000001`) but no noise samples.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Suggested GetNoise Test Interface", + "line_range": [ + 5247, + 5250 + ] + }, + { + "text": "image::esnoisetest.svg[title=\"Entropy source can't be read in test mode.\", align=\"center\",scaledwidth=66%] In `NOISETEST` mode, the WAIT and ES16 states are unreachable, and no entropy is output.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Suggested GetNoise Test Interface", + "line_range": [ + 5252, + 5264 + ] + }, + { + "text": "Implementation of test interfaces that directly affect ES16 entropy output from the `seed` CSR interface is discouraged.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Suggested GetNoise Test Interface", + "line_range": [ + 5252, + 5264 + ] + }, + { + "text": "Such vendor test interfaces have been exploited in attacks.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Suggested GetNoise Test Interface", + "line_range": [ + 5252, + 5264 + ] + }, + { + "text": "For example, an ECDSA cite:[nist:fips:186:4] signature process without sufficient entropy will not only create an insecure signature but can also reveal the secret signing key, that can be used for authentication forgeries by attackers.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Suggested GetNoise Test Interface", + "line_range": [ + 5252, + 5264 + ] + }, + { + "text": "Hence even a temporary lapse in `entropy` security may have serious security implications.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Entropy Source Rationale and Recommendations > Suggested GetNoise Test Interface", + "line_range": [ + 5252, + 5264 + ] + }, + { + "text": "While this chapter contains the specifications for the RISC-V cryptography extensions, numerous supplementary materials and example codes have also been developed.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Supplementary Materials", + "line_range": [ + 5269, + 5274 + ] + }, + { + "text": "All of the supplementary materials related to the RISC-V Cryptography extension live in a GitHub Repository, located at https://github.com/riscv/riscv-crypto", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Supplementary Materials", + "line_range": [ + 5269, + 5274 + ] + }, + { + "text": "`doc/supp/` Contains supplementary information and recommendations for implementers of software and hardware.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Supplementary Materials", + "line_range": [ + 5276, + 5278 + ] + }, + { + "text": "`benchmarks/` Example software implementations.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Supplementary Materials", + "line_range": [ + 5280, + 5281 + ] + }, + { + "text": "`rtl/` Example Verilog implementations of each instruction.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Supplementary Materials", + "line_range": [ + 5283, + 5284 + ] + }, + { + "text": "`sail/` Formal model implementations in Sail.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Supplementary Materials", + "line_range": [ + 5286, + 5287 + ] + }, + { + "text": "This section contains the supporting Sail code referenced by the instruction descriptions throughout the specification.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Supporting Sail Code", + "line_range": [ + 5292, + 5296 + ] + }, + { + "text": "The link:https://alasdair.github.io/manual.html[Sail Manual] is recommended reading in order to best understand the supporting code.", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Supporting Sail Code", + "line_range": [ + 5292, + 5296 + ] + }, + { + "text": "[source,sail] ---- val xt2 : bits(8) -> bits(8) function xt2(x) = { (x << 1) ^ (if bittobool(x[7]) then 0x1b else 0x00) }", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Supporting Sail Code", + "line_range": [ + 5298, + 5304 + ] + }, + { + "text": "val xt3 : bits(8) -> bits(8) function xt3(x) = x ^ xt2(x)", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Supporting Sail Code", + "line_range": [ + 5306, + 5307 + ] + }, + { + "text": "val gfmul : (bits(8), bits(4)) -> bits(8) function gfmul( x, y) = { (if bittobool(y[0]) then x else 0x00) ^ (if bittobool(y[1]) then xt2( x) else 0x00) ^ (if bittobool(y[2]) then xt2(xt2( x)) else 0x00) ^ (if bittobool(y[3]) then xt2(xt2(xt2(x))) else 0x00) }", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Supporting Sail Code", + "line_range": [ + 5309, + 5316 + ] + }, + { + "text": "val aesmixcolumnbytefwd : bits(8) -> bits(32) function aesmixcolumnbytefwd(so) = { gfmul(so, 0x3) @ so @ so @ gfmul(so, 0x2) }", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Supporting Sail Code", + "line_range": [ + 5318, + 5322 + ] + }, + { + "text": "val aesmixcolumnbyteinv : bits(8) -> bits(32) function aesmixcolumnbyteinv(so) = { gfmul(so, 0xb) @ gfmul(so, 0xd) @ gfmul(so, 0x9) @ gfmul(so, 0xe) }", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Supporting Sail Code", + "line_range": [ + 5324, + 5328 + ] + }, + { + "text": "val aesmixcolumnfwd : bits(32) -> bits(32) function aesmixcolumnfwd(x) = { let s0 : bits (8) = x[ 7.. 0]; let s1 : bits (8) = x[15.. 8]; let s2 : bits (8) = x[23..16]; let s3 : bits (8) = x[31..24]; let b0 : bits (8) = xt2(s0) ^ xt3(s1) ^ (s2) ^ (s3); let b1 : bits (8) = (s0) ^ xt2(s1) ^ xt3(s2) ^ (s3); let b2 : bits (8) = (s0) ^ (s1) ^ xt2(s2) ^ xt3(s3); let b3 : bits (8) = xt3(s0) ^ (s1) ^ (s2) ^ xt2(s3); b3 @ b2 @ b1 @ b0 }", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Supporting Sail Code", + "line_range": [ + 5330, + 5342 + ] + }, + { + "text": "val aesmixcolumninv : bits(32) -> bits(32) function aesmixcolumninv(x) = { let s0 : bits (8) = x[ 7.. 0]; let s1 : bits (8) = x[15.. 8]; let s2 : bits (8) = x[23..16]; let s3 : bits (8) = x[31..24]; let b0 : bits (8) = gfmul(s0, 0xE) ^ gfmul(s1, 0xB) ^ gfmul(s2, 0xD) ^ gfmul(s3, 0x9); let b1 : bits (8) = gfmul(s0, 0x9) ^ gfmul(s1, 0xE) ^ gfmul(s2, 0xB) ^ gfmul(s3, 0xD); let b2 : bits (8) = gfmul(s0, 0xD) ^ gfmul(s1, 0x9) ^ gfmul(s2, 0xE) ^ gfmul(s3, 0xB); let b3 : bits (8) = gfmul(s0, 0xB) ^ gfmul(s1, 0xD) ^ gfmul(s2, 0x9) ^ gfmul(s3, 0xE); b3 @ b2 @ b1 @ b0 }", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Supporting Sail Code", + "line_range": [ + 5344, + 5356 + ] + }, + { + "text": "val aesdecodercon : bits(4) -> bits(32) function aesdecodercon(r) = { assert(r 0x00000001, 0x1 => 0x00000002, 0x2 => 0x00000004, 0x3 => 0x00000008, 0x4 => 0x00000010, 0x5 => 0x00000020, 0x6 => 0x00000040, 0x7 => 0x00000080, 0x8 => 0x0000001b, 0x9 => 0x00000036, => internalerror(FILE, LINE, \"Unexpected AES r\") } }", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Supporting Sail Code", + "line_range": [ + 5358, + 5380 + ] + }, + { + "text": "let sm4sboxtable : vector(256, bits(8)) = [ 0xD6, 0x90, 0xE9, 0xFE, 0xCC, 0xE1, 0x3D, 0xB7, 0x16, 0xB6, 0x14, 0xC2, 0x28, 0xFB, 0x2C, 0x05, 0x2B, 0x67, 0x9A, 0x76, 0x2A, 0xBE, 0x04, 0xC3, 0xAA, 0x44, 0x13, 0x26, 0x49, 0x86, 0x06, 0x99, 0x9C, 0x42, 0x50, 0xF4, 0x91, 0xEF, 0x98, 0x7A, 0x33, 0x54, 0x0B, 0x43, 0xED, 0xCF, 0xAC, 0x62, 0xE4, 0xB3, 0x1C, 0xA9, 0xC9, 0x08, 0xE8, 0x95, 0x80, 0xDF, 0x94, 0xFA, 0x75, 0x8F, 0x3F, 0xA6, 0x47, 0x07, 0xA7, 0xFC, 0xF3, 0x73, 0x17, 0xBA, 0x83, 0x59, 0x3C, 0x19, 0xE6, 0x85, 0x4F, 0xA8, 0x68, 0x6B, 0x81, 0xB2, 0x71, 0x64, 0xDA, 0x8B, 0xF8, 0xEB, 0x0F, 0x4B, 0x70, 0x56, 0x9D, 0x35, 0x1E, 0x24, 0x0E, 0x5E, 0x63, 0x58, 0xD1, 0xA2, 0x25, 0x22, 0x7C, 0x3B, 0x01, 0x21, 0x78, 0x87, 0xD4, 0x00, 0x46, 0x57, 0x9F, 0xD3, 0x27, 0x52, 0x4C, 0x36, 0x02, 0xE7, 0xA0, 0xC4, 0xC8, 0x9E, 0xEA, 0xBF, 0x8A, 0xD2, 0x40, 0xC7, 0x38, 0xB5, 0xA3, 0xF7, 0xF2, 0xCE, 0xF9, 0x61, 0x15, 0xA1, 0xE0, 0xAE, 0x5D, 0xA4, 0x9B, 0x34, 0x1A, 0x55, 0xAD, 0x93, 0x32, 0x30, 0xF5, 0x8C, 0xB1, 0xE3, 0x1D, 0xF6, 0xE2, 0x2E, 0x82, 0x66, 0xCA, 0x60, 0xC0, 0x29, 0x23, 0xAB, 0x0D, 0x53, 0x4E, 0x6F, 0xD5, 0xDB, 0x37, 0x45, 0xDE, 0xFD, 0x8E, 0x2F, 0x03, 0xFF, 0x6A, 0x72, 0x6D, 0x6C, 0x5B, 0x51, 0x8D, 0x1B, 0xAF, 0x92, 0xBB, 0xDD, 0xBC, 0x7F, 0x11, 0xD9, 0x5C, 0x41, 0x1F, 0x10, 0x5A, 0xD8, 0x0A, 0xC1, 0x31, 0x88, 0xA5, 0xCD, 0x7B, 0xBD, 0x2D, 0x74, 0xD0, 0x12, 0xB8, 0xE5, 0xB4, 0xB0, 0x89, 0x69, 0x97, 0x4A, 0x0C, 0x96, 0x77, 0x7E, 0x65, 0xB9, 0xF1, 0x09, 0xC5, 0x6E, 0xC6, 0x84, 0x18, 0xF0, 0x7D, 0xEC, 0x3A, 0xDC, 0x4D, 0x20, 0x79, 0xEE, 0x5F, 0x3E, 0xD7, 0xCB, 0x39, 0x48 ]", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Supporting Sail Code", + "line_range": [ + 5382, + 5404 + ] + }, + { + "text": "let aessboxfwdtable : vector(256, bits(8)) = [ 0x63, 0x7c, 0x77, 0x7b, 0xf2, 0x6b, 0x6f, 0xc5, 0x30, 0x01, 0x67, 0x2b, 0xfe, 0xd7, 0xab, 0x76, 0xca, 0x82, 0xc9, 0x7d, 0xfa, 0x59, 0x47, 0xf0, 0xad, 0xd4, 0xa2, 0xaf, 0x9c, 0xa4, 0x72, 0xc0, 0xb7, 0xfd, 0x93, 0x26, 0x36, 0x3f, 0xf7, 0xcc, 0x34, 0xa5, 0xe5, 0xf1, 0x71, 0xd8, 0x31, 0x15, 0x04, 0xc7, 0x23, 0xc3, 0x18, 0x96, 0x05, 0x9a, 0x07, 0x12, 0x80, 0xe2, 0xeb, 0x27, 0xb2, 0x75, 0x09, 0x83, 0x2c, 0x1a, 0x1b, 0x6e, 0x5a, 0xa0, 0x52, 0x3b, 0xd6, 0xb3, 0x29, 0xe3, 0x2f, 0x84, 0x53, 0xd1, 0x00, 0xed, 0x20, 0xfc, 0xb1, 0x5b, 0x6a, 0xcb, 0xbe, 0x39, 0x4a, 0x4c, 0x58, 0xcf, 0xd0, 0xef, 0xaa, 0xfb, 0x43, 0x4d, 0x33, 0x85, 0x45, 0xf9, 0x02, 0x7f, 0x50, 0x3c, 0x9f, 0xa8, 0x51, 0xa3, 0x40, 0x8f, 0x92, 0x9d, 0x38, 0xf5, 0xbc, 0xb6, 0xda, 0x21, 0x10, 0xff, 0xf3, 0xd2, 0xcd, 0x0c, 0x13, 0xec, 0x5f, 0x97, 0x44, 0x17, 0xc4, 0xa7, 0x7e, 0x3d, 0x64, 0x5d, 0x19, 0x73, 0x60, 0x81, 0x4f, 0xdc, 0x22, 0x2a, 0x90, 0x88, 0x46, 0xee, 0xb8, 0x14, 0xde, 0x5e, 0x0b, 0xdb, 0xe0, 0x32, 0x3a, 0x0a, 0x49, 0x06, 0x24, 0x5c, 0xc2, 0xd3, 0xac, 0x62, 0x91, 0x95, 0xe4, 0x79, 0xe7, 0xc8, 0x37, 0x6d, 0x8d, 0xd5, 0x4e, 0xa9, 0x6c, 0x56, 0xf4, 0xea, 0x65, 0x7a, 0xae, 0x08, 0xba, 0x78, 0x25, 0x2e, 0x1c, 0xa6, 0xb4, 0xc6, 0xe8, 0xdd, 0x74, 0x1f, 0x4b, 0xbd, 0x8b, 0x8a, 0x70, 0x3e, 0xb5, 0x66, 0x48, 0x03, 0xf6, 0x0e, 0x61, 0x35, 0x57, 0xb9, 0x86, 0xc1, 0x1d, 0x9e, 0xe1, 0xf8, 0x98, 0x11, 0x69, 0xd9, 0x8e, 0x94, 0x9b, 0x1e, 0x87, 0xe9, 0xce, 0x55, 0x28, 0xdf, 0x8c, 0xa1, 0x89, 0x0d, 0xbf, 0xe6, 0x42, 0x68, 0x41, 0x99, 0x2d, 0x0f, 0xb0, 0x54, 0xbb, 0x16 ]", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Supporting Sail Code", + "line_range": [ + 5406, + 5427 + ] + }, + { + "text": "let aessboxinvtable : vector(256, bits(8)) = [ 0x52, 0x09, 0x6a, 0xd5, 0x30, 0x36, 0xa5, 0x38, 0xbf, 0x40, 0xa3, 0x9e, 0x81, 0xf3, 0xd7, 0xfb, 0x7c, 0xe3, 0x39, 0x82, 0x9b, 0x2f, 0xff, 0x87, 0x34, 0x8e, 0x43, 0x44, 0xc4, 0xde, 0xe9, 0xcb, 0x54, 0x7b, 0x94, 0x32, 0xa6, 0xc2, 0x23, 0x3d, 0xee, 0x4c, 0x95, 0x0b, 0x42, 0xfa, 0xc3, 0x4e, 0x08, 0x2e, 0xa1, 0x66, 0x28, 0xd9, 0x24, 0xb2, 0x76, 0x5b, 0xa2, 0x49, 0x6d, 0x8b, 0xd1, 0x25, 0x72, 0xf8, 0xf6, 0x64, 0x86, 0x68, 0x98, 0x16, 0xd4, 0xa4, 0x5c, 0xcc, 0x5d, 0x65, 0xb6, 0x92, 0x6c, 0x70, 0x48, 0x50, 0xfd, 0xed, 0xb9, 0xda, 0x5e, 0x15, 0x46, 0x57, 0xa7, 0x8d, 0x9d, 0x84, 0x90, 0xd8, 0xab, 0x00, 0x8c, 0xbc, 0xd3, 0x0a, 0xf7, 0xe4, 0x58, 0x05, 0xb8, 0xb3, 0x45, 0x06, 0xd0, 0x2c, 0x1e, 0x8f, 0xca, 0x3f, 0x0f, 0x02, 0xc1, 0xaf, 0xbd, 0x03, 0x01, 0x13, 0x8a, 0x6b, 0x3a, 0x91, 0x11, 0x41, 0x4f, 0x67, 0xdc, 0xea, 0x97, 0xf2, 0xcf, 0xce, 0xf0, 0xb4, 0xe6, 0x73, 0x96, 0xac, 0x74, 0x22, 0xe7, 0xad, 0x35, 0x85, 0xe2, 0xf9, 0x37, 0xe8, 0x1c, 0x75, 0xdf, 0x6e, 0x47, 0xf1, 0x1a, 0x71, 0x1d, 0x29, 0xc5, 0x89, 0x6f, 0xb7, 0x62, 0x0e, 0xaa, 0x18, 0xbe, 0x1b, 0xfc, 0x56, 0x3e, 0x4b, 0xc6, 0xd2, 0x79, 0x20, 0x9a, 0xdb, 0xc0, 0xfe, 0x78, 0xcd, 0x5a, 0xf4, 0x1f, 0xdd, 0xa8, 0x33, 0x88, 0x07, 0xc7, 0x31, 0xb1, 0x12, 0x10, 0x59, 0x27, 0x80, 0xec, 0x5f, 0x60, 0x51, 0x7f, 0xa9, 0x19, 0xb5, 0x4a, 0x0d, 0x2d, 0xe5, 0x7a, 0x9f, 0x93, 0xc9, 0x9c, 0xef, 0xa0, 0xe0, 0x3b, 0x4d, 0xae, 0x2a, 0xf5, 0xb0, 0xc8, 0xeb, 0xbb, 0x3c, 0x83, 0x53, 0x99, 0x61, 0x17, 0x2b, 0x04, 0x7e, 0xba, 0x77, 0xd6, 0x26, 0xe1, 0x69, 0x14, 0x63, 0x55, 0x21, 0x0c, 0x7d ]", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Supporting Sail Code", + "line_range": [ + 5429, + 5450 + ] + }, + { + "text": "val sboxlookup : (bits(8), vector(256, bits(8))) -> bits(8) function sboxlookup(x, table) = { table[255 - unsigned(x)] }", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Supporting Sail Code", + "line_range": [ + 5452, + 5459 + ] + }, + { + "text": "val aessboxfwd : bits(8) -> bits(8) function aessboxfwd(x) = sboxlookup(x, aessboxfwdtable)", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Supporting Sail Code", + "line_range": [ + 5461, + 5463 + ] + }, + { + "text": "val aessboxinv : bits(8) -> bits(8) function aessboxinv(x) = sboxlookup(x, aessboxinvtable)", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Supporting Sail Code", + "line_range": [ + 5465, + 5467 + ] + }, + { + "text": "val aessubwordfwd : bits(32) -> bits(32) function aessubwordfwd(x) = { aessboxfwd(x[31..24]) @ aessboxfwd(x[23..16]) @ aessboxfwd(x[15.. 8]) @ aessboxfwd(x[ 7.. 0]) }", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Supporting Sail Code", + "line_range": [ + 5469, + 5478 + ] + }, + { + "text": "val aessubwordinv : bits(32) -> bits(32) function aessubwordinv(x) = { aessboxinv(x[31..24]) @ aessboxinv(x[23..16]) @ aessboxinv(x[15.. 8]) @ aessboxinv(x[ 7.. 0]) }", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Supporting Sail Code", + "line_range": [ + 5480, + 5489 + ] + }, + { + "text": "val sm4sbox : bits(8) -> bits(8) function sm4sbox(x) = sboxlookup(x, sm4sboxtable)", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Supporting Sail Code", + "line_range": [ + 5491, + 5493 + ] + }, + { + "text": "val aesgetcolumn : (bits(128), nat) -> bits(32) function aesgetcolumn(state,c) = (state >> (tobits(7, 32 * c)))[31..0]", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Supporting Sail Code", + "line_range": [ + 5495, + 5496 + ] + }, + { + "text": "val aesapplyfwdsboxtoeachbyte : bits(64) -> bits(64) function aesapplyfwdsboxtoeachbyte(x) = { aessboxfwd(x[63..56]) @ aessboxfwd(x[55..48]) @ aessboxfwd(x[47..40]) @ aessboxfwd(x[39..32]) @ aessboxfwd(x[31..24]) @ aessboxfwd(x[23..16]) @ aessboxfwd(x[15.. 8]) @ aessboxfwd(x[ 7.. 0]) }", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Supporting Sail Code", + "line_range": [ + 5498, + 5511 + ] + }, + { + "text": "val aesapplyinvsboxtoeachbyte : bits(64) -> bits(64) function aesapplyinvsboxtoeachbyte(x) = { aessboxinv(x[63..56]) @ aessboxinv(x[55..48]) @ aessboxinv(x[47..40]) @ aessboxinv(x[39..32]) @ aessboxinv(x[31..24]) @ aessboxinv(x[23..16]) @ aessboxinv(x[15.. 8]) @ aessboxinv(x[ 7.. 0]) }", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Supporting Sail Code", + "line_range": [ + 5513, + 5526 + ] + }, + { + "text": "val getbyte : (bits(64), int) -> bits(8) function getbyte(x, i) = (x >> tobits(6, i * 8))[7..0]", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Supporting Sail Code", + "line_range": [ + 5532, + 5533 + ] + }, + { + "text": "val aesrv64shiftrowsfwd : (bits(64), bits(64)) -> bits(64) function aesrv64shiftrowsfwd(rs2, rs1) = { getbyte(rs1, 3) @ getbyte(rs2, 6) @ getbyte(rs2, 1) @ getbyte(rs1, 4) @ getbyte(rs2, 7) @ getbyte(rs2, 2) @ getbyte(rs1, 5) @ getbyte(rs1, 0) }", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Supporting Sail Code", + "line_range": [ + 5535, + 5545 + ] + }, + { + "text": "val aesrv64shiftrowsinv : (bits(64), bits(64)) -> bits(64) function aesrv64shiftrowsinv(rs2, rs1) = { getbyte(rs2, 3) @ getbyte(rs2, 6) @ getbyte(rs1, 1) @ getbyte(rs1, 4) @ getbyte(rs1, 7) @ getbyte(rs2, 2) @ getbyte(rs2, 5) @ getbyte(rs1, 0) }", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Supporting Sail Code", + "line_range": [ + 5547, + 5557 + ] + }, + { + "text": "val aesshiftrowsfwd : bits(128) -> bits(128) function aesshiftrowsfwd(x) = { let ic3 : bits(32) = aesgetcolumn(x, 3); let ic2 : bits(32) = aesgetcolumn(x, 2); let ic1 : bits(32) = aesgetcolumn(x, 1); let ic0 : bits(32) = aesgetcolumn(x, 0); let oc0 : bits(32) = ic0[31..24] @ ic1[23..16] @ ic2[15.. 8] @ ic3[ 7.. 0]; let oc1 : bits(32) = ic1[31..24] @ ic2[23..16] @ ic3[15.. 8] @ ic0[ 7.. 0]; let oc2 : bits(32) = ic2[31..24] @ ic3[23..16] @ ic0[15.. 8] @ ic1[ 7.. 0]; let oc3 : bits(32) = ic3[31..24] @ ic0[23..16] @ ic1[15.. 8] @ ic2[ 7.. 0]; (oc3 @ oc2 @ oc1 @ oc0) }", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Supporting Sail Code", + "line_range": [ + 5559, + 5574 + ] + }, + { + "text": "val aesshiftrowsinv : bits(128) -> bits(128) function aesshiftrowsinv(x) = { let ic3 : bits(32) = aesgetcolumn(x, 3); let ic2 : bits(32) = aesgetcolumn(x, 2); let ic1 : bits(32) = aesgetcolumn(x, 1); let ic0 : bits(32) = aesgetcolumn(x, 0); let oc0 : bits(32) = ic0[31..24] @ ic3[23..16] @ ic2[15.. 8] @ ic1[ 7.. 0]; let oc1 : bits(32) = ic1[31..24] @ ic0[23..16] @ ic3[15.. 8] @ ic2[ 7.. 0]; let oc2 : bits(32) = ic2[31..24] @ ic1[23..16] @ ic0[15.. 8] @ ic3[ 7.. 0]; let oc3 : bits(32) = ic3[31..24] @ ic2[23..16] @ ic1[15.. 8] @ ic0[ 7.. 0]; (oc3 @ oc2 @ oc1 @ oc0) }", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Supporting Sail Code", + "line_range": [ + 5576, + 5591 + ] + }, + { + "text": "val aessubbytesfwd : bits(128) -> bits(128) function aessubbytesfwd(x) = { let oc0 : bits(32) = aessubwordfwd(aesgetcolumn(x, 0)); let oc1 : bits(32) = aessubwordfwd(aesgetcolumn(x, 1)); let oc2 : bits(32) = aessubwordfwd(aesgetcolumn(x, 2)); let oc3 : bits(32) = aessubwordfwd(aesgetcolumn(x, 3)); (oc3 @ oc2 @ oc1 @ oc0) }", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Supporting Sail Code", + "line_range": [ + 5593, + 5603 + ] + }, + { + "text": "val aessubbytesinv : bits(128) -> bits(128) function aessubbytesinv(x) = { let oc0 : bits(32) = aessubwordinv(aesgetcolumn(x, 0)); let oc1 : bits(32) = aessubwordinv(aesgetcolumn(x, 1)); let oc2 : bits(32) = aessubwordinv(aesgetcolumn(x, 2)); let oc3 : bits(32) = aessubwordinv(aesgetcolumn(x, 3)); (oc3 @ oc2 @ oc1 @ oc0) }", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Supporting Sail Code", + "line_range": [ + 5605, + 5615 + ] + }, + { + "text": "val aesmixcolumnsfwd : bits(128) -> bits(128) function aesmixcolumnsfwd(x) = { let oc0 : bits(32) = aesmixcolumnfwd(aesgetcolumn(x, 0)); let oc1 : bits(32) = aesmixcolumnfwd(aesgetcolumn(x, 1)); let oc2 : bits(32) = aesmixcolumnfwd(aesgetcolumn(x, 2)); let oc3 : bits(32) = aesmixcolumnfwd(aesgetcolumn(x, 3)); (oc3 @ oc2 @ oc1 @ oc0) }", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Supporting Sail Code", + "line_range": [ + 5617, + 5627 + ] + }, + { + "text": "val aesmixcolumnsinv : bits(128) -> bits(128) function aesmixcolumnsinv(x) = { let oc0 : bits(32) = aesmixcolumninv(aesgetcolumn(x, 0)); let oc1 : bits(32) = aesmixcolumninv(aesgetcolumn(x, 1)); let oc2 : bits(32) = aesmixcolumninv(aesgetcolumn(x, 2)); let oc3 : bits(32) = aesmixcolumninv(aesgetcolumn(x, 3)); (oc3 @ oc2 @ oc1 @ oc0) } ----", + "section": "Preamble > Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1 > Supporting Sail Code", + "line_range": [ + 5629, + 5640 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__symbols.json b/tools/llm-extraction/data/output/raw_chunks/src__symbols.json new file mode 100644 index 0000000000..6e408239da --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__symbols.json @@ -0,0 +1,5 @@ +{ + "source_file": "src/symbols.adoc", + "total": 0, + "sentences": [] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__unpriv.json b/tools/llm-extraction/data/output/raw_chunks/src__unpriv.json new file mode 100644 index 0000000000..2088d86c5d --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__unpriv.json @@ -0,0 +1,5 @@ +{ + "source_file": "src/unpriv.adoc", + "total": 0, + "sentences": [] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__unpriv__a-st-ext.json b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__a-st-ext.json new file mode 100644 index 0000000000..66de34a653 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__a-st-ext.json @@ -0,0 +1,14 @@ +{ + "source_file": "src/unpriv/a-st-ext.adoc", + "total": 1, + "sentences": [ + { + "text": "The `A` extension comprises the and extensions, which are defined in the following sections.", + "section": "Preamble > `A` Extension for Atomic Instructions", + "line_range": [ + 3, + 4 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__unpriv__bitmanip-examples.json b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__bitmanip-examples.json new file mode 100644 index 0000000000..1e7dbfb5a7 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__bitmanip-examples.json @@ -0,0 +1,134 @@ +{ + "source_file": "src/unpriv/bitmanip-examples.adoc", + "total": 16, + "sentences": [ + { + "text": "The following examples provide software optimization guidance.", + "section": "Preamble > Bit Manipulation Extensions Assembly Code Examples", + "line_range": [ + 3, + 3 + ] + }, + { + "text": "The *orc.b* instruction allows for the efficient detection of *NUL* bytes in an XLEN-sized chunk of data:", + "section": "Preamble > Bit Manipulation Extensions Assembly Code Examples > strlen", + "line_range": [ + 7, + 7 + ] + }, + { + "text": "the result of *orc.b* on a chunk that does not contain any *NUL* bytes will be all-ones, and * after a bitwise-negation of the result of *orc.b*, the number of data bytes before the first *NUL* byte (if any) can be detected by *ctz*/*clz* (depending on the endianness of data).", + "section": "Preamble > Bit Manipulation Extensions Assembly Code Examples > strlen", + "line_range": [ + 9, + 10 + ] + }, + { + "text": "A full example of a *strlen* function, which uses these techniques and also demonstrates the use of it for unaligned/partial data, is the following:", + "section": "Preamble > Bit Manipulation Extensions Assembly Code Examples > strlen", + "line_range": [ + 12, + 12 + ] + }, + { + "text": "[source,asm] -- include ", + "section": "Preamble > Bit Manipulation Extensions Assembly Code Examples > strlen", + "line_range": [ + 14, + 16 + ] + }, + { + "text": ".text .globl strlen .type strlen, @function strlen: andi a3, a0, (SZREG-1) // offset andi a1, a0, -SZREG // align pointer .Lprologue: li a4, SZREG sub a4, a4, a3 // XLEN - offset slli a3, a3, 3 // offset * 8 REGL a2, 0(a1) // chunk if BYTEORDER ORDERLITTLEENDIAN srl a2, a2 ,a3 // chunk >> (offset * 8) else sll a2, a2, a3 endif orc.b a2, a2 not a2, a2 if BYTEORDER ORDERLITTLEENDIAN ctz a2, a2 else clz a2, a2 endif srli a0, a2, 3 bgtu a4, a0, .Ldone addi a3, a1, SZREG li a4, -1 .align 2 .Lloop: REGL a2, SZREG(a1) addi a1, a1, SZREG orc.b a2, a2 beq a2, a4, .Lloop", + "section": "Preamble > Bit Manipulation Extensions Assembly Code Examples > strlen", + "line_range": [ + 18, + 67 + ] + }, + { + "text": ".Lepilogue: not a2, a2 if BYTEORDER ORDERLITTLEENDIAN ctz a2, a2 else clz a2, a2 endif sub a1, a1, a3 add a0, a0, a1 srli a2, a2, 3 add a0, a0, a2 .Ldone: ret --", + "section": "Preamble > Bit Manipulation Extensions Assembly Code Examples > strlen", + "line_range": [ + 69, + 82 + ] + }, + { + "text": "[source,asm] -- include ", + "section": "Preamble > Bit Manipulation Extensions Assembly Code Examples > strlen > strcmp", + "line_range": [ + 86, + 88 + ] + }, + { + "text": ".text .globl strcmp .type strcmp, @function strcmp: or a4, a0, a1 li t2, -1 and a4, a4, SZREG-1 bnez a4, .Lsimpleloop", + "section": "Preamble > Bit Manipulation Extensions Assembly Code Examples > strlen > strcmp", + "line_range": [ + 90, + 97 + ] + }, + { + "text": "Main loop for aligned strings .Lloop: REGL a2, 0(a0) REGL a3, 0(a1) orc.b t0, a2 bne t0, t2, .Lfoundnull addi a0, a0, SZREG addi a1, a1, SZREG beq a2, a3, .Lloop", + "section": "Preamble > Bit Manipulation Extensions Assembly Code Examples > strlen > strcmp", + "line_range": [ + 99, + 107 + ] + }, + { + "text": "Words don't match, and no null byte in first word.", + "section": "Preamble > Bit Manipulation Extensions Assembly Code Examples > strlen > strcmp", + "line_range": [ + 109, + 119 + ] + }, + { + "text": "Get bytes in big-endian order and compare. if BYTEORDER ORDERLITTLEENDIAN rev8 a2, a2 rev8 a3, a3 endif Synthesize (a2 >= a3) ? 1 : -1 in a branchless sequence. sltu a0, a2, a3 neg a0, a0 ori a0, a0, 1 ret", + "section": "Preamble > Bit Manipulation Extensions Assembly Code Examples > strlen > strcmp", + "line_range": [ + 109, + 119 + ] + }, + { + "text": ".Lfoundnull: Found a null byte.", + "section": "Preamble > Bit Manipulation Extensions Assembly Code Examples > strlen > strcmp", + "line_range": [ + 121, + 124 + ] + }, + { + "text": "If words don't match, fall back to simple loop. bne a2, a3, .Lsimpleloop", + "section": "Preamble > Bit Manipulation Extensions Assembly Code Examples > strlen > strcmp", + "line_range": [ + 121, + 124 + ] + }, + { + "text": "Otherwise, strings are equal. li a0, 0 ret", + "section": "Preamble > Bit Manipulation Extensions Assembly Code Examples > strlen > strcmp", + "line_range": [ + 126, + 128 + ] + }, + { + "text": "Simple loop for misaligned strings .Lsimpleloop: lbu a2, 0(a0) lbu a3, 0(a1) addi a0, a0, 1 addi a1, a1, 1 bne a2, a3, 1f bnez a2, .Lsimpleloop", + "section": "Preamble > Bit Manipulation Extensions Assembly Code Examples > strlen > strcmp", + "line_range": [ + 130, + 137 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__unpriv__c-st-ext.json b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__c-st-ext.json new file mode 100644 index 0000000000..233854f651 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__c-st-ext.json @@ -0,0 +1,54 @@ +{ + "source_file": "src/unpriv/c-st-ext.adoc", + "total": 6, + "sentences": [ + { + "text": "This section describes the ext:c[] extension, which incorporates the compressed instruction-set extensions designed for application- and server-class processors.", + "section": "Preamble > ext:c[] Extension for Compressed Instructions", + "line_range": [ + 3, + 9 + ] + }, + { + "text": "The ext:c[] extension substantially improves code density across a wide range of applications, thereby improving performance, area-efficiency, and energy-efficiency of processors with instruction caches.", + "section": "Preamble > ext:c[] Extension for Compressed Instructions", + "line_range": [ + 3, + 9 + ] + }, + { + "text": "It excludes features that improve code density at the cost of performance.", + "section": "Preamble > ext:c[] Extension for Compressed Instructions", + "line_range": [ + 3, + 9 + ] + }, + { + "text": "The ext:c[] extension depends upon the extlink:zca[] extension.", + "section": "Preamble > ext:c[] Extension for Compressed Instructions", + "line_range": [ + 11, + 11 + ] + }, + { + "text": "If XLEN=32 and the F extension is present, the ext:c[] extension additionally depends upon the extlink:zcf[] extension.", + "section": "Preamble > ext:c[] Extension for Compressed Instructions", + "line_range": [ + 13, + 14 + ] + }, + { + "text": "If the D extension is present, the ext:c[] extension additionally depends upon the extlink:zcd[] extension.", + "section": "Preamble > ext:c[] Extension for Compressed Instructions", + "line_range": [ + 16, + 17 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__unpriv__cfi.json b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__cfi.json new file mode 100644 index 0000000000..32c54e52e6 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__cfi.json @@ -0,0 +1,1286 @@ +{ + "source_file": "src/unpriv/cfi.adoc", + "total": 160, + "sentences": [ + { + "text": "Control-flow Integrity (CFI) capabilities help defend against Return-Oriented Programming (ROP) and Call/Jump-Oriented Programming (COP/JOP) style control-flow subversion attacks.", + "section": "Preamble > Control-flow Integrity (CFI)", + "line_range": [ + 2, + 11 + ] + }, + { + "text": "These attack methodologies use code sequences in authorized modules, with at least one instruction in the sequence being a control transfer instruction that depends on attacker-controlled data either in the return stack or in memory used to obtain the target address for a call or jump.", + "section": "Preamble > Control-flow Integrity (CFI)", + "line_range": [ + 2, + 11 + ] + }, + { + "text": "Attackers stitch these sequences together by diverting the control flow instructions (e.g., `JALR`, `C.JR`, `C.JALR`), from their original target address to a new target via modification in the return stack or in the memory used to obtain the jump/call target address.", + "section": "Preamble > Control-flow Integrity (CFI)", + "line_range": [ + 2, + 11 + ] + }, + { + "text": "RV32/RV64 provides two types of control transfer instructions - unconditional jumps and conditional branches.", + "section": "Preamble > Control-flow Integrity (CFI)", + "line_range": [ + 13, + 20 + ] + }, + { + "text": "Conditional branches encode an offset in the immediate field of the instruction and are thus direct branches that are not susceptible to control-flow subversion.", + "section": "Preamble > Control-flow Integrity (CFI)", + "line_range": [ + 13, + 20 + ] + }, + { + "text": "Unconditional direct jumps using `JAL` transfer control to a target that is in a +/- 1 MiB range from the current `pc`.", + "section": "Preamble > Control-flow Integrity (CFI)", + "line_range": [ + 13, + 20 + ] + }, + { + "text": "Unconditional indirect jumps using the `JALR` obtain their branch target by adding the sign extended 12-bit immediate encoded in the instruction to the `rs1` register.", + "section": "Preamble > Control-flow Integrity (CFI)", + "line_range": [ + 13, + 20 + ] + }, + { + "text": "The RV32I/RV64I does not have a dedicated instruction for calling a procedure or returning from a procedure. A `JAL` or `JALR` may be used to perform a procedure call and `JALR` to return from a procedure.", + "section": "Preamble > Control-flow Integrity (CFI)", + "line_range": [ + 22, + 29 + ] + }, + { + "text": "The RISC-V ABI however defines the convention that a `JAL`/`JALR` where `rd` (i.e. the link register) is `x1` or `x5` is a procedure call, and a `JALR` where `rs1` is the conventional link register (i.e. `x1` or `x5`) is a return from procedure.", + "section": "Preamble > Control-flow Integrity (CFI)", + "line_range": [ + 22, + 29 + ] + }, + { + "text": "The architecture allows for using these hints and conventions to support return address prediction (See ).", + "section": "Preamble > Control-flow Integrity (CFI)", + "line_range": [ + 22, + 29 + ] + }, + { + "text": "The ext:zca[] standard extension for compressed instructions provides unconditional jump and conditional branch instructions.", + "section": "Preamble > Control-flow Integrity (CFI)", + "line_range": [ + 31, + 39 + ] + }, + { + "text": "The `C.J` and `C.JAL` instructions encode an offset in the immediate field of the instruction and thus are not susceptible to control-flow subversion.", + "section": "Preamble > Control-flow Integrity (CFI)", + "line_range": [ + 31, + 39 + ] + }, + { + "text": "The `C.JR` and `C.JALR` instructions perform an unconditional control transfer to the address in register `rs1`.", + "section": "Preamble > Control-flow Integrity (CFI)", + "line_range": [ + 31, + 39 + ] + }, + { + "text": "The `C.JALR` additionally writes the address of the instruction following the jump (`pc+2`) to the link register `x1` and is a procedure call.", + "section": "Preamble > Control-flow Integrity (CFI)", + "line_range": [ + 31, + 39 + ] + }, + { + "text": "The `C.JR` is a return from procedure if `rs1` is a conventional link register (i.e. `x1` or `x5`); else it is an indirect jump.", + "section": "Preamble > Control-flow Integrity (CFI)", + "line_range": [ + 31, + 39 + ] + }, + { + "text": "The term call is used to refer to a `JAL` or `JALR` instruction with a link register as destination, i.e., rd!=`x0`.", + "section": "Preamble > Control-flow Integrity (CFI)", + "line_range": [ + 41, + 46 + ] + }, + { + "text": "Conventionally, the link register is `x1` or `x5`. A call using `JAL` or `C.JAL` is termed a direct call. A `C.JALR` expands to `JALR x1, 0(rs1)` and is a call. A call using `JALR` or `C.JALR` is termed an indirect-call.", + "section": "Preamble > Control-flow Integrity (CFI)", + "line_range": [ + 41, + 46 + ] + }, + { + "text": "The term return is used to refer to a `JALR` instruction with rd=`x0` and with rs1=`x1` or rs1=`x5`. A `C.JR` instruction expands to `JALR x0, 0(rs1)` and is a return if rs1=`x1` or rs1=`x5`.", + "section": "Preamble > Control-flow Integrity (CFI)", + "line_range": [ + 48, + 51 + ] + }, + { + "text": "The term indirect-jump is used to refer to a `JALR` instruction with rd=`x0` and where the rs1 is not `x1` or `x5` (i.e., not a return). A `C.JR` instruction where rs1 is not `x1` or `x5` (i.e., not a return) is an indirect-jump.", + "section": "Preamble > Control-flow Integrity (CFI)", + "line_range": [ + 53, + 57 + ] + }, + { + "text": "The Zicfiss and Zicfilp extensions build on these conventions and hints and provide backward-edge and forward-edge control flow integrity respectively.", + "section": "Preamble > Control-flow Integrity (CFI)", + "line_range": [ + 59, + 60 + ] + }, + { + "text": "The Unprivileged ISA for Zicfilp extension is specified in and for the Unprivileged ISA for Zicfiss extension is specified in .", + "section": "Preamble > Control-flow Integrity (CFI)", + "line_range": [ + 62, + 65 + ] + }, + { + "text": "The Privileged ISA for these extensions is specified in the Privileged ISA specification.", + "section": "Preamble > Control-flow Integrity (CFI)", + "line_range": [ + 62, + 65 + ] + }, + { + "text": "To enforce forward-edge control-flow integrity, the Zicfilp extension introduces a landing pad (`LPAD`) instruction.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp)", + "line_range": [ + 70, + 74 + ] + }, + { + "text": "The `LPAD` instruction must be placed at the program locations that are valid targets of indirect jumps or calls.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp)", + "line_range": [ + 70, + 74 + ] + }, + { + "text": "The `LPAD` instruction (See ) is encoded using the `AUIPC` major opcode with rd=`x0`.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp)", + "line_range": [ + 70, + 74 + ] + }, + { + "text": "Compilers emit a landing pad instruction as the first instruction of an address-taken function, as well as at any indirect jump targets. A landing pad instruction is not required in functions that are only reached using a direct call or direct jump.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp)", + "line_range": [ + 76, + 79 + ] + }, + { + "text": "The landing pad is designed to provide integrity to control transfers performed using indirect calls and jumps, and this is referred to as forward-edge protection.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp)", + "line_range": [ + 81, + 87 + ] + }, + { + "text": "When the Zicfilp is active, the hart tracks an expected landing pad (`ELP`) state that is updated by an indirectcall or indirectjump to require a landing pad instruction at the target of the branch.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp)", + "line_range": [ + 81, + 87 + ] + }, + { + "text": "If the instruction at the target is not a landing pad, then a software-check exception is raised.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp)", + "line_range": [ + 81, + 87 + ] + }, + { + "text": "A landing pad may be optionally associated with a 20-bit label.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp)", + "line_range": [ + 89, + 96 + ] + }, + { + "text": "With labeling enabled, the number of landing pads that can be reached from an indirect call or jump sites can be defined using programming language-based policies.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp)", + "line_range": [ + 89, + 96 + ] + }, + { + "text": "Labeling of the landing pads enables software to achieve greater precision in pairing up indirect call/jump sites with valid targets.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp)", + "line_range": [ + 89, + 96 + ] + }, + { + "text": "When labeling of landing pads is used, indirect call or indirect jump site can specify the expected label of the landing pad and thereby constrain the set of landing pads that may be reached from each indirect call or indirect jump site in the program.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp)", + "line_range": [ + 89, + 96 + ] + }, + { + "text": "In the simplest form, a program can be built with a single label value to implement a coarse-grained version of forward-edge control-flow integrity.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp)", + "line_range": [ + 98, + 125 + ] + }, + { + "text": "By constraining gadgets to be preceded by a landing pad instruction that marks the start of indirect callable functions, the program can significantly reduce the available gadget space. A second form of label generation may generate a signature, such as a MAC, using the prototype of the function.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp)", + "line_range": [ + 98, + 125 + ] + }, + { + "text": "Programs that use this approach would further constrain the gadgets accessible from a call site to only indirectly callable functions that match the prototype of the called functions.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp)", + "line_range": [ + 98, + 125 + ] + }, + { + "text": "Another approach to label generation involves analyzing the control-flow-graph (CFG) of the program, which can lead to even more stringent constraints on the set of reachable gadgets.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp)", + "line_range": [ + 98, + 125 + ] + }, + { + "text": "Such programs may further use multiple labels per function, which means that if a function is called from two or more call sites, the functions can be labeled as being reachable from each of the call sites.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp)", + "line_range": [ + 98, + 125 + ] + }, + { + "text": "For instance, consider two call sites A and B, where A calls the functions X and Y, and B calls the functions Y and Z.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp)", + "line_range": [ + 98, + 125 + ] + }, + { + "text": "In a single label scheme, functions X, Y, and Z would need to be assigned the same label so that both call sites A and B can invoke the common function Y.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp)", + "line_range": [ + 98, + 125 + ] + }, + { + "text": "This scheme would allow call site A to also call function Z and call site B to also call function X.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp)", + "line_range": [ + 98, + 125 + ] + }, + { + "text": "However, if function Y was assigned two labels - one corresponding to call site A and the other to call site B, then Y can be invoked by both call sites, but X can only be invoked by call site A and Z can only be invoked by call site B.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp)", + "line_range": [ + 98, + 125 + ] + }, + { + "text": "To support multiple labels, the compiler could generate a call-site-specific entry point for shared functions, with each entry point having its own landing pad instruction followed by a direct branch to the start of the function.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp)", + "line_range": [ + 98, + 125 + ] + }, + { + "text": "This would allow the function to be labeled with multiple labels, each corresponding to a specific call site. A portion of the label space may be dedicated to labeled landing pads that are only valid targets of an indirect jump (and not an indirect call).", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp)", + "line_range": [ + 98, + 125 + ] + }, + { + "text": "The `LPAD` instruction uses the code points defined as HINTs for the `AUIPC` opcode.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp)", + "line_range": [ + 127, + 132 + ] + }, + { + "text": "When Zicfilp is not active at a privilege level or when the extension is not implemented, the landing pad instruction executes as a no-op. A program that is built with `LPAD` instructions can thus continue to operate correctly, but without forward-edge control-flow integrity, on processors that do not support the Zicfilp extension or if the Zicfilp extension is not active.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp)", + "line_range": [ + 127, + 132 + ] + }, + { + "text": "Compilers and linkers should provide an attribute flag to indicate if the program has been compiled with the Zicfilp extension and use that to determine if the Zicfilp extension should be activated.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp)", + "line_range": [ + 134, + 139 + ] + }, + { + "text": "The dynamic loader should activate the use of Zicfilp extension for an application only if all executables (the application and the dependent dynamically linked libraries) used by that application use the Zicfilp extension.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp)", + "line_range": [ + 134, + 139 + ] + }, + { + "text": "When Zicfilp extension is not active or not implemented, the hart does not require landing pad instructions at the targets of indirect calls/jumps, and the landing instructions revert to being no-ops.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp)", + "line_range": [ + 141, + 145 + ] + }, + { + "text": "This allows a program compiled with landing pad instructions to operate correctly but without forward-edge control-flow integrity.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp)", + "line_range": [ + 141, + 145 + ] + }, + { + "text": "The Zicfilp extensions may be activated for use individually and independently for each privilege mode.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp)", + "line_range": [ + 147, + 148 + ] + }, + { + "text": "The Zicfilp extension depends on the Zicsr extension.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp)", + "line_range": [ + 150, + 150 + ] + }, + { + "text": "To enforce that the target of an indirect call or indirect jump must be a valid landing pad instruction, the hart maintains an expected landing pad (`ELP`) state to determine if a landing pad instruction is required at the target of an indirect call or an indirect jump.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing Pad Enforcement", + "line_range": [ + 154, + 157 + ] + }, + { + "text": "The `ELP` state can be one of:", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing Pad Enforcement", + "line_range": [ + 154, + 157 + ] + }, + { + "text": "0 - `NOLPEXPECTED` * 1 - `LPEXPECTED`", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing Pad Enforcement", + "line_range": [ + 159, + 160 + ] + }, + { + "text": "The `ELP` state is initialized to `NOLPEXPECTED` by the hart upon reset.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing Pad Enforcement", + "line_range": [ + 162, + 162 + ] + }, + { + "text": "The Zicfilp extension, when enabled, determines if an indirect call or an indirect jump must land on a landing pad, as specified in .", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing Pad Enforcement", + "line_range": [ + 164, + 167 + ] + }, + { + "text": "If `islpexpected` is 1, then the hart updates the `ELP` to `LPEXPECTED`.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing Pad Enforcement", + "line_range": [ + 164, + 167 + ] + }, + { + "text": ".Landing pad expected determination [listing] ----", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing Pad Enforcement", + "line_range": [ + 169, + 172 + ] + }, + { + "text": "islpexpected = ( (JALR || C.JR || C.JALR) && (rs1 != x1) && (rs1 != x5) && (rs1 != x7) ) ? 1 : 0; ----", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing Pad Enforcement", + "line_range": [ + 174, + 176 + ] + }, + { + "text": "An indirect branch using `JALR`, `C.JALR`, or `C.JR` with `rs1` as `x7` is termed a software guarded branch.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing Pad Enforcement", + "line_range": [ + 178, + 181 + ] + }, + { + "text": "Such branches do not need to land on a `LPAD` instruction and thus do not set `ELP` to `LPEXPECTED`.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing Pad Enforcement", + "line_range": [ + 178, + 181 + ] + }, + { + "text": "The landing pad may be labeled.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing Pad Enforcement", + "line_range": [ + 183, + 191 + ] + }, + { + "text": "Zicfilp extension designates the register `x7` for use as the landing pad label register.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing Pad Enforcement", + "line_range": [ + 183, + 191 + ] + }, + { + "text": "To support labeled landing pads, the indirect call/jump sites establish an expected landing pad label (e.g., using the `LUI` instruction) in the bits 31:12 of the `x7` register.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing Pad Enforcement", + "line_range": [ + 183, + 191 + ] + }, + { + "text": "The `LPAD` instruction is encoded with a 20-bit immediate value called the landing-pad-label (`LPL`) that is matched to the expected landing pad label.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing Pad Enforcement", + "line_range": [ + 183, + 191 + ] + }, + { + "text": "When `LPL` is encoded as zero, the `LPAD` instruction does not perform the label check and in programs built with this single label mode of operation the indirect call/jump sites do not need to establish an expected landing pad label value in `x7`.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing Pad Enforcement", + "line_range": [ + 183, + 191 + ] + }, + { + "text": "When `ELP` is set to `LPEXPECTED`, if the next instruction in the instruction stream is not 4-byte aligned, or is not `LPAD`, or if the landing pad label encoded in `LPAD` is not zero and does not match the expected landing pad label in bits 31:12 of the `x7` register, then a software-check exception (cause=18) with `xtval` set to \"landing pad fault (code=2)\" is raised else the `ELP` is updated to `NOLPEXPECTED`.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing Pad Enforcement", + "line_range": [ + 193, + 199 + ] + }, + { + "text": "When Zicfilp is enabled, `LPAD` is the only instruction allowed to execute when the `ELP` state is `LPEXPECTED`.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing Pad Enforcement > Landing Pad Instruction", + "line_range": [ + 206, + 210 + ] + }, + { + "text": "If Zicfilp is not enabled then the instruction is a no-op.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing Pad Enforcement > Landing Pad Instruction", + "line_range": [ + 206, + 210 + ] + }, + { + "text": "If Zicfilp is enabled, the `LPAD` instruction causes a software-check exception with `xtval` set to \"landing pad fault (code=2)\" if any of the following conditions are true:", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing Pad Enforcement > Landing Pad Instruction", + "line_range": [ + 206, + 210 + ] + }, + { + "text": "The `pc` is not 4-byte aligned and `ELP` is `LPEXPECTED`. * The `ELP` is `LPEXPECTED` and the `LPL` is not zero and the `LPL` does not match the expected landing pad label in bits 31:12 of the `x7` register.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing Pad Enforcement > Landing Pad Instruction", + "line_range": [ + 212, + 213 + ] + }, + { + "text": "If a software-check exception is not caused then the `ELP` is updated to `NOLPEXPECTED`.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing Pad Enforcement > Landing Pad Instruction", + "line_range": [ + 215, + 217 + ] + }, + { + "text": "[wavedrom, ,svg] .... {reg: [ {bits: 7, name: 'opcode', attr:'AUIPC'}, {bits: 5, name: 'rd', attr:'00000'}, {bits: 20, name: 'LPL'}, ], config:{lanes: 1, hspace:1024}} ....", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing Pad Enforcement > Landing Pad Instruction", + "line_range": [ + 219, + 226 + ] + }, + { + "text": "The operation of the `LPAD` instruction is as follows:", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing Pad Enforcement > Landing Pad Instruction", + "line_range": [ + 228, + 228 + ] + }, + { + "text": ".`LPAD` operation [listing] ---- if (xLPE 1 && ELP LPEXPECTED) //", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing Pad Enforcement > Landing Pad Instruction", + "line_range": [ + 230, + 247 + ] + }, + { + "text": "If PC not 4-byte aligned then software-check exception if pc[1:0] != 0 raise software-check exception //", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing Pad Enforcement > Landing Pad Instruction", + "line_range": [ + 230, + 247 + ] + }, + { + "text": "If landing pad label not matched -> software-check exception else if (inst.LPL != x7[31:12] && inst.LPL != 0) raise software-check exception else ELP = NOLPEXPECTED else no-op endif ---- <<<", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Landing Pad Enforcement > Landing Pad Instruction", + "line_range": [ + 230, + 247 + ] + }, + { + "text": "The Zicfiss extension introduces a shadow stack to enforce backward-edge control-flow integrity. A shadow stack is a second stack used to store a shadow copy of the return address in the link register if it needs to be spilled.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss)", + "line_range": [ + 252, + 255 + ] + }, + { + "text": "The shadow stack is designed to provide integrity to control transfers performed using a return, where the return may be from a procedure invoked using an indirect call or a direct call, and this is referred to as backward-edge protection.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss)", + "line_range": [ + 257, + 260 + ] + }, + { + "text": "A program using backward-edge control-flow integrity has two stacks: a regular stack and a shadow stack.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss)", + "line_range": [ + 262, + 266 + ] + }, + { + "text": "The shadow stack is used to spill the link register, if required, by non-leaf functions.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss)", + "line_range": [ + 262, + 266 + ] + }, + { + "text": "An additional register, shadow-stack-pointer (`ssp`), is introduced in the architecture to hold the address of the top of the active shadow stack.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss)", + "line_range": [ + 262, + 266 + ] + }, + { + "text": "The shadow stack, similar to the regular stack, grows downwards, from higher addresses to lower addresses.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss)", + "line_range": [ + 268, + 272 + ] + }, + { + "text": "Each entry on the shadow stack is `XLEN` wide and holds the link register value.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss)", + "line_range": [ + 268, + 272 + ] + }, + { + "text": "The `ssp` points to the top of the shadow stack, which is the address of the last element stored on the shadow stack.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss)", + "line_range": [ + 268, + 272 + ] + }, + { + "text": "The shadow stack is architecturally protected from inadvertent corruptions and modifications, as detailed in the Privileged specification.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss)", + "line_range": [ + 274, + 275 + ] + }, + { + "text": "The Zicfiss extension provides instructions to store and load the link register to/from the shadow stack and to check the integrity of the return address.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss)", + "line_range": [ + 277, + 280 + ] + }, + { + "text": "The extension provides instructions to support common stack maintenance operations such as stack unwinding and stack switching.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss)", + "line_range": [ + 277, + 280 + ] + }, + { + "text": "When Zicfiss is enabled, each function that needs to spill the link register, typically non-leaf functions, store the link register value to the regular stack and a shadow copy of the link register value to the shadow stack when the function is entered (the prologue).", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss)", + "line_range": [ + 282, + 291 + ] + }, + { + "text": "When such a function returns (the epilogue), the function loads the link register from the regular stack and the shadow copy of the link register from the shadow stack.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss)", + "line_range": [ + 282, + 291 + ] + }, + { + "text": "Then, the link register value from the regular stack and the shadow link register value from the shadow stack are compared. A mismatch of the two values is indicative of a subversion of the return address control variable and causes a software-check exception.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss)", + "line_range": [ + 282, + 291 + ] + }, + { + "text": "The Zicfiss instructions, except `SSAMOSWAP.W/D`, are encoded using a subset of May-Be-Operation instructions defined by the Zimop and Zcmop extensions.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss)", + "line_range": [ + 293, + 301 + ] + }, + { + "text": "This subset of instructions revert to their Zimop/Zcmop defined behavior when the Zicfiss extension is not implemented or if the extension has not been activated. A program that is built with Zicfiss instructions can thus continue to operate correctly, but without backward-edge control-flow integrity, on processors that do not support the Zicfiss extension or if the Zicfiss extension is not active.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss)", + "line_range": [ + 293, + 301 + ] + }, + { + "text": "The Zicfiss extension may be activated for use individually and independently for each privilege mode.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss)", + "line_range": [ + 293, + 301 + ] + }, + { + "text": "Compilers should flag each object file (for example, using flags in the ELF attributes) to indicate if the object file has been compiled with the Zicfiss instructions.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss)", + "line_range": [ + 303, + 308 + ] + }, + { + "text": "The linker should flag (for example, using flags in the ELF attributes) the binary/executable generated by linking objects as being compiled with the Zicfiss instructions only if all the object files that are linked have the same Zicfiss attributes.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss)", + "line_range": [ + 303, + 308 + ] + }, + { + "text": "The dynamic loader should activate the use of Zicfiss extension for an application only if all executables (the application and the dependent dynamically-linked libraries) used by that application use the Zicfiss extension.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss)", + "line_range": [ + 310, + 313 + ] + }, + { + "text": "An application that has the Zicfiss extension active may request the dynamic loader at runtime to load a new dynamic shared object (using dlopen() for example).", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss)", + "line_range": [ + 317, + 323 + ] + }, + { + "text": "If the requested object does not have the Zicfiss attribute then the dynamic loader, based on its policy (e.g., established by the operating system or the administrator) configuration, could either deny the request or deactivate the Zicfiss extension for the application.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss)", + "line_range": [ + 317, + 323 + ] + }, + { + "text": "It is strongly recommended that the policy enforces a strict security posture and denies the request.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss)", + "line_range": [ + 317, + 323 + ] + }, + { + "text": "The Zicfiss extension depends on the Zicsr, Zimop and Zaamo extensions.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss)", + "line_range": [ + 325, + 328 + ] + }, + { + "text": "Furthermore, if the Zcmop extension is implemented, the Zicfiss extension also provides the `C.SSPUSH` and `C.SSPOPCHK` instructions.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss)", + "line_range": [ + 325, + 328 + ] + }, + { + "text": "Moreover, use of Zicfiss in U-mode requires S-mode to be implemented.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss)", + "line_range": [ + 325, + 328 + ] + }, + { + "text": "Use of Zicfiss in M-mode is not supported.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss)", + "line_range": [ + 325, + 328 + ] + }, + { + "text": "The Zicfiss extension introduces the following instructions:", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Zicfiss Instructions Summary", + "line_range": [ + 332, + 332 + ] + }, + { + "text": "Push to the shadow stack (See ) ** `SSPUSH x1` and `SSPUSH x5` - encoded using `MOP.RR.7` ** `C.SSPUSH x1` - encoded using `C.MOP.1`", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Zicfiss Instructions Summary", + "line_range": [ + 334, + 336 + ] + }, + { + "text": "Pop from the shadow stack (See ) ** `SSPOPCHK x1` and `SSPOPCHK x5` - encoded using `MOP.R.28` ** `C.SSPOPCHK x5` - encoded using `C.MOP.5`", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Zicfiss Instructions Summary", + "line_range": [ + 338, + 340 + ] + }, + { + "text": "Read the value of `ssp` into a register (See ) ** `SSRDP` - encoded using `MOP.R.28`", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Zicfiss Instructions Summary", + "line_range": [ + 342, + 343 + ] + }, + { + "text": "Perform an atomic swap from a shadow stack location (See ) ** `SSAMOSWAP.W` and `SSAMOSWAP.D`", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Zicfiss Instructions Summary", + "line_range": [ + 345, + 346 + ] + }, + { + "text": "Zicfiss does not use all encodings of `MOP.RR.7` or `MOP.R.28`.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Zicfiss Instructions Summary", + "line_range": [ + 348, + 351 + ] + }, + { + "text": "When a `MOP.RR.7` or `MOP.R.28` encoding is not used by the Zicfiss extension, the corresponding instruction adheres to its Zimop-defined behavior, unless redefined by another extension.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Zicfiss Instructions Summary", + "line_range": [ + 348, + 351 + ] + }, + { + "text": "The `ssp` CSR is an unprivileged read-write (URW) CSR that reads and writes `XLEN` low order bits of the shadow stack pointer (`ssp`).", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Pointer (`ssp`)", + "line_range": [ + 355, + 359 + ] + }, + { + "text": "There is no high CSR defined as the `ssp` is always as wide as the `XLEN` of the current privilege mode.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Pointer (`ssp`)", + "line_range": [ + 355, + 359 + ] + }, + { + "text": "The bits 1:0 of `ssp` are read-only zero.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Pointer (`ssp`)", + "line_range": [ + 355, + 359 + ] + }, + { + "text": "If the UXLEN or SXLEN may never be 32, then the bit 2 is also read-only zero.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Shadow Stack Pointer (`ssp`)", + "line_range": [ + 355, + 359 + ] + }, + { + "text": "A shadow stack push operation is defined as decrement of the `ssp` by `XLEN/8` followed by a store of the value in the link register to memory at the new top of the shadow stack.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Push to the Shadow Stack", + "line_range": [ + 368, + 371 + ] + }, + { + "text": "[wavedrom, ,svg] .... {reg: [ {bits: 7, name: 'opcode', attr:'SYSTEM'}, {bits: 5, name: 'rd', attr:['00000']}, {bits: 3, name: 'funct3', attr:['100']}, {bits: 5, name: 'rs1', attr:['00000']}, {bits: 5, name: 'rs2', attr:['00001', '00101']}, {bits: 7, name: '1100111', attr:['SSPUSH x1','SSPUSH x5']}, ], config:{lanes: 1, hspace:1024}} ....", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Push to the Shadow Stack", + "line_range": [ + 373, + 383 + ] + }, + { + "text": "[wavedrom, ,svg] .... {reg: [ {bits: 2, name: 'op', attr:'C1'}, {bits: 5, name: '00000'}, {bits: 1, name: '1'}, {bits: 3, name: 'n[3:1]', attr:['000']}, {bits: 1, name: '0'}, {bits: 1, name: '0'}, {bits: 3, name: '011', attr:['C.SSPUSH x1']}, ], config:{lanes: 1, hspace:1024}} ....", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Push to the Shadow Stack", + "line_range": [ + 385, + 396 + ] + }, + { + "text": "Only `x1` and `x5` registers are supported as `rs2` for `SSPUSH`.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Push to the Shadow Stack", + "line_range": [ + 398, + 400 + ] + }, + { + "text": "Zicfiss provides a 16-bit version of the `SSPUSH x1` instruction using the Zcmop defined `C.MOP.1` encoding.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Push to the Shadow Stack", + "line_range": [ + 398, + 400 + ] + }, + { + "text": "The `C.SSPUSH x1` expands to `SSPUSH x1`.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Push to the Shadow Stack", + "line_range": [ + 398, + 400 + ] + }, + { + "text": "The `SSPUSH` instruction and its compressed form `C.SSPUSH` can be used to push a link register on the shadow stack.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Push to the Shadow Stack", + "line_range": [ + 402, + 406 + ] + }, + { + "text": "The `SSPUSH` and `C.SSPUSH` instructions perform a store identically to the existing store instructions, with the difference that the base is implicitly `ssp` and the width is implicitly `XLEN`.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Push to the Shadow Stack", + "line_range": [ + 402, + 406 + ] + }, + { + "text": "The operation of the `SSPUSH` and `C.SSPUSH` instructions is as follows:", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Push to the Shadow Stack", + "line_range": [ + 408, + 408 + ] + }, + { + "text": ".`SSPUSH` and `C.SSPUSH` operation [listing] ---- if (xSSE 1) mem[ssp - (XLEN/8)] = X(src) Store src value to ssp - XLEN/8 ssp = ssp - (XLEN/8) decrement ssp by XLEN/8 endif ---- The `ssp` is decremented by `SSPUSH` and `C.SSPUSH` only if the store to the shadow stack completes successfully.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Push to the Shadow Stack", + "line_range": [ + 410, + 420 + ] + }, + { + "text": "A shadow stack pop operation is defined as an `XLEN` wide read from the current top of the shadow stack followed by an increment of the `ssp` by `XLEN/8`.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Pop from the Shadow Stack", + "line_range": [ + 426, + 429 + ] + }, + { + "text": "[wavedrom, ,svg] .... {reg: [ {bits: 7, name: 'opcode', attr:'SYSTEM'}, {bits: 5, name: 'rd', attr:['00000','00000']}, {bits: 3, name: 'funct3', attr:['100']}, {bits: 5, name: 'rs1', attr:['00001','00101']}, {bits: 12, name: '110011011100', attr:['SSPOPCHK x1','SSPOPCHK x5']}, ], config:{lanes: 1, hspace:1024}} ....", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Pop from the Shadow Stack", + "line_range": [ + 431, + 440 + ] + }, + { + "text": "[wavedrom, ,svg] .... {reg: [ {bits: 2, name: 'op', attr:'C1'}, {bits: 5, name: '00000'}, {bits: 1, name: '1'}, {bits: 3, name: 'n[3:1]', attr:['010']}, {bits: 1, name: '0'}, {bits: 1, name: '0'}, {bits: 3, name: '011', attr:['C.SSPOPCHK x5']}, ], config:{lanes: 1, hspace:1024}} ....", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Pop from the Shadow Stack", + "line_range": [ + 442, + 453 + ] + }, + { + "text": "Only `x1` and `x5` registers are supported as `rs1` for `SSPOPCHK`.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Pop from the Shadow Stack", + "line_range": [ + 455, + 457 + ] + }, + { + "text": "Zicfiss provides a 16-bit version of the `SSPOPCHK x5` using the Zcmop defined `C.MOP.5` encoding.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Pop from the Shadow Stack", + "line_range": [ + 455, + 457 + ] + }, + { + "text": "The `C.SSPOPCHK x5` expands to `SSPOPCHK x5`.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Pop from the Shadow Stack", + "line_range": [ + 455, + 457 + ] + }, + { + "text": "Programs with a shadow stack push the return address onto the regular stack as well as the shadow stack in the prologue of non-leaf functions.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Pop from the Shadow Stack", + "line_range": [ + 459, + 464 + ] + }, + { + "text": "When returning from these non-leaf functions, such programs pop the link register from the regular stack and pop a shadow copy of the link register from the shadow stack.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Pop from the Shadow Stack", + "line_range": [ + 459, + 464 + ] + }, + { + "text": "The two values are then compared.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Pop from the Shadow Stack", + "line_range": [ + 459, + 464 + ] + }, + { + "text": "If the values do not match, it is indicative of a corruption of the return address variable on the regular stack.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Pop from the Shadow Stack", + "line_range": [ + 459, + 464 + ] + }, + { + "text": "The `SSPOPCHK` instruction, and its compressed form `C.SSPOPCHK`, can be used to pop the shadow return address value from the shadow stack and check that the value matches the contents of the link register, and if not cause a software-check exception with `xtval` set to \"shadow stack fault (code=3)\".", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Pop from the Shadow Stack", + "line_range": [ + 466, + 470 + ] + }, + { + "text": "While any register may be used as link register, conventionally the `x1` or `x5` registers are used.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Pop from the Shadow Stack", + "line_range": [ + 472, + 474 + ] + }, + { + "text": "The shadow stack instructions are designed to be most efficient when the `x1` and `x5` registers are used as the link register.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Pop from the Shadow Stack", + "line_range": [ + 472, + 474 + ] + }, + { + "text": "The `C.SSPOPCHK`, and `SSPOPCHK` instructions perform a load identically to the existing load instructions, with the difference that the base is implicitly `ssp` and the width is implicitly `XLEN`.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Pop from the Shadow Stack", + "line_range": [ + 478, + 481 + ] + }, + { + "text": "The operation of the `SSPOPCHK` and `C.SSPOPCHK` instructions is as follows:", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Pop from the Shadow Stack", + "line_range": [ + 483, + 483 + ] + }, + { + "text": ".`SSPOPCHK` and `C.SSPOPCHK` operation [listing] ---- if (xSSE 1) temp = mem[ssp] Load temp from address in ssp and if temp != X(src) Compare temp to value in src and cause a software-check exception if they are not bitwise equal.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Pop from the Shadow Stack", + "line_range": [ + 485, + 499 + ] + }, + { + "text": "Only x1 and x5 may be used as src raise software-check exception else ssp = ssp + (XLEN/8) increment ssp by XLEN/8. endif endif ----", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Pop from the Shadow Stack", + "line_range": [ + 485, + 499 + ] + }, + { + "text": "If the value loaded from the address in `ssp` does not match the value in `rs1`, a software-check exception (cause=18) is raised with `xtval` set to \"shadow stack fault (code=3)\".", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Pop from the Shadow Stack", + "line_range": [ + 501, + 505 + ] + }, + { + "text": "The software-check exception caused by `SSPOPCHK`/ `C.SSPOPCHK` is lower in priority than a load/store/AMO access-fault exception.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Pop from the Shadow Stack", + "line_range": [ + 501, + 505 + ] + }, + { + "text": "The `ssp` is incremented by `SSPOPCHK` and `C.SSPOPCHK` only if the load from the shadow stack completes successfully and no software-check exception is raised.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Pop from the Shadow Stack", + "line_range": [ + 507, + 510 + ] + }, + { + "text": "The `SSRDP` instruction is provided to move the contents of `ssp` to a destination register.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Read `ssp` into a Register", + "line_range": [ + 518, + 520 + ] + }, + { + "text": "[wavedrom, ,svg] .... {reg: [ {bits: 7, name: 'opcode', attr:'SYSTEM'}, {bits: 5, name: 'rd', attr:['dst']}, {bits: 3, name: 'funct3', attr:['100']}, {bits: 5, name: '00000'}, {bits: 12, name: '110011011100', attr:['SSRDP']}, ], config:{lanes: 1, hspace:1024}} ....", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Read `ssp` into a Register", + "line_range": [ + 522, + 531 + ] + }, + { + "text": "Encoding rd as `x0` is not supported for `SSRDP`.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Read `ssp` into a Register", + "line_range": [ + 533, + 533 + ] + }, + { + "text": "The operation of the `SSRDP` instructions is as follows:", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Read `ssp` into a Register", + "line_range": [ + 535, + 535 + ] + }, + { + "text": ".`SSRDP` operation [listing] ---- if (xSSE 1) X(dst) = ssp else X(dst) = 0 endif ----", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Read `ssp` into a Register", + "line_range": [ + 537, + 545 + ] + }, + { + "text": "[wavedrom, ,svg] .... {reg: [ {bits: 7, name: 'opcode', attr:'AMO'}, {bits: 5, name: 'rd', attr:'dest'}, {bits: 3, name: 'funct3', attr:['010', '011']}, {bits: 5, name: 'rs1', attr:'addr'}, {bits: 5, name: 'rs2', attr:'src'}, {bits: 1, name: 'rl'}, {bits: 1, name: 'aq'}, {bits: 5, name: '01001', attr:['SSAMOSWAP.W', 'SSAMOSWAP.D']}, ], config:{lanes: 1, hspace:1024}} ....", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Atomic Swap from a Shadow Stack Location", + "line_range": [ + 554, + 566 + ] + }, + { + "text": "For RV32, `SSAMOSWAP.W` atomically loads a 32-bit data value from address of a shadow stack location in `rs1`, puts the loaded value into register `rd`, and stores the 32-bit value held in `rs2` to the original address in `rs1`. `SSAMOSWAP.D` (RV64 only) is similar to `SSAMOSWAP.W` but operates on 64-bit data values.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Atomic Swap from a Shadow Stack Location", + "line_range": [ + 568, + 573 + ] + }, + { + "text": ".`SSAMOSWAP.W` for RV32 and `SSAMOSWAP.D` (RV64 only) operation [listing] ---- if privilegemode != M && menvcfg.SSE 0 raise illegal-instruction exception else if S-mode not implemented raise illegal-instruction exception else if privilegemode U && senvcfg.SSE 0 raise illegal-instruction exception else if privilegemode VS && henvcfg.SSE 0 raise virtual-instruction exception else if privilegemode VU && senvcfg.SSE 0 raise virtual-instruction exception else X(rd) = mem[X(rs1)] mem[X(rs1)] = X(rs2) endif ----", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Atomic Swap from a Shadow Stack Location", + "line_range": [ + 575, + 592 + ] + }, + { + "text": "For RV64, `SSAMOSWAP.W` atomically loads a 32-bit data value from address of a shadow stack location in `rs1`, sign-extends the loaded value and puts it in `rd`, and stores the lower 32 bits of the value held in `rs2` to the original address in `rs1`.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Atomic Swap from a Shadow Stack Location", + "line_range": [ + 594, + 598 + ] + }, + { + "text": ".`SSAMOSWAP.W` for RV64 [listing] ---- if privilegemode != M && menvcfg.SSE 0 raise illegal-instruction exception else if S-mode not implemented raise illegal-instruction exception else if privilegemode U && senvcfg.SSE 0 raise illegal-instruction exception else if privilegemode VS && henvcfg.SSE 0 raise virtual-instruction exception else if privilegemode VU && senvcfg.SSE 0 raise virtual-instruction exception else temp[31:0] = mem[X(rs1)] X(rd) = SignExtend(temp[31:0]) mem[X(rs1)] = X(rs2)[31:0] endif ----", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Atomic Swap from a Shadow Stack Location", + "line_range": [ + 600, + 618 + ] + }, + { + "text": "Just as for AMOs in the A extension, `SSAMOSWAP.W/D` requires that the address held in `rs1` be naturally aligned to the size of the operand (i.e., eight-byte aligned for doublewords, and four-byte aligned for words).", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Atomic Swap from a Shadow Stack Location", + "line_range": [ + 620, + 624 + ] + }, + { + "text": "The same exception options apply if the address is not naturally aligned.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Atomic Swap from a Shadow Stack Location", + "line_range": [ + 620, + 624 + ] + }, + { + "text": "Just as for AMOs in the A extension, `SSAMOSWAP.W/D` optionally provides release consistency semantics, using the `aq` and `rl` bits, to help implement multiprocessor synchronization.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Atomic Swap from a Shadow Stack Location", + "line_range": [ + 626, + 629 + ] + }, + { + "text": "An `SSAMOSWAP.W/D` operation has acquire semantics if `aq=1` and release semantics if `rl=1`.", + "section": "Preamble > Control-flow Integrity (CFI) > Landing Pad (Zicfilp) > Shadow Stack (Zicfiss) > Atomic Swap from a Shadow Stack Location", + "line_range": [ + 626, + 629 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__unpriv__cmo.json b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__cmo.json new file mode 100644 index 0000000000..5007ef6b8a --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__cmo.json @@ -0,0 +1,1622 @@ +{ + "source_file": "src/unpriv/cmo.adoc", + "total": 202, + "sentences": [ + { + "text": "The semantics of each instruction in the chapter is expressed in a SAIL-like syntax.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics", + "line_range": [ + 5, + 6 + ] + }, + { + "text": "[intro-cmo,reftext=\"Introduction\"]", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics", + "line_range": [ + 8, + 8 + ] + }, + { + "text": "Cache-management operation (or CMO) instructions perform operations on copies of data in the memory hierarchy.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Introduction", + "line_range": [ + 11, + 15 + ] + }, + { + "text": "In general, CMO instructions operate on cached copies of data, but in some cases, a CMO instruction may operate on memory locations directly.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Introduction", + "line_range": [ + 11, + 15 + ] + }, + { + "text": "Furthermore, CMO instructions are grouped by operation into the following classes:", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Introduction", + "line_range": [ + 11, + 15 + ] + }, + { + "text": "A management instruction manipulates cached copies of data with respect to a set of agents that can access the data * A zero instruction zeros out a range of memory locations, potentially allocating cached copies of data in one or more caches * A prefetch instruction indicates to hardware that data at a given memory location may be accessed in the near future, potentially allocating cached copies of data in one or more caches", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Introduction", + "line_range": [ + 17, + 23 + ] + }, + { + "text": "This chapter introduces a base set of CMO ISA extensions that operate specifically on cache blocks or the memory locations corresponding to a cache block; these are known as cache-block operation (or CBO) instructions.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Introduction", + "line_range": [ + 25, + 29 + ] + }, + { + "text": "Each of the above classes of instructions represents an extension in this specification:", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Introduction", + "line_range": [ + 25, + 29 + ] + }, + { + "text": "The Zicbom extension defines a set of cache-block management instructions: `CBO.INVAL`, `CBO.CLEAN`, and `CBO.FLUSH` * The Zicboz extension defines a cache-block zero instruction: `CBO.ZERO` * The Zicbop extension defines a set of cache-block prefetch instructions: `PREFETCH.R`, `PREFETCH.W`, and `PREFETCH.I`", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Introduction", + "line_range": [ + 31, + 35 + ] + }, + { + "text": "The execution behavior of the above instructions is also modified by CSR state added by this specification.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Introduction", + "line_range": [ + 37, + 38 + ] + }, + { + "text": "The remainder of this chapter provides general background information on CMO instructions and describes each of the above ISA extensions.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Introduction", + "line_range": [ + 40, + 41 + ] + }, + { + "text": "[background,reftext=\"Background\"]", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Introduction", + "line_range": [ + 43, + 43 + ] + }, + { + "text": "This chapter provides information common to all CMO extensions.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Background", + "line_range": [ + 46, + 46 + ] + }, + { + "text": "[memory-caches,reftext=\"Memory and Caches\"]", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Background", + "line_range": [ + 48, + 48 + ] + }, + { + "text": "A memory location is a physical resource in a system uniquely identified by a physical address.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Background > Memory and Caches", + "line_range": [ + 51, + 53 + ] + }, + { + "text": "An agent is a logic block, such as a RISC-V hart, accelerator, I/O device, etc., that can access a given memory location.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Background > Memory and Caches", + "line_range": [ + 51, + 53 + ] + }, + { + "text": "A load operation (or store operation) is performed by an agent to consume (or modify) the data at a given memory location.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Background > Memory and Caches", + "line_range": [ + 55, + 60 + ] + }, + { + "text": "Load and store operations are performed as a result of explicit memory accesses to that memory location.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Background > Memory and Caches", + "line_range": [ + 55, + 60 + ] + }, + { + "text": "Additionally, a read transfer from memory fetches the data at the memory location, while a write transfer to memory updates the data at the memory location.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Background > Memory and Caches", + "line_range": [ + 55, + 60 + ] + }, + { + "text": "A cache is a structure that buffers copies of data to reduce average memory latency.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Background > Memory and Caches", + "line_range": [ + 62, + 65 + ] + }, + { + "text": "Any number of caches may be interspersed between an agent and a memory location, and load and store operations from an agent may be satisfied by a cache instead of the memory location.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Background > Memory and Caches", + "line_range": [ + 62, + 65 + ] + }, + { + "text": "Caches organize copies of data into cache blocks, each of which represents a contiguous, naturally aligned power-of-two (or NAPOT) range of memory locations. A cache block is identified by any of the physical addresses corresponding to the underlying memory locations.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Background > Memory and Caches", + "line_range": [ + 67, + 74 + ] + }, + { + "text": "The capacity and organization of a cache and the size of a cache block are both implementation-specific, and the execution environment provides software a means to discover information about the caches and cache blocks in a system.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Background > Memory and Caches", + "line_range": [ + 67, + 74 + ] + }, + { + "text": "In the initial set of CMO extensions, the size of a cache block shall be uniform throughout the system.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Background > Memory and Caches", + "line_range": [ + 67, + 74 + ] + }, + { + "text": "Implementation techniques such as speculative execution or hardware prefetching may cause a given cache to allocate or deallocate a copy of a cache block at any time, provided the corresponding physical addresses are accessible according to the supported access type PMA and are cacheable according to the cacheability PMA.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Background > Memory and Caches", + "line_range": [ + 76, + 84 + ] + }, + { + "text": "Allocating a copy of a cache block results in a read transfer from another cache or from memory, while deallocating a copy of a cache block may result in a write transfer to another cache or to memory depending on whether the data in the copy were modified by a store operation.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Background > Memory and Caches", + "line_range": [ + 76, + 84 + ] + }, + { + "text": "Additional details are discussed in .", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Background > Memory and Caches", + "line_range": [ + 76, + 84 + ] + }, + { + "text": "A CBO instruction causes one or more operations to be performed on the cache blocks identified by the instruction.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Background > Cache-Block Operations", + "line_range": [ + 88, + 91 + ] + }, + { + "text": "In general, a CBO instruction may identify one or more cache blocks; however, in the initial set of CMO extensions, CBO instructions identify a single cache block only.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Background > Cache-Block Operations", + "line_range": [ + 88, + 91 + ] + }, + { + "text": "A cache-block management instruction performs one of the following operations, relative to the copy of a given cache block allocated in a given cache:", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Background > Cache-Block Operations", + "line_range": [ + 93, + 94 + ] + }, + { + "text": "An invalidate operation deallocates the copy of the cache block", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Background > Cache-Block Operations", + "line_range": [ + 96, + 96 + ] + }, + { + "text": "A clean operation performs a write transfer to another cache or to memory if the data in the copy of the cache block have been modified by a store operation", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Background > Cache-Block Operations", + "line_range": [ + 98, + 100 + ] + }, + { + "text": "A flush operation atomically performs a clean operation followed by an invalidate operation", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Background > Cache-Block Operations", + "line_range": [ + 102, + 103 + ] + }, + { + "text": "Additional details, including the actual operation performed by a given cache-block management instruction, are described in .", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Background > Cache-Block Operations", + "line_range": [ + 105, + 106 + ] + }, + { + "text": "A cache-block zero instruction performs a set of store operations that write zeros to the set of bytes corresponding to a cache block.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Background > Cache-Block Operations", + "line_range": [ + 108, + 114 + ] + }, + { + "text": "Unless specified otherwise, the store operations generated by a cache-block zero instruction have the same general properties and behaviors that other store instructions in the architecture have.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Background > Cache-Block Operations", + "line_range": [ + 108, + 114 + ] + }, + { + "text": "An implementation may or may not update the entire set of bytes atomically with a single store operation.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Background > Cache-Block Operations", + "line_range": [ + 108, + 114 + ] + }, + { + "text": "Additional details are described in .", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Background > Cache-Block Operations", + "line_range": [ + 108, + 114 + ] + }, + { + "text": "A cache-block prefetch instruction is a HINT to the hardware that software expects to perform a particular type of memory access in the near future.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Background > Cache-Block Operations", + "line_range": [ + 116, + 118 + ] + }, + { + "text": "Additional details are described in .", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Background > Cache-Block Operations", + "line_range": [ + 116, + 118 + ] + }, + { + "text": "[coherent-agents-caches,reftext=\"Coherent Agents and Caches\"]", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Background > Cache-Block Operations", + "line_range": [ + 120, + 120 + ] + }, + { + "text": "For a given memory location, a set of coherent agents consists of the agents for which all of the following hold:", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches", + "line_range": [ + 123, + 124 + ] + }, + { + "text": "Store operations from all agents in the set appear to be serialized with respect to each other * Store operations from all agents in the set eventually appear to all other agents in the set * A load operation from an agent in the set returns data from a store operation from an agent in the set (or from the initial data in memory)", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches", + "line_range": [ + 126, + 131 + ] + }, + { + "text": "The coherent agents within such a set shall access a given memory location with the same physical address and the same physical memory attributes; however, if the coherence PMA for a given agent indicates a given memory location is not coherent, that agent shall not be a member of a set of coherent agents with any other agent for that memory location and shall be the sole member of a set of coherent agents consisting of itself.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches", + "line_range": [ + 133, + 138 + ] + }, + { + "text": "An agent who is a member of a set of coherent agents is said to be coherent with respect to the other agents in the set.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches", + "line_range": [ + 140, + 143 + ] + }, + { + "text": "On the other hand, an agent who is not a member is said to be non-coherent with respect to the agents in the set.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches", + "line_range": [ + 140, + 143 + ] + }, + { + "text": "Caches introduce the possibility that multiple copies of a given cache block may be present in a system at the same time.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches", + "line_range": [ + 145, + 151 + ] + }, + { + "text": "An implementation-specific mechanism keeps these copies coherent with respect to the load and store operations from the agents in the set of coherent agents.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches", + "line_range": [ + 145, + 151 + ] + }, + { + "text": "Additionally, if a coherent agent in the set executes a CBO instruction that specifies the cache block, the resulting operation shall apply to any and all of the copies in the caches that can be accessed by the load and store operations from the coherent agents.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches", + "line_range": [ + 145, + 151 + ] + }, + { + "text": "The set of caches subject to the above mechanism form a set of coherent caches, and each coherent cache has the following behaviors, assuming all operations are performed by the agents in a set of coherent agents:", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches", + "line_range": [ + 153, + 155 + ] + }, + { + "text": "A coherent cache is permitted to allocate and deallocate copies of a cache block and perform read and write transfers as described in", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches", + "line_range": [ + 157, + 158 + ] + }, + { + "text": "A coherent cache is permitted to perform a write transfer to memory provided that a store operation has modified the data in the cache block since the most recent invalidate, clean, or flush operation on the cache block", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches", + "line_range": [ + 160, + 162 + ] + }, + { + "text": "At least one coherent cache is responsible for performing a write transfer to memory once a store operation has modified the data in the cache block until the next invalidate, clean, or flush operation on the cache block, after which no coherent cache is responsible (or permitted) to perform a write transfer to memory until the next store operation has modified the data in the cache block", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches", + "line_range": [ + 164, + 168 + ] + }, + { + "text": "A coherent cache is required to perform a write transfer to memory if a store operation has modified the data in the cache block since the most recent invalidate, clean, or flush operation on the cache block and if the next clean or flush operation requires a write transfer to memory", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches", + "line_range": [ + 170, + 173 + ] + }, + { + "text": "A non-coherent agent may initiate a cache-block operation that operates on the set of coherent caches accessed by a set of coherent agents.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches", + "line_range": [ + 175, + 177 + ] + }, + { + "text": "The mechanism to perform such an operation is implementation-specific.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches", + "line_range": [ + 175, + 177 + ] + }, + { + "text": "The preserved program order (abbreviated PPO) rules are defined by the RVWMO memory ordering model.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Memory Ordering > Preserved Program Order", + "line_range": [ + 183, + 185 + ] + }, + { + "text": "How the operations resulting from CMO instructions fit into these rules is described below.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Memory Ordering > Preserved Program Order", + "line_range": [ + 183, + 185 + ] + }, + { + "text": "For cache-block management instructions, the resulting invalidate, clean, and flush operations behave as stores in the PPO rules subject to one additional overlapping address rule.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Memory Ordering > Preserved Program Order", + "line_range": [ + 187, + 190 + ] + }, + { + "text": "Specifically, if a precedes b in program order, then a will precede b in the global memory order if:", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Memory Ordering > Preserved Program Order", + "line_range": [ + 187, + 190 + ] + }, + { + "text": "a is an invalidate, clean, or flush, b is a load, and a and b access overlapping memory addresses", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Memory Ordering > Preserved Program Order", + "line_range": [ + 192, + 193 + ] + }, + { + "text": "Additionally, invalidate, clean, and flush operations are classified as W or O (depending on the physical memory attributes for the corresponding physical addresses) for the purposes of predecessor and successor sets in `FENCE` instructions.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Memory Ordering > Preserved Program Order", + "line_range": [ + 195, + 199 + ] + }, + { + "text": "These operations are not ordered by other instructions that order stores, e.g. `FENCE.I` and `SFENCE.VMA`.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Memory Ordering > Preserved Program Order", + "line_range": [ + 195, + 199 + ] + }, + { + "text": "For cache-block zero instructions, the resulting store operations behave as stores in the PPO rules and are ordered by other instructions that order stores.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Memory Ordering > Preserved Program Order", + "line_range": [ + 201, + 202 + ] + }, + { + "text": "Finally, for cache-block prefetch instructions, the resulting operations are not ordered by the PPO rules nor are they ordered by any other ordering instructions.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Memory Ordering > Preserved Program Order", + "line_range": [ + 204, + 206 + ] + }, + { + "text": "An invalidate operation may change the set of values that can be returned by a load.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Memory Ordering > Load Values", + "line_range": [ + 210, + 211 + ] + }, + { + "text": "In particular, an additional condition is added to the Load Value Axiom:", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Memory Ordering > Load Values", + "line_range": [ + 210, + 211 + ] + }, + { + "text": "If an invalidate operation i precedes a load r and operates on a byte x returned by r, and no store to x appears between i and r in program order or in the global memory order, then r returns any of the following values for x:", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Memory Ordering > Load Values", + "line_range": [ + 213, + 216 + ] + }, + { + "text": "If no clean or flush operations on x precede i in the global memory order, either the initial value of x or the value of any store to x that precedes i", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Memory Ordering > Load Values", + "line_range": [ + 218, + 220 + ] + }, + { + "text": "If no store to x precedes a clean or flush operation on x in the global memory order and if the clean or flush operation on x precedes i in the global memory order, either the initial value of x or the value of any store to x that precedes i", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Memory Ordering > Load Values", + "line_range": [ + 222, + 225 + ] + }, + { + "text": "If a store to x precedes a clean or flush operation on x in the global memory order and if the clean or flush operation on x precedes i in the global memory order, either the value of the latest store to x that precedes the latest clean or flush operation on x or the value of any store to x that both precedes i and succeeds the latest clean or flush operation on x that precedes i", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Memory Ordering > Load Values", + "line_range": [ + 227, + 232 + ] + }, + { + "text": "The value of any store to x by a non-coherent agent regardless of the above conditions", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Memory Ordering > Load Values", + "line_range": [ + 234, + 235 + ] + }, + { + "text": "Execution of certain CMO instructions may result in traps due to CSR state, described in the section, or due to the address translation and protection mechanisms.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Traps", + "line_range": [ + 239, + 242 + ] + }, + { + "text": "The trapping behavior of CMO instructions is described in the following sections.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Traps", + "line_range": [ + 239, + 242 + ] + }, + { + "text": "Cache-block management instructions and cache-block zero instructions may raise illegal-instruction exceptions or virtual-instruction exceptions depending on the current privilege mode and the state of the CMO control registers described in the section.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Traps > Illegal-Instruction and Virtual-Instruction Exceptions", + "line_range": [ + 246, + 249 + ] + }, + { + "text": "Cache-block prefetch instructions raise neither illegal-instruction exceptions nor virtual-instruction exceptions.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Traps > Illegal-Instruction and Virtual-Instruction Exceptions", + "line_range": [ + 251, + 252 + ] + }, + { + "text": "Similar to load and store instructions, CMO instructions are explicit memory access instructions that compute an effective address.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Traps > Page-Fault, Guest-Page-Fault, and Access-Fault Exceptions", + "line_range": [ + 256, + 260 + ] + }, + { + "text": "The effective address is ultimately translated into a physical address based on the privilege mode and the enabled translation mechanisms, and the CMO extensions impose the following constraints on the physical addresses in a given cache block:", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Traps > Page-Fault, Guest-Page-Fault, and Access-Fault Exceptions", + "line_range": [ + 256, + 260 + ] + }, + { + "text": "The PMP access control bits shall be the same for all physical addresses in the cache block, and if write permission is granted by the PMP access control bits, read permission shall also be granted", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Traps > Page-Fault, Guest-Page-Fault, and Access-Fault Exceptions", + "line_range": [ + 262, + 264 + ] + }, + { + "text": "The PMAs shall be the same for all physical addresses in the cache block, and if write permission is granted by the supported access type PMAs, read permission shall also be granted", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Traps > Page-Fault, Guest-Page-Fault, and Access-Fault Exceptions", + "line_range": [ + 266, + 268 + ] + }, + { + "text": "If the above constraints are not met, the behavior of a CBO instruction is UNSPECIFIED.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Traps > Page-Fault, Guest-Page-Fault, and Access-Fault Exceptions", + "line_range": [ + 270, + 271 + ] + }, + { + "text": "The Zicboz extension introduces an additional supported access type PMA for cache-block zero instructions.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Traps > Page-Fault, Guest-Page-Fault, and Access-Fault Exceptions", + "line_range": [ + 273, + 276 + ] + }, + { + "text": "Main memory regions are required to support accesses by cache-block zero instructions; however, I/O regions may specify whether accesses by cache-block zero instructions are supported.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Traps > Page-Fault, Guest-Page-Fault, and Access-Fault Exceptions", + "line_range": [ + 273, + 276 + ] + }, + { + "text": "A cache-block management instruction is permitted to access the specified cache block whenever a load instruction or store instruction is permitted to access the corresponding physical addresses.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Traps > Page-Fault, Guest-Page-Fault, and Access-Fault Exceptions", + "line_range": [ + 278, + 288 + ] + }, + { + "text": "If neither a load instruction nor store instruction is permitted to access the physical addresses, but an instruction fetch is permitted to access the physical addresses, whether a cache-block management instruction is permitted to access the cache block is UNSPECIFIED.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Traps > Page-Fault, Guest-Page-Fault, and Access-Fault Exceptions", + "line_range": [ + 278, + 288 + ] + }, + { + "text": "If access to the cache block is not permitted, a cache-block management instruction raises a store page-fault or store guest-page-fault exception if address translation does not permit any access or raises a store access-fault exception otherwise.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Traps > Page-Fault, Guest-Page-Fault, and Access-Fault Exceptions", + "line_range": [ + 278, + 288 + ] + }, + { + "text": "During address translation, the instruction also checks the accessed bit and may either raise an exception or set the bit as required.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Traps > Page-Fault, Guest-Page-Fault, and Access-Fault Exceptions", + "line_range": [ + 278, + 288 + ] + }, + { + "text": "A cache-block zero instruction is permitted to access the specified cache block whenever a store instruction is permitted to access the corresponding physical addresses and when the PMAs indicate that cache-block zero instructions are a supported access type.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Traps > Page-Fault, Guest-Page-Fault, and Access-Fault Exceptions", + "line_range": [ + 290, + 298 + ] + }, + { + "text": "If access to the cache block is not permitted, a cache-block zero instruction raises a store page-fault or store guest-page-fault exception if address translation does not permit write access or raises a store access-fault exception otherwise.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Traps > Page-Fault, Guest-Page-Fault, and Access-Fault Exceptions", + "line_range": [ + 290, + 298 + ] + }, + { + "text": "During address translation, the instruction also checks the accessed and dirty bits and may either raise an exception or set the bits as required.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Traps > Page-Fault, Guest-Page-Fault, and Access-Fault Exceptions", + "line_range": [ + 290, + 298 + ] + }, + { + "text": "A cache-block prefetch instruction is permitted to access the specified cache block whenever a load instruction, store instruction, or instruction fetch is permitted to access the corresponding physical addresses.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Traps > Page-Fault, Guest-Page-Fault, and Access-Fault Exceptions", + "line_range": [ + 300, + 306 + ] + }, + { + "text": "If access to the cache block is not permitted, a cache-block prefetch instruction does not raise any exceptions and shall not access any caches or memory.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Traps > Page-Fault, Guest-Page-Fault, and Access-Fault Exceptions", + "line_range": [ + 300, + 306 + ] + }, + { + "text": "During address translation, the instruction does not check the accessed and dirty bits and neither raises an exception nor sets the bits.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Traps > Page-Fault, Guest-Page-Fault, and Access-Fault Exceptions", + "line_range": [ + 300, + 306 + ] + }, + { + "text": "When a page-fault, guest-page-fault, or access-fault exception is taken, the relevant *tval CSR is written with the faulting effective address (i.e. the value of rs1).", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Traps > Page-Fault, Guest-Page-Fault, and Access-Fault Exceptions", + "line_range": [ + 308, + 310 + ] + }, + { + "text": "CMO instructions do not generate address-misaligned exceptions.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Traps > Address-Misaligned Exceptions", + "line_range": [ + 314, + 315 + ] + }, + { + "text": "Unless otherwise defined by the debug architecture specification, the behavior of trigger modules with respect to CMO instructions is UNSPECIFIED.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Traps > Breakpoint Exceptions and Debug Mode Entry", + "line_range": [ + 319, + 320 + ] + }, + { + "text": "For the purposes of writing the `mtinst` or `htinst` register on a trap, the following standard transformation is defined for cache-block management instructions and cache-block zero instructions:", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Traps > Hypervisor Extension", + "line_range": [ + 324, + 327 + ] + }, + { + "text": "[wavedrom, , svg] .... {reg:[ { bits: 7, name: 'opcode'}, { bits: 5, name: 0x0 }, { bits: 3, name: 'funct3'}, { bits: 5, name: 0x0}, { bits: 12, name: 'operation'}, ]} ....", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Traps > Hypervisor Extension", + "line_range": [ + 329, + 338 + ] + }, + { + "text": "The `operation` field corresponds to the 12 most significant bits of the trapping instruction.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Traps > Hypervisor Extension", + "line_range": [ + 340, + 341 + ] + }, + { + "text": "The following event is added to the list of events that satisfy the eventuality guarantee provided by constrained LR/SC loops, as defined in the A extension:", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Effects on Constrained LR/SC Loops", + "line_range": [ + 345, + 346 + ] + }, + { + "text": "Some other hart executes a cache-block management instruction or a cache-block zero instruction to the reservation set of the LR instruction in H's constrained LR/SC loop.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Effects on Constrained LR/SC Loops", + "line_range": [ + 348, + 350 + ] + }, + { + "text": "The initial set of CMO extensions requires the following information to be discovered by software:", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Software Discovery", + "line_range": [ + 354, + 355 + ] + }, + { + "text": "The size of the cache block for management and prefetch instructions * The size of the cache block for zero instructions * CBIE support at each privilege level", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Software Discovery", + "line_range": [ + 357, + 359 + ] + }, + { + "text": "Other general cache characteristics may also be specified in the discovery mechanism.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Software Discovery", + "line_range": [ + 361, + 362 + ] + }, + { + "text": "[csrstate,reftext=\"Control and Status Register State\"]", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Coherent Agents and Caches > Software Discovery", + "line_range": [ + 364, + 364 + ] + }, + { + "text": "The x{csrname} registers control CBO instruction execution based on the current privilege mode and the state of the appropriate CSRs, as detailed below.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > CSR controls for CMO instructions", + "line_range": [ + 367, + 368 + ] + }, + { + "text": "A `CBO.INVAL` instruction executes or raises either an illegal-instruction exception or a virtual-instruction exception based on the state of the `x{csrname}.CBIE` fields:", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > CSR controls for CMO instructions", + "line_range": [ + 370, + 373 + ] + }, + { + "text": "[source,sail,subs=\"attributes+\"] --", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > CSR controls for CMO instructions", + "line_range": [ + 375, + 376 + ] + }, + { + "text": "A `CBO.CLEAN` or `CBO.FLUSH` instruction executes or raises an illegal-instruction or virtual-instruction exception based on the state of the `x{csrname}.CBCFE` bits:", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > CSR controls for CMO instructions", + "line_range": [ + 408, + 411 + ] + }, + { + "text": "[source,sail,subs=\"attributes+\"] --", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > CSR controls for CMO instructions", + "line_range": [ + 413, + 414 + ] + }, + { + "text": "Finally, a `CBO.ZERO` instruction executes or raises an illegal-instruction or virtual-instruction exception based on the state of the `x{csrname}.CBZE` bits:", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > CSR controls for CMO instructions", + "line_range": [ + 436, + 438 + ] + }, + { + "text": "[source,sail,subs=\"attributes+\"] --", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > CSR controls for CMO instructions", + "line_range": [ + 440, + 441 + ] + }, + { + "text": "The CBIE/CBCFE/CBZE fields in each `x{csrname}` register do not affect the read and write behavior of the same fields in the other `x{csrname}` registers.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > CSR controls for CMO instructions", + "line_range": [ + 463, + 465 + ] + }, + { + "text": "Each `x{csrname}` register is WARL; however, software should determine the legal values from the execution environment discovery mechanism.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > CSR controls for CMO instructions", + "line_range": [ + 467, + 468 + ] + }, + { + "text": "[extensions,reftext=\"Extensions\"]", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > CSR controls for CMO instructions", + "line_range": [ + 470, + 470 + ] + }, + { + "text": "CMO instructions are defined in the following extensions:", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Extensions", + "line_range": [ + 474, + 474 + ] + }, + { + "text": "[Zicbom,reftext=\"Cache-Block Management Instructions\"]", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Extensions", + "line_range": [ + 480, + 480 + ] + }, + { + "text": "Cache-block management instructions enable software running on a set of coherent agents to communicate with a set of non-coherent agents by performing one of the following operations:", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Extensions > Cache-Block Management Instructions", + "line_range": [ + 483, + 485 + ] + }, + { + "text": "An invalidate operation makes data from store operations performed by a set of non-coherent agents visible to the set of coherent agents at a point common to both sets by deallocating all copies of a cache block from the set of coherent caches up to that point", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Extensions > Cache-Block Management Instructions", + "line_range": [ + 487, + 490 + ] + }, + { + "text": "A clean operation makes data from store operations performed by the set of coherent agents visible to a set of non-coherent agents at a point common to both sets by performing a write transfer of a copy of a cache block to that point provided a coherent agent performed a store operation that modified the data in the cache block since the previous invalidate, clean, or flush operation on the cache block", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Extensions > Cache-Block Management Instructions", + "line_range": [ + 492, + 497 + ] + }, + { + "text": "A flush operation atomically performs a clean operation followed by an invalidate operation", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Extensions > Cache-Block Management Instructions", + "line_range": [ + 499, + 500 + ] + }, + { + "text": "In the Zicbom extension, the instructions operate to a point common to all agents in the system.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Extensions > Cache-Block Management Instructions", + "line_range": [ + 502, + 506 + ] + }, + { + "text": "In other words, an invalidate operation ensures that store operations from all non-coherent agents visible to agents in the set of coherent agents, and a clean operation ensures that store operations from coherent agents visible to all non-coherent agents.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Extensions > Cache-Block Management Instructions", + "line_range": [ + 502, + 506 + ] + }, + { + "text": "These instructions operate on the cache block whose effective address is specified in rs1.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Extensions > Cache-Block Management Instructions", + "line_range": [ + 508, + 510 + ] + }, + { + "text": "The effective address is translated into a corresponding physical address by the appropriate translation mechanisms.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Extensions > Cache-Block Management Instructions", + "line_range": [ + 508, + 510 + ] + }, + { + "text": "The following instructions comprise the Zicbom extension:", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Extensions > Cache-Block Management Instructions", + "line_range": [ + 512, + 512 + ] + }, + { + "text": "| |RV32 |RV64 |Mnemonic |Instruction", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Extensions > Cache-Block Management Instructions", + "line_range": [ + 514, + 519 + ] + }, + { + "text": "|{check} |{check} |cbo.clean base |", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Extensions > Cache-Block Management Instructions", + "line_range": [ + 521, + 524 + ] + }, + { + "text": "|{check} |{check} |cbo.flush base |", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Extensions > Cache-Block Management Instructions", + "line_range": [ + 526, + 529 + ] + }, + { + "text": "|{check} |{check} |cbo.inval base |", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Extensions > Cache-Block Management Instructions", + "line_range": [ + 531, + 534 + ] + }, + { + "text": "[Zicboz,reftext=\"Cache-Block Zero Instructions\"]", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Extensions > Cache-Block Management Instructions", + "line_range": [ + 538, + 538 + ] + }, + { + "text": "Cache-block zero instructions store zeros to the set of bytes corresponding to a cache block.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Extensions > Cache-Block Zero Instructions", + "line_range": [ + 541, + 543 + ] + }, + { + "text": "An implementation may update the bytes in any order and with any granularity and atomicity, including individual bytes.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Extensions > Cache-Block Zero Instructions", + "line_range": [ + 541, + 543 + ] + }, + { + "text": "These instructions operate on the cache block, or the memory locations corresponding to the cache block, whose effective address is specified in rs1.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Extensions > Cache-Block Zero Instructions", + "line_range": [ + 545, + 548 + ] + }, + { + "text": "The effective address is translated into a corresponding physical address by the appropriate translation mechanisms.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Extensions > Cache-Block Zero Instructions", + "line_range": [ + 545, + 548 + ] + }, + { + "text": "The following instructions comprise the Zicboz extension:", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Extensions > Cache-Block Zero Instructions", + "line_range": [ + 550, + 550 + ] + }, + { + "text": "| |RV32 |RV64 |Mnemonic |Instruction", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Extensions > Cache-Block Zero Instructions", + "line_range": [ + 552, + 557 + ] + }, + { + "text": "|{check} |{check} |cbo.zero base |", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Extensions > Cache-Block Zero Instructions", + "line_range": [ + 559, + 562 + ] + }, + { + "text": "[Zicbop,reftext=\"Cache-Block Prefetch Instructions\"]", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Extensions > Cache-Block Zero Instructions", + "line_range": [ + 566, + 566 + ] + }, + { + "text": "Cache-block prefetch instructions are HINTs to the hardware to indicate that software intends to perform a particular type of memory access in the near future.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Extensions > Cache-Block Prefetch Instructions", + "line_range": [ + 569, + 572 + ] + }, + { + "text": "The types of memory accesses are instruction fetch, data read (i.e. load), and data write (i.e. store).", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Extensions > Cache-Block Prefetch Instructions", + "line_range": [ + 569, + 572 + ] + }, + { + "text": "These instructions operate on the cache block whose effective address is the sum of the base address specified in rs1 and the sign-extended offset encoded in imm[11:0], where imm[4:0] shall equal `0b00000`.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Extensions > Cache-Block Prefetch Instructions", + "line_range": [ + 574, + 578 + ] + }, + { + "text": "The effective address is translated into a corresponding physical address by the appropriate translation mechanisms.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Extensions > Cache-Block Prefetch Instructions", + "line_range": [ + 574, + 578 + ] + }, + { + "text": "The following instructions comprise the Zicbop extension:", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Extensions > Cache-Block Prefetch Instructions", + "line_range": [ + 580, + 580 + ] + }, + { + "text": "| |RV32 |RV64 |Mnemonic |Instruction", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Extensions > Cache-Block Prefetch Instructions", + "line_range": [ + 582, + 587 + ] + }, + { + "text": "|{check} |{check} |prefetch.i offset(base) |", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Extensions > Cache-Block Prefetch Instructions", + "line_range": [ + 589, + 592 + ] + }, + { + "text": "|{check} |{check} |prefetch.r offset(base) |", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Extensions > Cache-Block Prefetch Instructions", + "line_range": [ + 594, + 597 + ] + }, + { + "text": "|{check} |{check} |prefetch.w offset(base) |", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Extensions > Cache-Block Prefetch Instructions", + "line_range": [ + 599, + 602 + ] + }, + { + "text": "[insns,reftext=\"Instructions\"]", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Extensions > Cache-Block Prefetch Instructions", + "line_range": [ + 606, + 606 + ] + }, + { + "text": "[insns-cboclean,reftext=\"Cache Block Clean\"]", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions", + "line_range": [ + 609, + 609 + ] + }, + { + "text": "Synopsis:: Perform a clean operation on a cache block", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > cbo.clean", + "line_range": [ + 612, + 613 + ] + }, + { + "text": "Mnemonic:: cbo.clean offset(base)", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > cbo.clean", + "line_range": [ + 615, + 616 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0xF, attr: ['MISC-MEM'] }, { bits: 5, name: 0x0 }, { bits: 3, name: 0x2, attr: ['CBO'] }, { bits: 5, name: 'rs1', attr: ['base'] }, { bits: 12, name: 0x001, attr: ['CBO.CLEAN'] }, ]} ....", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > cbo.clean", + "line_range": [ + 618, + 628 + ] + }, + { + "text": "A *cbo.clean* instruction performs a clean operation on the cache block whose effective address is the base address specified in rs1.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > cbo.clean", + "line_range": [ + 632, + 636 + ] + }, + { + "text": "The offset operand may be omitted; otherwise, any expression that computes the offset shall evaluate to zero.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > cbo.clean", + "line_range": [ + 632, + 636 + ] + }, + { + "text": "The instruction operates on the set of coherent caches accessed by the agent executing the instruction.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > cbo.clean", + "line_range": [ + 632, + 636 + ] + }, + { + "text": "[insns-cboflush,reftext=\"Cache Block Flush\"]", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > cbo.clean", + "line_range": [ + 638, + 638 + ] + }, + { + "text": "Synopsis:: Perform a flush operation on a cache block", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > cbo.flush", + "line_range": [ + 641, + 642 + ] + }, + { + "text": "Mnemonic:: cbo.flush offset(base)", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > cbo.flush", + "line_range": [ + 644, + 645 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0xF, attr: ['MISC-MEM'] }, { bits: 5, name: 0x0 }, { bits: 3, name: 0x2, attr: ['CBO'] }, { bits: 5, name: 'rs1', attr: ['base'] }, { bits: 12, name: 0x002, attr: ['CBO.FLUSH'] }, ]} ....", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > cbo.flush", + "line_range": [ + 647, + 657 + ] + }, + { + "text": "A *cbo.flush* instruction performs a flush operation on the cache block whose that contains the address specified in rs1.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > cbo.flush", + "line_range": [ + 661, + 666 + ] + }, + { + "text": "It is not required that rs1 is aligned to the size of a cache block.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > cbo.flush", + "line_range": [ + 661, + 666 + ] + }, + { + "text": "On faults, the faulting virtual address is considered to be the value in rs1, rather than the base address of the cache block.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > cbo.flush", + "line_range": [ + 661, + 666 + ] + }, + { + "text": "The instruction operates on the set of coherent caches accessed by the agent executing the instruction.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > cbo.flush", + "line_range": [ + 661, + 666 + ] + }, + { + "text": "The assembly offset operand may be omitted.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > cbo.flush", + "line_range": [ + 668, + 669 + ] + }, + { + "text": "If it isn't then any expression that computes the offset shall evaluate to zero.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > cbo.flush", + "line_range": [ + 668, + 669 + ] + }, + { + "text": "[insns-cboinval,reftext=\"Cache Block Invalidate\"]", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > cbo.flush", + "line_range": [ + 671, + 671 + ] + }, + { + "text": "Synopsis:: Perform an invalidate operation on a cache block", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > cbo.inval", + "line_range": [ + 674, + 675 + ] + }, + { + "text": "Mnemonic:: cbo.inval offset(base)", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > cbo.inval", + "line_range": [ + 677, + 678 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0xF, attr: ['MISC-MEM'] }, { bits: 5, name: 0x0 }, { bits: 3, name: 0x2, attr: ['CBO'] }, { bits: 5, name: 'rs1', attr: ['base'] }, { bits: 12, name: 0x000, attr: ['CBO.INVAL'] }, ]} ....", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > cbo.inval", + "line_range": [ + 680, + 690 + ] + }, + { + "text": "A *cbo.inval* instruction performs an invalidate operation on the cache block that contains the address specified in rs1.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > cbo.inval", + "line_range": [ + 694, + 699 + ] + }, + { + "text": "It is not required that rs1 is aligned to the size of a cache block.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > cbo.inval", + "line_range": [ + 694, + 699 + ] + }, + { + "text": "On faults, the faulting virtual address is considered to be the value in rs1, rather than the base address of the cache block.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > cbo.inval", + "line_range": [ + 694, + 699 + ] + }, + { + "text": "The instruction operates on the set of coherent caches accessed by the agent executing the instruction.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > cbo.inval", + "line_range": [ + 694, + 699 + ] + }, + { + "text": "Depending on CSR programming, the instruction may perform a flush operation instead of an invalidate operation.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > cbo.inval", + "line_range": [ + 701, + 702 + ] + }, + { + "text": "The assembly offset operand may be omitted.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > cbo.inval", + "line_range": [ + 704, + 705 + ] + }, + { + "text": "If it isn't then any expression that computes the offset shall evaluate to zero.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > cbo.inval", + "line_range": [ + 704, + 705 + ] + }, + { + "text": "[insns-cbozero,reftext=\"Cache Block Zero\"]", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > cbo.inval", + "line_range": [ + 707, + 707 + ] + }, + { + "text": "Synopsis:: Store zeros to the full set of bytes corresponding to a cache block", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > cbo.zero", + "line_range": [ + 710, + 711 + ] + }, + { + "text": "Mnemonic:: cbo.zero offset(base)", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > cbo.zero", + "line_range": [ + 713, + 714 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0xF, attr: ['MISC-MEM'] }, { bits: 5, name: 0x0 }, { bits: 3, name: 0x2, attr: ['CBO'] }, { bits: 5, name: 'rs1', attr: ['base'] }, { bits: 12, name: 0x004, attr: ['CBO.ZERO'] }, ]} ....", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > cbo.zero", + "line_range": [ + 716, + 726 + ] + }, + { + "text": "A *cbo.zero* instruction performs stores of zeros to the full set of bytes corresponding to the cache block that contains the address specified in rs1.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > cbo.zero", + "line_range": [ + 730, + 735 + ] + }, + { + "text": "It is not required that rs1 is aligned to the size of a cache block.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > cbo.zero", + "line_range": [ + 730, + 735 + ] + }, + { + "text": "On faults, the faulting virtual address is considered to be the value in rs1, rather than the base address of the cache block.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > cbo.zero", + "line_range": [ + 730, + 735 + ] + }, + { + "text": "An implementation may or may not update the entire set of bytes atomically.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > cbo.zero", + "line_range": [ + 730, + 735 + ] + }, + { + "text": "The assembly offset operand may be omitted.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > cbo.zero", + "line_range": [ + 737, + 739 + ] + }, + { + "text": "If it isn't then any expression that computes the offset shall evaluate to zero.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > cbo.zero", + "line_range": [ + 737, + 739 + ] + }, + { + "text": "[insns-prefetchi,reftext=\"Cache Block Prefetch for Instruction Fetch\"]", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > cbo.zero", + "line_range": [ + 741, + 741 + ] + }, + { + "text": "Synopsis:: Provide a HINT to hardware that a cache block is likely to be accessed by an instruction fetch in the near future", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > prefetch.i", + "line_range": [ + 744, + 746 + ] + }, + { + "text": "Mnemonic:: prefetch.i offset(base)", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > prefetch.i", + "line_range": [ + 748, + 749 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0x13, attr: ['OP-IMM'] }, { bits: 5, name: 0x0, attr: ['offset[4:0]'] }, { bits: 3, name: 0x6, attr: ['ORI'] }, { bits: 5, name: 'rs1', attr: ['base'] }, { bits: 5, name: 0x0, attr: ['PREFETCH.I'] }, { bits: 7, name: 'imm[11:5]', attr: ['offset[11:5]'] }, ]} ....", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > prefetch.i", + "line_range": [ + 751, + 762 + ] + }, + { + "text": "A *prefetch.i* instruction indicates to hardware that the cache block whose effective address is the sum of the base address specified in rs1 and the sign-extended offset encoded in imm[11:0], where imm[4:0] equals `0b00000`, is likely to be accessed by an instruction fetch in the near future.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > prefetch.i", + "line_range": [ + 766, + 770 + ] + }, + { + "text": "[insns-prefetchr,reftext=\"Cache Block Prefetch for Data Read\"]", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > prefetch.i", + "line_range": [ + 772, + 772 + ] + }, + { + "text": "Synopsis:: Provide a HINT to hardware that a cache block is likely to be accessed by a data read in the near future", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > prefetch.r", + "line_range": [ + 775, + 777 + ] + }, + { + "text": "Mnemonic:: prefetch.r offset(base)", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > prefetch.r", + "line_range": [ + 779, + 780 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0x13, attr: ['OP-IMM'] }, { bits: 5, name: 0x0, attr: ['offset[4:0]'] }, { bits: 3, name: 0x6, attr: ['ORI'] }, { bits: 5, name: 'rs1', attr: ['base'] }, { bits: 5, name: 0x1, attr: ['PREFETCH.R'] }, { bits: 7, name: 'imm[11:5]', attr: ['offset[11:5]'] }, ]} ....", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > prefetch.r", + "line_range": [ + 782, + 793 + ] + }, + { + "text": "A *prefetch.r* instruction indicates to hardware that the cache block whose effective address is the sum of the base address specified in rs1 and the sign-extended offset encoded in imm[11:0], where imm[4:0] equals `0b00000`, is likely to be accessed by a data read (i.e. load) in the near future.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > prefetch.r", + "line_range": [ + 797, + 801 + ] + }, + { + "text": "[insns-prefetchw,reftext=\"Cache Block Prefetch for Data Write\"]", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > prefetch.r", + "line_range": [ + 803, + 803 + ] + }, + { + "text": "Synopsis:: Provide a HINT to hardware that a cache block is likely to be accessed by a data write in the near future", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > prefetch.w", + "line_range": [ + 806, + 808 + ] + }, + { + "text": "Mnemonic:: prefetch.w offset(base)", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > prefetch.w", + "line_range": [ + 810, + 811 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0x13, attr: ['OP-IMM'] }, { bits: 5, name: 0x0, attr: ['offset[4:0]'] }, { bits: 3, name: 0x6, attr: ['ORI'] }, { bits: 5, name: 'rs1', attr: ['base'] }, { bits: 5, name: 0x3, attr: ['PREFETCH.W'] }, { bits: 7, name: 'imm[11:5]', attr: ['offset[11:5]'] }, ]} ....", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > prefetch.w", + "line_range": [ + 813, + 824 + ] + }, + { + "text": "A *prefetch.w* instruction indicates to hardware that the cache block whose effective address is the sum of the base address specified in rs1 and the sign-extended offset encoded in imm[11:0], where imm[4:0] equals `0b00000`, is likely to be accessed by a data write (i.e. store) in the near future.", + "section": "Preamble > Cache Management Operations (CMOs) > Pseudocode for instruction semantics > Instructions > prefetch.w", + "line_range": [ + 828, + 832 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__unpriv__code-examples.json b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__code-examples.json new file mode 100644 index 0000000000..3081d25bc2 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__code-examples.json @@ -0,0 +1,14 @@ +{ + "source_file": "src/unpriv/code-examples.adoc", + "total": 1, + "sentences": [ + { + "text": "This appendix contains code examples for various RISC-V extensions, including implementations of library routines that are expected to be performant across a range of RISC-V implementations.", + "section": "Preamble > RISC-V Assembly Code Examples", + "line_range": [ + 4, + 6 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__unpriv__d-st-ext.json b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__d-st-ext.json new file mode 100644 index 0000000000..ce35be9c3d --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__d-st-ext.json @@ -0,0 +1,222 @@ +{ + "source_file": "src/unpriv/d-st-ext.adoc", + "total": 27, + "sentences": [ + { + "text": "This chapter describes the D standard extension for double-precision floating-point, which adds computational instructions compliant with the IEEE 754-2008 arithmetic standard's binary64 format and operations.", + "section": "Preamble > \"D\" Extension for Double-Precision Floating-Point, Version 2.2", + "line_range": [ + 3, + 8 + ] + }, + { + "text": "The D extension depends on the F extension.", + "section": "Preamble > \"D\" Extension for Double-Precision Floating-Point, Version 2.2", + "line_range": [ + 3, + 8 + ] + }, + { + "text": "The D extension widens the 32 floating-point registers, `f0-f31`, to 64 bits (FLEN=64 in ).", + "section": "Preamble > \"D\" Extension for Double-Precision Floating-Point, Version 2.2 > D Register State", + "line_range": [ + 12, + 15 + ] + }, + { + "text": "The `f` registers can now hold either 32-bit or 64-bit floating-point values as described below in .", + "section": "Preamble > \"D\" Extension for Double-Precision Floating-Point, Version 2.2 > D Register State", + "line_range": [ + 12, + 15 + ] + }, + { + "text": "When multiple floating-point precisions are supported, then valid values of narrower n-bit types, n \"D\" Extension for Double-Precision Floating-Point, Version 2.2 > D Register State > NaN Boxing of Narrower Values", + "line_range": [ + 22, + 27 + ] + }, + { + "text": "The upper bits of a valid NaN-boxed value must be all 1s.", + "section": "Preamble > \"D\" Extension for Double-Precision Floating-Point, Version 2.2 > D Register State > NaN Boxing of Narrower Values", + "line_range": [ + 22, + 27 + ] + }, + { + "text": "Valid NaN-boxed n-bit values therefore appear as negative quiet NaNs (qNaNs) when viewed as any wider m-bit value, n < m {le} FLEN.", + "section": "Preamble > \"D\" Extension for Double-Precision Floating-Point, Version 2.2 > D Register State > NaN Boxing of Narrower Values", + "line_range": [ + 22, + 27 + ] + }, + { + "text": "Any operation that writes a narrower result to an 'f' register must write all 1s to the uppermost FLEN-n bits to yield a legal NaN-boxedvalue.", + "section": "Preamble > \"D\" Extension for Double-Precision Floating-Point, Version 2.2 > D Register State > NaN Boxing of Narrower Values", + "line_range": [ + 22, + 27 + ] + }, + { + "text": "Floating-point n-bit transfer operations move external values held in the IEEE 754-2008 formats into and out of the `f` registers, and comprise floating-point loads and stores (FLn/FSn) and floating-point move instructions (FMV.n.X/FMV.X.n). A narrower n-bit transfer, n \"D\" Extension for Double-Precision Floating-Point, Version 2.2 > D Register State > NaN Boxing of Narrower Values", + "line_range": [ + 29, + 38 + ] + }, + { + "text": "Apart from transfer operations described in the previous paragraph, all other floating-point operations on narrower n-bit operations, n \"D\" Extension for Double-Precision Floating-Point, Version 2.2 > D Register State > NaN Boxing of Narrower Values", + "line_range": [ + 40, + 47 + ] + }, + { + "text": "If so, the n least-significant bits of the input are used as the input value, otherwise the input value is treated as an n-bit canonical NaN.", + "section": "Preamble > \"D\" Extension for Double-Precision Floating-Point, Version 2.2 > D Register State > NaN Boxing of Narrower Values", + "line_range": [ + 40, + 47 + ] + }, + { + "text": "The FLD instruction loads a double-precision floating-point value from memory into floating-point register rd. FSD stores a double-precision value from the floating-point registers to memory.", + "section": "Preamble > \"D\" Extension for Double-Precision Floating-Point, Version 2.2 > D Register State > Double-Precision Load and Store Instructions", + "line_range": [ + 51, + 54 + ] + }, + { + "text": "FLD and FSD are only guaranteed to execute atomically if the effective address is naturally aligned and XLEN{ge}64.", + "section": "Preamble > \"D\" Extension for Double-Precision Floating-Point, Version 2.2 > D Register State > Double-Precision Load and Store Instructions", + "line_range": [ + 60, + 62 + ] + }, + { + "text": "FLD and FSD do not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved.", + "section": "Preamble > \"D\" Extension for Double-Precision Floating-Point, Version 2.2 > D Register State > Double-Precision Load and Store Instructions", + "line_range": [ + 64, + 66 + ] + }, + { + "text": "The double-precision floating-point computational instructions are defined analogously to their single-precision counterparts, but operate on double-precision operands and produce double-precision results.", + "section": "Preamble > \"D\" Extension for Double-Precision Floating-Point, Version 2.2 > D Register State > Double-Precision Floating-Point Computational Instructions", + "line_range": [ + 70, + 73 + ] + }, + { + "text": "Floating-point-to-integer and integer-to-floating-point conversion instructions are encoded in the OP-FP major opcode space. FCVT.W.D or FCVT.L.D converts a double-precision floating-point number in floating-point register rs1 to a signed 32-bit or 64-bit integer, respectively, in integer register rd. FCVT.D.W or FCVT.D.L converts a 32-bit or 64-bit signed integer, respectively, in integer register rs1 into a double-precision floating-point number in floating-point register rd. FCVT.WU.D, FCVT.LU.D, FCVT.D.WU, and FCVT.D.LU variants convert to or from unsigned integer values.", + "section": "Preamble > \"D\" Extension for Double-Precision Floating-Point, Version 2.2 > D Register State > Double-Precision Floating-Point Conversion and Move Instructions", + "line_range": [ + 81, + 93 + ] + }, + { + "text": "For RV64, FCVT.W[U].D sign-extends the 32-bit result. FCVT.L[U].D and FCVT.D.L[U] are RV64-only instructions.", + "section": "Preamble > \"D\" Extension for Double-Precision Floating-Point, Version 2.2 > D Register State > Double-Precision Floating-Point Conversion and Move Instructions", + "line_range": [ + 81, + 93 + ] + }, + { + "text": "The range of valid inputs for FCVT.int.D and the behavior for invalid inputs are the same as for FCVT.int.S.", + "section": "Preamble > \"D\" Extension for Double-Precision Floating-Point, Version 2.2 > D Register State > Double-Precision Floating-Point Conversion and Move Instructions", + "line_range": [ + 81, + 93 + ] + }, + { + "text": "All floating-point to integer and integer to floating-point conversion instructions round according to the rm field.", + "section": "Preamble > \"D\" Extension for Double-Precision Floating-Point, Version 2.2 > D Register State > Double-Precision Floating-Point Conversion and Move Instructions", + "line_range": [ + 95, + 97 + ] + }, + { + "text": "Note FCVT.D.W[U] always produces an exact result and is unaffected by rounding mode.", + "section": "Preamble > \"D\" Extension for Double-Precision Floating-Point, Version 2.2 > D Register State > Double-Precision Floating-Point Conversion and Move Instructions", + "line_range": [ + 95, + 97 + ] + }, + { + "text": "The double-precision to single-precision and single-precision to double-precision conversion instructions, FCVT.S.D and FCVT.D.S, are encoded in the OP-FP major opcode space and both the source and destination are floating-point registers.", + "section": "Preamble > \"D\" Extension for Double-Precision Floating-Point, Version 2.2 > D Register State > Double-Precision Floating-Point Conversion and Move Instructions", + "line_range": [ + 103, + 111 + ] + }, + { + "text": "The rs2 field encodes the datatype of the source, and the fmt field encodes the datatype of the destination. FCVT.S.D rounds according to the RM field; FCVT.D.S will never round.", + "section": "Preamble > \"D\" Extension for Double-Precision Floating-Point, Version 2.2 > D Register State > Double-Precision Floating-Point Conversion and Move Instructions", + "line_range": [ + 103, + 111 + ] + }, + { + "text": "Floating-point to floating-point sign-injection instructions, FSGNJ.D, FSGNJN.D, and FSGNJX.D are defined analogously to the single-precision sign-injection instruction. //FSGNJ.D, FSGNJN.D, and FSGNJX.D", + "section": "Preamble > \"D\" Extension for Double-Precision Floating-Point, Version 2.2 > D Register State > Double-Precision Floating-Point Conversion and Move Instructions", + "line_range": [ + 117, + 121 + ] + }, + { + "text": "For XLEN{ge}64 only, instructions are provided to move bit patterns between the floating-point and integer registers. FMV.X.D moves the double-precision value in floating-point register rs1 to a representation in the IEEE 754-2008 encoding in integer register rd. FMV.D.X moves the double-precision value encoded in the IEEE 754-2008 encoding from the integer register rs1 to the floating-point register rd.", + "section": "Preamble > \"D\" Extension for Double-Precision Floating-Point, Version 2.2 > D Register State > Double-Precision Floating-Point Conversion and Move Instructions", + "line_range": [ + 126, + 132 + ] + }, + { + "text": "FMV.X.D and FMV.D.X do not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved.", + "section": "Preamble > \"D\" Extension for Double-Precision Floating-Point, Version 2.2 > D Register State > Double-Precision Floating-Point Conversion and Move Instructions", + "line_range": [ + 134, + 136 + ] + }, + { + "text": "The double-precision floating-point compare instructions are defined analogously to their single-precision counterparts, but operate on double-precision operands.", + "section": "Preamble > \"D\" Extension for Double-Precision Floating-Point, Version 2.2 > D Register State > Double-Precision Floating-Point Compare Instructions", + "line_range": [ + 144, + 148 + ] + }, + { + "text": "The double-precision floating-point classify instruction, FCLASS.D, is defined analogously to its single-precision counterpart, but operates on double-precision operands.", + "section": "Preamble > \"D\" Extension for Double-Precision Floating-Point, Version 2.2 > D Register State > Double-Precision Floating-Point Classify Instruction", + "line_range": [ + 156, + 160 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__unpriv__f-st-ext.json b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__f-st-ext.json new file mode 100644 index 0000000000..42160c91ab --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__f-st-ext.json @@ -0,0 +1,678 @@ +{ + "source_file": "src/unpriv/f-st-ext.adoc", + "total": 84, + "sentences": [ + { + "text": "This chapter describes the F standard extension for single-precision floating-point, which adds computational instructions compliant with the 's binary32 format and operations.", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2", + "line_range": [ + 3, + 7 + ] + }, + { + "text": "The F extension depends on the \"Zicsr\" extension for control and status register access.", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2", + "line_range": [ + 3, + 7 + ] + }, + { + "text": "The F extension adds 32 floating-point registers, `f0-f31`, each 32 bits wide, and a floating-point control and status register `fcsr`, which contains the operating mode and exception status of the floating-point unit.", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State", + "line_range": [ + 11, + 20 + ] + }, + { + "text": "This additional state is shown in .", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State", + "line_range": [ + 11, + 20 + ] + }, + { + "text": "We use the term FLEN to describe the width of the floating-point registers in the RISC-V ISA, and FLEN=32 for the F single-precision floating-point extension.", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State", + "line_range": [ + 11, + 20 + ] + }, + { + "text": "Most floating-point instructions operate on values in the floating-point register file.", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State", + "line_range": [ + 11, + 20 + ] + }, + { + "text": "Floating-point load and store instructions transfer floating-point values between registers and memory.", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State", + "line_range": [ + 11, + 20 + ] + }, + { + "text": "Instructions to transfer values to and from the integer register file are also provided.", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State", + "line_range": [ + 11, + 20 + ] + }, + { + "text": ".RISC-V standard F extension single-precision floating-point state [cols=\"<,^,>\",options=\"header\",width=\"50%\",align=\"center\",grid=\"rows\"] | | [.small]FLEN-1| >| [.small]0 3+^| [.small]f0 3+^| [.small]f1 3+^| [.small]f2 3+^| [.small]f3 3+^| [.small]f4 3+^| [.small]f5 3+^| [.small]f6 3+^| [.small]f7 3+^| [.small]f8 3+^| [.small]f9 3+^| [.small]f10 3+^| [.small]f11 3+^| [.small]f12 3+^| [.small]f13 3+^| [.small]f14 3+^| [.small]f15 3+^| [.small]f16 3+^| [.small]f17 3+^| [.small]f18 3+^| [.small]f19 3+^| [.small]f20 3+^| [.small]f21 3+^| [.small]f22 3+^| [.small]f23 3+^| [.small]f24 3+^| [.small]f25 3+^| [.small]f26 3+^| [.small]f27 3+^| [.small]f28 3+^| [.small]f29 3+^| [.small]f30 3+^| [.small]f31 3+^| [.small]FLEN | [.small]31| >| [.small]0 3+^| [.small]fcsr 3+^| [.small]32 |", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State", + "line_range": [ + 22, + 63 + ] + }, + { + "text": "The floating-point control and status register, `fcsr`, is a RISC-V control and status register (CSR).", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Floating-Point Control and Status Register", + "line_range": [ + 67, + 71 + ] + }, + { + "text": "It is a 32-bit read/write register that selects the dynamic rounding mode for floating-point arithmetic operations and holds the accrued exception flags, as shown in .", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Floating-Point Control and Status Register", + "line_range": [ + 67, + 71 + ] + }, + { + "text": ".Floating-point control and status register include::images/wavedrom/float-csr.edn[]", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Floating-Point Control and Status Register", + "line_range": [ + 73, + 75 + ] + }, + { + "text": "The `fcsr` register can be read and written with the FRCSR and FSCSR instructions, which are assembler pseudoinstructions built on the underlying CSR access instructions. FRCSR reads `fcsr` by copying it into integer register rd. FSCSR swaps the value in `fcsr` by copying the original value into integer register rd, and then writing a new value obtained from integer register rs1 into `fcsr`.", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Floating-Point Control and Status Register", + "line_range": [ + 77, + 82 + ] + }, + { + "text": "The fields within the `fcsr` can also be accessed individually through different CSR addresses, and separate assembler pseudoinstructions are defined for these accesses.", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Floating-Point Control and Status Register", + "line_range": [ + 84, + 93 + ] + }, + { + "text": "The FRRM instruction reads the Rounding Mode field `frm` (`fcsr` bits 7--5) and copies it into the least-significant three bits of integer register rd, with zero in all other bits. FSRM swaps the value in `frm` by copying the original value into integer register rd, and then writing a new value obtained from the three least-significant bits of integer register rs1 into `frm`. FRFLAGS and FSFLAGS are defined analogously for the Accrued Exception Flags field `fflags` (`fcsr` bits 4--0).", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Floating-Point Control and Status Register", + "line_range": [ + 84, + 93 + ] + }, + { + "text": "Bits 31--8 of the `fcsr` are reserved for other standard extensions.", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Floating-Point Control and Status Register", + "line_range": [ + 95, + 99 + ] + }, + { + "text": "If these extensions are not present, implementations shall ignore writes to these bits and supply a zero value when read.", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Floating-Point Control and Status Register", + "line_range": [ + 95, + 99 + ] + }, + { + "text": "Standard software should preserve the contents of these bits.", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Floating-Point Control and Status Register", + "line_range": [ + 95, + 99 + ] + }, + { + "text": "Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in `frm`.", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Floating-Point Control and Status Register", + "line_range": [ + 101, + 108 + ] + }, + { + "text": "Rounding modes are encoded as shown in . A value of 111 in the instruction's rm field selects the dynamic rounding mode held in `frm`.", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Floating-Point Control and Status Register", + "line_range": [ + 101, + 108 + ] + }, + { + "text": "The behavior of floating-point instructions that depend on rounding mode when executed with a reserved rounding mode is reserved, including both static reserved rounding modes (101-110) and dynamic reserved rounding modes (101-111).", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Floating-Point Control and Status Register", + "line_range": [ + 101, + 108 + ] + }, + { + "text": "Some instructions, including widening conversions, have the rm field but are nevertheless mathematically unaffected by the rounding mode; software should set their rm field to RNE (000) but implementations must treat the rm field as usual (in particular, with regard to decoding legal vs. reserved encodings).", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Floating-Point Control and Status Register", + "line_range": [ + 101, + 108 + ] + }, + { + "text": ".Rounding mode encoding. | |Rounding Mode |Mnemonic |Meaning |000 |RNE |Round to Nearest, ties to Even |001 |RTZ |Round towards Zero |010 |RDN |Round Down (towards −{inf}) |011 |RUP |Round Up (towards +{inf}) |100 |RMM |Round to Nearest, ties to Max Magnitude |101 | |Reserved for future use. |110 | |Reserved for future use. |111 |DYN |In instruction's rm field, selects dynamic rounding mode;", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Floating-Point Control and Status Register", + "line_range": [ + 110, + 123 + ] + }, + { + "text": "In Rounding Mode register, reserved. |", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Floating-Point Control and Status Register", + "line_range": [ + 110, + 123 + ] + }, + { + "text": "The accrued exception flags indicate the exception conditions that have arisen on any floating-point arithmetic instruction since the field was last reset by software, as shown in .", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Floating-Point Control and Status Register", + "line_range": [ + 125, + 130 + ] + }, + { + "text": "The base RISC-V ISA does not support generating a trap on the setting of a floating-point exception flag.", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Floating-Point Control and Status Register", + "line_range": [ + 125, + 130 + ] + }, + { + "text": ".Accrued exception flag encoding. | |Flag Mnemonic |Flag Meaning |NV |Invalid Operation |DZ |Divide by Zero |OF |Overflow |UF |Underflow |NX |Inexact |", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Floating-Point Control and Status Register", + "line_range": [ + 132, + 142 + ] + }, + { + "text": "Except when otherwise stated, if the result of a floating-point operation is NaN, it is the canonical NaN.", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > NaN Generation and Propagation", + "line_range": [ + 147, + 153 + ] + }, + { + "text": "The canonical NaN has a positive sign and all significand bits clear except the MSB, a.k.a. the quiet bit.", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > NaN Generation and Propagation", + "line_range": [ + 147, + 153 + ] + }, + { + "text": "For single-precision floating-point, this corresponds to the pattern `0x7fc00000`.", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > NaN Generation and Propagation", + "line_range": [ + 147, + 153 + ] + }, + { + "text": "Operations on subnormal numbers are handled in accordance with IEEE 754-2008.", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Subnormal Arithmetic", + "line_range": [ + 159, + 162 + ] + }, + { + "text": "In the parlance of IEEE 754-2008, tininess is detected after rounding.", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Subnormal Arithmetic", + "line_range": [ + 164, + 166 + ] + }, + { + "text": "Floating-point loads and stores use the same base+offset addressing mode as the integer base ISAs, with a base address in register rs1 and a 12-bit signed byte offset.", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Load and Store Instructions", + "line_range": [ + 170, + 171 + ] + }, + { + "text": "The FLW instruction loads a single-precision floating-point value from memory into floating-point register rd. FSW stores a single-precision value from floating-point register rs2 to memory.", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Load and Store Instructions", + "line_range": [ + 170, + 171 + ] + }, + { + "text": "FLW and FSW are only guaranteed to execute atomically if the effective address is naturally aligned.", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Load and Store Instructions", + "line_range": [ + 177, + 179 + ] + }, + { + "text": "FLW and FSW do not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved.", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Load and Store Instructions", + "line_range": [ + 181, + 182 + ] + }, + { + "text": "As described in , the execution environment defines whether misaligned floating-point loads and stores are handled invisibly or raise a contained or fatal trap.", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Load and Store Instructions", + "line_range": [ + 184, + 185 + ] + }, + { + "text": "Floating-point arithmetic instructions with one or two source operands use the R-type format with the OP-FP major opcode. FADD.S and FMUL.S perform single-precision floating-point addition and multiplication respectively, between rs1 and rs2. FSUB.S performs the single-precision floating-point subtraction of rs2 from rs1. FDIV.S performs the single-precision floating-point division of rs1 by rs2. FSQRT.S computes the square root of rs1.", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Computational Instructions", + "line_range": [ + 190, + 194 + ] + }, + { + "text": "In each case, the result is written to rd.", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Computational Instructions", + "line_range": [ + 190, + 194 + ] + }, + { + "text": "The 2-bit floating-point format field fmt is encoded as shown in .", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Computational Instructions", + "line_range": [ + 196, + 198 + ] + }, + { + "text": "It is set to S (00) for all instructions in the F extension.", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Computational Instructions", + "line_range": [ + 196, + 198 + ] + }, + { + "text": ".Format field encoding | |fmt field |Mnemonic |Meaning |00 |S |32-bit single-precision |01 |D |64-bit double-precision |10 |H |16-bit half-precision |11 |Q |128-bit quad-precision |", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Computational Instructions", + "line_range": [ + 200, + 209 + ] + }, + { + "text": "All floating-point operations that perform rounding can select the rounding mode using the rm field with the encoding shown in .", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Computational Instructions", + "line_range": [ + 211, + 214 + ] + }, + { + "text": "Floating-point minimum-number and maximum-number instructions FMIN.S and FMAX.S write, respectively, the smaller or larger of rs1 and rs2 to rd.", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Computational Instructions", + "line_range": [ + 216, + 220 + ] + }, + { + "text": "For the purposes of these instructions only, the value −0.0 is considered to be less than the value +0.0.", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Computational Instructions", + "line_range": [ + 216, + 220 + ] + }, + { + "text": "If both inputs are NaNs, the result is the canonical NaN.", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Computational Instructions", + "line_range": [ + 216, + 220 + ] + }, + { + "text": "If only one operand is a NaN, the result is the non-NaN operand.", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Computational Instructions", + "line_range": [ + 216, + 220 + ] + }, + { + "text": "Signaling NaN inputs set the invalid operation exception flag, even when the result is not NaN.", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Computational Instructions", + "line_range": [ + 216, + 220 + ] + }, + { + "text": "Floating-point fused multiply-add instructions require a new standard instruction format. R4-type instructions specify three source registers (rs1, rs2, and rs3) and a destination register (rd).", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Computational Instructions", + "line_range": [ + 227, + 229 + ] + }, + { + "text": "This format is only used by the floating-point fused multiply-add instructions.", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Computational Instructions", + "line_range": [ + 227, + 229 + ] + }, + { + "text": "FMADD.S multiplies the values in rs1 and rs2, adds the value in rs3, and writes the final result to rd. FMADD.S computes (rs1×rs2)+rs3.", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Computational Instructions", + "line_range": [ + 231, + 234 + ] + }, + { + "text": "FMSUB.S multiplies the values in rs1 and rs2, subtracts the value in rs3, and writes the final result to rd. FMSUB.S computes (rs1×rs2)−rs3.", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Computational Instructions", + "line_range": [ + 236, + 238 + ] + }, + { + "text": "FNMSUB.S multiplies the values in rs1 and rs2, negates the product, adds the value in rs3, and writes the final result to rd. FNMSUB.S computes −(rs1×rs2)+rs3.", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Computational Instructions", + "line_range": [ + 240, + 241 + ] + }, + { + "text": "FNMADD.S multiplies the values in rs1 and rs2, negates the product, subtracts the value in rs3, and writes the final result to rd. FNMADD.S computes −(rs1×rs2)−rs3.", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Computational Instructions", + "line_range": [ + 243, + 244 + ] + }, + { + "text": "The fused multiply-add instructions must set the invalid operation exception flag when the multiplicands are {inf} and zero, even when the addend is a quiet NaN.", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Computational Instructions", + "line_range": [ + 250, + 252 + ] + }, + { + "text": "Floating-point-to-integer and integer-to-floating-point conversion instructions are encoded in the OP-FP major opcode space. FCVT.W.S or FCVT.L.S converts a floating-point number in floating-point register rs1 to a signed 32-bit or 64-bit integer, respectively, in integer register rd. FCVT.S.W or FCVT.S.L converts a 32-bit or 64-bit signed integer, respectively, in integer register rs1 into a floating-point number in floating-point register rd. FCVT.WU.S, FCVT.LU.S, FCVT.S.WU, and FCVT.S.LU variants convert to or from unsigned integer values.", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Conversion and Move Instructions", + "line_range": [ + 256, + 270 + ] + }, + { + "text": "For XLEN>32, FCVT.W[U].S sign-extends the 32-bit result to the destination register width. FCVT.L[U].S and FCVT.S.L[U] are RV64-only instructions.", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Conversion and Move Instructions", + "line_range": [ + 256, + 270 + ] + }, + { + "text": "If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set. gives the range of valid inputs for FCVT.int.S and the behavior for invalid inputs.", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Conversion and Move Instructions", + "line_range": [ + 256, + 270 + ] + }, + { + "text": "All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, `x0`, which will never set any exception flags.", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Conversion and Move Instructions", + "line_range": [ + 272, + 276 + ] + }, + { + "text": ".Domains of float-to-integer conversions and behavior for invalid inputs | | |FCVT.W.S |FCVT.WU.S |FCVT.L.S |FCVT.LU.S |Minimum valid input (after rounding) |−2^31^ |0 |−2^63^ |0", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Conversion and Move Instructions", + "line_range": [ + 278, + 284 + ] + }, + { + "text": "|Maximum valid input (after rounding) |2^31^−1 |2^32^−1 |2^63^−1 |2^64^−1", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Conversion and Move Instructions", + "line_range": [ + 286, + 287 + ] + }, + { + "text": "|Output for out-of-range negative input |−2^31^ |0 |−2^63^ |0", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Conversion and Move Instructions", + "line_range": [ + 289, + 290 + ] + }, + { + "text": "|Output for -{inf} |−2^31^ |0 |−2^63^ |0", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Conversion and Move Instructions", + "line_range": [ + 292, + 293 + ] + }, + { + "text": "|Output for out-of-range positive input |2^31^−1 |2^32^−1 |2^63^−1 |2^64^−1", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Conversion and Move Instructions", + "line_range": [ + 295, + 296 + ] + }, + { + "text": "|Output for +{inf} or NaN |2^31^−1 |2^32^−1 |2^63^−1 |2^64^−1 |", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Conversion and Move Instructions", + "line_range": [ + 298, + 300 + ] + }, + { + "text": "All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set.", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Conversion and Move Instructions", + "line_range": [ + 302, + 305 + ] + }, + { + "text": "Floating-point to floating-point sign-injection instructions, FSGNJ.S, FSGNJN.S, and FSGNJX.S, produce a result that takes all bits except the sign bit from rs1.", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Conversion and Move Instructions", + "line_range": [ + 311, + 321 + ] + }, + { + "text": "For FSGNJ, the result's sign bit is rs2's sign bit; for FSGNJN, the result's sign bit is the opposite of rs2's sign bit; and for FSGNJX, the sign bit is the XOR of the sign bits of rs1 and rs2.", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Conversion and Move Instructions", + "line_range": [ + 311, + 321 + ] + }, + { + "text": "Sign-injection instructions do not set floating-point exception flags, nor do they canonicalize NaNs.", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Conversion and Move Instructions", + "line_range": [ + 311, + 321 + ] + }, + { + "text": "Note, FSGNJ.S rx, ry, ry moves ry to rx (assembler pseudoinstruction FMV.S rx, ry); FSGNJN.S rx, ry, ry moves the negation of ry to rx (assembler pseudoinstruction FNEG.S rx, ry); and FSGNJX.S rx, ry, ry moves the absolute value of ry to rx (assembler pseudoinstruction FABS.S rx, ry).", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Conversion and Move Instructions", + "line_range": [ + 311, + 321 + ] + }, + { + "text": "Instructions are provided to move bit patterns between the floating-point and integer registers. FMV.X.W moves the single-precision value in floating-point register rs1 represented in the IEEE 754-2008 encoding to the lower 32 bits of integer register rd.", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Conversion and Move Instructions", + "line_range": [ + 326, + 333 + ] + }, + { + "text": "The bits are not modified in the transfer, and in particular, the payloads of non-canonical NaNs are preserved.", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Conversion and Move Instructions", + "line_range": [ + 326, + 333 + ] + }, + { + "text": "For RV64, the higher 32 bits of the destination register are filled with copies of the floating-point number's sign bit.", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Conversion and Move Instructions", + "line_range": [ + 326, + 333 + ] + }, + { + "text": "FMV.W.X moves the single-precision value encoded in the IEEE 754-2008 encoding from the lower 32 bits of integer register rs1 to the floating-point register rd.", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Conversion and Move Instructions", + "line_range": [ + 335, + 339 + ] + }, + { + "text": "The bits are not modified in the transfer, and in particular, the payloads of non-canonical NaNs are preserved.", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Conversion and Move Instructions", + "line_range": [ + 335, + 339 + ] + }, + { + "text": "Floating-point compare instructions (FEQ.S, FLT.S, FLE.S) perform the specified comparison between floating-point registers (rs1 = rs2, rs1 < rs2, rs1 {le} rs2) writing 1 to the integer register rd if the condition holds, and 0 otherwise.", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Compare Instructions", + "line_range": [ + 347, + 352 + ] + }, + { + "text": "FLT.S and FLE.S perform what IEEE 754-2008 refers to as signaling comparisons: that is, they set the invalid operation exception flag if either input is NaN. FEQ.S performs a quiet comparison: it only sets the invalid operation exception flag if either input is a signaling NaN.", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Compare Instructions", + "line_range": [ + 354, + 360 + ] + }, + { + "text": "For all three instructions, the result is 0 if either operand is NaN.", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Compare Instructions", + "line_range": [ + 354, + 360 + ] + }, + { + "text": "The FCLASS.S instruction examines the value in floating-point register rs1 and writes to integer register rd a 10-bit mask that indicates the class of the floating-point number.", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Classify Instruction", + "line_range": [ + 367, + 375 + ] + }, + { + "text": "The format of the mask is described in .", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Classify Instruction", + "line_range": [ + 367, + 375 + ] + }, + { + "text": "The corresponding bit in rd will be set if the property is true and clear otherwise.", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Classify Instruction", + "line_range": [ + 367, + 375 + ] + }, + { + "text": "All other bits in rd are cleared.", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Classify Instruction", + "line_range": [ + 367, + 375 + ] + }, + { + "text": "Note that exactly one bit in rd will be set. FCLASS.S does not set the floating-point exception flags.", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Classify Instruction", + "line_range": [ + 367, + 375 + ] + }, + { + "text": ".Format of result of FCLASS instruction. | |rd bit |Meaning |0 |rs1 is −{inf}. |1 |rs1 is a negative normal number. |2 |rs1 is a negative subnormal number. |3 |rs1 is −0. |4 |rs1 is +0. |5 |rs1 is a positive subnormal number. |6 |rs1 is a positive normal number. |7 |rs1 is +{inf}. |8 |rs1 is a signaling NaN. |9 |rs1 is a quiet NaN. |", + "section": "Preamble > \"F\" Extension for Single-Precision Floating-Point, Version 2.2 > F Register State > Single-Precision Floating-Point Classify Instruction", + "line_range": [ + 381, + 396 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__unpriv__m-st-ext.json b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__m-st-ext.json new file mode 100644 index 0000000000..eba8cbd268 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__m-st-ext.json @@ -0,0 +1,150 @@ +{ + "source_file": "src/unpriv/m-st-ext.adoc", + "total": 18, + "sentences": [ + { + "text": "This chapter describes the standard integer multiplication and division instruction extension, which is named `M` and contains instructions that multiply or divide values held in two integer registers.", + "section": "Preamble > \"M\" Extension for Integer Multiplication and Division, Version 2.0", + "line_range": [ + 3, + 5 + ] + }, + { + "text": "MUL performs an XLEN-bit×XLEN-bit multiplication of `rs1` by `rs2` and places the lower XLEN bits in the destination register. MULH, MULHU, and MULHSU perform the same multiplication but return the upper XLEN bits of the full 2×XLEN-bit product, for signed×signed, unsigned×unsigned, and `rs1`×unsigned `rs2` multiplication.", + "section": "Preamble > \"M\" Extension for Integer Multiplication and Division, Version 2.0 > Multiplication Operations", + "line_range": [ + 17, + 23 + ] + }, + { + "text": "If both the high and low bits of the same product are required, then the recommended code sequence is: `MULH[[S]U] rdh, rs1, rs2; MUL rdl, rs1, rs2` (source register specifiers must be in same order and `rdh` cannot be the same as `rs1` or `rs2`).", + "section": "Preamble > \"M\" Extension for Integer Multiplication and Division, Version 2.0 > Multiplication Operations", + "line_range": [ + 17, + 23 + ] + }, + { + "text": "Microarchitectures can then fuse these into a single multiply operation instead of performing two separate multiplies.", + "section": "Preamble > \"M\" Extension for Integer Multiplication and Division, Version 2.0 > Multiplication Operations", + "line_range": [ + 17, + 23 + ] + }, + { + "text": "MULW is an RV64 instruction that multiplies the lower 32 bits of the source registers, placing the sign extension of the lower 32 bits of the result into the destination register.", + "section": "Preamble > \"M\" Extension for Integer Multiplication and Division, Version 2.0 > Multiplication Operations", + "line_range": [ + 25, + 27 + ] + }, + { + "text": "DIV and DIVU perform an XLEN bits by XLEN bits signed and unsigned integer division of `rs1` by `rs2`, rounding towards zero. REM and REMU provide the remainder of the corresponding division operation.", + "section": "Preamble > \"M\" Extension for Integer Multiplication and Division, Version 2.0 > Multiplication Operations > Division Operations", + "line_range": [ + 37, + 40 + ] + }, + { + "text": "For REM, the sign of a nonzero result equals the sign of the dividend.", + "section": "Preamble > \"M\" Extension for Integer Multiplication and Division, Version 2.0 > Multiplication Operations > Division Operations", + "line_range": [ + 37, + 40 + ] + }, + { + "text": "If both the quotient and remainder are required from the same division, the recommended code sequence is: `DIV[U] rdq, rs1, rs2; REM[U] rdr,` `rs1, rs2` (`rdq` cannot be the same as `rs1` or `rs2`).", + "section": "Preamble > \"M\" Extension for Integer Multiplication and Division, Version 2.0 > Multiplication Operations > Division Operations", + "line_range": [ + 42, + 46 + ] + }, + { + "text": "Microarchitectures can then fuse these into a single divide operation instead of performing two separate divides.", + "section": "Preamble > \"M\" Extension for Integer Multiplication and Division, Version 2.0 > Multiplication Operations > Division Operations", + "line_range": [ + 42, + 46 + ] + }, + { + "text": "DIVW and DIVUW are RV64 instructions that divide the lower 32 bits of `rs1` by the lower 32 bits of `rs2`, treating them as signed and unsigned integers, placing the 32-bit quotient in `rd`, sign-extended to 64 bits. REMW and REMUW are RV64 instructions that provide the corresponding signed and unsigned remainder operations.", + "section": "Preamble > \"M\" Extension for Integer Multiplication and Division, Version 2.0 > Multiplication Operations > Division Operations", + "line_range": [ + 48, + 55 + ] + }, + { + "text": "Both REMW and REMUW always sign-extend the 32-bit result to 64 bits, including on a divide by zero.", + "section": "Preamble > \"M\" Extension for Integer Multiplication and Division, Version 2.0 > Multiplication Operations > Division Operations", + "line_range": [ + 48, + 55 + ] + }, + { + "text": "The semantics for division by zero and division overflow are summarized in .", + "section": "Preamble > \"M\" Extension for Integer Multiplication and Division, Version 2.0 > Multiplication Operations > Division Operations", + "line_range": [ + 57, + 63 + ] + }, + { + "text": "The quotient of division by zero has all bits set, and the remainder of division by zero equals the dividend.", + "section": "Preamble > \"M\" Extension for Integer Multiplication and Division, Version 2.0 > Multiplication Operations > Division Operations", + "line_range": [ + 57, + 63 + ] + }, + { + "text": "Signed division overflow occurs only when the most-negative integer is divided by −1.", + "section": "Preamble > \"M\" Extension for Integer Multiplication and Division, Version 2.0 > Multiplication Operations > Division Operations", + "line_range": [ + 57, + 63 + ] + }, + { + "text": "The quotient of a signed division with overflow is equal to the dividend, and the remainder is zero.", + "section": "Preamble > \"M\" Extension for Integer Multiplication and Division, Version 2.0 > Multiplication Operations > Division Operations", + "line_range": [ + 57, + 63 + ] + }, + { + "text": "Unsigned division overflow cannot occur.", + "section": "Preamble > \"M\" Extension for Integer Multiplication and Division, Version 2.0 > Multiplication Operations > Division Operations", + "line_range": [ + 57, + 63 + ] + }, + { + "text": ".Semantics for division by zero and division overflow. L is the width of the operation in bits: XLEN for DIV[U] and REM[U], or 32 for DIV[U]W and REM[U]W. [cols=\"<2,^,^,^,^,^,^\",options=\"header\",] | |Condition |Dividend |Divisor |DIVU[W] |REMU[W] |DIV[W] |REM[W]", + "section": "Preamble > \"M\" Extension for Integer Multiplication and Division, Version 2.0 > Multiplication Operations > Division Operations", + "line_range": [ + 65, + 69 + ] + }, + { + "text": "|Division by zero + Overflow (signed only) |x + -2^L-1^ |0 + −1 |2^L^-1 + - |x + - |−1 + -2^L-1^ + |x + 0 |", + "section": "Preamble > \"M\" Extension for Integer Multiplication and Division, Version 2.0 > Multiplication Operations > Division Operations", + "line_range": [ + 71, + 80 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__unpriv__memory-models.json b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__memory-models.json new file mode 100644 index 0000000000..49412ab6b7 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__memory-models.json @@ -0,0 +1,38 @@ +{ + "source_file": "src/unpriv/memory-models.adoc", + "total": 4, + "sentences": [ + { + "text": "NOTE: This chapter is currently being restructured.", + "section": "Preamble > RISC-V Memory Models", + "line_range": [ + 3, + 4 + ] + }, + { + "text": "Its contents are normative, but the presentation might appear disjoint.", + "section": "Preamble > RISC-V Memory Models", + "line_range": [ + 3, + 4 + ] + }, + { + "text": "This chapter describes the two RISC-V memory consistency models: , the base weakly ordered model, and , a more strongly ordered model enabled via the Ztso standard extension.", + "section": "Preamble > RISC-V Memory Models", + "line_range": [ + 6, + 8 + ] + }, + { + "text": "Additional explanatory material for both models can be found in .", + "section": "Preamble > RISC-V Memory Models", + "line_range": [ + 10, + 11 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__unpriv__mm-appendix.json b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__mm-appendix.json new file mode 100644 index 0000000000..a4f6d182d7 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__mm-appendix.json @@ -0,0 +1,14 @@ +{ + "source_file": "src/unpriv/mm-appendix.adoc", + "total": 1, + "sentences": [ + { + "text": "This appendix contains non-normative documentation that helps explain the rationale behind and the workings of the RISC-V memory consistency models, including formal models of RVWMO.", + "section": "Preamble > Memory Model Supplemental Material", + "line_range": [ + 4, + 6 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__unpriv__mm-explanatory.json b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__mm-explanatory.json new file mode 100644 index 0000000000..9a618984f9 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__mm-explanatory.json @@ -0,0 +1,3582 @@ +{ + "source_file": "src/unpriv/mm-explanatory.adoc", + "total": 447, + "sentences": [ + { + "text": "This section provides more explanation for RVWMO , using more informal language and concrete examples.", + "section": "Preamble > RVWMO Explanatory Material", + "line_range": [ + 3, + 11 + ] + }, + { + "text": "These are intended to clarify the meaning and intent of the axioms and preserved program order rules.", + "section": "Preamble > RVWMO Explanatory Material", + "line_range": [ + 3, + 11 + ] + }, + { + "text": "This appendix should be treated as commentary; all normative material is provided in and in the rest of the main body of the ISA specification.", + "section": "Preamble > RVWMO Explanatory Material", + "line_range": [ + 3, + 11 + ] + }, + { + "text": "All currently known discrepancies are listed in .", + "section": "Preamble > RVWMO Explanatory Material", + "line_range": [ + 3, + 11 + ] + }, + { + "text": "Any other discrepancies are unintentional.", + "section": "Preamble > RVWMO Explanatory Material", + "line_range": [ + 3, + 11 + ] + }, + { + "text": "Memory consistency models fall along a loose spectrum from weak to strong.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO?", + "line_range": [ + 16, + 25 + ] + }, + { + "text": "Weak memory models allow more hardware implementation flexibility and deliver arguably better performance, performance per watt, power, scalability, and hardware verification overheads than strong models, at the expense of a more complex programming model.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO?", + "line_range": [ + 16, + 25 + ] + }, + { + "text": "Strong models provide simpler programming models, but at the cost of imposing more restrictions on the kinds of (non-speculative) hardware optimizations that can be performed in the pipeline and in the memory system, and in turn imposing some cost in terms of power, area overhead, and verification burden.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO?", + "line_range": [ + 16, + 25 + ] + }, + { + "text": "RISC-V has chosen the RVWMO memory model, a variant of release consistency.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO?", + "line_range": [ + 27, + 34 + ] + }, + { + "text": "This places it in between the two extremes of the memory model spectrum.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO?", + "line_range": [ + 27, + 34 + ] + }, + { + "text": "The RVWMO memory model enables architects to build simple implementations, aggressive implementations, implementations embedded deeply inside a much larger system and subject to complex memory system interactions, or any number of other possibilities, all while simultaneously being strong enough to support programming language memory models at high performance.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO?", + "line_range": [ + 27, + 34 + ] + }, + { + "text": "To facilitate the porting of code from other architectures, some hardware implementations may choose to implement the Ztso extension, which provides stricter RVTSO ordering semantics by default.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO?", + "line_range": [ + 36, + 45 + ] + }, + { + "text": "Code written for RVWMO is automatically and inherently compatible with RVTSO, but code written assuming RVTSO is not guaranteed to run correctly on RVWMO implementations.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO?", + "line_range": [ + 36, + 45 + ] + }, + { + "text": "In fact, most RVWMO implementations will (and should) simply refuse to run RVTSO-only binaries.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO?", + "line_range": [ + 36, + 45 + ] + }, + { + "text": "Each implementation must therefore choose whether to prioritize compatibility with RVTSO code (e.g., to facilitate porting from x86) or whether to instead prioritize compatibility with other RISC-V cores implementing RVWMO.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO?", + "line_range": [ + 36, + 45 + ] + }, + { + "text": "Some fences and/or memory ordering annotations in code written for RVWMO may become redundant under RVTSO; the cost that the default of RVWMO imposes on Ztso implementations is the incremental overhead of fetching those fences (e.g., FENCE R,RW and FENCE RW,W) which become no-ops on that implementation.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO?", + "line_range": [ + 47, + 52 + ] + }, + { + "text": "However, these fences must remain present in the code if compatibility with non-Ztso implementations is desired.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO?", + "line_range": [ + 47, + 52 + ] + }, + { + "text": "The explanations in this chapter make use of litmus tests, or small programs designed to test or highlight one particular aspect of a memory model. shows an example of a litmus test with two harts.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Litmus Tests", + "line_range": [ + 57, + 66 + ] + }, + { + "text": "As a convention for this figure and for all figures that follow in this chapter, we assume that `s0-s2` are pre-set to the same value in all harts and that `s0` holds the address labeled `x`, `s1` holds `y`, and `s2` holds `z`, where `x`, `y`, and `z` are disjoint memory locations aligned to 8 byte boundaries.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Litmus Tests", + "line_range": [ + 57, + 66 + ] + }, + { + "text": "All other registers and all referenced memory locations are presumed to be initialized to zero.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Litmus Tests", + "line_range": [ + 57, + 66 + ] + }, + { + "text": "Each figure shows the litmus test code on the left, and a visualization of one particular valid or invalid execution on the right.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Litmus Tests", + "line_range": [ + 57, + 66 + ] + }, + { + "text": "[float=\"center\",align=\"center\",cols=\"1a,.^1a\",frame=\"none\",grid=\"none\",options=\"noheader\"] .A sample litmus test and one forbidden execution (`a0=1`). | | [.left] ! 2+!Hart 0 2+!Hart 1 ! !{vertical-ellipsis} ! !{vertical-ellipsis} ! !li t1,1 ! !li t4,4 !(a) !sw t1,0(s0) !(e) !sw t4,0(s0) ! !{vertical-ellipsis} ! !{vertical-ellipsis} ! !li t2,2 ! ! !(b) !sw t2,0(s0) ! ! ! !{vertical-ellipsis} ! !{vertical-ellipsis} !(c) !lw a0,0(s0) ! ! ! !{vertical-ellipsis} ! !{vertical-ellipsis} ! !li t3,3 ! !li t5,5 !(d) !sw t3,0(s0) !(f) !sw t5,0(s0) ! !{vertical-ellipsis} ! !{vertical-ellipsis} ! | ! //a! graphviz::images/graphviz/litmussample.txt[] a! image::graphviz/litmussample.png[] ! |", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Litmus Tests", + "line_range": [ + 68, + 95 + ] + }, + { + "text": "Litmus tests are used to understand the implications of the memory model in specific concrete situations.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Litmus Tests", + "line_range": [ + 97, + 105 + ] + }, + { + "text": "For example, in the litmus test of , the final value of `a0` in the first hart can be either 2, 4, or 5, depending on the dynamic interleaving of the instruction stream from each hart at runtime.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Litmus Tests", + "line_range": [ + 97, + 105 + ] + }, + { + "text": "However, in this example, the final value of `a0` in Hart 0 will never be 1 or 3; intuitively, the value 1 will no longer be visible at the time the load executes, and the value 3 will not yet be visible by the time the load executes.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Litmus Tests", + "line_range": [ + 97, + 105 + ] + }, + { + "text": "We analyze this test and many others below.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Litmus Tests", + "line_range": [ + 97, + 105 + ] + }, + { + "text": "<<< .A key for the litmus test diagrams drawn in this appendix | |Edge |Full Name (and explanation) |rf |Reads From (from each store to the loads that return a value written by that store)", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Litmus Tests", + "line_range": [ + 107, + 114 + ] + }, + { + "text": "|co |Coherence (a total order on the stores to each address)", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Litmus Tests", + "line_range": [ + 116, + 116 + ] + }, + { + "text": "|fr |From-Reads (from each load to co-successors of the store from which the load returned a value)", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Litmus Tests", + "line_range": [ + 118, + 119 + ] + }, + { + "text": "|ppo |Preserved Program Order", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Litmus Tests", + "line_range": [ + 121, + 121 + ] + }, + { + "text": "|fence |Orderings enforced by a FENCE instruction", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Litmus Tests", + "line_range": [ + 123, + 123 + ] + }, + { + "text": "The diagram shown to the right of each litmus test shows a visual representation of the particular execution candidate being considered.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Litmus Tests", + "line_range": [ + 132, + 143 + ] + }, + { + "text": "These diagrams use a notation that is common in the memory model literature for constraining the set of possible global memory orders that could produce the execution in question.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Litmus Tests", + "line_range": [ + 132, + 143 + ] + }, + { + "text": "It is also the basis for the herd models presented in .", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Litmus Tests", + "line_range": [ + 132, + 143 + ] + }, + { + "text": "This notation is explained in .", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Litmus Tests", + "line_range": [ + 132, + 143 + ] + }, + { + "text": "Of the listed relations, rf edges between harts, co edges, fr edges, and ppo edges directly constrain the global memory order (as do fence, addr, data, and some ctrl edges, via ppo).", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Litmus Tests", + "line_range": [ + 132, + 143 + ] + }, + { + "text": "Other edges (such as intra-hart rf edges) are informative but do not constrain the global memory order.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Litmus Tests", + "line_range": [ + 132, + 143 + ] + }, + { + "text": "For example, in , `a0=1` could occur only if one of the following were true:", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Litmus Tests", + "line_range": [ + 145, + 146 + ] + }, + { + "text": "(b) appears before (a) in global memory order (and in the coherence order co).", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Litmus Tests", + "line_range": [ + 148, + 156 + ] + }, + { + "text": "However, this violates RVWMO PPO rule `ppo:->st`.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Litmus Tests", + "line_range": [ + 148, + 156 + ] + }, + { + "text": "The co edge from (b) to (a) highlights this contradiction. * (a) appears before (b) in global memory order (and in the coherence order co).", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Litmus Tests", + "line_range": [ + 148, + 156 + ] + }, + { + "text": "However, in this case, the Load Value Axiom would be violated, because (a) is not the latest matching store prior to (c) in program order.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Litmus Tests", + "line_range": [ + 148, + 156 + ] + }, + { + "text": "The fr edge from (c) to (b) highlights this contradiction.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Litmus Tests", + "line_range": [ + 148, + 156 + ] + }, + { + "text": "Since neither of these scenarios satisfies the RVWMO axioms, the outcome `a0=1` is forbidden.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Litmus Tests", + "line_range": [ + 158, + 159 + ] + }, + { + "text": "Beyond what is described in this appendix, a suite of more than seven thousand litmus tests is available at https://github.com/litmus-tests/litmus-tests-riscv.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Litmus Tests", + "line_range": [ + 161, + 163 + ] + }, + { + "text": "In this section, we provide explanation and examples for all of the RVWMO rules and axioms.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules", + "line_range": [ + 166, + 167 + ] + }, + { + "text": "Preserved program order represents the subset of program order that must be respected within the global memory order.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Preserved Program Order and Global Memory Order", + "line_range": [ + 171, + 177 + ] + }, + { + "text": "Conceptually, events from the same hart that are ordered by preserved program order must appear in that order from the perspective of other harts and/or observers.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Preserved Program Order and Global Memory Order", + "line_range": [ + 171, + 177 + ] + }, + { + "text": "Events from the same hart that are not ordered by preserved program order, on the other hand, may appear reordered from the perspective of other harts and/or observers.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Preserved Program Order and Global Memory Order", + "line_range": [ + 171, + 177 + ] + }, + { + "text": "Informally, the global memory order represents the order in which loads and stores perform.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Preserved Program Order and Global Memory Order", + "line_range": [ + 179, + 189 + ] + }, + { + "text": "The formal memory model literature has moved away from specifications built around the concept of performing, but the idea is still useful for building up informal intuition. A load is said to have performed when its return value is determined. A store is said to have performed not when it has executed inside the pipeline, but rather only when its value has been propagated to globally visible memory.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Preserved Program Order and Global Memory Order", + "line_range": [ + 179, + 189 + ] + }, + { + "text": "In this sense, the global memory order also represents the contribution of the coherence protocol and/or the rest of the memory system to interleave the (possibly reordered) memory accesses being issued by each hart into a single total order agreed upon by all harts.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Preserved Program Order and Global Memory Order", + "line_range": [ + 179, + 189 + ] + }, + { + "text": "The order in which loads perform does not always directly correspond to the relative age of the values those two loads return.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Preserved Program Order and Global Memory Order", + "line_range": [ + 191, + 205 + ] + }, + { + "text": "In particular, a load b may perform before another load a to the same address (i.e., b may execute before a, and b may appear before a in the global memory order), but a may nevertheless return an older value than b.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Preserved Program Order and Global Memory Order", + "line_range": [ + 191, + 205 + ] + }, + { + "text": "This discrepancy captures (among other things) the reordering effects of buffering placed between the core and memory.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Preserved Program Order and Global Memory Order", + "line_range": [ + 191, + 205 + ] + }, + { + "text": "For example, b may have returned a value from a store in the store buffer, while a may have ignored that younger store and read an older value from memory instead.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Preserved Program Order and Global Memory Order", + "line_range": [ + 191, + 205 + ] + }, + { + "text": "To account for this, at the time each load performs, the value it returns is determined by the load value axiom, not just strictly by determining the most recent store to the same address in the global memory order, as described below.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Preserved Program Order and Global Memory Order", + "line_range": [ + 191, + 205 + ] + }, + { + "text": "[IMPORTANT] : Each byte of each load i returns the value written to that byte by the store that is the latest in global memory order among the following stores:", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Load value axiom", + "line_range": [ + 210, + 214 + ] + }, + { + "text": "Stores that write that byte and that precede i in the global memory order .", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Load value axiom", + "line_range": [ + 216, + 219 + ] + }, + { + "text": "Stores that write that byte and that precede i in program order", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Load value axiom", + "line_range": [ + 216, + 219 + ] + }, + { + "text": "Preserved program order is not required to respect the ordering of a store followed by a load to an overlapping address.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Load value axiom", + "line_range": [ + 221, + 228 + ] + }, + { + "text": "This complexity arises due to the ubiquity of store buffers in nearly all implementations.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Load value axiom", + "line_range": [ + 221, + 228 + ] + }, + { + "text": "Informally, the load may perform (return a value) by forwarding from the store while the store is still in the store buffer, and hence before the store itself performs (writes back to globally visible memory).", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Load value axiom", + "line_range": [ + 221, + 228 + ] + }, + { + "text": "Any other hart will therefore observe the load as performing before the store.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Load value axiom", + "line_range": [ + 221, + 228 + ] + }, + { + "text": "When running this program on an implementation with store buffers, it is possible to arrive at the final outcome `a0=1, a1=0, a2=1, a3=0` as follows:", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Load value axiom", + "line_range": [ + 230, + 231 + ] + }, + { + "text": ".A store buffer forwarding litmus test (outcome permitted) [float=\"center\",align=\"center\",cols=\".^1a,.^1a\",frame=\"none\",grid=\"none\",options=\"noheader\"] | | ! 2+^!Hart 0 2+^!Hart 1 2+^!li t1, 1 2+^!li t1, 1 2+ RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Load value axiom", + "line_range": [ + 233, + 253 + ] + }, + { + "text": "(a) executes and enters the first hart's private store buffer * (b) executes and forwards its return value 1 from (a) in the store buffer * (c) executes since all previous loads (i.e., (b)) have completed * (d) executes and reads the value 0 from memory * (e) executes and enters the second hart's private store buffer * (f) executes and forwards its return value 1 from (e) in the store buffer * (g) executes since all previous loads (i.e., (f)) have completed * (h) executes and reads the value 0 from memory * (a) drains from the first hart's store buffer to memory * (e) drains from the second hart's store buffer to memory", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Load value axiom", + "line_range": [ + 255, + 268 + ] + }, + { + "text": "Therefore, the memory model must be able to account for this behavior.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Load value axiom", + "line_range": [ + 270, + 270 + ] + }, + { + "text": "To put it another way, suppose the definition of preserved program order did include the following hypothetical rule: memory access a precedes memory access b in preserved program order (and hence also in the global memory order) if a precedes b in program order and a and b are accesses to the same memory location, a is a write, and b is a read.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Load value axiom", + "line_range": [ + 272, + 279 + ] + }, + { + "text": "Then we get the following:", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Load value axiom", + "line_range": [ + 272, + 279 + ] + }, + { + "text": "(a) precedes (b): by rule X * (b) precedes (d): by rule * (d) precedes (e): by the load value axiom.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Load value axiom", + "line_range": [ + 281, + 288 + ] + }, + { + "text": "Otherwise, if (e) preceded (d), then (d) would be required to return the value 1. (This is a perfectly legal execution; it's just not the one in question) * (e) precedes (f): by rule X * (f) precedes (h): by rule * (h) precedes (a): by the load value axiom, as above.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Load value axiom", + "line_range": [ + 281, + 288 + ] + }, + { + "text": "The global memory order must be a total order and cannot be cyclic, because a cycle would imply that every event in the cycle happens before itself, which is impossible.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Load value axiom", + "line_range": [ + 290, + 295 + ] + }, + { + "text": "Therefore, the execution proposed above would be forbidden, and hence the addition of rule X would forbid implementations with store buffer forwarding, which would clearly be undesirable.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Load value axiom", + "line_range": [ + 290, + 295 + ] + }, + { + "text": "Nevertheless, even if (b) precedes (a) and/or (f) precedes (e) in the global memory order, the only sensible possibility in this example is for (b) to return the value written by (a), and likewise for (f) and (e).", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Load value axiom", + "line_range": [ + 297, + 306 + ] + }, + { + "text": "This combination of circumstances is what leads to the second option in the definition of the load value axiom.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Load value axiom", + "line_range": [ + 297, + 306 + ] + }, + { + "text": "Even though (b) precedes (a) in the global memory order, (a) will still be visible to (b) by virtue of sitting in the store buffer at the time (b) executes.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Load value axiom", + "line_range": [ + 297, + 306 + ] + }, + { + "text": "Therefore, even if (b) precedes (a) in the global memory order, (b) should return the value written by (a) because (a) precedes (b) in program order.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Load value axiom", + "line_range": [ + 297, + 306 + ] + }, + { + "text": ".Key for test that highlights the behavior of store buffers [float=\"center\",align=\"center\",cols=\".^1a,.^1a\",frame=\"none\",grid=\"none\",options=\"noheader\"] .The \"PPOCA\" store buffer forwarding litmus test (outcome permitted) | | ! 2+^!Hart 0 2+^!Hart 1 ! !li t1, 1 !!li t1, 1 !(a) !sw t1,0(s0) !!LOOP: !(b) !fence w,w !(d) !lw a0,0(s1) !(c) !sw t1,0(s1) !!beqz a0, LOOP 2+! !(e) !sw t1,0(s2) 2+! !(f) !lw a1,0(s2) 2+! ! !xor a2,a1,a1 2+! ! !add s0,s0,a2 2+! !(g) !lw a2,0(s0) 4+!Outcome: `a0=1`, `a1=1`, `a2=0` ! | ! //a! graphviz::images/graphviz/litmusppoca.txt[] a! image::graphviz/litmusppoca.png[] ! |", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Load value axiom", + "line_range": [ + 308, + 333 + ] + }, + { + "text": "Another test that highlights the behavior of store buffers is shown in .", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Load value axiom", + "line_range": [ + 335, + 341 + ] + }, + { + "text": "In this example, (d) is ordered before (e) because of the control dependency, and (f) is ordered before (g) because of the address dependency.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Load value axiom", + "line_range": [ + 335, + 341 + ] + }, + { + "text": "However, (e) is not necessarily ordered before (f), even though (f) returns the value written by (e).", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Load value axiom", + "line_range": [ + 335, + 341 + ] + }, + { + "text": "This could correspond to the following sequence of events:", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Load value axiom", + "line_range": [ + 335, + 341 + ] + }, + { + "text": "(e) executes speculatively and enters the second hart's private store buffer (but does not drain to memory) * (f) executes speculatively and forwards its return value 1 from (e) in the store buffer * (g) executes speculatively and reads the value 0 from memory * (a) executes, enters the first hart's private store buffer, and drains to memory * (b) executes and retires * (c) executes, enters the first hart's private store buffer, and drains to memory * (d) executes and reads the value 1 from memory * (e), (f), and (g) commit, since the speculation turned out to be correct * (e) drains from the store buffer to memory", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Load value axiom", + "line_range": [ + 343, + 356 + ] + }, + { + "text": "[IMPORTANT] (for Aligned Atomics):", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Atomicity axiom", + "line_range": [ + 361, + 369 + ] + }, + { + "text": "If r and w are paired load and store operations generated by aligned LR and SC instructions in a hart h, s is a store to byte x, and r returns a value written by s, then s must precede w in the global memory order, and there can be no store from a hart other than h to byte x following s and preceding w in the global memory order.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Atomicity axiom", + "line_range": [ + 361, + 369 + ] + }, + { + "text": "The RISC-V architecture decouples the notion of atomicity from the notion of ordering.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Atomicity axiom", + "line_range": [ + 371, + 374 + ] + }, + { + "text": "Unlike architectures such as TSO, RISC-V atomics under RVWMO do not impose any ordering requirements by default.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Atomicity axiom", + "line_range": [ + 371, + 374 + ] + }, + { + "text": "Ordering semantics are only guaranteed by the PPO rules that otherwise apply.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Atomicity axiom", + "line_range": [ + 371, + 374 + ] + }, + { + "text": "RISC-V contains two types of atomics: AMOs and LR/SC pairs.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Atomicity axiom", + "line_range": [ + 376, + 384 + ] + }, + { + "text": "These conceptually behave differently, in the following way. LR/SC behave as if the old value is brought up to the core, modified, and written back to memory, all while a reservation is held on that memory location. AMOs on the other hand conceptually behave as if they are performed directly in memory. AMOs are therefore inherently atomic, while LR/SC pairs are atomic in the slightly different sense that the memory location in question will not be modified by another hart during the time the original hart holds the reservation.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Atomicity axiom", + "line_range": [ + 376, + 384 + ] + }, + { + "text": "[frame=none] .In all four (independent) instances, the final store-conditional instruction is permitted but not guaranteed to succeed. | |(a) lr.d a0, 0(s0) |(a) lr.d a0, 0(s0) |(a) lr.w a0, 0(s0) |(a) lr.w a0, 0(s0)", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Atomicity axiom", + "line_range": [ + 388, + 391 + ] + }, + { + "text": "|(b) sd t1, 0(s0) |(b) sw t1, 4(s0) |(b) sw t1, 4(s0) |(b) sw t1, 4(s0)", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Atomicity axiom", + "line_range": [ + 393, + 393 + ] + }, + { + "text": "|(c) sc.d t3, t2, 0(s0) |(c) sc.d t3, t2, 0(s0) |(c) sc.w t3, t2, 0(s0) |(c) addi s0, s0, 8", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Atomicity axiom", + "line_range": [ + 395, + 395 + ] + }, + { + "text": "||||(d) sc.w t3, t2, 0(s0) |", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Atomicity axiom", + "line_range": [ + 397, + 398 + ] + }, + { + "text": "The atomicity axiom forbids stores from other harts from being interleaved in global memory order between an LR and the SC paired with that LR.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Atomicity axiom", + "line_range": [ + 400, + 416 + ] + }, + { + "text": "The atomicity axiom does not forbid loads from being interleaved between the paired operations in program order or in the global memory order, nor does it forbid stores from the same hart or stores to non-overlapping locations from appearing between the paired operations in either program order or in the global memory order.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Atomicity axiom", + "line_range": [ + 400, + 416 + ] + }, + { + "text": "For example, the SC instructions in may (but are not guaranteed to) succeed.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Atomicity axiom", + "line_range": [ + 400, + 416 + ] + }, + { + "text": "None of those successes would violate the atomicity axiom, because the intervening non-conditional stores are from the same hart as the paired load-reserved and store-conditional instructions.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Atomicity axiom", + "line_range": [ + 400, + 416 + ] + }, + { + "text": "This way, a memory system that tracks memory accesses at cache line granularity (and which therefore will see the four snippets of as identical) will not be forced to fail a store-conditional instruction that happens to (falsely) share another portion of the same cache line as the memory location being held by the reservation.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Atomicity axiom", + "line_range": [ + 400, + 416 + ] + }, + { + "text": "The atomicity axiom also technically supports cases in which the LR and SC touch different addresses and/or use different access sizes; however, use cases for such behaviors are expected to be rare in practice.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Atomicity axiom", + "line_range": [ + 418, + 424 + ] + }, + { + "text": "Likewise, scenarios in which stores from the same hart between an LR/SC pair actually overlap the memory location(s) referenced by the LR or SC are expected to be rare compared to scenarios where the intervening store may simply fall onto the same cache line.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Atomicity axiom", + "line_range": [ + 418, + 424 + ] + }, + { + "text": "[IMPORTANT] : No memory operation may be preceded in the global memory order by an infinite sequence of other memory operations.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Progress axiom", + "line_range": [ + 429, + 433 + ] + }, + { + "text": "The progress axiom ensures a minimal forward progress guarantee.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Progress axiom", + "line_range": [ + 435, + 441 + ] + }, + { + "text": "It ensures that stores from one hart will eventually be made visible to other harts in the system in a finite amount of time, and that loads from other harts will eventually be able to read those values (or successors thereof).", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Progress axiom", + "line_range": [ + 435, + 441 + ] + }, + { + "text": "Without this rule, it would be legal, for example, for a spinlock to spin infinitely on a value, even with a store from another hart unlocking the spinlock.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Progress axiom", + "line_range": [ + 435, + 441 + ] + }, + { + "text": "The progress axiom is intended not to impose any other notion of fairness, latency, or quality of service onto the harts in a RISC-V implementation.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Progress axiom", + "line_range": [ + 443, + 446 + ] + }, + { + "text": "Any stronger notions of fairness are up to the rest of the ISA and/or up to the platform and/or device to define and implement.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Progress axiom", + "line_range": [ + 443, + 446 + ] + }, + { + "text": "The forward progress axiom will in almost all cases be naturally satisfied by any standard cache coherence protocol.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Progress axiom", + "line_range": [ + 448, + 452 + ] + }, + { + "text": "Implementations with non-coherent caches may have to provide some other mechanism to ensure the eventual visibility of all stores (or successors thereof) to all harts.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Progress axiom", + "line_range": [ + 448, + 452 + ] + }, + { + "text": "Same-address orderings where the latter is a store are straightforward: a load or store can never be reordered with a later store to an overlapping memory location.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)", + "line_range": [ + 457, + 467 + ] + }, + { + "text": "From a microarchitecture perspective, generally speaking, it is difficult or impossible to undo a speculatively reordered store if the speculation turns out to be invalid, so such behavior is simply disallowed by the model.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)", + "line_range": [ + 457, + 467 + ] + }, + { + "text": "Same-address orderings from a store to a later load, on the other hand, do not need to be enforced.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)", + "line_range": [ + 457, + 467 + ] + }, + { + "text": "As discussed in , this reflects the observable behavior of implementations that forward values from buffered stores to later loads.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)", + "line_range": [ + 457, + 467 + ] + }, + { + "text": "Same-address load-load ordering requirements are far more subtle.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)", + "line_range": [ + 469, + 481 + ] + }, + { + "text": "The basic requirement is that a younger load must not return a value that is older than a value returned by an older load in the same hart to the same address.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)", + "line_range": [ + 469, + 481 + ] + }, + { + "text": "This is often known as \"CoRR\" (Coherence for Read-Read pairs), or as part of a broader \"coherence\" or \"sequential consistency per location\" requirement.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)", + "line_range": [ + 469, + 481 + ] + }, + { + "text": "Some architectures in the past have relaxed same-address load-load ordering, but in hindsight this is generally considered to complicate the programming model too much, and so RVWMO requires CoRR ordering to be enforced.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)", + "line_range": [ + 469, + 481 + ] + }, + { + "text": "However, because the global memory order corresponds to the order in which loads perform rather than the ordering of the values being returned, capturing CoRR requirements in terms of the global memory order requires a bit of indirection.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)", + "line_range": [ + 469, + 481 + ] + }, + { + "text": ".A litmus test MP+fence.w.w+fri-rfi-addr (outcome permitted)", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)", + "line_range": [ + 483, + 484 + ] + }, + { + "text": "[float=\"center\",align=\"center\",cols=\".^1a,.^1a\",frame=\"none\",grid=\"none\",options=\"noheader\"] .Litmus test MP+fence.w.w+fre-rfi-addr (outcome permitted) | | ! 2+!Hart 0 2+^!Hart 1 !!li t1, 1 !!li t2, 2 >!(a) !sw t1,0(s0) >!(d) !lw a0,0(s1) >!(b) !fence w, w >!(e) !sw t2,0(s1) >!(c) !sw t1,0(s1) >!(f) !lw a1,0(s1) ! ! >!(g) !xor t3,a1,a1 ! ! >!(h) !add s0,s0,t3 ! ! >!(i) !lw a2,0(s0) 4+^!Outcome: `a0=1`, `a1=2`, `a2=0` ! | ! //a! graphviz::images/graphviz/litmusmpfencewwfrirfiaddr.txt[] a! image::graphviz/litmusmpfencewwfrirfiaddr.png[] ! | Consider the litmus test of , which is one particular instance of the more general \"fri-rfi\" pattern.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)", + "line_range": [ + 486, + 512 + ] + }, + { + "text": "The term \"fri-rfi\" refers to the sequence (d), (e), (f): (d) \"from-reads\" (i.e., reads from an earlier write than) (e) which is the same hart, and (f) reads from (e) which is in the same hart.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)", + "line_range": [ + 486, + 512 + ] + }, + { + "text": "From a microarchitectural perspective, outcome `a0=1`, `a1=2`, `a2=0` is legal (as are various other less subtle outcomes).", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)", + "line_range": [ + 514, + 516 + ] + }, + { + "text": "Intuitively, the following would produce the outcome in question:", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)", + "line_range": [ + 514, + 516 + ] + }, + { + "text": "(d) stalls (for whatever reason; perhaps it's stalled waiting for some other preceding instruction) * (e) executes and enters the store buffer (but does not yet drain to memory) * (f) executes and forwards from (e) in the store buffer * (g), (h), and (i) execute * (a) executes and drains to memory, (b) executes, and (c) executes and drains to memory * (d) unstalls and executes * (e) drains from the store buffer to memory", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)", + "line_range": [ + 518, + 527 + ] + }, + { + "text": "This corresponds to a global memory order of (f), (i), (a), (c), (d), (e).", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)", + "line_range": [ + 529, + 532 + ] + }, + { + "text": "Note that even though (f) performs before (d), the value returned by (f) is newer than the value returned by (d).", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)", + "line_range": [ + 529, + 532 + ] + }, + { + "text": "Therefore, this execution is legal and does not violate the CoRR requirements.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)", + "line_range": [ + 529, + 532 + ] + }, + { + "text": "Likewise, if two back-to-back loads return the values written by the same store, then they may also appear out-of-order in the global memory order without violating CoRR.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)", + "line_range": [ + 534, + 538 + ] + }, + { + "text": "Note that this is not the same as saying that the two loads return the same value, since two different stores may write the same value.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)", + "line_range": [ + 534, + 538 + ] + }, + { + "text": ".Litmus test RSW (outcome permitted)", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)", + "line_range": [ + 540, + 541 + ] + }, + { + "text": "[float=\"center\",align=\"center\",cols=\".^1a,.^1a\",frame=\"none\",grid=\"none\",options=\"noheader\"] | | ! 2+!Hart 0 2+^!Hart 1 2+!li t1, 1 >!(d) !(a) !(e) !xor t2,a0,a0 >!(b) !(f) !add s4,s2,t2 >!(c) !(g) !lw a1,0(s4) ! ! >!(h) !lw a2,0(s2) ! ! >!(i) !xor t3,a2,a2 ! ! >!(j) !add s0,s0,t3 ! ! >!(k) !lw a3,0(s0) 4+!Outcome: `a0=1`, `a1=v`, `a2=v`, `a3=0` ! | ! //a! graphviz::images/graphviz/litmusrsw.txt[] a! image::graphviz/litmusrsw.png[] ! |", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)", + "line_range": [ + 543, + 564 + ] + }, + { + "text": "Consider the litmus test of .", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)", + "line_range": [ + 566, + 576 + ] + }, + { + "text": "The outcome `a0=1`, `a1=v`, `a2=v`, `a3=0` (where v is some value written by another hart) can be observed by allowing (g) and (h) to be reordered.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)", + "line_range": [ + 566, + 576 + ] + }, + { + "text": "This might be done speculatively, and the speculation can be justified by the microarchitecture (e.g., by snooping for cache invalidations and finding none) because replaying (h) after (g) would return the value written by the same store anyway.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)", + "line_range": [ + 566, + 576 + ] + }, + { + "text": "Hence assuming `a1` and `a2` would end up with the same value written by the same store anyway, (g) and (h) can be legally reordered.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)", + "line_range": [ + 566, + 576 + ] + }, + { + "text": "The global memory order corresponding to this execution would be (h),(k),(a),(c),(d),(g).", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)", + "line_range": [ + 566, + 576 + ] + }, + { + "text": "Executions of the test in in which `a1` does not equal `a2` do in fact require that (g) appears before (h) in the global memory order.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)", + "line_range": [ + 578, + 587 + ] + }, + { + "text": "Allowing (h) to appear before (g) in the global memory order would in that case result in a violation of CoRR, because then (h) would return an older value than that returned by (g).", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)", + "line_range": [ + 578, + 587 + ] + }, + { + "text": "Therefore, forbids this CoRR violation from occurring.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)", + "line_range": [ + 578, + 587 + ] + }, + { + "text": "As such, strikes a careful balance between enforcing CoRR in all cases while simultaneously being weak enough to permit \"RSW\" and \"fri-rfi\" patterns that commonly appear in real microarchitectures.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)", + "line_range": [ + 578, + 587 + ] + }, + { + "text": "There is one more overlapping-address rule: simply states that a value cannot be returned from an AMO or SC to a subsequent load until the AMO or SC has (in the case of the SC, successfully) performed globally.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)", + "line_range": [ + 589, + 601 + ] + }, + { + "text": "This follows somewhat naturally from the conceptual view that both AMOs and SC instructions are meant to be performed atomically in memory.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)", + "line_range": [ + 589, + 601 + ] + }, + { + "text": "However, notably, states that hardware may not even non-speculatively forward the value being stored by an AMOSWAP to a subsequent load, even though for AMOSWAP that store value is not actually semantically dependent on the previous value in memory, as is the case for the other AMOs.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)", + "line_range": [ + 589, + 601 + ] + }, + { + "text": "The same holds true even when forwarding from SC store values that are not semantically dependent on the value returned by the paired LR.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)", + "line_range": [ + 589, + 601 + ] + }, + { + "text": "The three PPO rules above also apply when the memory accesses in question only overlap partially.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)", + "line_range": [ + 603, + 609 + ] + }, + { + "text": "This can occur, for example, when accesses of different sizes are used to access the same object.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)", + "line_range": [ + 603, + 609 + ] + }, + { + "text": "Note also that the base addresses of two overlapping memory operations need not necessarily be the same for two memory accesses to overlap.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)", + "line_range": [ + 603, + 609 + ] + }, + { + "text": "When misaligned memory accesses are being used, the overlapping-address PPO rules apply to each of the component memory accesses independently.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Overlapping-Address Orderings (<>)", + "line_range": [ + 603, + 609 + ] + }, + { + "text": "[IMPORTANT] Rule : There is a FENCE instruction that orders a before b", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Fences (<>)", + "line_range": [ + 614, + 617 + ] + }, + { + "text": "By default, the FENCE instruction ensures that all memory accesses from instructions preceding the fence in program order (the \"predecessor set\") appear earlier in the global memory order than memory accesses from instructions appearing after the fence in program order (the \"successor set\").", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Fences (<>)", + "line_range": [ + 619, + 629 + ] + }, + { + "text": "However, fences can optionally further restrict the predecessor set and/or the successor set to a smaller set of memory accesses in order to provide some speedup.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Fences (<>)", + "line_range": [ + 619, + 629 + ] + }, + { + "text": "Specifically, fences have PR, PW, SR, and SW bits which restrict the predecessor and/or successor sets.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Fences (<>)", + "line_range": [ + 619, + 629 + ] + }, + { + "text": "The predecessor set includes loads (resp.stores) if and only if PR (resp.PW) is set.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Fences (<>)", + "line_range": [ + 619, + 629 + ] + }, + { + "text": "Similarly, the successor set includes loads (resp.stores) if and only if SR (resp.SW) is set.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Fences (<>)", + "line_range": [ + 619, + 629 + ] + }, + { + "text": "The FENCE encoding currently has nine non-trivial combinations of the four bits PR, PW, SR, and SW, plus one extra encoding FENCE.TSO which facilitates mapping of \"acquire+release\" or RVTSO semantics.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Fences (<>)", + "line_range": [ + 631, + 636 + ] + }, + { + "text": "The remaining seven combinations have empty predecessor and/or successor sets and hence are no-ops.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Fences (<>)", + "line_range": [ + 631, + 636 + ] + }, + { + "text": "Of the ten non-trivial options, six are commonly used in practice:", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Fences (<>)", + "line_range": [ + 631, + 636 + ] + }, + { + "text": "FENCE RW,RW * FENCE.TSO * FENCE RW,W * FENCE R,RW * FENCE R,R * FENCE W,W", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Fences (<>)", + "line_range": [ + 638, + 643 + ] + }, + { + "text": "FENCE instructions using other combinations of PR, PW, SR, and SW are not normally used in the Linux or C++ memory models but are otherwise well defined.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Fences (<>)", + "line_range": [ + 645, + 647 + ] + }, + { + "text": "Finally, we note that since RISC-V uses a multi-copy atomic memory model, programmers can reason about fences bits in a thread-local manner.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Fences (<>)", + "line_range": [ + 649, + 652 + ] + }, + { + "text": "Fences in RISC-V are not cumulative, as they are in some non-multi-copy-atomic memory models.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Fences (<>)", + "line_range": [ + 649, + 652 + ] + }, + { + "text": "[IMPORTANT] : a has an acquire annotation", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Explicit Synchronization (<>)", + "line_range": [ + 657, + 659 + ] + }, + { + "text": ": b has a release annotation", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Explicit Synchronization (<>)", + "line_range": [ + 661, + 661 + ] + }, + { + "text": ": a and b both have RCsc annotations", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Explicit Synchronization (<>)", + "line_range": [ + 663, + 663 + ] + }, + { + "text": "An acquire operation, as would be used at the start of a critical section, requires all memory operations following the acquire in program order to also follow the acquire in the global memory order.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Explicit Synchronization (<>)", + "line_range": [ + 668, + 676 + ] + }, + { + "text": "This ensures, for example, that all loads and stores inside the critical section are up to date with respect to the synchronization variable being used to protect it.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Explicit Synchronization (<>)", + "line_range": [ + 668, + 676 + ] + }, + { + "text": "Acquire ordering can be enforced in one of two ways: with an acquire annotation, which enforces ordering with respect to just the synchronization variable itself, or with a FENCE R,RW, which enforces ordering with respect to all previous loads.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Explicit Synchronization (<>)", + "line_range": [ + 668, + 676 + ] + }, + { + "text": ".A spinlock with atomics [source%linenums,asm] .... sd x1, (a1) Arbitrary unrelated store ld x2, (a2) Arbitrary unrelated load li t0, 1 Initialize swap value. again: amoswap.w.aq t0, t0, (a0) Attempt to acquire lock. bnez t0, again Retry if held. ...", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Explicit Synchronization (<>)", + "line_range": [ + 678, + 694 + ] + }, + { + "text": "Critical section. ... amoswap.w.rl x0, x0, (a0) Release lock by storing 0. sd x3, (a3) Arbitrary unrelated store ld x4, (a4) Arbitrary unrelated load ....", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Explicit Synchronization (<>)", + "line_range": [ + 678, + 694 + ] + }, + { + "text": "Because this example uses aq, the loads and stores in the critical section are guaranteed to appear in the global memory order after the AMOSWAP used to acquire the lock.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Explicit Synchronization (<>)", + "line_range": [ + 696, + 702 + ] + }, + { + "text": "However, assuming `a0`, `a1`, and `a2` point to different memory locations, the loads and stores in the critical section may or may not appear after the \"Arbitrary unrelated load\" at the beginning of the example in the global memory order.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Explicit Synchronization (<>)", + "line_range": [ + 696, + 702 + ] + }, + { + "text": ".A spinlock with fences [source%linenums,asm] .... sd x1, (a1) Arbitrary unrelated store ld x2, (a2) Arbitrary unrelated load li t0, 1 Initialize swap value. again: amoswap.w t0, t0, (a0) Attempt to acquire lock. fence r, rw Enforce \"acquire\" memory ordering bnez t0, again Retry if held. ...", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Explicit Synchronization (<>)", + "line_range": [ + 704, + 722 + ] + }, + { + "text": "Critical section. ... fence rw, w Enforce \"release\" memory ordering amoswap.w x0, x0, (a0) Release lock by storing 0. sd x3, (a3) Arbitrary unrelated store ld x4, (a4) Arbitrary unrelated load ....", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Explicit Synchronization (<>)", + "line_range": [ + 704, + 722 + ] + }, + { + "text": "Now, consider the alternative in .", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Explicit Synchronization (<>)", + "line_range": [ + 724, + 735 + ] + }, + { + "text": "In this case, even though the AMOSWAP does not enforce ordering with an aq bit, the fence nevertheless enforces that the acquire AMOSWAP appears earlier in the global memory order than all loads and stores in the critical section.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Explicit Synchronization (<>)", + "line_range": [ + 724, + 735 + ] + }, + { + "text": "Note, however, that in this case, the fence also enforces additional orderings: it also requires that the \"Arbitrary unrelated load\" at the start of the program appears earlier in the global memory order than the loads and stores of the critical section. (This particular fence does not, however, enforce any ordering with respect to the \"Arbitrary unrelated store\" at the start of the snippet.) In this way, fence-enforced orderings are slightly coarser than orderings enforced by .aq.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Explicit Synchronization (<>)", + "line_range": [ + 724, + 735 + ] + }, + { + "text": "Release orderings work exactly the same as acquire orderings, just in the opposite direction.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Explicit Synchronization (<>)", + "line_range": [ + 737, + 748 + ] + }, + { + "text": "Release semantics require all loads and stores preceding the release operation in program order to also precede the release operation in the global memory order.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Explicit Synchronization (<>)", + "line_range": [ + 737, + 748 + ] + }, + { + "text": "This ensures, for example, that memory accesses in a critical section appear before the lock-releasing store in the global memory order.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Explicit Synchronization (<>)", + "line_range": [ + 737, + 748 + ] + }, + { + "text": "Just as for acquire semantics, release semantics can be enforced using release annotations or with a FENCE RW,W operation.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Explicit Synchronization (<>)", + "line_range": [ + 737, + 748 + ] + }, + { + "text": "Using the same examples, the ordering between the loads and stores in the critical section and the \"Arbitrary unrelated store\" at the end of the code snippet is enforced only by the FENCE RW,W in , not by the rl in .", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Explicit Synchronization (<>)", + "line_range": [ + 737, + 748 + ] + }, + { + "text": "With RCpc annotations alone, store-release-to-load-acquire ordering is not enforced.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Explicit Synchronization (<>)", + "line_range": [ + 750, + 757 + ] + }, + { + "text": "This facilitates the porting of code written under the TSO and/or RCpc memory models.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Explicit Synchronization (<>)", + "line_range": [ + 750, + 757 + ] + }, + { + "text": "To enforce store-release-to-load-acquire ordering, the code must use store-release-RCsc and load-acquire-RCsc operations so that PPO rule 7 applies. RCpc alone is sufficient for many use cases in C/C\\++ but is insufficient for many other use cases in C/C++, Java, and Linux, to name just a few examples; see for details.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Explicit Synchronization (<>)", + "line_range": [ + 750, + 757 + ] + }, + { + "text": "PPO rule 8 indicates that an SC must appear after its paired LR in the global memory order.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Explicit Synchronization (<>)", + "line_range": [ + 759, + 764 + ] + }, + { + "text": "This will follow naturally from the common use of LR/SC to perform an atomic read-modify-write operation due to the inherent data dependency.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Explicit Synchronization (<>)", + "line_range": [ + 759, + 764 + ] + }, + { + "text": "However, PPO rule 8 also applies even when the value being stored does not syntactically depend on the value returned by the paired LR.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Explicit Synchronization (<>)", + "line_range": [ + 759, + 764 + ] + }, + { + "text": "Lastly, we note that, as with fences, ordering annotations are not cumulative.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Explicit Synchronization (<>)", + "line_range": [ + 766, + 767 + ] + }, + { + "text": "[IMPORTANT] : b has a syntactic address dependency on a", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)", + "line_range": [ + 772, + 775 + ] + }, + { + "text": ": b has a syntactic data dependency on a", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)", + "line_range": [ + 777, + 777 + ] + }, + { + "text": ": b is a store, and b has a syntactic control dependency on a", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)", + "line_range": [ + 779, + 780 + ] + }, + { + "text": "Dependencies from a load to a later memory operation in the same hart are respected by the RVWMO memory model.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)", + "line_range": [ + 782, + 789 + ] + }, + { + "text": "The Alpha memory model was notable for choosing not to enforce the ordering of such dependencies, but most modern hardware and software memory models consider allowing dependent instructions to be reordered too confusing and counterintuitive.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)", + "line_range": [ + 782, + 789 + ] + }, + { + "text": "Furthermore, modern code sometimes intentionally uses such dependencies as a particularly lightweight ordering enforcement mechanism.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)", + "line_range": [ + 782, + 789 + ] + }, + { + "text": "The terms in work as follows.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)", + "line_range": [ + 791, + 805 + ] + }, + { + "text": "Instructions are said to carry dependencies from their source register(s) to their destination register(s) whenever the value written into each destination register is a function of the source register(s).", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)", + "line_range": [ + 791, + 805 + ] + }, + { + "text": "For most instructions, this means that the destination register(s) carry a dependency from all source register(s).", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)", + "line_range": [ + 791, + 805 + ] + }, + { + "text": "However, there are a few notable exceptions.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)", + "line_range": [ + 791, + 805 + ] + }, + { + "text": "In the case of memory instructions, the value written into the destination register ultimately comes from the memory system rather than from the source register(s) directly, and so this breaks the chain of dependencies carried from the source register(s).", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)", + "line_range": [ + 791, + 805 + ] + }, + { + "text": "In the case of unconditional jumps, the value written into the destination register comes from the current `pc` (which is never considered a source register by the memory model), and so likewise, JALR (the only jump with a source register) does not carry a dependency from rs1 to rd.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)", + "line_range": [ + 791, + 805 + ] + }, + { + "text": ".(c) has a syntactic dependency on both (a) and (b) via fflags, a destination register that both (a) and (b) implicitly accumulate into [.text-center,source%linenums,asm] ---- (a) fadd f3,f1,f2 (b) fadd f6,f4,f5 (c) csrrs a0,fflags,x0 ----", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)", + "line_range": [ + 807, + 814 + ] + }, + { + "text": "The notion of accumulating into a destination register rather than writing into it reflects the behavior of CSRs such as `fflags`.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)", + "line_range": [ + 816, + 820 + ] + }, + { + "text": "In particular, an accumulation into a register does not clobber any previous writes or accumulations into the same register.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)", + "line_range": [ + 816, + 820 + ] + }, + { + "text": "For example, in , (c) has a syntactic dependency on both (a) and (b).", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)", + "line_range": [ + 816, + 820 + ] + }, + { + "text": "Like other modern memory models, the RVWMO memory model uses syntactic rather than semantic dependencies.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)", + "line_range": [ + 822, + 829 + ] + }, + { + "text": "In other words, this definition depends on the identities of the registers being accessed by different instructions, not the actual contents of those registers.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)", + "line_range": [ + 822, + 829 + ] + }, + { + "text": "This means that an address, control, or data dependency must be enforced even if the calculation could seemingly be `optimized away`.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)", + "line_range": [ + 822, + 829 + ] + }, + { + "text": "This choice ensures that RVWMO remains compatible with code that uses these false syntactic dependencies as a lightweight ordering mechanism.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)", + "line_range": [ + 822, + 829 + ] + }, + { + "text": ".A syntactic address dependency [.text-center, source%linenums, asm] ---- ld a1,0(s0) xor a2,a1,a1 add s1,s1,a2 ld a5,0(s1) ----", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)", + "line_range": [ + 831, + 839 + ] + }, + { + "text": "For example, there is a syntactic address dependency from the memory operation generated by the first instruction to the memory operation generated by the last instruction in , even though `a1` XOR `a1` is zero and hence has no effect on the address accessed by the second load.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)", + "line_range": [ + 841, + 846 + ] + }, + { + "text": "The benefit of using dependencies as a lightweight synchronization mechanism is that the ordering enforcement requirement is limited only to the specific two instructions in question.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)", + "line_range": [ + 848, + 856 + ] + }, + { + "text": "Other non-dependent instructions may be freely reordered by aggressive implementations.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)", + "line_range": [ + 848, + 856 + ] + }, + { + "text": "One alternative would be to use a load-acquire, but this would enforce ordering for the first load with respect to all subsequent instructions.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)", + "line_range": [ + 848, + 856 + ] + }, + { + "text": "Another would be to use a FENCE R,R, but this would include all previous and all subsequent loads, making this option more expensive.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)", + "line_range": [ + 848, + 856 + ] + }, + { + "text": ".A syntactic control dependency [.text-center, source%linenums, asm] ---- lw x1,0(x2) bne x1,x0,next sw x3,0(x4) next: sw x5,0(x6) ----", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)", + "line_range": [ + 858, + 866 + ] + }, + { + "text": "Control dependencies behave differently from address and data dependencies in the sense that a control dependency always extends to all instructions following the original target in program order.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)", + "line_range": [ + 868, + 874 + ] + }, + { + "text": "Consider the instruction at `next` will always execute, but the memory operation generated by that last instruction nevertheless still has a control dependency from the memory operation generated by the first instruction.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)", + "line_range": [ + 868, + 874 + ] + }, + { + "text": ".Another syntactic control dependency [.text-center,source%linenums,asm] ---- lw x1,0(x2) bne x1,x0,next next: sw x3,0(x4) ----", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)", + "line_range": [ + 876, + 883 + ] + }, + { + "text": "Even though both branch outcomes have the same target, there is still a control dependency from the memory operation generated by the first instruction in this snippet to the memory operation generated by the last instruction.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)", + "line_range": [ + 885, + 892 + ] + }, + { + "text": "This definition of control dependency is subtly stronger than what might be seen in other contexts (e.g., C++), but it conforms with standard definitions of control dependencies in the literature.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)", + "line_range": [ + 885, + 892 + ] + }, + { + "text": "Notably, PPO rules are also intentionally designed to respect dependencies that originate from the output of a successful store-conditional instruction.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)", + "line_range": [ + 894, + 909 + ] + }, + { + "text": "Typically, an SC instruction will be followed by a conditional branch checking whether the outcome was successful; this implies that there will be a control dependency from the store operation generated by the SC instruction to any memory operations following the branch. PPO rule in turn implies that any subsequent store operations will appear later in the global memory order than the store operation generated by the SC.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)", + "line_range": [ + 894, + 909 + ] + }, + { + "text": "However, since control, address, and data dependencies are defined over memory operations, and since an unsuccessful SC does not generate a memory operation, no order is enforced between unsuccessful SC and its dependent instructions.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)", + "line_range": [ + 894, + 909 + ] + }, + { + "text": "Moreover, since SC is defined to carry dependencies from its source registers to rd only when the SC is successful, an unsuccessful SC has no effect on the global memory order.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)", + "line_range": [ + 894, + 909 + ] + }, + { + "text": ".A variant of the LB litmus test (outcome forbidden) [float=\"center\",align=\"center\",cols=\".^1a,.^1a\",frame=\"none\",grid=\"none\",options=\"noheader\"] | | ! 4+!Initial values: 0(s0)=1; 0(s2)=1 4+! 2+^!Hart 0 2+^!Hart 1 !(a) !ld a0,0(s0) !(e) !ld a3,0(s2) !(b) !lr a1,0(s1) !(f) !sd a3,0(s0) !(c) !sc a2,a0,0(s1) ! ! !(d) !sd a2,0(s2) ! ! 4+!Outcome: `a0=0`, `a3=0` ! | ! //a! graphviz::images/graphviz/litmuslblrsc.txt[] a! image::graphviz/litmuslblrsc.png[] ! |", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)", + "line_range": [ + 911, + 932 + ] + }, + { + "text": "In addition, the choice to respect dependencies originating at store-conditional instructions ensures that certain out-of-thin-air-like behaviors will be prevented.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)", + "line_range": [ + 934, + 946 + ] + }, + { + "text": "Suppose a hypothetical implementation could occasionally make some early guarantee that a store-conditional operation will succeed.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)", + "line_range": [ + 934, + 946 + ] + }, + { + "text": "In this case, (c) could return 0 to `a2` early (before actually executing), allowing the sequence (d), (e), (f), (a), and then (b) to execute, and then (c) might execute (successfully) only at that point.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)", + "line_range": [ + 934, + 946 + ] + }, + { + "text": "This would imply that (c) writes its own success value to `0(s1)`! Fortunately, this situation and others like it are prevented by the fact that RVWMO respects dependencies originating at the stores generated by successful SC instructions.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)", + "line_range": [ + 934, + 946 + ] + }, + { + "text": "We also note that syntactic dependencies between instructions only have any force when they take the form of a syntactic address, control, and/or data dependency.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)", + "line_range": [ + 948, + 956 + ] + }, + { + "text": "For example: a syntactic dependency between two `F` instructions via one of the `accumulating CSRs` in does not imply that the two `F` instructions must be executed in order.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)", + "line_range": [ + 948, + 956 + ] + }, + { + "text": "Such a dependency would only serve to ultimately set up later a dependency from both `F` instructions to a later CSR instruction accessing the CSR flag in question.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Syntactic Dependencies (<>)", + "line_range": [ + 948, + 956 + ] + }, + { + "text": "[IMPORTANT] : b is a load, and there exists some store m between a and b in program order such that m has an address or data dependency on a, and b returns a value written by m", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Pipeline Dependencies (<>)", + "line_range": [ + 962, + 967 + ] + }, + { + "text": ": b is a store, and there exists some instruction m between a and b in program order such that m has an address dependency on a", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Pipeline Dependencies (<>)", + "line_range": [ + 969, + 971 + ] + }, + { + "text": ".Because of PPO and the data dependency from (d) to (e), (d) must also precede (f) in the global memory order (outcome forbidden) [float=\"center\",align=\"center\",cols=\".^1a,.^1a\",frame=\"none\",grid=\"none\",options=\"noheader\"] | | ! 2+!Hart 0 2+! Hart 1 ! !li t1, 1 !(d) !lw a0, 0(s1) !(a) !sw t1,0(s0) !(e) !sw a0, 0(s2) !(b) !fence w, w !(f) !lw a1, 0(s2) !(c) !sw t1,0(s1) ! !xor a2,a1,a1 ! ! ! !add s0,s0,a2 ! ! !(g) !lw a3,0(s0) 4+!Outcome: `a0=1`, `a3=0` ! | ! //a! graphviz::images/graphviz/litmusdatarfi.txt[] a! image::graphviz/litmusdatarfi.png[] ! |", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Pipeline Dependencies (<>)", + "line_range": [ + 973, + 994 + ] + }, + { + "text": "PPO rules and reflect behaviors of almost all real processor pipeline implementations.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Pipeline Dependencies (<>)", + "line_range": [ + 996, + 1004 + ] + }, + { + "text": "Rule states that a load cannot forward from a store until the address and data for that store are known.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Pipeline Dependencies (<>)", + "line_range": [ + 996, + 1004 + ] + }, + { + "text": "Consider (f) cannot be executed until the data for (e) has been resolved, because (f) must return the value written by (e) (or by something even later in the global memory order), and the old value must not be clobbered by the write-back of (e) before (d) has had a chance to perform.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Pipeline Dependencies (<>)", + "line_range": [ + 996, + 1004 + ] + }, + { + "text": "Therefore, (f) will never perform before (d) has performed.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Pipeline Dependencies (<>)", + "line_range": [ + 996, + 1004 + ] + }, + { + "text": ".Because of the extra store between (e) and (g), (d) no longer necessarily precedes (g) (outcome permitted)", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Pipeline Dependencies (<>)", + "line_range": [ + 1006, + 1006 + ] + }, + { + "text": "[float=\"center\",align=\"center\",cols=\".^1a,.^1a\",frame=\"none\",grid=\"none\",options=\"noheader\"] | | ! 2+!Hart 0 2+!Hart 1 2+!li t1, 1 2+^!li t1, 1 !(a) !sw t1,0(s0) !(d) !lw a0, 0(s1) !(b) !fence w, w !(e) !sw a0, 0(s2) !(c) !sw t1,0(s1) !(f) !sw t1, 0(s2) ! ! !(g) !lw a1, 0(s2) ! ! ! !xor a2,a1,a1 ! ! ! !add s0,s0,a2 ! ! !(h) !lw a3,0(s0) 4+!Outcome: `a0=1`, `a3=0` ! | ! //a! graphviz::images/graphviz/litmusdatacoirfi.txt[] a! image::graphviz/litmusdatacoirfi.png[] ! |", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Pipeline Dependencies (<>)", + "line_range": [ + 1008, + 1029 + ] + }, + { + "text": "If there were another store to the same address in between (e) and (f), as in , then (f) would no longer be dependent on the data of (e) being resolved, and hence the dependency of (f) on (d), which produces the data for (e), would be broken.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Pipeline Dependencies (<>)", + "line_range": [ + 1031, + 1035 + ] + }, + { + "text": "Rule makes a similar observation to the previous rule: a store cannot be performed at memory until all previous loads that might access the same address have themselves been performed.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Pipeline Dependencies (<>)", + "line_range": [ + 1037, + 1046 + ] + }, + { + "text": "Such a load must appear to execute before the store, but it cannot do so if the store were to overwrite the value in memory before the load had a chance to read the old value.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Pipeline Dependencies (<>)", + "line_range": [ + 1037, + 1046 + ] + }, + { + "text": "Likewise, a store generally cannot be performed until it is known that preceding instructions will not cause an exception due to failed address resolution, and in this sense, rule 13 can be seen as somewhat of a special case of rule .", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Pipeline Dependencies (<>)", + "line_range": [ + 1037, + 1046 + ] + }, + { + "text": ".Because of the address dependency from (d) to (e), (d) also precedes (f) (outcome forbidden) [float=\"center\",align=\"center\",cols=\".^1a,.^1a\",frame=\"none\",grid=\"none\",options=\"noheader\"] | | ! 2+!Hart 0 2+^!Hart 1 2+! 2+^!li t1, 1 !(a) !lw a0,0(s0) !(d) !lw a1, 0(s1) !(b) !fence rw,rw !(e) !lw a2, 0(a1) !(c) !sw s2,0(s1) !(f) !sw t1, 0(s0) 4+!Outcome: `a0=1`, `a1=t` ! | ! //a! graphviz::images/graphviz/litmusaddrpo.txt[] a! image:graphviz/litmusaddrpo.png[] ! |", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Pipeline Dependencies (<>)", + "line_range": [ + 1048, + 1067 + ] + }, + { + "text": "Consider (f) cannot be executed until the address for (e) is resolved, because it may turn out that the addresses match; i.e., that `a1=s0`.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Pipeline Dependencies (<>)", + "line_range": [ + 1069, + 1073 + ] + }, + { + "text": "Therefore, (f) cannot be sent to memory before (d) has executed and confirmed whether the addresses do indeed overlap.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Explaining the RVWMO Rules > Pipeline Dependencies (<>)", + "line_range": [ + 1069, + 1073 + ] + }, + { + "text": "RVWMO does not currently attempt to formally describe how FENCE.I, SFENCE.VMA, I/O fences, and PMAs behave.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory", + "line_range": [ + 1078, + 1084 + ] + }, + { + "text": "All of these behaviors will be described by future formalizations.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory", + "line_range": [ + 1078, + 1084 + ] + }, + { + "text": "In the meantime, the behavior of FENCE.I is described in , the behavior of SFENCE.VMA is described in the RISC-V Instruction Set Privileged Architecture Manual, and the behavior of I/O fences and the effects of PMAs are described below.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory", + "line_range": [ + 1078, + 1084 + ] + }, + { + "text": "The RISC-V Privileged ISA defines Physical Memory Attributes (PMAs) which specify, among other things, whether portions of the address space are coherent and/or cacheable.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > Coherence and Cacheability", + "line_range": [ + 1088, + 1092 + ] + }, + { + "text": "See the RISC-V Privileged ISA Specification for the complete details.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > Coherence and Cacheability", + "line_range": [ + 1088, + 1092 + ] + }, + { + "text": "Here, we simply discuss how the various details in each PMA relate to the memory model:", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > Coherence and Cacheability", + "line_range": [ + 1088, + 1092 + ] + }, + { + "text": "Main memory vs.I/O, and I/O memory ordering PMAs: the memory model as defined applies to main memory regions. I/O ordering is discussed below. * Supported access types and atomicity PMAs: the memory model is simply applied on top of whatever primitives each region supports. * Cacheability PMAs: the cacheability PMAs in general do not affect the memory model.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > Coherence and Cacheability", + "line_range": [ + 1094, + 1116 + ] + }, + { + "text": "Non-cacheable regions may have more restrictive behavior than cacheable regions, but the set of allowed behaviors does not change regardless.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > Coherence and Cacheability", + "line_range": [ + 1094, + 1116 + ] + }, + { + "text": "However, some platform-specific and/or device-specific cacheability settings may differ. * Coherence PMAs: The memory consistency model for memory regions marked as non-coherent in PMAs is currently platform-specific and/or device-specific: the load-value axiom, the atomicity axiom, and the progress axiom all may be violated with non-coherent memory.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > Coherence and Cacheability", + "line_range": [ + 1094, + 1116 + ] + }, + { + "text": "Note however that coherent memory does not require a hardware cache coherence protocol.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > Coherence and Cacheability", + "line_range": [ + 1094, + 1116 + ] + }, + { + "text": "The RISC-V Privileged ISA Specification suggests that hardware-incoherent regions of main memory are discouraged, but the memory model is compatible with hardware coherence, software coherence, implicit coherence due to read-only memory, implicit coherence due to only one agent having access, or otherwise. * Idempotency PMAs: Idempotency PMAs are used to specify memory regions for which loads and/or stores may have side effects, and this in turn is used by the microarchitecture to determine, e.g., whether prefetches are legal.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > Coherence and Cacheability", + "line_range": [ + 1094, + 1116 + ] + }, + { + "text": "This distinction does not affect the memory model.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > Coherence and Cacheability", + "line_range": [ + 1094, + 1116 + ] + }, + { + "text": "For I/O, the load value axiom and atomicity axiom in general do not apply, as both reads and writes might have device-specific side effects and may return values other than the value \"written\" by the most recent store to the same address.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > I/O Ordering", + "line_range": [ + 1120, + 1127 + ] + }, + { + "text": "Nevertheless, the following preserved program order rules still generally apply for accesses to I/O memory: memory access a precedes memory access b in global memory order if a precedes b in program order and one or more of the following holds:", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > I/O Ordering", + "line_range": [ + 1120, + 1127 + ] + }, + { + "text": ". a precedes b in preserved program order as defined in , with the exception that acquire and release ordering annotations apply only from one memory operation to another memory operation and from one I/O operation to another I/O operation, but not from a memory operation to an I/O nor vice versa . a and b are accesses to overlapping addresses in an I/O region . a and b are accesses to the same strongly ordered I/O region . a and b are accesses to I/O regions, and the channel associated with the I/O region accessed by either a or b is channel 1 . a and b are accesses to I/O regions associated with the same channel (except for channel 0)", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > I/O Ordering", + "line_range": [ + 1129, + 1143 + ] + }, + { + "text": "Note that the FENCE instruction distinguishes between main memory operations and I/O operations in its predecessor and successor sets.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > I/O Ordering", + "line_range": [ + 1145, + 1158 + ] + }, + { + "text": "To enforce ordering between I/O operations and main memory operations, code must use a FENCE with PI, PO, SI, and/or SO, plus PR, PW, SR, and/or SW.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > I/O Ordering", + "line_range": [ + 1145, + 1158 + ] + }, + { + "text": "For example, to enforce ordering between a write to main memory and an I/O write to a device register, a FENCE W,O or stronger is needed. .Ordering memory and I/O accesses [.text-center,source%linenums,asm] ---- sd t0, 0(a0) fence w,o sd a0, 0(a1) ----", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > I/O Ordering", + "line_range": [ + 1145, + 1158 + ] + }, + { + "text": "When a fence is in fact used, implementations must assume that the device may attempt to access memory immediately after receiving the MMIO signal, and subsequent memory accesses from that device to memory must observe the effects of all accesses ordered prior to that MMIO operation.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > I/O Ordering", + "line_range": [ + 1160, + 1176 + ] + }, + { + "text": "In other words, in , suppose `0(a0)` is in main memory and `0(a1)` is the address of a device register in I/O memory.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > I/O Ordering", + "line_range": [ + 1160, + 1176 + ] + }, + { + "text": "If the device accesses `0(a0)` upon receiving the MMIO write, then that load must conceptually appear after the first store to `0(a0)` according to the rules of the RVWMO memory model.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > I/O Ordering", + "line_range": [ + 1160, + 1176 + ] + }, + { + "text": "In some implementations, the only way to ensure this will be to require that the first store does in fact complete before the MMIO write is issued.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > I/O Ordering", + "line_range": [ + 1160, + 1176 + ] + }, + { + "text": "Other implementations may find ways to be more aggressive, while others still may not need to do anything different at all for I/O and main memory accesses.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > I/O Ordering", + "line_range": [ + 1160, + 1176 + ] + }, + { + "text": "Nevertheless, the RVWMO memory model does not distinguish between these options; it simply provides an implementation-agnostic mechanism to specify the orderings that must be enforced.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > I/O Ordering", + "line_range": [ + 1160, + 1176 + ] + }, + { + "text": "Many architectures include separate notions of \"ordering\" and \"completion\" fences, especially as it relates to I/O (as opposed to regular main memory).", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > I/O Ordering", + "line_range": [ + 1178, + 1185 + ] + }, + { + "text": "Ordering fences simply ensure that memory operations stay in order, while completion fences ensure that predecessor accesses have all completed before any successors are made visible. RISC-V does not explicitly distinguish between ordering and completion fences.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > I/O Ordering", + "line_range": [ + 1178, + 1185 + ] + }, + { + "text": "Instead, this distinction is simply inferred from different uses of the FENCE bits.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > I/O Ordering", + "line_range": [ + 1178, + 1185 + ] + }, + { + "text": "For implementations that conform to the RISC-V Unix Platform Specification, I/O devices and DMA operations are required to access memory coherently and via strongly ordered I/O channels.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > I/O Ordering", + "line_range": [ + 1187, + 1195 + ] + }, + { + "text": "Therefore, accesses to regular main memory regions that are concurrently accessed by external devices can also use the standard synchronization mechanisms.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > I/O Ordering", + "line_range": [ + 1187, + 1195 + ] + }, + { + "text": "Implementations that do not conform to the Unix Platform Specification and/or in which devices do not access memory coherently will need to use mechanisms (which are currently platform-specific or device-specific) to enforce coherency.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > I/O Ordering", + "line_range": [ + 1187, + 1195 + ] + }, + { + "text": "I/O regions in the address space should be considered non-cacheable regions in the PMAs for those regions.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > I/O Ordering", + "line_range": [ + 1197, + 1199 + ] + }, + { + "text": "Such regions can be considered coherent by the PMA if they are not cached by any agent.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > I/O Ordering", + "line_range": [ + 1197, + 1199 + ] + }, + { + "text": "The ordering guarantees in this section may not apply beyond a platform-specific boundary between the RISC-V cores and the device.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > I/O Ordering", + "line_range": [ + 1201, + 1206 + ] + }, + { + "text": "In particular, I/O accesses sent across an external bus (e.g., PCIe) may be reordered before they reach their ultimate destination.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > I/O Ordering", + "line_range": [ + 1201, + 1206 + ] + }, + { + "text": "Ordering must be enforced in such situations according to the platform-specific rules of those external devices and buses.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Beyond Main Memory > I/O Ordering", + "line_range": [ + 1201, + 1206 + ] + }, + { + "text": ".Mappings from TSO operations to RISC-V operations | !x86/TSO Operation !RVWMO Mapping !Load ! `l{b|h|w|d}; fence r,rw` !Store !`fence rw,w; s{b|h|w|d}` !Atomic RMW !`amo.{w|d}.aqrl OR` + `loop:lr.{w|d}.aq; ; sc.{w|d}.aqrl; bnez loop` !Fence !`fence rw,rw` |", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1211, + 1221 + ] + }, + { + "text": "provides a mapping from TSO memory operations onto RISC-V memory instructions.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1223, + 1235 + ] + }, + { + "text": "Normal x86 loads and stores are all inherently acquire-RCpc and release-RCpc operations: TSO enforces all load-load, load-store, and store-store ordering by default.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1223, + 1235 + ] + }, + { + "text": "Therefore, under RVWMO, all TSO loads must be mapped onto a load followed by FENCE R,RW, and all TSO stores must be mapped onto FENCE RW,W followed by a store. TSO atomic read-modify-writes and x86 instructions using the LOCK prefix are fully ordered and can be implemented either via an AMO with both aq and rl set, or via an LR with aq set, the arithmetic operation in question, an SC with both aq and rl set, and a conditional branch checking the success condition.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1223, + 1235 + ] + }, + { + "text": "In the latter case, the rl annotation on the LR turns out (for non-obvious reasons) to be redundant and can be omitted.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1223, + 1235 + ] + }, + { + "text": "Alternatives to are also possible. A TSO store can be mapped onto AMOSWAP with rl set.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1237, + 1245 + ] + }, + { + "text": "However, since RVWMO PPO Rule forbids forwarding of values from AMOs to subsequent loads, the use of AMOSWAP for stores may negatively affect performance. A TSO load can be mapped using LR with aq set: all such LR instructions will be unpaired, but that fact in and of itself does not preclude the use of LR for loads.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1237, + 1245 + ] + }, + { + "text": "However, again, this mapping may also negatively affect performance if it puts more pressure on the reservation mechanism than was originally intended.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1237, + 1245 + ] + }, + { + "text": ".Mappings from Power operations to RISC-V operations | !Power Operation !RVWMO Mapping !Load !`l{b|h|w|d}` !Load-Reserve !`lr.{w|d}` !Store !`s{b|h|w|d}` !Store-Conditional !`sc.{w|d}` !`lwsync` !`fence.tso` !`sync` !`fence rw,rw` !`isync` !`fence.i; fence r,r` |", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1247, + 1259 + ] + }, + { + "text": "provides a mapping from Power memory operations onto RISC-V memory instructions.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1261, + 1265 + ] + }, + { + "text": "Power ISYNC maps on RISC-V to a FENCE.I followed by a FENCE R,R; the latter fence is needed because ISYNC is used to define a \"control+control fence\" dependency that is not present in RVWMO.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1261, + 1265 + ] + }, + { + "text": ".Mappings from ARM operations to RISC-V operations | !ARM Operation !RVWMO Mapping !Load !`l{b|h|w|d}` !Load-Acquire !`fence rw, rw; l{b|h|w|d}; fence r,rw` !Load-Exclusive !`lr.{w|d}` !Load-Acquire-Exclusive !`lr.{w|d}.aqrl` !Store !`s{b|h|w|d}` !Store-Release !`fence rw,w; s{b|h|w|d}` !Store-Exclusive !`sc.{w|d}` !Store-Release-Exclusive !`sc.{w|d}.rl` !`dmb` !`fence rw,rw` !`dmb.ld` !`fence r,rw` !`dmb.st` !`fence w,w` !`isb` !`fence.i; fence r,r` |", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1267, + 1284 + ] + }, + { + "text": "provides a mapping from ARM memory operations onto RISC-V memory instructions.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1286, + 1298 + ] + }, + { + "text": "Since RISC-V does not currently have plain load and store opcodes with aq or rl annotations, ARM load-acquire and store-release operations should be mapped using fences instead.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1286, + 1298 + ] + }, + { + "text": "Furthermore, in order to enforce store-release-to-load-acquire ordering, there must be a FENCE RW,RW between the store-release and load-acquire; enforces this by always placing the fence in front of each acquire operation. ARM load-exclusive and store-exclusive instructions can likewise map onto their RISC-V LR and SC equivalents, but instead of placing a FENCE RW,RW in front of an LR with aq set, we simply also set rl instead. ARM ISB maps on RISC-V to FENCE.I followed by FENCE R,R similarly to how ISYNC maps for Power.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1286, + 1298 + ] + }, + { + "text": ".Mappings from Linux memory primitives to RISC-V primitives. | !Linux Operation !RVWMO Mapping", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1300, + 1304 + ] + }, + { + "text": "!`mb()` !`fence iorw,iorw`", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1316, + 1316 + ] + }, + { + "text": "!`smploadacquire()` !`l{b|h|w|d}; fence r,rw`", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1322, + 1322 + ] + }, + { + "text": "!`smpstorerelease()` !`fence.tso; s{b|h|w|d}`", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1324, + 1324 + ] + }, + { + "text": "!Linux Construct !RVWMO AMO Mapping", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1326, + 1326 + ] + }, + { + "text": "!`atomic relaxed` !`amo .{w|d}`", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1328, + 1328 + ] + }, + { + "text": "!`atomic acquire` !`amo .{w|d}.aq`", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1330, + 1330 + ] + }, + { + "text": "!`atomic release` !`amo .{w|d}.rl`", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1332, + 1332 + ] + }, + { + "text": "!`atomic ` !`amo .{w|d}.aqrl`", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1334, + 1334 + ] + }, + { + "text": "!Linux Construct !RVWMO LR/SC Mapping", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1336, + 1336 + ] + }, + { + "text": "!`atomic relaxed` !`loop:lr.{w|d}; ; sc.{w|d}; bnez loop`", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1338, + 1338 + ] + }, + { + "text": "!`atomic acquire` !`loop:lr.{w|d}.aq; ; sc.{w|d}; bnez loop`", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1340, + 1340 + ] + }, + { + "text": "!`atomic release` !`loop:lr.{w|d}; ; sc.{w|d}.aqrl^*^; bnez loop OR`", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1342, + 1342 + ] + }, + { + "text": "! !`fence.tso; loop:lr.{w|d}; ; sc.{w|d}^*^; bnez loop`", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1344, + 1344 + ] + }, + { + "text": "!`atomic ` !`loop:lr.{w|d}.aq;` `; sc.{w|d}.aqrl; bnez loop`", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1346, + 1346 + ] + }, + { + "text": "With regards to , other constructs (such as spinlocks) should follow accordingly.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1350, + 1354 + ] + }, + { + "text": "Platforms or devices with non-coherent DMA may need additional synchronization (such as cache flush or invalidate mechanisms); currently any such extra synchronization will be device-specific.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1350, + 1354 + ] + }, + { + "text": "provides a mapping of Linux memory ordering macros onto RISC-V memory instructions.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1356, + 1364 + ] + }, + { + "text": "The Linux fences `dmarmb()` and `dmawmb()` map onto FENCE R,R and FENCE W,W, respectively, since the RISC-V Unix Platform requires coherent DMA, but would be mapped onto FENCE RI,RI and FENCE WO,WO, respectively, on a platform with non-coherent DMA.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1356, + 1364 + ] + }, + { + "text": "Platforms with non-coherent DMA may also require a mechanism by which cache lines can be flushed and/or invalidated.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1356, + 1364 + ] + }, + { + "text": "Such mechanisms will be device-specific and/or standardized in a future extension to the ISA.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1356, + 1364 + ] + }, + { + "text": "The Linux mappings for release operations may seem stronger than necessary, but these mappings are needed to cover some cases in which Linux requires stronger orderings than the more intuitive mappings would provide.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1366, + 1376 + ] + }, + { + "text": "In particular, as of the time this text is being written, Linux is actively debating whether to require load-load, load-store, and store-store orderings between accesses in one critical section and accesses in a subsequent critical section in the same hart and protected by the same synchronization object.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1366, + 1376 + ] + }, + { + "text": "Not all combinations of FENCE RW,W/FENCE R,RW mappings with aq/rl mappings combine to provide such orderings.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1366, + 1376 + ] + }, + { + "text": "There are a few ways around this problem, including:", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1366, + 1376 + ] + }, + { + "text": "Always use FENCE RW,W/FENCE R,RW, and never use aq/rl.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1378, + 1387 + ] + }, + { + "text": "This suffices but is undesirable, as it defeats the purpose of the aq/rl modifiers. .", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1378, + 1387 + ] + }, + { + "text": "Always use aq/rl, and never use FENCE RW,W/FENCE R,RW.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1378, + 1387 + ] + }, + { + "text": "This does not currently work due to the lack of load and store opcodes with aq and rl modifiers. .", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1378, + 1387 + ] + }, + { + "text": "Strengthen the mappings of release operations such that they would enforce sufficient orderings in the presence of either type of acquire mapping.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1378, + 1387 + ] + }, + { + "text": "This is the currently recommended solution, and the one shown in .", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1378, + 1387 + ] + }, + { + "text": "RVWMO Mapping: (a) lw a0, 0(s0) (b) fence.tso // vs. fence rw,w (c) sd x0,0(s1) ... loop: (d) amoswap.d.aq a1,t1,0(s1) bnez a1,loop (e) lw a2,0(s2)", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1389, + 1391 + ] + }, + { + "text": "For example, the critical section ordering rule currently being debated by the Linux community would require (a) to be ordered before (e) in .", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1393, + 1398 + ] + }, + { + "text": "If that will indeed be required, then it would be insufficient for (b) to map as FENCE RW,W.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1393, + 1398 + ] + }, + { + "text": "That said, these mappings are subject to change as the Linux Kernel Memory Model evolves.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1393, + 1398 + ] + }, + { + "text": ".Orderings between critical sections in Linux [source%linenums,asm] ---- Linux Code: (a) int r0 = *x; (bc) spinunlock(y, 0); .... .... (d) spinlock(y); (e) int r1 = *z;", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1400, + 1410 + ] + }, + { + "text": "RVWMO Mapping: (a) lw a0, 0(s0) (b) fence.tso // vs. fence rw,w (c) sd x0,0(s1) .... loop: (d) lr.d.aq a1,(s1) bnez a1,loop sc.d a1,t1,(s1) bnez a1,loop (e) lw a2,0(s2) ----", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1412, + 1423 + ] + }, + { + "text": "provides a mapping of C11/C++11 atomic operations onto RISC-V memory instructions.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1425, + 1436 + ] + }, + { + "text": "If load and store opcodes with aq and rl modifiers are introduced, then the mappings in will suffice.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1425, + 1436 + ] + }, + { + "text": "Note however that the two mappings only interoperate correctly if `atomic(memoryorderseqcst)` is mapped using an LR that has both aq and rl set.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1425, + 1436 + ] + }, + { + "text": "Even more importantly, a sequentially consistent store, followed by a sequentially consistent load can be reordered unless the mapping of stores is strengthened by either adding a second fence or mapping the store to `amoswap.rl` instead.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1425, + 1436 + ] + }, + { + "text": ".Mappings from C/C++ primitives to RISC-V primitives. |", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1438, + 1441 + ] + }, + { + "text": "!C/C++ Construct ! RVWMO Mapping", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1443, + 1443 + ] + }, + { + "text": "!Non-atomic load ! `l{b|h|w|d}`", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1445, + 1445 + ] + }, + { + "text": "!`atomicload(memoryorderrelaxed)` !`l{b|h|w|d}`", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1447, + 1447 + ] + }, + { + "text": "!`atomicload(memoryorderacquire)` !`l{b|h|w|d}; fence r,rw`", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1449, + 1449 + ] + }, + { + "text": "!`atomicload(memoryorderseqcst)` !`fence rw,rw; l{b|h|w|d}; fence r,rw`", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1451, + 1451 + ] + }, + { + "text": "!Non-atomic store !`s{b|h|w|d}`", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1453, + 1453 + ] + }, + { + "text": "!`atomicstore(memoryorderrelaxed)` !`s{b|h|w|d}`", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1455, + 1455 + ] + }, + { + "text": "!`atomicstore(memoryorderrelease)` !`fence rw,w; s{b|h|w|d}`", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1457, + 1457 + ] + }, + { + "text": "!`atomicstore(memoryorderseqcst)` !`fence rw,w; s{b|h|w|d}`", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1459, + 1459 + ] + }, + { + "text": "!`atomicthreadfence(memoryorderacquire)` !`fence r,rw`", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1461, + 1461 + ] + }, + { + "text": "!`atomicthreadfence(memoryorderrelease)` !`fence rw,w`", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1463, + 1463 + ] + }, + { + "text": "!`atomicthreadfence(memoryorderacqrel)` !`fence.tso`", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1465, + 1465 + ] + }, + { + "text": "!`atomicthreadfence(memoryorderseqcst)` !`fence rw,rw`", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1467, + 1467 + ] + }, + { + "text": "!C/C++ Construct !RVWMO AMO Mapping", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1469, + 1469 + ] + }, + { + "text": "!`atomic(memoryorderrelaxed)` !`amo.{w|d}`", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1471, + 1471 + ] + }, + { + "text": "!`atomic(memoryorderacquire)` !`amo.{w|d}.aq`", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1473, + 1473 + ] + }, + { + "text": "!`atomic(memoryorderrelease)` !`amo.{w|d}.rl`", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1475, + 1475 + ] + }, + { + "text": "!`atomic(memoryorderacqrel)` !`amo.{w|d}.aqrl`", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1477, + 1477 + ] + }, + { + "text": "!`atomic(memoryorderseqcst)` !`amo.{w|d}.aqrl`", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1479, + 1479 + ] + }, + { + "text": "!C/C++ Construct !RVWMO LR/SC Mapping", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1481, + 1481 + ] + }, + { + "text": "!`atomic(memoryorderrelaxed)` !`loop:lr.{w|d}; ; sc.{w|d};`", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1483, + 1483 + ] + }, + { + "text": "!`atomic(memoryorderacquire)` !`loop:lr.{w|d}.aq; ; sc.{w|d};`", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1487, + 1487 + ] + }, + { + "text": "!`atomic(memoryorderrelease)` !`loop:lr.{w|d}; ; sc.{w|d}.rl;`", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1491, + 1491 + ] + }, + { + "text": "!`atomic(memoryorderacqrel)` !`loop:lr.{w|d}.aq; ; sc.{w|d}.rl;`", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1495, + 1495 + ] + }, + { + "text": "!`atomic(memoryorderseqcst)` !`loop:lr.{w|d}.aqrl; ;`", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1499, + 1499 + ] + }, + { + "text": "! !`sc.{w|d}.rl; bnez loop`", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1501, + 1501 + ] + }, + { + "text": ".Hypothetical mappings from C/C++ primitives to RISC-V primitives, if native load-acquire and store-release opcodes are introduced. | !C/C++ Construct !RVWMO Mapping", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1505, + 1509 + ] + }, + { + "text": "!Non-atomic load !`l{b|h|w|d}`", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1511, + 1511 + ] + }, + { + "text": "!`atomicload(memoryorderrelaxed)` !`l{b|h|w|d}`", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1513, + 1513 + ] + }, + { + "text": "!`atomicload(memoryorderacquire)` !`l{b|h|w|d}.aq`", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1515, + 1515 + ] + }, + { + "text": "!`atomicload(memoryorderseqcst)` !`l{b|h|w|d}.aq`", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1517, + 1517 + ] + }, + { + "text": "!Non-atomic store !`s{b|h|w|d}`", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1519, + 1519 + ] + }, + { + "text": "!`atomicstore(memoryorderrelaxed)` !`s{b|h|w|d}`", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1521, + 1521 + ] + }, + { + "text": "!`atomicstore(memoryorderrelease)` !`s{b|h|w|d}.rl`", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1523, + 1523 + ] + }, + { + "text": "!`atomicstore(memoryorderseqcst)` !`s{b|h|w|d}.rl`", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1525, + 1525 + ] + }, + { + "text": "!`atomicthreadfence(memoryorderacquire)` !`fence r,rw`", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1527, + 1527 + ] + }, + { + "text": "!`atomicthreadfence(memoryorderrelease)` !`fence rw,w`", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1529, + 1529 + ] + }, + { + "text": "!`atomicthreadfence(memoryorderacqrel)` !`fence.tso`", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1531, + 1531 + ] + }, + { + "text": "!`atomicthreadfence(memoryorderseqcst)` !`fence rw,rw`", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1533, + 1533 + ] + }, + { + "text": "!C/C++ Construct !RVWMO AMO Mapping", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1535, + 1535 + ] + }, + { + "text": "!`atomic(memoryorderrelaxed)` !`amo.{w|d}`", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1537, + 1537 + ] + }, + { + "text": "!`atomic(memoryorderacquire)` !`amo.{w|d}.aq`", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1539, + 1539 + ] + }, + { + "text": "!`atomic(memoryorderrelease)` !`amo.{w|d}.rl`", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1541, + 1541 + ] + }, + { + "text": "!`atomic(memoryorderacqrel)` !`amo.{w|d}.aqrl`", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1543, + 1543 + ] + }, + { + "text": "!`atomic(memoryorderseqcst)` !`amo.{w|d}.aqrl`", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1545, + 1545 + ] + }, + { + "text": "!C/C++ Construct !RVWMO LR/SC Mapping", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1547, + 1547 + ] + }, + { + "text": "!`atomic(memoryorderrelaxed)` !`lr.{w|d}; ; sc.{w|d}`", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1549, + 1549 + ] + }, + { + "text": "!`atomic(memoryorderacquire)` !`lr.{w|d}.aq; ; sc.{w|d}`", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1551, + 1551 + ] + }, + { + "text": "!`atomic(memoryorderrelease)` !`lr.{w|d}; ; sc.{w|d}.rl`", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1553, + 1553 + ] + }, + { + "text": "!`atomic(memoryorderacqrel)` !`lr.{w|d}.aq; ; sc.{w|d}.rl`", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1555, + 1555 + ] + }, + { + "text": "!`atomic(memoryorderseqcst)` !`lr.{w|d}.aq^*^ ; sc.{w|d}.rl`", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1557, + 1557 + ] + }, + { + "text": "2+!^*^ must be `lr.{w|d}.aqrl` in order to interoperate with code mapped per |", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1559, + 1560 + ] + }, + { + "text": "Any AMO can be emulated by an LR/SC pair, but care must be taken to ensure that any PPO orderings that originate from the LR are also made to originate from the SC, and that any PPO orderings that terminate at the SC are also made to terminate at the LR.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1562, + 1572 + ] + }, + { + "text": "For example, the LR must also be made to respect any data dependencies that the AMO has, given that load operations do not otherwise have any notion of a data dependency.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1562, + 1572 + ] + }, + { + "text": "Likewise, the effect a FENCE R,R elsewhere in the same hart must also be made to apply to the SC, which would not otherwise respect that fence.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1562, + 1572 + ] + }, + { + "text": "The emulator may achieve this effect by simply mapping AMOs onto `lr.aq; ; sc.aqrl`, matching the mapping used elsewhere for fully ordered atomics.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1562, + 1572 + ] + }, + { + "text": "These C11/C++11 mappings require the platform to provide the following Physical Memory Attributes (as defined in the RISC-V Privileged ISA) for all memory:", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1574, + 1576 + ] + }, + { + "text": "main memory * coherent * AMOArithmetic * RsrvEventual", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1578, + 1581 + ] + }, + { + "text": "Platforms with different attributes may require different mappings, or require platform-specific SW (e.g., memory-mapped I/O).", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Code Porting and Mapping Guidelines", + "line_range": [ + 1583, + 1584 + ] + }, + { + "text": "The RVWMO and RVTSO memory models by no means preclude microarchitectures from employing sophisticated speculation techniques or other forms of optimization in order to deliver higher performance.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Implementation Guidelines", + "line_range": [ + 1588, + 1600 + ] + }, + { + "text": "The models also do not impose any requirement to use any one particular cache hierarchy, nor even to use a cache coherence protocol at all.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Implementation Guidelines", + "line_range": [ + 1588, + 1600 + ] + }, + { + "text": "Instead, these models only specify the behaviors that can be exposed to software.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Implementation Guidelines", + "line_range": [ + 1588, + 1600 + ] + }, + { + "text": "Microarchitectures are free to use any pipeline design, any coherent or non-coherent cache hierarchy, any on-chip interconnect, etc., as long as the design only admits executions that satisfy the memory model rules.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Implementation Guidelines", + "line_range": [ + 1588, + 1600 + ] + }, + { + "text": "That said, to help people understand the actual implementations of the memory model, in this section we provide some guidelines on how architects and programmers should interpret the models' rules.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Implementation Guidelines", + "line_range": [ + 1588, + 1600 + ] + }, + { + "text": "Both RVWMO and RVTSO are multi-copy atomic (or other-multi-copy-atomic): any store value that is visible to a hart other than the one that originally issued it must also be conceptually visible to all other harts in the system.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Implementation Guidelines", + "line_range": [ + 1602, + 1611 + ] + }, + { + "text": "In other words, harts may forward from their own previous stores before those stores have become globally visible to all harts, but no early inter-hart forwarding is permitted.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Implementation Guidelines", + "line_range": [ + 1602, + 1611 + ] + }, + { + "text": "Multi-copy atomicity may be enforced in a number of ways.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Implementation Guidelines", + "line_range": [ + 1602, + 1611 + ] + }, + { + "text": "It might hold inherently due to the physical design of the caches and store buffers, it may be enforced via a single-writer/multiple-reader cache coherence protocol, or it might hold due to some other mechanism.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Implementation Guidelines", + "line_range": [ + 1602, + 1611 + ] + }, + { + "text": "Although multi-copy atomicity does impose some restrictions on the microarchitecture, it is one of the key properties keeping the memory model from becoming extremely complicated.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Implementation Guidelines", + "line_range": [ + 1613, + 1624 + ] + }, + { + "text": "For example, a hart may not legally forward a value from a neighbor hart's private store buffer (unless of course it is done in such a way that no new illegal behaviors become architecturally visible).", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Implementation Guidelines", + "line_range": [ + 1613, + 1624 + ] + }, + { + "text": "Nor may a cache coherence protocol forward a value from one hart to another until the coherence protocol has invalidated all older copies from other caches.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Implementation Guidelines", + "line_range": [ + 1613, + 1624 + ] + }, + { + "text": "Of course, microarchitectures may (and high-performance implementations likely will) violate these rules under the covers through speculation or other optimizations, as long as any non-compliant behaviors are not exposed to the programmer.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Implementation Guidelines", + "line_range": [ + 1613, + 1624 + ] + }, + { + "text": "As a rough guideline for interpreting the PPO rules in RVWMO, we expect the following from the software perspective:", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Implementation Guidelines", + "line_range": [ + 1626, + 1627 + ] + }, + { + "text": "programmers will use PPO rules and regularly and actively. * expert programmers will use PPO rules to speed up critical paths of important data structures. * even expert programmers will rarely if ever use PPO rules and directly.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Implementation Guidelines", + "line_range": [ + 1629, + 1639 + ] + }, + { + "text": "These are included to facilitate common microarchitectural optimizations (rule ) and the operational formal modeling approach (rules and ) described in .", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Implementation Guidelines", + "line_range": [ + 1629, + 1639 + ] + }, + { + "text": "They also facilitate the process of porting code from other architectures that have similar rules.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Implementation Guidelines", + "line_range": [ + 1629, + 1639 + ] + }, + { + "text": "We also expect the following from the hardware perspective:", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Implementation Guidelines", + "line_range": [ + 1641, + 1641 + ] + }, + { + "text": "PPO rules and reflect well-understood rules that should pose few surprises to architects. * PPO rule reflects a natural and common hardware optimization, but one that is very subtle and hence is worth double checking carefully. * PPO rule may not be immediately obvious to architects, but it is a standard memory model requirement * The load value axiom, the atomicity axiom, and PPO rules reflect rules that most hardware implementations will enforce naturally, unless they contain extreme optimizations.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Implementation Guidelines", + "line_range": [ + 1643, + 1655 + ] + }, + { + "text": "Of course, implementations should make sure to double check these rules nevertheless.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Implementation Guidelines", + "line_range": [ + 1643, + 1655 + ] + }, + { + "text": "Hardware must also ensure that syntactic dependencies are not `optimized away`.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Implementation Guidelines", + "line_range": [ + 1643, + 1655 + ] + }, + { + "text": "Architectures are free to implement any of the memory model rules as conservatively as they choose.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Implementation Guidelines", + "line_range": [ + 1657, + 1659 + ] + }, + { + "text": "For example, a hardware implementation may choose to do any or all of the following:", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Implementation Guidelines", + "line_range": [ + 1657, + 1659 + ] + }, + { + "text": "interpret all fences as if they were FENCE RW,RW (or FENCE IORW,IORW, if I/O is involved), regardless of the bits actually set * implement all fences with PW and SR as if they were FENCE RW,RW (or FENCE IORW,IORW, if I/O is involved), as PW with SR is the most expensive of the four possible main memory ordering components anyway * emulate aq and rl as described in * enforcing all same-address load-load ordering, even in the presence of patterns such as `fri-rfi` and `RSW` * forbid any forwarding of a value from a store in the store buffer to a subsequent AMO or LR to the same address * forbid any forwarding of a value from an AMO or SC in the store buffer to a subsequent load to the same address * implement TSO on all memory accesses, and ignore any main memory fences that do not include PW and SR ordering (e.g., as Ztso implementations will do) * implement all atomics to be RCsc or even fully ordered, regardless of annotation", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Implementation Guidelines", + "line_range": [ + 1661, + 1677 + ] + }, + { + "text": "Architectures that implement RVTSO can safely do the following:", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Implementation Guidelines", + "line_range": [ + 1679, + 1679 + ] + }, + { + "text": "Ignore all fences that do not have both PW and SR (unless the fence also orders I/O) * Ignore all PPO rules except for rules through , since the rest are redundant with other PPO rules under RVTSO assumptions", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Implementation Guidelines", + "line_range": [ + 1681, + 1684 + ] + }, + { + "text": "Silent stores (i.e., stores that write the same value that already exists at a memory location) behave like any other store from a memory model point of view.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Implementation Guidelines", + "line_range": [ + 1688, + 1700 + ] + }, + { + "text": "Likewise, AMOs which do not actually change the value in memory (e.g., an AMOMAX for which the value in rs2 is smaller than the value currently in memory) are still semantically considered store operations.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Implementation Guidelines", + "line_range": [ + 1688, + 1700 + ] + }, + { + "text": "Microarchitectures that attempt to implement silent stores must take care to ensure that the memory model is still obeyed, particularly in cases such as RSW which tend to be incompatible with silent stores. * Writes may be merged (i.e., two consecutive writes to the same address may be merged) or subsumed (i.e., the earlier of two back-to-back writes to the same address may be elided) as long as the resulting behavior does not otherwise violate the memory model semantics.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Implementation Guidelines", + "line_range": [ + 1688, + 1700 + ] + }, + { + "text": "The question of write subsumption can be understood from the following example:", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Implementation Guidelines", + "line_range": [ + 1702, + 1703 + ] + }, + { + "text": ".Write subsumption litmus test, allowed execution [float=\"center\",align=\"center\",cols=\".^1a,.^1a\",frame=\"none\",grid=\"none\",options=\"noheader\"] | | ! 2+!Hart 0 2+^!Hart 1 2+!li t1, 3 2+^!li t3, 2 ! !li t2, 1 ! ! !(a) !sw t1,0(s0) !(d) !lw a0,0(s1) !(b) !fence w, w !(e) !sw a0,0(s0) !(c) !sw t2,0(s1) !(f) !sw t3,0(s0) ! | ! //a! graphviz::images/graphviz/litmussubsumption.txt[] a! image::graphviz/litmussubsumption.png[] ! |", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Implementation Guidelines", + "line_range": [ + 1705, + 1723 + ] + }, + { + "text": "As written, if the load (d) reads value 1, then (a) must precede (f) in the global memory order:", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Implementation Guidelines", + "line_range": [ + 1725, + 1726 + ] + }, + { + "text": "(a) precedes (c) in the global memory order because of rule 4 * (c) precedes (d) in the global memory order because of the Load Value axiom * (d) precedes (e) in the global memory order because of rule 10 * (e) precedes (f) in the global memory order because of rule 1", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Implementation Guidelines", + "line_range": [ + 1728, + 1732 + ] + }, + { + "text": "In other words the final value of the memory location whose address is in `s0` must be 2 (the value written by the store (f)) and cannot be 3 (the value written by the store (a)).", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Implementation Guidelines", + "line_range": [ + 1734, + 1736 + ] + }, + { + "text": "A very aggressive microarchitecture might erroneously decide to discard (e), as (f) supersedes it, and this may in turn lead the microarchitecture to break the now-eliminated dependency between (d) and (f) (and hence also between (a) and (f)).", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Implementation Guidelines", + "line_range": [ + 1738, + 1744 + ] + }, + { + "text": "This would violate the memory model rules, and hence it is forbidden.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Implementation Guidelines", + "line_range": [ + 1738, + 1744 + ] + }, + { + "text": "Write subsumption may in other cases be legal, if for example there were no data dependency between (d) and (e).", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Implementation Guidelines", + "line_range": [ + 1738, + 1744 + ] + }, + { + "text": "We expect that any or all of the following possible future extensions would be compatible with the RVWMO memory model:", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Implementation Guidelines > Possible Future Extensions", + "line_range": [ + 1748, + 1749 + ] + }, + { + "text": "\"V\" vector ISA extensions * \"J\" JIT extension * Native encodings for load and store opcodes with aq and rl set * Fences limited to certain addresses * Cache write-back/flush/invalidate/etc.instructions", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Implementation Guidelines > Possible Future Extensions", + "line_range": [ + 1751, + 1755 + ] + }, + { + "text": ".Mixed-size discrepancy (permitted by axiomatic models, forbidden by operational model) | 2+|Hart 0 2+^|Hart 1 2+|li t1, 1 2+^|li t1, 1 |(a) |lw a0,0(s0) |(d) |lw a1,0(s1) |(b) |fence rw,rw |(e) |amoswap.w.rl a2,t1,0(s2) |(c) |sw t1,0(s1) |(f) |ld a3,0(s2) | | |(g) |lw a4,4(s2) | | | |xor a5,a4,a4 | | | |add s0,s0,a5 | | |(h) |sw t1,0(s0) 4+|Outcome: `a0=1`, `a1=1`, `a2=0`, `a3=1`, `a4=0` |", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Known Issues > Mixed-size RSW", + "line_range": [ + 1763, + 1777 + ] + }, + { + "text": ".Mixed-size discrepancy (permitted by axiomatic models, forbidden by operational model) | 2+|Hart 0 2+^|Hart 1 2+|li t1, 1 2+^|li t1, 1 |(a) |lw a0,0(s0) |(d) |ld a1,0(s1) |(b) |fence rw,rw |(e) |lw a2,4(s1) |(c) |sw t1,0(s1) | |xor a3,a2,a2 | | | |add s0,s0,a3 | | |(f) |sw t1,0(s0) 4+|Outcome: `a0=1`, `a1=1`, `a2=0` |", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Known Issues > Mixed-size RSW", + "line_range": [ + 1779, + 1791 + ] + }, + { + "text": ".Mixed-size discrepancy (permitted by axiomatic models, forbidden by operational model) | 2+|Hart 0 2+^|Hart 1 2+|li t1, 1 2+^|li t1, 1 |(a) |lw a0,0(s0) |(d) |sw t1,4(s1) |(b) |fence rw,rw |(e) |ld a1,0(s1) |(c) |sw t1,0(s1) |(f) |lw a2,4(s1) | | | |xor a3,a2,a2 | | | |add s0,s0,a3 | | |(g) |sw t1,0(s0) 4+|Outcome: `a0=1`, `a1=0x100000001`, `a2=1` |", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Known Issues > Mixed-size RSW", + "line_range": [ + 1793, + 1806 + ] + }, + { + "text": "There is a known discrepancy between the operational and axiomatic specifications within the family of mixed-size RSW variants shown in -.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Known Issues > Mixed-size RSW", + "line_range": [ + 1808, + 1827 + ] + }, + { + "text": "To address this, we may choose to add something like the following new PPO rule: Memory operation a precedes memory operation b in preserved program order (and hence also in the global memory order) if a precedes b in program order, a and b both access regular main memory (rather than I/O regions), a is a load, b is a store, there is a load m between a and b, there is a byte x that both a and m read, there is no store between a and m that writes to x, and m precedes b in PPO.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Known Issues > Mixed-size RSW", + "line_range": [ + 1808, + 1827 + ] + }, + { + "text": "In other words, in herd syntax, we may choose to add `(po-loc & rsw);ppo;[W]` to PPO.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Known Issues > Mixed-size RSW", + "line_range": [ + 1808, + 1827 + ] + }, + { + "text": "Many implementations will already enforce this ordering naturally.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Known Issues > Mixed-size RSW", + "line_range": [ + 1808, + 1827 + ] + }, + { + "text": "As such, even though this rule is not official, we recommend that implementers enforce it nevertheless in order to ensure forwards compatibility with the possible future addition of this rule to RVWMO.", + "section": "Preamble > RVWMO Explanatory Material > Why RVWMO? > Known Issues > Mixed-size RSW", + "line_range": [ + 1808, + 1827 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__unpriv__mm-formal.json b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__mm-formal.json new file mode 100644 index 0000000000..7ab5389904 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__mm-formal.json @@ -0,0 +1,1990 @@ +{ + "source_file": "src/unpriv/mm-formal.adoc", + "total": 248, + "sentences": [ + { + "text": "To facilitate formal analysis of RVWMO, this chapter presents a set of formalizations using different tools and modeling approaches.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1", + "line_range": [ + 3, + 6 + ] + }, + { + "text": "Any discrepancies are unintended; the expectation is that the models describe exactly the same sets of legal behaviors.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1", + "line_range": [ + 3, + 6 + ] + }, + { + "text": "This appendix should be treated as commentary; all normative material is provided in and in the rest of the main body of the ISA specification.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1", + "line_range": [ + 8, + 12 + ] + }, + { + "text": "All currently known discrepancies are listed in .", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1", + "line_range": [ + 8, + 12 + ] + }, + { + "text": "Any other discrepancies are unintentional.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1", + "line_range": [ + 8, + 12 + ] + }, + { + "text": "We present a formal specification of the RVWMO memory model in Alloy (http://alloy.mit.edu).", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy", + "line_range": [ + 17, + 19 + ] + }, + { + "text": "This model is available online at https://github.com/daniellustig/riscv-memory-model.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy", + "line_range": [ + 17, + 19 + ] + }, + { + "text": "The online material also contains some litmus tests and some examples of how Alloy can be used to model check some of the mappings in .", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy", + "line_range": [ + 21, + 22 + ] + }, + { + "text": ".The RVWMO memory model formalized in Alloy (1/5: PPO) [source,c] ---- // =RVWMO PPO=", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy", + "line_range": [ + 24, + 27 + ] + }, + { + "text": ".The RVWMO memory model formalized in Alloy (2/5: Axioms) [,io] .... // =RVWMO axioms=", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy", + "line_range": [ + 57, + 60 + ] + }, + { + "text": "fun latestamong[s: set Event] : Event { s - s.~^gmo }", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy", + "line_range": [ + 68, + 68 + ] + }, + { + "text": "pred LoadValue { all w: Store | all r: Load | w->r in rf <=> w = latestamong[candidates[r]] }", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy", + "line_range": [ + 70, + 73 + ] + }, + { + "text": "pred RISCVmm { LoadValue and Atomicity } ....", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy", + "line_range": [ + 86, + 87 + ] + }, + { + "text": ".The RVWMO memory model formalized in Alloy (3/5: model of memory) [source,sml] .... //Basic model of memory", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy", + "line_range": [ + 89, + 92 + ] + }, + { + "text": "sig Hart { // hardware thread start : one Event } sig Address {} abstract sig Event { po: lone Event // program order }", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy", + "line_range": [ + 94, + 100 + ] + }, + { + "text": "abstract sig MemoryEvent extends Event { address: one Address, acquireRCpc: lone MemoryEvent, acquireRCsc: lone MemoryEvent, releaseRCpc: lone MemoryEvent, releaseRCsc: lone MemoryEvent, addrdep: set MemoryEvent, ctrldep: set Event, datadep: set MemoryEvent, gmo: set MemoryEvent, // global memory order rf: set MemoryEvent } sig LoadNormal extends MemoryEvent {} // l{b|h|w|d} sig LoadReserve extends MemoryEvent { // lr pair: lone StoreConditional } sig StoreNormal extends MemoryEvent {} // s{b|h|w|d} // all StoreConditionals in the model are assumed to be successful sig StoreConditional extends MemoryEvent {} // sc sig AMO extends MemoryEvent {} // amo sig NOP extends Event {}", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy", + "line_range": [ + 102, + 122 + ] + }, + { + "text": "fun Load : Event { LoadNormal + LoadReserve + AMO } fun Store : Event { StoreNormal + StoreConditional + AMO }", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy", + "line_range": [ + 124, + 125 + ] + }, + { + "text": "sig Fence extends Event { pr: lone Fence, // opcode bit pw: lone Fence, // opcode bit sr: lone Fence, // opcode bit sw: lone Fence // opcode bit } sig FenceTSO extends Fence {}", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy", + "line_range": [ + 127, + 133 + ] + }, + { + "text": "fact { pr + pw + sr + sw in iden } // likewise for ordering annotations fact { acquireRCpc + acquireRCsc + releaseRCpc + releaseRCsc in iden } // don't try to encode FenceTSO via pr/pw/sr/sw; just use it as-is fact { no FenceTSO.(pr + pw + sr + sw) } ....", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy", + "line_range": [ + 135, + 143 + ] + }, + { + "text": ".The RVWMO memory model formalized in Alloy (4/5: Basic model rules) [source,scala] .... // =Basic model rules=", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy", + "line_range": [ + 145, + 148 + ] + }, + { + "text": "fun ppofence : MemoryEvent->MemoryEvent { (Load <: ^po :> FencePRSR).(^po :> Load) + (Load <: ^po :> FencePRSW).(^po :> Store) + (Store <: ^po :> FencePWSR).(^po :> Load) + (Store <: ^po :> FencePWSW).(^po :> Store) + (Load <: ^po :> FenceTSO) .(^po :> MemoryEvent) + (Store <: ^po :> FenceTSO) .(^po :> Store) }", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy", + "line_range": [ + 166, + 173 + ] + }, + { + "text": ".The RVWMO memory model formalized in Alloy (5/5: Auxiliaries) [source,asm] .... // po fact { acyclic[po] }", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy", + "line_range": [ + 190, + 194 + ] + }, + { + "text": "pred restricttocurrentencodings { no (LoadNormal + StoreNormal) & (Acquire + Release) }", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy", + "line_range": [ + 235, + 237 + ] + }, + { + "text": "The tool [.sans-serif]herd takes a memory model and a litmus test as input and simulates the execution of the test on top of the memory model.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > Formal Axiomatic Specification in Herd", + "line_range": [ + 251, + 259 + ] + }, + { + "text": "Memory models are written in the domain specific language Cat.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > Formal Axiomatic Specification in Herd", + "line_range": [ + 251, + 259 + ] + }, + { + "text": "This section provides two Cat memory model of RVWMO.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > Formal Axiomatic Specification in Herd", + "line_range": [ + 251, + 259 + ] + }, + { + "text": "The first model, , follows the global memory order, , definition of RVWMO, as much as is possible for a Cat model.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > Formal Axiomatic Specification in Herd", + "line_range": [ + 251, + 259 + ] + }, + { + "text": "The second model, , is an equivalent, more efficient, partial order based RVWMO model.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > Formal Axiomatic Specification in Herd", + "line_range": [ + 251, + 259 + ] + }, + { + "text": "The simulator `herd` is part of the `diy` tool suite — see http://diy.inria.fr for software and documentation.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > Formal Axiomatic Specification in Herd", + "line_range": [ + 261, + 270 + ] + }, + { + "text": "The models and more are available online at http://diy.inria.fr/cats7/riscv/. .riscv-defs.cat, a herd definition of preserved program order (1/3) [source,asm] .... (*************) (* Utilities *) (*************)", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > Formal Axiomatic Specification in Herd", + "line_range": [ + 261, + 270 + ] + }, + { + "text": "(* All fence relations *) let fence.r.r = [R];fencerel(Fence.r.r);[R] let fence.r.w = [R];fencerel(Fence.r.w);[W] let fence.r.rw = [R];fencerel(Fence.r.rw);[M] let fence.w.r = [W];fencerel(Fence.w.r);[R] let fence.w.w = [W];fencerel(Fence.w.w);[W] let fence.w.rw = [W];fencerel(Fence.w.rw);[M] let fence.rw.r = [M];fencerel(Fence.rw.r);[R] let fence.rw.w = [M];fencerel(Fence.rw.w);[W] let fence.rw.rw = [M];fencerel(Fence.rw.rw);[M] let fence.tso = let f = fencerel(Fence.tso) in ([W];f;[W]) | ([R];f;[M])", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > Formal Axiomatic Specification in Herd", + "line_range": [ + 272, + 284 + ] + }, + { + "text": "let fence = fence.r.r | fence.r.w | fence.r.rw | fence.w.r | fence.w.w | fence.w.rw | fence.rw.r | fence.rw.w | fence.rw.rw | fence.tso", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > Formal Axiomatic Specification in Herd", + "line_range": [ + 286, + 290 + ] + }, + { + "text": "(* Same address, no W to the same address in-between *) let po-loc-no-w = po-loc \\ (po-loc?;[W];po-loc) (* Read same write *) let rsw = rf^-1;rf (* Acquire, or stronger *) let AQ = Acq|AcqRel (* Release or stronger *) and RL = RelAcqRel (* All RCsc *) let RCsc = Acq|Rel|AcqRel (* Amo events are both R and W, relation rmw relates paired lr/sc *) let AMO = R & W let StCond = range(rmw)", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > Formal Axiomatic Specification in Herd", + "line_range": [ + 292, + 304 + ] + }, + { + "text": "(*************) (* ppo rules *) (*************)", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > Formal Axiomatic Specification in Herd", + "line_range": [ + 306, + 308 + ] + }, + { + "text": "(* Overlapping-Address Orderings *) let r1 = [M];po-loc;[W] and r2 = ([R];po-loc-no-w;[R]) \\ rsw and r3 = [AMO|StCond];rfi;[R] (* Explicit Synchronization *) and r4 = fence and r5 = [AQ];po;[M] and r6 = [M];po;[RL] and r7 = [RCsc];po;[RCsc] and r8 = rmw (* Syntactic Dependencies *) and r9 = [M];addr;[M] and r10 = [M];data;[W] and r11 = [M];ctrl;[W] (* Pipeline Dependencies *) and r12 = [R];(addr|data);[W];rfi;[R] and r13 = [R];addr;[M];po;[W]", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > Formal Axiomatic Specification in Herd", + "line_range": [ + 310, + 326 + ] + }, + { + "text": "let ppo = r1 | r2 | r3 | r4 | r5 | r6 | r7 | r8 | r9 | r10 | r11 | r12 | r13 .... .riscv.cat, a herd version of the RVWMO memory model (2/3) [source,asm] ....", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > Formal Axiomatic Specification in Herd", + "line_range": [ + 328, + 334 + ] + }, + { + "text": "(* Notice that herd has defined its own rf relation *)", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > Formal Axiomatic Specification in Herd", + "line_range": [ + 336, + 336 + ] + }, + { + "text": "(* Define ppo *) include \"riscv-defs.cat\"", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > Formal Axiomatic Specification in Herd", + "line_range": [ + 338, + 339 + ] + }, + { + "text": "(********************************) (* Generate global memory order *) (********************************)", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > Formal Axiomatic Specification in Herd", + "line_range": [ + 341, + 343 + ] + }, + { + "text": "let gmo0 = (* precursor: ie build gmo as an total order that include gmo0 *) loc & (W\\FW) * FW | Final write after any write to the same location ppo | ppo compatible rfe includes herd external rf (optimization)", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > Formal Axiomatic Specification in Herd", + "line_range": [ + 345, + 348 + ] + }, + { + "text": "(* Walk over all linear extensions of gmo0 *) with gmo from linearizations(M\\IW,gmo0)", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > Formal Axiomatic Specification in Herd", + "line_range": [ + 350, + 351 + ] + }, + { + "text": "(* Add initial writes upfront -- convenient for computing rfGMO *) let gmo = gmo | loc & IW * (M\\IW)", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > Formal Axiomatic Specification in Herd", + "line_range": [ + 353, + 354 + ] + }, + { + "text": "(**********) (* Axioms *) (**********)", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > Formal Axiomatic Specification in Herd", + "line_range": [ + 356, + 358 + ] + }, + { + "text": "(* Compute rf according to the load value axiom, aka rfGMO *) let WR = loc & ([W];(gmo|po);[R]) let rfGMO = WR \\ (loc&([W];gmo);WR)", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > Formal Axiomatic Specification in Herd", + "line_range": [ + 360, + 362 + ] + }, + { + "text": "(* Check equality of herd rf and of rfGMO *) empty (rf\\rfGMO)|(rfGMO\\rf) as RfCons", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > Formal Axiomatic Specification in Herd", + "line_range": [ + 364, + 365 + ] + }, + { + "text": "(* Atomicity axiom *) let infloc = (gmo & loc)^-1 let inflocext = infloc & ext let winside = (infloc;rmw;inflocext) & (infloc;rf;rmw;inflocext) & [W] empty winside as Atomic .... .`riscv.cat`, an alternative herd presentation of the RVWMO memory model (3/3) [source,asm] ....", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > Formal Axiomatic Specification in Herd", + "line_range": [ + 367, + 377 + ] + }, + { + "text": "(***************) (* Definitions *) (***************)", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > Formal Axiomatic Specification in Herd", + "line_range": [ + 379, + 381 + ] + }, + { + "text": "(* Define ppo *) include \"riscv-defs.cat\"", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > Formal Axiomatic Specification in Herd", + "line_range": [ + 383, + 384 + ] + }, + { + "text": "(* Compute coherence relation *) include \"cos-opt.cat\"", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > Formal Axiomatic Specification in Herd", + "line_range": [ + 386, + 387 + ] + }, + { + "text": "(**********) (* Axioms *) (**********)", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > Formal Axiomatic Specification in Herd", + "line_range": [ + 389, + 391 + ] + }, + { + "text": "(* Sc per location *) acyclic co|rf|fr|po-loc as Coherence", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > Formal Axiomatic Specification in Herd", + "line_range": [ + 393, + 394 + ] + }, + { + "text": "(* Main model axiom *) acyclic co|rfe|fr|ppo as Model", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > Formal Axiomatic Specification in Herd", + "line_range": [ + 396, + 397 + ] + }, + { + "text": "(* Atomicity axiom *) empty rmw & (fre;coe) as Atomic ....", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > Formal Axiomatic Specification in Herd", + "line_range": [ + 399, + 401 + ] + }, + { + "text": "This is an alternative presentation of the RVWMO memory model in operational style.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 406, + 409 + ] + }, + { + "text": "It aims to admit exactly the same extensional behavior as the axiomatic presentation: for any given program, admitting an execution if and only if the axiomatic presentation allows it.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 406, + 409 + ] + }, + { + "text": "The axiomatic presentation is defined as a predicate on complete candidate executions.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 411, + 422 + ] + }, + { + "text": "In contrast, this operational presentation has an abstract microarchitectural flavor: it is expressed as a state machine, with states that are an abstract representation of hardware machine states, and with explicit out-of-order and speculative execution (but abstracting from more implementation-specific microarchitectural details such as register renaming, store buffers, cache hierarchies, cache protocols, etc.).", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 411, + 422 + ] + }, + { + "text": "As such, it can provide useful intuition.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 411, + 422 + ] + }, + { + "text": "It can also construct executions incrementally, making it possible to interactively and randomly explore the behavior of larger examples, while the axiomatic model requires complete candidate executions over which the axioms can be checked.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 411, + 422 + ] + }, + { + "text": "The operational presentation covers mixed-size execution, with potentially overlapping memory accesses of different power-of-two byte sizes.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 424, + 426 + ] + }, + { + "text": "Misaligned accesses are broken up into single-byte accesses.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 424, + 426 + ] + }, + { + "text": "The operational model, together with a fragment of the RISC-V ISA semantics (RV64I and A), are integrated into the `rmem` exploration tool (https://github.com/rems-project/rmem). `rmem` can explore litmus tests (see ) and small ELF binaries exhaustively, pseudorandomly and interactively.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 428, + 437 + ] + }, + { + "text": "In `rmem`, the ISA semantics is expressed explicitly in Sail (see https://github.com/rems-project/sail for the Sail language, and https://github.com/rems-project/sail-riscv for the RISC-V ISA model), and the concurrency semantics is expressed in Lem (see https://github.com/rems-project/lem for the Lem language).", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 428, + 437 + ] + }, + { + "text": "`rmem` has a command-line interface and a web-interface.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 439, + 443 + ] + }, + { + "text": "The web-interface runs entirely on the client side, and is provided online together with a library of litmus tests: http://www.cl.cam.ac.uk/.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 439, + 443 + ] + }, + { + "text": "The command-line interface is faster than the web-interface, specially in exhaustive mode.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 439, + 443 + ] + }, + { + "text": "Below is an informal introduction of the model states and transitions.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 445, + 446 + ] + }, + { + "text": "The description of the formal model starts in the next subsection.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 445, + 446 + ] + }, + { + "text": "Terminology: In contrast to the axiomatic presentation, here every memory operation is either a load or a store.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 448, + 456 + ] + }, + { + "text": "Hence, AMOs give rise to two distinct memory operations, a load and a store.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 448, + 456 + ] + }, + { + "text": "When used in conjunction with `instruction`, the terms `load` and `store` refer to instructions that give rise to such memory operations.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 448, + 456 + ] + }, + { + "text": "As such, both include AMO instructions.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 448, + 456 + ] + }, + { + "text": "The term `acquire` refers to an instruction (or its memory operation) with the acquire-RCpc or acquire-RCsc annotation.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 448, + 456 + ] + }, + { + "text": "The term `release` refers to an instruction (or its memory operation) with the release-RCpc or release-RCsc annotation.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 448, + 456 + ] + }, + { + "text": "Model states: A model state consists of a shared memory and a tuple of hart states.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 460, + 460 + ] + }, + { + "text": "[\"ditaa\",shadows=false, separation=false, fontsize: 14,float=\"center\"] .... +----------+ +---------+ | Hart 0 | ... | Trace | +----------+ +---------+ ↑ ↓ ↑ ↓ +--------------------------+ | Shared memory | +--------------------------+ ....", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 462, + 471 + ] + }, + { + "text": "The shared memory state records all the memory store operations that have propagated so far, in the order they propagated (this can be made more efficient, but for simplicity of the presentation we keep it this way).", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 473, + 476 + ] + }, + { + "text": "Each hart state consists principally of a tree of instruction instances, some of which have been finished, and some of which have not.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 478, + 482 + ] + }, + { + "text": "Non-finished instruction instances can be subject to restart, e.g. if they depend on an out-of-order or speculative load that turns out to be unsound.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 478, + 482 + ] + }, + { + "text": "Conditional branch and indirect jump instructions may have multiple successors in the instruction tree.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 484, + 486 + ] + }, + { + "text": "When such instruction is finished, any untaken alternative paths are discarded.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 484, + 486 + ] + }, + { + "text": "Each instruction instance in the instruction tree has a state that includes an execution state of the intra-instruction semantics (the ISA pseudocode for this instruction).", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 488, + 496 + ] + }, + { + "text": "The model uses a formalization of the intra-instruction semantics in Sail.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 488, + 496 + ] + }, + { + "text": "One can think of the execution state of an instruction as a representation of the pseudocode control state, pseudocode call stack, and local variable values.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 488, + 496 + ] + }, + { + "text": "An instruction instance state also includes information about the instance's memory and register footprints, its register reads and writes, its memory operations, whether it is finished, etc.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 488, + 496 + ] + }, + { + "text": "The model defines, for any model state, the set of allowed transitions, each of which is a single atomic step to a new abstract machine state.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 500, + 510 + ] + }, + { + "text": "Execution of a single instruction will typically involve many transitions, and they may be interleaved in operational-model execution with transitions arising from other instructions.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 500, + 510 + ] + }, + { + "text": "Each transition arises from a single instruction instance; it will change the state of that instance, and it may depend on or change the rest of its hart state and the shared memory state, but it does not depend on other hart states, and it will not change them.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 500, + 510 + ] + }, + { + "text": "The transitions are introduced below and defined in , with a precondition and a construction of the post-transition model state for each.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 500, + 510 + ] + }, + { + "text": "Transitions for all instructions:", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 512, + 512 + ] + }, + { + "text": ": This transition represents a fetch and decode of a new instruction instance, as a program order successor of a previously fetched instruction instance (or the initial fetch address).", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 514, + 515 + ] + }, + { + "text": "The model assumes the instruction memory is fixed; it does not describe the behavior of self-modifying code.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 517, + 521 + ] + }, + { + "text": "In particular, the transition does not generate memory load operations, and the shared memory is not involved in the transition.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 517, + 521 + ] + }, + { + "text": "Instead, the model depends on an external oracle that provides an opcode when given a memory location.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 517, + 521 + ] + }, + { + "text": "[circle] * : This is a write of a register value.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 523, + 524 + ] + }, + { + "text": ": This is a read of a register value from the most recent program-order-predecessor instruction instance that writes to that register.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 526, + 528 + ] + }, + { + "text": ": This covers pseudocode internal computation: arithmetic, function calls, etc.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 530, + 531 + ] + }, + { + "text": ": At this point the instruction pseudocode is done, the instruction cannot be restarted, memory accesses cannot be discarded, and all memory effects have taken place.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 533, + 538 + ] + }, + { + "text": "For conditional branch and indirect jump instructions, any program order successors that were fetched from an address that is not the one that was written to the pc register are discarded, together with the sub-tree of instruction instances below them.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 533, + 538 + ] + }, + { + "text": "Transitions specific to load instructions:", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 540, + 540 + ] + }, + { + "text": "[circle] * : At this point the memory footprint of the load instruction is provisionally known (it could change if earlier instructions are restarted) and its individual memory load operations can start being satisfied.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 542, + 546 + ] + }, + { + "text": "[disc] * : This partially or entirely satisfies a single memory load operation by forwarding, from program-order-previous memory store operations.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 548, + 549 + ] + }, + { + "text": ": This entirely satisfies the outstanding slices of a single memory load operation, from memory.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 551, + 552 + ] + }, + { + "text": "[circle] * : At this point all the memory load operations of the instruction have been entirely satisfied and the instruction pseudocode can continue executing. A load instruction can be subject to being restarted until the transition.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 554, + 559 + ] + }, + { + "text": "But, under some conditions, the model might treat a load instruction as non-restartable even before it is finished (e.g. see ).", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 554, + 559 + ] + }, + { + "text": "Transitions specific to store instructions:", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 561, + 561 + ] + }, + { + "text": "[circle] * : At this point the memory footprint of the store is provisionally known.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 563, + 565 + ] + }, + { + "text": ": At this point the memory store operations have their values and program-order-successor memory load operations can be satisfied by forwarding from them.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 567, + 569 + ] + }, + { + "text": ": At this point the store operations are guaranteed to happen (the instruction can no longer be restarted or discarded), and they can start being propagated to memory.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 571, + 573 + ] + }, + { + "text": "[disc] * : This propagates a single memory store operation to memory.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 575, + 576 + ] + }, + { + "text": "[circle] * : At this point all the memory store operations of the instruction have been propagated to memory, and the instruction pseudocode can continue executing.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 578, + 581 + ] + }, + { + "text": "Transitions specific to `sc` instructions:", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 583, + 583 + ] + }, + { + "text": "[disc] * : This causes the `sc` to fail, either a spontaneous fail or because it is not paired with a program-order-previous `lr`.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 585, + 586 + ] + }, + { + "text": ": This transition indicates the `sc` is paired with an `lr` and might succeed.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 588, + 589 + ] + }, + { + "text": ": This is an atomic execution of the transitions and , it is enabled only if the stores from which the `lr` read from have not been overwritten.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 591, + 593 + ] + }, + { + "text": ": This causes the `sc` to fail, either a spontaneous fail or because the stores from which the `lr` read from have been overwritten.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 595, + 596 + ] + }, + { + "text": "Transitions specific to AMO instructions:", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 598, + 598 + ] + }, + { + "text": "[disc] * : This is an atomic execution of all the transitions needed to satisfy the load operation, do the required arithmetic, and propagate the store operation.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 600, + 603 + ] + }, + { + "text": "Transitions specific to fence instructions:", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 605, + 605 + ] + }, + { + "text": "The transitions labeled {circ} can always be taken eagerly, as soon as their precondition is satisfied, without excluding other behavior; the {bullet} cannot.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 610, + 614 + ] + }, + { + "text": "Although is marked with a {bullet}, it can be taken eagerly as long as it is not taken infinitely many times.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 610, + 614 + ] + }, + { + "text": "An instance of a non-AMO load instruction, after being fetched, will typically experience the following transitions in this order:", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 616, + 617 + ] + }, + { + "text": ". . . and/or (as many as needed to satisfy all the load operations of the instance) . . .", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 619, + 625 + ] + }, + { + "text": "Before, between, and after the transitions above, any number of transitions may appear.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 627, + 630 + ] + }, + { + "text": "In addition, a transition for fetching the instruction in the next program location will be available until it is taken.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 627, + 630 + ] + }, + { + "text": "This concludes the informal description of the operational model.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 632, + 633 + ] + }, + { + "text": "The following sections describe the formal operational model.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model", + "line_range": [ + 632, + 633 + ] + }, + { + "text": "The intra-instruction semantics for each instruction instance is expressed as a state machine, essentially running the instruction pseudocode.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Intra-instruction Pseudocode Execution", + "line_range": [ + 639, + 644 + ] + }, + { + "text": "Given a pseudocode execution state, it computes the next state.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Intra-instruction Pseudocode Execution", + "line_range": [ + 639, + 644 + ] + }, + { + "text": "Most states identify a pending memory or register operation, requested by the pseudocode, which the memory model has to do.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Intra-instruction Pseudocode Execution", + "line_range": [ + 639, + 644 + ] + }, + { + "text": "The states are (this is a tagged union; tags in small-caps):", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Intra-instruction Pseudocode Execution", + "line_range": [ + 639, + 644 + ] + }, + { + "text": "[cols=\"<,<\",grid=\"none\"] | |Loadmem(kind, address, size, loadcontinuation) |- memory load operation", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Intra-instruction Pseudocode Execution", + "line_range": [ + 646, + 649 + ] + }, + { + "text": "|Earlyscfail(rescontinuation) |- allow `sc` to fail early", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Intra-instruction Pseudocode Execution", + "line_range": [ + 651, + 651 + ] + }, + { + "text": "|Storeea(kind, address, size, nextstate) |- memory store effective address", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Intra-instruction Pseudocode Execution", + "line_range": [ + 653, + 654 + ] + }, + { + "text": "|Storememv(memvalue, storecontinuation) |- memory store value", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Intra-instruction Pseudocode Execution", + "line_range": [ + 656, + 656 + ] + }, + { + "text": "|Fence(kind, nextstate) |- fence", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Intra-instruction Pseudocode Execution", + "line_range": [ + 658, + 658 + ] + }, + { + "text": "|Readreg(regname, readcontinuation) |- register read", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Intra-instruction Pseudocode Execution", + "line_range": [ + 660, + 660 + ] + }, + { + "text": "|Writereg(regname, regvalue, nextstate) |- register write", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Intra-instruction Pseudocode Execution", + "line_range": [ + 662, + 662 + ] + }, + { + "text": "|Internal(nextstate) |- pseudocode internal step", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Intra-instruction Pseudocode Execution", + "line_range": [ + 664, + 664 + ] + }, + { + "text": "|Done |- end of pseudocode |", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Intra-instruction Pseudocode Execution", + "line_range": [ + 666, + 667 + ] + }, + { + "text": "memvalue and regvalue are lists of bytes; * address is an integer of XLEN bits;", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Intra-instruction Pseudocode Execution", + "line_range": [ + 671, + 672 + ] + }, + { + "text": "for load/store, kind identifies whether it is `lr/sc`, acquire-RCpc/release-RCpc, acquire-RCsc/release-RCsc, acquire-release-RCsc; * for fence, kind identifies whether it is a normal or TSO, and (for normal fences) the predecessor and successor ordering bits; * regname identifies a register and a slice thereof (start and end bit indices); and the continuations describe how the instruction instance will continue for each value that might be provided by the surrounding memory model (the loadcontinuation and readcontinuation take the value loaded from memory and read from the previous register write, the storecontinuation takes false for an `sc` that failed and true in all other cases, and rescontinuation takes false if the `sc` fails and true otherwise).", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Intra-instruction Pseudocode Execution", + "line_range": [ + 674, + 695 + ] + }, + { + "text": "Notice that writing to memory is split into two steps, Storeea and Storememv: the first one makes the memory footprint of the store provisionally known, and the second one adds the value to be stored.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Intra-instruction Pseudocode Execution", + "line_range": [ + 674, + 695 + ] + }, + { + "text": "We ensure these are paired in the pseudocode (Storeea followed by Storememv), but there may be other steps between them.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Intra-instruction Pseudocode Execution", + "line_range": [ + 674, + 695 + ] + }, + { + "text": "The pseudocode of each instruction performs at most one store or one load, except for AMOs that perform exactly one load and one store.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Intra-instruction Pseudocode Execution", + "line_range": [ + 674, + 695 + ] + }, + { + "text": "Those memory accesses are then split apart into the architecturally atomic units by the hart semantics (see and below).", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Intra-instruction Pseudocode Execution", + "line_range": [ + 674, + 695 + ] + }, + { + "text": "Informally, each bit of a register read should be satisfied from a register write by the most recent (in program order) instruction instance that can write that bit (or from the hart’s initial register state if there is no such write).", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Intra-instruction Pseudocode Execution", + "line_range": [ + 697, + 705 + ] + }, + { + "text": "Hence, it is essential to know the register write footprint of each instruction instance, which we calculate when the instruction instance is created (see the action of below).", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Intra-instruction Pseudocode Execution", + "line_range": [ + 697, + 705 + ] + }, + { + "text": "We ensure in the pseudocode that each instruction does at most one register write to each register bit, and also that it does not try to read a register value it just wrote.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Intra-instruction Pseudocode Execution", + "line_range": [ + 697, + 705 + ] + }, + { + "text": "Data-flow dependencies (address and data) in the model emerge from the fact that each register read has to wait for the appropriate register write to be executed (as described above).", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Intra-instruction Pseudocode Execution", + "line_range": [ + 707, + 709 + ] + }, + { + "text": "Each instruction instance i has a state comprising:", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Instruction Instance State", + "line_range": [ + 714, + 714 + ] + }, + { + "text": "programloc, the memory address from which the instruction was fetched; * instructionkind, identifying whether this is a load, store, AMO, fence, branch/jump or a `simple` instruction (this also includes a kind similar to the one described for the pseudocode execution states); * srcregs, the set of source regnames (including system registers), as statically determined from the pseudocode of the instruction; * dstregs, the destination regnames (including system registers), as statically determined from the pseudocode of the instruction; * pseudocodestate (or sometimes just `state` for short), one of (this is a tagged union; tags in small-caps): +", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Instruction Instance State", + "line_range": [ + 716, + 728 + ] + }, + { + "text": "[cols=\"<,<\",grid=\"none\"] | |Plain(isastate) |- ready to make a pseudocode transition", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Instruction Instance State", + "line_range": [ + 730, + 732 + ] + }, + { + "text": "|Pendingmemloads(loadcontinuation) |- requesting memory load operation(s)", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Instruction Instance State", + "line_range": [ + 734, + 735 + ] + }, + { + "text": "|Pendingmemstores(storecontinuation) |- requesting memory store operation(s) | * regreads, the register reads the instance has performed, including, for each one, the register write slices it read from; * regwrites, the register writes the instance has performed; * memloads, a set of memory load operations, and for each one the as-yet-unsatisfied slices (the byte indices that have not been satisfied yet), and, for the satisfied slices, the store slices (each consisting of a memory store operation and subset of its byte indices) that satisfied it. * memstores, a set of memory store operations, and for each one a flag that indicates whether it has been propagated (passed to the shared memory) or not. * information recording whether the instance is committed, finished, etc.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Instruction Instance State", + "line_range": [ + 737, + 752 + ] + }, + { + "text": "Each memory load operation includes a memory footprint (address and size).", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Instruction Instance State", + "line_range": [ + 754, + 756 + ] + }, + { + "text": "Each memory store operations includes a memory footprint, and, when available, a value.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Instruction Instance State", + "line_range": [ + 754, + 756 + ] + }, + { + "text": "A load instruction instance with a non-empty memloads, for which all the load operations are satisfied (i.e. there are no unsatisfied load slices) is said to be entirely satisfied.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Instruction Instance State", + "line_range": [ + 758, + 760 + ] + }, + { + "text": "Informally, an instruction instance is said to have fully determined data if the load (and `sc`) instructions feeding its source registers are finished.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Instruction Instance State", + "line_range": [ + 762, + 770 + ] + }, + { + "text": "Similarly, it is said to have a fully determined memory footprint if the load (and `sc`) instructions feeding its memory operation address register are finished.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Instruction Instance State", + "line_range": [ + 762, + 770 + ] + }, + { + "text": "Formally, we first define the notion of fully determined register write: a register write w from regwrites of instruction instance i is said to be fully determined if one of the following conditions hold:", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Instruction Instance State", + "line_range": [ + 762, + 770 + ] + }, + { + "text": ". i is finished; or . the value written by w is not affected by a memory operation that i has made (i.e. a value loaded from memory or the result of `sc`), and, for every register read that i has made, that affects w, the register write from which i read is fully determined (or i read from the initial register state).", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Instruction Instance State", + "line_range": [ + 772, + 778 + ] + }, + { + "text": "Now, an instruction instance i is said to have fully determined data if for every register read r from regreads, the register writes that r reads from are fully determined.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Instruction Instance State", + "line_range": [ + 780, + 787 + ] + }, + { + "text": "An instruction instance i is said to have a fully determined memory footprint if for every register read r from regreads that feeds into i’s memory operation address, the register writes that r reads from are fully determined.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Instruction Instance State", + "line_range": [ + 780, + 787 + ] + }, + { + "text": "The model state of a single hart comprises:", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Hart State", + "line_range": [ + 791, + 791 + ] + }, + { + "text": "hartid, a unique identifier of the hart; * initialregisterstate, the initial register value for each register; * initialfetchaddress, the initial instruction fetch address; * instructiontree, a tree of the instruction instances that have been fetched (and not discarded), in program order.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Hart State", + "line_range": [ + 793, + 798 + ] + }, + { + "text": "The model state of the shared memory comprises a list of memory store operations, in the order they propagated to the shared memory.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Shared Memory State", + "line_range": [ + 802, + 803 + ] + }, + { + "text": "When a store operation is propagated to the shared memory it is simply added to the end of the list.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Shared Memory State", + "line_range": [ + 805, + 809 + ] + }, + { + "text": "When a load operation is satisfied from memory, for each byte of the load operation, the most recent corresponding store slice is returned.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Shared Memory State", + "line_range": [ + 805, + 809 + ] + }, + { + "text": "Each of the paragraphs below describes a single kind of system transition.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions", + "line_range": [ + 812, + 817 + ] + }, + { + "text": "The description starts with a condition over the current system state.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions", + "line_range": [ + 812, + 817 + ] + }, + { + "text": "The transition can be taken in the current state only if the condition is satisfied.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions", + "line_range": [ + 812, + 817 + ] + }, + { + "text": "The condition is followed by an action that is applied to that state when the transition is taken, in order to generate the new system state.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions", + "line_range": [ + 812, + 817 + ] + }, + { + "text": "A possible program-order-successor of instruction instance i can be fetched from address loc if:", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Fetch instruction", + "line_range": [ + 822, + 823 + ] + }, + { + "text": ". it has not already been fetched, i.e., none of the immediate successors of i in the hart’s instructiontree are from loc; and . if i’s pseudocode has already written an address to pc, then loc must be that address, otherwise loc is: * for a conditional branch, the successor address or the branch target address; * for a (direct) jump and link instruction (`jal`), the target address; * for an indirect jump instruction (`jalr`), any address; and * for any other instruction, i.programloc+4.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Fetch instruction", + "line_range": [ + 825, + 834 + ] + }, + { + "text": "Action: construct a freshly initialized instruction instance i' for the instruction in the program memory at loc, with state Plain(isastate), computed from the instruction pseudocode, including the static information available from the pseudocode such as its instructionkind, srcregs, and dstregs, and add i' to the hart’s instructiontree as a successor of i.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Fetch instruction", + "line_range": [ + 836, + 842 + ] + }, + { + "text": "The possible next fetch addresses (loc) are available immediately after fetching i and the model does not need to wait for the pseudocode to write to pc; this allows out-of-order execution, and speculation past conditional branches and jumps.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Fetch instruction", + "line_range": [ + 844, + 862 + ] + }, + { + "text": "For most instructions these addresses are easily obtained from the instruction pseudocode.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Fetch instruction", + "line_range": [ + 844, + 862 + ] + }, + { + "text": "The only exception to that is the indirect jump instruction (`jalr`), where the address depends on the value held in a register.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Fetch instruction", + "line_range": [ + 844, + 862 + ] + }, + { + "text": "In principle the mathematical model should allow speculation to arbitrary addresses here.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Fetch instruction", + "line_range": [ + 844, + 862 + ] + }, + { + "text": "The exhaustive search in the `rmem` tool handles this by running the exhaustive search multiple times with a growing set of possible next fetch addresses for each indirect jump.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Fetch instruction", + "line_range": [ + 844, + 862 + ] + }, + { + "text": "The initial search uses empty sets, hence there is no fetch after indirect jump instruction until the pseudocode of the instruction writes to pc, and then we use that value for fetching the next instruction.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Fetch instruction", + "line_range": [ + 844, + 862 + ] + }, + { + "text": "Before starting the next iteration of exhaustive search, we collect for each indirect jump (grouped by code location) the set of values it wrote to pc in all the executions in the previous search iteration, and use that as possible next fetch addresses of the instruction.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Fetch instruction", + "line_range": [ + 844, + 862 + ] + }, + { + "text": "This process terminates when no new fetch addresses are detected.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Fetch instruction", + "line_range": [ + 844, + 862 + ] + }, + { + "text": "An instruction instance i in state Plain(Loadmem(kind, address, size, loadcontinuation)) can always initiate the corresponding memory load operations.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Initiate memory load operations", + "line_range": [ + 867, + 869 + ] + }, + { + "text": "Construct the appropriate memory load operations mlos: * if address is aligned to size then mlos is a single memory load operation of size bytes from address; * otherwise, mlos is a set of size memory load operations, each of one byte, from the addresses address...address+size−1. . set memloads of i to mlos; and . update the state of i to Pendingmemloads(loadcontinuation).", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Initiate memory load operations", + "line_range": [ + 871, + 880 + ] + }, + { + "text": "For a non-AMO load instruction instance i in state Pendingmemloads(loadcontinuation), and a memory load operation mlo in i.memloads that has unsatisfied slices, the memory load operation can be partially or entirely satisfied by forwarding from unpropagated memory store operations by store instruction instances that are program-order-before i if:", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Satisfy memory load operation by forwarding from unpropagated stores", + "line_range": [ + 883, + 889 + ] + }, + { + "text": ". all program-order-previous `fence` instructions with `.sr` and `.pw` set are finished; . for every program-order-previous `fence` instruction, f, with `.sr` and `.pr` set, and `.pw` not set, if f is not finished then all load instructions that are program-order-before f are entirely satisfied; . for every program-order-previous `fence.tso` instruction, f, that is not finished, all load instructions that are program-order-before f are entirely satisfied; . if i is a load-acquire-RCsc, all program-order-previous store-releases-RCsc are finished; . if i is a load-acquire-release, all program-order-previous instructions are finished; . all non-finished program-order-previous load-acquire instructions are entirely satisfied; and . all program-order-previous store-acquire-release instructions are finished;", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Satisfy memory load operation by forwarding from unpropagated stores", + "line_range": [ + 891, + 907 + ] + }, + { + "text": "Let msoss be the set of all unpropagated memory store operation slices from non-`sc` store instruction instances that are program-order-before i and have already calculated the value to be stored, that overlap with the unsatisfied slices of mlo, and which are not superseded by intervening store operations or store operations that are read from by an intervening load.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Satisfy memory load operation by forwarding from unpropagated stores", + "line_range": [ + 909, + 917 + ] + }, + { + "text": "The last condition requires, for each memory store operation slice msos in msoss from instruction i':", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Satisfy memory load operation by forwarding from unpropagated stores", + "line_range": [ + 909, + 917 + ] + }, + { + "text": "that there is no store instruction program-order-between i and i' with a memory store operation overlapping msos; and * that there is no load instruction program-order-between i and i' that was satisfied from an overlapping memory store operation slice from a different hart.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Satisfy memory load operation by forwarding from unpropagated stores", + "line_range": [ + 919, + 924 + ] + }, + { + "text": ". update i.memloads to indicate that mlo was satisfied by msoss; and . restart any speculative instructions which have violated coherence as a result of this, i.e., for every non-finished instruction i' that is a program-order-successor of i, and every memory load operation mlo' of i' that was satisfied from msoss', if there exists a memory store operation slice msos' in msoss', and an overlapping memory store operation slice from a different memory store operation in msoss, and msos' is not from an instruction that is a program-order-successor of i, restart i' and its restart-dependents.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Satisfy memory load operation by forwarding from unpropagated stores", + "line_range": [ + 928, + 939 + ] + }, + { + "text": "Where, the restart-dependents of instruction j are:", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Satisfy memory load operation by forwarding from unpropagated stores", + "line_range": [ + 941, + 941 + ] + }, + { + "text": "program-order-successors of j that have data-flow dependency on a register write of j; * program-order-successors of j that have a memory load operation that reads from a memory store operation of j (by forwarding); * if j is a load-acquire, all the program-order-successors of j; * if j is a load, for every `fence`, f, with `.sr` and `.pr` set, and `.pw` not set, that is a program-order-successor of j, all the load instructions that are program-order-successors of f; * if j is a load, for every `fence.tso`, f, that is a program-order-successor of j, all the load instructions that are program-order-successors of f; and * (recursively) all the restart-dependents of all the instruction instances above.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Satisfy memory load operation by forwarding from unpropagated stores", + "line_range": [ + 943, + 959 + ] + }, + { + "text": "For an instruction instance i of a non-AMO load instruction or an AMO instruction in the context of the transition, any memory load operation mlo in i.memloads that has unsatisfied slices, can be satisfied from memory if all the conditions of > are satisfied.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Satisfy memory load operation from memory", + "line_range": [ + 962, + 970 + ] + }, + { + "text": "Action: let msoss be the memory store operation slices from memory covering the unsatisfied slices of mlo, and apply the action of .", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Satisfy memory load operation from memory", + "line_range": [ + 962, + 970 + ] + }, + { + "text": "A load instruction instance i in state Pendingmemloads(loadcontinuation) can be completed (not to be confused with finished) if all the memory load operations i.memloads are entirely satisfied (i.e. there are no unsatisfied slices).", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Complete load operations", + "line_range": [ + 973, + 980 + ] + }, + { + "text": "Action: update the state of i to Plain(loadcontinuation(memvalue)), where memvalue is assembled from all the memory store operation slices that satisfied i.memloads.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Complete load operations", + "line_range": [ + 973, + 980 + ] + }, + { + "text": "An `sc` instruction instance i in state Plain(Earlyscfail(rescontinuation)) can always be made to fail.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Early `sc` fail", + "line_range": [ + 985, + 988 + ] + }, + { + "text": "Action: update the state of i to Plain(rescontinuation(false)).", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Early `sc` fail", + "line_range": [ + 985, + 988 + ] + }, + { + "text": "An `sc` instruction instance i in state Plain(Earlyscfail(rescontinuation)) can continue its (potentially successful) execution if i is paired with an `lr`.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Paired `sc`", + "line_range": [ + 993, + 996 + ] + }, + { + "text": "Action: update the state of i to Plain(rescontinuation(true)).", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Paired `sc`", + "line_range": [ + 993, + 996 + ] + }, + { + "text": "An instruction instance i in state Plain(Storeea(kind, address, size, nextstate)) can always announce its pending memory store operation footprint.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Initiate memory store operation footprints", + "line_range": [ + 1001, + 1003 + ] + }, + { + "text": ". construct the appropriate memory store operations msos (without the store value): * if address is aligned to size then msos is a single memory store operation of size bytes to address; * otherwise, msos is a set of size memory store operations, each of one-byte size, to the addresses address...address+size−1. . set i.memstores to msos; and . update the state of i to Plain(nextstate).", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Initiate memory store operation footprints", + "line_range": [ + 1005, + 1014 + ] + }, + { + "text": "An instruction instance i in state Plain(Storememv(memvalue, storecontinuation)) can always instantiate the values of the memory store operations i.memstores.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Instantiate memory store operation values", + "line_range": [ + 1017, + 1020 + ] + }, + { + "text": ". split memvalue between the memory store operations i.memstores; and . update the state of i to Pendingmemstores(storecontinuation).", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Instantiate memory store operation values", + "line_range": [ + 1022, + 1025 + ] + }, + { + "text": "An uncommitted instruction instance i of a non-`sc` store instruction or an `sc` instruction in the context of the transition, in state Pendingmemstores(storecontinuation), can be committed (not to be confused with propagated) if:", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Commit store instruction", + "line_range": [ + 1030, + 1033 + ] + }, + { + "text": ". i has fully determined data; . all program-order-previous conditional branch and indirect jump instructions are finished; . all program-order-previous `fence` instructions with `.sw` set are finished; . all program-order-previous `fence.tso` instructions are finished; . all program-order-previous load-acquire instructions are finished; . all program-order-previous store-acquire-release instructions are finished; . if i is a store-release, all program-order-previous instructions are finished; . all program-order-previous memory access instructions have a fully determined memory footprint; . all program-order-previous store instructions, except for `sc` that failed, have initiated and so have non-empty memstores; and . all program-order-previous load instructions have initiated and so have non-empty memloads.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Commit store instruction", + "line_range": [ + 1035, + 1051 + ] + }, + { + "text": "Action: record that i is committed.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Commit store instruction", + "line_range": [ + 1053, + 1054 + ] + }, + { + "text": "For a committed instruction instance i in state Pendingmemstores(storecontinuation), and an unpropagated memory store operation mso in i.memstores, mso can be propagated if:", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Propagate store operation", + "line_range": [ + 1057, + 1061 + ] + }, + { + "text": ". all memory store operations of program-order-previous store instructions that overlap with mso have already propagated; . all memory load operations of program-order-previous load instructions that overlap with mso have already been satisfied, and (the load instructions) are non-restartable (see definition below); and . all memory load operations that were satisfied by forwarding mso are entirely satisfied.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Propagate store operation", + "line_range": [ + 1063, + 1071 + ] + }, + { + "text": "Where a non-finished instruction instance j is non-restartable if:", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Propagate store operation", + "line_range": [ + 1073, + 1074 + ] + }, + { + "text": ". there does not exist a store instruction s and an unpropagated memory store operation mso of s such that applying the action of the transition to mso will result in the restart of j; and . there does not exist a non-finished load instruction l and a memory load operation mlo of l such that applying the action of the / transition (even if mlo is already satisfied) to mlo will result in the restart of j.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Propagate store operation", + "line_range": [ + 1076, + 1084 + ] + }, + { + "text": ". update the shared memory state with mso; . update i.memstores to indicate that mso was propagated; and . restart any speculative instructions which have violated coherence as a result of this, i.e., for every non-finished instruction i' program-order-after i and every memory load operation mlo' of i' that was satisfied from msoss', if there exists a memory store operation slice msos' in msoss' that overlaps with mso and is not from mso, and msos' is not from a program-order-successor of i, restart i' and its restart-dependents (see ).", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Propagate store operation", + "line_range": [ + 1088, + 1100 + ] + }, + { + "text": "An uncommitted `sc` instruction instance i, from hart h, in state Pendingmemstores(storecontinuation), with a paired `lr` i' that has been satisfied by some store slices msoss, can be committed and propagated at the same time if:", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Commit and propagate store operation of an `sc`", + "line_range": [ + 1105, + 1109 + ] + }, + { + "text": ". i' is finished; . every memory store operation that has been forwarded to i' is propagated; . the conditions of is satisfied; . the conditions of is satisfied (notice that an `sc` instruction can only have one memory store operation); and . for every store slice msos from msoss, msos has not been overwritten, in the shared memory, by a store that is from a hart that is not h, at any point since msos was propagated to memory.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Commit and propagate store operation of an `sc`", + "line_range": [ + 1111, + 1120 + ] + }, + { + "text": ". apply the actions of ; and . apply the action of .", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Commit and propagate store operation of an `sc`", + "line_range": [ + 1124, + 1125 + ] + }, + { + "text": "An `sc` instruction instance i in state Pendingmemstores(storecontinuation), that has not propagated its memory store operation, can always be made to fail.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Late `sc` fail", + "line_range": [ + 1130, + 1132 + ] + }, + { + "text": ". clear i.memstores; and . update the state of i to Plain(storecontinuation(false)).", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Late `sc` fail", + "line_range": [ + 1134, + 1137 + ] + }, + { + "text": "A store instruction instance i in state Pendingmemstores(storecontinuation), for which all the memory store operations in i.memstores have been propagated, can always be completed (not to be confused with finished).", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Complete store operations", + "line_range": [ + 1140, + 1145 + ] + }, + { + "text": "Action: update the state of i to Plain(storecontinuation(true)).", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Complete store operations", + "line_range": [ + 1140, + 1145 + ] + }, + { + "text": "An AMO instruction instance i in state Pendingmemloads(loadcontinuation) can perform its memory access if it is possible to perform the following sequence of transitions with no intervening transitions:", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Satisfy, commit and propagate operations of an AMO", + "line_range": [ + 1150, + 1153 + ] + }, + { + "text": ". . . (zero or more times) . . . .", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Satisfy, commit and propagate operations of an AMO", + "line_range": [ + 1155, + 1161 + ] + }, + { + "text": "and in addition, the condition of , with the exception of not requiring i to be in state Plain(Done), holds after those transitions.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Satisfy, commit and propagate operations of an AMO", + "line_range": [ + 1163, + 1168 + ] + }, + { + "text": "Action: perform the above sequence of transitions (this does not include ), one after the other, with no intervening transitions.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Satisfy, commit and propagate operations of an AMO", + "line_range": [ + 1163, + 1168 + ] + }, + { + "text": "A fence instruction instance i in state Plain(Fence(kind, nextstate)) can be committed if:", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Commit fence", + "line_range": [ + 1171, + 1172 + ] + }, + { + "text": ". if i is a normal fence and it has `.pr` set, all program-order-previous load instructions are finished; . if i is a normal fence and it has `.pw` set, all program-order-previous store instructions are finished; and . if i is a `fence.tso`, all program-order-previous load and store instructions are finished.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Commit fence", + "line_range": [ + 1174, + 1179 + ] + }, + { + "text": ". record that i is committed; and . update the state of i to Plain(nextstate).", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Commit fence", + "line_range": [ + 1183, + 1184 + ] + }, + { + "text": "An instruction instance i in state Plain(Readreg(regname, readcont)) can do a register read of regname if every instruction instance that it needs to read from has already performed the expected regname register write.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Register read", + "line_range": [ + 1189, + 1192 + ] + }, + { + "text": "Let readsources include, for each bit of regname, the write to that bit by the most recent (in program order) instruction instance that can write to that bit, if any.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Register read", + "line_range": [ + 1194, + 1198 + ] + }, + { + "text": "If there is no such instruction, the source is the initial register value from initialregisterstate.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Register read", + "line_range": [ + 1194, + 1198 + ] + }, + { + "text": "Let regvalue be the value assembled from readsources.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Register read", + "line_range": [ + 1194, + 1198 + ] + }, + { + "text": ". add regname to i.regreads with readsources and regvalue; and . update the state of i to Plain(readcont(regvalue)).", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Register read", + "line_range": [ + 1200, + 1202 + ] + }, + { + "text": "An instruction instance i in state Plain(Writereg(regname, regvalue, nextstate)) can always do a regname register write.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Register write", + "line_range": [ + 1207, + 1209 + ] + }, + { + "text": ". add regname to i.regwrites with deps and regvalue; and . update the state of i to Plain(nextstate).", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Register write", + "line_range": [ + 1211, + 1213 + ] + }, + { + "text": "where deps is a pair of the set of all readsources from i.regreads, and a flag that is true iff i is a load instruction instance that has already been entirely satisfied.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Register write", + "line_range": [ + 1215, + 1218 + ] + }, + { + "text": "An instruction instance i in state Plain(Internal(nextstate)) can always do that pseudocode-internal step.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Pseudocode internal step", + "line_range": [ + 1223, + 1226 + ] + }, + { + "text": "Action: update the state of i to Plain(nextstate).", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Pseudocode internal step", + "line_range": [ + 1223, + 1226 + ] + }, + { + "text": "A non-finished instruction instance i in state Plain(Done) can be finished if:", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Finish instruction", + "line_range": [ + 1231, + 1232 + ] + }, + { + "text": ". if i is a load instruction: .. all program-order-previous load-acquire instructions are finished; .. all program-order-previous `fence` instructions with `.sr` set are finished; .. for every program-order-previous `fence.tso` instruction, f, that is not finished, all load instructions that are program-order-before f are finished; and .. it is guaranteed that the values read by the memory load operations of i will not cause coherence violations, i.e., for any program-order-previous instruction instance i', let cfp be the combined footprint of propagated memory store operations from store instructions program-order-between i and i', and fixed memory store operations that were forwarded to i from store instructions program-order-between i and i' including i', and let /cfp be the complement of cfp in the memory footprint of i.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Finish instruction", + "line_range": [ + 1234, + 1267 + ] + }, + { + "text": "If /cfp is not empty: ... i' has a fully determined memory footprint; ... i' has no unpropagated memory store operations that overlap with /cfp; and ... if i' is a load with a memory footprint that overlaps with /cfp, then all the memory load operations of i' that overlap with /cfp are satisfied and i' is non-restartable (see the transition for how to determined if an instruction is non-restartable). + Here, a memory store operation is called fixed if the store instruction has fully determined data. . i has a fully determined data; and . if i is not a fence, all program-order-previous conditional branch and indirect jump instructions are finished.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Finish instruction", + "line_range": [ + 1234, + 1267 + ] + }, + { + "text": ". if i is a conditional branch or indirect jump instruction, discard any untaken paths of execution, i.e., remove all instruction instances that are not reachable by the branch/jump taken in instructiontree; and . record the instruction as finished, i.e., set finished to true.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Transitions > Finish instruction", + "line_range": [ + 1271, + 1275 + ] + }, + { + "text": "The model covers user-level RV64I and RV64A.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Limitations", + "line_range": [ + 1280, + 1293 + ] + }, + { + "text": "In particular, it does not support the misaligned atomicity granule PMA or the total store ordering extension \"Ztso\".", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Limitations", + "line_range": [ + 1280, + 1293 + ] + }, + { + "text": "It should be trivial to adapt the model to RV32I/A and to the G, Q and C extensions, but we have never tried it.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Limitations", + "line_range": [ + 1280, + 1293 + ] + }, + { + "text": "This will involve, mostly, writing Sail code for the instructions, with minimal, if any, changes to the concurrency model. * The model covers only normal memory accesses (it does not handle I/O accesses). * The model does not cover TLB-related effects. * The model assumes the instruction memory is fixed.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Limitations", + "line_range": [ + 1280, + 1293 + ] + }, + { + "text": "In particular, the transition does not generate memory load operations, and the shared memory is not involved in the transition.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Limitations", + "line_range": [ + 1280, + 1293 + ] + }, + { + "text": "Instead, the model depends on an external oracle that provides an opcode when given a memory location. * The model does not cover exceptions, traps and interrupts.", + "section": "Preamble > Formal Memory Model Specifications, Version 0.1 > Formal Axiomatic Specification in Alloy > An Operational Memory Model > Limitations", + "line_range": [ + 1280, + 1293 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__unpriv__preface.json b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__preface.json new file mode 100644 index 0000000000..13c6fbe8a5 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__preface.json @@ -0,0 +1,606 @@ +{ + "source_file": "src/unpriv/preface.adoc", + "total": 75, + "sentences": [ + { + "text": "| |Base |Version |*RV32I* |*2.1* |*RV32E* |*2.0* |*RV64E* |*2.0* |*RV64I* |*2.1*", + "section": "Preamble > Preface", + "line_range": [ + 14, + 20 + ] + }, + { + "text": "|*Zifencei* |*2.0* |*Zicsr* |*2.0* |*Zicntr* |*2.0* |*Zihpm* |*2.0* |*Zihintntl* |*1.0* |*Zihintpause* |*2.0* |*Zimop* |*1.0* |*Zcmop* |*1.0* |*Zicond* |*1.0* |*Zilsd* |*1.0* |*M* |*2.0* |*Zmmul* |*1.0* |*A* |*2.1* |*Zalrsc* |*1.0* |*Zaamo* |*1.0* |*Zawrs* |*1.0* |*Zacas* |*1.0* |*Zabha* |*1.0* |*Zalasr* |*1.0* |*RVWMO* |*2.0* |*Ztso* |*1.0* |*Zicbom* |*1.0* |*Zicboz* |*1.0* |*Zicbop* |*1.0* |*F* |*2.2* |*D* |*2.2* |*Q* |*2.2* |*Zfh* |*1.0* |*Zfhmin* |*1.0* |*Zfbfmin* |*1.0* |*Zfa* |*1.0* |*Zfinx* |*1.0* |*Zdinx* |*1.0* |*Zhinx* |*1.0* |*Zhinxmin* |*1.0* |*C* |*2.0* |*Zce* |*1.0* |*Zca* |*1.0* |*Zcf* |*1.0* |*Zcd* |*1.0* |*Zcb* |*1.0* |*Zcmp* |*1.0* |*Zcmt* |*1.0* |*Zclsd* |*1.0* |*B* |*1.0* |*Zba* |*1.0* |*Zbb* |*1.0* |*Zbc* |*1.0* |*Zbs* |*1.0* |*Zbkb* |*1.0* |*Zbkc* |*1.0* |*Zbkx* |*1.0* |*V* |*1.0* |*Zvl{asterisk}* |*1.0* |*Zve32x* |*1.0* |*Zve32f* |*1.0* |*Zve64x* |*1.0* |*Zve64f* |*1.0* |*Zve64d* |*1.0* |*Zvfhmin* |*1.0* |*Zvfh* |*1.0* |*Zvfbfmin* |*1.0* |*Zvfbfwma* |*1.0* |*Zknd* |*1.0* |*Zkne* |*1.0* |*Zknh* |*1.0* |*Zksed* |*1.0* |*Zksh* |*1.0* |*Zkr* |*1.0* |*Zkn* |*1.0* |*Zks* |*1.0* |*Zk* |*1.0* |*Zkt* |*1.0* |*Zvbb* |*1.0* |*Zvbc* |*1.0* |*Zvkb* |*1.0* |*Zvkg* |*1.0* |*Zvkned* |*1.0* |*Zvknha* |*1.0* |*Zvknhb* |*1.0* |*Zvksed* |*1.0* |*Zvksh* |*1.0* |*Zvkn* |*1.0* |*Zvknc* |*1.0* |*Zvkng* |*1.0* |*Zvks* |*1.0* |*Zvksc* |*1.0* |*Zvksg* |*1.0* |*Zvkt* |*1.0* |*Zicfiss* |*1.0* |*Zicfilp* |*1.0* |*Zama16b* |*1.0* |*Za128rs* |*1.0* |*Za64rs* |*1.0* |*Zic64b* |*1.0* |*Ziccamoa* |*1.0* |*Ziccamoc* |*1.0* |*Ziccif* |*1.0* |*Zicclsm* |*1.0* |*Ziccrse* |*1.0* |", + "section": "Preamble > Preface", + "line_range": [ + 24, + 124 + ] + }, + { + "text": "The changes in this version of the document include:", + "section": "Preamble > Preface", + "line_range": [ + 126, + 126 + ] + }, + { + "text": "Addition of extensions that have already been ratified as part of the profile specifications. * Numerous non-normative descriptive improvements.", + "section": "Preamble > Preface", + "line_range": [ + 128, + 130 + ] + }, + { + "text": "[.big]*Preface to Document Version 20260120*", + "section": "Preamble > Preface", + "line_range": [ + 132, + 132 + ] + }, + { + "text": "This document describes the RISC-V unprivileged architecture.", + "section": "Preamble > Preface", + "line_range": [ + 134, + 136 + ] + }, + { + "text": "It contains the following versions of the RISC-V ISA modules, all of which have been ratified:", + "section": "Preamble > Preface", + "line_range": [ + 134, + 136 + ] + }, + { + "text": "| |Base |Version |Status |*RV32I* |*2.1* |*Ratified* |*RV32E* |*2.0* |*Ratified* |*RV64E* |*2.0* |*Ratified* |*RV64I* |*2.1* |*Ratified*", + "section": "Preamble > Preface", + "line_range": [ + 138, + 144 + ] + }, + { + "text": "h|Extension h|Version h|Status", + "section": "Preamble > Preface", + "line_range": [ + 146, + 146 + ] + }, + { + "text": "|*Zifencei* |*2.0* |*Ratified* |*Zicsr* |*2.0* |*Ratified* |*Zicntr* |*2.0* |*Ratified* |*Zihpm* | *2.0* | *Ratified* |*Zihintntl* |*1.0* |*Ratified* |*Zihintpause* |*2.0* |*Ratified* |*Zimop* | *1.0* | *Ratified* |*Zicond* | *1.0* |*Ratified* |*Zilsd* | *1.0* |*Ratified* |*M* |*2.0* |*Ratified* |*Zmmul* |*1.0* |*Ratified* |*A* |*2.1* |*Ratified* |*Zalrsc* |*1.0* | *Ratified* |*Zaamo* |*1.0* | *Ratified* |*Zawrs* |*1.0* |*Ratified* |*Zacas* |*1.0* |*Ratified* |*Zabha* |*1.0* |*Ratified* |*Zalasr* |*1.0* |*Ratified* |*RVWMO* |*2.0* |*Ratified* |*Ztso* |*1.0* |*Ratified* |*CMO* |*1.0* |*Ratified* |*F* |*2.2* |*Ratified* |*D* |*2.2* |*Ratified* |*Q* |*2.2* |*Ratified* |*Zfh* |*1.0* |*Ratified* |*Zfhmin* |*1.0* |*Ratified* |*BF16* |*1.0* |*Ratified* |*Zfa* |*1.0* |*Ratified* |*Zfinx* |*1.0* |*Ratified* |*Zdinx* |*1.0* |*Ratified* |*Zhinx* |*1.0* |*Ratified* |*Zhinxmin* |*1.0* |*Ratified* |*C* |*2.0* |*Ratified* |*Zce* |*1.0* |*Ratified* |*Zclsd* |*1.0* |*Ratified* |*B* |*1.0* |*Ratified* |*V* |*1.0* |*Ratified* |*Zbkb* |*1.0* |*Ratified* |*Zbkc* |*1.0* |*Ratified* |*Zbkx* |*1.0* |*Ratified* |*Zk* |*1.0* |*Ratified* |*Zks* |*1.0* |*Ratified* |*Zvbb* |*1.0* |*Ratified* |*Zvbc* |*1.0* |*Ratified* |*Zvkg* |*1.0* |*Ratified* |*Zvkned* |*1.0* |*Ratified* |*Zvknhb* |*1.0* |*Ratified* |*Zvksed* |*1.0* |*Ratified* |*Zvksh* |*1.0* |*Ratified* |*Zvkt* |*1.0* |*Ratified* |*Zicfiss* |*1.0* |*Ratified* |*Zicfilp* |*1.0* |*Ratified* |", + "section": "Preamble > Preface", + "line_range": [ + 148, + 200 + ] + }, + { + "text": "The changes in this version of the document include:", + "section": "Preamble > Preface", + "line_range": [ + 202, + 202 + ] + }, + { + "text": "Addition of the Zalasr extension for Load-Acquire/Store-Release operations.", + "section": "Preamble > Preface", + "line_range": [ + 204, + 204 + ] + }, + { + "text": "[.big]*Preface to Document Version 20250508*", + "section": "Preamble > Preface", + "line_range": [ + 206, + 206 + ] + }, + { + "text": "This document describes the RISC-V unprivileged architecture.", + "section": "Preamble > Preface", + "line_range": [ + 208, + 210 + ] + }, + { + "text": "It contains the following versions of the RISC-V ISA modules, all of which have been ratified:", + "section": "Preamble > Preface", + "line_range": [ + 208, + 210 + ] + }, + { + "text": "| |Base |Version |Status |*RV32I* |*2.1* |*Ratified* |*RV32E* |*2.0* |*Ratified* |*RV64E* |*2.0* |*Ratified* |*RV64I* |*2.1* |*Ratified*", + "section": "Preamble > Preface", + "line_range": [ + 212, + 218 + ] + }, + { + "text": "h|Extension h|Version h|Status", + "section": "Preamble > Preface", + "line_range": [ + 220, + 220 + ] + }, + { + "text": "|*Zifencei* |*2.0* |*Ratified* |*Zicsr* |*2.0* |*Ratified* |*Zicntr* |*2.0* |*Ratified* |*Zihintntl* |*1.0* |*Ratified* |*Zihintpause* |*2.0* |*Ratified* |*Zimop* | *1.0* | *Ratified* |*Zicond* | *1.0* |*Ratified* |*Zilsd* | *1.0* |*Ratified* |*M* |*2.0* |*Ratified* |*Zmmul* |*1.0* |*Ratified* |*A* |*2.1* |*Ratified* |*Zalrsc* |*1.0* | *Ratified* |*Zaamo* |*1.0* | *Ratified* |*Zawrs* |*1.0* |*Ratified* |*Zacas* |*1.0* |*Ratified* |*Zabha* |*1.0* |*Ratified* |*RVWMO* |*2.0* |*Ratified* |*Ztso* |*1.0* |*Ratified* |*CMO* |*1.0* |*Ratified* |*F* |*2.2* |*Ratified* |*D* |*2.2* |*Ratified* |*Q* |*2.2* |*Ratified* |*Zfh* |*1.0* |*Ratified* |*Zfhmin* |*1.0* |*Ratified* |*BF16* |*1.0* |*Ratified* |*Zfa* |*1.0* |*Ratified* |*Zfinx* |*1.0* |*Ratified* |*Zdinx* |*1.0* |*Ratified* |*Zhinx* |*1.0* |*Ratified* |*Zhinxmin* |*1.0* |*Ratified* |*C* |*2.0* |*Ratified* |*Zce* |*1.0* |*Ratified* |*Zclsd* |*1.0* |*Ratified* |*B* |*1.0* |*Ratified* |*V* |*1.0* |*Ratified* |*Zbkb* |*1.0* |*Ratified* |*Zbkc* |*1.0* |*Ratified* |*Zbkx* |*1.0* |*Ratified* |*Zk* |*1.0* |*Ratified* |*Zks* |*1.0* |*Ratified* |*Zvbb* |*1.0* |*Ratified* |*Zvbc* |*1.0* |*Ratified* |*Zvkg* |*1.0* |*Ratified* |*Zvkned* |*1.0* |*Ratified* |*Zvknhb* |*1.0* |*Ratified* |*Zvksed* |*1.0* |*Ratified* |*Zvksh* |*1.0* |*Ratified* |*Zvkt* |*1.0* |*Ratified* |*Zicfiss* |*1.0* |*Ratified* |*Zicfilp* |*1.0* |*Ratified* |", + "section": "Preamble > Preface", + "line_range": [ + 222, + 272 + ] + }, + { + "text": "The changes in this version of the document include:", + "section": "Preamble > Preface", + "line_range": [ + 274, + 274 + ] + }, + { + "text": "The inclusion of all ratified extensions through May 2025. * Removal of all unratified material. * Addition of the BFloat16-precision Floating Point extension. * Addition of the Zabha extension for Byte and Halfword Atomic Memory Operations.", + "section": "Preamble > Preface", + "line_range": [ + 276, + 279 + ] + }, + { + "text": "[.big]*Preface to Document Version 20240411*", + "section": "Preamble > Preface", + "line_range": [ + 281, + 281 + ] + }, + { + "text": "This document describes the RISC-V unprivileged architecture.", + "section": "Preamble > Preface", + "line_range": [ + 283, + 284 + ] + }, + { + "text": "It contains the following versions of the RISC-V ISA modules:", + "section": "Preamble > Preface", + "line_range": [ + 283, + 284 + ] + }, + { + "text": "| |Base |Version |Status |*RV32I* |*2.1* |*Ratified* |*RV32E* |*2.0* |*Ratified* |*RV64E* |*2.0* |*Ratified* |*RV64I* |*2.1* |*Ratified*", + "section": "Preamble > Preface", + "line_range": [ + 286, + 292 + ] + }, + { + "text": "h|Extension h|Version h|Status", + "section": "Preamble > Preface", + "line_range": [ + 294, + 294 + ] + }, + { + "text": "|*Zifencei* |*2.0* |*Ratified* |*Zicsr* |*2.0* |*Ratified* |*Zicntr* |*2.0* |*Ratified* |*Zihintntl* |*1.0* |*Ratified* |*Zihintpause* |*2.0* |*Ratified* |*Zimop* | *1.0* | *Ratified* |*Zicond* | *1.0* |*Ratified* |*Zilsd* | *1.0* |*Ratified* |*M* |*2.0* |*Ratified* |*Zmmul* |*1.0* |*Ratified* |*A* |*2.1* |*Ratified* |*Zalrsc* |*1.0* | *Ratified* |*Zaamo* |*1.0* | *Ratified* |*Zawrs* |*1.0* |*Ratified* |*Zacas* |*1.0* |*Ratified* |*Zabha* |*1.0* |*Ratified* |*RVWMO* |*2.0* |*Ratified* |*Ztso* |*1.0* |*Ratified* |*CMO* |*1.0* |*Ratified* |*F* |*2.2* |*Ratified* |*D* |*2.2* |*Ratified* |*Q* |*2.2* |*Ratified* |*Zfh* |*1.0* |*Ratified* |*Zfhmin* |*1.0* |*Ratified* |*Zfa* |*1.0* |*Ratified* |*Zfinx* |*1.0* |*Ratified* |*Zdinx* |*1.0* |*Ratified* |*Zhinx* |*1.0* |*Ratified* |*Zhinxmin* |*1.0* |*Ratified* |*C* |*2.0* |*Ratified* |*Zce* |*1.0* |*Ratified* |*Zclsd* |*1.0* |*Ratified* |*B* |*1.0* |*Ratified* |*V* |*1.0* |*Ratified* |*Zbkb* |*1.0* |*Ratified* |*Zbkc* |*1.0* |*Ratified* |*Zbkx* |*1.0* |*Ratified* |*Zk* |*1.0* |*Ratified* |*Zks* |*1.0* |*Ratified* |*Zvbb* |*1.0* |*Ratified* |*Zvbc* |*1.0* |*Ratified* |*Zvkg* |*1.0* |*Ratified* |*Zvkned* |*1.0* |*Ratified* |*Zvknhb* |*1.0* |*Ratified* |*Zvksed* |*1.0* |*Ratified* |*Zvksh* |*1.0* |*Ratified* |*Zvkt* |*1.0* |*Ratified* |*Zicfiss* |*1.0* |*Ratified* |*Zicfilp* |*1.0* |*Ratified* |", + "section": "Preamble > Preface", + "line_range": [ + 296, + 345 + ] + }, + { + "text": "The changes in this version of the document include:", + "section": "Preamble > Preface", + "line_range": [ + 347, + 347 + ] + }, + { + "text": "The inclusion of all ratified extensions through February 2025. * The draft Zam extension has been removed, in favor of the definition of a misaligned atomicity granule PMA. * The concept of vacant memory regions has been superseded by inaccessible memory or I/O regions. * The removal of unratified content, including the sketch of the RV128I base ISA.", + "section": "Preamble > Preface", + "line_range": [ + 349, + 352 + ] + }, + { + "text": "[.big]*Preface to Document Version 20191213-Base-Ratified*", + "section": "Preamble > Preface", + "line_range": [ + 354, + 354 + ] + }, + { + "text": "This document describes the RISC-V unprivileged architecture.", + "section": "Preamble > Preface", + "line_range": [ + 356, + 356 + ] + }, + { + "text": "The ISA modules marked *Ratified* have been ratified at this time.", + "section": "Preamble > Preface", + "line_range": [ + 358, + 361 + ] + }, + { + "text": "The modules marked Frozen are not expected to change significantly before being put up for ratification.", + "section": "Preamble > Preface", + "line_range": [ + 358, + 361 + ] + }, + { + "text": "The modules marked Draft are expected to change before ratification.", + "section": "Preamble > Preface", + "line_range": [ + 358, + 361 + ] + }, + { + "text": "The document contains the following versions of the RISC-V ISA modules:", + "section": "Preamble > Preface", + "line_range": [ + 363, + 363 + ] + }, + { + "text": "| |Base |Version |Status |RVWMO |2.0 |*Ratified* |*RV32I* |*2.1* |*Ratified* |*RV64I* |*2.1* |*Ratified* |RV32E |1.9 |Draft |RV128I |1.7 |Draft h|Extension h|Version h|Status |*M* |*2.0* |*Ratified* |*A* |*2.1* |*Ratified* |*F* |*2.2* |*Ratified* |*D* |*2.2* |*Ratified* |*Q* |*2.2* |*Ratified* |*C* |*2.0* |*Ratified* |Counters |2.0 |Draft |L |0.0 |Draft |B |0.0 |Draft |J |0.0 |Draft |T |0.0 |Draft |P |0.2 |Draft |V |0.7 |Draft |*Zicsr* |*2.0* |*Ratified* |*Zifencei* |*2.0* |*Ratified* |Zam |0.1 |Draft |Ztso |0.1 |Frozen |", + "section": "Preamble > Preface", + "line_range": [ + 365, + 391 + ] + }, + { + "text": "The changes in this version of the document include:", + "section": "Preamble > Preface", + "line_range": [ + 393, + 393 + ] + }, + { + "text": "The A extension, now version 2.1, was ratified by the board in December 2019. * Defined big-endian ISA variant. * Moved N extension for user-mode interrupts into Volume II. * Defined PAUSE hint instruction.", + "section": "Preamble > Preface", + "line_range": [ + 395, + 399 + ] + }, + { + "text": "[.big]*Preface to Document Version 20190608-Base-Ratified*", + "section": "Preamble > Preface", + "line_range": [ + 401, + 401 + ] + }, + { + "text": "This document describes the RISC-V unprivileged architecture.", + "section": "Preamble > Preface", + "line_range": [ + 403, + 403 + ] + }, + { + "text": "The RVWMO memory model has been ratified at this time.", + "section": "Preamble > Preface", + "line_range": [ + 405, + 409 + ] + }, + { + "text": "The ISA modules marked *Ratified*, have been ratified at this time.", + "section": "Preamble > Preface", + "line_range": [ + 405, + 409 + ] + }, + { + "text": "The modules marked Frozen are not expected to change significantly before being put up for ratification.", + "section": "Preamble > Preface", + "line_range": [ + 405, + 409 + ] + }, + { + "text": "The modules marked Draft are expected to change before ratification.", + "section": "Preamble > Preface", + "line_range": [ + 405, + 409 + ] + }, + { + "text": "The document contains the following versions of the RISC-V ISA modules:", + "section": "Preamble > Preface", + "line_range": [ + 411, + 411 + ] + }, + { + "text": "| |Base |Version |Status |RVWMO |2.0 |*Ratified* |*RV32I* |*2.1* |*Ratified* |*RV64I* |*2.1* |*Ratified* |RV32E |1.9 |Draft |RV128I |1.7 |Draft h|Extension h|Version h|Status |*Zifencei* |*2.0* |*Ratified* |*Zicsr* |*2.0* |*Ratified* |*M* |*2.0* |*Ratified* |A |2.0 |Frozen |*F* |*2.2* |*Ratified* |*D* |*2.2* |*Ratified* |*Q* |*2.2* |*Ratified* |*C* |*2.0* |*Ratified* |Ztso |0.1 |Frozen |Counters |2.0 |Draft |L |0.0 |Draft |B |0.0 |Draft |J |0.0 |Draft |T |0.0 |Draft |P |0.2 |Draft |V |0.7 |Draft |Zam |0.1 |Draft |", + "section": "Preamble > Preface", + "line_range": [ + 413, + 439 + ] + }, + { + "text": "The changes in this version of the document include:", + "section": "Preamble > Preface", + "line_range": [ + 441, + 441 + ] + }, + { + "text": "Moved description to *Ratified* for the ISA modules ratified by the board in early 2019. * Removed the A extension from ratification. * Changed document version scheme to avoid confusion with versions of the ISA modules. * Incremented the version numbers of the base integer ISA to 2.1, reflecting the presence of the ratified RVWMO memory model and exclusion of FENCE.I, counters, and CSR instructions that were in previous base ISA. * Incremented the version numbers of the F and D extensions to 2.2, reflecting that version 2.1 changed the canonical NaN, and version 2.2 defined the NaN-boxing scheme and changed the definition of the FMIN and FMAX instructions. * Changed name of document to refer to \"unprivileged\" instructions as part of move to separate ISA specifications from platform profile mandates. * Added clearer and more precise definitions of execution environments, harts, traps, and memory accesses. * Defined instruction-set categories: standard, reserved, custom, non-standard, and non-conforming. * Removed text implying operation under alternate endianness, as alternate-endianness operation has not yet been defined for RISC-V. * Changed description of misaligned load and store behavior.", + "section": "Preamble > Preface", + "line_range": [ + 443, + 503 + ] + }, + { + "text": "The specification now allows visible misaligned address traps in execution environment interfaces, rather than just mandating invisible handling of misaligned loads and stores in user mode.", + "section": "Preamble > Preface", + "line_range": [ + 443, + 503 + ] + }, + { + "text": "Also, now allows access-fault exceptions to be reported for misaligned accesses (including atomics) that should not be emulated. * Moved FENCE.I out of the mandatory base and into a separate extension, with Zifencei ISA name. FENCE.I was removed from the Linux user ABI and is problematic in implementations with large incoherent instruction and data caches.", + "section": "Preamble > Preface", + "line_range": [ + 443, + 503 + ] + }, + { + "text": "However, it remains the only standard instruction-fetch coherence mechanism. * Removed prohibitions on using RV32E with other extensions. * Removed platform-specific mandates that certain encodings produce illegal-instruction exceptions in RV32E and RV64I chapters. * Counter/timer instructions are now not considered part of the mandatory base ISA, and so CSR instructions were moved into separate chapter and marked as version 2.0, with the unprivileged counters moved into another separate chapter.", + "section": "Preamble > Preface", + "line_range": [ + 443, + 503 + ] + }, + { + "text": "The counters are not ready for ratification as there are outstanding issues, including counter inaccuracies. * A CSR-access ordering model has been added. * Explicitly defined the 16-bit half-precision floating-point format for floating-point instructions in the 2-bit fmt field. * Defined the signed-zero behavior of FMIN.fmt and FMAX.fmt, and changed their behavior on signaling-NaN inputs to conform to the `minimumNumber` and `maximumNumber` operations in the proposed IEEE 754-201x specification. * The memory consistency model, RVWMO, has been defined. * The \"Zam\" extension, which permits misaligned AMOs and specifies their semantics, has been defined. * The \"Ztso\" extension, which enforces a stricter memory consistency model than RVWMO, has been defined. * Improvements to the description and commentary. * Defined the term `IALIGN` as shorthand to describe the instruction-address alignment constraint. * Removed text of `P` extension chapter as now superseded by active task group documents. * Removed text of `V` extension chapter as now superseded by separate vector extension draft document.", + "section": "Preamble > Preface", + "line_range": [ + 443, + 503 + ] + }, + { + "text": "[.big]*Preface to Document Version 2.2*", + "section": "Preamble > Preface", + "line_range": [ + 505, + 505 + ] + }, + { + "text": "This is version 2.2 of the document describing the RISC-V user-level architecture.", + "section": "Preamble > Preface", + "line_range": [ + 507, + 509 + ] + }, + { + "text": "The document contains the following versions of the RISC-V ISA modules:", + "section": "Preamble > Preface", + "line_range": [ + 507, + 509 + ] + }, + { + "text": "| h|Base h|Version h|Draft Frozen? |RV32I |2.0 |Y |RV32E |1.9 |N |RV64I |2.0 |Y |RV128I |1.7 |N h|Extension h|Version h|Frozen? |M |2.0 |Y |A |2.0 |Y |F |2.0 |Y |D |2.0 |Y |Q |2.0 |Y |L |0.0 |N |C |2.0 |Y |B |0.0 |N |J |0.0 |N |T |0.0 |N |P |0.1 |N |V |0.7 |N |N |1.1 |N |", + "section": "Preamble > Preface", + "line_range": [ + 511, + 532 + ] + }, + { + "text": "To date, no parts of the standard have been officially ratified by the RISC-V Foundation, but the components labeled \"frozen\" above are not expected to change during the ratification process beyond resolving ambiguities and holes in the specification.", + "section": "Preamble > Preface", + "line_range": [ + 534, + 537 + ] + }, + { + "text": "The major changes in this version of the document include:", + "section": "Preamble > Preface", + "line_range": [ + 539, + 539 + ] + }, + { + "text": "The previous version of this document was released under a Creative Commons Attribution 4.0 International License by the original authors, and this and future versions of this document will be released under the same license. * Rearranged chapters to put all extensions first in canonical order. * Improvements to the description and commentary. * Modified implicit hinting suggestion on `JALR` to support more efficient macro-op fusion of `LUI/JALR` and `AUIPC/JALR` pairs. * Clarification of constraints on load-reserved/store-conditional sequences. * A new table of control and status register (CSR) mappings. * Clarified purpose and behavior of high-order bits of `fcsr`. * Corrected the description of the `FNMADD`.fmt and `FNMSUB`.fmt instructions, which had suggested the incorrect sign of a zero result. * Instructions `FMV.S.X` and `FMV.X.S` were renamed to `FMV.W.X` and `FMV.X.W` respectively to be more consistent with their semantics, which did not change.", + "section": "Preamble > Preface", + "line_range": [ + 541, + 569 + ] + }, + { + "text": "The old names will continue to be supported in the tools. * Specified behavior of narrower ( Preface", + "line_range": [ + 541, + 569 + ] + }, + { + "text": "[.big]*Preface to Document Version 2.1*", + "section": "Preamble > Preface", + "line_range": [ + 571, + 571 + ] + }, + { + "text": "This is version 2.1 of the document describing the RISC-V user-level architecture.", + "section": "Preamble > Preface", + "line_range": [ + 573, + 578 + ] + }, + { + "text": "Note the frozen user-level ISA base and extensions `IMAFDQ` version 2.0 have not changed from the previous version of this document cite:[riscvtr2], but some specification holes have been fixed and the documentation has been improved.", + "section": "Preamble > Preface", + "line_range": [ + 573, + 578 + ] + }, + { + "text": "Some changes have been made to the software conventions.", + "section": "Preamble > Preface", + "line_range": [ + 573, + 578 + ] + }, + { + "text": "Numerous additions and improvements to the commentary sections. * Separate version numbers for each chapter. * Modification to long instruction encodings >64 bits to avoid moving the rd specifier in very long instruction formats. * CSR instructions are now described in the base integer format where the counter registers are introduced, as opposed to only being introduced later in the floating-point section (and the companion privileged architecture manual). * The SCALL and SBREAK instructions have been renamed to `ECALL` and `EBREAK`, respectively.", + "section": "Preamble > Preface", + "line_range": [ + 580, + 601 + ] + }, + { + "text": "Their encoding and functionality are unchanged. * Clarification of floating-point NaN handling, and a new canonical NaN value. * Clarification of values returned by floating-point to integer conversions that overflow. * Clarification of `LR/SC` allowed successes and required failures, including use of compressed instructions in the sequence. * A new `RV32E` base ISA proposal for reduced integer register counts, supports `MAC` extensions. * A revised calling convention. * Relaxed stack alignment for soft-float calling convention, and description of the RV32E calling convention. * A revised proposal for the `C` compressed extension, version 1.9 .", + "section": "Preamble > Preface", + "line_range": [ + 580, + 601 + ] + }, + { + "text": "[.big]*Preface to Version 2.0*", + "section": "Preamble > Preface", + "line_range": [ + 603, + 603 + ] + }, + { + "text": "This is the second release of the user ISA specification, and we intend the specification of the base user ISA plus general extensions (i.e., IMAFD) to remain fixed for future development.", + "section": "Preamble > Preface", + "line_range": [ + 605, + 608 + ] + }, + { + "text": "The following changes have been made since Version 1.0 cite:[riscvtr] of this ISA specification.", + "section": "Preamble > Preface", + "line_range": [ + 605, + 608 + ] + }, + { + "text": "The ISA has been divided into an integer base with several standard extensions. * The instruction formats have been rearranged to make immediate encoding more efficient. * The base ISA has been defined to have a little-endian memory system, with big-endian or bi-endian as non-standard variants. * Load-Reserved/Store-Conditional (`LR/SC`) instructions have been added in the atomic instruction extension. * `AMOs` and `LR/SC` can support the release consistency model. * The `FENCE` instruction provides finer-grain memory and I/O orderings. * An `AMO` for fetch-and-`XOR` (`AMOXOR`) has been added, and the encoding for `AMOSWAP` has been changed to make room. * The `AUIPC` instruction, which adds a 20-bit upper immediate to the `PC`, replaces the `RDNPC` instruction, which only read the current `PC` value.", + "section": "Preamble > Preface", + "line_range": [ + 610, + 658 + ] + }, + { + "text": "This results in significant savings for position-independent code. * The `JAL` instruction has now moved to the `U-Type` format with an explicit destination register, and the `J` instruction has been dropped being replaced by `JAL` with rd=`x0`.", + "section": "Preamble > Preface", + "line_range": [ + 610, + 658 + ] + }, + { + "text": "This removes the only instruction with an implicit destination register and removes the `J-Type` instruction format from the base ISA.", + "section": "Preamble > Preface", + "line_range": [ + 610, + 658 + ] + }, + { + "text": "There is an accompanying reduction in `JAL` reach, but a significant reduction in base ISA complexity. * The static hints on the `JALR` instruction have been dropped.", + "section": "Preamble > Preface", + "line_range": [ + 610, + 658 + ] + }, + { + "text": "The hints are redundant with the rd and rs1 register specifiers for code compliant with the standard calling convention. * The `JALR` instruction now clears the lowest bit of the calculated target address, to simplify hardware and to allow auxiliary information to be stored in function pointers. * The `MFTX.S` and `MFTX.D` instructions have been renamed to `FMV.X.S` and `FMV.X.D`, respectively.", + "section": "Preamble > Preface", + "line_range": [ + 610, + 658 + ] + }, + { + "text": "Similarly, `MXTF.S` and `MXTF.D` instructions have been renamed to `FMV.S.X` and `FMV.D.X`, respectively. * The `MFFSR` and `MTFSR` instructions have been renamed to `FRCSR` and `FSCSR`, respectively. `FRRM`, `FSRM`, `FRFLAGS`, and `FSFLAGS` instructions have been added to individually access the rounding mode and exception flags subfields of the `fcsr`. * The `FMV.X.S` and `FMV.X.D` instructions now source their operands from rs1, instead of rs2.", + "section": "Preamble > Preface", + "line_range": [ + 610, + 658 + ] + }, + { + "text": "This change simplifies datapath design. * `FCLASS.S` and `FCLASS.D` floating-point classify instructions have been added. * A simpler NaN generation and propagation scheme has been adopted. * For `RV32I`, the system performance counters have been extended to 64-bits wide, with separate read access to the upper and lower 32 bits. * Canonical `NOP` and `MV` encodings have been defined. * Standard instruction-length encodings have been defined for 48-bit, 64-bit, and >64-bit instructions. * Description of a 128-bit address space variant, `RV128`, has been added. * Major opcodes in the 32-bit base instruction format have been allocated for user-defined custom extensions. * A typographical error that suggested that stores source their data from rd has been corrected to refer to rs2.", + "section": "Preamble > Preface", + "line_range": [ + 610, + 658 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__unpriv__q-st-ext.json b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__q-st-ext.json new file mode 100644 index 0000000000..dc97a96ed4 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__q-st-ext.json @@ -0,0 +1,158 @@ +{ + "source_file": "src/unpriv/q-st-ext.adoc", + "total": 19, + "sentences": [ + { + "text": "This chapter describes the Q standard extension for quad-precision floating-point, which adds computational instructions compliant with the IEEE 754-2008 arithmetic standard's binary128 format and operations.", + "section": "Preamble > \"Q\" Extension for Quad-Precision Floating-Point, Version 2.2", + "line_range": [ + 3, + 6 + ] + }, + { + "text": "The Q extension depends on the D extension.", + "section": "Preamble > \"Q\" Extension for Quad-Precision Floating-Point, Version 2.2", + "line_range": [ + 3, + 6 + ] + }, + { + "text": "The floating-point registers are now extended to hold either a single, double, or quad-precision floating-point value (FLEN=128).", + "section": "Preamble > \"Q\" Extension for Quad-Precision Floating-Point, Version 2.2", + "line_range": [ + 8, + 12 + ] + }, + { + "text": "The NaN-boxing scheme described in is now extended recursively to allow a single-precision value to be NaN-boxed inside a double-precision value which is itself NaN-boxed inside a quad-precision value.", + "section": "Preamble > \"Q\" Extension for Quad-Precision Floating-Point, Version 2.2", + "line_range": [ + 8, + 12 + ] + }, + { + "text": "New 128-bit variants of LOAD-FP and STORE-FP instructions are added, encoded with a new value for the funct3 width field.", + "section": "Preamble > \"Q\" Extension for Quad-Precision Floating-Point, Version 2.2 > Quad-Precision Load and Store Instructions", + "line_range": [ + 16, + 18 + ] + }, + { + "text": "FLQ and FSQ are only guaranteed to execute atomically if the effective address is naturally aligned and XLEN=128.", + "section": "Preamble > \"Q\" Extension for Quad-Precision Floating-Point, Version 2.2 > Quad-Precision Load and Store Instructions", + "line_range": [ + 24, + 26 + ] + }, + { + "text": "FLQ and FSQ do not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved.", + "section": "Preamble > \"Q\" Extension for Quad-Precision Floating-Point, Version 2.2 > Quad-Precision Load and Store Instructions", + "line_range": [ + 28, + 30 + ] + }, + { + "text": "A new supported format is added to the format field of most instructions, as shown in", + "section": "Preamble > \"Q\" Extension for Quad-Precision Floating-Point, Version 2.2 > Quad-Precision Load and Store Instructions > Quad-Precision Computational Instructions", + "line_range": [ + 34, + 35 + ] + }, + { + "text": ".Format field encoding. | |fmt field |Mnemonic |Meaning |00 |S |32-bit single-precision |01 |D |64-bit double-precision |10 |H |16-bit half-precision |11 |Q |128-bit quad-precision |", + "section": "Preamble > \"Q\" Extension for Quad-Precision Floating-Point, Version 2.2 > Quad-Precision Load and Store Instructions > Quad-Precision Computational Instructions", + "line_range": [ + 37, + 46 + ] + }, + { + "text": "The quad-precision floating-point computational instructions are defined analogously to their double-precision counterparts, but operate on quad-precision operands and produce quad-precision results.", + "section": "Preamble > \"Q\" Extension for Quad-Precision Floating-Point, Version 2.2 > Quad-Precision Load and Store Instructions > Quad-Precision Computational Instructions", + "line_range": [ + 48, + 51 + ] + }, + { + "text": "New floating-point-to-integer and integer-to-floating-point conversion instructions are added.", + "section": "Preamble > \"Q\" Extension for Quad-Precision Floating-Point, Version 2.2 > Quad-Precision Load and Store Instructions > Quad-Precision Convert and Move Instructions", + "line_range": [ + 59, + 68 + ] + }, + { + "text": "These instructions are defined analogously to the double-precision-to-integer and integer-to-double-precision conversion instructions. FCVT.W.Q or FCVT.L.Q converts a quad-precision floating-point number to a signed 32-bit or 64-bit integer, respectively. FCVT.Q.W or FCVT.Q.L converts a 32-bit or 64-bit signed integer, respectively, into a quad-precision floating-point number. FCVT.WU.Q, FCVT.LU.Q, FCVT.Q.WU, and FCVT.Q.LU variants convert to or from unsigned integer values. FCVT.L[U].Q and FCVT.Q.L[U] are RV64-only instructions.", + "section": "Preamble > \"Q\" Extension for Quad-Precision Floating-Point, Version 2.2 > Quad-Precision Load and Store Instructions > Quad-Precision Convert and Move Instructions", + "line_range": [ + 59, + 68 + ] + }, + { + "text": "Note FCVT.Q.L[U] always produces an exact result and is unaffected by rounding mode.", + "section": "Preamble > \"Q\" Extension for Quad-Precision Floating-Point, Version 2.2 > Quad-Precision Load and Store Instructions > Quad-Precision Convert and Move Instructions", + "line_range": [ + 59, + 68 + ] + }, + { + "text": "New floating-point-to-floating-point conversion instructions are added.", + "section": "Preamble > \"Q\" Extension for Quad-Precision Floating-Point, Version 2.2 > Quad-Precision Load and Store Instructions > Quad-Precision Convert and Move Instructions", + "line_range": [ + 74, + 80 + ] + }, + { + "text": "These instructions are defined analogously to the double-precision floating-point-to-floating-point conversion instructions. FCVT.S.Q or FCVT.Q.S converts a quad-precision floating-point number to a single-precision floating-point number, or vice-versa, respectively. FCVT.D.Q or FCVT.Q.D converts a quad-precision floating-point number to a double-precision floating-point number, or vice-versa, respectively.", + "section": "Preamble > \"Q\" Extension for Quad-Precision Floating-Point, Version 2.2 > Quad-Precision Load and Store Instructions > Quad-Precision Convert and Move Instructions", + "line_range": [ + 74, + 80 + ] + }, + { + "text": "Floating-point to floating-point sign-injection instructions, FSGNJ.Q, FSGNJN.Q, and FSGNJX.Q are defined analogously to the double-precision sign-injection instruction.", + "section": "Preamble > \"Q\" Extension for Quad-Precision Floating-Point, Version 2.2 > Quad-Precision Load and Store Instructions > Quad-Precision Convert and Move Instructions", + "line_range": [ + 86, + 89 + ] + }, + { + "text": "FMV.X.Q and FMV.Q.X instructions are not provided in RV32 or RV64, so quad-precision bit patterns must be moved to the integer registers via memory.", + "section": "Preamble > \"Q\" Extension for Quad-Precision Floating-Point, Version 2.2 > Quad-Precision Load and Store Instructions > Quad-Precision Convert and Move Instructions", + "line_range": [ + 95, + 97 + ] + }, + { + "text": "The quad-precision floating-point compare instructions are defined analogously to their double-precision counterparts, but operate on quad-precision operands.", + "section": "Preamble > \"Q\" Extension for Quad-Precision Floating-Point, Version 2.2 > Quad-Precision Load and Store Instructions > Quad-Precision Floating-Point Compare Instructions", + "line_range": [ + 101, + 104 + ] + }, + { + "text": "The quad-precision floating-point classify instruction, FCLASS.Q, is defined analogously to its double-precision counterpart, but operates on quad-precision operands.", + "section": "Preamble > \"Q\" Extension for Quad-Precision Floating-Point, Version 2.2 > Quad-Precision Load and Store Instructions > Quad-Precision Floating-Point Classify Instruction", + "line_range": [ + 112, + 115 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__unpriv__rationale.json b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__rationale.json new file mode 100644 index 0000000000..061c5eedbf --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__rationale.json @@ -0,0 +1,486 @@ +{ + "source_file": "src/unpriv/rationale.adoc", + "total": 60, + "sentences": [ + { + "text": "This appendix contains the rationale for RISC-V ISA extensions at the time they were ratified.", + "section": "Preamble > Historical Rationale for Extensions", + "line_range": [ + 4, + 12 + ] + }, + { + "text": "Unlike the ISA specification, this appendix is ordered chronologically, so as to convey the motivation and architectural reasoning underpinning each extension at the time of ratification.", + "section": "Preamble > Historical Rationale for Extensions", + "line_range": [ + 4, + 12 + ] + }, + { + "text": "For extensions ratified prior to the conception of this appendix (ca. 2025), the rationale will be added over time.", + "section": "Preamble > Historical Rationale for Extensions", + "line_range": [ + 4, + 12 + ] + }, + { + "text": "In cases where the rationale was not recorded, the authors and editors will synthesize it from the historical record.", + "section": "Preamble > Historical Rationale for Extensions", + "line_range": [ + 4, + 12 + ] + }, + { + "text": "The PAUSE instruction hints to a hart that it should temporarily reduce its rate of execution.", + "section": "Preamble > Historical Rationale for Extensions > \"Zihintpause\" Extension for Pause Hint", + "line_range": [ + 16, + 19 + ] + }, + { + "text": "It is normally used to save energy and execution resources while polling, e.g. while waiting for a spinlock to become free.", + "section": "Preamble > Historical Rationale for Extensions > \"Zihintpause\" Extension for Pause Hint", + "line_range": [ + 16, + 19 + ] + }, + { + "text": "Much of the debate surrounding this extension centered on whether a facility similar to x86's MONITOR/MWAIT should instead be provided.", + "section": "Preamble > Historical Rationale for Extensions > \"Zihintpause\" Extension for Pause Hint", + "line_range": [ + 21, + 29 + ] + }, + { + "text": "We concluded that, even if such a facility were to be defined for RISC-V, it would not supplant PAUSE. PAUSE is more appropriate when polling for non-memory events, when polling for multiple events, or when software does not know precisely what events it is polling for. (Perhaps surprisingly, the latter case is ubiquitous, in part because it is the mechanism expected by the Linux kernel's `cpurelax` API.)", + "section": "Preamble > Historical Rationale for Extensions > \"Zihintpause\" Extension for Pause Hint", + "line_range": [ + 21, + 29 + ] + }, + { + "text": "Replacing unpredictable branches with conditional-select or conditional-move instructions can mitigate a class of costly branch mispredictions.", + "section": "Preamble > Historical Rationale for Extensions > \"Zicond\" Extension for Integer Conditional Operations", + "line_range": [ + 33, + 37 + ] + }, + { + "text": "Unfortunately, conditional-select instructions require three source operands.", + "section": "Preamble > Historical Rationale for Extensions > \"Zicond\" Extension for Integer Conditional Operations", + "line_range": [ + 33, + 37 + ] + }, + { + "text": "These instructions are a logical addition to ISAs that include three-source integer instructions for other reasons, but are too costly otherwise.", + "section": "Preamble > Historical Rationale for Extensions > \"Zicond\" Extension for Integer Conditional Operations", + "line_range": [ + 33, + 37 + ] + }, + { + "text": "Some ISAs have instead furnished conditional-move instructions, which consume less encoding space and avoid the extra register read in simple microarchitectures.", + "section": "Preamble > Historical Rationale for Extensions > \"Zicond\" Extension for Integer Conditional Operations", + "line_range": [ + 39, + 44 + ] + }, + { + "text": "Unfortunately, in register-renamed microarchitectures, these instructions incur costs simlar to conditional select, or require additional microarchitectural structures and micro-op-issue constraints.", + "section": "Preamble > Historical Rationale for Extensions > \"Zicond\" Extension for Integer Conditional Operations", + "line_range": [ + 39, + 44 + ] + }, + { + "text": "The Zicond extension was defined to solve the same problem as conditional select and conditional move, but with very little incremental cost for complex microarchitectures.", + "section": "Preamble > Historical Rationale for Extensions > \"Zicond\" Extension for Integer Conditional Operations", + "line_range": [ + 46, + 56 + ] + }, + { + "text": "It provides conditional-zero instructions, which read two source operands and, based upon the zeroness of the second operand, produce either the first operand or zero.", + "section": "Preamble > Historical Rationale for Extensions > \"Zicond\" Extension for Integer Conditional Operations", + "line_range": [ + 46, + 56 + ] + }, + { + "text": "These instructions can be used as part of a three-instruction sequence to synthesize conditional select.", + "section": "Preamble > Historical Rationale for Extensions > \"Zicond\" Extension for Integer Conditional Operations", + "line_range": [ + 46, + 56 + ] + }, + { + "text": "Several common conditional-execution idioms require only two instructions, as would be the case with conditional select or move, including conditional addition, subtraction, and bitwise AND, OR, and XOR.", + "section": "Preamble > Historical Rationale for Extensions > \"Zicond\" Extension for Integer Conditional Operations", + "line_range": [ + 46, + 56 + ] + }, + { + "text": "Two conditional-zero instructions are included: one that writes zero if the comparand is zero, and one that does so if the comparand is nonzero.", + "section": "Preamble > Historical Rationale for Extensions > \"Zicond\" Extension for Integer Conditional Operations", + "line_range": [ + 58, + 61 + ] + }, + { + "text": "Variants that perform magnitude comparisons with zero were considered but ultimately excluded for insufficient quantitative justification.", + "section": "Preamble > Historical Rationale for Extensions > \"Zicond\" Extension for Integer Conditional Operations", + "line_range": [ + 58, + 61 + ] + }, + { + "text": "While compare-and-swap for XLEN wide data may be accomplished using LR/SC, the CAS atomic instructions scale better to highly parallel systems than LR/SC.", + "section": "Preamble > Historical Rationale for Extensions > \"Zacas\" Extension for Atomic Compare-and-Swap (CAS) Instructions", + "line_range": [ + 65, + 74 + ] + }, + { + "text": "Many lock-free algorithms, such as a lock-free queue, require manipulation of pointer variables. A simple CAS operation may not be sufficient to guard against what is commonly referred to as the ABA problem in such algorithms that manipulate pointer variables.", + "section": "Preamble > Historical Rationale for Extensions > \"Zacas\" Extension for Atomic Compare-and-Swap (CAS) Instructions", + "line_range": [ + 65, + 74 + ] + }, + { + "text": "To avoid the ABA problem, the algorithms associate a reference counter with the pointer variable and perform updates using a quadword compare and swap (of both the pointer and the counter).", + "section": "Preamble > Historical Rationale for Extensions > \"Zacas\" Extension for Atomic Compare-and-Swap (CAS) Instructions", + "line_range": [ + 65, + 74 + ] + }, + { + "text": "The double and quadword CAS instructions support implementation of algorithms for ABA problem avoidance.", + "section": "Preamble > Historical Rationale for Extensions > \"Zacas\" Extension for Atomic Compare-and-Swap (CAS) Instructions", + "line_range": [ + 65, + 74 + ] + }, + { + "text": "The CAS instruction supports the C++11 atomic compare and exchange operation.", + "section": "Preamble > Historical Rationale for Extensions > \"Zacas\" Extension for Atomic Compare-and-Swap (CAS) Instructions", + "line_range": [ + 76, + 77 + ] + }, + { + "text": "The A-extension offers atomic memory operation (AMO) instructions for words, doublewords, and quadwords (only for `AMOCAS`).", + "section": "Preamble > Historical Rationale for Extensions > \"Zabha\" Extension for Byte and Halfword Atomic Memory Operations, Version 1.0", + "line_range": [ + 81, + 86 + ] + }, + { + "text": "The absence of atomic operations for subword data types necessitates emulation strategies.", + "section": "Preamble > Historical Rationale for Extensions > \"Zabha\" Extension for Byte and Halfword Atomic Memory Operations, Version 1.0", + "line_range": [ + 81, + 86 + ] + }, + { + "text": "For bitwise operations, this emulation can be performed via word-sized bitwise AMO* instructions.", + "section": "Preamble > Historical Rationale for Extensions > \"Zabha\" Extension for Byte and Halfword Atomic Memory Operations, Version 1.0", + "line_range": [ + 81, + 86 + ] + }, + { + "text": "For non-bitwise operations, emulation is achievable using word-sized `LR`/`SC` instructions.", + "section": "Preamble > Historical Rationale for Extensions > \"Zabha\" Extension for Byte and Halfword Atomic Memory Operations, Version 1.0", + "line_range": [ + 81, + 86 + ] + }, + { + "text": "Several limitations arise from this emulation approach:", + "section": "Preamble > Historical Rationale for Extensions > \"Zabha\" Extension for Byte and Halfword Atomic Memory Operations, Version 1.0", + "line_range": [ + 88, + 88 + ] + }, + { + "text": "In systems with large-scale or Non-Uniform Memory Access (NUMA) configurations, emulation based on `LR`/`SC` introduces issues related to scalability and fairness, particularly under conditions of high contention.", + "section": "Preamble > Historical Rationale for Extensions > \"Zabha\" Extension for Byte and Halfword Atomic Memory Operations, Version 1.0", + "line_range": [ + 90, + 92 + ] + }, + { + "text": "Emulation of narrower AMOs through wider AMO* instructions on non-idempotent IO memory regions may result in unintended side effects.", + "section": "Preamble > Historical Rationale for Extensions > \"Zabha\" Extension for Byte and Halfword Atomic Memory Operations, Version 1.0", + "line_range": [ + 94, + 95 + ] + }, + { + "text": "Utilizing wider AMO* instructions for emulating narrower AMOs risks activating extraneous breakpoints or watchpoints.", + "section": "Preamble > Historical Rationale for Extensions > \"Zabha\" Extension for Byte and Halfword Atomic Memory Operations, Version 1.0", + "line_range": [ + 97, + 98 + ] + }, + { + "text": "In the absence of native support for subword atomics, compilers often resort to inlining code sequences to provide the required emulation.", + "section": "Preamble > Historical Rationale for Extensions > \"Zabha\" Extension for Byte and Halfword Atomic Memory Operations, Version 1.0", + "line_range": [ + 100, + 103 + ] + }, + { + "text": "This practice contributes to an increase in code size, with consequent impacts on system performance and memory utilization.", + "section": "Preamble > Historical Rationale for Extensions > \"Zabha\" Extension for Byte and Halfword Atomic Memory Operations, Version 1.0", + "line_range": [ + 100, + 103 + ] + }, + { + "text": "The Zabha extension addresses these limitations by adding support for byte and halfword atomic memory operations to the RISC-V Unprivileged ISA.", + "section": "Preamble > Historical Rationale for Extensions > \"Zabha\" Extension for Byte and Halfword Atomic Memory Operations, Version 1.0", + "line_range": [ + 105, + 106 + ] + }, + { + "text": "NOTE: The following text previously comprised the introduction to the BFloat16 extensions chapter.", + "section": "Preamble > Historical Rationale for Extensions > \"Zfbfmin\" Extension for Scalar BFloat16 Operations", + "line_range": [ + 110, + 112 + ] + }, + { + "text": "It needs to be rewritten to fit into the flow of the Rationale appendix.", + "section": "Preamble > Historical Rationale for Extensions > \"Zfbfmin\" Extension for Scalar BFloat16 Operations", + "line_range": [ + 110, + 112 + ] + }, + { + "text": "When FP16 (officially called binary16) was first introduced by IEEE 754-2008, it was just an interchange format.", + "section": "Preamble > Historical Rationale for Extensions > \"Zfbfmin\" Extension for Scalar BFloat16 Operations", + "line_range": [ + 114, + 117 + ] + }, + { + "text": "It was intended as a space/bandwidth efficient encoding that would be used to transfer information.", + "section": "Preamble > Historical Rationale for Extensions > \"Zfbfmin\" Extension for Scalar BFloat16 Operations", + "line_range": [ + 114, + 117 + ] + }, + { + "text": "This is in line with the Zfhmin extension.", + "section": "Preamble > Historical Rationale for Extensions > \"Zfbfmin\" Extension for Scalar BFloat16 Operations", + "line_range": [ + 114, + 117 + ] + }, + { + "text": "However, there were some applications (notably graphics) that found that the smaller precision and dynamic range was sufficient for their space.", + "section": "Preamble > Historical Rationale for Extensions > \"Zfbfmin\" Extension for Scalar BFloat16 Operations", + "line_range": [ + 119, + 122 + ] + }, + { + "text": "So, FP16 started to see some widespread adoption as an arithmetic format.", + "section": "Preamble > Historical Rationale for Extensions > \"Zfbfmin\" Extension for Scalar BFloat16 Operations", + "line_range": [ + 119, + 122 + ] + }, + { + "text": "This is in line with the Zfh extension.", + "section": "Preamble > Historical Rationale for Extensions > \"Zfbfmin\" Extension for Scalar BFloat16 Operations", + "line_range": [ + 119, + 122 + ] + }, + { + "text": "While it was not the intention of IEEE 754-2008 to have FP16 be an arithmetic format, it is supported by the standard.", + "section": "Preamble > Historical Rationale for Extensions > \"Zfbfmin\" Extension for Scalar BFloat16 Operations", + "line_range": [ + 124, + 130 + ] + }, + { + "text": "Even though IEEE 754 WG recognized that FP16 was gaining popularity, the working group decided to hold off on making it a basic format in IEEE 754-2019.", + "section": "Preamble > Historical Rationale for Extensions > \"Zfbfmin\" Extension for Scalar BFloat16 Operations", + "line_range": [ + 124, + 130 + ] + }, + { + "text": "This means that an IEEE 754-2019 compliant implementation of binary floating point, which needs to support at least one basic format, cannot support only FP16 - it needs to support at least one of binary32, binary64, and binary128.", + "section": "Preamble > Historical Rationale for Extensions > \"Zfbfmin\" Extension for Scalar BFloat16 Operations", + "line_range": [ + 124, + 130 + ] + }, + { + "text": "Experts working in machine learning noticed that FP16 was a much more compact way of storing operands and often provided sufficient precision for them.", + "section": "Preamble > Historical Rationale for Extensions > \"Zfbfmin\" Extension for Scalar BFloat16 Operations", + "line_range": [ + 132, + 144 + ] + }, + { + "text": "However, they also found that intermediate values were much better when accumulated into a higher precision.", + "section": "Preamble > Historical Rationale for Extensions > \"Zfbfmin\" Extension for Scalar BFloat16 Operations", + "line_range": [ + 132, + 144 + ] + }, + { + "text": "The final computations were then typically converted back into the more compact FP16 encoding.", + "section": "Preamble > Historical Rationale for Extensions > \"Zfbfmin\" Extension for Scalar BFloat16 Operations", + "line_range": [ + 132, + 144 + ] + }, + { + "text": "This approach has become very common in machine learning (ML) inference where the weights and activations are stored in FP16 encodings.", + "section": "Preamble > Historical Rationale for Extensions > \"Zfbfmin\" Extension for Scalar BFloat16 Operations", + "line_range": [ + 132, + 144 + ] + }, + { + "text": "There was the added benefit that smaller multiplication blocks could be created for the FP16's smaller number of significant bits.", + "section": "Preamble > Historical Rationale for Extensions > \"Zfbfmin\" Extension for Scalar BFloat16 Operations", + "line_range": [ + 132, + 144 + ] + }, + { + "text": "At this point, widening multiply-accumulate instructions became much more common.", + "section": "Preamble > Historical Rationale for Extensions > \"Zfbfmin\" Extension for Scalar BFloat16 Operations", + "line_range": [ + 132, + 144 + ] + }, + { + "text": "Also, more complicated dot product instructions started to show up including those that packed two FP16 numbers in a 32-bit register, multiplied these by another pair of FP16 numbers in another register, added these two products to an FP32 accumulate value in a 3rd register and returned an FP32 result.", + "section": "Preamble > Historical Rationale for Extensions > \"Zfbfmin\" Extension for Scalar BFloat16 Operations", + "line_range": [ + 132, + 144 + ] + }, + { + "text": "Experts working in machine learning at Google who continued to work with FP32 values noted that the least significant 16 bits of their mantissas were not always needed for good results, even in training.", + "section": "Preamble > Historical Rationale for Extensions > \"Zfbfmin\" Extension for Scalar BFloat16 Operations", + "line_range": [ + 146, + 158 + ] + }, + { + "text": "They proposed a truncated version of FP32, which was the 16 most significant bits of the FP32 encoding.", + "section": "Preamble > Historical Rationale for Extensions > \"Zfbfmin\" Extension for Scalar BFloat16 Operations", + "line_range": [ + 146, + 158 + ] + }, + { + "text": "This format was named BFloat16 (or BF16).", + "section": "Preamble > Historical Rationale for Extensions > \"Zfbfmin\" Extension for Scalar BFloat16 Operations", + "line_range": [ + 146, + 158 + ] + }, + { + "text": "The B in BF16, stands for Brain since it was initially introduced by the Google Brain team.", + "section": "Preamble > Historical Rationale for Extensions > \"Zfbfmin\" Extension for Scalar BFloat16 Operations", + "line_range": [ + 146, + 158 + ] + }, + { + "text": "Not only did they find that the number of significant bits in BF16 tended to be sufficient for their work (despite being fewer than in FP16), but it was very easy for them to reuse their existing data; FP32 numbers could be readily rounded to BF16 with a minimal amount of work.", + "section": "Preamble > Historical Rationale for Extensions > \"Zfbfmin\" Extension for Scalar BFloat16 Operations", + "line_range": [ + 146, + 158 + ] + }, + { + "text": "Furthermore, the even smaller number of the BF16 significant bits enabled even smaller multiplication blocks to be built.", + "section": "Preamble > Historical Rationale for Extensions > \"Zfbfmin\" Extension for Scalar BFloat16 Operations", + "line_range": [ + 146, + 158 + ] + }, + { + "text": "Similar to FP16, BF16 multiply-accumulate widening and dot-product instructions started to proliferate.", + "section": "Preamble > Historical Rationale for Extensions > \"Zfbfmin\" Extension for Scalar BFloat16 Operations", + "line_range": [ + 146, + 158 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__unpriv__rv-32-64g.json b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__rv-32-64g.json new file mode 100644 index 0000000000..d461053f8b --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__rv-32-64g.json @@ -0,0 +1,310 @@ +{ + "source_file": "src/unpriv/rv-32-64g.adoc", + "total": 38, + "sentences": [ + { + "text": "One goal of the RISC-V project is that it be used as a stable software development target.", + "section": "Preamble > RV32/64G Instruction Set Listings", + "line_range": [ + 4, + 10 + ] + }, + { + "text": "For this purpose, we define a combination of a base ISA (RV32I or RV64I) plus selected standard extensions (IMAFD, Zicsr, Zifencei) as a \"general-purpose\" ISA, and we use the abbreviation G for the IMAFDZicsrZifencei combination of instruction-set extensions.", + "section": "Preamble > RV32/64G Instruction Set Listings", + "line_range": [ + 4, + 10 + ] + }, + { + "text": "This chapter presents opcode maps and instruction-set listings for RV32G and RV64G.", + "section": "Preamble > RV32/64G Instruction Set Listings", + "line_range": [ + 4, + 10 + ] + }, + { + "text": ".RISC-V base opcode map, inst[1:0]=11 | |inst[4:2] .2+|000 .2+|001 .2+|010 .2+|011 .2+|100 .2+|101 .2+|110 .2+|111 (>32b) |inst[6:5] |00 |LOAD |LOAD-FP |custom-0 |MISC-MEM |OP-IMM |AUIPC |OP-IMM-32 |reserved |01 |STORE |STORE-FP |custom-1 |AMO |OP |LUI |OP-32 |reserved |10 |MADD |MSUB |NMSUB |NMADD |OP-FP |OP-V |custom-2 |reserved |11 |BRANCH |JALR |reserved |JAL |SYSTEM |OP-VE |custom-3 |reserved |", + "section": "Preamble > RV32/64G Instruction Set Listings", + "line_range": [ + 12, + 22 + ] + }, + { + "text": "shows a map of the major opcodes for RVG.", + "section": "Preamble > RV32/64G Instruction Set Listings", + "line_range": [ + 24, + 30 + ] + }, + { + "text": "Opcodes marked as reserved should be avoided for custom instruction-set extensions as they might be used by future standard extensions.", + "section": "Preamble > RV32/64G Instruction Set Listings", + "line_range": [ + 24, + 30 + ] + }, + { + "text": "Major opcodes marked as custom-0 through custom-3 will be avoided by future standard extensions and are recommended for use by custom instruction-set extensions within the base 32-bit instruction format.", + "section": "Preamble > RV32/64G Instruction Set Listings", + "line_range": [ + 24, + 30 + ] + }, + { + "text": "We believe RV32G and RV64G provide simple but complete instruction sets for a broad range of general-purpose computing.", + "section": "Preamble > RV32/64G Instruction Set Listings", + "line_range": [ + 32, + 36 + ] + }, + { + "text": "The optional compressed instruction-set extension ext:c[] can be added (forming RV32GC and RV64GC) to improve performance, code size, and energy efficiency, though with some additional hardware complexity.", + "section": "Preamble > RV32/64G Instruction Set Listings", + "line_range": [ + 32, + 36 + ] + }, + { + "text": "As we move beyond IMAFDC into further instruction-set extensions, the added instructions tend to be more domain-specific and only provide benefits to a restricted class of applications, e.g., for multimedia or security.", + "section": "Preamble > RV32/64G Instruction Set Listings", + "line_range": [ + 38, + 43 + ] + }, + { + "text": "Unlike most commercial ISAs, the RISC-V ISA design clearly separates the base ISA and broadly applicable standard extensions from these more specialized additions.", + "section": "Preamble > RV32/64G Instruction Set Listings", + "line_range": [ + 38, + 43 + ] + }, + { + "text": "| |31 |27 |26 |25 |24 | 20|19 | 15| 14 | 12|11 | 7|6 | 0| 4+^|funct7 2+^|rs2 2+^|rs1 2+^|funct3 2+^|rd 2+^|opcode <|R-type 6+^|imm[11:0] 2+^|rs1 2+^|funct3 2+^|rd 2+^|opcode <|I-type 4+^|imm[11:5] 2+^|rs2 2+^|rs1 2+^|funct3 2+^|imm[4:0] 2+^|opcode <|S-type 4+^|imm[12\\|10:5] 2+^|rs2 2+^|rs1 2+^|funct3 2+^|imm[4:1\\|11] 2+^|opcode <|B-type 10+^|imm[31:12] 2+^|rd 2+^|opcode <|U-type 10+^|imm[20\\|10:1\\|11\\|19:12] 2+^|rd 2+^|opcode <|J-type |", + "section": "Preamble > RV32/64G Instruction Set Listings", + "line_range": [ + 47, + 56 + ] + }, + { + "text": "| 15+^|*RV32I Base Instruction Set* 10+^|imm[31:12] 2+^|rd 2+^|0110111 <|LUI 10+^|imm[31:12] 2+^|rd 2+^|0010111 <|AUIPC 10+^|imm[20\\|10:1\\|11\\|19:12] 2+^|rd 2+^|1101111 <|JAL 6+^|imm[11:0] 2+^|rs1 2+^|000 2+^|rd 2+^|1100111 <|JALR 4+^|imm[12\\|10:5] 2+^|rs2 2+^|rs1 2+^|000 2+^|imm[4:1\\|11] 2+^|1100011 <|BEQ 4+^|imm[12\\|10:5] 2+^|rs2 2+^|rs1 2+^|001 2+^|imm[4:1\\|11] 2+^|1100011 <|BNE 4+^|imm[12\\|10:5] 2+^|rs2 2+^|rs1 2+^|100 2+^|imm[4:1\\|11] 2+^|1100011 <|BLT 4+^|imm[12\\|10:5] 2+^|rs2 2+^|rs1 2+^|101 2+^|imm[4:1\\|11] 2+^|1100011 <|BGE 4+^|imm[12\\|10:5] 2+^|rs2 2+^|rs1 2+^|110 2+^|imm[4:1\\|11] 2+^|1100011 <|BLTU 4+^|imm[12\\|10:5] 2+^|rs2 2+^|rs1 2+^|111 2+^|imm[4:1\\|11] 2+^|1100011 <|BGEU 6+^|imm[11:0] 2+^|rs1 2+^|000 2+^|rd 2+^|0000011 <|LB 6+^|imm[11:0] 2+^|rs1 2+^|001 2+^|rd 2+^|0000011 <|LH 6+^|imm[11:0] 2+^|rs1 2+^|010 2+^|rd 2+^|0000011 <|LW 6+^|imm[11:0] 2+^|rs1 2+^|100 2+^|rd 2+^|0000011 <|LBU 6+^|imm[11:0] 2+^|rs1 2+^|101 2+^|rd 2+^|0000011 <|LHU 4+^|imm[11:5] 2+^|rs2 2+^|rs1 2+^|000 2+^|imm[4:0] 2+^|0100011 <|SB 4+^|imm[11:5] 2+^|rs2 2+^|rs1 2+^|001 2+^|imm[4:0] 2+^|0100011 <|SH 4+^|imm[11:5] 2+^|rs2 2+^|rs1 2+^|010 2+^|imm[4:0] 2+^|0100011 <|SW 6+^|imm[11:0] 2+^|rs1 2+^|000 2+^|rd 2+^|0010011 <|ADDI 6+^|imm[11:0] 2+^|rs1 2+^|010 2+^|rd 2+^|0010011 <|SLTI 6+^|imm[11:0] 2+^|rs1 2+^|011 2+^|rd 2+^|0010011 <|SLTIU 6+^|imm[11:0] 2+^|rs1 2+^|100 2+^|rd 2+^|0010011 <|XORI 6+^|imm[11:0] 2+^|rs1 2+^|110 2+^|rd 2+^|0010011 <|ORI 6+^|imm[11:0] 2+^|rs1 2+^|111 2+^|rd 2+^|0010011 <|ANDI 4+^|0000000 2+^|shamt 2+^|rs1 2+^|001 2+^|rd 2+^|0010011 <|SLLI 4+^|0000000 2+^|shamt 2+^|rs1 2+^|101 2+^|rd 2+^|0010011 <|SRLI 4+^|0100000 2+^|shamt 2+^|rs1 2+^|101 2+^|rd 2+^|0010011 <|SRAI 4+^|0000000 2+^|rs2 2+^|rs1 2+^|000 2+^|rd 2+^|0110011 <|ADD 4+^|0100000 2+^|rs2 2+^|rs1 2+^|000 2+^|rd 2+^|0110011 <|SUB 4+^|0000000 2+^|rs2 2+^|rs1 2+^|001 2+^|rd 2+^|0110011 <|SLL 4+^|0000000 2+^|rs2 2+^|rs1 2+^|010 2+^|rd 2+^|0110011 <|SLT 4+^|0000000 2+^|rs2 2+^|rs1 2+^|011 2+^|rd 2+^|0110011 <|SLTU 4+^|0000000 2+^|rs2 2+^|rs1 2+^|100 2+^|rd 2+^|0110011 <|XOR 4+^|0000000 2+^|rs2 2+^|rs1 2+^|101 2+^|rd 2+^|0110011 <|SRL 4+^|0100000 2+^|rs2 2+^|rs1 2+^|101 2+^|rd 2+^|0110011 <|SRA 4+^|0000000 2+^|rs2 2+^|rs1 2+^|110 2+^|rd 2+^|0110011 <|OR 4+^|0000000 2+^|rs2 2+^|rs1 2+^|111 2+^|rd 2+^|0110011 <|AND 3+^|fm 2+^|pred 1+^|succ 2+^|rs1 2+^|000 2+^|rd 2+^|0001111 <|FENCE 3+^|1000 2+^|0011 1+^|0011 2+^|00000 2+^|000 2+^|00000 2+^|0001111 <|FENCE.TSO 3+^|0000 2+^|0001 1+^|0000 2+^|00000 2+^|000 2+^|00000 2+^|0001111 <|PAUSE 6+^|000000000000 2+^|00000 2+^|000 2+^|00000 2+^|1110011 <|ECALL 6+^|000000000001 2+^|00000 2+^|000 2+^|00000 2+^|1110011 <|EBREAK |", + "section": "Preamble > RV32/64G Instruction Set Listings", + "line_range": [ + 58, + 103 + ] + }, + { + "text": "| 15+^| |31 |27 |26 |25 |24 | 20|19 | 15| 14 | 12|11 | 7|6 | 0| 4+^|funct7 2+^|rs2 2+^|rs1 2+^|funct3 2+^|rd 2+^|opcode <|R-type 6+^|imm[11:0] 2+^|rs1 2+^|funct3 2+^|rd 2+^|opcode <|I-type 4+^|imm[11:5] 2+^|rs2 2+^|rs1 2+^|funct3 2+^|imm[4:0] 2+^|opcode <|S-type |", + "section": "Preamble > RV32/64G Instruction Set Listings", + "line_range": [ + 107, + 114 + ] + }, + { + "text": "| 15+^|*RV64I Base Instruction Set (in addition to RV32I)* 6+^|imm[11:0] 2+^|rs1 2+^|110 2+^|rd 2+^|0000011 <|LWU 6+^|imm[11:0] 2+^|rs1 2+^|011 2+^|rd 2+^|0000011 <|LD 4+^|imm[11:5] 2+^|rs2 2+^|rs1 2+^|011 2+^|imm[4:0] 2+^|0100011 <|SD 3+^|000000 3+^|shamt 2+^|rs1 2+^|001 2+^|rd 2+^|0010011 <|SLLI 3+^|000000 3+^|shamt 2+^|rs1 2+^|101 2+^|rd 2+^|0010011 <|SRLI 3+^|010000 3+^|shamt 2+^|rs1 2+^|101 2+^|rd 2+^|0010011 <|SRAI 6+^|imm[11:0] 2+^|rs1 2+^|000 2+^|rd 2+^|0011011 <|ADDIW 4+^|0000000 2+^|shamt 2+^|rs1 2+^|001 2+^|rd 2+^|0011011 <|SLLIW 4+^|0000000 2+^|shamt 2+^|rs1 2+^|101 2+^|rd 2+^|0011011 <|SRLIW 4+^|0100000 2+^|shamt 2+^|rs1 2+^|101 2+^|rd 2+^|0011011 <|SRAIW 4+^|0000000 2+^|rs2 2+^|rs1 2+^|000 2+^|rd 2+^|0111011 <|ADDW 4+^|0100000 2+^|rs2 2+^|rs1 2+^|000 2+^|rd 2+^|0111011 <|SUBW 4+^|0000000 2+^|rs2 2+^|rs1 2+^|001 2+^|rd 2+^|0111011 <|SLLW 4+^|0000000 2+^|rs2 2+^|rs1 2+^|101 2+^|rd 2+^|0111011 <|SRLW 4+^|0100000 2+^|rs2 2+^|rs1 2+^|101 2+^|rd 2+^|0111011 <|SRAW | | 15+^|*RV32/RV64 Zifencei Standard Extension* 6+^|imm[11:0] 2+^|rs1 2+^|001 2+^|rd 2+^|0001111 <|FENCE.I |", + "section": "Preamble > RV32/64G Instruction Set Listings", + "line_range": [ + 116, + 139 + ] + }, + { + "text": "| 15+^|*RV32/RV64 Zicsr Standard Extension* 6+^|csr 2+^|rs1 2+^|001 2+^|rd 2+^|1110011 <|CSRRW 6+^|csr 2+^|rs1 2+^|010 2+^|rd 2+^|1110011 <|CSRRS 6+^|csr 2+^|rs1 2+^|011 2+^|rd 2+^|1110011 <|CSRRC 6+^|csr 2+^|uimm 2+^|101 2+^|rd 2+^|1110011 <|CSRRWI 6+^|csr 2+^|uimm 2+^|110 2+^|rd 2+^|1110011 <|CSRRSI 6+^|csr 2+^|uimm 2+^|111 2+^|rd 2+^|1110011 <|CSRRCI |", + "section": "Preamble > RV32/64G Instruction Set Listings", + "line_range": [ + 141, + 150 + ] + }, + { + "text": "| 15+^|*RV32M Standard Extension* 4+^|0000001 2+^|rs2 2+^|rs1 2+^|000 2+^|rd 2+^|0110011 <|MUL 4+^|0000001 2+^|rs2 2+^|rs1 2+^|001 2+^|rd 2+^|0110011 <|MULH 4+^|0000001 2+^|rs2 2+^|rs1 2+^|010 2+^|rd 2+^|0110011 <|MULHSU 4+^|0000001 2+^|rs2 2+^|rs1 2+^|011 2+^|rd 2+^|0110011 <|MULHU 4+^|0000001 2+^|rs2 2+^|rs1 2+^|100 2+^|rd 2+^|0110011 <|DIV 4+^|0000001 2+^|rs2 2+^|rs1 2+^|101 2+^|rd 2+^|0110011 <|DIVU 4+^|0000001 2+^|rs2 2+^|rs1 2+^|110 2+^|rd 2+^|0110011 <|REM 4+^|0000001 2+^|rs2 2+^|rs1 2+^|111 2+^|rd 2+^|0110011 <|REMU |", + "section": "Preamble > RV32/64G Instruction Set Listings", + "line_range": [ + 152, + 163 + ] + }, + { + "text": "| 15+^|*RV64M Standard Extension (in addition to RV32M)* 4+^|0000001 2+^|rs2 2+^|rs1 2+^|000 2+^|rd 2+^|0111011 <|MULW 4+^|0000001 2+^|rs2 2+^|rs1 2+^|100 2+^|rd 2+^|0111011 <|DIVW 4+^|0000001 2+^|rs2 2+^|rs1 2+^|101 2+^|rd 2+^|0111011 <|DIVUW 4+^|0000001 2+^|rs2 2+^|rs1 2+^|110 2+^|rd 2+^|0111011 <|REMW 4+^|0000001 2+^|rs2 2+^|rs1 2+^|111 2+^|rd 2+^|0111011 <|REMUW |", + "section": "Preamble > RV32/64G Instruction Set Listings", + "line_range": [ + 165, + 173 + ] + }, + { + "text": "| 15+^| |31 |27 |26 |25 |24 | 20|19 | 15| 14 | 12|11 | 7|6 | 0| 4+^|funct7 2+^|rs2 2+^|rs1 2+^|funct3 2+^|rd 2+^|opcode <|R-type |", + "section": "Preamble > RV32/64G Instruction Set Listings", + "line_range": [ + 177, + 182 + ] + }, + { + "text": "| 15+^|*RV32A Standard Extension* 2+^|00010 ^|aq ^|rl 2+^|00000 2+^|rs1 2+^|010 2+^|rd 2+^|0101111 <|LR.W 2+^|00011 ^|aq ^|rl 2+^|rs2 2+^|rs1 2+^|010 2+^|rd 2+^|0101111 <|SC.W 2+^|00001 ^|aq ^|rl 2+^|rs2 2+^|rs1 2+^|010 2+^|rd 2+^|0101111 <|AMOSWAP.W 2+^|00000 ^|aq ^|rl 2+^|rs2 2+^|rs1 2+^|010 2+^|rd 2+^|0101111 <|AMOADD.W 2+^|00100 ^|aq ^|rl 2+^|rs2 2+^|rs1 2+^|010 2+^|rd 2+^|0101111 <|AMOXOR.W 2+^|01100 ^|aq ^|rl 2+^|rs2 2+^|rs1 2+^|010 2+^|rd 2+^|0101111 <|AMOAND.W 2+^|01000 ^|aq ^|rl 2+^|rs2 2+^|rs1 2+^|010 2+^|rd 2+^|0101111 <|AMOOR.W 2+^|10000 ^|aq ^|rl 2+^|rs2 2+^|rs1 2+^|010 2+^|rd 2+^|0101111 <|AMOMIN.W 2+^|10100 ^|aq ^|rl 2+^|rs2 2+^|rs1 2+^|010 2+^|rd 2+^|0101111 <|AMOMAX.W 2+^|11000 ^|aq ^|rl 2+^|rs2 2+^|rs1 2+^|010 2+^|rd 2+^|0101111 <|AMOMINU.W 2+^|11100 ^|aq ^|rl 2+^|rs2 2+^|rs1 2+^|010 2+^|rd 2+^|0101111 <|AMOMAXU.W |", + "section": "Preamble > RV32/64G Instruction Set Listings", + "line_range": [ + 184, + 198 + ] + }, + { + "text": "| 15+^|*RV64A Standard Extension (in addition to RV32A)* 2+^|00010 ^|aq ^|rl 2+^|00000 2+^|rs1 2+^|011 2+^|rd 2+^|0101111 <|LR.D 2+^|00011 ^|aq ^|rl 2+^|rs2 2+^|rs1 2+^|011 2+^|rd 2+^|0101111 <|SC.D 2+^|00001 ^|aq ^|rl 2+^|rs2 2+^|rs1 2+^|011 2+^|rd 2+^|0101111 <|AMOSWAP.D 2+^|00000 ^|aq ^|rl 2+^|rs2 2+^|rs1 2+^|011 2+^|rd 2+^|0101111 <|AMOADD.D 2+^|00100 ^|aq ^|rl 2+^|rs2 2+^|rs1 2+^|011 2+^|rd 2+^|0101111 <|AMOXOR.D 2+^|01100 ^|aq ^|rl 2+^|rs2 2+^|rs1 2+^|011 2+^|rd 2+^|0101111 <|AMOAND.D 2+^|01000 ^|aq ^|rl 2+^|rs2 2+^|rs1 2+^|011 2+^|rd 2+^|0101111 <|AMOOR.D 2+^|10000 ^|aq ^|rl 2+^|rs2 2+^|rs1 2+^|011 2+^|rd 2+^|0101111 <|AMOMIN.D 2+^|10100 ^|aq ^|rl 2+^|rs2 2+^|rs1 2+^|011 2+^|rd 2+^|0101111 <|AMOMAX.D 2+^|11000 ^|aq ^|rl 2+^|rs2 2+^|rs1 2+^|011 2+^|rd 2+^|0101111 <|AMOMINU.D 2+^|11100 ^|aq ^|rl 2+^|rs2 2+^|rs1 2+^|011 2+^|rd 2+^|0101111 <|AMOMAXU.D |", + "section": "Preamble > RV32/64G Instruction Set Listings", + "line_range": [ + 200, + 214 + ] + }, + { + "text": "| |31 |27 |26 |25 |24 | 20|19 | 15| 14 | 12|11 | 7|6 | 0| 4+^|funct7 2+^|rs2 2+^|rs1 2+^|funct3 2+^|rd 2+^|opcode <|R-type 2+^|rs3 2+^|funct2 2+^|rs2 2+^|rs1 2+^|funct3 2+^|rd 2+^|opcode <|R4-type 6+^|imm[11:0] 2+^|rs1 2+^|funct3 2+^|rd 2+^|opcode <|I-type 4+^|imm[11:5] 2+^|rs2 2+^|rs1 2+^|funct3 2+^|imm[4:0] 2+^|opcode <|S-type |", + "section": "Preamble > RV32/64G Instruction Set Listings", + "line_range": [ + 218, + 225 + ] + }, + { + "text": "| 15+^|*RV32F Standard Extension* 6+^|imm[11:0] 2+^|rs1 2+^|010 2+^|rd 2+^|0000111 <|FLW 4+^|imm[11:5] 2+^|rs2 2+^|rs1 2+^|010 2+^|imm[4:0] 2+^|0100111 <|FSW 2+^|rs3 2+^|00 2+^|rs2 2+^|rs1 2+^|rm 2+^|rd 2+^|1000011 <|FMADD.S 2+^|rs3 2+^|00 2+^|rs2 2+^|rs1 2+^|rm 2+^|rd 2+^|1000111 <|FMSUB.S 2+^|rs3 2+^|00 2+^|rs2 2+^|rs1 2+^|rm 2+^|rd 2+^|1001011 <|FNMSUB.S 2+^|rs3 2+^|00 2+^|rs2 2+^|rs1 2+^|rm 2+^|rd 2+^|1001111 <|FNMADD.S 4+^|0000000 2+^|rs2 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FADD.S 4+^|0000100 2+^|rs2 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FSUB.S 4+^|0001000 2+^|rs2 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FMUL.S 4+^|0001100 2+^|rs2 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FDIV.S 4+^|0101100 2+^|00000 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FSQRT.S 4+^|0010000 2+^|rs2 2+^|rs1 2+^|000 2+^|rd 2+^|1010011 <|FSGNJ.S 4+^|0010000 2+^|rs2 2+^|rs1 2+^|001 2+^|rd 2+^|1010011 <|FSGNJN.S 4+^|0010000 2+^|rs2 2+^|rs1 2+^|010 2+^|rd 2+^|1010011 <|FSGNJX.S 4+^|0010100 2+^|rs2 2+^|rs1 2+^|000 2+^|rd 2+^|1010011 <|FMIN.S 4+^|0010100 2+^|rs2 2+^|rs1 2+^|001 2+^|rd 2+^|1010011 <|FMAX.S 4+^|1100000 2+^|00000 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FCVT.W.S 4+^|1100000 2+^|00001 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FCVT.WU.S 4+^|1110000 2+^|00000 2+^|rs1 2+^|000 2+^|rd 2+^|1010011 <|FMV.X.W 4+^|1010000 2+^|rs2 2+^|rs1 2+^|010 2+^|rd 2+^|1010011 <|FEQ.S 4+^|1010000 2+^|rs2 2+^|rs1 2+^|001 2+^|rd 2+^|1010011 <|FLT.S 4+^|1010000 2+^|rs2 2+^|rs1 2+^|000 2+^|rd 2+^|1010011 <|FLE.S 4+^|1110000 2+^|00000 2+^|rs1 2+^|001 2+^|rd 2+^|1010011 <|FCLASS.S 4+^|1101000 2+^|00000 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FCVT.S.W 4+^|1101000 2+^|00001 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FCVT.S.WU 4+^|1111000 2+^|00000 2+^|rs1 2+^|000 2+^|rd 2+^|1010011 <|FMV.W.X |", + "section": "Preamble > RV32/64G Instruction Set Listings", + "line_range": [ + 227, + 256 + ] + }, + { + "text": "| 15+^|*RV64F Standard Extension (in addition to RV32F)* 4+^|1100000 2+^|00010 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FCVT.L.S 4+^|1100000 2+^|00011 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FCVT.LU.S 4+^|1101000 2+^|00010 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FCVT.S.L 4+^|1101000 2+^|00011 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FCVT.S.LU |", + "section": "Preamble > RV32/64G Instruction Set Listings", + "line_range": [ + 258, + 265 + ] + }, + { + "text": "| |31 |27 |26 |25 |24 | 20|19 | 15| 14 | 12|11 | 7|6 | 0| 4+^|funct7 2+^|rs2 2+^|rs1 2+^|funct3 2+^|rd 2+^|opcode <|R-type 2+^|rs3 2+^|funct2 2+^|rs2 2+^|rs1 2+^|funct3 2+^|rd 2+^|opcode <|R4-type 6+^|imm[11:0] 2+^|rs1 2+^|funct3 2+^|rd 2+^|opcode <|I-type 4+^|imm[11:5] 2+^|rs2 2+^|rs1 2+^|funct3 2+^|imm[4:0] 2+^|opcode <|S-type |", + "section": "Preamble > RV32/64G Instruction Set Listings", + "line_range": [ + 269, + 276 + ] + }, + { + "text": "| 15+|*RV32D Standard Extension* 6+^|imm[11:0] 2+^|rs1 2+^|011 2+^|rd 2+^|0000111 <|FLD 4+^|imm[11:5] 2+^|rs2 2+^|rs1 2+^|011 2+^|imm[4:0] 2+^|0100111 <|FSD 2+^|rs3 2+^|01 2+^|rs2 2+^|rs1 2+^|rm 2+^|rd 2+^|1000011 <|FMADD.D 2+^|rs3 2+^|01 2+^|rs2 2+^|rs1 2+^|rm 2+^|rd 2+^|1000111 <|FMSUB.D 2+^|rs3 2+^|01 2+^|rs2 2+^|rs1 2+^|rm 2+^|rd 2+^|1001011 <|FNMSUB.D 2+^|rs3 2+^|01 2+^|rs2 2+^|rs1 2+^|rm 2+^|rd 2+^|1001111 <|FNMADD.D 4+^|0000001 2+^|rs2 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FADD.D 4+^|0000101 2+^|rs2 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FSUB.D 4+^|0001001 2+^|rs2 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FMUL.D 4+^|0001101 2+^|rs2 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FDIV.D 4+^|0101101 2+^|00000 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FSQRT.D 4+^|0010001 2+^|rs2 2+^|rs1 2+^|000 2+^|rd 2+^|1010011 <|FSGNJ.D 4+^|0010001 2+^|rs2 2+^|rs1 2+^|001 2+^|rd 2+^|1010011 <|FSGNJN.D 4+^|0010001 2+^|rs2 2+^|rs1 2+^|010 2+^|rd 2+^|1010011 <|FSGNJX.D 4+^|0010101 2+^|rs2 2+^|rs1 2+^|000 2+^|rd 2+^|1010011 <|FMIN.D 4+^|0010101 2+^|rs2 2+^|rs1 2+^|001 2+^|rd 2+^|1010011 <|FMAX.D 4+^|0100000 2+^|00001 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FCVT.S.D 4+^|0100001 2+^|00000 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FCVT.D.S 4+^|1010001 2+^|rs2 2+^|rs1 2+^|010 2+^|rd 2+^|1010011 <|FEQ.D 4+^|1010001 2+^|rs2 2+^|rs1 2+^|001 2+^|rd 2+^|1010011 <|FLT.D 4+^|1010001 2+^|rs2 2+^|rs1 2+^|000 2+^|rd 2+^|1010011 <|FLE.D 4+^|1110001 2+^|00000 2+^|rs1 2+^|001 2+^|rd 2+^|1010011 <|FCLASS.D 4+^|1100001 2+^|00000 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FCVT.W.D 4+^|1100001 2+^|00001 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FCVT.WU.D 4+^|1101001 2+^|00000 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FCVT.D.W 4+^|1101001 2+^|00001 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FCVT.D.WU |", + "section": "Preamble > RV32/64G Instruction Set Listings", + "line_range": [ + 278, + 307 + ] + }, + { + "text": "| 15+^|*RV64D Standard Extension (in addition to RV32D)* 4+^|1100001 2+^|00010 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FCVT.L.D 4+^|1100001 2+^|00011 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FCVT.LU.D 4+^|1110001 2+^|00000 2+^|rs1 2+^|000 2+^|rd 2+^|1010011 <|FMV.X.D 4+^|1101001 2+^|00010 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FCVT.D.L 4+^|1101001 2+^|00011 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FCVT.D.LU 4+^|1111001 2+^|00000 2+^|rs1 2+^|000 2+^|rd 2+^|1010011 <|FMV.D.X |", + "section": "Preamble > RV32/64G Instruction Set Listings", + "line_range": [ + 309, + 318 + ] + }, + { + "text": "| 15+^| |31 |27 |26 |25 |24 | 20|19 | 15| 14 | 12|11 | 7|6 | 0| 4+^|funct7 2+^|rs2 2+^|rs1 2+^|funct3 2+^|rd 2+^|opcode <|R-type 2+^|rs3 2+^|funct2 2+^|rs2 2+^|rs1 2+^|funct3 2+^|rd 2+^|opcode <|R4-type 6+^|imm[11:0] 2+^|rs1 2+^|funct3 2+^|rd 2+^|opcode <|I-type 4+^|imm[11:5] 2+^|rs2 2+^|rs1 2+^|funct3 2+^|imm[4:0] 2+^|opcode <|S-type |", + "section": "Preamble > RV32/64G Instruction Set Listings", + "line_range": [ + 322, + 330 + ] + }, + { + "text": "| 15+^|*RV32Q Standard Extension* 4+^|imm[11:0] 2+^| 2+^|rs1 2+^|100 2+^|rd 2+^|0000111 <|FLQ 4+^|imm[11:5] 2+^|rs2 2+^|rs1 2+^|100 2+^|imm[4:0] 2+^|0100111 <|FSQ 2+^|rs3 2+^|11 2+^|rs2 2+^|rs1 2+^|rm 2+^|rd 2+^|1000011 <|FMADD.Q 2+^|rs3 2+^|11 2+^|rs2 2+^|rs1 2+^|rm 2+^|rd 2+^|1000111 <|FMSUB.Q 2+^|rs3 2+^|11 2+^|rs2 2+^|rs1 2+^|rm 2+^|rd 2+^|1001011 <|FNMSUB.Q 2+^|rs3 2+^|11 2+^|rs2 2+^|rs1 2+^|rm 2+^|rd 2+^|1001111 <|FNMADD.Q 4+^|0000011 2+^|rs2 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FADD.Q 4+^|0000111 2+^|rs2 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FSUB.Q 4+^|0001011 2+^|rs2 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FMUL.Q 4+^|0001111 2+^|rs2 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FDIV.Q 4+^|0101111 2+^|00000 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FSQRT.Q 4+^|0010011 2+^|rs2 2+^|rs1 2+^|000 2+^|rd 2+^|1010011 <|FSGNJ.Q 4+^|0010011 2+^|rs2 2+^|rs1 2+^|001 2+^|rd 2+^|1010011 <|FSGNJN.Q 4+^|0010011 2+^|rs2 2+^|rs1 2+^|010 2+^|rd 2+^|1010011 <|FSGNJX.Q 4+^|0010111 2+^|rs2 2+^|rs1 2+^|000 2+^|rd 2+^|1010011 <|FMIN.Q 4+^|0010111 2+^|rs2 2+^|rs1 2+^|001 2+^|rd 2+^|1010011 <|FMAX.Q 4+^|0100000 2+^|00011 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FCVT.S.Q 4+^|0100011 2+^|00000 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FCVT.Q.S 4+^|0100001 2+^|00011 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FCVT.D.Q 4+^|0100011 2+^|00001 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FCVT.Q.D 4+^|1010011 2+^|rs2 2+^|rs1 2+^|010 2+^|rd 2+^|1010011 <|FEQ.Q 4+^|1010011 2+^|rs2 2+^|rs1 2+^|001 2+^|rd 2+^|1010011 <|FLT.Q 4+^|1010011 2+^|rs2 2+^|rs1 2+^|000 2+^|rd 2+^|1010011 <|FLE.Q 4+^|1110011 2+^|00000 2+^|rs1 2+^|001 2+^|rd 2+^|1010011 <|FCLASS.Q 4+^|1100011 2+^|00000 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FCVT.W.Q 4+^|1100011 2+^|00001 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FCVT.WU.Q 4+^|1101011 2+^|00000 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FCVT.Q.W 4+^|1101011 2+^|00001 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FCVT.Q.WU |", + "section": "Preamble > RV32/64G Instruction Set Listings", + "line_range": [ + 332, + 363 + ] + }, + { + "text": "| 15+^|*RV64Q Standard Extension (in addition to RV32Q)* 4+^|1100011 2+^|00010 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FCVT.L.Q 4+^|1100011 2+^|00011 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FCVT.LU.Q 4+^|1101011 2+^|00010 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FCVT.Q.L 4+^|1101011 2+^|00011 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FCVT.Q.LU |", + "section": "Preamble > RV32/64G Instruction Set Listings", + "line_range": [ + 365, + 372 + ] + }, + { + "text": "| 15+^| |31 |27 |26 |25 |24 | 20|19 | 15| 14 | 12|11 | 7|6 | 0| 4+^|funct7 2+^|rs2 2+^|rs1 2+^|funct3 2+^|rd 2+^|opcode <|R-type 2+^|rs3 2+^|funct2 2+^|rs2 2+^|rs1 2+^|funct3 2+^|rd 2+^|opcode <|R4-type 6+^|imm[11:0] 2+^|rs1 2+^|funct3 2+^|rd 2+^|opcode <|I-type 4+^|imm[11:5] 2+^|rs2 2+^|rs1 2+^|funct3 2+^|imm[4:0] 2+^|opcode <|S-type |", + "section": "Preamble > RV32/64G Instruction Set Listings", + "line_range": [ + 376, + 384 + ] + }, + { + "text": "| 8+|RV32Zfh Standard Extension 3+|imm[11:0] |rs1 |001 |rd |0000111 |FLH 2+|imm[11:5] |rs2 |rs1 |001 |imm[4:0] |0100111 |FSH |rs3 |10 |rs2 |rs1 |rm |rd |1000011 |FMADD.H |rs3 |10 |rs2 |rs1 |rm |rd |1000111 |FMSUB.H |rs3 |10 |rs2 |rs1 |rm |rd |1001011 |FNMSUB.H |rs3 |10 |rs2 |rs1 |rm |rd |1001111 |FNMADD.H 2+|0000010 |rs2 |rs1 |rm |rd |1010011 |FADD.H 2+|0000110 |rs2 |rs1 |rm |rd |1010011 |FSUB.H 2+|0001010 |rs2 |rs1 |rm |rd |1010011 |FMUL.H 2+|0001110 |rs2 |rs1 |rm |rd |1010011 |FDIV.H 2+|0101110 |00000 |rs1 |rm |rd |1010011 |FSQRT.H 2+|0010010 |rs2 |rs1 |000 |rd |1010011 |FSGNJ.H 2+|0010010 |rs2 |rs1 |001 |rd |1010011 |FSGNJN.H 2+|0010010 |rs2 |rs1 |010 |rd |1010011 |FSGNJX.H 2+|0010110 |rs2 |rs1 |000 |rd |1010011 |FMIN.H 2+|0010110 |rs2 |rs1 |001 |rd |1010011 |FMAX.H 2+|0100000 |00010 |rs1 |rm |rd |1010011 |FCVT.S.H 2+|0100010 |00000 |rs1 |rm |rd |1010011 |FCVT.H.S 2+|0100001 |00010 |rs1 |rm |rd |1010011 |FCVT.D.H 2+|0100010 |00001 |rs1 |rm |rd |1010011 |FCVT.H.D 2+|0100011 |00010 |rs1 |rm |rd |1010011 |FCVT.Q.H 2+|0100010 |00011 |rs1 |rm |rd |1010011 |FCVT.H.Q 2+|1010010 |rs2 |rs1 |010 |rd |1010011 |FEQ.H 2+|1010010 |rs2 |rs1 |001 |rd |1010011 |FLT.H 2+|1010010 |rs2 |rs1 |000 |rd |1010011 |FLE.H 2+|1110010 |00000 |rs1 |001 |rd |1010011 |FCLASS.H 2+|1100010 |00000 |rs1 |rm |rd |1010011 |FCVT.W.H 2+|1100010 |00001 |rs1 |rm |rd |1010011 |FCVT.WU.H 2+|1110010 |00000 |rs1 |000 |rd |1010011 |FMV.X.H 2+|1101010 |00000 |rs1 |rm |rd |1010011 |FCVT.H.W 2+|1101010 |00001 |rs1 |rm |rd |1010011 |FCVT.H.WU 2+|1111010 |00000 |rs1 |000 |rd |1010011 |FMV.H.X |", + "section": "Preamble > RV32/64G Instruction Set Listings", + "line_range": [ + 386, + 421 + ] + }, + { + "text": "| 8+|RV64Zfh Standard Extension (in addition to RV32Zfh) 2+|1100010 |00010 |rs1 |rm |rd |1010011 |FCVT.L.H 2+|1100010 |00011 |rs1 |rm |rd |1010011 |FCVT.LU.H 2+|1101010 |00010 |rs1 |rm |rd |1010011 |FCVT.H.L 2+|1101010 |00011 |rs1 |rm |rd |1010011 |FCVT.H.LU |", + "section": "Preamble > RV32/64G Instruction Set Listings", + "line_range": [ + 423, + 430 + ] + }, + { + "text": "| 15+^|Zawrs Standard Extension", + "section": "Preamble > RV32/64G Instruction Set Listings", + "line_range": [ + 432, + 434 + ] + }, + { + "text": "6+^|000000001101 2+^|00000 2+^|000 2+^|00000 2+^|1110011 <|WRS.NTO 6+^|000000011101 2+^|00000 2+^|000 2+^|00000 2+^|1110011 <|WRS.STO |", + "section": "Preamble > RV32/64G Instruction Set Listings", + "line_range": [ + 436, + 438 + ] + }, + { + "text": "lists the CSRs that have currently been allocated CSR addresses.", + "section": "Preamble > RV32/64G Instruction Set Listings", + "line_range": [ + 440, + 442 + ] + }, + { + "text": "The timers, counters, and floating-point CSRs are the only CSRs defined in this specification.", + "section": "Preamble > RV32/64G Instruction Set Listings", + "line_range": [ + 440, + 442 + ] + }, + { + "text": ".RISC-V control and status register (CSR) address map. | |Number|Privilege|Name|Description 4+^|Floating-Point Control and Status Registers |0x001|Read write|fflags|Floating-Point Accrued Exceptions. |0x002|Read write|frm|Floating-Point Dynamic Rounding Mode. |0x003|Read write|fcsr|Floating-Point Control and Status Register (`frm` + `fflags`). 4+^|Counters and Timers |0xC00|Read-only|cycle|Cycle counter for RDCYCLE instruction. |0xC01|Read-only|time|Timer for RDTIME instruction. |0xC02|Read-only|instret|Instructions-retired counter for RDINSTRET instruction. |0xC80|Read-only|cycleh|Upper 32 bits of `cycle`, RV32I only. |0xC81|Read-only|timeh|Upper 32 bits of `time`, RV32I only. |0xC82|Read-only|instreth|Upper 32 bits of `instret`, RV32I only. |", + "section": "Preamble > RV32/64G Instruction Set Listings", + "line_range": [ + 444, + 460 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__unpriv__rvwmo.json b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__rvwmo.json new file mode 100644 index 0000000000..7acc671ef7 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__rvwmo.json @@ -0,0 +1,1342 @@ +{ + "source_file": "src/unpriv/rvwmo.adoc", + "total": 167, + "sentences": [ + { + "text": "This chapter defines the RISC-V memory consistency model. A memory consistency model is a set of rules specifying the values that can be returned by loads of memory. RISC-V uses a memory model called RISC-V Weak Memory Ordering (RVWMO) which is designed to provide flexibility for architects to build high-performance scalable designs while simultaneously supporting a tractable programming model.", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0", + "line_range": [ + 3, + 10 + ] + }, + { + "text": "Under RVWMO, code running on a single hart appears to execute in order from the perspective of other memory instructions in the same hart, but memory instructions from another hart may observe the memory instructions from the first hart being executed in a different order.", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0", + "line_range": [ + 12, + 20 + ] + }, + { + "text": "Therefore, multithreaded code may require explicit synchronization to guarantee ordering between memory instructions from different harts.", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0", + "line_range": [ + 12, + 20 + ] + }, + { + "text": "The base RISC-V ISA provides a FENCE instruction for this purpose, described in , while the atomics extension \"A\" additionally defines load-reserved/store-conditional and atomic read-modify-write instructions.", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0", + "line_range": [ + 12, + 20 + ] + }, + { + "text": "The standard ISA extension for total store ordering \"Ztso\" () augments RVWMO with additional rules specific to those extensions.", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0", + "line_range": [ + 22, + 23 + ] + }, + { + "text": "The appendices to this specification provide both axiomatic and operational formalizations of the memory consistency model as well as additional explanatory material.", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0", + "line_range": [ + 25, + 29 + ] + }, + { + "text": "The RVWMO memory model is defined in terms of the global memory order, a total ordering of the memory operations produced by all harts.", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model", + "line_range": [ + 34, + 38 + ] + }, + { + "text": "In general, a multithreaded program has many different possible executions, with each execution having its own corresponding global memory order.", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model", + "line_range": [ + 34, + 38 + ] + }, + { + "text": "The global memory order is defined over the primitive load and store operations generated by memory instructions.", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model", + "line_range": [ + 40, + 44 + ] + }, + { + "text": "It is then subject to the constraints defined in the rest of this chapter.", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model", + "line_range": [ + 40, + 44 + ] + }, + { + "text": "Any execution satisfying all of the memory model constraints is a legal execution (as far as the memory model is concerned).", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model", + "line_range": [ + 40, + 44 + ] + }, + { + "text": "The program order over memory operations reflects the order in which the instructions that generate each load and store are logically laid out in that hart's dynamic instruction stream; i.e., the order in which a simple in-order processor would execute the instructions of that hart.", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives", + "line_range": [ + 49, + 52 + ] + }, + { + "text": "Memory-accessing instructions give rise to memory operations. A memory operation can be either a load operation, a store operation, or both simultaneously.", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives", + "line_range": [ + 54, + 59 + ] + }, + { + "text": "All memory operations are single-copy atomic: they can never be observed in a partially complete state.", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives", + "line_range": [ + 54, + 59 + ] + }, + { + "text": "Each aligned memory instruction that accesses XLEN or fewer bits gives rise to exactly one memory operation, unless specified otherwise.", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives", + "line_range": [ + 61, + 64 + ] + }, + { + "text": "An aligned AMO gives rise to a single memory operation that is both a load operation and a store operation simultaneously.", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives", + "line_range": [ + 61, + 64 + ] + }, + { + "text": "A misaligned load or store instruction may be decomposed into a set of component memory operations of any granularity. A floating-point load or store of more than XLEN bits may also be decomposed into a set of component memory operations of any granularity.", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives", + "line_range": [ + 66, + 80 + ] + }, + { + "text": "The memory operations generated by such instructions are not ordered with respect to each other in program order, but they are ordered normally with respect to the memory operations generated by preceding and subsequent instructions in program order.", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives", + "line_range": [ + 66, + 80 + ] + }, + { + "text": "The atomics extension \"A\" does not require execution environments to support misaligned atomic instructions at all.", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives", + "line_range": [ + 66, + 80 + ] + }, + { + "text": "However, if misaligned atomics are supported via the misaligned atomicity granule PMA, then AMOs within an atomicity granule are not decomposed, nor are loads and stores defined in the base ISAs, nor are loads and stores of no more than XLEN bits defined in the F, D, and Q extensions.", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives", + "line_range": [ + 66, + 80 + ] + }, + { + "text": "An LR instruction and an SC instruction are said to be paired if the LR precedes the SC in program order and if there are no other LR or SC instructions in between; the corresponding memory operations are said to be paired as well (except in case of a failed SC, where no store operation is generated).", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives", + "line_range": [ + 82, + 88 + ] + }, + { + "text": "The complete list of conditions determining whether an SC must succeed, may succeed, or must fail is defined in .", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives", + "line_range": [ + 82, + 88 + ] + }, + { + "text": "Load and store operations may also carry one or more ordering annotations from the following set: \"acquire-RCpc\", \"acquire-RCsc\", \"release-RCpc\", and \"release-RCsc\".", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives", + "line_range": [ + 90, + 96 + ] + }, + { + "text": "An AMO or LR instruction with aq set has an \"acquire-RCsc\" annotation.", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives", + "line_range": [ + 90, + 96 + ] + }, + { + "text": "An AMO or SC instruction with rl set has a \"release-RCsc\" annotation.", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives", + "line_range": [ + 90, + 96 + ] + }, + { + "text": "An AMO, LR, or SC instruction with both aq and rl set has both \"acquire-RCsc\" and \"release-RCsc\" annotations.", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives", + "line_range": [ + 90, + 96 + ] + }, + { + "text": "For convenience, we use the term \"acquire annotation\" to refer to an acquire-RCpc annotation or an acquire-RCsc annotation.", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives", + "line_range": [ + 98, + 104 + ] + }, + { + "text": "Likewise, a \"release annotation\" refers to a release-RCpc annotation or a release-RCsc annotation.", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives", + "line_range": [ + 98, + 104 + ] + }, + { + "text": "An \"RCpc annotation\" refers to an acquire-RCpc annotation or a release-RCpc annotation.", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives", + "line_range": [ + 98, + 104 + ] + }, + { + "text": "An RCsc annotation refers to an acquire-RCsc annotation or a release-RCsc annotation.", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives", + "line_range": [ + 98, + 104 + ] + }, + { + "text": "The definition of the RVWMO memory model depends in part on the notion of a syntactic dependency, defined as follows.", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives > Syntactic Dependencies", + "line_range": [ + 109, + 110 + ] + }, + { + "text": "In the context of defining dependencies, a register refers either to an entire general-purpose register, some portion of a CSR, or an entire CSR.", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives > Syntactic Dependencies", + "line_range": [ + 112, + 116 + ] + }, + { + "text": "The granularity at which dependencies are tracked through CSRs is specific to each CSR and is defined in .", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives > Syntactic Dependencies", + "line_range": [ + 112, + 116 + ] + }, + { + "text": "Syntactic dependencies are defined in terms of instructions' source registers, instructions' destination registers, and the way instructions carry a dependency from their source registers to their destination registers.", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives > Syntactic Dependencies", + "line_range": [ + 118, + 123 + ] + }, + { + "text": "This section provides a general definition of all of these terms; however, provides a complete listing of the specifics for each instruction.", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives > Syntactic Dependencies", + "line_range": [ + 118, + 123 + ] + }, + { + "text": "In general, a register r other than `x0` is a source register for an instruction i if any of the following hold:", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives > Syntactic Dependencies", + "line_range": [ + 125, + 127 + ] + }, + { + "text": "In the opcode of i, rs1, rs2, or rs3 is set to r * i is a CSR instruction, and in the opcode of i, csr is set to r, unless i is CSRRW or CSRRWI and rd is set to `x0` * r is a CSR and an implicit source register for i, as defined in * r is a CSR that aliases with another source register for i", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives > Syntactic Dependencies", + "line_range": [ + 129, + 137 + ] + }, + { + "text": "Memory instructions also further specify which source registers are address source registers and which are data source registers.", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives > Syntactic Dependencies", + "line_range": [ + 139, + 140 + ] + }, + { + "text": "In general, a register r other than `x0` is a destination register for an instruction i if any of the following hold:", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives > Syntactic Dependencies", + "line_range": [ + 142, + 144 + ] + }, + { + "text": "In the opcode of i, rd is set to r * i is a CSR instruction, and in the opcode of i, csr is set to r, unless i is CSRRS or CSRRC and rs1 is set to `x0` or i is CSRRSI or CSRRCI and uimm[4:0] is set to zero. * r is a CSR and an implicit destination register for i, as defined in * r is a CSR that aliases with another destination register for i", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives > Syntactic Dependencies", + "line_range": [ + 146, + 154 + ] + }, + { + "text": "Most non-memory instructions carry a dependency from each of their source registers to each of their destination registers.", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives > Syntactic Dependencies", + "line_range": [ + 156, + 158 + ] + }, + { + "text": "However, there are exceptions to this rule; see .", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives > Syntactic Dependencies", + "line_range": [ + 156, + 158 + ] + }, + { + "text": "Instruction j has a syntactic dependency on instruction i via destination register s of i and source register r of j if either of the following hold:", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives > Syntactic Dependencies", + "line_range": [ + 160, + 163 + ] + }, + { + "text": "s is the same as r, and no instruction program-ordered between i and j has r as a destination register * There is an instruction m program-ordered between i and j such that all of the following hold: . j has a syntactic dependency on m via destination register q and source register r . m has a syntactic dependency on i via destination register s and source register p . m carries a dependency from p to q", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives > Syntactic Dependencies", + "line_range": [ + 165, + 175 + ] + }, + { + "text": "Finally, in the definitions that follow, let a and b be two memory operations, and let i and j be the instructions that generate a and b, respectively.", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives > Syntactic Dependencies", + "line_range": [ + 177, + 180 + ] + }, + { + "text": "b has a syntactic address dependency on a if r is an address source register for j and j has a syntactic dependency on i via source register r", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives > Syntactic Dependencies", + "line_range": [ + 182, + 185 + ] + }, + { + "text": "b has a syntactic data dependency on a if b is a store operation, r is a data source register for j, and j has a syntactic dependency on i via source register r", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives > Syntactic Dependencies", + "line_range": [ + 187, + 190 + ] + }, + { + "text": "b has a syntactic control dependency on a if there is an instruction m program-ordered between i and j such that m is a branch or indirect jump and m has a syntactic dependency on i.", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives > Syntactic Dependencies", + "line_range": [ + 192, + 196 + ] + }, + { + "text": "The global memory order for any given execution of a program respects some but not all of each hart’s program order.", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives > Preserved Program Order", + "line_range": [ + 200, + 204 + ] + }, + { + "text": "The subset of program order that must be respected by the global memory order is known as preserved program order.", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives > Preserved Program Order", + "line_range": [ + 200, + 204 + ] + }, + { + "text": "The complete definition of preserved program order is as follows (and note that AMOs are simultaneously both loads and stores): memory operation a precedes memory operation b in preserved program order (and hence also in the global memory order) if a precedes b in program order, a and b both access regular main memory (rather than I/O regions), and any of the following hold:", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives > Preserved Program Order", + "line_range": [ + 206, + 213 + ] + }, + { + "text": "* Overlapping-Address Orderings: . b is a store, and a and b access overlapping memory addresses . a and b are loads, x is a byte read by both a and b, there is no store to x between a and b in program order, and a and b return values for x written by different memory operations . a is generated by an AMO or SC instruction, b is a load, and b returns a value written by a * Explicit Synchronization: [start=4] .", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives > Preserved Program Order", + "line_range": [ + 215, + 241 + ] + }, + { + "text": "There is a FENCE instruction that orders a before b . a has an acquire annotation annotation . b has a release annotation . a and b both have RCsc annotations . a is paired with b * Syntactic Dependencies: [start=9] . b has a syntactic address dependency on a . b has a syntactic data dependency on a . b is a store, and b has a syntactic control dependency on a * Pipeline Dependencies: [start=12] . b is a load, and there exists some store m between a and b in program order such that m has an address or data dependency on a, and b returns a value written by m . b is a store, and there exists some instruction m between a and b in program order such that m has an address dependency on a", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives > Preserved Program Order", + "line_range": [ + 215, + 241 + ] + }, + { + "text": "An execution of a RISC-V program obeys the RVWMO memory consistency model only if there exists a global memory order conforming to preserved program order and satisfying the load value axiom, the atomicity axiom, and the progress axiom.", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives > Memory Model Axioms", + "line_range": [ + 244, + 248 + ] + }, + { + "text": "Each byte of each load i returns the value written to that byte by the store that is the latest in global memory order among the following stores:", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives > Memory Model Axioms > Load Value Axiom", + "line_range": [ + 253, + 256 + ] + }, + { + "text": "Stores that write that byte and that precede i in the global memory order .", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives > Memory Model Axioms > Load Value Axiom", + "line_range": [ + 258, + 262 + ] + }, + { + "text": "Stores that write that byte and that precede i in program order", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives > Memory Model Axioms > Load Value Axiom", + "line_range": [ + 258, + 262 + ] + }, + { + "text": "If r and w are paired load and store operations generated by aligned LR and SC instructions in a hart h, s is a store to byte x, and r returns a value written by s, then s must precede w in the global memory order, and there can be no store from a hart other than h to byte x following s and preceding w in the global memory order.", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives > Memory Model Axioms > Atomicity Axiom", + "line_range": [ + 267, + 276 + ] + }, + { + "text": "No memory operation may be preceded in the global memory order by an infinite sequence of other memory operations.", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Memory Model Primitives > Memory Model Axioms > Progress Axiom", + "line_range": [ + 279, + 281 + ] + }, + { + "text": ".Granularities at which syntactic dependencies are tracked through CSRs | |Name |Portions Tracked as Independent Units |Aliases |fflags |Bits 4, 3, 2, 1, 0 |fcsr |frm |entire CSR |fcsr |fcsr |Bits 7-5, 4, 3, 2, 1, 0 |fflags, frm |", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > CSR Dependency Tracking Granularity", + "line_range": [ + 286, + 293 + ] + }, + { + "text": "Note: read-only CSRs are not listed, as they do not participate in the definition of syntactic dependencies.", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > CSR Dependency Tracking Granularity", + "line_range": [ + 295, + 296 + ] + }, + { + "text": "This section provides a concrete listing of the source and destination registers for each instruction.", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 301, + 304 + ] + }, + { + "text": "These listings are used in the definition of syntactic dependencies in .", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 301, + 304 + ] + }, + { + "text": "The term \"accumulating CSR\" is used to describe a CSR that is both a source and a destination register, but which carries a dependency only from itself to itself.", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 306, + 308 + ] + }, + { + "text": "Instructions carry a dependency from each source register in the \"Source Registers\" column to each destination register in the \"Destination Registers\" column, from each source register in the \"Source Registers\" column to each CSR in the \"Accumulating CSRs\" column, and from each CSR in the \"Accumulating CSRs\" column to itself, except where annotated otherwise.", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 310, + 315 + ] + }, + { + "text": "^A^Address source register", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 319, + 319 + ] + }, + { + "text": "† The instruction does not carry a dependency from any source register to any destination register", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 323, + 324 + ] + }, + { + "text": "‡ The instruction carries dependencies from source register(s) to destination register(s) as specified", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 326, + 327 + ] + }, + { + "text": ".RV32I Base Integer Instruction Set | ||Source Registers |Destination Registers|Accumulating CSRs|", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 329, + 332 + ] + }, + { + "text": "|SB |rs1 ^A^, rs2 ^D^ | ||", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 364, + 364 + ] + }, + { + "text": "|SH |rs1 ^A^, rs2 ^D^ | ||", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 366, + 366 + ] + }, + { + "text": "|SW |rs1 ^A^, rs2 ^D^ | ||", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 368, + 368 + ] + }, + { + "text": "|CSRRW‡ |rs1, csr^*^ | rd, csr | |^*^unless rd=`x0`", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 416, + 416 + ] + }, + { + "text": "5+| ‡ carries a dependency from rs1 to csr and from csr to rd", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 418, + 418 + ] + }, + { + "text": "|CSRRS‡ |rs1, csr |rd, csr^*^ | |^*^unless rs1=`x0`", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 420, + 420 + ] + }, + { + "text": "|CSRRC‡ |rs1, csr |rd, csr^*^ | |^*^unless rs1=`x0`", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 422, + 422 + ] + }, + { + "text": "5+| ‡ carries a dependency from csr and rs1 to csr and from csr to rd", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 424, + 424 + ] + }, + { + "text": "|CSRRWI ‡ |csr ^*^ |rd, csr | |^*^unless rd=x0", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 426, + 426 + ] + }, + { + "text": "5+| ‡ carries a dependency from csr to rd", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 428, + 428 + ] + }, + { + "text": "|CSRRSI ‡ |csr |rd, csr^*^ | |^*^unless uimm[4:0]=0", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 430, + 430 + ] + }, + { + "text": "|CSRRCI ‡ |csr |rd, csr^*^ | |^*^unless uimm[4:0]=0", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 432, + 432 + ] + }, + { + "text": "5+| ‡ carries a dependency from csr to rd and csr |", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 434, + 435 + ] + }, + { + "text": ".RV64I Base Integer Instruction Set | | |Source Registers |Destination Registers |Accumulating CSRs|", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 437, + 440 + ] + }, + { + "text": "|SD |rs1 ^A^, rs2 ^D^ | | |", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 446, + 446 + ] + }, + { + "text": ".RV32M Standard Extension | | |Source Registers |Destination Registers |Accumulating CSRs|", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 473, + 476 + ] + }, + { + "text": ".RV64M Standard Extension | ||Source Registers |Destination Registers |Accumulating CSRs|", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 495, + 498 + ] + }, + { + "text": ".RV32A Standard Extension | ||Source Registers |Destination Registers |Accumulating CSRs|", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 511, + 514 + ] + }, + { + "text": "|SC.W† | rs1 ^A^, rs2 ^D^ | rd ^*^ | | ^*^ if successful", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 518, + 518 + ] + }, + { + "text": "|AMOSWAP.W† |rs1 ^A^, rs2 ^D^ |rd | |", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 520, + 520 + ] + }, + { + "text": "|AMOADD.W† |rs1 ^A^, rs2 ^D^ |rd | |", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 522, + 522 + ] + }, + { + "text": "|AMOXOR.W† |rs1 ^A^, rs2 ^D^ |rd | |", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 524, + 524 + ] + }, + { + "text": "|AMOAND.W† |rs1 ^A^, rs2 ^D^ |rd | |", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 526, + 526 + ] + }, + { + "text": "|AMOOR.W† |rs1 ^A^, rs2^D^ |rd | |", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 528, + 528 + ] + }, + { + "text": "|AMOMIN.W† |rs1 ^A^, rs2 ^D^ |rd | |", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 530, + 530 + ] + }, + { + "text": "|AMOMAX.W† |rs1 ^A^, rs2 ^D^ |rd | |", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 532, + 532 + ] + }, + { + "text": "|AMOMINU.W† |rs1 ^A^, rs2 ^D^ |rd | |", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 534, + 534 + ] + }, + { + "text": "|AMOMAXU.W† |rs1 ^A^, rs2 ^D^ |rd | |", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 536, + 536 + ] + }, + { + "text": ".RV64A Standard Extension |", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 540, + 542 + ] + }, + { + "text": "| |Source Registers |Destination Registers |Accumulating CSRs|", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 544, + 544 + ] + }, + { + "text": "|SC.D† |rs1 ^A^, rs2 ^D^ |rd ^*^ | |^*^if successful", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 548, + 548 + ] + }, + { + "text": "|AMOSWAP.D† |rs1 ^A^, rs2 ^D^ |rd | |", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 550, + 550 + ] + }, + { + "text": "|AMOADD.D† |rs1 ^A^, rs2 ^D^ |rd | |", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 552, + 552 + ] + }, + { + "text": "|AMOXOR.D† |rs1 ^A^, rs2 ^D^ |rd | |", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 554, + 554 + ] + }, + { + "text": "|AMOAND.D† |rs1 ^A^, rs2^D^ |rd | |", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 556, + 556 + ] + }, + { + "text": "|AMOOR.D† |rs1 ^A^, rs2^D^ |rd | |", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 558, + 558 + ] + }, + { + "text": "|AMOMIN.D† |rs1 ^A^, rs2^D^ |rd | |", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 560, + 560 + ] + }, + { + "text": "|AMOMAX.D† |rs1 ^A^, rs2^D^ |rd | |", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 562, + 562 + ] + }, + { + "text": "|AMOMINU.D† |rs1 ^A^, rs2^D^ |rd | |", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 564, + 564 + ] + }, + { + "text": "|AMOMAXU.D† |rs1 ^A^, rs2^D^ |rd | |", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 566, + 566 + ] + }, + { + "text": ".RV32F Standard Extension |", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 570, + 572 + ] + }, + { + "text": "| |Source Registers |Destination Registers |Accumulating CSRs |", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 574, + 574 + ] + }, + { + "text": "|FSW |rs1 ^A^, rs2^D^ | | |", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 578, + 578 + ] + }, + { + "text": "|FMADD.S |rs1, rs2, rs3, frm^*^ |rd |NV, OF, UF, NX |^*^if rm=111", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 580, + 580 + ] + }, + { + "text": "|FMSUB.S |rs1, rs2, rs3, frm^*^ |rd |NV, OF, UF, NX |^*^if rm=111", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + 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> Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 590, + 590 + ] + }, + { + "text": "|FMUL.S |rs1, rs2, frm^*^ |rd |NV, OF, UF, NX |^*^if rm=111", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 592, + 592 + ] + }, + { + "text": "|FDIV.S |rs1, rs2, frm^*^ |rd |NV, DZ, OF, UF, NX |^*^if rm=111", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 594, + 594 + ] + }, + { + "text": "|FSQRT.S |rs1, frm^*^ |rd |NV, NX |^*^if rm=111", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 596, + 596 + ] + }, + { + "text": "|FSGNJ.S |rs1, rs2 |rd | |", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 598, + 598 + ] + }, + { + "text": "|FSGNJN.S |rs1, rs2 |rd | |", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 600, + 600 + ] + }, + { + "text": "|FSGNJX.S |rs1, rs2 |rd | |", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 602, + 602 + ] + }, + { + "text": "|FMIN.S |rs1, rs2 |rd |NV |", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 604, + 604 + ] + }, + { + "text": "|FMAX.S |rs1, rs2 |rd |NV |", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 606, + 606 + ] + }, + { + "text": "|FCVT.W.S |rs1, frm^*^ |rd |NV, NX |^*^if rm=111", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 608, + 608 + ] + }, + { + "text": "|FCVT.WU.S |rs1, frm^*^ |rd |NV, NX |^*^if rm=111", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 610, + 610 + ] + }, + { + "text": "|FEQ.S |rs1, rs2 |rd |NV |", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 614, + 614 + ] + }, + { + "text": "|FLT.S |rs1, rs2 |rd |NV |", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 616, + 616 + ] + }, + { + "text": "|FLE.S |rs1, rs2 |rd |NV |", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 618, + 618 + ] + }, + { + "text": "|FCVT.S.W |rs1, frm^*^ |rd |NX |^*^if rm=111", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 622, + 622 + ] + }, + { + "text": "|FCVT.S.WU |rs1, frm^*^ |rd |NX |^*^if rm=111", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 624, + 624 + ] + }, + { + "text": ".RV64F Standard Extension | | |Source Registers |Destination Registers |Accumulating CSRs|", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 630, + 633 + ] + }, + { + "text": "|FCVT.L.S |rs1, frm^*^ |rd |NV, NX |^*^if rm=111", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 635, + 635 + ] + }, + { + "text": "|FCVT.LU.S |rs1, frm^*^ |rd |NV, NX |^*^if rm=111", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 637, + 637 + ] + }, + { + "text": "|FCVT.S.L |rs1, frm^*^ |rd |NX |^*^if rm=111", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 639, + 639 + ] + }, + { + "text": "|FCVT.S.LU |rs1, frm^*^ |rd |NX |^*^if rm=111", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 641, + 641 + ] + }, + { + "text": ".RV32D Standard Extension |", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 645, + 647 + ] + }, + { + "text": "| |Source Registers|Destination Registers |Accumulating CSRs |", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 649, + 649 + ] + }, + { + "text": "|FSD |rs1 ^A^, rs2^D^ | | |", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 653, + 653 + ] + }, + { + "text": "|FMADD.D |rs1, rs2, rs3, frm^*^ |rd |NV, OF, UF, NX |^*^if rm=111", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 655, + 655 + ] + }, + { + "text": "|FMSUB.D |rs1, rs2, rs3, frm^*^ |rd |NV, OF, UF, NX |^*^if rm=111", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 657, + 657 + ] + }, + { + "text": "|FNMSUB.D |rs1, rs2, rs3, frm^*^ |rd |NV, OF, UF, NX |^*^if rm=111", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 659, + 659 + ] + }, + { + "text": "|FNMADD.D |rs1, rs2, rs3, frm^*^ |rd |NV, OF, UF, NX |^*^if rm=111", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 661, + 661 + ] + }, + { + "text": "|FADD.D |rs1, rs2, frm^*^ |rd |NV, OF, NX |^*^if rm=111", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 663, + 663 + ] + }, + { + "text": "|FSUB.D |rs1, rs2, frm^*^ |rd |NV, OF, NX |^*^if rm=111", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 665, + 665 + ] + }, + { + "text": "|FMUL.D |rs1, rs2, frm^*^ |rd |NV, OF, UF, NX |^*^if rm=111", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 667, + 667 + ] + }, + { + "text": "|FDIV.D |rs1, rs2, frm^*^ |rd |NV, DZ, OF, UF, NX |^*^if rm=111", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 669, + 669 + ] + }, + { + "text": "|FSQRT.D |rs1, frm^*^ |rd |NV, NX |^*^if rm=111", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 671, + 671 + ] + }, + { + "text": "|FSGNJ.D |rs1, rs2 |rd | |", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 673, + 673 + ] + }, + { + "text": "|FSGNJN.D |rs1, rs2 |rd | |", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 675, + 675 + ] + }, + { + "text": "|FSGNJX.D |rs1, rs2 |rd | |", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 677, + 677 + ] + }, + { + "text": "|FMIN.D |rs1, rs2 |rd |NV |", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 679, + 679 + ] + }, + { + "text": "|FMAX.D |rs1, rs2 |rd |NV |", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 681, + 681 + ] + }, + { + "text": "|FCVT.S.D |rs1, frm^*^ |rd |NV, OF, UF, NX |^*^if rm=111", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 683, + 683 + ] + }, + { + "text": "|FEQ.D |rs1, rs2 |rd |NV |", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 687, + 687 + ] + }, + { + "text": "|FLT.D |rs1, rs2 |rd |NV |", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 689, + 689 + ] + }, + { + "text": "|FLE.D |rs1, rs2 |rd |NV |", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 691, + 691 + ] + }, + { + "text": "|FCVT.W.D |rs1, frm^*^ |rd |NV, NX |^*^if rm=111", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 695, + 695 + ] + }, + { + "text": "|FCVT.WU.D |rs1, frm^*^ |rd |NV, NX |^*^if rm=111", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 697, + 697 + ] + }, + { + "text": ".RV64D Standard Extension |", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 705, + 707 + ] + }, + { + "text": "| |Source Registers |Destination Registers |Accumulating CSRs |", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 709, + 709 + ] + }, + { + "text": "|FCVT.L.D |rs1, frm^*^ |rd |NV, NX |^*^if rm=111", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 711, + 711 + ] + }, + { + "text": "|FCVT.LU.D |rs1, frm^*^ |rd |NV, NX |^*^if rm=111", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 713, + 713 + ] + }, + { + "text": "|FCVT.D.L |rs1, frm^*^ |rd |NX |^*^if rm=111", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 717, + 717 + ] + }, + { + "text": "|FCVT.D.LU |rs1, frm^*^ |rd |NX |^*^if rm=111", + "section": "Preamble > RVWMO Memory Consistency Model, Version 2.0 > Definition of the RVWMO Memory Model > Source and Destination Register Listings", + "line_range": [ + 719, + 719 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__unpriv__vector-examples.json b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__vector-examples.json new file mode 100644 index 0000000000..7182f92360 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__vector-examples.json @@ -0,0 +1,222 @@ +{ + "source_file": "src/unpriv/vector-examples.adoc", + "total": 27, + "sentences": [ + { + "text": "The following are provided as non-normative text to help explain the vector ISA.", + "section": "Preamble > Vector Assembly Code Examples", + "line_range": [ + 3, + 3 + ] + }, + { + "text": "---- include::example/vvaddint32.s[lines=4..-1] ----", + "section": "Preamble > Vector Assembly Code Examples > Vector-vector add example", + "line_range": [ + 7, + 9 + ] + }, + { + "text": "---- Code using one width for predicate and different width for masked compute. int8t a[]; int32t b[], c[]; for (i=0; i Vector Assembly Code Examples > Vector-vector add example > Example with mixed-width mask and compute.", + "line_range": [ + 13, + 24 + ] + }, + { + "text": "vsetvli x0, a0, e32, m4, ta, mu Vector of 32-bit values. sub a0, a0, a4 Decrement count vmv.v.i v4, 1 Splat immediate to destination vle32.v v4, (a3), v0.t Load requested elements of C, others undisturbed sll t1, a4, 2 add a3, a3, t1 Bump pointer. vse32.v v4, (a2) Store b[i]. add a2, a2, t1 Bump pointer. bnez a0, loop Any more? ----", + "section": "Preamble > Vector Assembly Code Examples > Vector-vector add example > Example with mixed-width mask and compute.", + "line_range": [ + 26, + 35 + ] + }, + { + "text": "---- include::example/memcpy.s[lines=4..-1] ----", + "section": "Preamble > Vector Assembly Code Examples > Vector-vector add example > Memcpy example", + "line_range": [ + 39, + 41 + ] + }, + { + "text": "---- (int16) z[i] = ((int8) x[i] < 5) ? (int16) a[i] : (int16) b[i];", + "section": "Preamble > Vector Assembly Code Examples > Vector-vector add example > Conditional example", + "line_range": [ + 45, + 47 + ] + }, + { + "text": "loop: vsetvli t0, a0, e8, m1, ta, ma Use 8b elements. vle8.v v0, (a1) Get x[i] sub a0, a0, t0 Decrement element count add a1, a1, t0 x[i] Bump pointer vmslt.vi v0, v0, 5 Set mask in v0 vsetvli x0, x0, e16, m2, ta, mu Use 16b elements. slli t0, t0, 1 Multiply by 2 bytes vle16.v v2, (a2), v0.t z[i] = a[i] case vmnot.m v0, v0 Invert v0 add a2, a2, t0 a[i] bump pointer vle16.v v2, (a3), v0.t z[i] = b[i] case add a3, a3, t0 b[i] bump pointer vse16.v v2, (a4) Store z add a4, a4, t0 z[i] bump pointer bnez a0, loop ----", + "section": "Preamble > Vector Assembly Code Examples > Vector-vector add example > Conditional example", + "line_range": [ + 49, + 65 + ] + }, + { + "text": "---- include::example/saxpy.s[lines=4..-1] ----", + "section": "Preamble > Vector Assembly Code Examples > Vector-vector add example > SAXPY example", + "line_range": [ + 68, + 70 + ] + }, + { + "text": "---- include::example/sgemm.S[lines=4..-1] ----", + "section": "Preamble > Vector Assembly Code Examples > Vector-vector add example > SGEMM example", + "line_range": [ + 74, + 76 + ] + }, + { + "text": "---- v1 = v1 / v2 to almost 23 bits of precision.", + "section": "Preamble > Vector Assembly Code Examples > Vector-vector add example > Division approximation example", + "line_range": [ + 80, + 81 + ] + }, + { + "text": "vfrec7.v v3, v2 Estimate 1/v2 li t0, 0x3f800000 vmv.v.x v4, t0 Splat 1.0 vfnmsac.vv v4, v2, v3 1.0 - v2 * est(1/v2) vfmadd.vv v3, v4, v3 Better estimate of 1/v2 vmv.v.x v4, t0 Splat 1.0 vfnmsac.vv v4, v2, v3 1.0 - v2 * est(1/v2) vfmadd.vv v3, v4, v3 Better estimate of 1/v2 vfmul.vv v1, v1, v3 Estimate of v1/v2 ----", + "section": "Preamble > Vector Assembly Code Examples > Vector-vector add example > Division approximation example", + "line_range": [ + 83, + 92 + ] + }, + { + "text": "---- v1 = sqrt(v1) to more than 23 bits of precision.", + "section": "Preamble > Vector Assembly Code Examples > Vector-vector add example > Square root approximation example", + "line_range": [ + 96, + 97 + ] + }, + { + "text": "fmv.w.x ft0, x0 Mask off zero inputs vmfne.vf v0, v1, ft0 to avoid DZ exception vfrsqrt7.v v2, v1, v0.t Estimate r ~= 1/sqrt(v1) vmfne.vf v0, v2, ft0, v0.t Mask off +inf to avoid NV li t0, 0x3f800000 fli.s ft0, 0.5 vmv.v.x v5, t0 Splat 1.0 vfmul.vv v3, v1, v2, v0.t t = v1 r vfmul.vf v4, v2, ft0, v0.t 0.5 r vfmsub.vv v3, v2, v5, v0.t t r - 1 vfnmsac.vv v2, v3, v4, v0.t r - (0.5 r) (t r - 1) Better estimate of 1/sqrt(v1) vfmul.vv v1, v1, v2, v0.t t = v1 r vfmsub.vv v2, v1, v5, v0.t t r - 1 vfmul.vf v3, v1, ft0, v0.t 0.5 t vfnmsac.vv v1, v2, v3, v0.t t - (0.5 t) (t r - 1) ~ sqrt(v1) to about 23.3 bits ----", + "section": "Preamble > Vector Assembly Code Examples > Vector-vector add example > Square root approximation example", + "line_range": [ + 99, + 116 + ] + }, + { + "text": "---- include::example/strcmp.s[lines=4..-1] ----", + "section": "Preamble > Vector Assembly Code Examples > Vector-vector add example > C standard library strcmp example", + "line_range": [ + 120, + 122 + ] + }, + { + "text": "This appendix presents a non-normative example to help explain where compilers can make good use of the fractional LMUL feature.", + "section": "Preamble > Vector Assembly Code Examples > Vector-vector add example > Fractional LMUL example", + "line_range": [ + 126, + 127 + ] + }, + { + "text": "Consider the following (admittedly contrived) loop written in C:", + "section": "Preamble > Vector Assembly Code Examples > Vector-vector add example > Fractional LMUL example", + "line_range": [ + 129, + 129 + ] + }, + { + "text": "[source,c] ---- void addref(long N, signed char *restrict cc, signed char *restrict ca, signed char *restrict cb, long *restrict lc, long *restrict la, long *restrict lb, long *restrict ld, long *restrict le, long *restrict lf, long *restrict lg, long *restrict lh, long *restrict li, long *restrict lj, long *restrict lk, long *restrict ll, long *restrict lm) { long i; for (i = 0; i < N; i++) { cc[i] = ca[i] + cb[i]; // Note this 'char' addition that creates a mixed type situation lc[i] = la[i] + lb[i]; lf[i] = ld[i] + le[i]; li[i] = lg[i] + lh[i]; ll[i] = lk[i] + lj[i]; lm[i] += lm[i] + lc[i] + lf[i] + li[i] + ll[i]; } } ----", + "section": "Preamble > Vector Assembly Code Examples > Vector-vector add example > Fractional LMUL example", + "line_range": [ + 131, + 150 + ] + }, + { + "text": "The example loop has a high register pressure due to the many input variables and temporaries required.", + "section": "Preamble > Vector Assembly Code Examples > Vector-vector add example > Fractional LMUL example", + "line_range": [ + 152, + 160 + ] + }, + { + "text": "The compiler realizes there are two datatypes within the loop: an 8-bit 'char' and a 64-bit 'long *'.", + "section": "Preamble > Vector Assembly Code Examples > Vector-vector add example > Fractional LMUL example", + "line_range": [ + 152, + 160 + ] + }, + { + "text": "Without fractional LMUL, the compiler would be forced to use LMUL=1 for the 8-bit computation and LMUL=8 for the 64-bit computation(s), to have equal number of elements on all computations within the same loop iteration.", + "section": "Preamble > Vector Assembly Code Examples > Vector-vector add example > Fractional LMUL example", + "line_range": [ + 152, + 160 + ] + }, + { + "text": "Under LMUL=8, only 4 registers are available to the register allocator.", + "section": "Preamble > Vector Assembly Code Examples > Vector-vector add example > Fractional LMUL example", + "line_range": [ + 152, + 160 + ] + }, + { + "text": "Given the large number of 64-bit variables and temporaries required in this loop, the compiler ends up generating a lot of spill code.", + "section": "Preamble > Vector Assembly Code Examples > Vector-vector add example > Fractional LMUL example", + "line_range": [ + 152, + 160 + ] + }, + { + "text": "The code below demonstrates this effect:", + "section": "Preamble > Vector Assembly Code Examples > Vector-vector add example > Fractional LMUL example", + "line_range": [ + 152, + 160 + ] + }, + { + "text": "---- .LBB04: %vector.body =>This Inner Loop Header: Depth=1 add s9, a2, s6 vsetvli s1, zero, e8,m1,ta,mu vle8.v v25, (s9) add s1, a3, s6 vle8.v v26, (s1) vadd.vv v25, v26, v25 add s1, a1, s6 vse8.v v25, (s1) add s9, a5, s10 vsetvli s1, zero, e64,m8,ta,mu vle64.v v8, (s9) add s1, a6, s10 vle64.v v16, (s1) add s1, a7, s10 vle64.v v24, (s1) add s1, s3, s10 vle64.v v0, (s1) sd a0, -112(s0) ld a0, -128(s0) vs8r.v v0, (a0) Spill LMUL=8 add s9, t6, s10 add s11, t5, s10 add ra, t2, s10 add s1, t3, s10 vle64.v v0, (s9) ld s9, -136(s0) vs8r.v v0, (s9) Spill LMUL=8 vle64.v v0, (s11) ld s9, -144(s0) vs8r.v v0, (s9) Spill LMUL=8 vle64.v v0, (ra) ld s9, -160(s0) vs8r.v v0, (s9) Spill LMUL=8 vle64.v v0, (s1) ld s1, -152(s0) vs8r.v v0, (s1) Spill LMUL=8 vadd.vv v16, v16, v8 ld s1, -128(s0) vl8r.v v8, (s1) Reload LMUL=8 vadd.vv v8, v8, v24 ld s1, -136(s0) vl8r.v v24, (s1) Reload LMUL=8 ld s1, -144(s0) vl8r.v v0, (s1) Reload LMUL=8 vadd.vv v24, v0, v24 ld s1, -128(s0) vs8r.v v24, (s1) Spill LMUL=8 ld s1, -152(s0) vl8r.v v0, (s1) Reload LMUL=8 ld s1, -160(s0) vl8r.v v24, (s1) Reload LMUL=8 vadd.vv v0, v0, v24 add s1, a4, s10 vse64.v v16, (s1) add s1, s2, s10 vse64.v v8, (s1) vadd.vv v8, v8, v16 add s1, t4, s10 ld s9, -128(s0) vl8r.v v16, (s9) Reload LMUL=8 vse64.v v16, (s1) add s9, t0, s10 vadd.vv v8, v8, v16 vle64.v v16, (s9) add s1, t1, s10 vse64.v v0, (s1) vadd.vv v8, v8, v0 vsll.vi v16, v16, 1 vadd.vv v8, v8, v16 vse64.v v8, (s9) add s6, s6, s7 add s10, s10, s8 bne s6, s4, .LBB04 ----", + "section": "Preamble > Vector Assembly Code Examples > Vector-vector add example > Fractional LMUL example", + "line_range": [ + 162, + 238 + ] + }, + { + "text": "If instead of using LMUL=1 for the 8-bit computation, the compiler is allowed to use a fractional LMUL=1/2, then the 64-bit computations can be performed using LMUL=4 (note that the same ratio of 64-bit elements and 8-bit elements is preserved as in the previous example).", + "section": "Preamble > Vector Assembly Code Examples > Vector-vector add example > Fractional LMUL example", + "line_range": [ + 240, + 245 + ] + }, + { + "text": "Now the compiler has 8 available registers to perform register allocation, resulting in no spill code, as shown in the loop below:", + "section": "Preamble > Vector Assembly Code Examples > Vector-vector add example > Fractional LMUL example", + "line_range": [ + 240, + 245 + ] + }, + { + "text": "---- .LBB04: %vector.body =>This Inner Loop Header: Depth=1 add s9, a2, s6 vsetvli s1, zero, e8,mf2,ta,mu // LMUL=1/2 ! vle8.v v25, (s9) add s1, a3, s6 vle8.v v26, (s1) vadd.vv v25, v26, v25 add s1, a1, s6 vse8.v v25, (s1) add s9, a5, s10 vsetvli s1, zero, e64,m4,ta,mu // LMUL=4 vle64.v v28, (s9) add s1, a6, s10 vle64.v v8, (s1) vadd.vv v28, v8, v28 add s1, a7, s10 vle64.v v8, (s1) add s1, s3, s10 vle64.v v12, (s1) add s1, t6, s10 vle64.v v16, (s1) add s1, t5, s10 vle64.v v20, (s1) add s1, a4, s10 vse64.v v28, (s1) vadd.vv v8, v12, v8 vadd.vv v12, v20, v16 add s1, t2, s10 vle64.v v16, (s1) add s1, t3, s10 vle64.v v20, (s1) add s1, s2, s10 vse64.v v8, (s1) add s9, t4, s10 vadd.vv v16, v20, v16 add s11, t0, s10 vle64.v v20, (s11) vse64.v v12, (s9) add s1, t1, s10 vse64.v v16, (s1) vsll.vi v20, v20, 1 vadd.vv v28, v8, v28 vadd.vv v28, v28, v12 vadd.vv v28, v28, v16 vadd.vv v28, v28, v20 vse64.v v28, (s11) add s6, s6, s7 add s10, s10, s8 bne s6, s4, .LBB04 ----", + "section": "Preamble > Vector Assembly Code Examples > Vector-vector add example > Fractional LMUL example", + "line_range": [ + 247, + 298 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__unpriv__za.json b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__za.json new file mode 100644 index 0000000000..3c77e540dd --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__za.json @@ -0,0 +1,126 @@ +{ + "source_file": "src/unpriv/za.adoc", + "total": 15, + "sentences": [ + { + "text": "NOTE: This chapter is currently being restructured.", + "section": "Preamble > Atomic Instructions", + "line_range": [ + 3, + 4 + ] + }, + { + "text": "Its contents are normative, but the presentation might appear disjoint.", + "section": "Preamble > Atomic Instructions", + "line_range": [ + 3, + 4 + ] + }, + { + "text": "RISC-V provides several extensions that atomically read-modify-write memory to support synchronization between multiple RISC-V harts running in the same memory space.", + "section": "Preamble > Atomic Instructions", + "line_range": [ + 6, + 15 + ] + }, + { + "text": "The two forms of atomic instruction provided are load-reserved/store-conditional instructions and atomic fetch-and-op memory instructions.", + "section": "Preamble > Atomic Instructions", + "line_range": [ + 6, + 15 + ] + }, + { + "text": "Both types of atomic instruction support various memory consistency orderings including unordered, acquire, release, and sequentially consistent semantics.", + "section": "Preamble > Atomic Instructions", + "line_range": [ + 6, + 15 + ] + }, + { + "text": "These instructions allow RISC-V to support the RCsc memory consistency model. cite:[Gharachorloo90memoryconsistency]", + "section": "Preamble > Atomic Instructions", + "line_range": [ + 6, + 15 + ] + }, + { + "text": "The base RISC-V ISA has a relaxed memory model, with the FENCE instruction used to impose additional ordering constraints.", + "section": "Preamble > Atomic Instructions > Specifying Ordering of Atomic Instructions", + "line_range": [ + 22, + 26 + ] + }, + { + "text": "The address space is divided by the execution environment into memory and I/O domains, and the FENCE instruction provides options to order accesses to one or both of these two address domains.", + "section": "Preamble > Atomic Instructions > Specifying Ordering of Atomic Instructions", + "line_range": [ + 22, + 26 + ] + }, + { + "text": "To provide more efficient support for release consistency cite:[Gharachorloo90memoryconsistency], each atomic instruction has two bits, aq and rl, used to specify additional memory ordering constraints as viewed by other RISC-V harts.", + "section": "Preamble > Atomic Instructions > Specifying Ordering of Atomic Instructions", + "line_range": [ + 28, + 34 + ] + }, + { + "text": "The bits order accesses to one of the two address domains, memory or I/O, depending on which address domain the atomic instruction is accessing.", + "section": "Preamble > Atomic Instructions > Specifying Ordering of Atomic Instructions", + "line_range": [ + 28, + 34 + ] + }, + { + "text": "No ordering constraint is implied to accesses to the other domain, and a FENCE instruction should be used to order across both domains.", + "section": "Preamble > Atomic Instructions > Specifying Ordering of Atomic Instructions", + "line_range": [ + 28, + 34 + ] + }, + { + "text": "If both bits are clear, no additional ordering constraints are imposed on the atomic memory operation.", + "section": "Preamble > Atomic Instructions > Specifying Ordering of Atomic Instructions", + "line_range": [ + 36, + 47 + ] + }, + { + "text": "If only the aq bit is set, the atomic memory operation is treated as an acquire access, i.e., no following memory operations on this RISC-V hart can be observed to take place before the acquire memory operation.", + "section": "Preamble > Atomic Instructions > Specifying Ordering of Atomic Instructions", + "line_range": [ + 36, + 47 + ] + }, + { + "text": "If only the rl bit is set, the atomic memory operation is treated as a release access, i.e., the release memory operation cannot be observed to take place before any earlier memory operations on this RISC-V hart.", + "section": "Preamble > Atomic Instructions > Specifying Ordering of Atomic Instructions", + "line_range": [ + 36, + 47 + ] + }, + { + "text": "If both the aq and rl bits are set, the atomic memory operation is sequentially consistent and cannot be observed to happen before any earlier memory operations or after any later memory operations in the same RISC-V hart and to the same address domain.", + "section": "Preamble > Atomic Instructions > Specifying Ordering of Atomic Instructions", + "line_range": [ + 36, + 47 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zaamo.json b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zaamo.json new file mode 100644 index 0000000000..65c40598b5 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zaamo.json @@ -0,0 +1,134 @@ +{ + "source_file": "src/unpriv/zaamo.adoc", + "total": 16, + "sentences": [ + { + "text": "The atomic memory operation (AMO) instructions perform read-modify-write operations for multiprocessor synchronization and are encoded with an R-type instruction format.", + "section": "Preamble > \"Zaamo\" Extension for Atomic Memory Operations", + "line_range": [ + 5, + 13 + ] + }, + { + "text": "These AMO instructions atomically load a data value from the address in rs1, place the value into register rd, apply a binary operator to the loaded value and the original value in rs2, then store the result back to the original address in rs1. AMOs can either operate on doublewords (RV64 only) or words in memory.", + "section": "Preamble > \"Zaamo\" Extension for Atomic Memory Operations", + "line_range": [ + 5, + 13 + ] + }, + { + "text": "For RV64, 32-bit AMOs always sign-extend the value placed in rd, and ignore the upper 32 bits of the original value of rs2.", + "section": "Preamble > \"Zaamo\" Extension for Atomic Memory Operations", + "line_range": [ + 5, + 13 + ] + }, + { + "text": "For AMOs, the Zaamo extension requires that the address held in rs1 be naturally aligned to the size of the operand (i.e., eight-byte aligned for doublewords and four-byte aligned for words).", + "section": "Preamble > \"Zaamo\" Extension for Atomic Memory Operations", + "line_range": [ + 15, + 22 + ] + }, + { + "text": "If the address is not naturally aligned, an address-misaligned exception or an access-fault exception will be generated.", + "section": "Preamble > \"Zaamo\" Extension for Atomic Memory Operations", + "line_range": [ + 15, + 22 + ] + }, + { + "text": "The access-fault exception can be generated for a memory access that would otherwise be able to complete except for the misalignment, if the misaligned access should not be emulated.", + "section": "Preamble > \"Zaamo\" Extension for Atomic Memory Operations", + "line_range": [ + 15, + 22 + ] + }, + { + "text": "The misaligned atomicity granule PMA, defined in , optionally relaxes this alignment requirement.", + "section": "Preamble > \"Zaamo\" Extension for Atomic Memory Operations", + "line_range": [ + 24, + 34 + ] + }, + { + "text": "If present, the misaligned atomicity granule PMA specifies the size of a misaligned atomicity granule, a power-of-two number of bytes.", + "section": "Preamble > \"Zaamo\" Extension for Atomic Memory Operations", + "line_range": [ + 24, + 34 + ] + }, + { + "text": "The misaligned atomicity granule PMA applies only to AMOs, loads and stores defined in the base ISAs, and loads and stores of no more than XLEN bits defined in the F, D, and Q extensions, and compressed encodings thereof.", + "section": "Preamble > \"Zaamo\" Extension for Atomic Memory Operations", + "line_range": [ + 24, + 34 + ] + }, + { + "text": "For an instruction in that set, if all accessed bytes lie within the same misaligned atomicity granule, the instruction will not raise an exception for reasons of address alignment, and the instruction will give rise to only one memory operation for the purposes of RVWMO--i.e., it will execute atomically.", + "section": "Preamble > \"Zaamo\" Extension for Atomic Memory Operations", + "line_range": [ + 24, + 34 + ] + }, + { + "text": "The operations supported are swap, integer add, bitwise AND, bitwise OR, bitwise XOR, and signed and unsigned integer maximum and minimum.", + "section": "Preamble > \"Zaamo\" Extension for Atomic Memory Operations", + "line_range": [ + 36, + 40 + ] + }, + { + "text": "Without ordering constraints, these AMOs can be used to implement parallel reduction operations, where typically the return value would be discarded by writing to `x0`.", + "section": "Preamble > \"Zaamo\" Extension for Atomic Memory Operations", + "line_range": [ + 36, + 40 + ] + }, + { + "text": "To help implement multiprocessor synchronization, the AMOs optionally provide release consistency semantics.", + "section": "Preamble > \"Zaamo\" Extension for Atomic Memory Operations", + "line_range": [ + 42, + 50 + ] + }, + { + "text": "If the aq bit is set, then no later memory operations in this RISC-V hart can be observed to take place before the AMO.", + "section": "Preamble > \"Zaamo\" Extension for Atomic Memory Operations", + "line_range": [ + 42, + 50 + ] + }, + { + "text": "Conversely, if the rl bit is set, then other RISC-V harts will not observe the AMO before memory accesses preceding the AMO in this RISC-V hart.", + "section": "Preamble > \"Zaamo\" Extension for Atomic Memory Operations", + "line_range": [ + 42, + 50 + ] + }, + { + "text": "Setting both the aq and the rl bit on an AMO makes the sequence sequentially consistent, meaning that it cannot be reordered with earlier or later memory operations from the same hart.", + "section": "Preamble > \"Zaamo\" Extension for Atomic Memory Operations", + "line_range": [ + 42, + 50 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zabha.json b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zabha.json new file mode 100644 index 0000000000..e80e764c73 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zabha.json @@ -0,0 +1,166 @@ +{ + "source_file": "src/unpriv/zabha.adoc", + "total": 20, + "sentences": [ + { + "text": "The A-extension offers atomic memory operation (AMO) instructions for words, doublewords, and quadwords (only for `AMOCAS`).", + "section": "Preamble > \"Zabha\" Extension for Byte and Halfword Atomic Memory Operations, Version 1.0", + "line_range": [ + 3, + 8 + ] + }, + { + "text": "The absence of atomic operations for subword data types necessitates emulation strategies.", + "section": "Preamble > \"Zabha\" Extension for Byte and Halfword Atomic Memory Operations, Version 1.0", + "line_range": [ + 3, + 8 + ] + }, + { + "text": "For bitwise operations, this emulation can be performed via word-sized bitwise AMO* instructions.", + "section": "Preamble > \"Zabha\" Extension for Byte and Halfword Atomic Memory Operations, Version 1.0", + "line_range": [ + 3, + 8 + ] + }, + { + "text": "For non-bitwise operations, emulation is achievable using word-sized `LR`/`SC` instructions.", + "section": "Preamble > \"Zabha\" Extension for Byte and Halfword Atomic Memory Operations, Version 1.0", + "line_range": [ + 3, + 8 + ] + }, + { + "text": "Several limitations arise from this emulation approach:", + "section": "Preamble > \"Zabha\" Extension for Byte and Halfword Atomic Memory Operations, Version 1.0", + "line_range": [ + 10, + 10 + ] + }, + { + "text": "In systems with large-scale or Non-Uniform Memory Access (NUMA) configurations, emulation based on `LR`/`SC` introduces issues related to scalability and fairness, particularly under conditions of high contention.", + "section": "Preamble > \"Zabha\" Extension for Byte and Halfword Atomic Memory Operations, Version 1.0", + "line_range": [ + 12, + 14 + ] + }, + { + "text": "Emulation of narrower AMOs through wider AMO* instructions on non-idempotent IO memory regions may result in unintended side effects.", + "section": "Preamble > \"Zabha\" Extension for Byte and Halfword Atomic Memory Operations, Version 1.0", + "line_range": [ + 16, + 17 + ] + }, + { + "text": "Utilizing wider AMO* instructions for emulating narrower AMOs risks activating extraneous breakpoints or watchpoints.", + "section": "Preamble > \"Zabha\" Extension for Byte and Halfword Atomic Memory Operations, Version 1.0", + "line_range": [ + 19, + 20 + ] + }, + { + "text": "In the absence of native support for subword atomics, compilers often resort to inlining code sequences to provide the required emulation.", + "section": "Preamble > \"Zabha\" Extension for Byte and Halfword Atomic Memory Operations, Version 1.0", + "line_range": [ + 22, + 25 + ] + }, + { + "text": "This practice contributes to an increase in code size, with consequent impacts on system performance and memory utilization.", + "section": "Preamble > \"Zabha\" Extension for Byte and Halfword Atomic Memory Operations, Version 1.0", + "line_range": [ + 22, + 25 + ] + }, + { + "text": "The Zabha extension addresses these limitations by adding support for byte and halfword atomic memory operations to the RISC-V Unprivileged ISA.", + "section": "Preamble > \"Zabha\" Extension for Byte and Halfword Atomic Memory Operations, Version 1.0", + "line_range": [ + 27, + 29 + ] + }, + { + "text": "The Zabha extension depends upon the Zaamo standard extension.", + "section": "Preamble > \"Zabha\" Extension for Byte and Halfword Atomic Memory Operations, Version 1.0", + "line_range": [ + 27, + 29 + ] + }, + { + "text": "Zabha extension provides the `AMO[ADD|AND|OR|XOR|SWAP|MIN[U]|MAX[U]].[B|H]` instructions.", + "section": "Preamble > \"Zabha\" Extension for Byte and Halfword Atomic Memory Operations, Version 1.0 > Byte and Halfword Atomic Memory Operation Instructions", + "line_range": [ + 33, + 35 + ] + }, + { + "text": "If Zacas extension is also implemented, Zabha further provides the `AMOCAS.[B|H]` instructions.", + "section": "Preamble > \"Zabha\" Extension for Byte and Halfword Atomic Memory Operations, Version 1.0 > Byte and Halfword Atomic Memory Operation Instructions", + "line_range": [ + 33, + 35 + ] + }, + { + "text": "[wavedrom, zabha-ext-wavedrom-reg,svg] .... {reg: [ {bits: 7, name: 'opcode', attr:['AMO','AMO','AMO','AMO','AMO','AMO','AMO','AMO']}, {bits: 5, name: 'rd', attr:['dest','dest','dest','dest','dest','dest','dest','dest']}, {bits: 3, name: 'funct3', attr:['width=0/1','width=0/1','width=0/1','width=0/1','width=0/1','width=0/1','width=0/1','width=0/1']}, {bits: 5, name: 'rs1', attr:['addr','addr','addr','addr','addr','addr','addr','addr']}, {bits: 5, name: 'rs2', attr:['src','src','src','src','src','src','src','src']}, {bits: 1, name: 'rl'}, {bits: 1, name: 'aq', attr:['ordering','ordering','ordering','ordering','ordering','ordering','ordering','ordering']}, {bits: 5, name: 'funct5', attr:['AMOSWAP.B/H','AMOADD.B/H','AMOAND.B/H','AMOOR.B/H','AMOXOR.B/H','AMOMAX[U].B/H','AMOMIN[U].B/H','AMOCAS.B/H']}, ], config:{lanes: 1, hspace:1024}} ....", + "section": "Preamble > \"Zabha\" Extension for Byte and Halfword Atomic Memory Operations, Version 1.0 > Byte and Halfword Atomic Memory Operation Instructions", + "line_range": [ + 37, + 49 + ] + }, + { + "text": "Byte and halfword AMOs always sign-extend the value placed in `rd`, and ignore the stem:[XLEN-1:2^{(width + 3)}] bits of the original value in `rs2`.", + "section": "Preamble > \"Zabha\" Extension for Byte and Halfword Atomic Memory Operations, Version 1.0 > Byte and Halfword Atomic Memory Operation Instructions", + "line_range": [ + 51, + 54 + ] + }, + { + "text": "The `AMOCAS.[B|H]` instructions similarly ignore the stem:[XLEN-1:2^{(width + 3)}] bits of the original value in `rd`.", + "section": "Preamble > \"Zabha\" Extension for Byte and Halfword Atomic Memory Operations, Version 1.0 > Byte and Halfword Atomic Memory Operation Instructions", + "line_range": [ + 51, + 54 + ] + }, + { + "text": "Similar to the AMOs specified in the A extension, the Zabha extension mandates that the address contained in the `rs1` register must be naturally aligned to the size of the operand.", + "section": "Preamble > \"Zabha\" Extension for Byte and Halfword Atomic Memory Operations, Version 1.0 > Byte and Halfword Atomic Memory Operation Instructions", + "line_range": [ + 56, + 59 + ] + }, + { + "text": "The same exception options as specified in the A extension are applicable in cases where the address is not naturally aligned.", + "section": "Preamble > \"Zabha\" Extension for Byte and Halfword Atomic Memory Operations, Version 1.0 > Byte and Halfword Atomic Memory Operation Instructions", + "line_range": [ + 56, + 59 + ] + }, + { + "text": "Similar to the AMOs specified in the A and Zacas extensions, the AMOs in the Zabha extension optionally provide release consistency semantics, using the `aq` and `rl` bits, to help implement multiprocessor synchronization.", + "section": "Preamble > \"Zabha\" Extension for Byte and Halfword Atomic Memory Operations, Version 1.0 > Byte and Halfword Atomic Memory Operation Instructions", + "line_range": [ + 61, + 63 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zacas.json b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zacas.json new file mode 100644 index 0000000000..6d87bf4938 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zacas.json @@ -0,0 +1,302 @@ +{ + "source_file": "src/unpriv/zacas.adoc", + "total": 37, + "sentences": [ + { + "text": "Compare-and-Swap (CAS) provides an easy and typically faster way to perform thread synchronization operations when supported as a hardware instruction. CAS is typically used by lock-free and wait-free algorithms.", + "section": "Preamble > \"Zacas\" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0", + "line_range": [ + 3, + 7 + ] + }, + { + "text": "This extension defines CAS instructions to operate on 32-bit, 64-bit, and 128-bit (RV64 only) data values.", + "section": "Preamble > \"Zacas\" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0", + "line_range": [ + 3, + 7 + ] + }, + { + "text": "The Zacas extension depends upon the Zaamo extension.", + "section": "Preamble > \"Zacas\" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0", + "line_range": [ + 3, + 7 + ] + }, + { + "text": "[wavedrom, , svg] .... {reg: [ {bits: 7, name: 'opcode', attr:'AMO'}, {bits: 5, name: 'rd', attr:'dest'}, {bits: 3, name: 'funct3', attr:['010', '011', '100']}, {bits: 5, name: 'rs1', attr:'addr'}, {bits: 5, name: 'rs2', attr:'src'}, {bits: 1, name: 'rl'}, {bits: 1, name: 'aq'}, {bits: 5, name: '00101', attr:['AMOCAS.W', 'AMOCAS.D', 'AMOCAS.Q']}, ], config:{lanes: 1, hspace:1024}} ....", + "section": "Preamble > \"Zacas\" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 > Word/Doubleword/Quadword CAS (AMOCAS.W/D/Q) Instructions", + "line_range": [ + 11, + 23 + ] + }, + { + "text": "For RV32, `AMOCAS.W` atomically loads a 32-bit data value from address in `rs1`, compares the loaded value to the 32-bit value held in `rd`, and if the comparison is bitwise equal, then stores the 32-bit value held in `rs2` to the original address in `rs1`.", + "section": "Preamble > \"Zacas\" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 > Word/Doubleword/Quadword CAS (AMOCAS.W/D/Q) Instructions", + "line_range": [ + 25, + 29 + ] + }, + { + "text": "The value loaded from memory is placed into register `rd`.", + "section": "Preamble > \"Zacas\" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 > Word/Doubleword/Quadword CAS (AMOCAS.W/D/Q) Instructions", + "line_range": [ + 25, + 29 + ] + }, + { + "text": "The operation performed by `AMOCAS.W` for RV32 is as follows:", + "section": "Preamble > \"Zacas\" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 > Word/Doubleword/Quadword CAS (AMOCAS.W/D/Q) Instructions", + "line_range": [ + 25, + 29 + ] + }, + { + "text": "[listing] ---- temp = mem[X(rs1)] if ( temp X(rd) ) mem[X(rs1)] = X(rs2) X(rd) = temp ----", + "section": "Preamble > \"Zacas\" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 > Word/Doubleword/Quadword CAS (AMOCAS.W/D/Q) Instructions", + "line_range": [ + 31, + 37 + ] + }, + { + "text": "`AMOCAS.D` is similar to `AMOCAS.W` but operates on 64-bit data values.", + "section": "Preamble > \"Zacas\" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 > Word/Doubleword/Quadword CAS (AMOCAS.W/D/Q) Instructions", + "line_range": [ + 39, + 39 + ] + }, + { + "text": "For RV32, `AMOCAS.D` atomically loads 64-bits of a data value from address in `rs1`, compares the loaded value to a 64-bit value held in a register pair consisting of `rd` and `rd+1`, and if the comparison is bitwise equal, then stores the 64-bit value held in the register pair `rs2` and `rs2+1` to the original address in `rs1`.", + "section": "Preamble > \"Zacas\" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 > Word/Doubleword/Quadword CAS (AMOCAS.W/D/Q) Instructions", + "line_range": [ + 41, + 52 + ] + }, + { + "text": "The value loaded from memory is placed into the register pair `rd` and `rd+1`.", + "section": "Preamble > \"Zacas\" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 > Word/Doubleword/Quadword CAS (AMOCAS.W/D/Q) Instructions", + "line_range": [ + 41, + 52 + ] + }, + { + "text": "The instruction requires the first register in the pair to be even numbered; encodings with odd numbered registers specified in `rs2` and `rd` are reserved.", + "section": "Preamble > \"Zacas\" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 > Word/Doubleword/Quadword CAS (AMOCAS.W/D/Q) Instructions", + "line_range": [ + 41, + 52 + ] + }, + { + "text": "When the first register of a source register pair is `x0`, then both halves of the pair read as zero.", + "section": "Preamble > \"Zacas\" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 > Word/Doubleword/Quadword CAS (AMOCAS.W/D/Q) Instructions", + "line_range": [ + 41, + 52 + ] + }, + { + "text": "When the first register of a destination register pair is `x0`, then the entire register result is discarded and neither destination register is written.", + "section": "Preamble > \"Zacas\" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 > Word/Doubleword/Quadword CAS (AMOCAS.W/D/Q) Instructions", + "line_range": [ + 41, + 52 + ] + }, + { + "text": "The operation performed by `AMOCAS.D` for RV32 is as follows:", + "section": "Preamble > \"Zacas\" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 > Word/Doubleword/Quadword CAS (AMOCAS.W/D/Q) Instructions", + "line_range": [ + 41, + 52 + ] + }, + { + "text": "[listing] temp0 = mem[X(rs1)+0] temp1 = mem[X(rs1)+4] comp0 = (rd x0) ? 0 : X(rd) comp1 = (rd x0) ? 0 : X(rd+1) swap0 = (rs2 x0) ? 0 : X(rs2) swap1 = (rs2 x0) ? 0 : X(rs2+1) if ( temp0 comp0 ) && ( temp1 comp1 ) mem[X(rs1)+0] = swap0 mem[X(rs1)+4] = swap1 endif if ( rd != x0 ) X(rd) = temp0 X(rd+1) = temp1 endif", + "section": "Preamble > \"Zacas\" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 > Word/Doubleword/Quadword CAS (AMOCAS.W/D/Q) Instructions", + "line_range": [ + 56, + 70 + ] + }, + { + "text": "For RV64, `AMOCAS.W` atomically loads a 32-bit data value from address in `rs1`, compares the loaded value to the lower 32 bits of the value held in `rd`, and if the comparison is bitwise equal, then stores the lower 32 bits of the value held in `rs2` to the original address in `rs1`.", + "section": "Preamble > \"Zacas\" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 > Word/Doubleword/Quadword CAS (AMOCAS.W/D/Q) Instructions", + "line_range": [ + 72, + 77 + ] + }, + { + "text": "The 32-bit value loaded from memory is sign-extended and is placed into register `rd`.", + "section": "Preamble > \"Zacas\" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 > Word/Doubleword/Quadword CAS (AMOCAS.W/D/Q) Instructions", + "line_range": [ + 72, + 77 + ] + }, + { + "text": "The operation performed by `AMOCAS.W` for RV64 is as follows:", + "section": "Preamble > \"Zacas\" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 > Word/Doubleword/Quadword CAS (AMOCAS.W/D/Q) Instructions", + "line_range": [ + 72, + 77 + ] + }, + { + "text": "[listing] temp[31:0] = mem[X(rs1)] if ( temp[31:0] X(rd)[31:0] ) mem[X(rs1)] = X(rs2)[31:0] X(rd) = SignExtend(temp[31:0])", + "section": "Preamble > \"Zacas\" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 > Word/Doubleword/Quadword CAS (AMOCAS.W/D/Q) Instructions", + "line_range": [ + 79, + 83 + ] + }, + { + "text": "For RV64, `AMOCAS.D` atomically loads 64-bits of a data value from address in `rs1`, compares the loaded value to a 64-bit value held in `rd`, and if the comparison is bitwise equal, then stores the 64-bit value held in `rs2` to the original address in `rs1`.", + "section": "Preamble > \"Zacas\" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 > Word/Doubleword/Quadword CAS (AMOCAS.W/D/Q) Instructions", + "line_range": [ + 85, + 94 + ] + }, + { + "text": "The value loaded from memory is placed into register `rd`.", + "section": "Preamble > \"Zacas\" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 > Word/Doubleword/Quadword CAS (AMOCAS.W/D/Q) Instructions", + "line_range": [ + 85, + 94 + ] + }, + { + "text": "The operation performed by `AMOCAS.D` for RV64 is as follows: [listing] temp = mem[X(rs1)] if ( temp X(rd) ) mem[X(rs1)] = X(rs2) X(rd) = temp", + "section": "Preamble > \"Zacas\" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 > Word/Doubleword/Quadword CAS (AMOCAS.W/D/Q) Instructions", + "line_range": [ + 85, + 94 + ] + }, + { + "text": "`AMOCAS.Q` (RV64 only) atomically loads 128-bits of a data value from address in `rs1`, compares the loaded value to a 128-bit value held in a register pair consisting of `rd` and `rd+1`, and if the comparison is bitwise equal, then stores the 128-bit value held in the register pair `rs2` and `rs2+1` to the original address in `rs1`.", + "section": "Preamble > \"Zacas\" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 > Word/Doubleword/Quadword CAS (AMOCAS.W/D/Q) Instructions", + "line_range": [ + 96, + 107 + ] + }, + { + "text": "The value loaded from memory is placed into the register pair `rd` and `rd+1`.", + "section": "Preamble > \"Zacas\" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 > Word/Doubleword/Quadword CAS (AMOCAS.W/D/Q) Instructions", + "line_range": [ + 96, + 107 + ] + }, + { + "text": "The instruction requires the first register in the pair to be even numbered; encodings with odd numbered registers specified in `rs2` and `rd` are reserved.", + "section": "Preamble > \"Zacas\" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 > Word/Doubleword/Quadword CAS (AMOCAS.W/D/Q) Instructions", + "line_range": [ + 96, + 107 + ] + }, + { + "text": "When the first register of a source register pair is `x0`, then both halves of the pair read as zero.", + "section": "Preamble > \"Zacas\" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 > Word/Doubleword/Quadword CAS (AMOCAS.W/D/Q) Instructions", + "line_range": [ + 96, + 107 + ] + }, + { + "text": "When the first register of a destination register pair is `x0`, then the entire register result is discarded and neither destination register is written.", + "section": "Preamble > \"Zacas\" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 > Word/Doubleword/Quadword CAS (AMOCAS.W/D/Q) Instructions", + "line_range": [ + 96, + 107 + ] + }, + { + "text": "The operation performed by `AMOCAS.Q` is as follows:", + "section": "Preamble > \"Zacas\" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 > Word/Doubleword/Quadword CAS (AMOCAS.W/D/Q) Instructions", + "line_range": [ + 96, + 107 + ] + }, + { + "text": "[listing] temp0 = mem[X(rs1)+0] temp1 = mem[X(rs1)+8] comp0 = (rd x0) ? 0 : X(rd) comp1 = (rd x0) ? 0 : X(rd+1) swap0 = (rs2 x0) ? 0 : X(rs2) swap1 = (rs2 x0) ? 0 : X(rs2+1) if ( temp0 comp0 ) && ( temp1 comp1 ) mem[X(rs1)+0] = swap0 mem[X(rs1)+8] = swap1 endif if ( rd != x0 ) X(rd) = temp0 X(rd+1) = temp1 endif", + "section": "Preamble > \"Zacas\" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 > Word/Doubleword/Quadword CAS (AMOCAS.W/D/Q) Instructions", + "line_range": [ + 111, + 125 + ] + }, + { + "text": "Just as for AMOs in the A extension, `AMOCAS.W/D/Q` requires that the address held in `rs1` be naturally aligned to the size of the operand (i.e., 16-byte aligned for quadwords, eight-byte aligned for doublewords, and four-byte aligned for words).", + "section": "Preamble > \"Zacas\" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 > Word/Doubleword/Quadword CAS (AMOCAS.W/D/Q) Instructions", + "line_range": [ + 127, + 131 + ] + }, + { + "text": "And the same exception options apply if the address is not naturally aligned.", + "section": "Preamble > \"Zacas\" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 > Word/Doubleword/Quadword CAS (AMOCAS.W/D/Q) Instructions", + "line_range": [ + 127, + 131 + ] + }, + { + "text": "Just as for AMOs in the A extension, the `AMOCAS.W/D/Q` optionally provide release consistency semantics, using the `aq` and `rl` bits, to help implement multiprocessor synchronization.", + "section": "Preamble > \"Zacas\" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 > Word/Doubleword/Quadword CAS (AMOCAS.W/D/Q) Instructions", + "line_range": [ + 133, + 139 + ] + }, + { + "text": "The memory operation performed by an `AMOCAS.W/D/Q`, when successful, has acquire semantics if `aq` bit is 1 and has release semantics if `rl` bit is 1.", + "section": "Preamble > \"Zacas\" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 > Word/Doubleword/Quadword CAS (AMOCAS.W/D/Q) Instructions", + "line_range": [ + 133, + 139 + ] + }, + { + "text": "The memory operation performed by an `AMOCAS.W/D/Q`, when not successful, has acquire semantics if `aq` bit is 1 but does not have release semantics, regardless of `rl`.", + "section": "Preamble > \"Zacas\" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 > Word/Doubleword/Quadword CAS (AMOCAS.W/D/Q) Instructions", + "line_range": [ + 133, + 139 + ] + }, + { + "text": "A FENCE instruction may be used to order the memory read access and, if produced, the memory write access by an `AMOCAS.W/D/Q` instruction.", + "section": "Preamble > \"Zacas\" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 > Word/Doubleword/Quadword CAS (AMOCAS.W/D/Q) Instructions", + "line_range": [ + 141, + 142 + ] + }, + { + "text": "An `AMOCAS.W/D/Q` instruction always requires write permissions.", + "section": "Preamble > \"Zacas\" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0 > Word/Doubleword/Quadword CAS (AMOCAS.W/D/Q) Instructions", + "line_range": [ + 144, + 144 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zalasr.json b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zalasr.json new file mode 100644 index 0000000000..91ad93b28a --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zalasr.json @@ -0,0 +1,270 @@ +{ + "source_file": "src/unpriv/zalasr.adoc", + "total": 33, + "sentences": [ + { + "text": "The Zalasr (Load-Acquire and Store-Release) extension provides load-acquire and store-release instructions in RISC-V.", + "section": "Preamble > \"Zalasr\" Atomic Load-Acquire and Store-Release Instructions, Version 1.0", + "line_range": [ + 2, + 5 + ] + }, + { + "text": "These can be important for high performance designs by enabling finer-grained synchronisation than is possible with fences alone, by providing a unidirectional fence.", + "section": "Preamble > \"Zalasr\" Atomic Load-Acquire and Store-Release Instructions, Version 1.0", + "line_range": [ + 2, + 5 + ] + }, + { + "text": "Load-acquire and store-release are widely used in language-level memory models: both the Java and {cpp} memory models make use of acquire-release semantics, and {cpp}'s `atomic` provides primitives that are meant to map directly to load-acquire and store-release instructions.", + "section": "Preamble > \"Zalasr\" Atomic Load-Acquire and Store-Release Instructions, Version 1.0", + "line_range": [ + 2, + 5 + ] + }, + { + "text": "The Zalasr extension builds on the atomic support provided by the Zaamo (Atomic Memory Operations), Zalrsc (Load-Reserved and Store-Conditional), and Zabha (Byte and Halfword Atomic Memory Operations) extensions by providing additional atomic operations (although it can be implemented independently of them).", + "section": "Preamble > \"Zalasr\" Atomic Load-Acquire and Store-Release Instructions, Version 1.0", + "line_range": [ + 7, + 12 + ] + }, + { + "text": "All of the AMO operations in Zaamo (and Zabha) are read-modify-write operations that both load and store.", + "section": "Preamble > \"Zalasr\" Atomic Load-Acquire and Store-Release Instructions, Version 1.0", + "line_range": [ + 7, + 12 + ] + }, + { + "text": "The Zalrsc extension provides operations that are only loads or stores.", + "section": "Preamble > \"Zalasr\" Atomic Load-Acquire and Store-Release Instructions, Version 1.0", + "line_range": [ + 7, + 12 + ] + }, + { + "text": "However, since it is designed to perform an atomic operation on a single memory word or doubleword, the loads and stores are designed to be paired.", + "section": "Preamble > \"Zalasr\" Atomic Load-Acquire and Store-Release Instructions, Version 1.0", + "line_range": [ + 7, + 12 + ] + }, + { + "text": "The load-reserved implies that a future store-conditional will follow while store-conditional requires that there was a previous load-reserved without other intervening loads or stores.", + "section": "Preamble > \"Zalasr\" Atomic Load-Acquire and Store-Release Instructions, Version 1.0", + "line_range": [ + 7, + 12 + ] + }, + { + "text": "Therefore, the Zalrsc extension does not provide a general atomic and ordered load or store.", + "section": "Preamble > \"Zalasr\" Atomic Load-Acquire and Store-Release Instructions, Version 1.0", + "line_range": [ + 7, + 12 + ] + }, + { + "text": "Zalasr fills this gap by offering truly standalone atomic and ordered loads and stores.", + "section": "Preamble > \"Zalasr\" Atomic Load-Acquire and Store-Release Instructions, Version 1.0", + "line_range": [ + 14, + 16 + ] + }, + { + "text": "The Zalasr instructions are atomic loads and stores that support ordering annotations.", + "section": "Preamble > \"Zalasr\" Atomic Load-Acquire and Store-Release Instructions, Version 1.0", + "line_range": [ + 14, + 16 + ] + }, + { + "text": "With the combination of Zaamo, Zabha, and Zalasr all {cpp} atomic operations can be supported with single instructions.", + "section": "Preamble > \"Zalasr\" Atomic Load-Acquire and Store-Release Instructions, Version 1.0", + "line_range": [ + 14, + 16 + ] + }, + { + "text": "The Zalasr instructions always sign-extend the value placed in rd and ignore the upper bits of the value of rs2.", + "section": "Preamble > \"Zalasr\" Atomic Load-Acquire and Store-Release Instructions, Version 1.0 > Load-Acquire and Store-Release Instructions", + "line_range": [ + 20, + 23 + ] + }, + { + "text": "The instructions in the Zalasr extension require that the address held in rs1 be naturally aligned to the size in bytes (2^width^) of the operand.", + "section": "Preamble > \"Zalasr\" Atomic Load-Acquire and Store-Release Instructions, Version 1.0 > Load-Acquire and Store-Release Instructions", + "line_range": [ + 20, + 23 + ] + }, + { + "text": "If the address is not naturally aligned, an address-misaligned exception or an access-fault exception will be generated.", + "section": "Preamble > \"Zalasr\" Atomic Load-Acquire and Store-Release Instructions, Version 1.0 > Load-Acquire and Store-Release Instructions", + "line_range": [ + 20, + 23 + ] + }, + { + "text": "The access-fault exception can be generated for a memory access that would otherwise be able to complete except for the misalignment, if the misaligned access should not be emulated.", + "section": "Preamble > \"Zalasr\" Atomic Load-Acquire and Store-Release Instructions, Version 1.0 > Load-Acquire and Store-Release Instructions", + "line_range": [ + 20, + 23 + ] + }, + { + "text": "The misaligned atomicity granule PMA, defined in , optionally relaxes this alignment requirement.", + "section": "Preamble > \"Zalasr\" Atomic Load-Acquire and Store-Release Instructions, Version 1.0 > Load-Acquire and Store-Release Instructions", + "line_range": [ + 25, + 26 + ] + }, + { + "text": "If all accessed bytes lie within the same misaligned atomicity granule, the instruction will not raise an exception for reasons of address alignment, and the instruction will give rise to only one memory operation for the purposes of RVWMO—i.e., it will execute atomically.", + "section": "Preamble > \"Zalasr\" Atomic Load-Acquire and Store-Release Instructions, Version 1.0 > Load-Acquire and Store-Release Instructions", + "line_range": [ + 25, + 26 + ] + }, + { + "text": "[insns-ldatomic,reftext=\"Load Acquire\"]", + "section": "Preamble > \"Zalasr\" Atomic Load-Acquire and Store-Release Instructions, Version 1.0 > Load-Acquire and Store-Release Instructions", + "line_range": [ + 30, + 30 + ] + }, + { + "text": "Synopsis:: The load-acquire instruction atomically loads a 2^width^-byte value from the address in rs1 and places the sign-extended value into the register rd, subject to the ordering annotations specified in the instruction.", + "section": "Preamble > \"Zalasr\" Atomic Load-Acquire and Store-Release Instructions, Version 1.0 > Load-Acquire and Store-Release Instructions > Load Acquire", + "line_range": [ + 33, + 34 + ] + }, + { + "text": "Mnemonic:: lb.{aq,aqrl} rd, (rs1)", + "section": "Preamble > \"Zalasr\" Atomic Load-Acquire and Store-Release Instructions, Version 1.0 > Load-Acquire and Store-Release Instructions > Load Acquire", + "line_range": [ + 36, + 38 + ] + }, + { + "text": "ld.{aq,aqrl} rd, (rs1) Encoding:: [wavedrom, ,svg] .... {reg: [ {bits: 7, name: 'opcode', attr: ['7', 'AMO'], type: 8}, {bits: 5, name: 'rd', attr: ['5', 'dest'], type: 2}, {bits: 3, name: 'funct3', attr: ['3', 'width'], type: 8}, {bits: 5, name: 'rs1', attr: ['5', 'addr'], type: 4}, {bits: 5, name: 'rs2', attr: ['5', '0'], type: 4}, {bits: 1, name: 'rl', attr: ['1', 'ring'], type: 8}, {bits: 1, name: 'aq', attr: ['1', 'orde', '1'], type: 8}, {bits: 5, name: 'funct5', attr: ['5', 'Load Acquire', '00110'], type: 8}, ]} ....", + "section": "Preamble > \"Zalasr\" Atomic Load-Acquire and Store-Release Instructions, Version 1.0 > Load-Acquire and Store-Release Instructions > Load Acquire", + "line_range": [ + 44, + 60 + ] + }, + { + "text": "This instruction loads 2^width^ bytes of memory from rs1 atomically and writes the result into rd.", + "section": "Preamble > \"Zalasr\" Atomic Load-Acquire and Store-Release Instructions, Version 1.0 > Load-Acquire and Store-Release Instructions > Load Acquire", + "line_range": [ + 64, + 70 + ] + }, + { + "text": "If the size (2^width+3^) is less than XLEN, it is sign-extended to fill the destination register.", + "section": "Preamble > \"Zalasr\" Atomic Load-Acquire and Store-Release Instructions, Version 1.0 > Load-Acquire and Store-Release Instructions > Load Acquire", + "line_range": [ + 64, + 70 + ] + }, + { + "text": "This load must have the ordering annotation aq and may have ordering annotation rl encoded in the instruction.", + "section": "Preamble > \"Zalasr\" Atomic Load-Acquire and Store-Release Instructions, Version 1.0 > Load-Acquire and Store-Release Instructions > Load Acquire", + "line_range": [ + 64, + 70 + ] + }, + { + "text": "The instruction always has an \"acquire-RCsc\" annotation, and if the bit rl is set the instruction has a \"release-RCsc\" annotation. + The versions without the aq bit set are RESERVED. LD.{AQ, AQRL} is RV64-only.", + "section": "Preamble > \"Zalasr\" Atomic Load-Acquire and Store-Release Instructions, Version 1.0 > Load-Acquire and Store-Release Instructions > Load Acquire", + "line_range": [ + 64, + 70 + ] + }, + { + "text": "[insns-sdatomic,reftext=\"Store Release\"]", + "section": "Preamble > \"Zalasr\" Atomic Load-Acquire and Store-Release Instructions, Version 1.0 > Load-Acquire and Store-Release Instructions > Load Acquire", + "line_range": [ + 74, + 74 + ] + }, + { + "text": "Synopsis:: The store-release instruction atomically stores the 2^width^-byte value from the low bits of register rs2 to the address in rs1, subject to the ordering annotations specified in the instruction.", + "section": "Preamble > \"Zalasr\" Atomic Load-Acquire and Store-Release Instructions, Version 1.0 > Load-Acquire and Store-Release Instructions > Store Release", + "line_range": [ + 78, + 79 + ] + }, + { + "text": "Mnemonic:: sb.{rl,aqrl} rs2, (rs1)", + "section": "Preamble > \"Zalasr\" Atomic Load-Acquire and Store-Release Instructions, Version 1.0 > Load-Acquire and Store-Release Instructions > Store Release", + "line_range": [ + 81, + 83 + ] + }, + { + "text": "Encoding:: [wavedrom, ,svg] .... {reg: [ {bits: 7, name: 'opcode', attr: ['7', 'AMO'], type: 8}, {bits: 5, name: 'rd', attr: ['5', '0'], type: 2}, {bits: 3, name: 'funct3', attr: ['3', 'width'], type: 8}, {bits: 5, name: 'rs1', attr: ['5', 'addr'], type: 4}, {bits: 5, name: 'rs2', attr: ['5', 'src'], type: 4}, {bits: 1, name: 'rl', attr: ['1', 'ring', '1'], type: 8}, {bits: 1, name: 'aq', attr: ['1', 'orde'], type: 8}, {bits: 5, name: 'funct5', attr: ['5', 'Store Release', '00111'], type: 8}, ]} ....", + "section": "Preamble > \"Zalasr\" Atomic Load-Acquire and Store-Release Instructions, Version 1.0 > Load-Acquire and Store-Release Instructions > Store Release", + "line_range": [ + 92, + 106 + ] + }, + { + "text": "This instruction stores 2^width^ bytes of memory from rs1 atomically.", + "section": "Preamble > \"Zalasr\" Atomic Load-Acquire and Store-Release Instructions, Version 1.0 > Load-Acquire and Store-Release Instructions > Store Release", + "line_range": [ + 110, + 115 + ] + }, + { + "text": "This store must have ordering annotation rl and may have ordering annotation aq encoded in the instruction.", + "section": "Preamble > \"Zalasr\" Atomic Load-Acquire and Store-Release Instructions, Version 1.0 > Load-Acquire and Store-Release Instructions > Store Release", + "line_range": [ + 110, + 115 + ] + }, + { + "text": "The instruction always has an \"release-RCsc\" annotation, and if the bit aq is set the instruction has a \"acquire-RCsc\" annotation. + The versions without the rl bit set are RESERVED. SD.{RL, AQRL} is RV64-only.", + "section": "Preamble > \"Zalasr\" Atomic Load-Acquire and Store-Release Instructions, Version 1.0 > Load-Acquire and Store-Release Instructions > Store Release", + "line_range": [ + 110, + 115 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zalrsc.json b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zalrsc.json new file mode 100644 index 0000000000..c7fe2d678d --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zalrsc.json @@ -0,0 +1,278 @@ +{ + "source_file": "src/unpriv/zalrsc.adoc", + "total": 34, + "sentences": [ + { + "text": "Complex atomic memory operations on a single memory word or doubleword are performed with the load-reserved (LR) and store-conditional (SC) instructions. LR.W loads a word from the address in rs1, places the sign-extended value in rd, and registers a reservation set—a set of bytes that subsumes the bytes in the addressed word. SC.W conditionally writes a word in rs2 to the address in rs1: the SC.W succeeds only if the reservation is still valid and the reservation set contains the bytes being written.", + "section": "Preamble > \"Zalrsc\" Extension for Load-Reserved/Store-Conditional Instructions", + "line_range": [ + 5, + 25 + ] + }, + { + "text": "If the SC.W succeeds, the instruction writes the word in rs2 to memory, and it writes zero to rd.", + "section": "Preamble > \"Zalrsc\" Extension for Load-Reserved/Store-Conditional Instructions", + "line_range": [ + 5, + 25 + ] + }, + { + "text": "If the SC.W fails, the instruction does not write to memory, and it writes a nonzero value to rd.", + "section": "Preamble > \"Zalrsc\" Extension for Load-Reserved/Store-Conditional Instructions", + "line_range": [ + 5, + 25 + ] + }, + { + "text": "No SC.W instruction shall retire unless it passes memory permission checks, but it is UNSPECIFIED whether any side effects of implicit address translation and protection memory accesses (such as setting a page-table entry D bit) occur on a failed SC.W.", + "section": "Preamble > \"Zalrsc\" Extension for Load-Reserved/Store-Conditional Instructions", + "line_range": [ + 5, + 25 + ] + }, + { + "text": "For the purposes of memory protection, a failed SC.W may be treated like a store.", + "section": "Preamble > \"Zalrsc\" Extension for Load-Reserved/Store-Conditional Instructions", + "line_range": [ + 5, + 25 + ] + }, + { + "text": "Regardless of success or failure, executing an SC.W instruction invalidates any reservation held by this hart. LR.D and SC.D act analogously on doublewords and are only available on RV64.", + "section": "Preamble > \"Zalrsc\" Extension for Load-Reserved/Store-Conditional Instructions", + "line_range": [ + 5, + 25 + ] + }, + { + "text": "For RV64, LR.W and SC.W sign-extend the value placed in rd.", + "section": "Preamble > \"Zalrsc\" Extension for Load-Reserved/Store-Conditional Instructions", + "line_range": [ + 5, + 25 + ] + }, + { + "text": "The failure code with value 1 encodes an unspecified failure.", + "section": "Preamble > \"Zalrsc\" Extension for Load-Reserved/Store-Conditional Instructions", + "line_range": [ + 27, + 29 + ] + }, + { + "text": "Other failure codes are reserved at this time.", + "section": "Preamble > \"Zalrsc\" Extension for Load-Reserved/Store-Conditional Instructions", + "line_range": [ + 27, + 29 + ] + }, + { + "text": "Portable software should only assume the failure code will be non-zero.", + "section": "Preamble > \"Zalrsc\" Extension for Load-Reserved/Store-Conditional Instructions", + "line_range": [ + 27, + 29 + ] + }, + { + "text": "For LR and SC, the Zalrsc extension requires that the address held in rs1 be naturally aligned to the size of the operand (i.e., eight-byte aligned for doublewords and four-byte aligned for words).", + "section": "Preamble > \"Zalrsc\" Extension for Load-Reserved/Store-Conditional Instructions", + "line_range": [ + 31, + 49 + ] + }, + { + "text": "If the address is not naturally aligned, an address-misaligned exception or an access-fault exception will be generated.", + "section": "Preamble > \"Zalrsc\" Extension for Load-Reserved/Store-Conditional Instructions", + "line_range": [ + 31, + 49 + ] + }, + { + "text": "The access-fault exception can be generated for a memory access that would otherwise be able to complete except for the misalignment, if the misaligned access should not be emulated.", + "section": "Preamble > \"Zalrsc\" Extension for Load-Reserved/Store-Conditional Instructions", + "line_range": [ + 31, + 49 + ] + }, + { + "text": "An implementation can register an arbitrarily large reservation set on each LR, provided the reservation set includes all bytes of the addressed data word or doubleword.", + "section": "Preamble > \"Zalrsc\" Extension for Load-Reserved/Store-Conditional Instructions", + "line_range": [ + 31, + 49 + ] + }, + { + "text": "An SC can only pair with the most recent LR in program order.", + "section": "Preamble > \"Zalrsc\" Extension for Load-Reserved/Store-Conditional Instructions", + "line_range": [ + 31, + 49 + ] + }, + { + "text": "An SC may succeed only if no store from another hart to the reservation set can be observed to have occurred between the LR and the SC, and if there is no other SC between the LR and itself in program order.", + "section": "Preamble > \"Zalrsc\" Extension for Load-Reserved/Store-Conditional Instructions", + "line_range": [ + 31, + 49 + ] + }, + { + "text": "An SC may succeed only if no write from a device other than a hart to the bytes accessed by the LR instruction can be observed to have occurred between the LR and SC.", + "section": "Preamble > \"Zalrsc\" Extension for Load-Reserved/Store-Conditional Instructions", + "line_range": [ + 31, + 49 + ] + }, + { + "text": "Note this LR might have had a different effective address and data size, but reserved the SC's address as part of the reservation set.", + "section": "Preamble > \"Zalrsc\" Extension for Load-Reserved/Store-Conditional Instructions", + "line_range": [ + 31, + 49 + ] + }, + { + "text": "The SC must fail if the address is not within the reservation set of the most recent LR in program order.", + "section": "Preamble > \"Zalrsc\" Extension for Load-Reserved/Store-Conditional Instructions", + "line_range": [ + 51, + 61 + ] + }, + { + "text": "The SC must fail if a store to the reservation set from another hart can be observed to occur between the LR and SC.", + "section": "Preamble > \"Zalrsc\" Extension for Load-Reserved/Store-Conditional Instructions", + "line_range": [ + 51, + 61 + ] + }, + { + "text": "The SC must fail if a write from some other device to the bytes accessed by the LR can be observed to occur between the LR and SC. (", + "section": "Preamble > \"Zalrsc\" Extension for Load-Reserved/Store-Conditional Instructions", + "line_range": [ + 51, + 61 + ] + }, + { + "text": "If such a device writes the reservation set but does not write the bytes accessed by the LR, the SC may or may not fail.) An SC must fail if there is another SC (to any address) between the LR and the SC in program order.", + "section": "Preamble > \"Zalrsc\" Extension for Load-Reserved/Store-Conditional Instructions", + "line_range": [ + 51, + 61 + ] + }, + { + "text": "The precise statement of the atomicity requirements for successful LR/SC sequences is defined by the Atomicity Axiom in .", + "section": "Preamble > \"Zalrsc\" Extension for Load-Reserved/Store-Conditional Instructions", + "line_range": [ + 51, + 61 + ] + }, + { + "text": "An SC instruction can never be observed by another RISC-V hart before the LR instruction that established the reservation.", + "section": "Preamble > \"Zalrsc\" Extension for Load-Reserved/Store-Conditional Instructions", + "line_range": [ + 63, + 64 + ] + }, + { + "text": "Software should not set the rl bit on an LR instruction unless the aq bit is also set, nor should software set the aq bit on an SC instruction unless the rl bit is also set. LR.rl and SC.aq instructions are not guaranteed to provide any stronger ordering than those with both bits clear, but may result in lower performance.", + "section": "Preamble > \"Zalrsc\" Extension for Load-Reserved/Store-Conditional Instructions", + "line_range": [ + 66, + 70 + ] + }, + { + "text": "The Zalrsc extension defines constrained LR/SC loops, which have the following properties:", + "section": "Preamble > \"Zalrsc\" Extension for Load-Reserved/Store-Conditional Instructions > Eventual Success of Store-Conditional Instructions", + "line_range": [ + 75, + 76 + ] + }, + { + "text": "The loop comprises only an LR/SC sequence and code to retry the sequence in the case of failure, and must comprise at most 16 instructions placed sequentially in memory. * An LR/SC sequence begins with an LR instruction and ends with an SC instruction.", + "section": "Preamble > \"Zalrsc\" Extension for Load-Reserved/Store-Conditional Instructions > Eventual Success of Store-Conditional Instructions", + "line_range": [ + 78, + 95 + ] + }, + { + "text": "The dynamic code executed between the LR and SC instructions can only contain instructions from the base ''I'' instruction set, excluding loads, stores, backward jumps, taken backward branches, JALR, FENCE, and SYSTEM instructions.", + "section": "Preamble > \"Zalrsc\" Extension for Load-Reserved/Store-Conditional Instructions > Eventual Success of Store-Conditional Instructions", + "line_range": [ + 78, + 95 + ] + }, + { + "text": "Compressed forms of the aforementioned ''I'' instructions in the C (hence Zca) and Zcb extensions are also permitted. * The code to retry a failing LR/SC sequence can contain backwards jumps and/or branches to repeat the LR/SC sequence, but otherwise has the same constraint as the code between the LR and SC. * The LR and SC addresses must lie within a memory region with the LR/SC eventuality property.", + "section": "Preamble > \"Zalrsc\" Extension for Load-Reserved/Store-Conditional Instructions > Eventual Success of Store-Conditional Instructions", + "line_range": [ + 78, + 95 + ] + }, + { + "text": "The execution environment is responsible for communicating which regions have this property. * The SC must be to the same effective address and of the same data size as the latest LR executed by the same hart.", + "section": "Preamble > \"Zalrsc\" Extension for Load-Reserved/Store-Conditional Instructions > Eventual Success of Store-Conditional Instructions", + "line_range": [ + 78, + 95 + ] + }, + { + "text": "LR/SC sequences that do not lie within constrained LR/SC loops are unconstrained.", + "section": "Preamble > \"Zalrsc\" Extension for Load-Reserved/Store-Conditional Instructions > Eventual Success of Store-Conditional Instructions", + "line_range": [ + 97, + 100 + ] + }, + { + "text": "Unconstrained LR/SC sequences might succeed on some attempts on some implementations, but might never succeed on other implementations.", + "section": "Preamble > \"Zalrsc\" Extension for Load-Reserved/Store-Conditional Instructions > Eventual Success of Store-Conditional Instructions", + "line_range": [ + 97, + 100 + ] + }, + { + "text": "If a hart H enters a constrained LR/SC loop, the execution environment must guarantee that one of the following events eventually occurs:", + "section": "Preamble > \"Zalrsc\" Extension for Load-Reserved/Store-Conditional Instructions > Eventual Success of Store-Conditional Instructions", + "line_range": [ + 102, + 103 + ] + }, + { + "text": "H or some other hart executes a successful SC to the reservation set of the LR instruction in H's constrained LR/SC loops. * Some other hart executes an unconditional store or AMO instruction to the reservation set of the LR instruction in H's constrained LR/SC loop, or some other device in the system writes to that reservation set. * H executes a branch or jump that exits the constrained LR/SC loop. * H traps.", + "section": "Preamble > \"Zalrsc\" Extension for Load-Reserved/Store-Conditional Instructions > Eventual Success of Store-Conditional Instructions", + "line_range": [ + 105, + 111 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zama.json b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zama.json new file mode 100644 index 0000000000..7d8f02a5b3 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zama.json @@ -0,0 +1,22 @@ +{ + "source_file": "src/unpriv/zama.adoc", + "total": 2, + "sentences": [ + { + "text": "If the Zama16b extension is implemented, then the in main memory regions with both the cacheability and coherence PMAs is 16 bytes.", + "section": "Preamble > Zama16b Extension for 16-byte Misaligned Atomicity, Version 1.0", + "line_range": [ + 3, + 8 + ] + }, + { + "text": "Misaligned loads, stores, and AMOs to main memory regions that do not cross a naturally aligned 16-byte boundary are atomic.", + "section": "Preamble > Zama16b Extension for 16-byte Misaligned Atomicity, Version 1.0", + "line_range": [ + 3, + 8 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zars.json b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zars.json new file mode 100644 index 0000000000..d56d11b2ec --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zars.json @@ -0,0 +1,30 @@ +{ + "source_file": "src/unpriv/zars.adoc", + "total": 3, + "sentences": [ + { + "text": "The Za128rs extension requires that the reservation sets used by the instructions in the Zalrsc extension be contiguous, naturally aligned, and at most 128 bytes in size.", + "section": "Preamble > Za128rs Extension for Reservation-Set Size, Version 1.0", + "line_range": [ + 3, + 5 + ] + }, + { + "text": "The Za64rs extension requires that the reservation sets used by the instructions in the Zalrsc extension be contiguous, naturally aligned, and at most 64 bytes in size.", + "section": "Preamble > Za128rs Extension for Reservation-Set Size, Version 1.0 > Za64rs Extension for Reservation-Set Size, Version 1.0", + "line_range": [ + 10, + 12 + ] + }, + { + "text": "The Za64rs extension implies the Za128rs extension.", + "section": "Preamble > Za128rs Extension for Reservation-Set Size, Version 1.0 > Za64rs Extension for Reservation-Set Size, Version 1.0", + "line_range": [ + 14, + 14 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zawrs.json b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zawrs.json new file mode 100644 index 0000000000..b0302670d8 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zawrs.json @@ -0,0 +1,214 @@ +{ + "source_file": "src/unpriv/zawrs.adoc", + "total": 26, + "sentences": [ + { + "text": "The Zawrs extension defines a pair of instructions to be used in polling loops that allows a core to enter a low-power state and wait on a store to a memory location.", + "section": "Preamble > \"Zawrs\" Extension for Wait-on-Reservation-Set instructions, Version 1.01", + "line_range": [ + 3, + 6 + ] + }, + { + "text": "Waiting for a memory location to be updated is a common pattern in many use cases such as:", + "section": "Preamble > \"Zawrs\" Extension for Wait-on-Reservation-Set instructions, Version 1.01", + "line_range": [ + 3, + 6 + ] + }, + { + "text": "Contenders for a lock waiting for the lock variable to be updated.", + "section": "Preamble > \"Zawrs\" Extension for Wait-on-Reservation-Set instructions, Version 1.01", + "line_range": [ + 8, + 8 + ] + }, + { + "text": "Consumers waiting on the tail of an empty queue for the producer to queue work/data.", + "section": "Preamble > \"Zawrs\" Extension for Wait-on-Reservation-Set instructions, Version 1.01", + "line_range": [ + 10, + 12 + ] + }, + { + "text": "The producer may be code executing on a RISC-V hart, an accelerator device, an external I/O agent.", + "section": "Preamble > \"Zawrs\" Extension for Wait-on-Reservation-Set instructions, Version 1.01", + "line_range": [ + 10, + 12 + ] + }, + { + "text": "Code waiting on a flag to be set in memory indicative of an event occurring.", + "section": "Preamble > \"Zawrs\" Extension for Wait-on-Reservation-Set instructions, Version 1.01", + "line_range": [ + 14, + 17 + ] + }, + { + "text": "For example, software on a RISC-V hart may wait on a \"done\" flag to be set in memory by an accelerator device indicating completion of a job previously submitted to the device.", + "section": "Preamble > \"Zawrs\" Extension for Wait-on-Reservation-Set instructions, Version 1.01", + "line_range": [ + 14, + 17 + ] + }, + { + "text": "Such use cases involve polling on memory locations, and such busy loops can be a wasteful expenditure of energy.", + "section": "Preamble > \"Zawrs\" Extension for Wait-on-Reservation-Set instructions, Version 1.01", + "line_range": [ + 19, + 26 + ] + }, + { + "text": "To mitigate the wasteful looping in such usages, a `WRS.NTO` (WRS-with-no-timeout) instruction is provided.", + "section": "Preamble > \"Zawrs\" Extension for Wait-on-Reservation-Set instructions, Version 1.01", + "line_range": [ + 19, + 26 + ] + }, + { + "text": "Instead of polling for a store to a specific memory location, software registers a reservation set that includes all the bytes of the memory location using the `LR` instruction.", + "section": "Preamble > \"Zawrs\" Extension for Wait-on-Reservation-Set instructions, Version 1.01", + "line_range": [ + 19, + 26 + ] + }, + { + "text": "Then a subsequent `WRS.NTO` instruction would cause the hart to temporarily stall execution in a low-power state until a store occurs to the reservation set or an interrupt is observed.", + "section": "Preamble > \"Zawrs\" Extension for Wait-on-Reservation-Set instructions, Version 1.01", + "line_range": [ + 19, + 26 + ] + }, + { + "text": "Sometimes the program waiting on a memory update may also need to carry out a task at a future time or otherwise place an upper bound on the wait.", + "section": "Preamble > \"Zawrs\" Extension for Wait-on-Reservation-Set instructions, Version 1.01", + "line_range": [ + 28, + 35 + ] + }, + { + "text": "To support such use cases a second instruction `WRS.STO` (WRS-with-short-timeout) is provided that works like `WRS.NTO` but bounds the stall duration to an implementation-define short timeout such that the stall is terminated on the timeout if no other conditions have occurred to terminate the stall.", + "section": "Preamble > \"Zawrs\" Extension for Wait-on-Reservation-Set instructions, Version 1.01", + "line_range": [ + 28, + 35 + ] + }, + { + "text": "The program using this instruction may then determine if its deadline has been reached.", + "section": "Preamble > \"Zawrs\" Extension for Wait-on-Reservation-Set instructions, Version 1.01", + "line_range": [ + 28, + 35 + ] + }, + { + "text": "The `WRS.NTO` and `WRS.STO` instructions cause the hart to temporarily stall execution in a low-power state as long as the reservation set is valid and no pending interrupts, even if disabled, are observed.", + "section": "Preamble > \"Zawrs\" Extension for Wait-on-Reservation-Set instructions, Version 1.01 > Wait-on-Reservation-Set Instructions", + "line_range": [ + 40, + 44 + ] + }, + { + "text": "For `WRS.STO` the stall duration is bounded by an implementation defined short timeout.", + "section": "Preamble > \"Zawrs\" Extension for Wait-on-Reservation-Set instructions, Version 1.01 > Wait-on-Reservation-Set Instructions", + "line_range": [ + 40, + 44 + ] + }, + { + "text": "These instructions are available in all privilege modes.", + "section": "Preamble > \"Zawrs\" Extension for Wait-on-Reservation-Set instructions, Version 1.01 > Wait-on-Reservation-Set Instructions", + "line_range": [ + 40, + 44 + ] + }, + { + "text": "[wavedrom, ,svg] .... {reg: [ {bits: 7, name: 'opcode', attr: ['SYSTEM(0x73)'] }, {bits: 5, name: 'rd', attr: ['0'] }, {bits: 3, name: 'funct3', attr: ['0'] }, {bits: 5, name: 'rs1', attr: ['0'] }, {bits: 12, name: 'funct12', attr:['WRS.NTO(0x0d)', 'WRS.STO(0x1d)'] }, ], config:{lanes: 1, hspace:1024}} ....", + "section": "Preamble > \"Zawrs\" Extension for Wait-on-Reservation-Set instructions, Version 1.01 > Wait-on-Reservation-Set Instructions", + "line_range": [ + 46, + 55 + ] + }, + { + "text": "Hart execution may be stalled while the following conditions are all satisfied: [loweralpha] .", + "section": "Preamble > \"Zawrs\" Extension for Wait-on-Reservation-Set instructions, Version 1.01 > Wait-on-Reservation-Set Instructions", + "line_range": [ + 59, + 63 + ] + }, + { + "text": "The reservation set is valid .", + "section": "Preamble > \"Zawrs\" Extension for Wait-on-Reservation-Set instructions, Version 1.01 > Wait-on-Reservation-Set Instructions", + "line_range": [ + 59, + 63 + ] + }, + { + "text": "If `WRS.STO`, a \"short\" duration since start of stall has not elapsed .", + "section": "Preamble > \"Zawrs\" Extension for Wait-on-Reservation-Set instructions, Version 1.01 > Wait-on-Reservation-Set Instructions", + "line_range": [ + 59, + 63 + ] + }, + { + "text": "No pending interrupt is observed (see the rules below)", + "section": "Preamble > \"Zawrs\" Extension for Wait-on-Reservation-Set instructions, Version 1.01 > Wait-on-Reservation-Set Instructions", + "line_range": [ + 59, + 63 + ] + }, + { + "text": "While stalled, an implementation is permitted to occasionally terminate the stall and complete execution for any reason.", + "section": "Preamble > \"Zawrs\" Extension for Wait-on-Reservation-Set instructions, Version 1.01 > Wait-on-Reservation-Set Instructions", + "line_range": [ + 65, + 66 + ] + }, + { + "text": "`WRS.NTO` and `WRS.STO` instructions follow the rules of the `WFI` instruction for resuming execution on a pending interrupt.", + "section": "Preamble > \"Zawrs\" Extension for Wait-on-Reservation-Set instructions, Version 1.01 > Wait-on-Reservation-Set Instructions", + "line_range": [ + 68, + 69 + ] + }, + { + "text": "When the `TW` (Timeout Wait) bit in `mstatus` is set and `WRS.NTO` is executed in any privilege mode other than M mode, and it does not complete within an implementation-specific bounded time limit, the `WRS.NTO` instruction will cause an illegal-instruction exception.", + "section": "Preamble > \"Zawrs\" Extension for Wait-on-Reservation-Set instructions, Version 1.01 > Wait-on-Reservation-Set Instructions", + "line_range": [ + 71, + 74 + ] + }, + { + "text": "When executing in VS or VU mode, if the `VTW` bit is set in `hstatus`, the `TW` bit in `mstatus` is clear, and the `WRS.NTO` does not complete within an implementation-specific bounded time limit, the `WRS.NTO` instruction will cause a virtual-instruction exception.", + "section": "Preamble > \"Zawrs\" Extension for Wait-on-Reservation-Set instructions, Version 1.01 > Wait-on-Reservation-Set Instructions", + "line_range": [ + 76, + 79 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zc.json b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zc.json new file mode 100644 index 0000000000..521fea7e02 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zc.json @@ -0,0 +1,62 @@ +{ + "source_file": "src/unpriv/zc.adoc", + "total": 7, + "sentences": [ + { + "text": "This chapter describes the RISC-V compressed instruction-set extensions, which reduce static and dynamic code size by adding short 16-bit instruction encodings for common operations.", + "section": "Preamble > Compressed Instructions", + "line_range": [ + 3, + 7 + ] + }, + { + "text": "Typically, 50%-60% of the RISC-V instructions in a program can be replaced with compressed instructions, resulting in a 25%-30% code-size reduction.", + "section": "Preamble > Compressed Instructions", + "line_range": [ + 3, + 7 + ] + }, + { + "text": "The extlink:zca[] extension forms the core of the compressed extensions; it provides compressed forms of integer loads, stores, branches, and computational instructions.", + "section": "Preamble > Compressed Instructions", + "line_range": [ + 9, + 18 + ] + }, + { + "text": "The extlink:zcf[] extension is an XLEN=32-only extension that adds single-precision floating-point loads and stores.", + "section": "Preamble > Compressed Instructions", + "line_range": [ + 9, + 18 + ] + }, + { + "text": "The extlink:zcd[] extension adds double-precision floating-point loads and stores.", + "section": "Preamble > Compressed Instructions", + "line_range": [ + 9, + 18 + ] + }, + { + "text": "The extlink:c[] extension combines ext:zca[], ext:zcf[] if XLEN=32 and the F extension is present, and ext:zcd[] if the D extension is present.", + "section": "Preamble > Compressed Instructions", + "line_range": [ + 9, + 18 + ] + }, + { + "text": "Various additional ext:Zc*[]` extensions are also defined.", + "section": "Preamble > Compressed Instructions", + "line_range": [ + 9, + 18 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zca.json b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zca.json new file mode 100644 index 0000000000..9c0ebe6e4f --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zca.json @@ -0,0 +1,1278 @@ +{ + "source_file": "src/unpriv/zca.adoc", + "total": 159, + "sentences": [ + { + "text": "The compressed extensions use a simple compression scheme that offers shorter 16-bit versions of common 32-bit RISC-V instructions when:", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension", + "line_range": [ + 3, + 4 + ] + }, + { + "text": "the immediate or address offset is small, or * one of the registers is the zero register (`x0`), the ABI link register (`x1`), or the ABI stack pointer (`x2`), or * the destination register and the first source register are identical, or * the registers used are the 8 most popular ones.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension", + "line_range": [ + 6, + 10 + ] + }, + { + "text": "The ext:zca[] extension is compatible with all other standard instruction extensions.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension", + "line_range": [ + 12, + 17 + ] + }, + { + "text": "The ext:zca[] extension allows 16-bit instructions to be freely intermixed with 32-bit instructions, with the latter now able to start on any 16-bit boundary, i.e., IALIGN=16.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension", + "line_range": [ + 12, + 17 + ] + }, + { + "text": "With the addition of the ext:zca[] extension, no instructions can raise instruction-address-misaligned exceptions.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension", + "line_range": [ + 12, + 17 + ] + }, + { + "text": "The compressed instruction encodings are mostly common across XLEN=32 and XLEN=64, but as shown in , a few opcodes are used for different purposes depending on base ISA.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension", + "line_range": [ + 19, + 32 + ] + }, + { + "text": "For example, the XLEN=64 variant requires additional opcodes to compress loads and stores of 64-bit integer values, whereas the XLEN=32-only extlink:zcf[] extension uses the same opcodes to compress loads and stores of single-precision floating-point values.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension", + "line_range": [ + 19, + 32 + ] + }, + { + "text": "If the C extension is implemented, the appropriate compressed floating-point load and store instructions must be provided whenever the relevant standard floating-point extension (F and/or D) is also implemented.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension", + "line_range": [ + 19, + 32 + ] + }, + { + "text": "In addition, the XLEN=32 variant includes a compressed jump and link instruction to compress short-range subroutine calls, where the same opcode is used to compress ADDIW for XLEN=64.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension", + "line_range": [ + 19, + 32 + ] + }, + { + "text": "ext:zca[] was designed under the constraint that each ext:zca[] instruction expands into a single 32-bit instruction in the base ISA.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension", + "line_range": [ + 34, + 36 + ] + }, + { + "text": "Adopting this constraint has two main benefits:", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension", + "line_range": [ + 34, + 36 + ] + }, + { + "text": "Hardware designs can simply expand ext:zca[] instructions during decode, simplifying verification and minimizing modifications to existing microarchitectures.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension", + "line_range": [ + 38, + 40 + ] + }, + { + "text": "Compilers can be unaware of the ext:zca[] extension and leave code compression to the assembler and linker, although a compression-aware compiler will generally be able to produce better results.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension", + "line_range": [ + 42, + 44 + ] + }, + { + "text": "It is important to note that the Zca extension is not designed to be a stand-alone ISA, and is meant to be used alongside a base ISA.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension", + "line_range": [ + 46, + 47 + ] + }, + { + "text": "shows the nine compressed instruction formats. CR, CI, and CSS can use any of the 32 RVI registers, but CIW, CL, CS, CA, and CB are limited to just 8 of them. lists these popular registers, which correspond to registers `x8` to `x15`.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats", + "line_range": [ + 53, + 62 + ] + }, + { + "text": "Note that there is a separate version of load and store instructions that use the stack pointer as the base address register, since saving to and restoring from the stack are so prevalent, and that they use the CI and CSS formats to allow access to all 32 data registers. CIW supplies an 8-bit immediate for the ADDI4SPN instruction.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats", + "line_range": [ + 53, + 62 + ] + }, + { + "text": "Compressed register-based floating-point loads and stores also use the CL and CS formats respectively, with the eight registers mapping to `f8` to `f15`. ) ) The formats were designed to keep bits for the two register source specifiers in the same place in all instructions, while the destination register field can move.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats", + "line_range": [ + 64, + 77 + ] + }, + { + "text": "When the full 5-bit destination register specifier is present, it is in the same place as in the 32-bit RISC-V encoding.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats", + "line_range": [ + 64, + 77 + ] + }, + { + "text": "Where immediates are sign-extended, the sign extension is always from bit 12.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats", + "line_range": [ + 64, + 77 + ] + }, + { + "text": "Immediate fields have been scrambled, as in the base specification, to reduce the number of immediate multiplexers required.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats", + "line_range": [ + 64, + 77 + ] + }, + { + "text": "For many ext:zca[] instructions, zero-valued immediates are disallowed and `x0` is not a valid 5-bit register specifier.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats", + "line_range": [ + 64, + 77 + ] + }, + { + "text": "These restrictions free up encoding space for other instructions requiring fewer operand bits.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats", + "line_range": [ + 64, + 77 + ] + }, + { + "text": ".Compressed 16-bit ext:zca[] instruction formats // [float=\"center\",align=\"center\",cols=\"1a, 2a\",frame=\"none\",grid=\"none\"] | | ! !Format ! Meaning !CR ! Register !CI ! Immediate !CSS ! Stack-relative Store !CIW ! Wide Immediate !CL ! Load !CS ! Store !CA ! Arithmetic !CB ! Branch/Arithmetic !CJ ! Jump ! | [float=\"left\",align=\"left\",cols=\"1,1,1,1,1,1,1\",options=\"noheader\"] ! ^!15 14 13 ^!12 ^!11 10 ^!9 8 7 ^!6 5 ^!4 3 2 ^!1 0 2+^!funct4 2+^!rd/rs1 2+^!rs2 ^! op ^!funct3 ^!imm 2+^!rd/rs1 2+^!imm ^! op ^!funct3 3+^!imm 2+^!rs2 ^! op ^!funct3 4+^!imm ^!rd{prime} ^! op ^!funct3 2+^!imm ^!rs1{prime} ^!imm ^!rd{prime} ^! op ^!funct3 2+^!imm ^!rs1{prime} ^! imm ^!rs2{prime} ^! op 3+^!funct6 ^!rd{prime}/rs1{prime} ^!funct2 ^!rs2{prime} ^! op ^!funct3 2+^!offset ^!rd{prime}/rs1{prime} 2+^!offset ^! op ^!funct3 5+^!jump target ^! op ! |", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats", + "line_range": [ + 79, + 112 + ] + }, + { + "text": ".Registers specified by the three-bit rs1{prime}, rs2{prime}, and rd{prime} fields of the CIW, CL, CS, CA, and CB formats. //[cols=\"20%,10%,10%,10%,10%,10%,10%,10%,10%\"] [float=\"center\",align=\"center\",cols=\"1a, 1a\",frame=\"none\",grid=\"none\"] | | ! !ext:zca[] Register Number !Integer Register Number !Integer Register ABI Name ! |", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats", + "line_range": [ + 114, + 126 + ] + }, + { + "text": "! !`000` !`001` !`010` !`011` !`100` !`101` !`110` !`111` !`x8` !`x9` !`x10` !`x11` !`x12` !`x13` !`x14`!`x15` !`s0` !`s1` !`a0` !`a1` !`a2` !`a3` !`a4`!`a5` ! |", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats", + "line_range": [ + 128, + 134 + ] + }, + { + "text": "To increase the reach of 16-bit instructions, data-transfer instructions use zero-extended immediates that are scaled by the size of the data in bytes: ×4 for words, ×8 for doublewords, and ×16 for quadwords.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Load and Store Instructions", + "line_range": [ + 138, + 140 + ] + }, + { + "text": "ext:zca[] provides two variants of loads and stores.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Load and Store Instructions", + "line_range": [ + 142, + 145 + ] + }, + { + "text": "One uses the ABI stack pointer, `x2`, as the base address and can target any data register.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Load and Store Instructions", + "line_range": [ + 142, + 145 + ] + }, + { + "text": "The other can reference one of 8 base address registers and one of 8 data registers.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Load and Store Instructions", + "line_range": [ + 142, + 145 + ] + }, + { + "text": "These instructions use the CI format.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Load and Store Instructions > Stack-Pointer-Based Loads and Stores", + "line_range": [ + 153, + 153 + ] + }, + { + "text": "C.LWSP loads a 32-bit value from memory into register rd.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Load and Store Instructions > Stack-Pointer-Based Loads and Stores", + "line_range": [ + 155, + 159 + ] + }, + { + "text": "It computes an effective address by adding the zero-extended offset, scaled by 4, to the stack pointer, `x2`.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Load and Store Instructions > Stack-Pointer-Based Loads and Stores", + "line_range": [ + 155, + 159 + ] + }, + { + "text": "It expands to `lw rd, offset(x2)`. C.LWSP is valid only when rd!=`x0`; the code points with rd=`x0` are reserved.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Load and Store Instructions > Stack-Pointer-Based Loads and Stores", + "line_range": [ + 155, + 159 + ] + }, + { + "text": "C.LDSP is an XLEN=64-only instruction that loads a 64-bit value from memory into register rd.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Load and Store Instructions > Stack-Pointer-Based Loads and Stores", + "line_range": [ + 161, + 167 + ] + }, + { + "text": "It computes its effective address by adding the zero-extended offset, scaled by 8, to the stack pointer, `x2`.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Load and Store Instructions > Stack-Pointer-Based Loads and Stores", + "line_range": [ + 161, + 167 + ] + }, + { + "text": "It expands to `ld rd, offset(x2)`. C.LDSP is valid only when rd!=`x0`; the code points with rd=`x0` are reserved.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Load and Store Instructions > Stack-Pointer-Based Loads and Stores", + "line_range": [ + 161, + 167 + ] + }, + { + "text": "These instructions use the CSS format.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Load and Store Instructions > Stack-Pointer-Based Loads and Stores", + "line_range": [ + 173, + 173 + ] + }, + { + "text": "C.SWSP stores a 32-bit value in register rs2 to memory.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Load and Store Instructions > Stack-Pointer-Based Loads and Stores", + "line_range": [ + 175, + 177 + ] + }, + { + "text": "It computes an effective address by adding the zero-extended offset, scaled by 4, to the stack pointer, `x2`.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Load and Store Instructions > Stack-Pointer-Based Loads and Stores", + "line_range": [ + 175, + 177 + ] + }, + { + "text": "It expands to `sw rs2, offset(x2)`.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Load and Store Instructions > Stack-Pointer-Based Loads and Stores", + "line_range": [ + 175, + 177 + ] + }, + { + "text": "C.SDSP is an XLEN=64-only instruction that stores a 64-bit value in register rs2 to memory.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Load and Store Instructions > Stack-Pointer-Based Loads and Stores", + "line_range": [ + 179, + 182 + ] + }, + { + "text": "It computes an effective address by adding the zero-extended offset, scaled by 8, to the stack pointer, `x2`.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Load and Store Instructions > Stack-Pointer-Based Loads and Stores", + "line_range": [ + 179, + 182 + ] + }, + { + "text": "It expands to `sd rs2, offset(x2)`.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Load and Store Instructions > Stack-Pointer-Based Loads and Stores", + "line_range": [ + 179, + 182 + ] + }, + { + "text": "include::images/wavedrom/reg-based-ldnstr.edn[] //.Compressed, register-based load and stores--these instructions use the CL format.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Load and Store Instructions > Register-Based Loads and Stores", + "line_range": [ + 186, + 190 + ] + }, + { + "text": "These instructions use the CL format.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Load and Store Instructions > Register-Based Loads and Stores", + "line_range": [ + 186, + 190 + ] + }, + { + "text": "C.LW loads a 32-bit value from memory into register `rd′`.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Load and Store Instructions > Register-Based Loads and Stores", + "line_range": [ + 192, + 195 + ] + }, + { + "text": "It computes an effective address by adding the zero-extended offset, scaled by 4, to the base address in register `rs1′`.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Load and Store Instructions > Register-Based Loads and Stores", + "line_range": [ + 192, + 195 + ] + }, + { + "text": "It expands to `lw rd′, offset(rs1′)`.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Load and Store Instructions > Register-Based Loads and Stores", + "line_range": [ + 192, + 195 + ] + }, + { + "text": "C.LD is an XLEN=64-only instruction that loads a 64-bit value from memory into register `rd′`.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Load and Store Instructions > Register-Based Loads and Stores", + "line_range": [ + 197, + 201 + ] + }, + { + "text": "It computes an effective address by adding the zero-extended offset, scaled by 8, to the base address in register `rs1′`.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Load and Store Instructions > Register-Based Loads and Stores", + "line_range": [ + 197, + 201 + ] + }, + { + "text": "It expands to `ld rd′, offset(rs1′)`.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Load and Store Instructions > Register-Based Loads and Stores", + "line_range": [ + 197, + 201 + ] + }, + { + "text": "include::images/wavedrom/c-cs-format-ls.edn[] //.Compressed, CS format load and store--these instructions use the CS format.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Load and Store Instructions > Register-Based Loads and Stores", + "line_range": [ + 203, + 206 + ] + }, + { + "text": "These instructions use the CS format.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Load and Store Instructions > Register-Based Loads and Stores", + "line_range": [ + 208, + 208 + ] + }, + { + "text": "C.SW stores a 32-bit value in register `rs2′` to memory.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Load and Store Instructions > Register-Based Loads and Stores", + "line_range": [ + 210, + 213 + ] + }, + { + "text": "It computes an effective address by adding the zero-extended offset, scaled by 4, to the base address in register `rs1′`.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Load and Store Instructions > Register-Based Loads and Stores", + "line_range": [ + 210, + 213 + ] + }, + { + "text": "It expands to `sw rs2′, offset(rs1′)`.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Load and Store Instructions > Register-Based Loads and Stores", + "line_range": [ + 210, + 213 + ] + }, + { + "text": "C.SD is an XLEN=64-only instruction that stores a 64-bit value in register `rs2′` to memory.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Load and Store Instructions > Register-Based Loads and Stores", + "line_range": [ + 215, + 219 + ] + }, + { + "text": "It computes an effective address by adding the zero-extended offset, scaled by 8, to the base address in register `rs1′`.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Load and Store Instructions > Register-Based Loads and Stores", + "line_range": [ + 215, + 219 + ] + }, + { + "text": "It expands to `sd rs2′, offset(rs1′)`.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Load and Store Instructions > Register-Based Loads and Stores", + "line_range": [ + 215, + 219 + ] + }, + { + "text": "ext:zca[] provides unconditional jump instructions and conditional branch instructions.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Control Transfer Instructions", + "line_range": [ + 223, + 225 + ] + }, + { + "text": "As with base RVI instructions, the offsets of all ext:zca[] control transfer instructions are in multiples of 2 bytes.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Control Transfer Instructions", + "line_range": [ + 223, + 225 + ] + }, + { + "text": "include::images/wavedrom/c-cj-format-ls.edn[] //.Compressed, CJ format load and store--these instructions use the CJ format.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Control Transfer Instructions", + "line_range": [ + 227, + 230 + ] + }, + { + "text": "These instructions use the CJ format.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Control Transfer Instructions", + "line_range": [ + 232, + 232 + ] + }, + { + "text": "C.J performs an unconditional control transfer.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Control Transfer Instructions", + "line_range": [ + 234, + 237 + ] + }, + { + "text": "The offset is sign-extended and added to the `pc` to form the jump target address. C.J can therefore target a {pm}2 KiB range. C.J expands to `jal x0, offset`.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Control Transfer Instructions", + "line_range": [ + 234, + 237 + ] + }, + { + "text": "C.JAL is an XLEN=32-only instruction that performs the same operation as C.J, but additionally writes the address of the instruction following the jump (`pc+2`) to the link register, `x1`. C.JAL expands to `jal x1, offset`.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Control Transfer Instructions", + "line_range": [ + 239, + 242 + ] + }, + { + "text": "include::images/wavedrom/c-cr-format-ls.edn[] //.Compressed, CR format load and store--these instructions use the CR format.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Control Transfer Instructions", + "line_range": [ + 244, + 247 + ] + }, + { + "text": "These instructions use the CR format.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Control Transfer Instructions", + "line_range": [ + 249, + 249 + ] + }, + { + "text": "C.JR (jump register) performs an unconditional control transfer to the address in register rs1. C.JR expands to `jalr x0, 0(rs1)`. C.JR is valid only when rs1!=`x0`; the code point with rs1=`x0` is reserved.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Control Transfer Instructions", + "line_range": [ + 251, + 255 + ] + }, + { + "text": "C.JALR (jump and link register) performs the same operation as C.JR, but additionally writes the address of the instruction following the jump (`pc`+2) to the link register, `x1`. C.JALR expands to `jalr x1, 0(rs1)`. C.JALR is valid only when rs1!=`x0`; the code point with rs1=`x0` corresponds to the C.EBREAK instruction.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Control Transfer Instructions", + "line_range": [ + 257, + 264 + ] + }, + { + "text": "include::images/wavedrom/c-cb-format-ls.edn[] //.Compressed, CB format load and store--these instructions use the CB format.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Control Transfer Instructions", + "line_range": [ + 266, + 269 + ] + }, + { + "text": "These instructions use the CB format.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Control Transfer Instructions", + "line_range": [ + 271, + 271 + ] + }, + { + "text": "C.BEQZ performs conditional control transfers.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Control Transfer Instructions", + "line_range": [ + 273, + 277 + ] + }, + { + "text": "The offset is sign-extended and added to the `pc` to form the branch target address.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Control Transfer Instructions", + "line_range": [ + 273, + 277 + ] + }, + { + "text": "It can therefore target a {pm}256 B range. C.BEQZ takes the branch if the value in register rs1′ is zero.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Control Transfer Instructions", + "line_range": [ + 273, + 277 + ] + }, + { + "text": "It expands to `beq rs1′, x0, offset`.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Control Transfer Instructions", + "line_range": [ + 273, + 277 + ] + }, + { + "text": "C.BNEZ is defined analogously, but it takes the branch if rs1′ contains a nonzero value.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Control Transfer Instructions", + "line_range": [ + 279, + 281 + ] + }, + { + "text": "It expands to `bne rs1′, x0, offset`.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Control Transfer Instructions", + "line_range": [ + 279, + 281 + ] + }, + { + "text": "ext:zca[] provides several instructions for integer arithmetic and constant generation.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions", + "line_range": [ + 285, + 286 + ] + }, + { + "text": "The two constant-generation instructions both use the CI instruction format and can target any integer register.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Constant-Generation Instructions", + "line_range": [ + 290, + 291 + ] + }, + { + "text": "include::images/wavedrom/c-integer-const-gen.edn[] //.Integer constant generation format.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Constant-Generation Instructions", + "line_range": [ + 293, + 296 + ] + }, + { + "text": "C.LI loads the sign-extended 6-bit immediate, imm, into register rd. C.LI expands into `addi rd, x0, imm`.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Constant-Generation Instructions", + "line_range": [ + 298, + 300 + ] + }, + { + "text": "The C.LI code points with rd=`x0` are HINTs.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Constant-Generation Instructions", + "line_range": [ + 298, + 300 + ] + }, + { + "text": "C.LUI loads the non-zero 6-bit immediate field into bits 17–12 of the destination register, clears the bottom 12 bits, and sign-extends bit 17 into all higher bits of the destination. C.LUI expands into `lui rd, imm`. C.LUI is valid only when rd!=`x2`, and when the immediate is not equal to zero.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Constant-Generation Instructions", + "line_range": [ + 302, + 312 + ] + }, + { + "text": "The code points with imm=0 are reserved.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Constant-Generation Instructions", + "line_range": [ + 302, + 312 + ] + }, + { + "text": "The code points with rd=`x2` and imm!=0 correspond to the C.ADDI16SP instruction.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Constant-Generation Instructions", + "line_range": [ + 302, + 312 + ] + }, + { + "text": "The code points with rd=`x0` and imm!=0 are HINTs.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Constant-Generation Instructions", + "line_range": [ + 302, + 312 + ] + }, + { + "text": "These integer register-immediate operations are encoded in the CI format and perform operations on an integer register and a 6-bit immediate.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Immediate Operations", + "line_range": [ + 317, + 318 + ] + }, + { + "text": "include::images/wavedrom/c-int-reg-immed.edn[] //.Integer register-immediate format.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Immediate Operations", + "line_range": [ + 320, + 323 + ] + }, + { + "text": "C.ADDI adds the non-zero sign-extended 6-bit immediate to the value in register rd then writes the result to rd. C.ADDI expands into `addi rd, rd, imm`.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Immediate Operations", + "line_range": [ + 325, + 330 + ] + }, + { + "text": "The code points with rd!=0 and imm=0 are HINTs.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Immediate Operations", + "line_range": [ + 325, + 330 + ] + }, + { + "text": "The code points with rd=`x0` encode the C.NOP instruction, of which the code points with imm!=0 are HINTs.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Immediate Operations", + "line_range": [ + 325, + 330 + ] + }, + { + "text": "C.ADDIW is an XLEN=64-only instruction that performs the same computation but produces a 32-bit result, then sign-extends result to 64 bits. C.ADDIW expands into `addiw rd, rd, imm`.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Immediate Operations", + "line_range": [ + 332, + 338 + ] + }, + { + "text": "The immediate can be zero for C.ADDIW, where this corresponds to `sext.w rd`. C.ADDIW is valid only when rd!=`x0`; the code points with rd=`x0` are reserved.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Immediate Operations", + "line_range": [ + 332, + 338 + ] + }, + { + "text": "C.ADDI16SP (add immediate to stack pointer) shares the opcode with C.LUI, but has a destination field of `x2`. C.ADDI16SP adds the non-zero sign-extended 6-bit immediate to the value in the stack pointer (`sp=x2`), where the immediate is scaled to represent multiples of 16 in the range [-512, 496]. C.ADDI16SP is used to adjust the stack pointer in procedure prologues and epilogues.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Immediate Operations", + "line_range": [ + 340, + 348 + ] + }, + { + "text": "It expands into `addi x2, x2, nzimm[9:4]`. C.ADDI16SP is valid only when nzimm!=0; the code point with nzimm=0 is reserved.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Immediate Operations", + "line_range": [ + 340, + 348 + ] + }, + { + "text": "include::images/wavedrom/c-ciw.edn[] //.CIW format. C.ADDI4SPN (add immediate to stack pointer, non-destructive) is a CIW-format instruction that adds a zero-extended non-zero immediate, scaled by 4, to the stack pointer, `x2`, and writes the result to `rd′`.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Immediate Operations", + "line_range": [ + 350, + 362 + ] + }, + { + "text": "This instruction is used to generate pointers to stack-allocated variables, and expands to `addi rd′, x2, nzuimm[9:2]`. C.ADDI4SPN is valid only when nzuimm!=0; the code points with nzuimm=0 are reserved.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Immediate Operations", + "line_range": [ + 350, + 362 + ] + }, + { + "text": "include::images/wavedrom/c-ci.edn[] //.CI format.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Immediate Operations", + "line_range": [ + 364, + 367 + ] + }, + { + "text": "C.SLLI is a CI-format instruction that performs a logical left shift of the value in register rd then writes the result to rd.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Immediate Operations", + "line_range": [ + 369, + 372 + ] + }, + { + "text": "The shift amount is encoded in the shamt field. C.SLLI expands into `slli rd, rd, shamt[5:0]`.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Immediate Operations", + "line_range": [ + 369, + 372 + ] + }, + { + "text": "The C.SLLI code points with shamt=0 or with rd=`x0` are HINTs.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Immediate Operations", + "line_range": [ + 374, + 374 + ] + }, + { + "text": "For XLEN=32, shamt[5] must be zero; the code points with shamt[5]=1 are designated for custom extensions.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Immediate Operations", + "line_range": [ + 376, + 377 + ] + }, + { + "text": "C.SRLI is a CB-format instruction that performs a logical right shift of the value in register rd′ then writes the result to rd′.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Immediate Operations", + "line_range": [ + 385, + 388 + ] + }, + { + "text": "The shift amount is encoded in the shamt field. C.SRLI expands into `srli rd′, rd′, shamt`.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Immediate Operations", + "line_range": [ + 385, + 388 + ] + }, + { + "text": "The C.SRLI code points with shamt=0 are HINTs.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Immediate Operations", + "line_range": [ + 390, + 390 + ] + }, + { + "text": "For XLEN=32, shamt[5] must be zero; the code points with shamt[5]=1 are designated for custom extensions.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Immediate Operations", + "line_range": [ + 392, + 393 + ] + }, + { + "text": "C.SRAI is defined analogously to C.SRLI, but instead performs an arithmetic right shift. C.SRAI expands to `srai rd′, rd′, shamt`.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Immediate Operations", + "line_range": [ + 395, + 397 + ] + }, + { + "text": "include::images/wavedrom/c-andi.edn[] //.C.ANDI format", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Immediate Operations", + "line_range": [ + 399, + 402 + ] + }, + { + "text": "C.ANDI is a CB-format instruction that computes the bitwise AND of the value in register rd′ and the sign-extended 6-bit immediate, then writes the result to rd′. C.ANDI expands to `andi rd′, rd′, imm`.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Immediate Operations", + "line_range": [ + 404, + 407 + ] + }, + { + "text": "include::images/wavedrom/c-int-reg-to-reg-cr-format.edn[] //C.CR format ) These instructions use the CR format.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Register Operations", + "line_range": [ + 412, + 416 + ] + }, + { + "text": "C.MV copies the value in register rs2 into register rd. C.MV expands into `add rd, x0, rs2`. C.MV is valid only when rs2!=`x0`; the code points with rs2=`x0` correspond to the C.JR instruction.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Register Operations", + "line_range": [ + 418, + 422 + ] + }, + { + "text": "The code points with rs2!=`x0` and rd=`x0` are HINTs.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Register Operations", + "line_range": [ + 418, + 422 + ] + }, + { + "text": "C.ADD adds the values in registers rd and rs2 and writes the result to register rd. C.ADD expands into `add rd, rd, rs2`. C.ADD is only valid when rs2!=`x0`; the code points with rs2=`x0` correspond to the C.JALR and C.EBREAK instructions.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Register Operations", + "line_range": [ + 424, + 429 + ] + }, + { + "text": "The code points with rs2!=`x0` and rd=`x0` are HINTs.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Register Operations", + "line_range": [ + 424, + 429 + ] + }, + { + "text": "include::images/wavedrom/c-int-reg-to-reg-ca-format.edn[] //C.CA format )", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Register Operations", + "line_range": [ + 431, + 434 + ] + }, + { + "text": "These instructions use the CA format.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Register Operations", + "line_range": [ + 436, + 436 + ] + }, + { + "text": "`C.AND` computes the bitwise `AND` of the values in registers rd′ and rs2′, then writes the result to register rd′. `C.AND` expands into `and rd′, rd′, rs2′`.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Register Operations", + "line_range": [ + 438, + 441 + ] + }, + { + "text": "`C.OR` computes the bitwise `OR` of the values in registers rd′ and rs2′, then writes the result to register rd′. `C.OR` expands into `or rd′, rd′, rs2′`.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Register Operations", + "line_range": [ + 443, + 446 + ] + }, + { + "text": "`C.XOR` computes the bitwise `XOR` of the values in registers rd′ and rs2′, then writes the result to register rd′. `C.XOR` expands into `xor rd′, rd′, rs2′`.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Register Operations", + "line_range": [ + 448, + 451 + ] + }, + { + "text": "`C.SUB` subtracts the value in register rs2′ from the value in register rd′, then writes the result to register rd′. `C.SUB` expands into `sub rd′, rd′, rs2′`.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Register Operations", + "line_range": [ + 453, + 456 + ] + }, + { + "text": "`C.ADDW` is an XLEN=64-only instruction that adds the values in registers rd′ and rs2′, then sign-extends the lower 32 bits of the sum before writing the result to register rd′. `C.ADDW` expands into `addw rd′, rd′, rs2′`.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Register Operations", + "line_range": [ + 458, + 462 + ] + }, + { + "text": "`C.SUBW` is an XLEN=64-only instruction that subtracts the value in register rs2′ from the value in register rd′, then sign-extends the lower 32 bits of the difference before writing the result to register rd′. `C.SUBW` expands into `subw rd′, rd′, rs2′`.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Integer Register-Register Operations", + "line_range": [ + 464, + 468 + ] + }, + { + "text": "include::images/wavedrom/c-def-illegal-inst.edn[] )", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Defined Illegal Instruction", + "line_range": [ + 472, + 474 + ] + }, + { + "text": "A 16-bit instruction with all bits zero is permanently reserved as an illegal instruction.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Defined Illegal Instruction", + "line_range": [ + 476, + 477 + ] + }, + { + "text": "include::images/wavedrom/c-nop-instr.edn[] )", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > NOP Instruction", + "line_range": [ + 481, + 483 + ] + }, + { + "text": "`C.NOP` is a CI-format instruction that does not change any user-visible state, except for advancing the `pc` and incrementing any applicable performance counters. `C.NOP` expands to `nop`.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > NOP Instruction", + "line_range": [ + 485, + 489 + ] + }, + { + "text": "The `C.NOP` code points with imm!=0 encode HINTs.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > NOP Instruction", + "line_range": [ + 485, + 489 + ] + }, + { + "text": "Debuggers can use the `C.EBREAK` instruction, which expands to `ebreak`, to cause control to be transferred back to the debugging environment. `C.EBREAK` shares the opcode with the `C.ADD` instruction, but with rd and rs2 both zero, thus can also use the `CR` format.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Integer Computational Instructions > Breakpoint Instruction", + "line_range": [ + 497, + 500 + ] + }, + { + "text": "On implementations that support the ext:Zca[] extension, compressed forms of instructions permitted inside constrained LR/SC sequences, as described in , are also permitted inside constrained LR/SC sequences.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > Usage of Compressed Instructions in LR/SC Sequences", + "line_range": [ + 504, + 507 + ] + }, + { + "text": "A portion of the ext:zca[] encoding space is reserved for microarchitectural HINTs.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > HINT Instructions", + "line_range": [ + 512, + 517 + ] + }, + { + "text": "Like the HINTs in the RV32I base ISA (see ), these instructions do not modify any architectural state, except for advancing the `pc` and any applicable performance counters. HINTs are executed as no-ops on implementations that ignore them.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > HINT Instructions", + "line_range": [ + 512, + 517 + ] + }, + { + "text": "ext:zca[] HINTs are encoded as computational instructions that do not modify the architectural state, either because rd=`x0` (e.g. `C.ADD x0, t0`), or because rd is overwritten with a copy of itself (e.g. `C.ADDI t0, 0`).", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > HINT Instructions", + "line_range": [ + 519, + 522 + ] + }, + { + "text": "ext:zca[] HINTs do not necessarily expand to their RVI HINT counterparts.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > HINT Instructions", + "line_range": [ + 524, + 526 + ] + }, + { + "text": "For example, `C.ADD` x0, a0 might not encode the same HINT as `ADD` x0, x0, a0.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > HINT Instructions", + "line_range": [ + 524, + 526 + ] + }, + { + "text": "lists all ext:zca[] HINT code points.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > HINT Instructions", + "line_range": [ + 528, + 530 + ] + }, + { + "text": "For XLEN=32, 78% of the HINT space is reserved for standard HINTs.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > HINT Instructions", + "line_range": [ + 528, + 530 + ] + }, + { + "text": "The remainder of the HINT space is designated for custom HINTs; no standard HINTs will ever be defined in this subspace.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > HINT Instructions", + "line_range": [ + 528, + 530 + ] + }, + { + "text": ".ext:zca[] HINT instructions. [cols=\"<,<,>,<\",options=\"header\",] | |Instruction |Constraints |Code Points |Purpose", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > HINT Instructions", + "line_range": [ + 532, + 536 + ] + }, + { + "text": "|C.NOP |imm!=0 |63 .6+.^|Designated for future standard use", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > HINT Instructions", + "line_range": [ + 538, + 538 + ] + }, + { + "text": "|C.ADDI | rd!=`x0`, imm=0 |31", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > HINT Instructions", + "line_range": [ + 540, + 540 + ] + }, + { + "text": "|C.LUI | rd=`x0`, imm!=0 |63", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > HINT Instructions", + "line_range": [ + 544, + 544 + ] + }, + { + "text": "|C.MV | rd=`x0`, rs2!=`x0` |31", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > HINT Instructions", + "line_range": [ + 546, + 546 + ] + }, + { + "text": "|C.ADD | rd=`x0`, rs2!=`x0`, rs2!=`x2-x5` | 27", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > HINT Instructions", + "line_range": [ + 548, + 548 + ] + }, + { + "text": "|C.ADD | rd=`x0`, rs2=`x2-x5` |4|(rs2=x2) C.NTL.P1 (rs2=x3) C.NTL.PALL (rs2=x4) C.NTL.S1 (rs2=x5) C.NTL.ALL", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > HINT Instructions", + "line_range": [ + 550, + 550 + ] + }, + { + "text": "|C.SLLI |rd=`x0` or imm=0 |63 (RV32), 95 (RV64) .3+.^|Designated for custom use", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > HINT Instructions", + "line_range": [ + 552, + 552 + ] + }, + { + "text": "shows a map of the major opcodes for the compressed extensions.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > ext:zca[] Instruction Set Listings", + "line_range": [ + 561, + 570 + ] + }, + { + "text": "Each row of the table corresponds to one quadrant of the encoding space.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > ext:zca[] Instruction Set Listings", + "line_range": [ + 561, + 570 + ] + }, + { + "text": "The last quadrant, which has the two least-significant bits set, corresponds to instructions wider than 16 bits, including those in the base ISAs.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > ext:zca[] Instruction Set Listings", + "line_range": [ + 561, + 570 + ] + }, + { + "text": "Several instructions are only valid for certain operands; when invalid, they are marked either RES to indicate that the opcode is reserved for future standard extensions;", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > ext:zca[] Instruction Set Listings", + "line_range": [ + 561, + 570 + ] + }, + { + "text": "Custom to indicate that the opcode is designated for custom extensions; or HINT to indicate that the opcode is reserved for microarchitectural hints (see ).", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > ext:zca[] Instruction Set Listings", + "line_range": [ + 561, + 570 + ] + }, + { + "text": ".ext:zca[] opcode map. | 2+>|inst[15:13] + inst[1:0] ^.^s|000 ^.^s|001 ^.^s|010 ^.^s|011 ^.^s|100 ^.^s|101 ^.^s|110 ^.^s|111 |", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > ext:zca[] Instruction Set Listings", + "line_range": [ + 574, + 579 + ] + }, + { + "text": "2+>.^|00 .^|ADDI4SPN ^.^|FLD + FLD ^.^| LW ^.^| FLW + LD ^.^| Reserved ^.^| FSD + FSD ^.^| SW ^.^| FSW + SD ^.^| RV32 + RV64", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > ext:zca[] Instruction Set Listings", + "line_range": [ + 581, + 587 + ] + }, + { + "text": "2+>.^|01 ^.^|ADDI ^.^|JAL + ADDIW ^.^|LI ^.^|LUI/ADDI16SP ^.^|MISC-ALU ^.^|J ^.^|BEQZ ^.^|BNEZ ^.^|RV32 + RV64", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > ext:zca[] Instruction Set Listings", + "line_range": [ + 589, + 591 + ] + }, + { + "text": "2+>.^|10 ^.^|SLLI ^.^|FLDSP + FLDSP ^.^|LWSP ^.^|FLWSP + LDSP ^.^|J[AL]R/MV/ADD ^.^|FSDSP + FSDSP ^.^|SWSP ^.^|FSWSP + SDSP ^.^|RV32 + RV64", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > ext:zca[] Instruction Set Listings", + "line_range": [ + 593, + 598 + ] + }, + { + "text": ", , and list the ext:zca[] instructions.", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > ext:zca[] Instruction Set Listings", + "line_range": [ + 603, + 603 + ] + }, + { + "text": ".ext:zca[] Instruction listing, Quadrant 0 include::images/bytefield/rvc-instr-quad0.edn[]", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > ext:zca[] Instruction Set Listings", + "line_range": [ + 605, + 607 + ] + }, + { + "text": ".ext:zca[] Instruction listing, Quadrant 1 include::images/bytefield/rvc-instr-quad1.edn[]", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > ext:zca[] Instruction Set Listings", + "line_range": [ + 609, + 611 + ] + }, + { + "text": ".ext:zca[] Instruction listing, Quadrant 2 include::images/bytefield/rvc-instr-quad2.edn[]", + "section": "Preamble > ext:zca[] Integer Compressed Instructions Extension > Compressed Instruction Formats > ext:zca[] Instruction Set Listings", + "line_range": [ + 613, + 615 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zcb.json b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zcb.json new file mode 100644 index 0000000000..da1fa783b6 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zcb.json @@ -0,0 +1,926 @@ +{ + "source_file": "src/unpriv/zcb.adoc", + "total": 115, + "sentences": [ + { + "text": "The ext:zcb[] extension adds several compressed instructions which, like those in the extlink:zca[] extension, expand into a single 32-bit instruction.", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions", + "line_range": [ + 3, + 5 + ] + }, + { + "text": "The ext:zcb[] extension depends on the ext:zca[] extension.", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions", + "line_range": [ + 3, + 5 + ] + }, + { + "text": "As shown on the individual instruction pages, many of the instructions in Zcb depend upon another extension being implemented.", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions", + "line_range": [ + 7, + 11 + ] + }, + { + "text": "For example, inst:c.mul[] is only implemented if extlink:m[] or extlink:zmmul[] is implemented, and inst:c.sext.b[] is only implemented if extlink:zbb[] is implemented.", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions", + "line_range": [ + 7, + 11 + ] + }, + { + "text": "| |RV32 |RV64 |Mnemonic |Instruction", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions", + "line_range": [ + 13, + 18 + ] + }, + { + "text": "|yes |yes |c.lbu rd', uimm(rs1') |", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions", + "line_range": [ + 20, + 23 + ] + }, + { + "text": "|yes |yes |c.lhu rd', uimm(rs1') |", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions", + "line_range": [ + 25, + 28 + ] + }, + { + "text": "|yes |yes |c.lh rd', uimm(rs1') |", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions", + "line_range": [ + 30, + 33 + ] + }, + { + "text": "|yes |yes |c.sb rs2', uimm(rs1') |", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions", + "line_range": [ + 35, + 38 + ] + }, + { + "text": "|yes |yes |c.sh rs2', uimm(rs1') |", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions", + "line_range": [ + 40, + 43 + ] + }, + { + "text": "|yes |yes |c.zext.b rsd' |", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions", + "line_range": [ + 45, + 48 + ] + }, + { + "text": "|yes |yes |c.sext.b rsd' |", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions", + "line_range": [ + 50, + 53 + ] + }, + { + "text": "|yes |yes |c.zext.h rsd' |", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions", + "line_range": [ + 55, + 58 + ] + }, + { + "text": "|yes |yes |c.sext.h rsd' |", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions", + "line_range": [ + 60, + 63 + ] + }, + { + "text": "|yes |yes |c.mul rsd', rs2' |", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions", + "line_range": [ + 75, + 78 + ] + }, + { + "text": "[insns-clbu,reftext=\"Load unsigned byte, 16-bit encoding\"]", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions", + "line_range": [ + 82, + 82 + ] + }, + { + "text": "Load unsigned byte, 16-bit encoding", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu", + "line_range": [ + 87, + 87 + ] + }, + { + "text": "[wavedrom, , svg] .... {reg:[ { bits: 2, name: 0x0, attr: ['C0'] }, { bits: 3, name: 'rd\\'' }, { bits: 2, name: 'uimm[0|1]' }, { bits: 3, name: 'rs1\\'' }, { bits: 3, name: 0x0 }, { bits: 3, name: 0x4, attr: ['FUNCT3'] }, ],config:{bits:16}} ....", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu", + "line_range": [ + 95, + 105 + ] + }, + { + "text": "The immediate offset is formed as follows:", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu", + "line_range": [ + 107, + 107 + ] + }, + { + "text": "[source,sail] -- uimm[31:2] = 0; uimm[1] = encoding[5]; uimm[0] = encoding[6]; --", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu", + "line_range": [ + 109, + 114 + ] + }, + { + "text": "This instruction loads a byte from the memory address formed by adding rs1' to the zero extended immediate uimm.", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu", + "line_range": [ + 118, + 118 + ] + }, + { + "text": "The resulting byte is zero extended to XLEN bits and is written to rd'.", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu", + "line_range": [ + 118, + 118 + ] + }, + { + "text": "None //32-bit equivalent: //", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu", + "line_range": [ + 122, + 124 + ] + }, + { + "text": "[source,sail] ---- //This is not SAIL, it's pseudocode.", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu", + "line_range": [ + 128, + 130 + ] + }, + { + "text": "The SAIL hasn't been written yet.", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu", + "line_range": [ + 128, + 130 + ] + }, + { + "text": "X(rdc) = EXTZ(mem[X(rs1c)+EXTZ(uimm)][7..0]); ----", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu", + "line_range": [ + 132, + 133 + ] + }, + { + "text": "<<< [insns-clhu,reftext=\"Load unsigned halfword, 16-bit encoding\"]", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu", + "line_range": [ + 135, + 136 + ] + }, + { + "text": "Load unsigned halfword, 16-bit encoding", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.lhu", + "line_range": [ + 141, + 141 + ] + }, + { + "text": "[wavedrom, , svg] .... {reg:[ { bits: 2, name: 0x0, attr: ['C0'] }, { bits: 3, name: 'rd\\'' }, { bits: 1, name: 'uimm[1]' }, { bits: 1, name: 0x0 }, { bits: 3, name: 'rs1\\'' }, { bits: 3, name: 0x1 }, { bits: 3, name: 0x4, attr: ['FUNCT3'] }, ],config:{bits:16}} ....", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.lhu", + "line_range": [ + 149, + 160 + ] + }, + { + "text": "The immediate offset is formed as follows:", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.lhu", + "line_range": [ + 162, + 162 + ] + }, + { + "text": "[source,sail] ---- uimm[31:2] = 0; uimm[1] = encoding[5]; uimm[0] = 0; ----", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.lhu", + "line_range": [ + 164, + 169 + ] + }, + { + "text": "This instruction loads a halfword from the memory address formed by adding rs1' to the zero extended immediate uimm.", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.lhu", + "line_range": [ + 173, + 173 + ] + }, + { + "text": "The resulting halfword is zero extended to XLEN bits and is written to rd'.", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.lhu", + "line_range": [ + 173, + 173 + ] + }, + { + "text": "None //32-bit equivalent: // //", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.lhu", + "line_range": [ + 177, + 180 + ] + }, + { + "text": "[source,sail] -- //This is not SAIL, it's pseudocode.", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.lhu", + "line_range": [ + 184, + 186 + ] + }, + { + "text": "The SAIL hasn't been written yet.", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.lhu", + "line_range": [ + 184, + 186 + ] + }, + { + "text": "X(rdc) = EXTZ(loadmem[X(rs1c)+EXTZ(uimm)][15..0]); --", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.lhu", + "line_range": [ + 188, + 189 + ] + }, + { + "text": "<<< [insns-clh,reftext=\"Load signed halfword, 16-bit encoding\"]", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.lhu", + "line_range": [ + 191, + 192 + ] + }, + { + "text": "Load signed halfword, 16-bit encoding", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.lh", + "line_range": [ + 197, + 197 + ] + }, + { + "text": "[wavedrom, , svg] .... {reg:[ { bits: 2, name: 0x0, attr: ['C0'] }, { bits: 3, name: 'rd\\'' }, { bits: 1, name: 'uimm[1]' }, { bits: 1, name: 0x1 }, { bits: 3, name: 'rs1\\'' }, { bits: 3, name: 0x1 }, { bits: 3, name: 0x4, attr: ['FUNCT3'] }, ],config:{bits:16}} ....", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.lh", + "line_range": [ + 205, + 216 + ] + }, + { + "text": "The immediate offset is formed as follows:", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.lh", + "line_range": [ + 218, + 218 + ] + }, + { + "text": "[source,sail] ---- uimm[31:2] = 0; uimm[1] = encoding[5]; uimm[0] = 0; ----", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.lh", + "line_range": [ + 220, + 225 + ] + }, + { + "text": "This instruction loads a halfword from the memory address formed by adding rs1' to the zero extended immediate uimm.", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.lh", + "line_range": [ + 229, + 229 + ] + }, + { + "text": "The resulting halfword is sign extended to XLEN bits and is written to rd'.", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.lh", + "line_range": [ + 229, + 229 + ] + }, + { + "text": "None //32-bit equivalent: // //", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.lh", + "line_range": [ + 233, + 236 + ] + }, + { + "text": "[source,sail] ---- //This is not SAIL, it's pseudocode.", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.lh", + "line_range": [ + 240, + 242 + ] + }, + { + "text": "The SAIL hasn't been written yet.", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.lh", + "line_range": [ + 240, + 242 + ] + }, + { + "text": "X(rdc) = EXTS(loadmem[X(rs1c)+EXTZ(uimm)][15..0]); ----", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.lh", + "line_range": [ + 244, + 245 + ] + }, + { + "text": "<<< [insns-csb,reftext=\"Store byte, 16-bit encoding\"]", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.lh", + "line_range": [ + 247, + 248 + ] + }, + { + "text": "Store byte, 16-bit encoding", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.sb", + "line_range": [ + 253, + 253 + ] + }, + { + "text": "[wavedrom, , svg] .... {reg:[ { bits: 2, name: 0x0, attr: ['C0'] }, { bits: 3, name: 'rs2\\'' }, { bits: 2, name: 'uimm[0|1]' }, { bits: 3, name: 'rs1\\'' }, { bits: 3, name: 0x2 }, { bits: 3, name: 0x4, attr: ['FUNCT3'] }, ],config:{bits:16}} ....", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.sb", + "line_range": [ + 261, + 271 + ] + }, + { + "text": "The immediate offset is formed as follows:", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.sb", + "line_range": [ + 273, + 273 + ] + }, + { + "text": "[source,sail] ---- uimm[31:2] = 0; uimm[1] = encoding[5]; uimm[0] = encoding[6]; ----", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.sb", + "line_range": [ + 275, + 280 + ] + }, + { + "text": "This instruction stores the least significant byte of rs2' to the memory address formed by adding rs1' to the zero extended immediate uimm.", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.sb", + "line_range": [ + 284, + 284 + ] + }, + { + "text": "None // //32-bit equivalent: // //", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.sb", + "line_range": [ + 288, + 292 + ] + }, + { + "text": "[source,sail] -- //This is not SAIL, it's pseudocode.", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.sb", + "line_range": [ + 296, + 298 + ] + }, + { + "text": "The SAIL hasn't been written yet.", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.sb", + "line_range": [ + 296, + 298 + ] + }, + { + "text": "mem[X(rs1c)+EXTZ(uimm)][7..0] = X(rs2c) --", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.sb", + "line_range": [ + 300, + 301 + ] + }, + { + "text": "<<< [insns-csh,reftext=\"Store halfword, 16-bit encoding\"]", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.sb", + "line_range": [ + 303, + 304 + ] + }, + { + "text": "Store halfword, 16-bit encoding", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.sh", + "line_range": [ + 309, + 309 + ] + }, + { + "text": "[wavedrom, , svg] .... {reg:[ { bits: 2, name: 0x0, attr: ['C0'] }, { bits: 3, name: 'rs2\\'' }, { bits: 1, name: 'uimm[1]' }, { bits: 1, name: '0' }, { bits: 3, name: 'rs1\\'' }, { bits: 3, name: 0x3 }, { bits: 3, name: 0x4, attr: ['FUNCT3'] }, ],config:{bits:16}} ....", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.sh", + "line_range": [ + 317, + 328 + ] + }, + { + "text": "The immediate offset is formed as follows:", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.sh", + "line_range": [ + 330, + 330 + ] + }, + { + "text": "[source,sail] ---- uimm[31:2] = 0; uimm[1] = encoding[5]; uimm[0] = 0; ----", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.sh", + "line_range": [ + 332, + 337 + ] + }, + { + "text": "This instruction stores the least significant halfword of rs2' to the memory address formed by adding rs1' to the zero extended immediate uimm.", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.sh", + "line_range": [ + 341, + 341 + ] + }, + { + "text": "None // //32-bit equivalent: // //", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.sh", + "line_range": [ + 345, + 349 + ] + }, + { + "text": "Operation:: [source,sail] ---- //This is not SAIL, it's pseudocode.", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.sh", + "line_range": [ + 351, + 354 + ] + }, + { + "text": "The SAIL hasn't been written yet.", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.sh", + "line_range": [ + 351, + 354 + ] + }, + { + "text": "mem[X(rs1c)+EXTZ(uimm)][15..0] = X(rs2c) ----", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.sh", + "line_range": [ + 356, + 357 + ] + }, + { + "text": "<<< [insns-czextb,reftext=\"Zero extend byte, 16-bit encoding\"]", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.sh", + "line_range": [ + 359, + 360 + ] + }, + { + "text": "Zero extend byte, 16-bit encoding", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.zext.b", + "line_range": [ + 365, + 365 + ] + }, + { + "text": "[wavedrom, , svg] .... {reg:[ { bits: 2, name: 0x1, attr: ['C1'] }, { bits: 3, name: 0x0, attr: ['C.ZEXT.B'] }, { bits: 2, name: 0x3, attr: ['FUNCT2'] }, { bits: 3, name: 'rd\\'/rs1\\'', attr: ['SRCDST'] }, { bits: 3, name: 0x7 }, { bits: 3, name: 0x4, attr: ['FUNCT3'] }, ],config:{bits:16}} ....", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.zext.b", + "line_range": [ + 373, + 383 + ] + }, + { + "text": "This instruction takes a single source/destination operand.", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.zext.b", + "line_range": [ + 387, + 389 + ] + }, + { + "text": "It zero-extends the least-significant byte of the operand to XLEN bits by inserting zeros into all of the bits more significant than 7.", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.zext.b", + "line_range": [ + 387, + 389 + ] + }, + { + "text": "[source,asm] ---- andi rd'/rs1', rd'/rs1', 0xff ----", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.zext.b", + "line_range": [ + 397, + 400 + ] + }, + { + "text": "[source,sail] ---- X(rsdc) = EXTZ(X(rsdc)[7..0]); ----", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.zext.b", + "line_range": [ + 404, + 407 + ] + }, + { + "text": "<<< [insns-csextb,reftext=\"Sign extend byte, 16-bit encoding\"]", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.zext.b", + "line_range": [ + 409, + 410 + ] + }, + { + "text": "Sign extend byte, 16-bit encoding", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.sext.b", + "line_range": [ + 415, + 415 + ] + }, + { + "text": "[wavedrom, , svg] .... {reg:[ { bits: 2, name: 0x1, attr: ['C1'] }, { bits: 3, name: 0x1, attr: ['C.SEXT.B'] }, { bits: 2, name: 0x3, attr: ['FUNCT2'] }, { bits: 3, name: 'rd\\'/rs1\\'', attr: ['SRCDST'] }, { bits: 3, name: 0x7 }, { bits: 3, name: 0x4, attr: ['FUNCT3'] }, ],config:{bits:16}} ....", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.sext.b", + "line_range": [ + 423, + 433 + ] + }, + { + "text": "This instruction takes a single source/destination operand.", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.sext.b", + "line_range": [ + 437, + 439 + ] + }, + { + "text": "It sign-extends the least-significant byte in the operand to XLEN bits by copying the most-significant bit in the byte (i.e., bit 7) to all of the more-significant bits.", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.sext.b", + "line_range": [ + 437, + 439 + ] + }, + { + "text": "Zbb is also required. // //32-bit equivalent: // // from Zbb", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.sext.b", + "line_range": [ + 443, + 447 + ] + }, + { + "text": "The SAIL module variable for rd'/rs1' is called rsdc.", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.sext.b", + "line_range": [ + 451, + 451 + ] + }, + { + "text": "[source,sail] ---- X(rsdc) = EXTS(X(rsdc)[7..0]); ----", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.sext.b", + "line_range": [ + 455, + 458 + ] + }, + { + "text": "<<< [insns-czexth,reftext=\"Zero extend halfword, 16-bit encoding\"]", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.sext.b", + "line_range": [ + 460, + 461 + ] + }, + { + "text": "Zero extend halfword, 16-bit encoding", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.zext.h", + "line_range": [ + 466, + 466 + ] + }, + { + "text": "[wavedrom, , svg] .... {reg:[ { bits: 2, name: 0x1, attr: ['C1'] }, { bits: 3, name: 0x2, attr: ['C.ZEXT.H'] }, { bits: 2, name: 0x3, attr: ['FUNCT2'] }, { bits: 3, name: 'rd\\'/rs1\\'', attr: ['SRCDST'] }, { bits: 3, name: 0x7 }, { bits: 3, name: 0x4, attr: ['FUNCT3'] }, ],config:{bits:16}} ....", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.zext.h", + "line_range": [ + 474, + 484 + ] + }, + { + "text": "This instruction takes a single source/destination operand.", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.zext.h", + "line_range": [ + 488, + 490 + ] + }, + { + "text": "It zero-extends the least-significant halfword of the operand to XLEN bits by inserting zeros into all of the bits more significant than 15.", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.zext.h", + "line_range": [ + 488, + 490 + ] + }, + { + "text": "Zbb is also required. // //32-bit equivalent: // // from Zbb", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.zext.h", + "line_range": [ + 494, + 498 + ] + }, + { + "text": "[source,sail] ---- X(rsdc) = EXTZ(X(rsdc)[15..0]); ----", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.zext.h", + "line_range": [ + 502, + 505 + ] + }, + { + "text": "<<< [insns-csexth,reftext=\"Sign extend halfword, 16-bit encoding\"]", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.zext.h", + "line_range": [ + 507, + 508 + ] + }, + { + "text": "Sign extend halfword, 16-bit encoding", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.sext.h", + "line_range": [ + 513, + 513 + ] + }, + { + "text": "[wavedrom, , svg] .... {reg:[ { bits: 2, name: 0x1, attr: ['C1'] }, { bits: 3, name: 0x3, attr: ['C.SEXT.H'] }, { bits: 2, name: 0x3, attr: ['FUNCT2'] }, { bits: 3, name: 'rd\\'/rs1\\'', attr: ['SRCDST'] }, { bits: 3, name: 0x7 }, { bits: 3, name: 0x4, attr: ['FUNCT3'] }, ],config:{bits:16}} ....", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.sext.h", + "line_range": [ + 521, + 531 + ] + }, + { + "text": "This instruction takes a single source/destination operand.", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.sext.h", + "line_range": [ + 535, + 537 + ] + }, + { + "text": "It sign-extends the least-significant halfword in the operand to XLEN bits by copying the most-significant bit in the halfword (i.e., bit 15) to all of the more-significant bits.", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.sext.h", + "line_range": [ + 535, + 537 + ] + }, + { + "text": "Zbb is also required. // //32-bit equivalent: // // from Zbb", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.sext.h", + "line_range": [ + 541, + 545 + ] + }, + { + "text": "[source,sail] ---- X(rsdc) = EXTS(X(rsdc)[15..0]); ----", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.sext.h", + "line_range": [ + 549, + 552 + ] + }, + { + "text": "<<< [insns-czextw,reftext=\"Zero extend word, 16-bit encoding\"]", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.sext.h", + "line_range": [ + 554, + 555 + ] + }, + { + "text": "Zero extend word, 16-bit encoding", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.zext.w", + "line_range": [ + 560, + 560 + ] + }, + { + "text": "[wavedrom, , svg] .... {reg:[ { bits: 2, name: 0x1, attr: ['C1'] }, { bits: 3, name: 0x4, attr: ['C.ZEXT.W'] }, { bits: 2, name: 0x3, attr: ['FUNCT2'] }, { bits: 3, name: 'rd\\'/rs1\\'', attr: ['SRCDST'] }, { bits: 3, name: 0x7 }, { bits: 3, name: 0x4, attr: ['FUNCT3'] }, ],config:{bits:16}} ....", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.zext.w", + "line_range": [ + 568, + 578 + ] + }, + { + "text": "This instruction takes a single source/destination operand.", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.zext.w", + "line_range": [ + 582, + 584 + ] + }, + { + "text": "It zero-extends the least-significant word of the operand to XLEN bits by inserting zeros into all of the bits more significant than 31.", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.zext.w", + "line_range": [ + 582, + 584 + ] + }, + { + "text": "[source,asm] ---- add.uw rd'/rs1', rd'/rs1', zero ----", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.zext.w", + "line_range": [ + 592, + 595 + ] + }, + { + "text": "[source,sail] ---- X(rsdc) = EXTZ(X(rsdc)[31..0]); ----", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.zext.w", + "line_range": [ + 599, + 602 + ] + }, + { + "text": "<<< [insns-cnot,reftext=\"Bitwise not, 16-bit encoding\"]", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.zext.w", + "line_range": [ + 604, + 605 + ] + }, + { + "text": "Bitwise not, 16-bit encoding", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.not", + "line_range": [ + 610, + 610 + ] + }, + { + "text": "[wavedrom, , svg] .... {reg:[ { bits: 2, name: 0x1, attr: ['C1'] }, { bits: 3, name: 0x5, attr: ['C.NOT'] }, { bits: 2, name: 0x3, attr: ['FUNCT2'] }, { bits: 3, name: 'rd\\'/rs1\\'', attr: ['SRCDST'] }, { bits: 3, name: 0x7 }, { bits: 3, name: 0x4, attr: ['FUNCT3'] }, ],config:{bits:16}} ....", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.not", + "line_range": [ + 618, + 628 + ] + }, + { + "text": "This instruction takes the one's complement of rd'/rs1' and writes the result to the same register.", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.not", + "line_range": [ + 632, + 632 + ] + }, + { + "text": "[source,asm] ---- xori rd'/rs1', rd'/rs1', -1 ----", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.not", + "line_range": [ + 640, + 643 + ] + }, + { + "text": "[source,sail] ---- X(rsdc) = X(rsdc) XOR -1; ----", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.not", + "line_range": [ + 647, + 650 + ] + }, + { + "text": "<<< [insns-cmul,reftext=\"Multiply, 16-bit encoding\"]", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.not", + "line_range": [ + 652, + 653 + ] + }, + { + "text": "[wavedrom, , svg] .... {reg:[ { bits: 2, name: 0x1, attr: ['C1'] }, { bits: 3, name: 'rs2\\'', attr: ['SRC2'] }, { bits: 2, name: 0x2, attr: ['FUNCT2'] }, { bits: 3, name: 'rd\\'/rs1\\'', attr: ['SRCDST'] }, { bits: 3, name: 0x7 }, { bits: 3, name: 0x4, attr: ['FUNCT3'] }, ],config:{bits:16}} ....", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.mul", + "line_range": [ + 666, + 676 + ] + }, + { + "text": "This instruction multiplies XLEN bits of the source operands from rsd' and rs2' and writes the lowest XLEN bits of the result to rsd'.", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.mul", + "line_range": [ + 680, + 680 + ] + }, + { + "text": "M or Zmmul must be configured. // //32-bit equivalent: // //", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.mul", + "line_range": [ + 684, + 688 + ] + }, + { + "text": "[source,sail] ---- let resultwide = tobits(2 * sizeof(xlen), signed(X(rsdc)) * signed(X(rs2c))); X(rsdc) = resultwide[(sizeof(xlen) - 1) .. 0]; ----", + "section": "Preamble > ext:zcb[] Extension for Additional Compressed Instructions > c.lbu > c.mul", + "line_range": [ + 692, + 696 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zcd.json b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zcd.json new file mode 100644 index 0000000000..2bc328bdbc --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zcd.json @@ -0,0 +1,118 @@ +{ + "source_file": "src/unpriv/zcd.adoc", + "total": 14, + "sentences": [ + { + "text": "The ext:zcd[] extension adds compressed double-precision floating-point load and store instructions.", + "section": "Preamble > ext:zcd[] Double-Precision Floating-Point Compressed Instructions Extension", + "line_range": [ + 3, + 4 + ] + }, + { + "text": "C.FLDSP is an RV32DC/RV64DC-only instruction that loads a double-precision floating-point value from memory into floating-point register rd.", + "section": "Preamble > ext:zcd[] Double-Precision Floating-Point Compressed Instructions Extension > Stack-Pointer-Based Loads and Stores", + "line_range": [ + 8, + 12 + ] + }, + { + "text": "It computes its effective address by adding the zero-extended offset, scaled by 8, to the stack pointer, `x2`.", + "section": "Preamble > ext:zcd[] Double-Precision Floating-Point Compressed Instructions Extension > Stack-Pointer-Based Loads and Stores", + "line_range": [ + 8, + 12 + ] + }, + { + "text": "It expands to `fld rd, offset(x2)`.", + "section": "Preamble > ext:zcd[] Double-Precision Floating-Point Compressed Instructions Extension > Stack-Pointer-Based Loads and Stores", + "line_range": [ + 8, + 12 + ] + }, + { + "text": "C.FSDSP is an RV32DC/RV64DC-only instruction that stores a double-precision floating-point value in floating-point register rs2 to memory.", + "section": "Preamble > ext:zcd[] Double-Precision Floating-Point Compressed Instructions Extension > Stack-Pointer-Based Loads and Stores", + "line_range": [ + 14, + 18 + ] + }, + { + "text": "It computes an effective address by adding the zero-extended offset, scaled by 8, to the stack pointer, `x2`.", + "section": "Preamble > ext:zcd[] Double-Precision Floating-Point Compressed Instructions Extension > Stack-Pointer-Based Loads and Stores", + "line_range": [ + 14, + 18 + ] + }, + { + "text": "It expands to `fsd rs2, offset(x2)`.", + "section": "Preamble > ext:zcd[] Double-Precision Floating-Point Compressed Instructions Extension > Stack-Pointer-Based Loads and Stores", + "line_range": [ + 14, + 18 + ] + }, + { + "text": "These instructions encode their data source or destination as described in .", + "section": "Preamble > ext:zcd[] Double-Precision Floating-Point Compressed Instructions Extension > Stack-Pointer-Based Loads and Stores > Register-Based Loads and Stores", + "line_range": [ + 22, + 23 + ] + }, + { + "text": "C.FLD is an RV32DC/RV64DC-only instruction that loads a double-precision floating-point value from memory into floating-point register `rd′`.", + "section": "Preamble > ext:zcd[] Double-Precision Floating-Point Compressed Instructions Extension > Stack-Pointer-Based Loads and Stores > Register-Based Loads and Stores", + "line_range": [ + 25, + 30 + ] + }, + { + "text": "It computes an effective address by adding the zero-extended offset, scaled by 8, to the base address in register `rs1′`.", + "section": "Preamble > ext:zcd[] Double-Precision Floating-Point Compressed Instructions Extension > Stack-Pointer-Based Loads and Stores > Register-Based Loads and Stores", + "line_range": [ + 25, + 30 + ] + }, + { + "text": "It expands to `fld rd′, offset(rs1′)`.", + "section": "Preamble > ext:zcd[] Double-Precision Floating-Point Compressed Instructions Extension > Stack-Pointer-Based Loads and Stores > Register-Based Loads and Stores", + "line_range": [ + 25, + 30 + ] + }, + { + "text": "C.FSD is an RV32DC/RV64DC-only instruction that stores a double-precision floating-point value in floating-point register `rs2′` to memory.", + "section": "Preamble > ext:zcd[] Double-Precision Floating-Point Compressed Instructions Extension > Stack-Pointer-Based Loads and Stores > Register-Based Loads and Stores", + "line_range": [ + 32, + 37 + ] + }, + { + "text": "It computes an effective address by adding the zero-extended offset, scaled by 8, to the base address in register `rs1′`.", + "section": "Preamble > ext:zcd[] Double-Precision Floating-Point Compressed Instructions Extension > Stack-Pointer-Based Loads and Stores > Register-Based Loads and Stores", + "line_range": [ + 32, + 37 + ] + }, + { + "text": "It expands to `fsd rs2′, offset(rs1′)`.", + "section": "Preamble > ext:zcd[] Double-Precision Floating-Point Compressed Instructions Extension > Stack-Pointer-Based Loads and Stores > Register-Based Loads and Stores", + "line_range": [ + 32, + 37 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zce.json b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zce.json new file mode 100644 index 0000000000..d9aa6775d9 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zce.json @@ -0,0 +1,38 @@ +{ + "source_file": "src/unpriv/zce.adoc", + "total": 4, + "sentences": [ + { + "text": "This section describes the ext:zce[] extension, which incorporates the compressed instruction-set extensions designed for microcontrollers.", + "section": "Preamble > ext:zce[] Extension for Enhanced Instruction Compression", + "line_range": [ + 3, + 6 + ] + }, + { + "text": "Unlike the ext:c[] extension, the ext:zce[] extension includes extensions that trade performance for code density.", + "section": "Preamble > ext:zce[] Extension for Enhanced Instruction Compression", + "line_range": [ + 3, + 6 + ] + }, + { + "text": "The ext:zce[] extension depends upon the extlink:zca[], extlink:zcb[], extlink:zcmp[], and extlink:zcmt[] extensions.", + "section": "Preamble > ext:zce[] Extension for Enhanced Instruction Compression", + "line_range": [ + 8, + 9 + ] + }, + { + "text": "If XLEN=32 and the F extension is present, the ext:zce[] extension additionally depends upon the extlink:zcf[] extension.", + "section": "Preamble > ext:zce[] Extension for Enhanced Instruction Compression", + "line_range": [ + 11, + 12 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zcf.json b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zcf.json new file mode 100644 index 0000000000..0c4fb26704 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zcf.json @@ -0,0 +1,142 @@ +{ + "source_file": "src/unpriv/zcf.adoc", + "total": 17, + "sentences": [ + { + "text": "The ext:zcf[] extension adds compressed single-precision floating-point load and store instructions.", + "section": "Preamble > ext:zcf[] Single-Precision Floating-Point Compressed Instructions Extension", + "line_range": [ + 3, + 5 + ] + }, + { + "text": "It is an XLEN=32-only extension.", + "section": "Preamble > ext:zcf[] Single-Precision Floating-Point Compressed Instructions Extension", + "line_range": [ + 3, + 5 + ] + }, + { + "text": "C.FLWSP is an RV32FC-only instruction that loads a single-precision floating-point value from memory into floating-point register rd.", + "section": "Preamble > ext:zcf[] Single-Precision Floating-Point Compressed Instructions Extension > Stack-Pointer-Based Loads and Stores", + "line_range": [ + 9, + 14 + ] + }, + { + "text": "It computes its effective address by adding the zero-extended offset, scaled by 4, to the stack pointer, `x2`.", + "section": "Preamble > ext:zcf[] Single-Precision Floating-Point Compressed Instructions Extension > Stack-Pointer-Based Loads and Stores", + "line_range": [ + 9, + 14 + ] + }, + { + "text": "It expands to `flw rd, offset(x2)`. C.FLWSP uses the .", + "section": "Preamble > ext:zcf[] Single-Precision Floating-Point Compressed Instructions Extension > Stack-Pointer-Based Loads and Stores", + "line_range": [ + 9, + 14 + ] + }, + { + "text": "C.FSWSP is an RV32FC-only instruction that stores a single-precision floating-point value in floating-point register rs2 to memory.", + "section": "Preamble > ext:zcf[] Single-Precision Floating-Point Compressed Instructions Extension > Stack-Pointer-Based Loads and Stores", + "line_range": [ + 16, + 20 + ] + }, + { + "text": "It computes an effective address by adding the zero-extended offset, scaled by 4, to the stack pointer, `x2`.", + "section": "Preamble > ext:zcf[] Single-Precision Floating-Point Compressed Instructions Extension > Stack-Pointer-Based Loads and Stores", + "line_range": [ + 16, + 20 + ] + }, + { + "text": "It expands to `fsw rs2, offset(x2)`.", + "section": "Preamble > ext:zcf[] Single-Precision Floating-Point Compressed Instructions Extension > Stack-Pointer-Based Loads and Stores", + "line_range": [ + 16, + 20 + ] + }, + { + "text": "These instructions encode their data source or destination as described in the following table.", + "section": "Preamble > ext:zcf[] Single-Precision Floating-Point Compressed Instructions Extension > Stack-Pointer-Based Loads and Stores > Register-Based Loads and Stores", + "line_range": [ + 24, + 25 + ] + }, + { + "text": ".Registers specified by the three-bit rs1{prime}, rs2{prime}, and rd{prime} fields of the CIW, CL, CS, CA, and CB formats. //[cols=\"20%,10%,10%,10%,10%,10%,10%,10%,10%\"] [float=\"center\",align=\"center\",cols=\"1a, 1a\",frame=\"none\",grid=\"none\"] | | ! !ext:zcf[] Register Number !Floating-Point Register Number !Floating-Point Register ABI Name ! |", + "section": "Preamble > ext:zcf[] Single-Precision Floating-Point Compressed Instructions Extension > Stack-Pointer-Based Loads and Stores > Register-Based Loads and Stores", + "line_range": [ + 27, + 39 + ] + }, + { + "text": "! !`000` !`001` !`010` !`011` !`100` !`101` !`110` !`111` !`f8` !`f9` !`f10` !`f11` !`f12` !`f13`!`f14` !`f15` !`fs0` !`fs1` !`fa0` !`fa1` !`fa2`!`fa3` !`fa4` !`fa5` ! |", + "section": "Preamble > ext:zcf[] Single-Precision Floating-Point Compressed Instructions Extension > Stack-Pointer-Based Loads and Stores > Register-Based Loads and Stores", + "line_range": [ + 41, + 47 + ] + }, + { + "text": "C.FLW is an RV32FC-only instruction that loads a single-precision floating-point value from memory into floating-point register `rd′`.", + "section": "Preamble > ext:zcf[] Single-Precision Floating-Point Compressed Instructions Extension > Stack-Pointer-Based Loads and Stores > Register-Based Loads and Stores", + "line_range": [ + 49, + 54 + ] + }, + { + "text": "It computes an effective address by adding the zero-extended offset, scaled by 4, to the base address in register `rs1′`.", + "section": "Preamble > ext:zcf[] Single-Precision Floating-Point Compressed Instructions Extension > Stack-Pointer-Based Loads and Stores > Register-Based Loads and Stores", + "line_range": [ + 49, + 54 + ] + }, + { + "text": "It expands to `flw rd′, offset(rs1′)`.", + "section": "Preamble > ext:zcf[] Single-Precision Floating-Point Compressed Instructions Extension > Stack-Pointer-Based Loads and Stores > Register-Based Loads and Stores", + "line_range": [ + 49, + 54 + ] + }, + { + "text": "C.FSW is an RV32FC-only instruction that stores a single-precision floating-point value in floating-point register `rs2′` to memory.", + "section": "Preamble > ext:zcf[] Single-Precision Floating-Point Compressed Instructions Extension > Stack-Pointer-Based Loads and Stores > Register-Based Loads and Stores", + "line_range": [ + 56, + 61 + ] + }, + { + "text": "It computes an effective address by adding the zero-extended offset, scaled by 4, to the base address in register `rs1′`.", + "section": "Preamble > ext:zcf[] Single-Precision Floating-Point Compressed Instructions Extension > Stack-Pointer-Based Loads and Stores > Register-Based Loads and Stores", + "line_range": [ + 56, + 61 + ] + }, + { + "text": "It expands to `fsw rs2′, offset(rs1′)`.", + "section": "Preamble > ext:zcf[] Single-Precision Floating-Point Compressed Instructions Extension > Stack-Pointer-Based Loads and Stores > Register-Based Loads and Stores", + "line_range": [ + 56, + 61 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zclsd.json b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zclsd.json new file mode 100644 index 0000000000..94f6ab12ab --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zclsd.json @@ -0,0 +1,358 @@ +{ + "source_file": "src/unpriv/zclsd.adoc", + "total": 44, + "sentences": [ + { + "text": "The ext:zclsd[] extension provides compressed load/store pair instructions for RV32, reusing the existing RV64 doubleword load/store instruction encodings.", + "section": "Preamble > ext:zclsd[] Extension for Compressed Load/Store Pair Instructions", + "line_range": [ + 3, + 4 + ] + }, + { + "text": "Zclsd depends on Zilsd and Zca.", + "section": "Preamble > ext:zclsd[] Extension for Compressed Load/Store Pair Instructions", + "line_range": [ + 6, + 6 + ] + }, + { + "text": "It has overlapping encodings with Zcf and is thus incompatible with Zcf.", + "section": "Preamble > ext:zclsd[] Extension for Compressed Load/Store Pair Instructions", + "line_range": [ + 6, + 6 + ] + }, + { + "text": "For C.LDSP, usage of `x0` as the destination is reserved.", + "section": "Preamble > ext:zclsd[] Extension for Compressed Load/Store Pair Instructions > Use of `x0` as operand", + "line_range": [ + 10, + 10 + ] + }, + { + "text": "If using `x0` as `src` of C.SDSP, the entire 64-bit operand is zero — i.e., register `x1` is not accessed.", + "section": "Preamble > ext:zclsd[] Extension for Compressed Load/Store Pair Instructions > Use of `x0` as operand", + "line_range": [ + 12, + 12 + ] + }, + { + "text": "C.LD and C.SD instructions can only use `x8-15`.", + "section": "Preamble > ext:zclsd[] Extension for Compressed Load/Store Pair Instructions > Use of `x0` as operand", + "line_range": [ + 14, + 14 + ] + }, + { + "text": "For the purposes of RVWMO and exception handling, C.LD[SP] and C.SD[SP] instructions are considered to be misaligned loads and stores, with one additional constraint: a C.LD[SP] or C.SD[SP] instruction whose effective address is a multiple of 4 gives rise to two 4-byte memory operations.", + "section": "Preamble > ext:zclsd[] Extension for Compressed Load/Store Pair Instructions > Use of `x0` as operand > Exception Handling", + "line_range": [ + 18, + 21 + ] + }, + { + "text": "Zclsd adds the following RV32-only instructions:", + "section": "Preamble > ext:zclsd[] Extension for Compressed Load/Store Pair Instructions > Use of `x0` as operand > Exception Handling", + "line_range": [ + 23, + 23 + ] + }, + { + "text": "| |RV32 |RV64 |Mnemonic |Instruction", + "section": "Preamble > ext:zclsd[] Extension for Compressed Load/Store Pair Instructions > Use of `x0` as operand > Exception Handling", + "line_range": [ + 25, + 30 + ] + }, + { + "text": "|yes |no |c.ldsp rd, offset(sp) |", + "section": "Preamble > ext:zclsd[] Extension for Compressed Load/Store Pair Instructions > Use of `x0` as operand > Exception Handling", + "line_range": [ + 32, + 35 + ] + }, + { + "text": "|yes |no |c.sdsp rs2, offset(sp) |", + "section": "Preamble > ext:zclsd[] Extension for Compressed Load/Store Pair Instructions > Use of `x0` as operand > Exception Handling", + "line_range": [ + 37, + 40 + ] + }, + { + "text": "|yes |no |c.ld rd', offset(rs1') |", + "section": "Preamble > ext:zclsd[] Extension for Compressed Load/Store Pair Instructions > Use of `x0` as operand > Exception Handling", + "line_range": [ + 42, + 45 + ] + }, + { + "text": "|yes |no |c.sd rs2', offset(rs1') |", + "section": "Preamble > ext:zclsd[] Extension for Compressed Load/Store Pair Instructions > Use of `x0` as operand > Exception Handling", + "line_range": [ + 47, + 50 + ] + }, + { + "text": "[insns-cldsp,reftext=\"Stack-pointer based load doubleword to register pair, 16-bit encoding\"]", + "section": "Preamble > ext:zclsd[] Extension for Compressed Load/Store Pair Instructions > Use of `x0` as operand > Exception Handling", + "line_range": [ + 56, + 56 + ] + }, + { + "text": "Synopsis:: Stack-pointer based load doubleword to even/odd register pair, 16-bit encoding", + "section": "Preamble > ext:zclsd[] Extension for Compressed Load/Store Pair Instructions > Use of `x0` as operand > Exception Handling > c.ldsp", + "line_range": [ + 59, + 60 + ] + }, + { + "text": "Mnemonic:: c.ldsp rd, offset(sp)", + "section": "Preamble > ext:zclsd[] Extension for Compressed Load/Store Pair Instructions > Use of `x0` as operand > Exception Handling > c.ldsp", + "line_range": [ + 62, + 63 + ] + }, + { + "text": "Encoding (RV32):: [wavedrom, ,svg] .... {reg: [ {bits: 2, name: 0x2, type: 8, attr: ['C2']}, {bits: 5, name: 'imm', type: 3, attr: ['offset[4:3|8:6]']}, {bits: 5, name: 'rd', type: 2, attr: ['dest!=0, dest[0]=0']}, {bits: 1, name: 'imm', type: 3, attr: ['offset[5]']}, {bits: 3, name: 0x3, type: 8, attr: ['C.LDSP']}, ], config: {bits: 16}} ....", + "section": "Preamble > ext:zclsd[] Extension for Compressed Load/Store Pair Instructions > Use of `x0` as operand > Exception Handling > c.ldsp", + "line_range": [ + 65, + 75 + ] + }, + { + "text": "Description:: Loads stack-pointer relative 64-bit value into registers `rd'` and `rd'+1`.", + "section": "Preamble > ext:zclsd[] Extension for Compressed Load/Store Pair Instructions > Use of `x0` as operand > Exception Handling > c.ldsp", + "line_range": [ + 77, + 79 + ] + }, + { + "text": "It computes its effective address by adding the zero-extended offset, scaled by 8, to the stack pointer, `x2`.", + "section": "Preamble > ext:zclsd[] Extension for Compressed Load/Store Pair Instructions > Use of `x0` as operand > Exception Handling > c.ldsp", + "line_range": [ + 77, + 79 + ] + }, + { + "text": "It expands to `ld rd, offset(x2)`. C.LDSP is only valid when rd{ne}x0; the code points with rd=x0 are reserved.", + "section": "Preamble > ext:zclsd[] Extension for Compressed Load/Store Pair Instructions > Use of `x0` as operand > Exception Handling > c.ldsp", + "line_range": [ + 77, + 79 + ] + }, + { + "text": "Included in: extlink:zclsd[]", + "section": "Preamble > ext:zclsd[] Extension for Compressed Load/Store Pair Instructions > Use of `x0` as operand > Exception Handling > c.ldsp", + "line_range": [ + 81, + 81 + ] + }, + { + "text": "[insns-csdsp,reftext=\"Stack-pointer based store doubleword from register pair, 16-bit encoding\"]", + "section": "Preamble > ext:zclsd[] Extension for Compressed Load/Store Pair Instructions > Use of `x0` as operand > Exception Handling > c.ldsp", + "line_range": [ + 85, + 85 + ] + }, + { + "text": "Synopsis:: Stack-pointer based store doubleword from even/odd register pair, 16-bit encoding", + "section": "Preamble > ext:zclsd[] Extension for Compressed Load/Store Pair Instructions > Use of `x0` as operand > Exception Handling > c.sdsp", + "line_range": [ + 88, + 89 + ] + }, + { + "text": "Mnemonic:: c.sdsp rs2, offset(sp)", + "section": "Preamble > ext:zclsd[] Extension for Compressed Load/Store Pair Instructions > Use of `x0` as operand > Exception Handling > c.sdsp", + "line_range": [ + 91, + 92 + ] + }, + { + "text": "Encoding (RV32):: [wavedrom, ,svg] .... {reg: [ {bits: 2, name: 0x2, type: 8, attr: ['C2']}, {bits: 5, name: 'rs2', type: 4, attr: ['src, src[0]=0']}, {bits: 6, name: 'imm', type: 3, attr: ['offset[5:3|8:6]']}, {bits: 3, name: 0x7, type: 8, attr: ['C.SDSP']}, ], config: {bits: 16}} ....", + "section": "Preamble > ext:zclsd[] Extension for Compressed Load/Store Pair Instructions > Use of `x0` as operand > Exception Handling > c.sdsp", + "line_range": [ + 94, + 103 + ] + }, + { + "text": "Description:: Stores a stack-pointer relative 64-bit value from registers `rs2'` and `rs2'+1`.", + "section": "Preamble > ext:zclsd[] Extension for Compressed Load/Store Pair Instructions > Use of `x0` as operand > Exception Handling > c.sdsp", + "line_range": [ + 105, + 107 + ] + }, + { + "text": "It computes an effective address by adding the zero-extended offset, scaled by 8, to the stack pointer, `x2`.", + "section": "Preamble > ext:zclsd[] Extension for Compressed Load/Store Pair Instructions > Use of `x0` as operand > Exception Handling > c.sdsp", + "line_range": [ + 105, + 107 + ] + }, + { + "text": "It expands to `sd rs2, offset(x2)`.", + "section": "Preamble > ext:zclsd[] Extension for Compressed Load/Store Pair Instructions > Use of `x0` as operand > Exception Handling > c.sdsp", + "line_range": [ + 105, + 107 + ] + }, + { + "text": "Included in: extlink:zclsd[]", + "section": "Preamble > ext:zclsd[] Extension for Compressed Load/Store Pair Instructions > Use of `x0` as operand > Exception Handling > c.sdsp", + "line_range": [ + 109, + 109 + ] + }, + { + "text": "[insns-cld,reftext=\"Load doubleword to register pair, 16-bit encoding\"]", + "section": "Preamble > ext:zclsd[] Extension for Compressed Load/Store Pair Instructions > Use of `x0` as operand > Exception Handling > c.sdsp", + "line_range": [ + 113, + 113 + ] + }, + { + "text": "Synopsis:: Load doubleword to even/odd register pair, 16-bit encoding", + "section": "Preamble > ext:zclsd[] Extension for Compressed Load/Store Pair Instructions > Use of `x0` as operand > Exception Handling > c.ld", + "line_range": [ + 116, + 117 + ] + }, + { + "text": "Mnemonic:: c.ld rd', offset(rs1')", + "section": "Preamble > ext:zclsd[] Extension for Compressed Load/Store Pair Instructions > Use of `x0` as operand > Exception Handling > c.ld", + "line_range": [ + 119, + 120 + ] + }, + { + "text": "Encoding (RV32):: [wavedrom, ,svg] .... {reg: [ {bits: 2, name: 0x0, type: 8, attr: ['C0']}, {bits: 3, name: 'rd`', type: 2, attr: ['dest, dest[0]=0']}, {bits: 2, name: 'imm', type: 3, attr: ['offset[7:6]']}, {bits: 3, name: 'rs1`', type: 4, attr: ['base']}, {bits: 3, name: 'imm', type: 3, attr: ['offset[5:3]']}, {bits: 3, name: 0x3, type: 8, attr: ['C.LD']}, ], config: {bits: 16}} ....", + "section": "Preamble > ext:zclsd[] Extension for Compressed Load/Store Pair Instructions > Use of `x0` as operand > Exception Handling > c.ld", + "line_range": [ + 122, + 133 + ] + }, + { + "text": "Description:: Loads a 64-bit value into registers `rd'` and `rd'+1`.", + "section": "Preamble > ext:zclsd[] Extension for Compressed Load/Store Pair Instructions > Use of `x0` as operand > Exception Handling > c.ld", + "line_range": [ + 135, + 138 + ] + }, + { + "text": "It computes an effective address by adding the zero-extended offset, scaled by 8, to the base address in register rs1'.", + "section": "Preamble > ext:zclsd[] Extension for Compressed Load/Store Pair Instructions > Use of `x0` as operand > Exception Handling > c.ld", + "line_range": [ + 135, + 138 + ] + }, + { + "text": "Included in: extlink:zclsd[]", + "section": "Preamble > ext:zclsd[] Extension for Compressed Load/Store Pair Instructions > Use of `x0` as operand > Exception Handling > c.ld", + "line_range": [ + 140, + 140 + ] + }, + { + "text": "[insns-csd,reftext=\"Store doubleword from register pair, 16-bit encoding\"]", + "section": "Preamble > ext:zclsd[] Extension for Compressed Load/Store Pair Instructions > Use of `x0` as operand > Exception Handling > c.ld", + "line_range": [ + 144, + 144 + ] + }, + { + "text": "Synopsis:: Store doubleword from even/odd register pair, 16-bit encoding", + "section": "Preamble > ext:zclsd[] Extension for Compressed Load/Store Pair Instructions > Use of `x0` as operand > Exception Handling > c.sd", + "line_range": [ + 147, + 148 + ] + }, + { + "text": "Mnemonic:: c.sd rs2', offset(rs1')", + "section": "Preamble > ext:zclsd[] Extension for Compressed Load/Store Pair Instructions > Use of `x0` as operand > Exception Handling > c.sd", + "line_range": [ + 150, + 151 + ] + }, + { + "text": "Encoding (RV32):: [wavedrom, ,svg] .... {reg: [ {bits: 2, name: 0x0, type: 8, attr: ['C0']}, {bits: 3, name: 'rs2`', type: 4, attr: ['src, src[0]=0']}, {bits: 2, name: 'imm', type: 3, attr: ['offset[7:6]']}, {bits: 3, name: 'rs1`', type: 4, attr: ['base']}, {bits: 3, name: 'imm', type: 3, attr: ['offset[5:3]']}, {bits: 3, name: 0x7, type: 8, attr: ['C.SD']}, ], config: {bits: 16}} ....", + "section": "Preamble > ext:zclsd[] Extension for Compressed Load/Store Pair Instructions > Use of `x0` as operand > Exception Handling > c.sd", + "line_range": [ + 153, + 164 + ] + }, + { + "text": "Description:: Stores a 64-bit value from registers `rs2'` and `rs2'+1`.", + "section": "Preamble > ext:zclsd[] Extension for Compressed Load/Store Pair Instructions > Use of `x0` as operand > Exception Handling > c.sd", + "line_range": [ + 166, + 170 + ] + }, + { + "text": "It computes an effective address by adding the zero-extended offset, scaled by 8, to the base address in register rs1'.", + "section": "Preamble > ext:zclsd[] Extension for Compressed Load/Store Pair Instructions > Use of `x0` as operand > Exception Handling > c.sd", + "line_range": [ + 166, + 170 + ] + }, + { + "text": "It expands to `sd rs2', offset(rs1')`.", + "section": "Preamble > ext:zclsd[] Extension for Compressed Load/Store Pair Instructions > Use of `x0` as operand > Exception Handling > c.sd", + "line_range": [ + 166, + 170 + ] + }, + { + "text": "Included in: extlink:zclsd[]", + "section": "Preamble > ext:zclsd[] Extension for Compressed Load/Store Pair Instructions > Use of `x0` as operand > Exception Handling > c.sd", + "line_range": [ + 172, + 172 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zcmop.json b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zcmop.json new file mode 100644 index 0000000000..a9aad9d016 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zcmop.json @@ -0,0 +1,110 @@ +{ + "source_file": "src/unpriv/zcmop.adoc", + "total": 13, + "sentences": [ + { + "text": "This section defines the ext:zcmop[] extension, which defines eight 16-bit MOP instructions named C.MOP.n, where n is an odd integer between 1 and 15, inclusive. C.MOP.n is encoded in the reserved encoding space corresponding to C.LUI xn, 0, as shown in .", + "section": "Preamble > ext:zcmop[] Compressed May-Be-Operations Extension", + "line_range": [ + 3, + 10 + ] + }, + { + "text": "Unlike the MOPs defined in the extlink:zimop[] extension, the C.MOP.n instructions are defined to not write any register.", + "section": "Preamble > ext:zcmop[] Compressed May-Be-Operations Extension", + "line_range": [ + 3, + 10 + ] + }, + { + "text": "Their encoding allows future extensions to define them to read register `x[n]`.", + "section": "Preamble > ext:zcmop[] Compressed May-Be-Operations Extension", + "line_range": [ + 3, + 10 + ] + }, + { + "text": "The ext:zcmop[] extension depends upon the Zca extension.", + "section": "Preamble > ext:zcmop[] Compressed May-Be-Operations Extension", + "line_range": [ + 12, + 12 + ] + }, + { + "text": "NOTE: Very few suitable 16-bit encoding spaces exist.", + "section": "Preamble > ext:zcmop[] Compressed May-Be-Operations Extension", + "line_range": [ + 17, + 20 + ] + }, + { + "text": "This space was chosen because it already has unusual behavior with respect to the `rd`/`rs1` field--it encodes `c.addi16sp` when the field contains `x2`--and is therefore of lower value for most purposes.", + "section": "Preamble > ext:zcmop[] Compressed May-Be-Operations Extension", + "line_range": [ + 17, + 20 + ] + }, + { + "text": ".C.MOP.n instruction encoding.", + "section": "Preamble > ext:zcmop[] Compressed May-Be-Operations Extension", + "line_range": [ + 22, + 23 + ] + }, + { + "text": "| |Mnemonic | Encoding | Redefinable to read register", + "section": "Preamble > ext:zcmop[] Compressed May-Be-Operations Extension", + "line_range": [ + 25, + 26 + ] + }, + { + "text": "|C.MOP.1 | `0110000010000001` | `x1` |C.MOP.3 | `0110000110000001` | `x3` |C.MOP.5 | `0110001010000001` | `x5` |C.MOP.7 | `0110001110000001` | `x7` |C.MOP.9 | `0110010010000001` | `x9` |C.MOP.11 | `0110010110000001` | `x11` |C.MOP.13 | `0110011010000001` | `x13` |C.MOP.15 | `0110011110000001` | `x15` |", + "section": "Preamble > ext:zcmop[] Compressed May-Be-Operations Extension", + "line_range": [ + 28, + 36 + ] + }, + { + "text": "NOTE: The recommended assembly syntax for C.MOP.n is simply the nullary C.MOP.n.", + "section": "Preamble > ext:zcmop[] Compressed May-Be-Operations Extension", + "line_range": [ + 38, + 39 + ] + }, + { + "text": "The possibly accessed register is implicitly `xn`.", + "section": "Preamble > ext:zcmop[] Compressed May-Be-Operations Extension", + "line_range": [ + 38, + 39 + ] + }, + { + "text": "NOTE: The expectation is that each ext:zcmop[] instruction is equivalent to some ext:zimop[] instruction, but the choice of expansion (if any) is left to the extension that redefines the MOP.", + "section": "Preamble > ext:zcmop[] Compressed May-Be-Operations Extension", + "line_range": [ + 41, + 45 + ] + }, + { + "text": "Note, a ext:zcmop[] instruction that does not write a value can expand into a write to `x0`.", + "section": "Preamble > ext:zcmop[] Compressed May-Be-Operations Extension", + "line_range": [ + 41, + 45 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zcmp.json b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zcmp.json new file mode 100644 index 0000000000..02e320636f --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zcmp.json @@ -0,0 +1,1606 @@ +{ + "source_file": "src/unpriv/zcmp.adoc", + "total": 200, + "sentences": [ + { + "text": "The ext:zcmp[] extension adds instructions that substantially reduce the static code size of procedure prologues and epilogues.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues", + "line_range": [ + 3, + 5 + ] + }, + { + "text": "The instructions it adds are collectively referred to as PUSH/POP:", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues", + "line_range": [ + 3, + 5 + ] + }, + { + "text": "The term PUSH refers to cm.push.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues", + "line_range": [ + 12, + 12 + ] + }, + { + "text": "The term POP refers to cm.pop.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues", + "line_range": [ + 14, + 14 + ] + }, + { + "text": "The term POPRET refers to cm.popret and cm.popretz.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues", + "line_range": [ + 16, + 16 + ] + }, + { + "text": "Common details for these instructions are in this section.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues", + "line_range": [ + 18, + 18 + ] + }, + { + "text": "PUSH, POP, POPRET are used to reduce the size of function prologues and epilogues.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview", + "line_range": [ + 22, + 22 + ] + }, + { + "text": "The PUSH instruction ** adjusts the stack pointer to create the stack frame ** pushes (stores) the registers specified in the register list to the stack frame", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview", + "line_range": [ + 24, + 26 + ] + }, + { + "text": "The POP instruction ** pops (loads) the registers in the register list from the stack frame ** adjusts the stack pointer to destroy the stack frame", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview", + "line_range": [ + 28, + 30 + ] + }, + { + "text": "The POPRET instructions ** pop (load) the registers in the register list from the stack frame ** cm.popretz also moves zero into a0 as the return value ** adjust the stack pointer to destroy the stack frame ** execute a ret instruction to return from the function", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview", + "line_range": [ + 32, + 36 + ] + }, + { + "text": "This example gives an illustration of the use of PUSH and POPRET.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Example usage", + "line_range": [ + 41, + 41 + ] + }, + { + "text": "The function processMarkers in the EMBench benchmark picojpeg in the following file on github: https://github.com/embench/embench-iot/blob/master/src/picojpeg/libpicojpeg.c[libpicojpeg.c]", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Example usage", + "line_range": [ + 43, + 43 + ] + }, + { + "text": "The prologue and epilogue compile with GCC10 to:", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Example usage", + "line_range": [ + 45, + 45 + ] + }, + { + "text": "0001098a : 1098a: 711d addi sp,sp,-96 ;cm.push(1) 1098c: c8ca sw s2,80(sp) ;cm.push(2) 1098e: c6ce sw s3,76(sp) ;cm.push(3) 10990: c4d2 sw s4,72(sp) ;cm.push(4) 10992: ce86 sw ra,92(sp) ;cm.push(5) 10994: cca2 sw s0,88(sp) ;cm.push(6) 10996: caa6 sw s1,84(sp) ;cm.push(7) 10998: c2d6 sw s5,68(sp) ;cm.push(8) 1099a: c0da sw s6,64(sp) ;cm.push(9) 1099c: de5e sw s7,60(sp) ;cm.push(10) 1099e: dc62 sw s8,56(sp) ;cm.push(11) 109a0: da66 sw s9,52(sp) ;cm.push(12) 109a2: d86a sw s10,48(sp);cm.push(13) 109a4: d66e sw s11,44(sp);cm.push(14) ... 109f4: 4501 li a0,0 ;cm.popretz(1) 109f6: 40f6 lw ra,92(sp) ;cm.popretz(2) 109f8: 4466 lw s0,88(sp) ;cm.popretz(3) 109fa: 44d6 lw s1,84(sp) ;cm.popretz(4) 109fc: 4946 lw s2,80(sp) ;cm.popretz(5) 109fe: 49b6 lw s3,76(sp) ;cm.popretz(6) 10a00: 4a26 lw s4,72(sp) ;cm.popretz(7) 10a02: 4a96 lw s5,68(sp) ;cm.popretz(8) 10a04: 4b06 lw s6,64(sp) ;cm.popretz(9) 10a06: 5bf2 lw s7,60(sp) ;cm.popretz(10) 10a08: 5c62 lw s8,56(sp) ;cm.popretz(11) 10a0a: 5cd2 lw s9,52(sp) ;cm.popretz(12) 10a0c: 5d42 lw s10,48(sp);cm.popretz(13) 10a0e: 5db2 lw s11,44(sp);cm.popretz(14) 10a10: 6125 addi sp,sp,96 ;cm.popretz(15) 10a12: 8082 ret ;cm.popretz(16) ----", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Example usage", + "line_range": [ + 50, + 82 + ] + }, + { + "text": "with the GCC option -msave-restore the output is the following:", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Example usage", + "line_range": [ + 86, + 86 + ] + }, + { + "text": "[source,asm] ---- 0001080e : 1080e: 73a012ef jal t0,11f48 10812: 1101 addi sp,sp,-32 ... 10862: 4501 li a0,0 10864: 6105 addi sp,sp,32 10866: 71e0106f j 11f84 ----", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Example usage", + "line_range": [ + 88, + 97 + ] + }, + { + "text": "with PUSH/POPRET this reduces to", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Example usage", + "line_range": [ + 99, + 99 + ] + }, + { + "text": "[source,asm] ---- 0001080e : 1080e: b8fa cm.push \\{ra,s0-s11},-96 ... 10866: bcfa cm.popretz \\{ra,s0-s11}, 96 ----", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Example usage", + "line_range": [ + 101, + 107 + ] + }, + { + "text": "The prologue / epilogue reduce from 60-bytes in the original code, to 14-bytes with -msave-restore, and to 4-bytes with PUSH and POPRET.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Example usage", + "line_range": [ + 109, + 112 + ] + }, + { + "text": "As well as reducing the code-size PUSH and POPRET eliminate the branches from calling the millicode save/restore routines and so may also perform better.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Example usage", + "line_range": [ + 109, + 112 + ] + }, + { + "text": "The instructions all automatically adjust the stack pointer by enough to cover the memory required for the registers being saved or restored.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Example usage > Stack pointer adjustment handling", + "line_range": [ + 118, + 120 + ] + }, + { + "text": "Additionally the spimm field in the encoding allows the stack pointer to be adjusted in additional increments of 16-bytes.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Example usage > Stack pointer adjustment handling", + "line_range": [ + 118, + 120 + ] + }, + { + "text": "There is only a small restricted range available in the encoding; if the range is insufficient then a separate c.addi16sp can be used to increase the range.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Example usage > Stack pointer adjustment handling", + "line_range": [ + 118, + 120 + ] + }, + { + "text": "There is no support for the \\{ra, s0-s10} register list without also adding s11.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Example usage > Register list handling", + "line_range": [ + 124, + 124 + ] + }, + { + "text": "Therefore the \\{ra, s0-s11} register list must be used in this case.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Example usage > Register list handling", + "line_range": [ + 124, + 124 + ] + }, + { + "text": "[pushpop-idempotent-memory]", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Example usage > Register list handling", + "line_range": [ + 126, + 126 + ] + }, + { + "text": "Correct execution requires that sp refers to idempotent memory (also see ), because the core must be able to handle traps detected during the sequence.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > PUSH/POP Fault handling", + "line_range": [ + 129, + 132 + ] + }, + { + "text": "The entire PUSH/POP sequence is re-executed after returning from the trap handler, and multiple traps are possible during the sequence.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > PUSH/POP Fault handling", + "line_range": [ + 129, + 132 + ] + }, + { + "text": "If a trap occurs during the sequence then xEPC is updated with the PC of the instruction, xTVAL (if not read-only-zero) updated with the bad address if it was an access fault and xCAUSE updated with the type of trap.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > PUSH/POP Fault handling", + "line_range": [ + 134, + 134 + ] + }, + { + "text": "NOTE: It is implementation defined whether interrupts can also be taken during the sequence execution.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > PUSH/POP Fault handling", + "line_range": [ + 136, + 137 + ] + }, + { + "text": "From a software perspective the PUSH sequence appears as:", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Software view of execution > Software view of the PUSH sequence", + "line_range": [ + 144, + 144 + ] + }, + { + "text": "A sequence of stores writing the bytes required by the pseudocode ** The bytes may be written in any order. ** The bytes may be grouped into larger accesses. ** Any of the bytes may be written multiple times. * A stack pointer adjustment", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Software view of execution > Software view of the PUSH sequence", + "line_range": [ + 146, + 150 + ] + }, + { + "text": "The stack pointer adjustment must only be committed only when it is certain that the entire PUSH instruction will commit.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Software view of execution > Software view of the PUSH sequence", + "line_range": [ + 152, + 152 + ] + }, + { + "text": "Stores may also return imprecise faults from the bus.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Software view of execution > Software view of the PUSH sequence", + "line_range": [ + 154, + 157 + ] + }, + { + "text": "It is platform defined whether the core implementation waits for the bus responses before continuing to the final stage of the sequence, or handles errors responses after completing the PUSH instruction.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Software view of execution > Software view of the PUSH sequence", + "line_range": [ + 154, + 157 + ] + }, + { + "text": "[source,asm] ---- cm.push \\{ra, s0-s5}, -64 ----", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Software view of execution > Software view of the PUSH sequence", + "line_range": [ + 163, + 166 + ] + }, + { + "text": "[source,asm] ---- any bytes from sp-1 to sp-28 may be written multiple times before the instruction completes therefore these updates may be visible in the interrupt/exception handler below the stack pointer sw s5, -4(sp) sw s4, -8(sp) sw s3,-12(sp) sw s2,-16(sp) sw s1,-20(sp) sw s0,-24(sp) sw ra,-28(sp)", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Software view of execution > Software view of the PUSH sequence", + "line_range": [ + 170, + 181 + ] + }, + { + "text": "this must only execute once, and will only execute after all stores completed without any precise faults, therefore this update is only visible in the interrupt/exception handler if cm.push has completed addi sp, sp, -64 ----", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Software view of execution > Software view of the PUSH sequence", + "line_range": [ + 183, + 187 + ] + }, + { + "text": "From a software perspective the POP/POPRET sequence appears as:", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Software view of execution > Software view of the POP/POPRET sequence", + "line_range": [ + 191, + 191 + ] + }, + { + "text": "A sequence of loads reading the bytes required by the pseudocode. ** The bytes may be loaded in any order. ** The bytes may be grouped into larger accesses. ** Any of the bytes may be loaded multiple times. * A stack pointer adjustment * An optional `li a0, 0` * An optional `ret`", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Software view of execution > Software view of the POP/POPRET sequence", + "line_range": [ + 193, + 199 + ] + }, + { + "text": "If a trap occurs during the sequence, then any loads which were executed before the trap may update architectural state.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Software view of execution > Software view of the POP/POPRET sequence", + "line_range": [ + 201, + 203 + ] + }, + { + "text": "The loads will be re-executed once the trap handler completes, so the values will be overwritten.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Software view of execution > Software view of the POP/POPRET sequence", + "line_range": [ + 201, + 203 + ] + }, + { + "text": "Therefore it is permitted for an implementation to update some of the destination registers before taking a fault.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Software view of execution > Software view of the POP/POPRET sequence", + "line_range": [ + 201, + 203 + ] + }, + { + "text": "The optional `li a0, 0`, stack pointer adjustment and optional `ret` must only be committed only when it is certain that the entire POP/POPRET instruction will commit.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Software view of execution > Software view of the POP/POPRET sequence", + "line_range": [ + 205, + 205 + ] + }, + { + "text": "For POPRET once the stack pointer adjustment has been committed the `ret` must execute.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Software view of execution > Software view of the POP/POPRET sequence", + "line_range": [ + 207, + 207 + ] + }, + { + "text": "[source,asm] ---- cm.popretz \\{ra, s0-s3}, 32; ----", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Software view of execution > Software view of the POP/POPRET sequence", + "line_range": [ + 212, + 215 + ] + }, + { + "text": "[source,asm] ---- any or all of these load instructions may execute multiple times therefore these updates may be visible in the interrupt/exception handler lw s3, 28(sp) lw s2, 24(sp) lw s1, 20(sp) lw s0, 16(sp) lw ra, 12(sp)", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Software view of execution > Software view of the POP/POPRET sequence", + "line_range": [ + 219, + 227 + ] + }, + { + "text": "these must only execute once, will only execute after all loads complete successfully all instructions must execute atomically therefore these updates are not visible in the interrupt/exception handler li a0, 0 addi sp, sp, 32 ret ----", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Software view of execution > Software view of the POP/POPRET sequence", + "line_range": [ + 229, + 235 + ] + }, + { + "text": "An implementation may have a requirement to issue a PUSH/POP instruction to non-idempotent memory.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Non-idempotent memory handling", + "line_range": [ + 240, + 240 + ] + }, + { + "text": "If the core implementation does not support PUSH/POP to non-idempotent memories, the core may use an idempotency PMA to detect it and take a load (POP/POPRET) or store (PUSH) access-fault exception in order to avoid unpredictable results.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Non-idempotent memory handling", + "line_range": [ + 242, + 243 + ] + }, + { + "text": "Software should only use these instructions on non-idempotent memory regions when software can tolerate the required memory accesses being issued repeatedly in the case that they cause exceptions.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Non-idempotent memory handling", + "line_range": [ + 245, + 246 + ] + }, + { + "text": "The examples are included show the load/store series expansion and the stack adjustment.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Example RV32I PUSH/POP sequences", + "line_range": [ + 252, + 253 + ] + }, + { + "text": "Examples of cm.popret and cm.popretz are not included, as the difference in the expanded sequence from cm.pop is trivial in all cases.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Example RV32I PUSH/POP sequences", + "line_range": [ + 252, + 253 + ] + }, + { + "text": "Encoding: rlist=7, spimm=3", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Example RV32I PUSH/POP sequences > cm.push \\{ra, s0-s2}, -64", + "line_range": [ + 257, + 257 + ] + }, + { + "text": "[source,asm] ---- sw s2, -4(sp); sw s1, -8(sp); sw s0, -12(sp); sw ra, -16(sp); addi sp, sp, -64; ----", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Example RV32I PUSH/POP sequences > cm.push \\{ra, s0-s2}, -64", + "line_range": [ + 261, + 268 + ] + }, + { + "text": "Encoding: rlist=15, spimm=3", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Example RV32I PUSH/POP sequences > cm.push \\{ra, s0-s11}, -112", + "line_range": [ + 272, + 272 + ] + }, + { + "text": "[source,asm] ---- sw s11, -4(sp); sw s10, -8(sp); sw s9, -12(sp); sw s8, -16(sp); sw s7, -20(sp); sw s6, -24(sp); sw s5, -28(sp); sw s4, -32(sp); sw s3, -36(sp); sw s2, -40(sp); sw s1, -44(sp); sw s0, -48(sp); sw ra, -52(sp); addi sp, sp, -112; ----", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Example RV32I PUSH/POP sequences > cm.push \\{ra, s0-s11}, -112", + "line_range": [ + 276, + 292 + ] + }, + { + "text": "Encoding: rlist=4, spimm=0", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Example RV32I PUSH/POP sequences > cm.pop \\{ra}, 16", + "line_range": [ + 298, + 298 + ] + }, + { + "text": "[source,asm] ---- lw ra, 12(sp); addi sp, sp, 16; ----", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Example RV32I PUSH/POP sequences > cm.pop \\{ra}, 16", + "line_range": [ + 302, + 306 + ] + }, + { + "text": "Encoding: rlist=8, spimm=1", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Example RV32I PUSH/POP sequences > cm.pop \\{ra, s0-s3}, 48", + "line_range": [ + 310, + 310 + ] + }, + { + "text": "[source,asm] ---- lw s3, 44(sp); lw s2, 40(sp); lw s1, 36(sp); lw s0, 32(sp); lw ra, 28(sp); addi sp, sp, 48; ----", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Example RV32I PUSH/POP sequences > cm.pop \\{ra, s0-s3}, 48", + "line_range": [ + 314, + 322 + ] + }, + { + "text": "Encoding: rlist=9, spimm=2", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Example RV32I PUSH/POP sequences > cm.pop \\{ra, s0-s4}, 64", + "line_range": [ + 326, + 326 + ] + }, + { + "text": "[source,asm] ---- lw s4, 60(sp); lw s3, 56(sp); lw s2, 52(sp); lw s1, 48(sp); lw s0, 44(sp); lw ra, 40(sp); addi sp, sp, 64; ----", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Example RV32I PUSH/POP sequences > cm.pop \\{ra, s0-s4}, 64", + "line_range": [ + 330, + 339 + ] + }, + { + "text": "<<< [insns-cmpush,reftext=\"cm.push\"]", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > Example RV32I PUSH/POP sequences > cm.pop \\{ra, s0-s4}, 64", + "line_range": [ + 341, + 342 + ] + }, + { + "text": "Create stack frame: store ra and 0 to 12 saved registers to the stack frame, optionally allocate additional stack space.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.push", + "line_range": [ + 348, + 348 + ] + }, + { + "text": "cm.push \\{reglist}, -stackadj", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.push", + "line_range": [ + 352, + 352 + ] + }, + { + "text": "[wavedrom, , svg] .... {reg:[ { bits: 2, name: 0x2, attr: ['C2'] }, { bits: 2, name: 'spimm', attr: [] }, { bits: 4, name: 'rlist', attr: [] }, { bits: 5, name: 0x18, attr: [] }, { bits: 3, name: 0x5, attr: ['FUNCT3'] }, ],config:{bits:16}} ....", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.push", + "line_range": [ + 356, + 365 + ] + }, + { + "text": "[source,asm] -- cm.push \\{reglist}, -stackadj cm.push {xreglist}, -stackadj --", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.push", + "line_range": [ + 369, + 373 + ] + }, + { + "text": "The variables used in the assembly syntax are defined below.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.push", + "line_range": [ + 375, + 375 + ] + }, + { + "text": "switch (rlist){ case 4: \\{reglist=\"ra\"; xreglist=\"x1\";} case 5: \\{reglist=\"ra, s0\"; xreglist=\"x1, x8\";} case 6: \\{reglist=\"ra, s0-s1\"; xreglist=\"x1, x8-x9\";} default: reserved(); } stackadj = stackadjbase + spimm * 16; ----", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.push", + "line_range": [ + 381, + 388 + ] + }, + { + "text": "[source,sail] ---- RV32I, RV64: switch (rlist){ case 4: \\{reglist=\"ra\"; xreglist=\"x1\";} case 5: \\{reglist=\"ra, s0\"; xreglist=\"x1, x8\";} case 6: \\{reglist=\"ra, s0-s1\"; xreglist=\"x1, x8-x9\";} case 7: \\{reglist=\"ra, s0-s2\"; xreglist=\"x1, x8-x9, x18\";} case 8: \\{reglist=\"ra, s0-s3\"; xreglist=\"x1, x8-x9, x18-x19\";} case 9: \\{reglist=\"ra, s0-s4\"; xreglist=\"x1, x8-x9, x18-x20\";} case 10: \\{reglist=\"ra, s0-s5\"; xreglist=\"x1, x8-x9, x18-x21\";} case 11: \\{reglist=\"ra, s0-s6\"; xreglist=\"x1, x8-x9, x18-x22\";} case 12: \\{reglist=\"ra, s0-s7\"; xreglist=\"x1, x8-x9, x18-x23\";} case 13: \\{reglist=\"ra, s0-s8\"; xreglist=\"x1, x8-x9, x18-x24\";} case 14: \\{reglist=\"ra, s0-s9\"; xreglist=\"x1, x8-x9, x18-x25\";} //note - to include s10, s11 must also be included case 15: \\{reglist=\"ra, s0-s11\"; xreglist=\"x1, x8-x9, x18-x27\";} default: reserved(); } stackadj = stackadjbase + spimm * 16; ----", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.push", + "line_range": [ + 390, + 410 + ] + }, + { + "text": "Valid values: stackadj = [16|32|48|64]; ----", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.push", + "line_range": [ + 416, + 419 + ] + }, + { + "text": "switch (rlist) { case 4.. 7: stackadjbase = 16; case 8..11: stackadjbase = 32; case 12..14: stackadjbase = 48; case 15: stackadjbase = 64; }", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.push", + "line_range": [ + 425, + 430 + ] + }, + { + "text": "Valid values: switch (rlist) { case 4.. 7: stackadj = [16|32|48| 64]; case 8..11: stackadj = [32|48|64| 80]; case 12..14: stackadj = [48|64|80| 96]; case 15: stackadj = [64|80|96|112]; } ----", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.push", + "line_range": [ + 432, + 439 + ] + }, + { + "text": "switch (rlist) { case 4.. 5: stackadjbase = 16; case 6.. 7: stackadjbase = 32; case 8.. 9: stackadjbase = 48; case 10..11: stackadjbase = 64; case 12..13: stackadjbase = 80; case 14: stackadjbase = 96; case 15: stackadjbase = 112; }", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.push", + "line_range": [ + 445, + 453 + ] + }, + { + "text": "Valid values: switch (rlist) { case 4.. 5: stackadj = [ 16| 32| 48| 64]; case 6.. 7: stackadj = [ 32| 48| 64| 80]; case 8.. 9: stackadj = [ 48| 64| 80| 96]; case 10..11: stackadj = [ 64| 80| 96|112]; case 12..13: stackadj = [ 80| 96|112|128]; case 14: stackadj = [ 96|112|128|144]; case 15: stackadj = [112|128|144|160]; } ----", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.push", + "line_range": [ + 455, + 465 + ] + }, + { + "text": "This instruction pushes (stores) the registers in reglist to the memory below the stack pointer, and then creates the stack frame by decrementing the stack pointer by stackadj, including any additional stack space requested by the value of spimm.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.push", + "line_range": [ + 470, + 472 + ] + }, + { + "text": "For further information see ext:zcmp[].", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.push", + "line_range": [ + 474, + 474 + ] + }, + { + "text": "Stack Adjustment Calculation:", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.push", + "line_range": [ + 476, + 476 + ] + }, + { + "text": "stackadjbase is the minimum number of bytes, in multiples of 16-byte address increments, required to cover the registers in the list.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.push", + "line_range": [ + 478, + 478 + ] + }, + { + "text": "spimm is the number of additional 16-byte address increments allocated for the stack frame.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.push", + "line_range": [ + 480, + 480 + ] + }, + { + "text": "The total stack adjustment represents the total size of the stack frame, which is stackadjbase added to spimm scaled by 16, as defined above.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.push", + "line_range": [ + 482, + 483 + ] + }, + { + "text": "No direct equivalent encoding exists", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.push", + "line_range": [ + 491, + 491 + ] + }, + { + "text": "The first section of pseudocode may be executed multiple times before the instruction successfully completes.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.push", + "line_range": [ + 495, + 495 + ] + }, + { + "text": "[source,sail] ---- //This is not SAIL, it's pseudocode.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.push", + "line_range": [ + 497, + 499 + ] + }, + { + "text": "The SAIL hasn't been written yet.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.push", + "line_range": [ + 497, + 499 + ] + }, + { + "text": "if (XLEN32) bytes=4; else bytes=8;", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.push", + "line_range": [ + 501, + 501 + ] + }, + { + "text": "addr=sp-bytes; for(i in 27,26,25,24,23,22,21,20,19,18,9,8,1) { //if register i is in xreglist if (xreglist[i]) { switch(bytes) { 4: asm(\"sw x[i], 0(addr)\"); 8: asm(\"sd x[i], 0(addr)\"); } addr-=bytes; } } ----", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.push", + "line_range": [ + 503, + 514 + ] + }, + { + "text": "The final section of pseudocode executes atomically, and only executes if the section above completes without any exceptions or interrupts.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.push", + "line_range": [ + 516, + 516 + ] + }, + { + "text": "[source,sail] ---- //This is not SAIL, it's pseudocode.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.push", + "line_range": [ + 518, + 520 + ] + }, + { + "text": "The SAIL hasn't been written yet.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.push", + "line_range": [ + 518, + 520 + ] + }, + { + "text": "<<< [insns-cmpop,reftext=\"cm.pop\"]", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.push", + "line_range": [ + 525, + 526 + ] + }, + { + "text": "Destroy stack frame: load ra and 0 to 12 saved registers from the stack frame, deallocate the stack frame.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.pop", + "line_range": [ + 532, + 532 + ] + }, + { + "text": "cm.pop \\{reglist}, stackadj", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.pop", + "line_range": [ + 536, + 536 + ] + }, + { + "text": "[wavedrom, , svg] .... {reg:[ { bits: 2, name: 0x2, attr: ['C2'] }, { bits: 2, name: 'spimm', attr: [] }, { bits: 4, name: 'rlist', attr: [] }, { bits: 5, name: 0x1a, attr: [] }, { bits: 3, name: 0x5, attr: ['FUNCT3'] }, ],config:{bits:16}} ....", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.pop", + "line_range": [ + 540, + 549 + ] + }, + { + "text": "[source,asm] ---- cm.pop \\{reglist}, stackadj cm.pop {xreglist}, stackadj ----", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.pop", + "line_range": [ + 553, + 557 + ] + }, + { + "text": "The variables used in the assembly syntax are defined below.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.pop", + "line_range": [ + 559, + 559 + ] + }, + { + "text": "[source,sail] ---- RV32E: switch (rlist){ case 4: \\{reglist=\"ra\"; xreglist=\"x1\";} case 5: \\{reglist=\"ra, s0\"; xreglist=\"x1, x8\";} case 6: \\{reglist=\"ra, s0-s1\"; xreglist=\"x1, x8-x9\";} default: reserved(); } stackadj = stackadjbase + spimm * 16; ----", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.pop", + "line_range": [ + 561, + 571 + ] + }, + { + "text": "[source,sail] ---- RV32I, RV64: switch (rlist){ case 4: \\{reglist=\"ra\"; xreglist=\"x1\";} case 5: \\{reglist=\"ra, s0\"; xreglist=\"x1, x8\";} case 6: \\{reglist=\"ra, s0-s1\"; xreglist=\"x1, x8-x9\";} case 7: \\{reglist=\"ra, s0-s2\"; xreglist=\"x1, x8-x9, x18\";} case 8: \\{reglist=\"ra, s0-s3\"; xreglist=\"x1, x8-x9, x18-x19\";} case 9: \\{reglist=\"ra, s0-s4\"; xreglist=\"x1, x8-x9, x18-x20\";} case 10: \\{reglist=\"ra, s0-s5\"; xreglist=\"x1, x8-x9, x18-x21\";} case 11: \\{reglist=\"ra, s0-s6\"; xreglist=\"x1, x8-x9, x18-x22\";} case 12: \\{reglist=\"ra, s0-s7\"; xreglist=\"x1, x8-x9, x18-x23\";} case 13: \\{reglist=\"ra, s0-s8\"; xreglist=\"x1, x8-x9, x18-x24\";} case 14: \\{reglist=\"ra, s0-s9\"; xreglist=\"x1, x8-x9, x18-x25\";} //note - to include s10, s11 must also be included case 15: \\{reglist=\"ra, s0-s11\"; xreglist=\"x1, x8-x9, x18-x27\";} default: reserved(); } stackadj = stackadjbase + spimm * 16; ----", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.pop", + "line_range": [ + 573, + 593 + ] + }, + { + "text": "Valid values: stackadj = [16|32|48|64]; ----", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.pop", + "line_range": [ + 599, + 602 + ] + }, + { + "text": "switch (rlist) { case 4.. 7: stackadjbase = 16; case 8..11: stackadjbase = 32; case 12..14: stackadjbase = 48; case 15: stackadjbase = 64; }", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.pop", + "line_range": [ + 608, + 613 + ] + }, + { + "text": "Valid values: switch (rlist) { case 4.. 7: stackadj = [16|32|48| 64]; case 8..11: stackadj = [32|48|64| 80]; case 12..14: stackadj = [48|64|80| 96]; case 15: stackadj = [64|80|96|112]; } ----", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.pop", + "line_range": [ + 615, + 622 + ] + }, + { + "text": "switch (rlist) { case 4.. 5: stackadjbase = 16; case 6.. 7: stackadjbase = 32; case 8.. 9: stackadjbase = 48; case 10..11: stackadjbase = 64; case 12..13: stackadjbase = 80; case 14: stackadjbase = 96; case 15: stackadjbase = 112; }", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.pop", + "line_range": [ + 628, + 636 + ] + }, + { + "text": "Valid values: switch (rlist) { case 4.. 5: stackadj = [ 16| 32| 48| 64]; case 6.. 7: stackadj = [ 32| 48| 64| 80]; case 8.. 9: stackadj = [ 48| 64| 80| 96]; case 10..11: stackadj = [ 64| 80| 96|112]; case 12..13: stackadj = [ 80| 96|112|128]; case 14: stackadj = [ 96|112|128|144]; case 15: stackadj = [112|128|144|160]; } ----", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.pop", + "line_range": [ + 638, + 648 + ] + }, + { + "text": "This instruction pops (loads) the registers in reglist from stack memory, and then adjusts the stack pointer by stackadj.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.pop", + "line_range": [ + 654, + 655 + ] + }, + { + "text": "For further information see ext:zcmp[].", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.pop", + "line_range": [ + 657, + 657 + ] + }, + { + "text": "Stack Adjustment Calculation:", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.pop", + "line_range": [ + 659, + 659 + ] + }, + { + "text": "stackadjbase is the minimum number of bytes, in multiples of 16-byte address increments, required to cover the registers in the list.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.pop", + "line_range": [ + 661, + 661 + ] + }, + { + "text": "spimm is the number of additional 16-byte address increments allocated for the stack frame.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.pop", + "line_range": [ + 663, + 663 + ] + }, + { + "text": "The total stack adjustment represents the total size of the stack frame, which is stackadjbase added to spimm scaled by 16, as defined above.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.pop", + "line_range": [ + 665, + 666 + ] + }, + { + "text": "No direct equivalent encoding exists", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.pop", + "line_range": [ + 674, + 674 + ] + }, + { + "text": "The first section of pseudocode may be executed multiple times before the instruction successfully completes.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.pop", + "line_range": [ + 678, + 678 + ] + }, + { + "text": "[source,sail] ---- //This is not SAIL, it's pseudocode.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.pop", + "line_range": [ + 680, + 682 + ] + }, + { + "text": "The SAIL hasn't been written yet.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.pop", + "line_range": [ + 680, + 682 + ] + }, + { + "text": "if (XLEN32) bytes=4; else bytes=8;", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.pop", + "line_range": [ + 684, + 684 + ] + }, + { + "text": "addr=sp+stackadj-bytes; for(i in 27,26,25,24,23,22,21,20,19,18,9,8,1) { //if register i is in xreglist if (xreglist[i]) { switch(bytes) { 4: asm(\"lw x[i], 0(addr)\"); 8: asm(\"ld x[i], 0(addr)\"); } addr-=bytes; } } ----", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.pop", + "line_range": [ + 686, + 697 + ] + }, + { + "text": "The final section of pseudocode executes atomically, and only executes if the section above completes without any exceptions or interrupts.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.pop", + "line_range": [ + 699, + 699 + ] + }, + { + "text": "[source,sail] ---- //This is not SAIL, it's pseudocode.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.pop", + "line_range": [ + 701, + 703 + ] + }, + { + "text": "The SAIL hasn't been written yet.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.pop", + "line_range": [ + 701, + 703 + ] + }, + { + "text": "<<< [insns-cmpopretz,reftext=\"cm.popretz\"]", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.pop", + "line_range": [ + 708, + 709 + ] + }, + { + "text": "Destroy stack frame: load ra and 0 to 12 saved registers from the stack frame, deallocate the stack frame, move zero into a0, return to ra.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popretz", + "line_range": [ + 714, + 714 + ] + }, + { + "text": "cm.popretz \\{reglist}, stackadj", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popretz", + "line_range": [ + 718, + 718 + ] + }, + { + "text": "[wavedrom, , svg] .... {reg:[ { bits: 2, name: 0x2, attr: ['C2'] }, { bits: 2, name: 'spimm\\[5:4\\]', attr: [] }, { bits: 4, name: 'rlist', attr: [] }, { bits: 5, name: 0x1c, attr: [] }, { bits: 3, name: 0x5, attr: ['FUNCT3'] }, ],config:{bits:16}} ....", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popretz", + "line_range": [ + 722, + 731 + ] + }, + { + "text": "[source,sail] ---- cm.popretz \\{reglist}, stackadj cm.popretz {xreglist}, stackadj ----", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popretz", + "line_range": [ + 735, + 739 + ] + }, + { + "text": "[source,sail] ---- RV32E: switch (rlist){ case 4: \\{reglist=\"ra\"; xreglist=\"x1\";} case 5: \\{reglist=\"ra, s0\"; xreglist=\"x1, x8\";} case 6: \\{reglist=\"ra, s0-s1\"; xreglist=\"x1, x8-x9\";} default: reserved(); } stackadj = stackadjbase + spimm * 16; ----", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popretz", + "line_range": [ + 741, + 751 + ] + }, + { + "text": "[source,sail] ---- RV32I, RV64:", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popretz", + "line_range": [ + 753, + 755 + ] + }, + { + "text": "switch (rlist){ case 4: \\{reglist=\"ra\"; xreglist=\"x1\";} case 5: \\{reglist=\"ra, s0\"; xreglist=\"x1, x8\";} case 6: \\{reglist=\"ra, s0-s1\"; xreglist=\"x1, x8-x9\";} case 7: \\{reglist=\"ra, s0-s2\"; xreglist=\"x1, x8-x9, x18\";} case 8: \\{reglist=\"ra, s0-s3\"; xreglist=\"x1, x8-x9, x18-x19\";} case 9: \\{reglist=\"ra, s0-s4\"; xreglist=\"x1, x8-x9, x18-x20\";} case 10: \\{reglist=\"ra, s0-s5\"; xreglist=\"x1, x8-x9, x18-x21\";} case 11: \\{reglist=\"ra, s0-s6\"; xreglist=\"x1, x8-x9, x18-x22\";} case 12: \\{reglist=\"ra, s0-s7\"; xreglist=\"x1, x8-x9, x18-x23\";} case 13: \\{reglist=\"ra, s0-s8\"; xreglist=\"x1, x8-x9, x18-x24\";} case 14: \\{reglist=\"ra, s0-s9\"; xreglist=\"x1, x8-x9, x18-x25\";} //note - to include s10, s11 must also be included case 15: \\{reglist=\"ra, s0-s11\"; xreglist=\"x1, x8-x9, x18-x27\";} default: reserved(); } stackadj = stackadjbase + spimm * 16; ----", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popretz", + "line_range": [ + 757, + 774 + ] + }, + { + "text": "Valid values: stackadj = [16|32|48|64]; ----", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popretz", + "line_range": [ + 780, + 783 + ] + }, + { + "text": "switch (rlist) { case 4.. 7: stackadjbase = 16; case 8..11: stackadjbase = 32; case 12..14: stackadjbase = 48; case 15: stackadjbase = 64; }", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popretz", + "line_range": [ + 789, + 794 + ] + }, + { + "text": "Valid values: switch (rlist) { case 4.. 7: stackadj = [16|32|48| 64]; case 8..11: stackadj = [32|48|64| 80]; case 12..14: stackadj = [48|64|80| 96]; case 15: stackadj = [64|80|96|112]; } ----", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popretz", + "line_range": [ + 796, + 803 + ] + }, + { + "text": "switch (rlist) { case 4.. 5: stackadjbase = 16; case 6.. 7: stackadjbase = 32; case 8.. 9: stackadjbase = 48; case 10..11: stackadjbase = 64; case 12..13: stackadjbase = 80; case 14: stackadjbase = 96; case 15: stackadjbase = 112; }", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popretz", + "line_range": [ + 809, + 817 + ] + }, + { + "text": "Valid values: switch (rlist) { case 4.. 5: stackadj = [ 16| 32| 48| 64]; case 6.. 7: stackadj = [ 32| 48| 64| 80]; case 8.. 9: stackadj = [ 48| 64| 80| 96]; case 10..11: stackadj = [ 64| 80| 96|112]; case 12..13: stackadj = [ 80| 96|112|128]; case 14: stackadj = [ 96|112|128|144]; case 15: stackadj = [112|128|144|160]; } ----", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popretz", + "line_range": [ + 819, + 829 + ] + }, + { + "text": "This instruction pops (loads) the registers in reglist from stack memory, adjusts the stack pointer by stackadj, moves zero into a0 and then returns to ra.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popretz", + "line_range": [ + 835, + 835 + ] + }, + { + "text": "For further information see ext:zcmp[].", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popretz", + "line_range": [ + 837, + 837 + ] + }, + { + "text": "Stack Adjustment Calculation:", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popretz", + "line_range": [ + 839, + 839 + ] + }, + { + "text": "stackadjbase is the minimum number of bytes, in multiples of 16-byte address increments, required to cover the registers in the list.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popretz", + "line_range": [ + 841, + 841 + ] + }, + { + "text": "spimm is the number of additional 16-byte address increments allocated for the stack frame.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popretz", + "line_range": [ + 843, + 843 + ] + }, + { + "text": "The total stack adjustment represents the total size of the stack frame, which is stackadjbase added to spimm scaled by 16, as defined above.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popretz", + "line_range": [ + 845, + 845 + ] + }, + { + "text": "No direct equivalent encoding exists", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popretz", + "line_range": [ + 853, + 853 + ] + }, + { + "text": "The first section of pseudocode may be executed multiple times before the instruction successfully completes.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popretz", + "line_range": [ + 857, + 857 + ] + }, + { + "text": "[source,sail] ---- //This is not SAIL, it's pseudocode.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popretz", + "line_range": [ + 859, + 861 + ] + }, + { + "text": "The SAIL hasn't been written yet.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popretz", + "line_range": [ + 859, + 861 + ] + }, + { + "text": "if (XLEN32) bytes=4; else bytes=8;", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popretz", + "line_range": [ + 863, + 863 + ] + }, + { + "text": "addr=sp+stackadj-bytes; for(i in 27,26,25,24,23,22,21,20,19,18,9,8,1) { //if register i is in xreglist if (xreglist[i]) { switch(bytes) { 4: asm(\"lw x[i], 0(addr)\"); 8: asm(\"ld x[i], 0(addr)\"); } addr-=bytes; } } ----", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popretz", + "line_range": [ + 865, + 876 + ] + }, + { + "text": "The final section of pseudocode executes atomically, and only executes if the section above completes without any exceptions or interrupts.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popretz", + "line_range": [ + 878, + 878 + ] + }, + { + "text": "[source,sail] ---- //This is not SAIL, it's pseudocode.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popretz", + "line_range": [ + 880, + 882 + ] + }, + { + "text": "The SAIL hasn't been written yet.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popretz", + "line_range": [ + 880, + 882 + ] + }, + { + "text": "asm(\"li a0, 0\"); sp+=stackadj; asm(\"ret\"); ----", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popretz", + "line_range": [ + 884, + 887 + ] + }, + { + "text": "<<< [insns-cmpopret,reftext=\"cm.popret\"]", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popretz", + "line_range": [ + 889, + 890 + ] + }, + { + "text": "Destroy stack frame: load ra and 0 to 12 saved registers from the stack frame, deallocate the stack frame, return to ra.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popret", + "line_range": [ + 896, + 896 + ] + }, + { + "text": "cm.popret \\{reglist}, stackadj", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popret", + "line_range": [ + 900, + 900 + ] + }, + { + "text": "[wavedrom, , svg] .... {reg:[ { bits: 2, name: 0x2, attr: ['C2'] }, { bits: 2, name: 'spimm', attr: [] }, { bits: 4, name: 'rlist', attr: [] }, { bits: 5, name: 0x1e, attr: [] }, { bits: 3, name: 0x5, attr: ['FUNCT3'] }, ],config:{bits:16}} ....", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popret", + "line_range": [ + 904, + 913 + ] + }, + { + "text": "[source,sail] ---- cm.popret \\{reglist}, stackadj cm.popret {xreglist}, stackadj ----", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popret", + "line_range": [ + 917, + 921 + ] + }, + { + "text": "The variables used in the assembly syntax are defined below.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popret", + "line_range": [ + 923, + 923 + ] + }, + { + "text": "switch (rlist){ case 4: \\{reglist=\"ra\"; xreglist=\"x1\";} case 5: \\{reglist=\"ra, s0\"; xreglist=\"x1, x8\";} case 6: \\{reglist=\"ra, s0-s1\"; xreglist=\"x1, x8-x9\";} default: reserved(); } stackadj = stackadjbase + spimm * 16; ----", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popret", + "line_range": [ + 929, + 936 + ] + }, + { + "text": "[source,sail] ---- RV32I, RV64:", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popret", + "line_range": [ + 938, + 940 + ] + }, + { + "text": "switch (rlist){ case 4: \\{reglist=\"ra\"; xreglist=\"x1\";} case 5: \\{reglist=\"ra, s0\"; xreglist=\"x1, x8\";} case 6: \\{reglist=\"ra, s0-s1\"; xreglist=\"x1, x8-x9\";} case 7: \\{reglist=\"ra, s0-s2\"; xreglist=\"x1, x8-x9, x18\";} case 8: \\{reglist=\"ra, s0-s3\"; xreglist=\"x1, x8-x9, x18-x19\";} case 9: \\{reglist=\"ra, s0-s4\"; xreglist=\"x1, x8-x9, x18-x20\";} case 10: \\{reglist=\"ra, s0-s5\"; xreglist=\"x1, x8-x9, x18-x21\";} case 11: \\{reglist=\"ra, s0-s6\"; xreglist=\"x1, x8-x9, x18-x22\";} case 12: \\{reglist=\"ra, s0-s7\"; xreglist=\"x1, x8-x9, x18-x23\";} case 13: \\{reglist=\"ra, s0-s8\"; xreglist=\"x1, x8-x9, x18-x24\";} case 14: \\{reglist=\"ra, s0-s9\"; xreglist=\"x1, x8-x9, x18-x25\";} //note - to include s10, s11 must also be included case 15: \\{reglist=\"ra, s0-s11\"; xreglist=\"x1, x8-x9, x18-x27\";} default: reserved(); } stackadj = stackadjbase + spimm * 16; ----", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popret", + "line_range": [ + 942, + 959 + ] + }, + { + "text": "Valid values: stackadj = [16|32|48|64]; ----", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popret", + "line_range": [ + 965, + 968 + ] + }, + { + "text": "switch (rlist) { case 4.. 7: stackadjbase = 16; case 8..11: stackadjbase = 32; case 12..14: stackadjbase = 48; case 15: stackadjbase = 64; }", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popret", + "line_range": [ + 974, + 979 + ] + }, + { + "text": "Valid values: switch (rlist) { case 4.. 7: stackadj = [16|32|48| 64]; case 8..11: stackadj = [32|48|64| 80]; case 12..14: stackadj = [48|64|80| 96]; case 15: stackadj = [64|80|96|112]; } ----", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popret", + "line_range": [ + 981, + 988 + ] + }, + { + "text": "switch (rlist) { case 4.. 5: stackadjbase = 16; case 6.. 7: stackadjbase = 32; case 8.. 9: stackadjbase = 48; case 10..11: stackadjbase = 64; case 12..13: stackadjbase = 80; case 14: stackadjbase = 96; case 15: stackadjbase = 112; }", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popret", + "line_range": [ + 994, + 1002 + ] + }, + { + "text": "Valid values: switch (rlist) { case 4.. 5: stackadj = [ 16| 32| 48| 64]; case 6.. 7: stackadj = [ 32| 48| 64| 80]; case 8.. 9: stackadj = [ 48| 64| 80| 96]; case 10..11: stackadj = [ 64| 80| 96|112]; case 12..13: stackadj = [ 80| 96|112|128]; case 14: stackadj = [ 96|112|128|144]; case 15: stackadj = [112|128|144|160]; } ----", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popret", + "line_range": [ + 1004, + 1014 + ] + }, + { + "text": "This instruction pops (loads) the registers in reglist from stack memory, adjusts the stack pointer by stackadj and then returns to ra.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popret", + "line_range": [ + 1020, + 1020 + ] + }, + { + "text": "For further information see ext:zcmp[].", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popret", + "line_range": [ + 1022, + 1022 + ] + }, + { + "text": "Stack Adjustment Calculation:", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popret", + "line_range": [ + 1024, + 1024 + ] + }, + { + "text": "stackadjbase is the minimum number of bytes, in multiples of 16-byte address increments, required to cover the registers in the list.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popret", + "line_range": [ + 1026, + 1026 + ] + }, + { + "text": "spimm is the number of additional 16-byte address increments allocated for the stack frame.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popret", + "line_range": [ + 1028, + 1028 + ] + }, + { + "text": "The total stack adjustment represents the total size of the stack frame, which is stackadjbase added to spimm scaled by 16, as defined above.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popret", + "line_range": [ + 1030, + 1030 + ] + }, + { + "text": "No direct equivalent encoding exists", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popret", + "line_range": [ + 1038, + 1038 + ] + }, + { + "text": "The first section of pseudocode may be executed multiple times before the instruction successfully completes.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popret", + "line_range": [ + 1042, + 1042 + ] + }, + { + "text": "[source,sail] ---- //This is not SAIL, it's pseudocode.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popret", + "line_range": [ + 1044, + 1046 + ] + }, + { + "text": "The SAIL hasn't been written yet.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popret", + "line_range": [ + 1044, + 1046 + ] + }, + { + "text": "if (XLEN32) bytes=4; else bytes=8;", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popret", + "line_range": [ + 1048, + 1048 + ] + }, + { + "text": "addr=sp+stackadj-bytes; for(i in 27,26,25,24,23,22,21,20,19,18,9,8,1) { //if register i is in xreglist if (xreglist[i]) { switch(bytes) { 4: asm(\"lw x[i], 0(addr)\"); 8: asm(\"ld x[i], 0(addr)\"); } addr-=bytes; } } ----", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popret", + "line_range": [ + 1050, + 1061 + ] + }, + { + "text": "The final section of pseudocode executes atomically, and only executes if the section above completes without any exceptions or interrupts.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popret", + "line_range": [ + 1063, + 1063 + ] + }, + { + "text": "[source,sail] ---- //This is not SAIL, it's pseudocode.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popret", + "line_range": [ + 1065, + 1067 + ] + }, + { + "text": "The SAIL hasn't been written yet.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popret", + "line_range": [ + 1065, + 1067 + ] + }, + { + "text": "sp+=stackadj; asm(\"ret\"); ----", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popret", + "line_range": [ + 1069, + 1071 + ] + }, + { + "text": "[insns-cmmvsa01,reftext=\"Move a0-a1 into two different s0-s7 registers\"]", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.popret", + "line_range": [ + 1075, + 1075 + ] + }, + { + "text": "Move a0-a1 into two registers of s0-s7", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.mvsa01", + "line_range": [ + 1080, + 1080 + ] + }, + { + "text": "[wavedrom, , svg] .... {reg:[ { bits: 2, name: 0x2, attr: ['C2'] }, { bits: 3, name: 'r2s\\'', attr: [] }, { bits: 2, name: 0x1, attr: [] }, { bits: 3, name: 'r1s\\'', attr: [] }, { bits: 3, name: 0x3, attr: [] }, { bits: 3, name: 0x5, attr: ['FUNCT3'] }, ],config:{bits:16}} ....", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.mvsa01", + "line_range": [ + 1088, + 1098 + ] + }, + { + "text": "[source,asm] ---- cm.mvsa01 r1s', r2s' ----", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.mvsa01", + "line_range": [ + 1102, + 1105 + ] + }, + { + "text": "Description:: This instruction moves a0 into r1s' and a1 into r2s'. r1s' and r2s' must be different.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.mvsa01", + "line_range": [ + 1107, + 1109 + ] + }, + { + "text": "The execution is atomic, so it is not possible to observe state where only one of r1s' or r2s' has been updated.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.mvsa01", + "line_range": [ + 1107, + 1109 + ] + }, + { + "text": "The encoding uses sreg number specifiers instead of xreg number specifiers to save encoding space.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.mvsa01", + "line_range": [ + 1111, + 1112 + ] + }, + { + "text": "The mapping between them is specified in the pseudocode below.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.mvsa01", + "line_range": [ + 1111, + 1112 + ] + }, + { + "text": "No direct equivalent encoding exists.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.mvsa01", + "line_range": [ + 1120, + 1120 + ] + }, + { + "text": "[source,sail] ---- //This is not SAIL, it's pseudocode.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.mvsa01", + "line_range": [ + 1124, + 1134 + ] + }, + { + "text": "The SAIL hasn't been written yet. if (RV32E && (r1sc>1 || r2sc>1)) { reserved(); } xreg1 = {r1sc[2:1]>0,r1sc[2:1]0,r1sc[2:0]}; xreg2 = {r2sc[2:1]>0,r2sc[2:1]0,r2sc[2:0]}; X[xreg1] = X[10]; X[xreg2] = X[11]; ----", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.mvsa01", + "line_range": [ + 1124, + 1134 + ] + }, + { + "text": "[insns-cmmva01s,reftext=\"Move two s0-s7 registers into a0-a1\"]", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.mvsa01", + "line_range": [ + 1138, + 1138 + ] + }, + { + "text": "Move two s0-s7 registers into a0-a1", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.mva01s", + "line_range": [ + 1143, + 1143 + ] + }, + { + "text": "[wavedrom, , svg] .... {reg:[ { bits: 2, name: 0x2, attr: ['C2'] }, { bits: 3, name: 'r2s\\'', attr: [] }, { bits: 2, name: 0x3, attr: [] }, { bits: 3, name: 'r1s\\'', attr: [] }, { bits: 3, name: 0x3, attr: [] }, { bits: 3, name: 0x5, attr: ['FUNCT3'] }, ],config:{bits:16}} ....", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.mva01s", + "line_range": [ + 1151, + 1161 + ] + }, + { + "text": "[source,asm] ---- cm.mva01s r1s', r2s' ----", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.mva01s", + "line_range": [ + 1165, + 1168 + ] + }, + { + "text": "Description:: This instruction moves r1s' into a0 and r2s' into a1.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.mva01s", + "line_range": [ + 1170, + 1172 + ] + }, + { + "text": "The execution is atomic, so it is not possible to observe state where only one of a0 or a1 have been updated.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.mva01s", + "line_range": [ + 1170, + 1172 + ] + }, + { + "text": "The encoding uses sreg number specifiers instead of xreg number specifiers to save encoding space.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.mva01s", + "line_range": [ + 1174, + 1175 + ] + }, + { + "text": "The mapping between them is specified in the pseudocode below.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.mva01s", + "line_range": [ + 1174, + 1175 + ] + }, + { + "text": "No direct equivalent encoding exists.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.mva01s", + "line_range": [ + 1183, + 1183 + ] + }, + { + "text": "[source,sail] ---- //This is not SAIL, it's pseudocode.", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.mva01s", + "line_range": [ + 1187, + 1197 + ] + }, + { + "text": "The SAIL hasn't been written yet. if (RV32E && (r1sc>1 || r2sc>1)) { reserved(); } xreg1 = {r1sc[2:1]>0,r1sc[2:1]0,r1sc[2:0]}; xreg2 = {r2sc[2:1]>0,r2sc[2:1]0,r2sc[2:0]}; X[10] = X[xreg1]; X[11] = X[xreg2]; ----", + "section": "Preamble > ext:zcmp[] Extension for Compressed Prologues and Epilogues > PUSH/POP functional overview > cm.mva01s", + "line_range": [ + 1187, + 1197 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zcmt.json b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zcmt.json new file mode 100644 index 0000000000..cbd98f3635 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zcmt.json @@ -0,0 +1,574 @@ +{ + "source_file": "src/unpriv/zcmt.adoc", + "total": 71, + "sentences": [ + { + "text": "The ext:zcmt[] extension adds table-jump instructions, which improve code density when procedures have many call sites.", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps", + "line_range": [ + 3, + 7 + ] + }, + { + "text": "It also adds the csr:jvt[] CSR.", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps", + "line_range": [ + 3, + 7 + ] + }, + { + "text": "The csr:jvt[] CSR requires a state enable if Smstateen is implemented.", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps", + "line_range": [ + 3, + 7 + ] + }, + { + "text": "The ext:zcmt[] extension conflicts with the ext:zcd[] extension.", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps", + "line_range": [ + 9, + 9 + ] + }, + { + "text": "NOTE: ext:zcmt[] is primarily targeted at embedded class CPUs due to implementation complexity.", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps", + "line_range": [ + 11, + 12 + ] + }, + { + "text": "Additionally, it is not compatible with RVA profiles.", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps", + "line_range": [ + 11, + 12 + ] + }, + { + "text": "The ext:zcmt[] extension depends on the extlink:zca[] and extlink:zicsr[] extensions.", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps", + "line_range": [ + 14, + 14 + ] + }, + { + "text": "| |RV32 |RV64 |Mnemonic |Instruction", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps", + "line_range": [ + 16, + 21 + ] + }, + { + "text": "|yes |yes |cm.jalt index |", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps", + "line_range": [ + 28, + 31 + ] + }, + { + "text": "[insns-tablejump,reftext=\"Table Jump Overview\"]", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps", + "line_range": [ + 35, + 35 + ] + }, + { + "text": "cm.jt () and cm.jalt () are referred to as table jump.", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview", + "line_range": [ + 38, + 38 + ] + }, + { + "text": "Table jump uses a 256-entry XLEN wide table in instruction memory to contain function addresses.", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview", + "line_range": [ + 40, + 41 + ] + }, + { + "text": "The table must be a minimum of 64-byte aligned.", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview", + "line_range": [ + 40, + 41 + ] + }, + { + "text": "Table entries follow the current data endianness.", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview", + "line_range": [ + 43, + 43 + ] + }, + { + "text": "This is different from normal instruction fetch which is always little-endian.", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview", + "line_range": [ + 43, + 43 + ] + }, + { + "text": "cm.jt and cm.jalt encodings index the table, giving access to functions within the full XLEN wide address space.", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview", + "line_range": [ + 45, + 45 + ] + }, + { + "text": "This is used as a form of dictionary compression to reduce the code size of jal / auipc+jalr / jr / auipc+jr instructions.", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview", + "line_range": [ + 47, + 47 + ] + }, + { + "text": "Table jump allows the linker to replace the following instruction sequences with a cm.jt or cm.jalt encoding, and an entry in the table:", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview", + "line_range": [ + 49, + 49 + ] + }, + { + "text": "32-bit j calls * 32-bit jal ra calls * 64-bit auipc+jr calls to fixed locations * 64-bit auipc+jalr ra calls to fixed locations ** The auipc+jr/jalr sequence is used because the offset from the PC is out of the ±1{nbsp}MB range.", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview", + "line_range": [ + 51, + 55 + ] + }, + { + "text": "If a return address stack is implemented, then as cm.jalt is equivalent to jal ra, it pushes to the stack.", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview", + "line_range": [ + 57, + 57 + ] + }, + { + "text": "The base of the table is in the jvt CSR (see ), each table entry is XLEN bits.", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > jvt", + "line_range": [ + 61, + 61 + ] + }, + { + "text": "If the same function is called with and without linking then it must have two entries in the table.", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > jvt", + "line_range": [ + 63, + 64 + ] + }, + { + "text": "This is typically caused by the same function being called with and without tail calling.", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > jvt", + "line_range": [ + 63, + 64 + ] + }, + { + "text": "[tablejump-fault-handling]", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > jvt", + "line_range": [ + 66, + 66 + ] + }, + { + "text": "For a table jump instruction, the table entry that the instruction selects is considered an extension of the instruction itself.", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > Table Jump Fault handling", + "line_range": [ + 69, + 72 + ] + }, + { + "text": "Hence, the execution of a table jump instruction involves two instruction fetches, the first to read the instruction (cm.jt/cm.jalt) and the second to read from the jump vector table (JVT).", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > Table Jump Fault handling", + "line_range": [ + 69, + 72 + ] + }, + { + "text": "Both instruction fetches are implicit reads, and both require execute permission; read permission is irrelevant.", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > Table Jump Fault handling", + "line_range": [ + 69, + 72 + ] + }, + { + "text": "It is recommended that the second fetch be ignored for hardware triggers and breakpoints.", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > Table Jump Fault handling", + "line_range": [ + 69, + 72 + ] + }, + { + "text": "Memory writes to the jump vector table require an instruction barrier (fence.i) to guarantee that they are visible to the instruction fetch.", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > Table Jump Fault handling", + "line_range": [ + 74, + 74 + ] + }, + { + "text": "Multiple contexts may have different jump vector tables. JVT may be switched between them without an instruction barrier if the tables have not been updated in memory since the last fence.i.", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > Table Jump Fault handling", + "line_range": [ + 76, + 77 + ] + }, + { + "text": "If an exception occurs on either instruction fetch, xEPC is set to the PC of the table jump instruction, xCAUSE is set as expected for the type of fault and xTVAL (if not set to zero) contains the fetch address which caused the fault.", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > Table Jump Fault handling", + "line_range": [ + 79, + 79 + ] + }, + { + "text": "<<< [csrs-jvt,reftext=\"jvt CSR, table jump base vector and control register\"]", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > Table Jump Fault handling", + "line_range": [ + 81, + 82 + ] + }, + { + "text": "Table jump base vector and control register", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > jvt CSR", + "line_range": [ + 87, + 87 + ] + }, + { + "text": "[wavedrom, , svg] .... {reg:[ { bits: 6, name: 'mode', attr: ['6'] }, { bits: 26, name: 'base[XLEN-1:6] (WARL)', attr: ['XLEN-6'] }, ],config:{bits:32}} ....", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > jvt CSR", + "line_range": [ + 99, + 105 + ] + }, + { + "text": "[wavedrom, , svg] .... {reg:[ { bits: 6, name: 'mode', attr: ['6'] }, { bits: 58, name: 'base[XLEN-1:6] (WARL)', attr: ['XLEN-6'] }, ],config:{bits:64}} ....", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > jvt CSR", + "line_range": [ + 109, + 115 + ] + }, + { + "text": "The jvt register is an XLEN-bit *WARL* read/write register that holds the jump table configuration, consisting of the jump table base address (BASE) and the jump table mode (MODE).", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > jvt CSR", + "line_range": [ + 119, + 119 + ] + }, + { + "text": "If ext:zcmt[] is implemented then jvt must also be implemented, but can contain a read-only value.", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > jvt CSR", + "line_range": [ + 121, + 122 + ] + }, + { + "text": "If jvt is writable, the set of values the register may hold can vary by implementation.", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > jvt CSR", + "line_range": [ + 121, + 122 + ] + }, + { + "text": "The value in the BASE field must always be aligned on a 64-byte boundary.", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > jvt CSR", + "line_range": [ + 121, + 122 + ] + }, + { + "text": "Note that the CSR contains only bits XLEN-1 through 6 of the address base.", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > jvt CSR", + "line_range": [ + 121, + 122 + ] + }, + { + "text": "When computing jump-table accesses, the lower six bits of base are filled with zeroes to obtain an XLEN-bit jump-table base address jvt.base that is always aligned on a 64-byte boundary.", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > jvt CSR", + "line_range": [ + 121, + 122 + ] + }, + { + "text": "jvt.base is a virtual address, whenever virtual memory is enabled.", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > jvt CSR", + "line_range": [ + 124, + 124 + ] + }, + { + "text": "The memory pointed to by jvt.base is treated as instruction memory for the purpose of executing table jump instructions, implying execute access permission.", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > jvt CSR", + "line_range": [ + 126, + 126 + ] + }, + { + "text": "[JVT-config-table] .jvt.mode definition [width=\"60%\",options=header] | | jvt.mode | Comment | 000000 | Jump table mode | others | *reserved for future standard use* |", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > jvt CSR", + "line_range": [ + 128, + 135 + ] + }, + { + "text": "jvt.mode is a *WARL* field, so can only be programmed to modes which are implemented.", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > jvt CSR", + "line_range": [ + 137, + 138 + ] + }, + { + "text": "Therefore the discovery mechanism is to attempt to program different modes and read back the values to see which are available.", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > jvt CSR", + "line_range": [ + 137, + 138 + ] + }, + { + "text": "Jump table mode must be implemented.", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > jvt CSR", + "line_range": [ + 137, + 138 + ] + }, + { + "text": "jvt CSR adds architectural state to the system software context (such as an OS process), therefore must be saved/restored on context switches. <<< [insns-cmjt,reftext=\"Jump via table\"]", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > jvt CSR", + "line_range": [ + 142, + 144 + ] + }, + { + "text": "[wavedrom, , svg] .... {reg:[ { bits: 2, name: 0x2, attr: ['C2'] }, { bits: 8, name: 'index', attr: [] }, { bits: 3, name: 0x0, attr: [] }, { bits: 3, name: 0x5, attr: ['FUNCT3'] }, ],config:{bits:16}} ....", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > cm.jt", + "line_range": [ + 157, + 165 + ] + }, + { + "text": "[source,asm] ---- cm.jt index ----", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > cm.jt", + "line_range": [ + 169, + 172 + ] + }, + { + "text": "cm.jt reads an entry from the jump vector table in memory and jumps to the address that was read.", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > cm.jt", + "line_range": [ + 176, + 176 + ] + }, + { + "text": "For further information see .", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > cm.jt", + "line_range": [ + 178, + 178 + ] + }, + { + "text": "No direct equivalent encoding exists.", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > cm.jt", + "line_range": [ + 186, + 186 + ] + }, + { + "text": "[insns-cmjt-SAIL,reftext=\"cm.jt SAIL code\"] Operation::", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > cm.jt", + "line_range": [ + 190, + 191 + ] + }, + { + "text": "[source,sail] ---- //This is not SAIL, it's pseudocode.", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > cm.jt", + "line_range": [ + 193, + 195 + ] + }, + { + "text": "The SAIL hasn't been written yet.", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > cm.jt", + "line_range": [ + 193, + 195 + ] + }, + { + "text": "tableaddress is temporary internal state, it doesn't represent a real register InstMemory is byte indexed", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > cm.jt", + "line_range": [ + 197, + 198 + ] + }, + { + "text": "switch(XLEN) { 32: tableaddress[XLEN-1:0] = jvt.base + (index<<2); 64: tableaddress[XLEN-1:0] = jvt.base + (index<<3); }", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > cm.jt", + "line_range": [ + 200, + 203 + ] + }, + { + "text": "<<< [insns-cmjalt,reftext=\"Jump and link via table\"]", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > cm.jt", + "line_range": [ + 210, + 211 + ] + }, + { + "text": "jump via table with optional link", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > cm.jalt", + "line_range": [ + 216, + 216 + ] + }, + { + "text": "[wavedrom, , svg] .... {reg:[ { bits: 2, name: 0x2, attr: ['C2'] }, { bits: 8, name: 'index', attr: [] }, { bits: 3, name: 0x0, attr: [] }, { bits: 3, name: 0x5, attr: ['FUNCT3'] }, ],config:{bits:16}} ....", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > cm.jalt", + "line_range": [ + 224, + 232 + ] + }, + { + "text": "[source,asm] ---- cm.jalt index ----", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > cm.jalt", + "line_range": [ + 236, + 239 + ] + }, + { + "text": "cm.jalt reads an entry from the jump vector table in memory and jumps to the address that was read, linking to ra.", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > cm.jalt", + "line_range": [ + 243, + 243 + ] + }, + { + "text": "For further information see .", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > cm.jalt", + "line_range": [ + 245, + 245 + ] + }, + { + "text": "No direct equivalent encoding exists.", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > cm.jalt", + "line_range": [ + 253, + 253 + ] + }, + { + "text": "[insns-cmjalt-SAIL,reftext=\"cm.jalt SAIL code\"] Operation::", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > cm.jalt", + "line_range": [ + 257, + 258 + ] + }, + { + "text": "[source,sail] ---- //This is not SAIL, it's pseudocode.", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > cm.jalt", + "line_range": [ + 260, + 262 + ] + }, + { + "text": "The SAIL hasn't been written yet.", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > cm.jalt", + "line_range": [ + 260, + 262 + ] + }, + { + "text": "tableaddress is temporary internal state, it doesn't represent a real register InstMemory is byte indexed", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > cm.jalt", + "line_range": [ + 264, + 265 + ] + }, + { + "text": "switch(XLEN) { 32: tableaddress[XLEN-1:0] = jvt.base + (index<<2); 64: tableaddress[XLEN-1:0] = jvt.base + (index<<3); }", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > cm.jalt", + "line_range": [ + 267, + 270 + ] + }, + { + "text": "ra = pc+2; pc = InstMemory[tableaddress][XLEN-1:0]&~0x1; // Clear bit 0.", + "section": "Preamble > ext:zcmt[] Extension for Compressed Table Jumps > Table Jump Overview > cm.jalt", + "line_range": [ + 274, + 275 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zf.json b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zf.json new file mode 100644 index 0000000000..544e0bd70d --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zf.json @@ -0,0 +1,70 @@ +{ + "source_file": "src/unpriv/zf.adoc", + "total": 8, + "sentences": [ + { + "text": "NOTE: This chapter is currently being restructured.", + "section": "Preamble > Scalar Floating-Point Extensions", + "line_range": [ + 3, + 4 + ] + }, + { + "text": "Its contents are normative, but the presentation might appear disjoint.", + "section": "Preamble > Scalar Floating-Point Extensions", + "line_range": [ + 3, + 4 + ] + }, + { + "text": "This chapter describes the scalar floating-point extensions.", + "section": "Preamble > Scalar Floating-Point Extensions", + "line_range": [ + 6, + 13 + ] + }, + { + "text": "The extension adds floating-point registers and instructions for computation on single-precision floating-point values.", + "section": "Preamble > Scalar Floating-Point Extensions", + "line_range": [ + 6, + 13 + ] + }, + { + "text": "The and extensions widen those registers to hold double- and quad-precision floating-point values, respectively, and add instructions for computation on those formats.", + "section": "Preamble > Scalar Floating-Point Extensions", + "line_range": [ + 6, + 13 + ] + }, + { + "text": "Several additional extensions with the `Zf` and `Zd` prefixes provide additional computational instructions.", + "section": "Preamble > Scalar Floating-Point Extensions", + "line_range": [ + 6, + 13 + ] + }, + { + "text": "The and extensions add computational instructions analogous to those in the `F` and `D` extensions, but they instead operate on floating-point numbers in the `x` registers.", + "section": "Preamble > Scalar Floating-Point Extensions", + "line_range": [ + 15, + 19 + ] + }, + { + "text": "These extensions, intended for lower-cost systems, are incompatible with the `F` and `D` extensions.", + "section": "Preamble > Scalar Floating-Point Extensions", + "line_range": [ + 15, + 19 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zfa.json b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zfa.json new file mode 100644 index 0000000000..5e390270d5 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zfa.json @@ -0,0 +1,398 @@ +{ + "source_file": "src/unpriv/zfa.adoc", + "total": 49, + "sentences": [ + { + "text": "This chapter describes the Zfa standard extension, which adds instructions for immediate loads, IEEE 754-2019 `minimum` and `maximum` operations, round-to-integer operations, and quiet floating-point comparisons.", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0", + "line_range": [ + 3, + 10 + ] + }, + { + "text": "For RV32D, the Zfa extension also adds instructions to transfer double-precision floating-point values to and from integer registers, and for RV64Q, it adds analogous instructions for quad-precision floating-point values.", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0", + "line_range": [ + 3, + 10 + ] + }, + { + "text": "The Zfa extension depends on the F extension.", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0", + "line_range": [ + 3, + 10 + ] + }, + { + "text": "The FLI.S instruction loads one of 32 single-precision floating-point constants, encoded in the rs1 field, into floating-point register rd.", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions", + "line_range": [ + 14, + 19 + ] + }, + { + "text": "The correspondence of rs1 field values and single-precision floating-point values is shown in . FLI.S is encoded like FMV.W.X, but with rs2=1.", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions", + "line_range": [ + 14, + 19 + ] + }, + { + "text": ".Immediate values loaded by the FLI.S instruction. | |rs1 |Value |Sign |Exponent |Significand |0 |−1.0 |`1` |`01111111` |`000...000` |1 |Minimum positive normal |`0` |`00000001` |`000...000` |2 |1.0 × 2^−16^ |`0` |`01101111` |`000...000` |3 |1.0 × 2^−15^ |`0` |`01110000` |`000...000` |4 |1.0 × 2^−8^ |`0` |`01110111` |`000...000` |5 |1.0 × 2^−7^ |`0` |`01111000` |`000...000` |6 |0.0625 (2^−4^) |`0` |`01111011` |`000...000` |7 |0.125 (2^−3^) |`0` |`01111100` |`000...000` |8 |0.25 |`0` |`01111101` |`000...000` |9 |0.3125 |`0` |`01111101` |`010...000` |10 |0.375 |`0` |`01111101` |`100...000` |11 |0.4375 |`0` |`01111101` |`110...000` |12 |0.5 |`0` |`01111110` |`000...000` |13 |0.625 |`0` |`01111110` |`010...000` |14 |0.75 |`0` |`01111110` |`100...000` |15 |0.875 |`0` |`01111110` |`110...000` |16 |1.0 |`0` |`01111111` |`000...000` |17 |1.25 |`0` |`01111111` |`010...000` |18 |1.5 |`0` |`01111111` |`100...000` |19 |1.75 |`0` |`01111111` |`110...000` |20 |2.0 |`0` |`10000000` |`000...000` |21 |2.5 |`0` |`10000000` |`010...000` |22 |3 |`0` |`10000000` |`100...000` |23 |4 |`0` |`10000001` |`000...000` |24 |8 |`0` |`10000010` |`000...000` |25 |16 |`0` |`10000011` |`000...000` |26 |128 (2^7^) |`0` |`10000110` |`000...000` |27 |256 (2^8^) |`0` |`10000111` |`000...000` |28 |2^15^ |`0` |`10001110` |`000...000` |29 |2^16^ |`0` |`10001111` |`000...000` |30 |+{inf} |`0` |`11111111` |`000...000` |31 |Canonical NaN |`0` |`11111111` |`100...000` |", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions", + "line_range": [ + 21, + 58 + ] + }, + { + "text": "If the D extension is implemented, FLI.D performs the analogous operation, but loads a double-precision value into floating-point register rd.", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions", + "line_range": [ + 60, + 66 + ] + }, + { + "text": "Note that entry 1 (corresponding to the minimum positive normal value) has a numerically different value for double-precision than for single-precision. FLI.D is encoded like FLI.S, but with fmt=D.", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions", + "line_range": [ + 60, + 66 + ] + }, + { + "text": "If the Q extension is implemented, FLI.Q performs the analogous operation, but loads a quad-precision value into floating-point register rd.", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions", + "line_range": [ + 68, + 73 + ] + }, + { + "text": "Note that entry 1 (corresponding to the minimum positive normal value) has a numerically different value for quad-precision. FLI.Q is encoded like FLI.S, but with fmt=Q.", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions", + "line_range": [ + 68, + 73 + ] + }, + { + "text": "If the Zfh or Zvfh extension is implemented, FLI.H performs the analogous operation, but loads a half-precision floating-point value into register rd.", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions", + "line_range": [ + 75, + 84 + ] + }, + { + "text": "Note that entry 1 (corresponding to the minimum positive normal value) has a numerically different value for half-precision.", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions", + "line_range": [ + 75, + 84 + ] + }, + { + "text": "Furthermore, since 2^16^ is not representable in half-precision floating-point, entry 29 in the table instead loads positive infinity—i.e., it is redundant with entry 30. FLI.H is encoded like FLI.S, but with fmt=H.", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions", + "line_range": [ + 75, + 84 + ] + }, + { + "text": "The FLI.fmt instructions never set any floating-point exception flags.", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions", + "line_range": [ + 75, + 84 + ] + }, + { + "text": "The FMINM.S and FMAXM.S instructions are defined like the FMIN.S and FMAX.S instructions, except that if either input is NaN, the result is the canonical NaN.", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Minimum and Maximum Instructions", + "line_range": [ + 88, + 91 + ] + }, + { + "text": "If the D extension is implemented, FMINM.D and FMAXM.D instructions are analogously defined to operate on double-precision numbers.", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Minimum and Maximum Instructions", + "line_range": [ + 93, + 95 + ] + }, + { + "text": "If the Zfh extension is implemented, FMINM.H and FMAXM.H instructions are analogously defined to operate on half-precision numbers.", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Minimum and Maximum Instructions", + "line_range": [ + 97, + 99 + ] + }, + { + "text": "If the Q extension is implemented, FMINM.Q and FMAXM.Q instructions are analogously defined to operate on quad-precision numbers.", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Minimum and Maximum Instructions", + "line_range": [ + 101, + 103 + ] + }, + { + "text": "These instructions are encoded like their FMIN and FMAX counterparts, but with instruction bit 13 set to 1.", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Minimum and Maximum Instructions", + "line_range": [ + 105, + 106 + ] + }, + { + "text": "The FROUND.S instruction rounds the single-precision floating-point number in floating-point register rs1 to an integer, according to the rounding mode specified in the instruction's rm field.", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Round-to-Integer Instructions", + "line_range": [ + 109, + 116 + ] + }, + { + "text": "It then writes that integer, represented as a single-precision floating-point number, to floating-point register rd.", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Round-to-Integer Instructions", + "line_range": [ + 109, + 116 + ] + }, + { + "text": "Zero and infinite inputs are copied to rd unmodified.", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Round-to-Integer Instructions", + "line_range": [ + 109, + 116 + ] + }, + { + "text": "Signaling NaN inputs cause the invalid operation exception flag to be set; no other exception flags are set. FROUND.S is encoded like FCVT.S.D, but with rs2=4.", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Round-to-Integer Instructions", + "line_range": [ + 109, + 116 + ] + }, + { + "text": "The FROUNDNX.S instruction is defined similarly, but it also sets the inexact exception flag if the input differs from the rounded result and is not NaN. FROUNDNX.S is encoded like FCVT.S.D, but with rs2=5.", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Round-to-Integer Instructions", + "line_range": [ + 118, + 121 + ] + }, + { + "text": "If the D extension is implemented, FROUND.D and FROUNDNX.D instructions are analogously defined to operate on double-precision numbers.", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Round-to-Integer Instructions", + "line_range": [ + 123, + 126 + ] + }, + { + "text": "They are encoded like FCVT.D.S, but with rs2=4 and 5, respectively,", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Round-to-Integer Instructions", + "line_range": [ + 123, + 126 + ] + }, + { + "text": "If the Zfh extension is implemented, FROUND.H and FROUNDNX.H instructions are analogously defined to operate on half-precision numbers.", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Round-to-Integer Instructions", + "line_range": [ + 128, + 132 + ] + }, + { + "text": "They are encoded like FCVT.H.S, but with rs2=4 and 5, respectively,", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Round-to-Integer Instructions", + "line_range": [ + 128, + 132 + ] + }, + { + "text": "If the Q extension is implemented, FROUND.Q and FROUNDNX.Q instructions are analogously defined to operate on quad-precision numbers.", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Round-to-Integer Instructions", + "line_range": [ + 134, + 137 + ] + }, + { + "text": "They are encoded like FCVT.Q.S, but with rs2=4 and 5, respectively,", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Round-to-Integer Instructions", + "line_range": [ + 134, + 137 + ] + }, + { + "text": "The FCVTMOD.W.D instruction is defined similarly to the FCVT.W.D instruction, with the following differences. FCVTMOD.W.D always rounds towards zero.", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Modular Convert-to-Integer Instruction", + "line_range": [ + 140, + 146 + ] + }, + { + "text": "Bits 31:0 are taken from the rounded, unbounded two's complement result, then sign-extended to XLEN bits and written to integer register rd. ±{inf} and NaN are converted to zero.", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Modular Convert-to-Integer Instruction", + "line_range": [ + 140, + 146 + ] + }, + { + "text": "Floating-point exception flags are raised the same as they would be for FCVT.W.D with the same input operand.", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Modular Convert-to-Integer Instruction", + "line_range": [ + 148, + 150 + ] + }, + { + "text": "This instruction is only provided if the D extension is implemented.", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Modular Convert-to-Integer Instruction", + "line_range": [ + 152, + 154 + ] + }, + { + "text": "It is encoded like FCVT.W.D, but with the rs2 field set to 8 and the rm field set to 1 (RTZ).", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Modular Convert-to-Integer Instruction", + "line_range": [ + 152, + 154 + ] + }, + { + "text": "Other rm values are reserved.", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Modular Convert-to-Integer Instruction", + "line_range": [ + 152, + 154 + ] + }, + { + "text": "For RV32 only, if the D extension is implemented, the FMVH.X.D instruction moves bits 63:32 of floating-point register rs1 into integer register rd.", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Move Instructions", + "line_range": [ + 157, + 168 + ] + }, + { + "text": "It is encoded in the OP-FP major opcode with funct3=0, rs2=1, and funct7=1110001.", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Move Instructions", + "line_range": [ + 157, + 168 + ] + }, + { + "text": "For RV32 only, if the D extension is implemented, the FMVP.D.X instruction moves a double-precision number from a pair of integer registers into a floating-point register.", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Move Instructions", + "line_range": [ + 157, + 168 + ] + }, + { + "text": "Integer registers rs1 and rs2 supply bits 31:0 and 63:32, respectively; the result is written to floating-point register rd. FMVP.D.X is encoded in the OP-FP major opcode with funct3=0 and funct7=1011001.", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Move Instructions", + "line_range": [ + 157, + 168 + ] + }, + { + "text": "For RV64 only, if the Q extension is implemented, the FMVH.X.Q instruction moves bits 127:64 of floating-point register rs1 into integer register rd.", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Move Instructions", + "line_range": [ + 170, + 181 + ] + }, + { + "text": "It is encoded in the OP-FP major opcode with funct3=0, rs2=1, and funct7=1110011.", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Move Instructions", + "line_range": [ + 170, + 181 + ] + }, + { + "text": "For RV64 only, if the Q extension is implemented, the FMVP.Q.X instruction moves a double-precision number from a pair of integer registers into a floating-point register.", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Move Instructions", + "line_range": [ + 170, + 181 + ] + }, + { + "text": "Integer registers rs1 and rs2 supply bits 63:0 and 127:64, respectively; the result is written to floating-point register rd. FMVP.Q.X is encoded in the OP-FP major opcode with funct3=0 and funct7=1011011.", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Move Instructions", + "line_range": [ + 170, + 181 + ] + }, + { + "text": "The FLEQ.S and FLTQ.S instructions are defined like the FLE.S and FLT.S instructions, except that quiet NaN inputs do not cause the invalid operation exception flag to be set.", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Comparison Instructions", + "line_range": [ + 185, + 188 + ] + }, + { + "text": "If the D extension is implemented, FLEQ.D and FLTQ.D instructions are analogously defined to operate on double-precision numbers.", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Comparison Instructions", + "line_range": [ + 190, + 192 + ] + }, + { + "text": "If the Zfh extension is implemented, FLEQ.H and FLTQ.H instructions are analogously defined to operate on half-precision numbers.", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Comparison Instructions", + "line_range": [ + 194, + 196 + ] + }, + { + "text": "If the Q extension is implemented, FLEQ.Q and FLTQ.Q instructions are analogously defined to operate on quad-precision numbers.", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Comparison Instructions", + "line_range": [ + 198, + 200 + ] + }, + { + "text": "These instructions are encoded like their FLE and FLT counterparts, but with instruction bit 14 set to 1.", + "section": "Preamble > \"Zfa\" Extension for Additional Floating-Point Instructions, Version 1.0 > Load-Immediate Instructions > Comparison Instructions", + "line_range": [ + 202, + 203 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zfbfmin.json b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zfbfmin.json new file mode 100644 index 0000000000..6982bfd4ab --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zfbfmin.json @@ -0,0 +1,182 @@ +{ + "source_file": "src/unpriv/zfbfmin.adoc", + "total": 22, + "sentences": [ + { + "text": "This extension provides the minimal set of instructions needed to enable scalar support of the BF16 format.", + "section": "Preamble > `Zfbfmin` Extension for Scalar BFloat16 Conversions", + "line_range": [ + 3, + 5 + ] + }, + { + "text": "It enables BF16 as an interchange format as it provides conversion between BF16 values and FP32 values.", + "section": "Preamble > `Zfbfmin` Extension for Scalar BFloat16 Conversions", + "line_range": [ + 3, + 5 + ] + }, + { + "text": "This extension depends upon the single-precision floating-point extension `F`.", + "section": "Preamble > `Zfbfmin` Extension for Scalar BFloat16 Conversions", + "line_range": [ + 7, + 8 + ] + }, + { + "text": "This extension includes six instructions: the `FCVT.BF16.S` and `FCVT.S.BF16` instructions, defined below, and the `FLH`, `FSH`, `FMV.X.H`, and `FMV.H.X` instructions, defined in .", + "section": "Preamble > `Zfbfmin` Extension for Scalar BFloat16 Conversions", + "line_range": [ + 10, + 12 + ] + }, + { + "text": "BF16 bits:: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 'frac'}, {bits: 8, name: 'expo'}, {bits: 1, name: 'S'}, ]} ....", + "section": "Preamble > `Zfbfmin` Extension for Scalar BFloat16 Conversions > BF16 Number Format", + "line_range": [ + 16, + 24 + ] + }, + { + "text": "While BF16 (also known as BFloat16) is not an IEEE 754 standard format, it is a valid floating-point format as defined by IEEE 754-2008, with radix 2, number of significand digits 8, and maximum exponent 127.", + "section": "Preamble > `Zfbfmin` Extension for Scalar BFloat16 Conversions > BF16 Number Format", + "line_range": [ + 26, + 28 + ] + }, + { + "text": "BF16 computational instructions defined in this chapter support all IEEE 754-2008 features, including all rounding modes, subnormal inputs and outputs, overflow and underflow, and default exception handling.", + "section": "Preamble > `Zfbfmin` Extension for Scalar BFloat16 Conversions > BF16 Number Format", + "line_range": [ + 30, + 34 + ] + }, + { + "text": "Tininess is detected after rounding.", + "section": "Preamble > `Zfbfmin` Extension for Scalar BFloat16 Conversions > BF16 Number Format", + "line_range": [ + 30, + 34 + ] + }, + { + "text": "The BF16 canonical NaN is `0x7fc0`.", + "section": "Preamble > `Zfbfmin` Extension for Scalar BFloat16 Conversions > BF16 Number Format", + "line_range": [ + 36, + 36 + ] + }, + { + "text": "BF16 values are NaN-boxed when held in `f` registers, as described in .", + "section": "Preamble > `Zfbfmin` Extension for Scalar BFloat16 Conversions > BF16 Number Format", + "line_range": [ + 38, + 38 + ] + }, + { + "text": "Synopsis:: Convert FP32 value to a BF16 value", + "section": "Preamble > `Zfbfmin` Extension for Scalar BFloat16 Conversions > BF16 Number Format > fcvt.bf16.s", + "line_range": [ + 42, + 43 + ] + }, + { + "text": "Mnemonic:: fcvt.bf16.s rd, rs1", + "section": "Preamble > `Zfbfmin` Extension for Scalar BFloat16 Conversions > BF16 Number Format > fcvt.bf16.s", + "line_range": [ + 45, + 46 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ {bits: 7, name: '1010011', attr: ['OP-FP']}, {bits: 5, name: 'rd'}, {bits: 3, name: 'rm'}, {bits: 5, name: 'rs1'}, {bits: 5, name: '01000', attr: ['bf16.s']}, {bits: 2, name: '10', attr: ['h']}, {bits: 5, name: '01000', attr: 'fcvt'}, ]} ....", + "section": "Preamble > `Zfbfmin` Extension for Scalar BFloat16 Conversions > BF16 Number Format > fcvt.bf16.s", + "line_range": [ + 48, + 60 + ] + }, + { + "text": "Description:: Narrowing convert FP32 value to a BF16 value.", + "section": "Preamble > `Zfbfmin` Extension for Scalar BFloat16 Conversions > BF16 Number Format > fcvt.bf16.s", + "line_range": [ + 62, + 64 + ] + }, + { + "text": "Round according to the RM field.", + "section": "Preamble > `Zfbfmin` Extension for Scalar BFloat16 Conversions > BF16 Number Format > fcvt.bf16.s", + "line_range": [ + 62, + 64 + ] + }, + { + "text": "This instruction is similar to other narrowing floating-point-to-floating-point conversion instructions.", + "section": "Preamble > `Zfbfmin` Extension for Scalar BFloat16 Conversions > BF16 Number Format > fcvt.bf16.s", + "line_range": [ + 66, + 67 + ] + }, + { + "text": "Exceptions: Overflow, Underflow, Inexact, Invalid", + "section": "Preamble > `Zfbfmin` Extension for Scalar BFloat16 Conversions > BF16 Number Format > fcvt.bf16.s", + "line_range": [ + 69, + 69 + ] + }, + { + "text": "Synopsis:: Convert BF16 value to an FP32 value", + "section": "Preamble > `Zfbfmin` Extension for Scalar BFloat16 Conversions > BF16 Number Format > fcvt.s.bf16", + "line_range": [ + 75, + 76 + ] + }, + { + "text": "Mnemonic:: fcvt.s.bf16 rd, rs1", + "section": "Preamble > `Zfbfmin` Extension for Scalar BFloat16 Conversions > BF16 Number Format > fcvt.s.bf16", + "line_range": [ + 78, + 79 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ {bits: 7, name: '1010011', attr: ['OP-FP']}, {bits: 5, name: 'rd'}, {bits: 3, name: 'rm'}, {bits: 5, name: 'rs1'}, {bits: 5, name: '00110', attr: ['bf16']}, {bits: 2, name: '00', attr: ['s']}, {bits: 5, name: '01000', attr: 'fcvt'}, ]} ....", + "section": "Preamble > `Zfbfmin` Extension for Scalar BFloat16 Conversions > BF16 Number Format > fcvt.s.bf16", + "line_range": [ + 81, + 93 + ] + }, + { + "text": "Description:: Converts a BF16 value to an FP32 value.", + "section": "Preamble > `Zfbfmin` Extension for Scalar BFloat16 Conversions > BF16 Number Format > fcvt.s.bf16", + "line_range": [ + 95, + 97 + ] + }, + { + "text": "This instruction is similar to other widening floating-point-to-floating-point conversion instructions.", + "section": "Preamble > `Zfbfmin` Extension for Scalar BFloat16 Conversions > BF16 Number Format > fcvt.s.bf16", + "line_range": [ + 99, + 100 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zfh.json b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zfh.json new file mode 100644 index 0000000000..455a6e55f6 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zfh.json @@ -0,0 +1,174 @@ +{ + "source_file": "src/unpriv/zfh.adoc", + "total": 21, + "sentences": [ + { + "text": "This chapter describes the Zfh standard extension for half-precision floating-point, which adds computational instructions compliant with the IEEE 754-2008 arithmetic standard's binary16 format and operations.", + "section": "Preamble > `Zfh` Extension for Half-Precision Floating-Point", + "line_range": [ + 3, + 9 + ] + }, + { + "text": "The Zfh extension depends on the F extension.", + "section": "Preamble > `Zfh` Extension for Half-Precision Floating-Point", + "line_range": [ + 3, + 9 + ] + }, + { + "text": "The NaN-boxing scheme described in is extended to allow a half-precision value to be NaN-boxed inside a single-precision value (which may be recursively NaN-boxed inside a double- or quad-precision value when the D or Q extension is present).", + "section": "Preamble > `Zfh` Extension for Half-Precision Floating-Point", + "line_range": [ + 3, + 9 + ] + }, + { + "text": "New 16-bit variants of LOAD-FP and STORE-FP instructions are added, encoded with a new value for the funct3 width field.", + "section": "Preamble > `Zfh` Extension for Half-Precision Floating-Point > Half-Precision Load and Store Instructions", + "line_range": [ + 13, + 15 + ] + }, + { + "text": "FLH and FSH are only guaranteed to execute atomically if the effective address is naturally aligned.", + "section": "Preamble > `Zfh` Extension for Half-Precision Floating-Point > Half-Precision Load and Store Instructions", + "line_range": [ + 21, + 23 + ] + }, + { + "text": "FLH and FSH do not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved. FLH NaN-boxes the result written to rd, whereas FSH ignores all but the lower 16 bits in rs2.", + "section": "Preamble > `Zfh` Extension for Half-Precision Floating-Point > Half-Precision Load and Store Instructions", + "line_range": [ + 25, + 28 + ] + }, + { + "text": "A new supported format is added to the format field of most instructions, as shown in .", + "section": "Preamble > `Zfh` Extension for Half-Precision Floating-Point > Half-Precision Load and Store Instructions > Half-Precision Computational Instructions", + "line_range": [ + 32, + 33 + ] + }, + { + "text": ".Format field encoding. | |fmt field |Mnemonic |Meaning |00 |S |32-bit single-precision |01 |D |64-bit double-precision |10 |H |16-bit half-precision |11 |Q |128-bit quad-precision |", + "section": "Preamble > `Zfh` Extension for Half-Precision Floating-Point > Half-Precision Load and Store Instructions > Half-Precision Computational Instructions", + "line_range": [ + 35, + 44 + ] + }, + { + "text": "The half-precision floating-point computational instructions are defined analogously to their single-precision counterparts, but operate on half-precision operands and produce half-precision results.", + "section": "Preamble > `Zfh` Extension for Half-Precision Floating-Point > Half-Precision Load and Store Instructions > Half-Precision Computational Instructions", + "line_range": [ + 46, + 49 + ] + }, + { + "text": "New floating-point-to-integer and integer-to-floating-point conversion instructions are added.", + "section": "Preamble > `Zfh` Extension for Half-Precision Floating-Point > Half-Precision Load and Store Instructions > Half-Precision Conversion and Move Instructions", + "line_range": [ + 57, + 66 + ] + }, + { + "text": "These instructions are defined analogously to the single-precision-to-integer and integer-to-single-precision conversion instructions. FCVT.W.H or FCVT.L.H converts a half-precision floating-point number to a signed 32-bit or 64-bit integer, respectively. FCVT.H.W or FCVT.H.L converts a 32-bit or 64-bit signed integer, respectively, into a half-precision floating-point number. FCVT.WU.H, FCVT.LU.H, FCVT.H.WU, and FCVT.H.LU variants convert to or from unsigned integer values. FCVT.L[U].H and FCVT.H.L[U] are RV64-only instructions.", + "section": "Preamble > `Zfh` Extension for Half-Precision Floating-Point > Half-Precision Load and Store Instructions > Half-Precision Conversion and Move Instructions", + "line_range": [ + 57, + 66 + ] + }, + { + "text": "New floating-point-to-floating-point conversion instructions are added.", + "section": "Preamble > `Zfh` Extension for Half-Precision Floating-Point > Half-Precision Load and Store Instructions > Half-Precision Conversion and Move Instructions", + "line_range": [ + 71, + 81 + ] + }, + { + "text": "These instructions are defined analogously to the double-precision floating-point-to-floating-point conversion instructions. FCVT.S.H or FCVT.H.S converts a half-precision floating-point number to a single-precision floating-point number, or vice-versa, respectively.", + "section": "Preamble > `Zfh` Extension for Half-Precision Floating-Point > Half-Precision Load and Store Instructions > Half-Precision Conversion and Move Instructions", + "line_range": [ + 71, + 81 + ] + }, + { + "text": "If the D extension is present, FCVT.D.H or FCVT.H.D converts a half-precision floating-point number to a double-precision floating-point number, or vice-versa, respectively.", + "section": "Preamble > `Zfh` Extension for Half-Precision Floating-Point > Half-Precision Load and Store Instructions > Half-Precision Conversion and Move Instructions", + "line_range": [ + 71, + 81 + ] + }, + { + "text": "If the Q extension is present, FCVT.Q.H or FCVT.H.Q converts a half-precision floating-point number to a quad-precision floating-point number, or vice-versa, respectively.", + "section": "Preamble > `Zfh` Extension for Half-Precision Floating-Point > Half-Precision Load and Store Instructions > Half-Precision Conversion and Move Instructions", + "line_range": [ + 71, + 81 + ] + }, + { + "text": "Floating-point to floating-point sign-injection instructions, FSGNJ.H, FSGNJN.H, and FSGNJX.H are defined analogously to the single-precision sign-injection instruction.", + "section": "Preamble > `Zfh` Extension for Half-Precision Floating-Point > Half-Precision Load and Store Instructions > Half-Precision Conversion and Move Instructions", + "line_range": [ + 86, + 89 + ] + }, + { + "text": "Instructions are provided to move bit patterns between the floating-point and integer registers. FMV.X.H moves the half-precision value in floating-point register rs1 to a representation in the IEEE 754-2008 encoding in integer register rd, filling the upper XLEN-16 bits with copies of the floating-point number's sign bit.", + "section": "Preamble > `Zfh` Extension for Half-Precision Floating-Point > Half-Precision Load and Store Instructions > Half-Precision Conversion and Move Instructions", + "line_range": [ + 94, + 99 + ] + }, + { + "text": "FMV.H.X moves the half-precision value encoded in the IEEE 754-2008 encoding from the lower 16 bits of integer register rs1 to the floating-point register rd, NaN-boxing the result.", + "section": "Preamble > `Zfh` Extension for Half-Precision Floating-Point > Half-Precision Load and Store Instructions > Half-Precision Conversion and Move Instructions", + "line_range": [ + 101, + 104 + ] + }, + { + "text": "FMV.X.H and FMV.H.X do not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved.", + "section": "Preamble > `Zfh` Extension for Half-Precision Floating-Point > Half-Precision Load and Store Instructions > Half-Precision Conversion and Move Instructions", + "line_range": [ + 106, + 108 + ] + }, + { + "text": "The half-precision floating-point compare instructions are defined analogously to their single-precision counterparts, but operate on half-precision operands.", + "section": "Preamble > `Zfh` Extension for Half-Precision Floating-Point > Half-Precision Load and Store Instructions > Half-Precision Floating-Point Compare Instructions", + "line_range": [ + 115, + 118 + ] + }, + { + "text": "The half-precision floating-point classify instruction, FCLASS.H, is defined analogously to its single-precision counterpart, but operates on half-precision operands.", + "section": "Preamble > `Zfh` Extension for Half-Precision Floating-Point > Half-Precision Load and Store Instructions > Half-Precision Floating-Point Classify Instruction", + "line_range": [ + 125, + 128 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zfhmin.json b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zfhmin.json new file mode 100644 index 0000000000..02060343e4 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zfhmin.json @@ -0,0 +1,62 @@ +{ + "source_file": "src/unpriv/zfhmin.adoc", + "total": 7, + "sentences": [ + { + "text": "This section describes the Zfhmin standard extension, which provides minimal support for 16-bit half-precision binary floating-point instructions.", + "section": "Preamble > ext:zfhmin[] Extension for Minimal Half-Precision Floating-Point", + "line_range": [ + 3, + 10 + ] + }, + { + "text": "The Zfhmin extension is a subset of the Zfh extension, consisting only of data transfer and conversion instructions.", + "section": "Preamble > ext:zfhmin[] Extension for Minimal Half-Precision Floating-Point", + "line_range": [ + 3, + 10 + ] + }, + { + "text": "Like Zfh, the Zfhmin extension depends on the single-precision floating-point extension, F.", + "section": "Preamble > ext:zfhmin[] Extension for Minimal Half-Precision Floating-Point", + "line_range": [ + 3, + 10 + ] + }, + { + "text": "The expectation is that Zfhmin software primarily uses the half-precision format for storage, performing most computation in higher precision.", + "section": "Preamble > ext:zfhmin[] Extension for Minimal Half-Precision Floating-Point", + "line_range": [ + 3, + 10 + ] + }, + { + "text": "The Zfhmin extension includes the following instructions from the Zfh extension: FLH, FSH, FMV.X.H, FMV.H.X, FCVT.S.H, and FCVT.H.S.", + "section": "Preamble > ext:zfhmin[] Extension for Minimal Half-Precision Floating-Point", + "line_range": [ + 12, + 17 + ] + }, + { + "text": "If the D extension is present, the FCVT.D.H and FCVT.H.D instructions are also included.", + "section": "Preamble > ext:zfhmin[] Extension for Minimal Half-Precision Floating-Point", + "line_range": [ + 12, + 17 + ] + }, + { + "text": "If the Q extension is present, the FCVT.Q.H and FCVT.H.Q instructions are additionally included.", + "section": "Preamble > ext:zfhmin[] Extension for Minimal Half-Precision Floating-Point", + "line_range": [ + 12, + 17 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zfinx.json b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zfinx.json new file mode 100644 index 0000000000..d82b5dee8f --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zfinx.json @@ -0,0 +1,222 @@ +{ + "source_file": "src/unpriv/zfinx.adoc", + "total": 27, + "sentences": [ + { + "text": "This chapter defines the \"Zfinx\" extension (pronounced \"z-f-in-x\") that provides instructions similar to those in the standard floating-point F extension for single-precision floating-point instructions but which operate on the `x` registers instead of the `f` registers.", + "section": "Preamble > \"Zfinx\", \"Zdinx\", \"Zhinx\", \"Zhinxmin\" Extensions for Floating-Point in Integer Registers, Version 1.0", + "line_range": [ + 3, + 9 + ] + }, + { + "text": "This chapter also defines the \"Zdinx\", \"Zhinx\", and \"Zhinxmin\" extensions that provide similar instructions for other floating-point precisions.", + "section": "Preamble > \"Zfinx\", \"Zdinx\", \"Zhinx\", \"Zhinxmin\" Extensions for Floating-Point in Integer Registers, Version 1.0", + "line_range": [ + 3, + 9 + ] + }, + { + "text": "The Zfinx extension adds all of the instructions that the F extension adds, except for the transfer instructions FLW, FSW, FMV.W.X, FMV.X.W, C.FLW[SP], and C.FSW[SP].", + "section": "Preamble > \"Zfinx\", \"Zdinx\", \"Zhinx\", \"Zhinxmin\" Extensions for Floating-Point in Integer Registers, Version 1.0", + "line_range": [ + 11, + 14 + ] + }, + { + "text": "The Zfinx variants of these F-extension instructions have the same semantics, except that whenever such an instruction would have accessed an `f` register, it instead accesses the `x` register with the same number.", + "section": "Preamble > \"Zfinx\", \"Zdinx\", \"Zhinx\", \"Zhinxmin\" Extensions for Floating-Point in Integer Registers, Version 1.0", + "line_range": [ + 16, + 20 + ] + }, + { + "text": "The Zfinx extension depends on the \"Zicsr\" extension for control and status register access.", + "section": "Preamble > \"Zfinx\", \"Zdinx\", \"Zhinx\", \"Zhinxmin\" Extensions for Floating-Point in Integer Registers, Version 1.0", + "line_range": [ + 22, + 22 + ] + }, + { + "text": "Floating-point operands of width w < XLEN bits occupy bits w-1:0 of an `x` register.", + "section": "Preamble > \"Zfinx\", \"Zdinx\", \"Zhinx\", \"Zhinxmin\" Extensions for Floating-Point in Integer Registers, Version 1.0 > Processing of Narrower Values", + "line_range": [ + 26, + 29 + ] + }, + { + "text": "Floating-point operations on w-bit operands ignore operand bits XLEN-1: w.", + "section": "Preamble > \"Zfinx\", \"Zdinx\", \"Zhinx\", \"Zhinxmin\" Extensions for Floating-Point in Integer Registers, Version 1.0 > Processing of Narrower Values", + "line_range": [ + 26, + 29 + ] + }, + { + "text": "Floating-point operations that produce w < XLEN-bit results fill bits XLEN-1: w with copies of bit w-1 (the sign bit).", + "section": "Preamble > \"Zfinx\", \"Zdinx\", \"Zhinx\", \"Zhinxmin\" Extensions for Floating-Point in Integer Registers, Version 1.0 > Processing of Narrower Values", + "line_range": [ + 31, + 33 + ] + }, + { + "text": "The Zdinx extension provides analogous double-precision floating-point instructions.", + "section": "Preamble > \"Zfinx\", \"Zdinx\", \"Zhinx\", \"Zhinxmin\" Extensions for Floating-Point in Integer Registers, Version 1.0 > Processing of Narrower Values > Zdinx", + "line_range": [ + 37, + 38 + ] + }, + { + "text": "The Zdinx extension depends upon the Zfinx extension.", + "section": "Preamble > \"Zfinx\", \"Zdinx\", \"Zhinx\", \"Zhinxmin\" Extensions for Floating-Point in Integer Registers, Version 1.0 > Processing of Narrower Values > Zdinx", + "line_range": [ + 37, + 38 + ] + }, + { + "text": "The Zdinx extension adds all of the instructions that the D extension adds, except for the transfer instructions FLD, FSD, FMV.D.X, FMV.X.D, C.FLD[SP], and C.FSD[SP].", + "section": "Preamble > \"Zfinx\", \"Zdinx\", \"Zhinx\", \"Zhinxmin\" Extensions for Floating-Point in Integer Registers, Version 1.0 > Processing of Narrower Values > Zdinx", + "line_range": [ + 40, + 43 + ] + }, + { + "text": "The Zdinx variants of these D-extension instructions have the same semantics, except that whenever such an instruction would have accessed an `f` register, it instead accesses the `x` register with the same number.", + "section": "Preamble > \"Zfinx\", \"Zdinx\", \"Zhinx\", \"Zhinxmin\" Extensions for Floating-Point in Integer Registers, Version 1.0 > Processing of Narrower Values > Zdinx", + "line_range": [ + 45, + 49 + ] + }, + { + "text": "Double-precision operands in RV32Zdinx are held in aligned `x`-register pairs, i.e., register numbers must be even.", + "section": "Preamble > \"Zfinx\", \"Zdinx\", \"Zhinx\", \"Zhinxmin\" Extensions for Floating-Point in Integer Registers, Version 1.0 > Processing of Narrower Values > Processing of Wider Values", + "line_range": [ + 53, + 57 + ] + }, + { + "text": "Use of misaligned (odd-numbered) registers for double-width floating-point operands is reserved.", + "section": "Preamble > \"Zfinx\", \"Zdinx\", \"Zhinx\", \"Zhinxmin\" Extensions for Floating-Point in Integer Registers, Version 1.0 > Processing of Narrower Values > Processing of Wider Values", + "line_range": [ + 53, + 57 + ] + }, + { + "text": "Regardless of endianness, the lower-numbered register holds the low-order bits, and the higher-numbered register holds the high-order bits: e.g., bits 31:0 of a double-precision operand in RV32Zdinx might be held in register `x14`, with bits 63:32 of that operand held in `x15`.", + "section": "Preamble > \"Zfinx\", \"Zdinx\", \"Zhinx\", \"Zhinxmin\" Extensions for Floating-Point in Integer Registers, Version 1.0 > Processing of Narrower Values > Processing of Wider Values", + "line_range": [ + 59, + 64 + ] + }, + { + "text": "When a double-width floating-point result is written to `x0`, the entire write takes no effect: e.g., for RV32Zdinx, writing a double-precision result to `x0` does not cause `x1` to be written.", + "section": "Preamble > \"Zfinx\", \"Zdinx\", \"Zhinx\", \"Zhinxmin\" Extensions for Floating-Point in Integer Registers, Version 1.0 > Processing of Narrower Values > Processing of Wider Values", + "line_range": [ + 66, + 69 + ] + }, + { + "text": "When `x0` is used as a double-width floating-point operand, the entire operand is zero—i.e., `x1` is not accessed.", + "section": "Preamble > \"Zfinx\", \"Zdinx\", \"Zhinx\", \"Zhinxmin\" Extensions for Floating-Point in Integer Registers, Version 1.0 > Processing of Narrower Values > Processing of Wider Values", + "line_range": [ + 71, + 73 + ] + }, + { + "text": "The Zhinx extension provides analogous half-precision floating-point instructions.", + "section": "Preamble > \"Zfinx\", \"Zdinx\", \"Zhinx\", \"Zhinxmin\" Extensions for Floating-Point in Integer Registers, Version 1.0 > Processing of Narrower Values > Zhinx", + "line_range": [ + 77, + 78 + ] + }, + { + "text": "The Zhinx extension depends upon the Zfinx extension.", + "section": "Preamble > \"Zfinx\", \"Zdinx\", \"Zhinx\", \"Zhinxmin\" Extensions for Floating-Point in Integer Registers, Version 1.0 > Processing of Narrower Values > Zhinx", + "line_range": [ + 77, + 78 + ] + }, + { + "text": "The Zhinx extension adds all of the instructions that the Zfh extension adds, except for the transfer instructions FLH, FSH, FMV.H.X, and FMV.X.H.", + "section": "Preamble > \"Zfinx\", \"Zdinx\", \"Zhinx\", \"Zhinxmin\" Extensions for Floating-Point in Integer Registers, Version 1.0 > Processing of Narrower Values > Zhinx", + "line_range": [ + 80, + 83 + ] + }, + { + "text": "The Zhinx variants of these Zfh-extension instructions have the same semantics, except that whenever such an instruction would have accessed an `f` register, it instead accesses the `x` register with the same number.", + "section": "Preamble > \"Zfinx\", \"Zdinx\", \"Zhinx\", \"Zhinxmin\" Extensions for Floating-Point in Integer Registers, Version 1.0 > Processing of Narrower Values > Zhinx", + "line_range": [ + 85, + 89 + ] + }, + { + "text": "The Zhinxmin extension provides minimal support for 16-bit half-precision floating-point instructions that operate on the `x` registers.", + "section": "Preamble > \"Zfinx\", \"Zdinx\", \"Zhinx\", \"Zhinxmin\" Extensions for Floating-Point in Integer Registers, Version 1.0 > Processing of Narrower Values > Zhinxmin", + "line_range": [ + 93, + 95 + ] + }, + { + "text": "The Zhinxmin extension depends upon the Zfinx extension.", + "section": "Preamble > \"Zfinx\", \"Zdinx\", \"Zhinx\", \"Zhinxmin\" Extensions for Floating-Point in Integer Registers, Version 1.0 > Processing of Narrower Values > Zhinxmin", + "line_range": [ + 93, + 95 + ] + }, + { + "text": "The Zhinxmin extension includes the following instructions from the Zhinx extension: FCVT.S.H and FCVT.H.S.", + "section": "Preamble > \"Zfinx\", \"Zdinx\", \"Zhinx\", \"Zhinxmin\" Extensions for Floating-Point in Integer Registers, Version 1.0 > Processing of Narrower Values > Zhinxmin", + "line_range": [ + 97, + 100 + ] + }, + { + "text": "If the Zdinx extension is present, the FCVT.D.H and FCVT.H.D instructions are also included.", + "section": "Preamble > \"Zfinx\", \"Zdinx\", \"Zhinx\", \"Zhinxmin\" Extensions for Floating-Point in Integer Registers, Version 1.0 > Processing of Narrower Values > Zhinxmin", + "line_range": [ + 97, + 100 + ] + }, + { + "text": "As described in , the `mstatus` field FS is hardwired to 0 if the Zfinx extension is implemented, and FS no longer affects the trapping behavior of floating-point instructions or `fcsr` accesses.", + "section": "Preamble > \"Zfinx\", \"Zdinx\", \"Zhinx\", \"Zhinxmin\" Extensions for Floating-Point in Integer Registers, Version 1.0 > Processing of Narrower Values > Privileged Architecture Implications", + "line_range": [ + 103, + 107 + ] + }, + { + "text": "The `misa` bits F, D, and Q are hardwired to 0 when the Zfinx extension is implemented.", + "section": "Preamble > \"Zfinx\", \"Zdinx\", \"Zhinx\", \"Zhinxmin\" Extensions for Floating-Point in Integer Registers, Version 1.0 > Processing of Narrower Values > Privileged Architecture Implications", + "line_range": [ + 109, + 111 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zi.json b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zi.json new file mode 100644 index 0000000000..336f70ee30 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zi.json @@ -0,0 +1,38 @@ +{ + "source_file": "src/unpriv/zi.adoc", + "total": 4, + "sentences": [ + { + "text": "NOTE: This chapter is currently being restructured.", + "section": "Preamble > Scalar Integer Extensions", + "line_range": [ + 3, + 4 + ] + }, + { + "text": "Its contents are normative, but the presentation might appear disjoint.", + "section": "Preamble > Scalar Integer Extensions", + "line_range": [ + 3, + 4 + ] + }, + { + "text": "This chapter describes the scalar integer extensions.", + "section": "Preamble > Scalar Integer Extensions", + "line_range": [ + 6, + 9 + ] + }, + { + "text": "Most of these extensions are accordingly named with the prefix \"Zi\", with the exception of the integer multiplication and division extensions, which are named \"M\" or prefixed with \"Zm\".", + "section": "Preamble > Scalar Integer Extensions", + "line_range": [ + 6, + 9 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zic64b.json b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zic64b.json new file mode 100644 index 0000000000..4596ab7794 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zic64b.json @@ -0,0 +1,14 @@ +{ + "source_file": "src/unpriv/zic64b.adoc", + "total": 1, + "sentences": [ + { + "text": "If the Zic64b extension is implemented, then cache blocks must be 64 bytes in size, naturally aligned in the address space.", + "section": "Preamble > Zic64b Extension for 64-byte Cache Blocks, Version 1.0", + "line_range": [ + 3, + 4 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__unpriv__ziccamoa.json b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__ziccamoa.json new file mode 100644 index 0000000000..f2948b41b1 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__ziccamoa.json @@ -0,0 +1,14 @@ +{ + "source_file": "src/unpriv/ziccamoa.adoc", + "total": 1, + "sentences": [ + { + "text": "If the Ziccamoa extension is implemented, then main memory regions with both the cacheability and coherence PMAs must support all atomics in the Zaamo extension.", + "section": "Preamble > Ziccamoa Extension for Main Memory Atomics, Version 1.0", + "line_range": [ + 3, + 5 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__unpriv__ziccamoc.json b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__ziccamoc.json new file mode 100644 index 0000000000..8601bb2232 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__ziccamoc.json @@ -0,0 +1,14 @@ +{ + "source_file": "src/unpriv/ziccamoc.adoc", + "total": 1, + "sentences": [ + { + "text": "If the Ziccamoc extension is implemented, then main memory regions with both the cacheability and coherence PMAs must provide ``AMOCASQ``-level PMA support.", + "section": "Preamble > Ziccamoc Extension for Main Memory Compare-and-Swap, Version 1.0", + "line_range": [ + 3, + 5 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__unpriv__ziccif.json b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__ziccif.json new file mode 100644 index 0000000000..0c8c1eb203 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__ziccif.json @@ -0,0 +1,94 @@ +{ + "source_file": "src/unpriv/ziccif.adoc", + "total": 11, + "sentences": [ + { + "text": "NOTE: This extension was ratified alongside the RVA20U64 profile.", + "section": "Preamble > Ziccif Extension for Instruction-Fetch Atomicity, Version 1.0", + "line_range": [ + 3, + 5 + ] + }, + { + "text": "This chapter supplies an operational definition for the extension and adds expository material.", + "section": "Preamble > Ziccif Extension for Instruction-Fetch Atomicity, Version 1.0", + "line_range": [ + 3, + 5 + ] + }, + { + "text": "If the Ziccif extension is implemented, main memory regions with both the cacheability and coherence PMAs must support instruction fetch, and any instruction fetches of naturally aligned power-of-2 sizes of at most `min(ILEN,XLEN)` bits are atomic.", + "section": "Preamble > Ziccif Extension for Instruction-Fetch Atomicity, Version 1.0", + "line_range": [ + 7, + 10 + ] + }, + { + "text": "An implementation with the Ziccif extension fetches instructions in a manner equivalent to the following state machine.", + "section": "Preamble > Ziccif Extension for Instruction-Fetch Atomicity, Version 1.0", + "line_range": [ + 12, + 13 + ] + }, + { + "text": "Let `M` be the smallest power of 2 such that `M` {ge} `min(ILEN,XLEN)/8`.", + "section": "Preamble > Ziccif Extension for Instruction-Fetch Atomicity, Version 1.0", + "line_range": [ + 15, + 18 + ] + }, + { + "text": "Let `N` be the `pc` modulo `M`.", + "section": "Preamble > Ziccif Extension for Instruction-Fetch Atomicity, Version 1.0", + "line_range": [ + 15, + 18 + ] + }, + { + "text": "Atomically fetch `M` - `N` bytes from memory at address `pc`.", + "section": "Preamble > Ziccif Extension for Instruction-Fetch Atomicity, Version 1.0", + "line_range": [ + 15, + 18 + ] + }, + { + "text": "Let `T` be the running total of bytes fetched, initially `M` - `N`.", + "section": "Preamble > Ziccif Extension for Instruction-Fetch Atomicity, Version 1.0", + "line_range": [ + 15, + 18 + ] + }, + { + "text": "If the `T` bytes fetched begin with a complete instruction of length `L` {le} `T`, then execute that instruction, discard the remaining `T` - `L` bytes fetched, and go back to step 1, using the updated `pc`.", + "section": "Preamble > Ziccif Extension for Instruction-Fetch Atomicity, Version 1.0", + "line_range": [ + 20, + 24 + ] + }, + { + "text": "Otherwise, atomically fetch `M` bytes from memory at address `pc` + `T`, increment `T` by `M`, and repeat step 2.", + "section": "Preamble > Ziccif Extension for Instruction-Fetch Atomicity, Version 1.0", + "line_range": [ + 20, + 24 + ] + }, + { + "text": "Memory protection and executability PMAs are applied only to bytes that are not discarded by this algorithm.", + "section": "Preamble > Ziccif Extension for Instruction-Fetch Atomicity, Version 1.0", + "line_range": [ + 26, + 27 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zicclsm.json b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zicclsm.json new file mode 100644 index 0000000000..4c14a9aed5 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zicclsm.json @@ -0,0 +1,46 @@ +{ + "source_file": "src/unpriv/zicclsm.adoc", + "total": 5, + "sentences": [ + { + "text": "If the Zicclsm extension is implemented, then misaligned loads and stores to main memory regions with both the cacheability and coherence PMAs must be supported.", + "section": "Preamble > Zicclsm Extension for Main Memory Misaligned Accesses, Version 1.0", + "line_range": [ + 3, + 5 + ] + }, + { + "text": "NOTE: This definition includes vector memory accesses.", + "section": "Preamble > Zicclsm Extension for Main Memory Misaligned Accesses, Version 1.0", + "line_range": [ + 7, + 8 + ] + }, + { + "text": "It does not include any instructions in the various ext:Za*[] extensions.", + "section": "Preamble > Zicclsm Extension for Main Memory Misaligned Accesses, Version 1.0", + "line_range": [ + 7, + 8 + ] + }, + { + "text": "NOTE: Even though mandated, misaligned loads and stores might execute extremely slowly.", + "section": "Preamble > Zicclsm Extension for Main Memory Misaligned Accesses, Version 1.0", + "line_range": [ + 10, + 13 + ] + }, + { + "text": "Standard software distributions should assume their existence only for correctness, not for performance.", + "section": "Preamble > Zicclsm Extension for Main Memory Misaligned Accesses, Version 1.0", + "line_range": [ + 10, + 13 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__unpriv__ziccrse.json b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__ziccrse.json new file mode 100644 index 0000000000..7bb45c1938 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__ziccrse.json @@ -0,0 +1,14 @@ +{ + "source_file": "src/unpriv/ziccrse.adoc", + "total": 1, + "sentences": [ + { + "text": "If the Ziccrse extension is implemented, then main memory regions with both the cacheability and coherence PMAs must support the RsrvEventual PMA.", + "section": "Preamble > Ziccrse Extension for Main Memory Reservability, Version 1.0", + "line_range": [ + 3, + 4 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zicntr.json b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zicntr.json new file mode 100644 index 0000000000..dab52a508b --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zicntr.json @@ -0,0 +1,182 @@ +{ + "source_file": "src/unpriv/zicntr.adoc", + "total": 22, + "sentences": [ + { + "text": "RISC-V ISAs provide a set of up to thirty-two 64-bit performance counters and timers that are accessible via unprivileged XLEN-bit read-only CSR registers `0xC00`–`0xC1F` (when XLEN=32, the upper 32 bits are accessed via CSR registers `0xC80`–`0xC9F`).", + "section": "Preamble > \"Zicntr\" Extension for Base Counters and Timers", + "line_range": [ + 3, + 7 + ] + }, + { + "text": "These counters are divided between the Zicntr and extensions.", + "section": "Preamble > \"Zicntr\" Extension for Base Counters and Timers", + "line_range": [ + 3, + 7 + ] + }, + { + "text": "The Zicntr standard extension comprises the first three of these counters (CYCLE, TIME, and INSTRET), which have dedicated functions (cycle count, real-time clock, and instructions retired, respectively).", + "section": "Preamble > \"Zicntr\" Extension for Base Counters and Timers", + "line_range": [ + 9, + 12 + ] + }, + { + "text": "The Zicntr extension depends on the Zicsr extension.", + "section": "Preamble > \"Zicntr\" Extension for Base Counters and Timers", + "line_range": [ + 9, + 12 + ] + }, + { + "text": "For base ISAs with XLEN{ge}64, CSR instructions can access the full 64-bit CSRs directly.", + "section": "Preamble > \"Zicntr\" Extension for Base Counters and Timers", + "line_range": [ + 16, + 19 + ] + }, + { + "text": "In particular, the RDCYCLE, RDTIME, and RDINSTRET pseudoinstructions read the full 64 bits of the `cycle`, `time`, and `instret` counters.", + "section": "Preamble > \"Zicntr\" Extension for Base Counters and Timers", + "line_range": [ + 16, + 19 + ] + }, + { + "text": "For base ISAs with XLEN=32, the Zicntr extension enables the three 64-bit read-only counters to be accessed in 32-bit pieces.", + "section": "Preamble > \"Zicntr\" Extension for Base Counters and Timers", + "line_range": [ + 21, + 57 + ] + }, + { + "text": "The RDCYCLE, RDTIME, and RDINSTRET pseudoinstructions provide the lower 32 bits, and the RDCYCLEH, RDTIMEH, and RDINSTRETH pseudoinstructions provide the upper 32 bits of the respective counters.", + "section": "Preamble > \"Zicntr\" Extension for Base Counters and Timers", + "line_range": [ + 21, + 57 + ] + }, + { + "text": "The RDCYCLE pseudoinstruction reads the low XLEN bits of the `cycle` CSR which holds a count of the number of clock cycles executed by the processor core on which the hart is running from an arbitrary start time in the past. RDCYCLEH is only present when XLEN=32 and reads bits 63-32 of the same cycle counter.", + "section": "Preamble > \"Zicntr\" Extension for Base Counters and Timers", + "line_range": [ + 21, + 57 + ] + }, + { + "text": "The underlying 64-bit counter should never overflow in practice.", + "section": "Preamble > \"Zicntr\" Extension for Base Counters and Timers", + "line_range": [ + 21, + 57 + ] + }, + { + "text": "The rate at which the cycle counter advances will depend on the implementation and operating environment.", + "section": "Preamble > \"Zicntr\" Extension for Base Counters and Timers", + "line_range": [ + 21, + 57 + ] + }, + { + "text": "The execution environment should provide a means to determine the current rate (cycles/second) at which the cycle counter is incrementing.", + "section": "Preamble > \"Zicntr\" Extension for Base Counters and Timers", + "line_range": [ + 21, + 57 + ] + }, + { + "text": "The RDTIME pseudoinstruction reads the low XLEN bits of the \"time\" CSR, which counts wall-clock real time that has passed from an arbitrary start time in the past. RDTIMEH is only present when XLEN=32 and reads bits 63-32 of the same real-time counter.", + "section": "Preamble > \"Zicntr\" Extension for Base Counters and Timers", + "line_range": [ + 21, + 57 + ] + }, + { + "text": "The underlying 64-bit counter increments by one with each tick of the real-time clock, and, for realistic real-time clock frequencies, should never overflow in practice.", + "section": "Preamble > \"Zicntr\" Extension for Base Counters and Timers", + "line_range": [ + 21, + 57 + ] + }, + { + "text": "The execution environment should provide a means of determining the period of a counter tick (seconds/tick).", + "section": "Preamble > \"Zicntr\" Extension for Base Counters and Timers", + "line_range": [ + 21, + 57 + ] + }, + { + "text": "The period should be constant within a small error bound.", + "section": "Preamble > \"Zicntr\" Extension for Base Counters and Timers", + "line_range": [ + 21, + 57 + ] + }, + { + "text": "The environment should provide a means to determine the accuracy of the clock (i.e., the maximum relative error between the nominal and actual real-time clock periods).", + "section": "Preamble > \"Zicntr\" Extension for Base Counters and Timers", + "line_range": [ + 21, + 57 + ] + }, + { + "text": "The real-time clocks of all harts must be synchronized to within one tick of the real-time clock.", + "section": "Preamble > \"Zicntr\" Extension for Base Counters and Timers", + "line_range": [ + 21, + 57 + ] + }, + { + "text": "The RDINSTRET pseudoinstruction reads the low XLEN bits of the `instret` CSR, which counts the number of instructions retired by this hart from some arbitrary start point in the past. RDINSTRETH is only present when XLEN=32 and reads bits 63-32 of the same instruction counter.", + "section": "Preamble > \"Zicntr\" Extension for Base Counters and Timers", + "line_range": [ + 21, + 57 + ] + }, + { + "text": "The underlying 64-bit counter should never overflow in practice.", + "section": "Preamble > \"Zicntr\" Extension for Base Counters and Timers", + "line_range": [ + 21, + 57 + ] + }, + { + "text": "The following code sequence will read a valid 64-bit cycle counter value into `x3:x2`, even if the counter overflows its lower half between reading its upper and lower halves.", + "section": "Preamble > \"Zicntr\" Extension for Base Counters and Timers", + "line_range": [ + 21, + 57 + ] + }, + { + "text": "[source,asm.] .Sample code for reading the 64-bit cycle counter when XLEN=32. again: rdcycleh x3 rdcycle x2 rdcycleh x4 bne x3, x4, again", + "section": "Preamble > \"Zicntr\" Extension for Base Counters and Timers", + "line_range": [ + 59, + 65 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zicond.json b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zicond.json new file mode 100644 index 0000000000..7d6c40e4f2 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zicond.json @@ -0,0 +1,294 @@ +{ + "source_file": "src/unpriv/zicond.adoc", + "total": 36, + "sentences": [ + { + "text": "The Zicond extension defines two R-type instructions that support branchless conditional operations.", + "section": "Preamble > \"Zicond\" Extension for Integer Conditional Operations, Version 1.0.0", + "line_range": [ + 3, + 4 + ] + }, + { + "text": "| |RV32 |RV64 |Mnemonic |Instruction", + "section": "Preamble > \"Zicond\" Extension for Integer Conditional Operations, Version 1.0.0", + "line_range": [ + 6, + 11 + ] + }, + { + "text": "|{check} |{check} |czero.eqz rd, rs1, rs2 |", + "section": "Preamble > \"Zicond\" Extension for Integer Conditional Operations, Version 1.0.0", + "line_range": [ + 13, + 16 + ] + }, + { + "text": "|{check} |{check} |czero.nez rd, rs1, rs2 |", + "section": "Preamble > \"Zicond\" Extension for Integer Conditional Operations, Version 1.0.0", + "line_range": [ + 18, + 21 + ] + }, + { + "text": "[insns-czero-eqz,reftext=\"Conditional zero, if condition is equal to zero\"]", + "section": "Preamble > \"Zicond\" Extension for Integer Conditional Operations, Version 1.0.0 > Instructions (in alphabetical order)", + "line_range": [ + 27, + 27 + ] + }, + { + "text": "Synopsis:: Moves zero to a register rd, if the condition rs2 is equal to zero, otherwise moves rs1 to rd.", + "section": "Preamble > \"Zicond\" Extension for Integer Conditional Operations, Version 1.0.0 > Instructions (in alphabetical order) > czero.eqz", + "line_range": [ + 30, + 31 + ] + }, + { + "text": "Mnemonic:: czero.eqz rd, rs1, rs2", + "section": "Preamble > \"Zicond\" Extension for Integer Conditional Operations, Version 1.0.0 > Instructions (in alphabetical order) > czero.eqz", + "line_range": [ + 33, + 34 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0x33, attr: ['OP'] }, { bits: 5, name: 'rd' }, { bits: 3, name: 0x5, attr: ['CZERO.EQZ']}, { bits: 5, name: 'rs1', attr: ['value'] }, { bits: 5, name: 'rs2', attr: ['condition'] }, { bits: 7, name: 0x7, attr: ['CZERO'] }, ]} ....", + "section": "Preamble > \"Zicond\" Extension for Integer Conditional Operations, Version 1.0.0 > Instructions (in alphabetical order) > czero.eqz", + "line_range": [ + 36, + 47 + ] + }, + { + "text": "If rs2 contains the value zero, this instruction writes the value zero to rd.", + "section": "Preamble > \"Zicond\" Extension for Integer Conditional Operations, Version 1.0.0 > Instructions (in alphabetical order) > czero.eqz", + "line_range": [ + 49, + 51 + ] + }, + { + "text": "Otherwise, this instruction copies the contents of rs1 to rd.", + "section": "Preamble > \"Zicond\" Extension for Integer Conditional Operations, Version 1.0.0 > Instructions (in alphabetical order) > czero.eqz", + "line_range": [ + 49, + 51 + ] + }, + { + "text": "This instruction carries a syntactic dependency from both rs1 and rs2 to rd.", + "section": "Preamble > \"Zicond\" Extension for Integer Conditional Operations, Version 1.0.0 > Instructions (in alphabetical order) > czero.eqz", + "line_range": [ + 53, + 55 + ] + }, + { + "text": "Furthermore, if the Zkt extension is implemented, this instruction's timing is independent of the data values in rs1 and rs2.", + "section": "Preamble > \"Zicond\" Extension for Integer Conditional Operations, Version 1.0.0 > Instructions (in alphabetical order) > czero.eqz", + "line_range": [ + 53, + 55 + ] + }, + { + "text": "SAIL code:: [source,sail] -- let condition = X(rs2); result : xlenbits = if (condition zeros()) then zeros() else X(rs1); X(rd) = result; --", + "section": "Preamble > \"Zicond\" Extension for Integer Conditional Operations, Version 1.0.0 > Instructions (in alphabetical order) > czero.eqz", + "line_range": [ + 57, + 64 + ] + }, + { + "text": "[insns-czero-nez,reftext=\"Conditional zero, if condition is nonzero\"]", + "section": "Preamble > \"Zicond\" Extension for Integer Conditional Operations, Version 1.0.0 > Instructions (in alphabetical order) > czero.eqz", + "line_range": [ + 68, + 68 + ] + }, + { + "text": "Synopsis:: Moves zero to a register rd, if the condition rs2 is nonzero, otherwise moves rs1 to rd.", + "section": "Preamble > \"Zicond\" Extension for Integer Conditional Operations, Version 1.0.0 > Instructions (in alphabetical order) > czero.eqz > czero.nez", + "line_range": [ + 71, + 72 + ] + }, + { + "text": "Mnemonic:: czero.nez rd, rs1, rs2", + "section": "Preamble > \"Zicond\" Extension for Integer Conditional Operations, Version 1.0.0 > Instructions (in alphabetical order) > czero.eqz > czero.nez", + "line_range": [ + 74, + 75 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ { bits: 7, name: 0x33, attr: ['OP'] }, { bits: 5, name: 'rd' }, { bits: 3, name: 0x7, attr: ['CZERO.NEZ']}, { bits: 5, name: 'rs1', attr: ['value'] }, { bits: 5, name: 'rs2', attr: ['condition'] }, { bits: 7, name: 0x7, attr: ['CZERO'] }, ]} ....", + "section": "Preamble > \"Zicond\" Extension for Integer Conditional Operations, Version 1.0.0 > Instructions (in alphabetical order) > czero.eqz > czero.nez", + "line_range": [ + 77, + 88 + ] + }, + { + "text": "If rs2 contains a nonzero value, this instruction writes the value zero to rd.", + "section": "Preamble > \"Zicond\" Extension for Integer Conditional Operations, Version 1.0.0 > Instructions (in alphabetical order) > czero.eqz > czero.nez", + "line_range": [ + 90, + 92 + ] + }, + { + "text": "Otherwise, this instruction copies the contents of rs1 to rd.", + "section": "Preamble > \"Zicond\" Extension for Integer Conditional Operations, Version 1.0.0 > Instructions (in alphabetical order) > czero.eqz > czero.nez", + "line_range": [ + 90, + 92 + ] + }, + { + "text": "This instruction carries a syntactic dependency from both rs1 and rs2 to rd.", + "section": "Preamble > \"Zicond\" Extension for Integer Conditional Operations, Version 1.0.0 > Instructions (in alphabetical order) > czero.eqz > czero.nez", + "line_range": [ + 94, + 96 + ] + }, + { + "text": "Furthermore, if the Zkt extension is implemented, this instruction's timing is independent of the data values in rs1 and rs2.", + "section": "Preamble > \"Zicond\" Extension for Integer Conditional Operations, Version 1.0.0 > Instructions (in alphabetical order) > czero.eqz > czero.nez", + "line_range": [ + 94, + 96 + ] + }, + { + "text": "SAIL code:: [source,sail] -- let condition = X(rs2); result : xlenbits = if (condition != zeros()) then zeros() else X(rs1); X(rd) = result; --", + "section": "Preamble > \"Zicond\" Extension for Integer Conditional Operations, Version 1.0.0 > Instructions (in alphabetical order) > czero.eqz > czero.nez", + "line_range": [ + 98, + 105 + ] + }, + { + "text": "The instructions from this extension can be used to construct sequences that perform conditional-arithmetic, conditional-bitwise-logical, and conditional-select operations.", + "section": "Preamble > \"Zicond\" Extension for Integer Conditional Operations, Version 1.0.0 > Instructions (in alphabetical order) > Usage examples", + "line_range": [ + 109, + 109 + ] + }, + { + "text": "| |Operation |Instruction sequence |Length", + "section": "Preamble > \"Zicond\" Extension for Integer Conditional Operations, Version 1.0.0 > Instructions (in alphabetical order) > Usage examples > Instruction sequences", + "line_range": [ + 113, + 117 + ] + }, + { + "text": "|*Conditional add, if zero* + `rd = (rc 0) ? (rs1 + rs2) : rs1` |czero.nez rd, rs2, rc add rd, rs1, rd .8+.^|2 insns", + "section": "Preamble > \"Zicond\" Extension for Integer Conditional Operations, Version 1.0.0 > Instructions (in alphabetical order) > Usage examples > Instruction sequences", + "line_range": [ + 119, + 123 + ] + }, + { + "text": "|*Conditional add, if non-zero* + `rd = (rc != 0) ? (rs1 + rs2) : rs1` |czero.eqz rd, rs2, rc add rd, rs1, rd", + "section": "Preamble > \"Zicond\" Extension for Integer Conditional Operations, Version 1.0.0 > Instructions (in alphabetical order) > Usage examples > Instruction sequences", + "line_range": [ + 125, + 128 + ] + }, + { + "text": "|*Conditional subtract, if zero* + `rd = (rc 0) ? (rs1 - rs2) : rs1` |czero.nez rd, rs2, rc sub rd, rs1, rd", + "section": "Preamble > \"Zicond\" Extension for Integer Conditional Operations, Version 1.0.0 > Instructions (in alphabetical order) > Usage examples > Instruction sequences", + "line_range": [ + 130, + 133 + ] + }, + { + "text": "|*Conditional subtract, if non-zero* + `rd = (rc != 0) ? (rs1 - rs2) : rs1` |czero.eqz rd, rs2, rc sub rd, rs1, rd", + "section": "Preamble > \"Zicond\" Extension for Integer Conditional Operations, Version 1.0.0 > Instructions (in alphabetical order) > Usage examples > Instruction sequences", + "line_range": [ + 135, + 138 + ] + }, + { + "text": "|*Conditional bitwise-or, if zero* + `rd = (rc 0) ? (rs1 \\| rs2) : rs1` |czero.nez rd, rs2, rc or rd, rs1, rd", + "section": "Preamble > \"Zicond\" Extension for Integer Conditional Operations, Version 1.0.0 > Instructions (in alphabetical order) > Usage examples > Instruction sequences", + "line_range": [ + 140, + 143 + ] + }, + { + "text": "|*Conditional bitwise-or, if non-zero* + `rd = (rc != 0) ? (rs1 \\| rs2) : rs1` |czero.eqz rd, rs2, rc or rd, rs1, rd", + "section": "Preamble > \"Zicond\" Extension for Integer Conditional Operations, Version 1.0.0 > Instructions (in alphabetical order) > Usage examples > Instruction sequences", + "line_range": [ + 145, + 148 + ] + }, + { + "text": "|*Conditional bitwise-xor, if zero* + `rd = (rc 0) ? (rs1 ^ rs2) : rs1` |czero.nez rd, rs2, rc xor rd, rs1, rd", + "section": "Preamble > \"Zicond\" Extension for Integer Conditional Operations, Version 1.0.0 > Instructions (in alphabetical order) > Usage examples > Instruction sequences", + "line_range": [ + 150, + 153 + ] + }, + { + "text": "|*Conditional bitwise-xor, if non-zero* + `rd = (rc != 0) ? (rs1 ^ rs2) : rs1` |czero.eqz rd, rs2, rc xor rd, rs1, rd", + "section": "Preamble > \"Zicond\" Extension for Integer Conditional Operations, Version 1.0.0 > Instructions (in alphabetical order) > Usage examples > Instruction sequences", + "line_range": [ + 155, + 158 + ] + }, + { + "text": "|*Conditional bitwise-and, if zero* + `rd = (rc 0) ? (rs1 & rs2) : rs1` |and rd, rs1, rs2 czero.eqz rtmp, rs1, rc or rd, rd, rtmp .4+.^|3 insns + (requires 1 temporary)", + "section": "Preamble > \"Zicond\" Extension for Integer Conditional Operations, Version 1.0.0 > Instructions (in alphabetical order) > Usage examples > Instruction sequences", + "line_range": [ + 160, + 166 + ] + }, + { + "text": "|*Conditional bitwise-and, if non-zero* + `rd = (rc != 0) ? (rs1 & rs2) : rs1` |and rd, rs1, rs2 czero.nez rtmp, rs1, rc or rd, rd, rtmp", + "section": "Preamble > \"Zicond\" Extension for Integer Conditional Operations, Version 1.0.0 > Instructions (in alphabetical order) > Usage examples > Instruction sequences", + "line_range": [ + 168, + 172 + ] + }, + { + "text": "|*Conditional select, if zero* + `rd = (rc 0) ? rs1 : rs2` |czero.nez rd, rs1, rc czero.eqz rtmp, rs2, rc add rd, rd, rtmp", + "section": "Preamble > \"Zicond\" Extension for Integer Conditional Operations, Version 1.0.0 > Instructions (in alphabetical order) > Usage examples > Instruction sequences", + "line_range": [ + 174, + 178 + ] + }, + { + "text": "|*Conditional select, if non-zero* + `rd = (rc != 0) ? rs1 : rs2` |czero.eqz rd, rs1, rc czero.nez rtmp, rs2, rc add rd, rd, rtmp", + "section": "Preamble > \"Zicond\" Extension for Integer Conditional Operations, Version 1.0.0 > Instructions (in alphabetical order) > Usage examples > Instruction sequences", + "line_range": [ + 180, + 184 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zicsr.json b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zicsr.json new file mode 100644 index 0000000000..94c2614572 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zicsr.json @@ -0,0 +1,406 @@ +{ + "source_file": "src/unpriv/zicsr.adoc", + "total": 50, + "sentences": [ + { + "text": "RISC-V defines a separate address space of 4096 Control and Status registers associated with each hart.", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0", + "line_range": [ + 3, + 5 + ] + }, + { + "text": "This chapter defines the full set of CSR instructions that operate on these CSRs.", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0", + "line_range": [ + 3, + 5 + ] + }, + { + "text": "All CSR instructions atomically read-modify-write a single CSR, whose CSR specifier is encoded in the 12-bit csr field of the instruction held in bits 31-20.", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions", + "line_range": [ + 9, + 12 + ] + }, + { + "text": "The immediate forms use a 5-bit zero-extended immediate encoded in the rs1 field.", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions", + "line_range": [ + 9, + 12 + ] + }, + { + "text": "The CSRRW (Atomic Read/Write CSR) instruction atomically swaps values in the CSRs and integer registers. CSRRW reads the old value of the CSR, zero-extends the value to XLEN bits, then writes it to integer register rd.", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions", + "line_range": [ + 16, + 22 + ] + }, + { + "text": "The initial value in rs1 is written to the CSR.", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions", + "line_range": [ + 16, + 22 + ] + }, + { + "text": "If rd=`x0`, then the instruction shall not read the CSR and shall not cause any of the side effects that might occur on a CSR read.", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions", + "line_range": [ + 16, + 22 + ] + }, + { + "text": "The CSRRS (Atomic Read and Set Bits in CSR) instruction reads the value of the CSR, zero-extends the value to XLEN bits, and writes it to integer register rd.", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions", + "line_range": [ + 24, + 30 + ] + }, + { + "text": "The initial value in integer register rs1 is treated as a bit mask that specifies bit positions to be set in the CSR.", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions", + "line_range": [ + 24, + 30 + ] + }, + { + "text": "Any bit that is high in rs1 will cause the corresponding bit to be set in the CSR, if that CSR bit is writable.", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions", + "line_range": [ + 24, + 30 + ] + }, + { + "text": "The CSRRC (Atomic Read and Clear Bits in CSR) instruction reads the value of the CSR, zero-extends the value to XLEN bits, and writes it to integer register rd.", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions", + "line_range": [ + 32, + 38 + ] + }, + { + "text": "The initial value in integer register rs1 is treated as a bit mask that specifies bit positions to be cleared in the CSR.", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions", + "line_range": [ + 32, + 38 + ] + }, + { + "text": "Any bit that is high in rs1 will cause the corresponding bit to be cleared in the CSR, if that CSR bit is writable.", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions", + "line_range": [ + 32, + 38 + ] + }, + { + "text": "For both CSRRS and CSRRC, if rs1=`x0`, then the instruction will not write to the CSR at all, and so shall not cause any of the side effects that might otherwise occur on a CSR write, nor raise illegal-instruction exceptions on accesses to read-only CSRs.", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions", + "line_range": [ + 40, + 50 + ] + }, + { + "text": "Both CSRRS and CSRRC always read the addressed CSR and cause any read side effects regardless of rs1 and rd fields.", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions", + "line_range": [ + 40, + 50 + ] + }, + { + "text": "Note that if rs1 specifies a register other than `x0`, and that register holds a zero value, the instruction will not action any attendant per-field side effects, but will action any side effects caused by writing to the entire CSR.", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions", + "line_range": [ + 40, + 50 + ] + }, + { + "text": "A CSRRW with rs1=`x0` will attempt to write zero to the destination CSR.", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions", + "line_range": [ + 52, + 53 + ] + }, + { + "text": "The CSRRWI, CSRRSI, and CSRRCI variants are similar to CSRRW, CSRRS, and CSRRC respectively, except they update the CSR using an XLEN-bit value obtained by zero-extending a 5-bit unsigned immediate (uimm[4:0]) field encoded in the rs1 field instead of a value from an integer register.", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions", + "line_range": [ + 55, + 67 + ] + }, + { + "text": "For CSRRSI and CSRRCI, if the uimm[4:0] field is zero, then these instructions will not write to the CSR, and shall not cause any of the side effects that might otherwise occur on a CSR write, nor raise illegal-instruction exceptions on accesses to read-only CSRs.", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions", + "line_range": [ + 55, + 67 + ] + }, + { + "text": "For CSRRWI, if rd=`x0`, then the instruction shall not read the CSR and shall not cause any of the side effects that might occur on a CSR read.", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions", + "line_range": [ + 55, + 67 + ] + }, + { + "text": "Both CSRRSI and CSRRCI will always read the CSR and cause any read side effects regardless of rd and rs1 fields.", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions", + "line_range": [ + 55, + 67 + ] + }, + { + "text": ".Conditions determining whether a CSR instruction reads or writes the specified CSR. | 5+^|*Register operand* |Instruction |rd is `x0` |rs1 is `x0` |Reads CSR |Writes CSR", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions", + "line_range": [ + 69, + 74 + ] + }, + { + "text": "|CSRRS/CSRRC |- |Yes |Yes |No", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions", + "line_range": [ + 80, + 80 + ] + }, + { + "text": "|CSRRS/CSRRC |- |No |Yes |Yes", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions", + "line_range": [ + 82, + 82 + ] + }, + { + "text": "|Instruction |rd is `x0` |uimm=0 |Reads CSR |Writes CSR", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions", + "line_range": [ + 86, + 87 + ] + }, + { + "text": "|CSRRSI/CSRRCI |- |Yes |Yes |No", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions", + "line_range": [ + 93, + 93 + ] + }, + { + "text": "|CSRRSI/CSRRCI |- |No |Yes |Yes |", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions", + "line_range": [ + 95, + 96 + ] + }, + { + "text": "summarizes the behavior of the CSR instructions with respect to whether they read and/or write the CSR.", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions", + "line_range": [ + 98, + 100 + ] + }, + { + "text": "In addition to side effects that occur as a consequence of reading or writing a CSR, individual fields within a CSR might have side effects when written.", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions", + "line_range": [ + 102, + 120 + ] + }, + { + "text": "The CSRRW[I] instructions action side effects for all such fields within the written CSR.", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions", + "line_range": [ + 102, + 120 + ] + }, + { + "text": "The CSRRS[I] and CSRRC[I] instructions only action side effects for fields for which the rs1 or uimm argument has at least one bit set corresponding to that field.", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions", + "line_range": [ + 102, + 120 + ] + }, + { + "text": "For any event or consequence that occurs due to a CSR having a particular value, if a write to the CSR gives it that value, the resulting event or consequence is said to be an indirect effect of the write.", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions", + "line_range": [ + 102, + 120 + ] + }, + { + "text": "Indirect effects of a CSR write are not considered by the RISC-V ISA to be side effects of that write.", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions", + "line_range": [ + 102, + 120 + ] + }, + { + "text": "Some CSRs, such as the instructions-retired counter, `instret`, may be modified as side effects of instruction execution.", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions", + "line_range": [ + 102, + 120 + ] + }, + { + "text": "In these cases, if a CSR access instruction reads a CSR, it reads the value prior to the execution of the instruction.", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions", + "line_range": [ + 102, + 120 + ] + }, + { + "text": "If a CSR access instruction writes such a CSR, the explicit write is done instead of the update from the side effect.", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions", + "line_range": [ + 102, + 120 + ] + }, + { + "text": "In particular, a value written to `instret` by one instruction will be the value read by the following instruction.", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions", + "line_range": [ + 102, + 120 + ] + }, + { + "text": "The assembler pseudoinstruction to read a CSR, CSRR rd, csr, is encoded as CSRRS rd, csr, x0.", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions", + "line_range": [ + 122, + 125 + ] + }, + { + "text": "The assembler pseudoinstruction to write a CSR, CSRW csr, rs1, is encoded as CSRRW x0, csr, rs1, while CSRWI csr, uimm, is encoded as CSRRWI x0, csr, uimm.", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions", + "line_range": [ + 122, + 125 + ] + }, + { + "text": "Further assembler pseudoinstructions are defined to set and clear bits in the CSR when the old value is not required: CSRS/CSRC csr, rs1; CSRSI/CSRCI csr, uimm.", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions", + "line_range": [ + 127, + 129 + ] + }, + { + "text": "Each RISC-V hart normally observes its own CSR accesses, including its implicit CSR accesses, as performed in program order.", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions > CSR Access Ordering", + "line_range": [ + 133, + 142 + ] + }, + { + "text": "In particular, unless specified otherwise, a CSR access is performed after the execution of any prior instructions in program order whose behavior modifies or is modified by the CSR state and before the execution of any subsequent instructions in program order whose behavior modifies or is modified by the CSR state.", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions > CSR Access Ordering", + "line_range": [ + 133, + 142 + ] + }, + { + "text": "Furthermore, an explicit CSR read returns the CSR state before the execution of the instruction, while an explicit CSR write suppresses and overrides any implicit writes or modifications to the same CSR by the same instruction.", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions > CSR Access Ordering", + "line_range": [ + 133, + 142 + ] + }, + { + "text": "Likewise, any side effects from an explicit CSR access are normally observed to occur synchronously in program order.", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions > CSR Access Ordering", + "line_range": [ + 144, + 149 + ] + }, + { + "text": "Unless specified otherwise, the full consequences of any such side effects are observable by the very next instruction, and no consequences may be observed out-of-order by preceding instructions. (Note the distinction made earlier between side effects and indirect effects of CSR writes.)", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions > CSR Access Ordering", + "line_range": [ + 144, + 149 + ] + }, + { + "text": "For the RVWMO memory consistency model (), CSR accesses are weakly ordered by default, so other harts or devices may observe CSR accesses in an order different from program order.", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions > CSR Access Ordering", + "line_range": [ + 151, + 168 + ] + }, + { + "text": "In addition, CSR accesses are not ordered with respect to explicit memory accesses, unless a CSR access modifies the execution behavior of the instruction that performs the explicit memory access or unless a CSR access and an explicit memory access are ordered by either the syntactic dependencies defined by the memory model or the ordering requirements defined in .", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions > CSR Access Ordering", + "line_range": [ + 151, + 168 + ] + }, + { + "text": "To enforce ordering in all other cases, software should execute a FENCE instruction between the relevant accesses.", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions > CSR Access Ordering", + "line_range": [ + 151, + 168 + ] + }, + { + "text": "For the purposes of the FENCE instruction, CSR read accesses are classified as device input (I), and CSR write accesses are classified as device output (O).", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions > CSR Access Ordering", + "line_range": [ + 151, + 168 + ] + }, + { + "text": "The hardware platform may define that accesses to certain CSRs are strongly ordered, Accesses to strongly ordered CSRs have stronger ordering constraints with respect to accesses to both weakly ordered CSRs and accesses to memory-mapped I/O regions.", + "section": "Preamble > \"Zicsr\" Extension for Control and Status Register (CSR) Instructions, Version 2.0 > CSR Instructions > CSR Access Ordering", + "line_range": [ + 151, + 168 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zifencei.json b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zifencei.json new file mode 100644 index 0000000000..94bc6ca74a --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zifencei.json @@ -0,0 +1,78 @@ +{ + "source_file": "src/unpriv/zifencei.adoc", + "total": 9, + "sentences": [ + { + "text": "This chapter defines the \"Zifencei\" extension, which includes the FENCE.I instruction that provides explicit synchronization between writes to instruction memory and instruction fetches on the same hart.", + "section": "Preamble > \"Zifencei\" Extension for Instruction-Fetch Fence, Version 2.0", + "line_range": [ + 3, + 9 + ] + }, + { + "text": "Currently, this instruction is the only standard mechanism to ensure that stores visible to a hart will also be visible to its instruction fetches.", + "section": "Preamble > \"Zifencei\" Extension for Instruction-Fetch Fence, Version 2.0", + "line_range": [ + 3, + 9 + ] + }, + { + "text": "''' include::images/wavedrom/zifencei-ff.edn[] //.FENCE.I instruction", + "section": "Preamble > \"Zifencei\" Extension for Instruction-Fetch Fence, Version 2.0", + "line_range": [ + 11, + 15 + ] + }, + { + "text": "The FENCE.I instruction is used to synchronize the instruction and data streams. RISC-V does not guarantee that stores to instruction memory will be made visible to instruction fetches on a RISC-V hart until that hart executes a FENCE.I instruction. A FENCE.I instruction ensures that a subsequent instruction fetch on a RISC-V hart will see any previous data stores already visible to the same RISC-V hart. FENCE.I does not ensure that other RISC-V harts' instruction fetches will observe the local hart's stores in a multiprocessor system.", + "section": "Preamble > \"Zifencei\" Extension for Instruction-Fetch Fence, Version 2.0", + "line_range": [ + 17, + 27 + ] + }, + { + "text": "To make a store to instruction memory visible to all RISC-V harts, the writing hart also has to execute a data FENCE before requesting that all remote RISC-V harts execute a FENCE.I.", + "section": "Preamble > \"Zifencei\" Extension for Instruction-Fetch Fence, Version 2.0", + "line_range": [ + 17, + 27 + ] + }, + { + "text": "A FENCE.I instruction orders all explicit memory accesses that precede the FENCE.I in program order before all instruction fetches that follow the FENCE.I in program order.", + "section": "Preamble > \"Zifencei\" Extension for Instruction-Fetch Fence, Version 2.0", + "line_range": [ + 29, + 32 + ] + }, + { + "text": "An instruction fetch is always ordered before any explicit memory accesses that instruction gives rise to.", + "section": "Preamble > \"Zifencei\" Extension for Instruction-Fetch Fence, Version 2.0", + "line_range": [ + 34, + 35 + ] + }, + { + "text": "The unused fields in the FENCE.I instruction, funct12, rs1, and rd, are reserved for finer-grain fences in future extensions.", + "section": "Preamble > \"Zifencei\" Extension for Instruction-Fetch Fence, Version 2.0", + "line_range": [ + 37, + 43 + ] + }, + { + "text": "For forward compatibility, base implementations shall ignore these fields, and standard software shall zero these fields.", + "section": "Preamble > \"Zifencei\" Extension for Instruction-Fetch Fence, Version 2.0", + "line_range": [ + 37, + 43 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zihintntl.json b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zihintntl.json new file mode 100644 index 0000000000..2d0fac61f6 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zihintntl.json @@ -0,0 +1,174 @@ +{ + "source_file": "src/unpriv/zihintntl.adoc", + "total": 21, + "sentences": [ + { + "text": "The NTL instructions are HINTs that indicate that the explicit memory accesses of the immediately subsequent instruction (henceforth \"target instruction\") exhibit poor temporal locality of reference.", + "section": "Preamble > \"Zihintntl\" Extension for Non-Temporal Locality Hints, Version 1.0", + "line_range": [ + 3, + 8 + ] + }, + { + "text": "The NTL instructions do not change architectural state, nor do they alter the architecturally visible effects of the target instruction.", + "section": "Preamble > \"Zihintntl\" Extension for Non-Temporal Locality Hints, Version 1.0", + "line_range": [ + 3, + 8 + ] + }, + { + "text": "Four variants are provided:", + "section": "Preamble > \"Zihintntl\" Extension for Non-Temporal Locality Hints, Version 1.0", + "line_range": [ + 3, + 8 + ] + }, + { + "text": "The NTL.P1 instruction indicates that the target instruction does not exhibit temporal locality within the capacity of the innermost level of private cache in the memory hierarchy. NTL.P1 is encoded as ADD x0, x0, x2.", + "section": "Preamble > \"Zihintntl\" Extension for Non-Temporal Locality Hints, Version 1.0", + "line_range": [ + 10, + 13 + ] + }, + { + "text": "The NTL.PALL instruction indicates that the target instruction does not exhibit temporal locality within the capacity of any level of private cache in the memory hierarchy. NTL.PALL is encoded as ADD x0, x0, x3.", + "section": "Preamble > \"Zihintntl\" Extension for Non-Temporal Locality Hints, Version 1.0", + "line_range": [ + 15, + 17 + ] + }, + { + "text": "The NTL.S1 instruction indicates that the target instruction does not exhibit temporal locality within the capacity of the innermost level of shared cache in the memory hierarchy. NTL.S1 is encoded as ADD x0, x0, x4.", + "section": "Preamble > \"Zihintntl\" Extension for Non-Temporal Locality Hints, Version 1.0", + "line_range": [ + 19, + 22 + ] + }, + { + "text": "The NTL.ALL instruction indicates that the target instruction does not exhibit temporal locality within the capacity of any level of cache in the memory hierarchy. NTL.ALL is encoded as ADD x0, x0, x5.", + "section": "Preamble > \"Zihintntl\" Extension for Non-Temporal Locality Hints, Version 1.0", + "line_range": [ + 24, + 26 + ] + }, + { + "text": "lists several software use cases and the recommended NTL variant that portable software—i.e., software not tuned for any specific implementation's memory hierarchy—should use in each case.", + "section": "Preamble > \"Zihintntl\" Extension for Non-Temporal Locality Hints, Version 1.0", + "line_range": [ + 28, + 28 + ] + }, + { + "text": ".Recommended NTL variant for portable software to employ in various scenarios. | |Scenario |Recommended NTL variant |Access to a working set between 64 KiB and 256 KiB in size |NTL.P1 |Access to a working set between 256 KiB and 1 MiB in size |NTL.PALL |Access to a working set greater than 1 MiB in size |NTL.S1 |Access with no exploitable temporal locality (e.g., streaming) |NTL.ALL |Access to a contended synchronization variable |NTL.PALL |", + "section": "Preamble > \"Zihintntl\" Extension for Non-Temporal Locality Hints, Version 1.0", + "line_range": [ + 30, + 40 + ] + }, + { + "text": "lists several sample memory hierarchies and recommends how each NTL variant maps onto each cache level.", + "section": "Preamble > \"Zihintntl\" Extension for Non-Temporal Locality Hints, Version 1.0", + "line_range": [ + 42, + 52 + ] + }, + { + "text": "The table also recommends which NTL variant that implementation-tuned software should use to avoid allocating in a particular cache level.", + "section": "Preamble > \"Zihintntl\" Extension for Non-Temporal Locality Hints, Version 1.0", + "line_range": [ + 42, + 52 + ] + }, + { + "text": "For example, for a system with a private L1 and a shared L2, it is recommended that NTL.P1 and NTL.PALL indicate that temporal locality cannot be exploited by the L1, and that NTL.S1 and NTL.ALL indicate that temporal locality cannot be exploited by the L2.", + "section": "Preamble > \"Zihintntl\" Extension for Non-Temporal Locality Hints, Version 1.0", + "line_range": [ + 42, + 52 + ] + }, + { + "text": "Furthermore, software tuned for such a system should use NTL.P1 to indicate a lack of temporal locality exploitable by the L1, or should use NTL.ALL indicate a lack of temporal locality exploitable by the L2.", + "section": "Preamble > \"Zihintntl\" Extension for Non-Temporal Locality Hints, Version 1.0", + "line_range": [ + 42, + 52 + ] + }, + { + "text": "If the C or Zca extension is provided, compressed variants of these HINTs are also provided: C.NTL.P1 is encoded as C.ADD x0, x2; C.NTL.PALL is encoded as C.ADD x0, x3; C.NTL.S1 is encoded as C.ADD x0, x4; and C.NTL.ALL is encoded as C.ADD x0, x5.", + "section": "Preamble > \"Zihintntl\" Extension for Non-Temporal Locality Hints, Version 1.0", + "line_range": [ + 54, + 57 + ] + }, + { + "text": "The NTL instructions affect all memory-access instructions except the cache-management instructions in the Zicbom extension.", + "section": "Preamble > \"Zihintntl\" Extension for Non-Temporal Locality Hints, Version 1.0", + "line_range": [ + 59, + 60 + ] + }, + { + "text": ".Mapping of NTL variants to various memory hierarchies. | | Memory hierarchy 4+| Recommended mapping of NTL + variant to actual cache level 4+| Recommended NTL variant for + explicit cache management | |P1 |PALL |S1 |ALL |L1 |L2 |L3 |L4/L5 9+^| Common Scenarios | No caches 4+|--- 4+|none |Private L1 only |L1 |L1 |L1 |L1| ALL |--- |--- |--- |Private L1; shared L2 |L1 |L1 |L2 |L2 |P1|ALL|---|--- |Private L1; shared L2/L3 |L1 | L1 | L2 | L3 |P1 |S1 |ALL |--- |Private L1/L2 |L1 |L2 |L2 |L2 | P1 |ALL |--- |--- |Private L1/L2; shared L3 |L1 | L2 | L3 | L3 | P1 | PALL| ALL |--- |Private L1/L2; shared L3/L4 | L1 | L2| L3 | L4 | P1 | PALL | S1 | ALL 9+^| Uncommon Scenarios |Private L1/L2/L3; shared L4 | L1 | L3 |L4 |L4 |P1 |P1 |PALL |ALL |Private L1; shared L2/L3/L4 |L1 | L1 |L2 |L4 |P1 |S1 |ALL |ALL |Private L1/L2; shared L3/L4/L5 |L1 | L2 | L3 | L5 |P1 | PALL |S1 |ALL |Private L1/L2/L3; shared L4/L5 |L1 |L3 |L4 |L5 |P1 |P1 |PALL |ALL |", + "section": "Preamble > \"Zihintntl\" Extension for Non-Temporal Locality Hints, Version 1.0", + "line_range": [ + 64, + 87 + ] + }, + { + "text": "When an NTL instruction is applied to a prefetch hint in the Zicbop extension, it indicates that a cache line should be prefetched into a cache that is outer from the level specified by the NTL.", + "section": "Preamble > \"Zihintntl\" Extension for Non-Temporal Locality Hints, Version 1.0", + "line_range": [ + 89, + 91 + ] + }, + { + "text": "Software is discouraged from following an NTL instruction with an instruction that does not explicitly access memory.", + "section": "Preamble > \"Zihintntl\" Extension for Non-Temporal Locality Hints, Version 1.0", + "line_range": [ + 93, + 96 + ] + }, + { + "text": "Nonadherence to this recommendation might reduce performance but otherwise has no architecturally visible effect.", + "section": "Preamble > \"Zihintntl\" Extension for Non-Temporal Locality Hints, Version 1.0", + "line_range": [ + 93, + 96 + ] + }, + { + "text": "In the event that a trap is taken on the target instruction, implementations are discouraged from applying the NTL to the first instruction in the trap handler.", + "section": "Preamble > \"Zihintntl\" Extension for Non-Temporal Locality Hints, Version 1.0", + "line_range": [ + 98, + 101 + ] + }, + { + "text": "Instead, implementations are recommended to ignore the HINT in this case.", + "section": "Preamble > \"Zihintntl\" Extension for Non-Temporal Locality Hints, Version 1.0", + "line_range": [ + 98, + 101 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zihintpause.json b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zihintpause.json new file mode 100644 index 0000000000..a565c710e8 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zihintpause.json @@ -0,0 +1,30 @@ +{ + "source_file": "src/unpriv/zihintpause.adoc", + "total": 3, + "sentences": [ + { + "text": "The PAUSE instruction is a HINT that indicates the current hart's rate of instruction retirement should be temporarily reduced or paused.", + "section": "Preamble > \"Zihintpause\" Extension for Pause Hint, Version 2.0", + "line_range": [ + 3, + 7 + ] + }, + { + "text": "The duration of its effect must be bounded and may be zero.", + "section": "Preamble > \"Zihintpause\" Extension for Pause Hint, Version 2.0", + "line_range": [ + 3, + 7 + ] + }, + { + "text": "PAUSE is encoded as a FENCE instruction with pred=`W`, succ=`0`, fm=`0`, rd=`x0`, and rs1=`x0`.", + "section": "Preamble > \"Zihintpause\" Extension for Pause Hint, Version 2.0", + "line_range": [ + 9, + 10 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zihpm.json b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zihpm.json new file mode 100644 index 0000000000..492e7e14cf --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zihpm.json @@ -0,0 +1,62 @@ +{ + "source_file": "src/unpriv/zihpm.adoc", + "total": 7, + "sentences": [ + { + "text": "The Zihpm extension comprises up to 29 additional unprivileged 64-bit hardware performance counters, `hpmcounter3-hpmcounter31`.", + "section": "Preamble > \"Zihpm\" Extension for Hardware Performance Counters", + "line_range": [ + 3, + 13 + ] + }, + { + "text": "When XLEN=32, the upper 32 bits of these performance counters are accessible via additional CSRs `hpmcounter3h- hpmcounter31h`.", + "section": "Preamble > \"Zihpm\" Extension for Hardware Performance Counters", + "line_range": [ + 3, + 13 + ] + }, + { + "text": "The Zihpm extension depends on the Zicsr extension.", + "section": "Preamble > \"Zihpm\" Extension for Hardware Performance Counters", + "line_range": [ + 3, + 13 + ] + }, + { + "text": "The implemented number and width of these additional counters, and the set of events they count, are platform-specific.", + "section": "Preamble > \"Zihpm\" Extension for Hardware Performance Counters", + "line_range": [ + 3, + 13 + ] + }, + { + "text": "Accessing an unimplemented counter may cause an illegal-instruction exception or may return a constant value.", + "section": "Preamble > \"Zihpm\" Extension for Hardware Performance Counters", + "line_range": [ + 3, + 13 + ] + }, + { + "text": "If the configuration used to select the events counted by a counter is misconfigured, the counter may return a constant value.", + "section": "Preamble > \"Zihpm\" Extension for Hardware Performance Counters", + "line_range": [ + 3, + 13 + ] + }, + { + "text": "The execution environment should provide a means to determine the number and width of the implemented counters, and an interface to configure the events to be counted by each counter.", + "section": "Preamble > \"Zihpm\" Extension for Hardware Performance Counters", + "line_range": [ + 15, + 17 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zilsd.json b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zilsd.json new file mode 100644 index 0000000000..e57bca1869 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zilsd.json @@ -0,0 +1,310 @@ +{ + "source_file": "src/unpriv/zilsd.adoc", + "total": 38, + "sentences": [ + { + "text": "The ext:zilsd[] extension provides load/store pair instructions for RV32, reusing the existing RV64 doubleword load/store instruction encodings.", + "section": "Preamble > ext:zilsd[] Extension for Load/Store Pair Instructions", + "line_range": [ + 3, + 3 + ] + }, + { + "text": "Operands containing `src` for store instructions and `dest` for load instructions are held in aligned `x`-register pairs, i.e., register numbers must be even.", + "section": "Preamble > ext:zilsd[] Extension for Load/Store Pair Instructions", + "line_range": [ + 5, + 5 + ] + }, + { + "text": "Use of misaligned (odd-numbered) registers for these operands is reserved.", + "section": "Preamble > ext:zilsd[] Extension for Load/Store Pair Instructions", + "line_range": [ + 5, + 5 + ] + }, + { + "text": "Regardless of endianness, the lower-numbered register holds the low-order bits, and the higher-numbered register holds the high-order bits: e.g., bits 31:0 of an operand in Zilsd might be held in register `x14`, with bits 63:32 of that operand held in `x15`.", + "section": "Preamble > ext:zilsd[] Extension for Load/Store Pair Instructions", + "line_range": [ + 7, + 9 + ] + }, + { + "text": "The Zilsd extension adds the following RV32-only instructions:", + "section": "Preamble > ext:zilsd[] Extension for Load/Store Pair Instructions", + "line_range": [ + 11, + 11 + ] + }, + { + "text": "| |RV32 |RV64 |Mnemonic |Instruction", + "section": "Preamble > ext:zilsd[] Extension for Load/Store Pair Instructions", + "line_range": [ + 13, + 18 + ] + }, + { + "text": "|yes |no |ld rd, offset(rs1) |", + "section": "Preamble > ext:zilsd[] Extension for Load/Store Pair Instructions", + "line_range": [ + 20, + 23 + ] + }, + { + "text": "|yes |no |sd rs2, offset(rs1) |", + "section": "Preamble > ext:zilsd[] Extension for Load/Store Pair Instructions", + "line_range": [ + 25, + 28 + ] + }, + { + "text": "As the access size is 64-bit, accesses are only considered naturally aligned for effective addresses that are a multiple of 8.", + "section": "Preamble > ext:zilsd[] Extension for Load/Store Pair Instructions", + "line_range": [ + 32, + 34 + ] + }, + { + "text": "In this case, these instructions are guaranteed to not raise an address-misaligned exception.", + "section": "Preamble > ext:zilsd[] Extension for Load/Store Pair Instructions", + "line_range": [ + 32, + 34 + ] + }, + { + "text": "Even if naturally aligned, the memory access might not be performed atomically.", + "section": "Preamble > ext:zilsd[] Extension for Load/Store Pair Instructions", + "line_range": [ + 32, + 34 + ] + }, + { + "text": "If the effective address is a multiple of 4, then each word access is required to be performed atomically.", + "section": "Preamble > ext:zilsd[] Extension for Load/Store Pair Instructions", + "line_range": [ + 36, + 36 + ] + }, + { + "text": "The following table summarizes the required behavior:", + "section": "Preamble > ext:zilsd[] Extension for Load/Store Pair Instructions", + "line_range": [ + 38, + 38 + ] + }, + { + "text": "| |Alignment |Word accesses guaranteed atomic? |Can cause misaligned trap? |8{nbsp}B |yes |no |4{nbsp}B not 8{nbsp}B |yes |yes |else |no | yes |", + "section": "Preamble > ext:zilsd[] Extension for Load/Store Pair Instructions", + "line_range": [ + 40, + 46 + ] + }, + { + "text": "To ensure resumable trap handling is possible for the load instructions, the base register must have its original value if a trap is taken.", + "section": "Preamble > ext:zilsd[] Extension for Load/Store Pair Instructions", + "line_range": [ + 48, + 50 + ] + }, + { + "text": "The other register in the pair can have been updated.", + "section": "Preamble > ext:zilsd[] Extension for Load/Store Pair Instructions", + "line_range": [ + 48, + 50 + ] + }, + { + "text": "This affects x2 for the stack pointer relative instruction and rs1 otherwise.", + "section": "Preamble > ext:zilsd[] Extension for Load/Store Pair Instructions", + "line_range": [ + 48, + 50 + ] + }, + { + "text": "LD instructions with destination `x0` are processed as any other load, but the result is discarded entirely and x1 is not written.", + "section": "Preamble > ext:zilsd[] Extension for Load/Store Pair Instructions > Use of x0 as operand", + "line_range": [ + 54, + 55 + ] + }, + { + "text": "If using `x0` as `src` of SD, the entire 64-bit operand is zero — i.e., register `x1` is not accessed.", + "section": "Preamble > ext:zilsd[] Extension for Load/Store Pair Instructions > Use of x0 as operand", + "line_range": [ + 57, + 58 + ] + }, + { + "text": "For the purposes of RVWMO and exception handling, LD and SD instructions are considered to be misaligned loads and stores, with one additional constraint: an LD or SD instruction whose effective address is a multiple of 4 gives rise to two 4-byte memory operations.", + "section": "Preamble > ext:zilsd[] Extension for Load/Store Pair Instructions > Use of x0 as operand > Exception Handling", + "line_range": [ + 62, + 65 + ] + }, + { + "text": "NOTE: This definition permits LD and SD instructions giving rise to exactly one memory access, regardless of alignment.", + "section": "Preamble > ext:zilsd[] Extension for Load/Store Pair Instructions > Use of x0 as operand > Exception Handling", + "line_range": [ + 67, + 74 + ] + }, + { + "text": "If instructions with 4-byte-aligned effective address are decomposed into two 32b operations, there is no constraint on the order in which the operations are performed and each operation is guaranteed to be atomic.", + "section": "Preamble > ext:zilsd[] Extension for Load/Store Pair Instructions > Use of x0 as operand > Exception Handling", + "line_range": [ + 67, + 74 + ] + }, + { + "text": "These decomposed sequences are interruptible.", + "section": "Preamble > ext:zilsd[] Extension for Load/Store Pair Instructions > Use of x0 as operand > Exception Handling", + "line_range": [ + 67, + 74 + ] + }, + { + "text": "Exceptions might occur on subsequent operations, making the effects of previous operations within the same instruction visible.", + "section": "Preamble > ext:zilsd[] Extension for Load/Store Pair Instructions > Use of x0 as operand > Exception Handling", + "line_range": [ + 67, + 74 + ] + }, + { + "text": "NOTE: Software should make no assumptions about the number or order of accesses these instructions might give rise to, beyond the 4-byte constraint mentioned above.", + "section": "Preamble > ext:zilsd[] Extension for Load/Store Pair Instructions > Use of x0 as operand > Exception Handling", + "line_range": [ + 76, + 80 + ] + }, + { + "text": "For example, an interrupted store might overwrite the same bytes upon return from the interrupt handler.", + "section": "Preamble > ext:zilsd[] Extension for Load/Store Pair Instructions > Use of x0 as operand > Exception Handling", + "line_range": [ + 76, + 80 + ] + }, + { + "text": "[insns-ld,reftext=\"Load doubleword to register pair, 32-bit encoding\"]", + "section": "Preamble > ext:zilsd[] Extension for Load/Store Pair Instructions > Use of x0 as operand > Instructions", + "line_range": [ + 86, + 86 + ] + }, + { + "text": "Synopsis:: Load doubleword to even/odd register pair, 32-bit encoding", + "section": "Preamble > ext:zilsd[] Extension for Load/Store Pair Instructions > Use of x0 as operand > Instructions > ld", + "line_range": [ + 88, + 89 + ] + }, + { + "text": "Mnemonic:: ld rd, offset(rs1)", + "section": "Preamble > ext:zilsd[] Extension for Load/Store Pair Instructions > Use of x0 as operand > Instructions > ld", + "line_range": [ + 91, + 92 + ] + }, + { + "text": "Encoding (RV32):: [wavedrom, ,svg] .... {reg: [ {bits: 7, name: 0x3, attr: ['LOAD'], type: 8}, {bits: 5, name: 'rd', attr: ['dest, dest[0]=0'], type: 2}, {bits: 3, name: 0x3, attr: ['width=D'], type: 8}, {bits: 5, name: 'rs1', attr: ['base'], type: 4}, {bits: 12, name: 'imm[11:0]', attr: ['offset[11:0]'], type: 3}, ]} ....", + "section": "Preamble > ext:zilsd[] Extension for Load/Store Pair Instructions > Use of x0 as operand > Instructions > ld", + "line_range": [ + 94, + 104 + ] + }, + { + "text": "Description:: Loads a 64-bit value into registers `rd` and `rd+1`.", + "section": "Preamble > ext:zilsd[] Extension for Load/Store Pair Instructions > Use of x0 as operand > Instructions > ld", + "line_range": [ + 106, + 110 + ] + }, + { + "text": "The effective address is obtained by adding register rs1 to the sign-extended 12-bit offset.", + "section": "Preamble > ext:zilsd[] Extension for Load/Store Pair Instructions > Use of x0 as operand > Instructions > ld", + "line_range": [ + 106, + 110 + ] + }, + { + "text": "[insns-sd,reftext=\"Store doubleword from register pair, 32-bit encoding\"]", + "section": "Preamble > ext:zilsd[] Extension for Load/Store Pair Instructions > Use of x0 as operand > Instructions > ld", + "line_range": [ + 116, + 116 + ] + }, + { + "text": "Synopsis:: Store doubleword from even/odd register pair, 32-bit encoding", + "section": "Preamble > ext:zilsd[] Extension for Load/Store Pair Instructions > Use of x0 as operand > Instructions > sd", + "line_range": [ + 119, + 120 + ] + }, + { + "text": "Mnemonic:: sd rs2, offset(rs1)", + "section": "Preamble > ext:zilsd[] Extension for Load/Store Pair Instructions > Use of x0 as operand > Instructions > sd", + "line_range": [ + 122, + 123 + ] + }, + { + "text": "Encoding (RV32):: [wavedrom, ,svg] .... {reg: [ {bits: 7, name: 0x23, attr: ['STORE'], type: 8}, {bits: 5, name: 'imm[4:0]', attr: ['offset[4:0]'], type: 3}, {bits: 3, name: 0x3, attr: ['width=D'], type: 8}, {bits: 5, name: 'rs1', attr: ['base'], type: 4}, {bits: 5, name: 'rs2', attr: ['src, src[0]=0'], type: 4}, {bits: 7, name: 'imm[11:5]', attr: ['offset[11:5]'], type: 3}, ]} ....", + "section": "Preamble > ext:zilsd[] Extension for Load/Store Pair Instructions > Use of x0 as operand > Instructions > sd", + "line_range": [ + 125, + 136 + ] + }, + { + "text": "Description:: Stores a 64-bit value from registers `rs2` and `rs2+1`.", + "section": "Preamble > ext:zilsd[] Extension for Load/Store Pair Instructions > Use of x0 as operand > Instructions > sd", + "line_range": [ + 138, + 142 + ] + }, + { + "text": "The effective address is obtained by adding register rs1 to the sign-extended 12-bit offset.", + "section": "Preamble > ext:zilsd[] Extension for Load/Store Pair Instructions > Use of x0 as operand > Instructions > sd", + "line_range": [ + 138, + 142 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zimop.json b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zimop.json new file mode 100644 index 0000000000..f3a6a3c97b --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zimop.json @@ -0,0 +1,142 @@ +{ + "source_file": "src/unpriv/zimop.adoc", + "total": 17, + "sentences": [ + { + "text": "This chapter defines the ext:zimop[] extension, which introduces the concept of instructions that may be operations (MOPs). MOPs are initially defined to simply write zero to `x[rd]`, but are designed to be redefined by later extensions to perform some other action.", + "section": "Preamble > ext:zimop[] Extension for May-Be-Operations", + "line_range": [ + 3, + 7 + ] + }, + { + "text": "The ext:zimop[] extension defines an encoding space for 40 MOPs.", + "section": "Preamble > ext:zimop[] Extension for May-Be-Operations", + "line_range": [ + 3, + 7 + ] + }, + { + "text": "The ext:zimop[] extension defines 32 MOP instructions named MOP.R.n, where n is an integer between 0 and 31, inclusive.", + "section": "Preamble > ext:zimop[] Extension for May-Be-Operations", + "line_range": [ + 9, + 13 + ] + }, + { + "text": "Unless redefined by another extension, these instructions simply write 0 to `x[rd]`.", + "section": "Preamble > ext:zimop[] Extension for May-Be-Operations", + "line_range": [ + 9, + 13 + ] + }, + { + "text": "Their encoding allows future extensions to define them to read `x[rs1]`, as well as write `x[rd]`.", + "section": "Preamble > ext:zimop[] Extension for May-Be-Operations", + "line_range": [ + 9, + 13 + ] + }, + { + "text": "include::images/wavedrom/mop-r.edn[]", + "section": "Preamble > ext:zimop[] Extension for May-Be-Operations", + "line_range": [ + 15, + 17 + ] + }, + { + "text": "The ext:zimop[] extension additionally defines 8 MOP instructions named MOP.RR.n, where n is an integer between 0 and 7, inclusive.", + "section": "Preamble > ext:zimop[] Extension for May-Be-Operations", + "line_range": [ + 19, + 23 + ] + }, + { + "text": "Unless redefined by another extension, these instructions simply write 0 to `x[rd]`.", + "section": "Preamble > ext:zimop[] Extension for May-Be-Operations", + "line_range": [ + 19, + 23 + ] + }, + { + "text": "Their encoding allows future extensions to define them to read `x[rs1]` and `x[rs2]`, as well as write `x[rd]`.", + "section": "Preamble > ext:zimop[] Extension for May-Be-Operations", + "line_range": [ + 19, + 23 + ] + }, + { + "text": "include::images/wavedrom/mop-rr.edn[]", + "section": "Preamble > ext:zimop[] Extension for May-Be-Operations", + "line_range": [ + 25, + 27 + ] + }, + { + "text": "NOTE: The recommended assembly syntax for MOP.R.n is MOP.R.n rd, rs1, with any `x`-register specifier being valid for either argument.", + "section": "Preamble > ext:zimop[] Extension for May-Be-Operations", + "line_range": [ + 29, + 32 + ] + }, + { + "text": "Similarly for MOP.RR.n, the recommended syntax is MOP.RR.n rd, rs1, rs2.", + "section": "Preamble > ext:zimop[] Extension for May-Be-Operations", + "line_range": [ + 29, + 32 + ] + }, + { + "text": "The extension that redefines a MOP may define an alternate assembly mnemonic.", + "section": "Preamble > ext:zimop[] Extension for May-Be-Operations", + "line_range": [ + 29, + 32 + ] + }, + { + "text": "NOTE: These MOPs are encoded in the SYSTEM major opcode in part because it is expected their behavior will be modulated by privileged CSR state.", + "section": "Preamble > ext:zimop[] Extension for May-Be-Operations", + "line_range": [ + 34, + 35 + ] + }, + { + "text": "NOTE: These MOPs are defined to write zero to `x[rd]`, rather than performing no operation, to simplify instruction decoding and to allow testing the presence of features by branching on the zeroness of the result.", + "section": "Preamble > ext:zimop[] Extension for May-Be-Operations", + "line_range": [ + 37, + 39 + ] + }, + { + "text": "The MOPs defined in the ext:zimop[] extension do not carry a syntactic dependency from `x[rs1]` or `x[rs2]` to `x[rd]`, though an extension that redefines the MOP may impose such a requirement.", + "section": "Preamble > ext:zimop[] Extension for May-Be-Operations", + "line_range": [ + 41, + 43 + ] + }, + { + "text": "NOTE: Not carrying a syntactic dependency relieves straightforward implementations of reading `x[rs1]` and `x[rs2]`.", + "section": "Preamble > ext:zimop[] Extension for May-Be-Operations", + "line_range": [ + 45, + 46 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zmmul.json b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zmmul.json new file mode 100644 index 0000000000..5a079ee12d --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zmmul.json @@ -0,0 +1,30 @@ +{ + "source_file": "src/unpriv/zmmul.adoc", + "total": 3, + "sentences": [ + { + "text": "The ext:zmmul[] extension implements the multiplication subset of the M extension.", + "section": "Preamble > ext:zmmul[] Extension, Version 1.0", + "line_range": [ + 3, + 9 + ] + }, + { + "text": "It adds all of the instructions defined in extlink:m[], namely: MUL, MULH, MULHU, MULHSU, and (for RV64 only) MULW.", + "section": "Preamble > ext:zmmul[] Extension, Version 1.0", + "line_range": [ + 3, + 9 + ] + }, + { + "text": "The encodings are identical to those of the corresponding M-extension instructions. ext:m[] implies ext:zmmul[].", + "section": "Preamble > ext:zmmul[] Extension, Version 1.0", + "line_range": [ + 3, + 9 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zp.json b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zp.json new file mode 100644 index 0000000000..14ea5c13e5 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zp.json @@ -0,0 +1,22 @@ +{ + "source_file": "src/unpriv/zp.adoc", + "total": 2, + "sentences": [ + { + "text": "NOTE: This chapter is a placeholder for the forthcoming `P` and `Zp*` extensions for packed SIMD within the `x` registers.", + "section": "Preamble > Packed SIMD Extensions", + "line_range": [ + 3, + 6 + ] + }, + { + "text": "It is included so that chapter numbering will not change once the extensions are ratified and incorporated.", + "section": "Preamble > Packed SIMD Extensions", + "line_range": [ + 3, + 6 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__unpriv__ztso.json b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__ztso.json new file mode 100644 index 0000000000..3c33078e42 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__ztso.json @@ -0,0 +1,54 @@ +{ + "source_file": "src/unpriv/ztso.adoc", + "total": 6, + "sentences": [ + { + "text": "This chapter defines the \"Ztso\" extension for the RISC-V Total Store Ordering (RVTSO) memory consistency model. RVTSO is defined as a delta from RVWMO, which is defined in . RVTSO makes the following adjustments to RVWMO:", + "section": "Preamble > \"Ztso\" Extension for Total Store Ordering, Version 1.0", + "line_range": [ + 3, + 7 + ] + }, + { + "text": "All load operations behave as if they have an acquire-RCpc annotation * All store operations behave as if they have a release-RCpc annotation. * All AMOs behave as if they have both acquire-RCsc and release-RCsc annotations.", + "section": "Preamble > \"Ztso\" Extension for Total Store Ordering, Version 1.0", + "line_range": [ + 9, + 12 + ] + }, + { + "text": "Additionally, if the Ztso extension is implemented, then vector memory instructions in the V extension and Zve family of extensions follow RVTSO at the instruction level.", + "section": "Preamble > \"Ztso\" Extension for Total Store Ordering, Version 1.0", + "line_range": [ + 14, + 18 + ] + }, + { + "text": "The Ztso extension does not strengthen the ordering of intra-instruction element accesses.", + "section": "Preamble > \"Ztso\" Extension for Total Store Ordering, Version 1.0", + "line_range": [ + 14, + 18 + ] + }, + { + "text": "In spite of the fact that Ztso adds no new instructions to the ISA, code written assuming RVTSO will not run correctly on implementations not supporting Ztso.", + "section": "Preamble > \"Ztso\" Extension for Total Store Ordering, Version 1.0", + "line_range": [ + 20, + 24 + ] + }, + { + "text": "Binaries compiled to run only under Ztso should indicate as such via a flag in the binary, so that platforms which do not implement Ztso can simply refuse to run them.", + "section": "Preamble > \"Ztso\" Extension for Total Store Ordering, Version 1.0", + "line_range": [ + 20, + 24 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zvfbfmin.json b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zvfbfmin.json new file mode 100644 index 0000000000..721eb18b66 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zvfbfmin.json @@ -0,0 +1,190 @@ +{ + "source_file": "src/unpriv/zvfbfmin.adoc", + "total": 23, + "sentences": [ + { + "text": "This extension provides the minimal set of instructions needed to enable vector support of the BF16 format.", + "section": "Preamble > `Zvfbfmin` Extension for Vector BF16 Conversions", + "line_range": [ + 3, + 5 + ] + }, + { + "text": "It enables BF16 as an interchange format as it provides conversion between BF16 values and FP32 values.", + "section": "Preamble > `Zvfbfmin` Extension for Vector BF16 Conversions", + "line_range": [ + 3, + 5 + ] + }, + { + "text": "This extension depends upon `Zve32f` vector extension.", + "section": "Preamble > `Zvfbfmin` Extension for Vector BF16 Conversions", + "line_range": [ + 7, + 7 + ] + }, + { + "text": "Synopsis:: Vector convert FP32 to BF16", + "section": "Preamble > `Zvfbfmin` Extension for Vector BF16 Conversions > vfncvtbf16.f.f.w", + "line_range": [ + 11, + 12 + ] + }, + { + "text": "Mnemonic:: vfncvtbf16.f.f.w vd, vs2, vm", + "section": "Preamble > `Zvfbfmin` Extension for Vector BF16 Conversions > vfncvtbf16.f.f.w", + "line_range": [ + 14, + 15 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ {bits: 7, name: '1010111', attr:['OP-V']}, {bits: 5, name: 'vd'}, {bits: 3, name: '001', attr:['OPFVV']}, {bits: 5, name: '11101', attr:['vfncvtbf16']}, {bits: 5, name: 'vs2'}, {bits: 1, name: 'vm'}, {bits: 6, name: '010010', attr:['VFUNARY0']}, ]} ....", + "section": "Preamble > `Zvfbfmin` Extension for Vector BF16 Conversions > vfncvtbf16.f.f.w", + "line_range": [ + 17, + 29 + ] + }, + { + "text": "Reserved Encodings:: * `SEW` is any value other than 16", + "section": "Preamble > `Zvfbfmin` Extension for Vector BF16 Conversions > vfncvtbf16.f.f.w", + "line_range": [ + 31, + 33 + ] + }, + { + "text": "| |Register |Direction |EEW |Definition", + "section": "Preamble > `Zvfbfmin` Extension for Vector BF16 Conversions > vfncvtbf16.f.f.w", + "line_range": [ + 37, + 43 + ] + }, + { + "text": "| Vs2 | input | 32 | FP32 Source | Vd | output | 16 | BF16 Result |", + "section": "Preamble > `Zvfbfmin` Extension for Vector BF16 Conversions > vfncvtbf16.f.f.w", + "line_range": [ + 45, + 47 + ] + }, + { + "text": "Description:: Narrowing convert from FP32 to BF16.", + "section": "Preamble > `Zvfbfmin` Extension for Vector BF16 Conversions > vfncvtbf16.f.f.w", + "line_range": [ + 49, + 51 + ] + }, + { + "text": "Round according to the frm register.", + "section": "Preamble > `Zvfbfmin` Extension for Vector BF16 Conversions > vfncvtbf16.f.f.w", + "line_range": [ + 49, + 51 + ] + }, + { + "text": "This instruction is similar to `vfncvt.f.f.w` which converts a floating-point value in a 2*SEW-width format into an SEW-width format.", + "section": "Preamble > `Zvfbfmin` Extension for Vector BF16 Conversions > vfncvtbf16.f.f.w", + "line_range": [ + 53, + 55 + ] + }, + { + "text": "However, here the SEW-width format is limited to BF16.", + "section": "Preamble > `Zvfbfmin` Extension for Vector BF16 Conversions > vfncvtbf16.f.f.w", + "line_range": [ + 53, + 55 + ] + }, + { + "text": "Exceptions: Overflow, Underflow, Inexact, Invalid", + "section": "Preamble > `Zvfbfmin` Extension for Vector BF16 Conversions > vfncvtbf16.f.f.w", + "line_range": [ + 57, + 57 + ] + }, + { + "text": "Synopsis:: Vector convert BF16 to FP32", + "section": "Preamble > `Zvfbfmin` Extension for Vector BF16 Conversions > vfncvtbf16.f.f.w > vfwcvtbf16.f.f.v", + "line_range": [ + 64, + 65 + ] + }, + { + "text": "Mnemonic:: vfwcvtbf16.f.f.v vd, vs2, vm", + "section": "Preamble > `Zvfbfmin` Extension for Vector BF16 Conversions > vfncvtbf16.f.f.w > vfwcvtbf16.f.f.v", + "line_range": [ + 67, + 68 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ {bits: 7, name: '1010111', attr:['OP-V']}, {bits: 5, name: 'vd'}, {bits: 3, name: '001', attr:['OPFVV']}, {bits: 5, name: '01101', attr:['vfwcvtbf16']}, {bits: 5, name: 'vs2'}, {bits: 1, name: 'vm'}, {bits: 6, name: '010010', attr:['VFUNARY0']}, ]} ....", + "section": "Preamble > `Zvfbfmin` Extension for Vector BF16 Conversions > vfncvtbf16.f.f.w > vfwcvtbf16.f.f.v", + "line_range": [ + 70, + 82 + ] + }, + { + "text": "Reserved Encodings:: * `SEW` is any value other than 16", + "section": "Preamble > `Zvfbfmin` Extension for Vector BF16 Conversions > vfncvtbf16.f.f.w > vfwcvtbf16.f.f.v", + "line_range": [ + 84, + 86 + ] + }, + { + "text": "Arguments:: | |Register |Direction |EEW |Definition", + "section": "Preamble > `Zvfbfmin` Extension for Vector BF16 Conversions > vfncvtbf16.f.f.w > vfwcvtbf16.f.f.v", + "line_range": [ + 88, + 95 + ] + }, + { + "text": "| Vs2 | input | 16 | BF16 Source | Vd | output | 32 | FP32 Result |", + "section": "Preamble > `Zvfbfmin` Extension for Vector BF16 Conversions > vfncvtbf16.f.f.w > vfwcvtbf16.f.f.v", + "line_range": [ + 97, + 99 + ] + }, + { + "text": "Description:: Widening convert from BF16 to FP32.", + "section": "Preamble > `Zvfbfmin` Extension for Vector BF16 Conversions > vfncvtbf16.f.f.w > vfwcvtbf16.f.f.v", + "line_range": [ + 101, + 103 + ] + }, + { + "text": "This instruction is similar to `vfwcvt.f.f.v` which converts a floating-point value in an SEW-width format into a 2*SEW-width format.", + "section": "Preamble > `Zvfbfmin` Extension for Vector BF16 Conversions > vfncvtbf16.f.f.w > vfwcvtbf16.f.f.v", + "line_range": [ + 105, + 107 + ] + }, + { + "text": "However, here the SEW-width format is limited to BF16.", + "section": "Preamble > `Zvfbfmin` Extension for Vector BF16 Conversions > vfncvtbf16.f.f.w > vfwcvtbf16.f.f.v", + "line_range": [ + 105, + 107 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zvfbfwma.json b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zvfbfwma.json new file mode 100644 index 0000000000..997bb5c5a8 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__unpriv__zvfbfwma.json @@ -0,0 +1,158 @@ +{ + "source_file": "src/unpriv/zvfbfwma.adoc", + "total": 19, + "sentences": [ + { + "text": "This extension adds vector instructions that multiply BF16 numbers and accumulate into FP32.", + "section": "Preamble > `Zvfbfwma` Extension for Vector BF16 Widening Multiply-Accumulation", + "line_range": [ + 3, + 4 + ] + }, + { + "text": "This extension depends upon the `Zvfbfmin` extension and the `Zfbfmin` extension.", + "section": "Preamble > `Zvfbfwma` Extension for Vector BF16 Widening Multiply-Accumulation", + "line_range": [ + 6, + 6 + ] + }, + { + "text": "Synopsis:: Vector BF16 widening multiply-accumulate", + "section": "Preamble > `Zvfbfwma` Extension for Vector BF16 Widening Multiply-Accumulation > vfwmaccbf16", + "line_range": [ + 10, + 11 + ] + }, + { + "text": "Mnemonic:: vfwmaccbf16.vv vd, vs1, vs2, vm + vfwmaccbf16.vf vd, rs1, vs2, vm +", + "section": "Preamble > `Zvfbfwma` Extension for Vector BF16 Widening Multiply-Accumulation > vfwmaccbf16", + "line_range": [ + 13, + 15 + ] + }, + { + "text": "Encoding (Vector-Vector):: [wavedrom, , svg] .... {reg:[ {bits: 7, name: '1010111', attr:['OP-V']}, {bits: 5, name: 'vd'}, {bits: 3, name: '001', attr:['OPFVV']}, {bits: 5, name: 'vs1'}, {bits: 5, name: 'vs2'}, {bits: 1, name: 'vm'}, {bits: 6, name: '111011', attr:['vfwmaccbf16']}, ]} ....", + "section": "Preamble > `Zvfbfwma` Extension for Vector BF16 Widening Multiply-Accumulation > vfwmaccbf16", + "line_range": [ + 17, + 29 + ] + }, + { + "text": "Encoding (Vector-Scalar):: [wavedrom, , svg] .... {reg:[ {bits: 7, name: '1010111', attr:['OP-V']}, {bits: 5, name: 'vd'}, {bits: 3, name: '101', attr:['OPFVF']}, {bits: 5, name: 'rs1'}, {bits: 5, name: 'vs2'}, {bits: 1, name: 'vm'}, {bits: 6, name: '111011', attr:['vfwmaccbf16']}, ]} ....", + "section": "Preamble > `Zvfbfwma` Extension for Vector BF16 Widening Multiply-Accumulation > vfwmaccbf16", + "line_range": [ + 31, + 43 + ] + }, + { + "text": "Reserved Encodings:: * `SEW` is any value other than 16", + "section": "Preamble > `Zvfbfwma` Extension for Vector BF16 Widening Multiply-Accumulation > vfwmaccbf16", + "line_range": [ + 45, + 47 + ] + }, + { + "text": "Arguments:: | |Register |Direction |EEW |Definition", + "section": "Preamble > `Zvfbfwma` Extension for Vector BF16 Widening Multiply-Accumulation > vfwmaccbf16", + "line_range": [ + 49, + 56 + ] + }, + { + "text": "| Vd | input | 32 | FP32 Accumulate | Vs1/rs1 | input | 16 | BF16 Source | Vs2 | input | 16 | BF16 Source | Vd | output | 32 | FP32 Result |", + "section": "Preamble > `Zvfbfwma` Extension for Vector BF16 Widening Multiply-Accumulation > vfwmaccbf16", + "line_range": [ + 58, + 62 + ] + }, + { + "text": "This instruction performs a widening fused multiply-accumulate operation, where each pair of BF16 values are multiplied and their unrounded product is added to the corresponding FP32 accumulate value.", + "section": "Preamble > `Zvfbfwma` Extension for Vector BF16 Widening Multiply-Accumulation > vfwmaccbf16", + "line_range": [ + 66, + 70 + ] + }, + { + "text": "The sum is rounded according to the frm register.", + "section": "Preamble > `Zvfbfwma` Extension for Vector BF16 Widening Multiply-Accumulation > vfwmaccbf16", + "line_range": [ + 66, + 70 + ] + }, + { + "text": "In the vector-vector version, the BF16 elements are read from `vs1` and `vs2` and FP32 accumulate value is read from `vd`.", + "section": "Preamble > `Zvfbfwma` Extension for Vector BF16 Widening Multiply-Accumulation > vfwmaccbf16", + "line_range": [ + 72, + 75 + ] + }, + { + "text": "The FP32 result is written to the destination register `vd`.", + "section": "Preamble > `Zvfbfwma` Extension for Vector BF16 Widening Multiply-Accumulation > vfwmaccbf16", + "line_range": [ + 72, + 75 + ] + }, + { + "text": "The vector-scalar version is similar, but instead of reading elements from `vs1`, a scalar BF16 value is read from the FPU register `rs1`.", + "section": "Preamble > `Zvfbfwma` Extension for Vector BF16 Widening Multiply-Accumulation > vfwmaccbf16", + "line_range": [ + 77, + 79 + ] + }, + { + "text": "Exceptions: Overflow, Underflow, Inexact, Invalid", + "section": "Preamble > `Zvfbfwma` Extension for Vector BF16 Widening Multiply-Accumulation > vfwmaccbf16", + "line_range": [ + 81, + 81 + ] + }, + { + "text": "This `vfwmaccbf16.vv` instruction is equivalent to widening each of the BF16 inputs to FP32 and then performing an FMACC as shown in the following instruction sequence:", + "section": "Preamble > `Zvfbfwma` Extension for Vector BF16 Widening Multiply-Accumulation > vfwmaccbf16", + "line_range": [ + 85, + 87 + ] + }, + { + "text": "[source,asm] -- vfwcvtbf16.f.f.v T1, vs1, vm vfwcvtbf16.f.f.v T2, vs2, vm vfmacc.vv vd, T1, T2, vm --", + "section": "Preamble > `Zvfbfwma` Extension for Vector BF16 Widening Multiply-Accumulation > vfwmaccbf16", + "line_range": [ + 89, + 94 + ] + }, + { + "text": "Likewise, `vfwmaccbf16.vf` is equivalent to the following instruction sequence:", + "section": "Preamble > `Zvfbfwma` Extension for Vector BF16 Widening Multiply-Accumulation > vfwmaccbf16", + "line_range": [ + 96, + 96 + ] + }, + { + "text": "[source,asm] -- fcvt.s.bf16 T1, rs1 vfwcvtbf16.f.f.v T2, vs2, vm vfmacc.vf vd, T1, T2, vm --", + "section": "Preamble > `Zvfbfwma` Extension for Vector BF16 Widening Multiply-Accumulation > vfwmaccbf16", + "line_range": [ + 98, + 103 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__v-st-ext.json b/tools/llm-extraction/data/output/raw_chunks/src__v-st-ext.json new file mode 100644 index 0000000000..fd7ecfe7d8 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__v-st-ext.json @@ -0,0 +1,11526 @@ +{ + "source_file": "src/v-st-ext.adoc", + "total": 1440, + "sentences": [ + { + "text": "lists the standard vector extensions and which instructions and element widths are supported by each extension.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Introduction", + "line_range": [ + 5, + 7 + ] + }, + { + "text": "Each hart supporting a vector extension defines two parameters:", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Implementation-defined Constant Parameters", + "line_range": [ + 11, + 11 + ] + }, + { + "text": "The maximum size in bits of a vector element that any operation can produce or consume, ELEN {ge} 8, which must be a power of 2. .", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Implementation-defined Constant Parameters", + "line_range": [ + 13, + 15 + ] + }, + { + "text": "The number of bits in a single vector register, VLEN {ge} ELEN, which must be a power of 2, and must be no greater than 2^16^.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Implementation-defined Constant Parameters", + "line_range": [ + 13, + 15 + ] + }, + { + "text": "Standard vector extensions () and architecture profiles may set further constraints on ELEN and VLEN.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Implementation-defined Constant Parameters", + "line_range": [ + 17, + 18 + ] + }, + { + "text": "NOTE: Future extensions may allow ELEN {gt} VLEN by holding one element using bits from multiple vector registers, but this extension does not include this option.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Implementation-defined Constant Parameters", + "line_range": [ + 20, + 22 + ] + }, + { + "text": "NOTE: The upper limit on VLEN allows software to know that indices will fit into 16 bits (largest VLMAX of 65,536 occurs for LMUL=8 and SEW=8 with VLEN=65,536).", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Implementation-defined Constant Parameters", + "line_range": [ + 24, + 29 + ] + }, + { + "text": "Any future extension beyond 64Kib per vector register will require new configuration instructions such that software using the old configuration instructions does not see greater vector lengths.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Implementation-defined Constant Parameters", + "line_range": [ + 24, + 29 + ] + }, + { + "text": "The vector extension supports writing binary code that under certain constraints will execute portably on harts with different values for the VLEN parameter, provided the harts support the required element types and instructions.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Implementation-defined Constant Parameters", + "line_range": [ + 31, + 34 + ] + }, + { + "text": "NOTE: Code can be written that will expose differences in implementation parameters.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Implementation-defined Constant Parameters", + "line_range": [ + 36, + 37 + ] + }, + { + "text": "NOTE: In general, thread contexts with active vector state cannot be migrated during execution between harts that have any difference in VLEN or ELEN parameters.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Implementation-defined Constant Parameters", + "line_range": [ + 39, + 41 + ] + }, + { + "text": "The vector extension adds 32 vector registers, and seven unprivileged CSRs (`vstart`, `vxsat`, `vxrm`, `vcsr`, `vtype`, `vl`, `vlenb`) to a base scalar RISC-V ISA.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model", + "line_range": [ + 45, + 47 + ] + }, + { + "text": ".New vector CSRs [cols=\"2,2,2,10\"] | | Address | Privilege | Name | Description", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model", + "line_range": [ + 49, + 53 + ] + }, + { + "text": "| 0x008 | URW | vstart | Vector start element index | 0x009 | URW | vxsat | Fixed-Point Saturate Flag | 0x00A | URW | vxrm | Fixed-Point Rounding Mode | 0x00F | URW | vcsr | Vector control and status register | 0xC20 | URO | vl | Vector length | 0xC21 | URO | vtype | Vector data type register | 0xC22 | URO | vlenb | VLEN/8 (vector register length in bytes) |", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model", + "line_range": [ + 55, + 62 + ] + }, + { + "text": "NOTE: The four CSR numbers `0x00B`-`0x00E` are tentatively reserved for future vector CSRs, some of which may be mirrored into `vcsr`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model", + "line_range": [ + 64, + 65 + ] + }, + { + "text": "The vector extension adds 32 architectural vector registers, `v0`-`v31` to the base scalar RISC-V ISA.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Registers", + "line_range": [ + 69, + 71 + ] + }, + { + "text": "Each vector register has a fixed VLEN bits of state.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Registers", + "line_range": [ + 73, + 73 + ] + }, + { + "text": "A vector context status field, `VS`, is added to `mstatus[10:9]` and shadowed in `sstatus[10:9]`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Context Status in `mstatus`", + "line_range": [ + 77, + 80 + ] + }, + { + "text": "It is defined analogously to the floating-point context status field, `FS`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Context Status in `mstatus`", + "line_range": [ + 77, + 80 + ] + }, + { + "text": "Attempts to execute any vector instruction, or to access the vector CSRs, raise an illegal-instruction exception when `mstatus.VS` is set to Off.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Context Status in `mstatus`", + "line_range": [ + 82, + 85 + ] + }, + { + "text": "When `mstatus.VS` is set to Initial or Clean, executing any instruction that changes vector state, including the vector CSRs, will change `mstatus.VS` to Dirty.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Context Status in `mstatus`", + "line_range": [ + 87, + 92 + ] + }, + { + "text": "Implementations may also change `mstatus.VS` from Initial or Clean to Dirty at any time, even when there is no change in vector state.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Context Status in `mstatus`", + "line_range": [ + 87, + 92 + ] + }, + { + "text": "NOTE: Accurate setting of `mstatus.VS` is an optimization.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Context Status in `mstatus`", + "line_range": [ + 94, + 95 + ] + }, + { + "text": "Software will typically use VS to reduce context-swap overhead.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Context Status in `mstatus`", + "line_range": [ + 94, + 95 + ] + }, + { + "text": "If `mstatus.VS` is Dirty, `mstatus.SD` is 1; otherwise, `mstatus.SD` is set in accordance with existing specifications.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Context Status in `mstatus`", + "line_range": [ + 97, + 99 + ] + }, + { + "text": "Implementations may have a writable `misa.V` field.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Context Status in `mstatus`", + "line_range": [ + 101, + 103 + ] + }, + { + "text": "Analogous to the way in which the floating-point unit is handled, the `mstatus.VS` field may exist even if `misa.V` is clear.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Context Status in `mstatus`", + "line_range": [ + 101, + 103 + ] + }, + { + "text": "NOTE: Allowing `mstatus.VS` to exist when `misa.V` is clear, enables vector emulation and simplifies handling of `mstatus.VS` in systems with writable `misa.V`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Context Status in `mstatus`", + "line_range": [ + 105, + 107 + ] + }, + { + "text": "When the hypervisor extension is present, a vector context status field, `VS`, is added to `vsstatus[10:9]`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Context Status in `vsstatus`", + "line_range": [ + 111, + 114 + ] + }, + { + "text": "It is defined analogously to the floating-point context status field, `FS`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Context Status in `vsstatus`", + "line_range": [ + 111, + 114 + ] + }, + { + "text": "When V=1, both `vsstatus.VS` and `mstatus.VS` are in effect: attempts to execute any vector instruction, or to access the vector CSRs, raise an illegal-instruction exception when either field is set to Off.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Context Status in `vsstatus`", + "line_range": [ + 116, + 119 + ] + }, + { + "text": "When V=1 and neither `vsstatus.VS` nor `mstatus.VS` is set to Off, executing any instruction that changes vector state, including the vector CSRs, will change both `mstatus.VS` and `vsstatus.VS` to Dirty.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Context Status in `vsstatus`", + "line_range": [ + 121, + 125 + ] + }, + { + "text": "Implementations may also change `mstatus.VS` or `vsstatus.VS` from Initial or Clean to Dirty at any time, even when there is no change in vector state.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Context Status in `vsstatus`", + "line_range": [ + 121, + 125 + ] + }, + { + "text": "If `vsstatus.VS` is Dirty, `vsstatus.SD` is 1; otherwise, `vsstatus.SD` is set in accordance with existing specifications.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Context Status in `vsstatus`", + "line_range": [ + 127, + 129 + ] + }, + { + "text": "If `mstatus.VS` is Dirty, `mstatus.SD` is 1; otherwise, `mstatus.SD` is set in accordance with existing specifications.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Context Status in `vsstatus`", + "line_range": [ + 131, + 133 + ] + }, + { + "text": "For implementations with a writable `misa.V` field, the `vsstatus.VS` field may exist even if `misa.V` is clear.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Context Status in `vsstatus`", + "line_range": [ + 135, + 137 + ] + }, + { + "text": "The read-only XLEN-wide vector type CSR, `vtype` provides the default type used to interpret the contents of the vector register file, and can only be updated by `vset{i}vl{i}` instructions.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register", + "line_range": [ + 141, + 147 + ] + }, + { + "text": "The vector type determines the organization of elements in each vector register, and how multiple vector registers are grouped.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register", + "line_range": [ + 141, + 147 + ] + }, + { + "text": "The `vtype` register also indicates how masked-off elements and elements past the current vector length in a vector result are handled.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register", + "line_range": [ + 141, + 147 + ] + }, + { + "text": "NOTE: Allowing updates only via the `vset{i}vl{i}` instructions simplifies maintenance of the `vtype` register state.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register", + "line_range": [ + 149, + 150 + ] + }, + { + "text": "The `vtype` register has five fields, `vill`, `vma`, `vta`, `vsew[2:0]`, and `vlmul[2:0]`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register", + "line_range": [ + 152, + 155 + ] + }, + { + "text": "Bits `vtype[XLEN-2:8]` should be written with zero, and non-zero values in this field are reserved.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register", + "line_range": [ + 152, + 155 + ] + }, + { + "text": "NOTE: A small implementation supporting ELEN=32 requires only seven bits of state in `vtype`: two bits for `ma` and `ta`, two bits for `vsew[1:0]` and three bits for `vlmul[2:0]`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register", + "line_range": [ + 159, + 160 + ] + }, + { + "text": "The illegal value represented by `vill` can be internally encoded using the illegal 64-bit combination in `vsew[1:0]` without requiring an additional storage bit to hold `vill`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register", + "line_range": [ + 159, + 160 + ] + }, + { + "text": "NOTE: Further standard and custom vector extensions may extend these fields to support a greater variety of data types.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register", + "line_range": [ + 162, + 163 + ] + }, + { + "text": "NOTE: The primary motivation for the `vtype` CSR is to allow the vector instruction set to fit into a 32-bit instruction encoding space. A separate `vset{i}vl{i}` instruction can be used to set `vl` and/or `vtype` fields before execution of a vector instruction, and implementations may choose to fuse these two instructions into a single internal vector microop.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register", + "line_range": [ + 165, + 175 + ] + }, + { + "text": "In many cases, the `vl` and `vtype` values can be reused across multiple instructions, reducing the static and dynamic instruction overhead from the `vset{i}vl{i}` instructions.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register", + "line_range": [ + 165, + 175 + ] + }, + { + "text": "It is anticipated that a future extended 64-bit instruction encoding would allow these fields to be specified statically in the instruction encoding.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register", + "line_range": [ + 165, + 175 + ] + }, + { + "text": "The value in `vsew` sets the dynamic selected element width (SEW).", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Selected Element Width (`vsew[2:0]`)", + "line_range": [ + 180, + 183 + ] + }, + { + "text": "By default, a vector register is viewed as being divided into VLEN/SEW elements.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Selected Element Width (`vsew[2:0]`)", + "line_range": [ + 180, + 183 + ] + }, + { + "text": ".vsew[2:0] (selected element width) encoding [cols=\"1,1,1,1\"] | 3+| vsew[2:0] | SEW", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Selected Element Width (`vsew[2:0]`)", + "line_range": [ + 185, + 189 + ] + }, + { + "text": "| 0 | 0 | 0 | 8 | 0 | 0 | 1 | 16 | 0 | 1 | 0 | 32 | 0 | 1 | 1 | 64 | 1 | X | X | Reserved |", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Selected Element Width (`vsew[2:0]`)", + "line_range": [ + 191, + 196 + ] + }, + { + "text": "NOTE: While it is anticipated the larger `vsew[2:0]` encodings (`100`-`111`) will be used to encode larger SEW, the encodings are formally reserved at this point.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Selected Element Width (`vsew[2:0]`)", + "line_range": [ + 198, + 200 + ] + }, + { + "text": ".Example VLEN = 128 bits [cols=\">,>\"] | | SEW | Elements per vector register", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Selected Element Width (`vsew[2:0]`)", + "line_range": [ + 202, + 206 + ] + }, + { + "text": "| 64 | 2 | 32 | 4 | 16 | 8 | 8 | 16 |", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Selected Element Width (`vsew[2:0]`)", + "line_range": [ + 208, + 212 + ] + }, + { + "text": "The supported element width may vary with LMUL.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Selected Element Width (`vsew[2:0]`)", + "line_range": [ + 214, + 214 + ] + }, + { + "text": "NOTE: The current set of standard vector extensions do not vary supported element width with LMUL.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Selected Element Width (`vsew[2:0]`)", + "line_range": [ + 216, + 225 + ] + }, + { + "text": "Some future extensions may support larger SEWs only when bits from multiple vector registers are combined using LMUL.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Selected Element Width (`vsew[2:0]`)", + "line_range": [ + 216, + 225 + ] + }, + { + "text": "In this case, software that relies on large SEW should attempt to use the largest LMUL, and hence the fewest vector register groups, to increase the number of implementations on which the code will run.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Selected Element Width (`vsew[2:0]`)", + "line_range": [ + 216, + 225 + ] + }, + { + "text": "The `vill` bit in `vtype` should be checked after setting `vtype` to see if the configuration is supported, and an alternate code path should be provided if it is not.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Selected Element Width (`vsew[2:0]`)", + "line_range": [ + 216, + 225 + ] + }, + { + "text": "Alternatively, a profile can mandate the minimum SEW at each LMUL setting.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Selected Element Width (`vsew[2:0]`)", + "line_range": [ + 216, + 225 + ] + }, + { + "text": "Multiple vector registers can be grouped together, so that a single vector instruction can operate on multiple vector registers.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)", + "line_range": [ + 229, + 240 + ] + }, + { + "text": "The term vector register group is used herein to refer to one or more vector registers used as a single operand to a vector instruction.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)", + "line_range": [ + 229, + 240 + ] + }, + { + "text": "Vector register groups can be used to provide greater execution efficiency for longer application vectors, but the main reason for their inclusion is to allow double-width or larger elements to be operated on with the same vector length as single-width elements.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)", + "line_range": [ + 229, + 240 + ] + }, + { + "text": "The vector length multiplier, LMUL, when greater than 1, represents the default number of vector registers that are combined to form a vector register group.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)", + "line_range": [ + 229, + 240 + ] + }, + { + "text": "Implementations must support LMUL integer values of 1, 2, 4, and 8.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)", + "line_range": [ + 229, + 240 + ] + }, + { + "text": "NOTE: The vector architecture includes instructions that take multiple source and destination vector operands with different element widths, but the same number of elements.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)", + "line_range": [ + 242, + 248 + ] + }, + { + "text": "The effective LMUL (EMUL) of each vector operand is determined by the number of registers required to hold the elements.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)", + "line_range": [ + 242, + 248 + ] + }, + { + "text": "For example, for a widening add operation, such as add 32-bit values to produce 64-bit results, a double-width result requires twice the LMUL of the single-width inputs.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)", + "line_range": [ + 242, + 248 + ] + }, + { + "text": "LMUL can also be a fractional value, reducing the number of bits used in a single vector register.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)", + "line_range": [ + 250, + 253 + ] + }, + { + "text": "Fractional LMUL is used to increase the number of effective usable vector register groups when operating on mixed-width values.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)", + "line_range": [ + 250, + 253 + ] + }, + { + "text": "NOTE: With only integer LMUL values, a loop operating on a range of sizes would have to allocate at least one whole vector register (LMUL=1) for the narrowest data type and then would consume multiple vector registers (LMUL>1) to form a vector register group for each wider vector operand.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)", + "line_range": [ + 255, + 267 + ] + }, + { + "text": "This can limit the number of vector register groups available.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)", + "line_range": [ + 255, + 267 + ] + }, + { + "text": "With fractional LMUL, the widest values need occupy only a single vector register while narrower values can occupy a fraction of a single vector register, allowing all 32 architectural vector register names to be used for different values in a vector loop even when handling mixed-width values.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)", + "line_range": [ + 255, + 267 + ] + }, + { + "text": "Fractional LMUL implies portions of vector registers are unused, but in some cases, having more shorter register-resident vectors improves efficiency relative to fewer longer register-resident vectors.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)", + "line_range": [ + 255, + 267 + ] + }, + { + "text": "Implementations must provide fractional LMUL settings that allow the narrowest supported type to occupy a fraction of a vector register corresponding to the ratio of the narrowest supported type's width to that of the largest supported type's width.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)", + "line_range": [ + 269, + 279 + ] + }, + { + "text": "In general, the requirement is to support LMUL {ge} SEW~MIN~/ELEN, where SEW~MIN~ is the narrowest supported SEW value and ELEN is the widest supported SEW value.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)", + "line_range": [ + 269, + 279 + ] + }, + { + "text": "In the standard extensions, SEW~MIN~=8.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)", + "line_range": [ + 269, + 279 + ] + }, + { + "text": "For standard vector extensions with ELEN=32, fractional LMULs of 1/2 and 1/4 must be supported.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)", + "line_range": [ + 269, + 279 + ] + }, + { + "text": "For standard vector extensions with ELEN=64, fractional LMULs of 1/2, 1/4, and 1/8 must be supported.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)", + "line_range": [ + 269, + 279 + ] + }, + { + "text": "When LMUL < SEW~MIN~/ELEN, there is no guarantee an implementation would have enough bits in the fractional vector register to store at least one element, as VLEN=ELEN is a valid implementation choice.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)", + "line_range": [ + 281, + 286 + ] + }, + { + "text": "For example, with VLEN=ELEN=32, and SEW~MIN~=8, an LMUL of 1/8 would only provide four bits of storage in a vector register.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)", + "line_range": [ + 281, + 286 + ] + }, + { + "text": "For a given supported fractional LMUL setting, implementations must support SEW settings between SEW~MIN~ and LMUL * ELEN, inclusive.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)", + "line_range": [ + 288, + 290 + ] + }, + { + "text": "The use of `vtype` encodings with LMUL < SEW~MIN~/ELEN is reserved, but implementations can set `vill` if they do not support these configurations.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)", + "line_range": [ + 292, + 295 + ] + }, + { + "text": "NOTE: Requiring all implementations to set `vill` in this case would prohibit future use of this case in an extension, so to allow for a future definition of LMUL \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)", + "line_range": [ + 297, + 300 + ] + }, + { + "text": "NOTE: It is recommended that assemblers provide a warning (not an error) if a `vsetvli` instruction attempts to write an LMUL < SEW~MIN~/ELEN.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)", + "line_range": [ + 302, + 303 + ] + }, + { + "text": "LMUL is set by the signed `vlmul` field in `vtype` (i.e., LMUL = 2^`vlmul[2:0]`^).", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)", + "line_range": [ + 305, + 307 + ] + }, + { + "text": "The derived value VLMAX = LMUL*VLEN/SEW represents the maximum number of elements that can be operated on with a single vector instruction given the current SEW and LMUL settings as shown in the table below.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)", + "line_range": [ + 309, + 312 + ] + }, + { + "text": "[cols=\"1,1,1,2,2,5,5\"] | 3+| vlmul[2:0] | LMUL | groups | VLMAX | Registers grouped with register n", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)", + "line_range": [ + 314, + 317 + ] + }, + { + "text": "| 1 | 0 | 0 | - | - | - | reserved | 1 | 0 | 1 | 1/8| 32 | VLEN/SEW/8 | `v` n (single register in group) | 1 | 1 | 0 | 1/4| 32 | VLEN/SEW/4 | `v` n (single register in group) | 1 | 1 | 1 | 1/2| 32 | VLEN/SEW/2 | `v` n (single register in group) | 0 | 0 | 0 | 1 | 32 | VLEN/SEW | `v` n (single register in group) | 0 | 0 | 1 | 2 | 16 | 2*VLEN/SEW | `v` n, `v` n+1 | 0 | 1 | 0 | 4 | 8 | 4*VLEN/SEW | `v` n, ..., `v` n+3 | 0 | 1 | 1 | 8 | 4 | 8*VLEN/SEW | `v` n, ..., `v` n+7 |", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)", + "line_range": [ + 319, + 327 + ] + }, + { + "text": "When LMUL=2, the vector register group contains vector register `v` n and vector register `v` n+1, providing twice the vector length in bits.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)", + "line_range": [ + 329, + 332 + ] + }, + { + "text": "Instructions specifying an LMUL=2 vector register group with an odd-numbered vector register are reserved.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)", + "line_range": [ + 329, + 332 + ] + }, + { + "text": "When LMUL=4, the vector register group contains four vector registers, and instructions specifying an LMUL=4 vector register group using vector register numbers that are not multiples of four are reserved.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)", + "line_range": [ + 334, + 336 + ] + }, + { + "text": "When LMUL=8, the vector register group contains eight vector registers, and instructions specifying an LMUL=8 vector register group using register numbers that are not multiples of eight are reserved.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)", + "line_range": [ + 338, + 340 + ] + }, + { + "text": "Mask registers are always contained in a single vector register, regardless of LMUL.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Register Grouping (`vlmul[2:0]`)", + "line_range": [ + 342, + 344 + ] + }, + { + "text": "These two bits modify the behavior of destination tail elements and destination inactive masked-off elements respectively during the execution of vector instructions.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma`", + "line_range": [ + 350, + 355 + ] + }, + { + "text": "The tail and inactive sets contain element positions that are not receiving new results during a vector operation,", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma`", + "line_range": [ + 350, + 355 + ] + }, + { + "text": "All systems must support all four options:", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma`", + "line_range": [ + 357, + 358 + ] + }, + { + "text": "[cols=\"1,1,3,3\"] | | `vta` | `vma` | Tail Elements | Inactive Elements", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma`", + "line_range": [ + 360, + 363 + ] + }, + { + "text": "| 0 | 0 | undisturbed | undisturbed | 0 | 1 | undisturbed | agnostic | 1 | 0 | agnostic | undisturbed | 1 | 1 | agnostic | agnostic |", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma`", + "line_range": [ + 365, + 369 + ] + }, + { + "text": "Mask destination tail elements are always treated as tail-agnostic, regardless of the setting of `vta`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma`", + "line_range": [ + 371, + 373 + ] + }, + { + "text": "When a set is marked undisturbed, the corresponding set of destination elements in a vector register group retain the value they previously held.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma`", + "line_range": [ + 375, + 378 + ] + }, + { + "text": "When a set is marked agnostic, the corresponding set of destination elements in any vector destination operand can either retain the value they previously held, or are overwritten with 1s.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma`", + "line_range": [ + 380, + 387 + ] + }, + { + "text": "Within a single vector instruction, each destination element can be either left undisturbed or overwritten with 1s, in any combination, and the pattern of undisturbed or overwritten with 1s is not required to be deterministic when the instruction is executed with the same inputs.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma`", + "line_range": [ + 380, + 387 + ] + }, + { + "text": "NOTE: The agnostic policy was added to accommodate machines with vector register renaming.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma`", + "line_range": [ + 389, + 394 + ] + }, + { + "text": "With an undisturbed policy, all elements would have to be read from the old physical destination vector register to be copied into the new physical destination vector register.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma`", + "line_range": [ + 389, + 394 + ] + }, + { + "text": "This causes an inefficiency when these inactive or tail values are not required for subsequent calculations.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma`", + "line_range": [ + 389, + 394 + ] + }, + { + "text": "NOTE: The value of all 1s instead of all 0s was chosen for the overwrite value to discourage software developers from depending on the value written.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma`", + "line_range": [ + 396, + 398 + ] + }, + { + "text": "NOTE: A simple in-order implementation can ignore the settings and simply execute all vector instructions using the undisturbed policy.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma`", + "line_range": [ + 400, + 403 + ] + }, + { + "text": "The `vta` and `vma` state bits must still be provided in `vtype` for compatibility and to support thread migration.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma`", + "line_range": [ + 400, + 403 + ] + }, + { + "text": "NOTE: An out-of-order implementation can choose to implement tail-agnostic + mask-agnostic using tail-agnostic + mask-undisturbed to reduce implementation complexity.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma`", + "line_range": [ + 405, + 407 + ] + }, + { + "text": "NOTE: The definition of agnostic result policy is left loose to accommodate migrating application threads between harts on a small in-order core (which probably leaves agnostic regions undisturbed) and harts on a larger out-of-order core with register renaming (which probably overwrites agnostic elements with 1s).", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma`", + "line_range": [ + 409, + 419 + ] + }, + { + "text": "As it might be necessary to restart in the middle, we allow arbitrary mixing of agnostic policies within a single vector instruction.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma`", + "line_range": [ + 409, + 419 + ] + }, + { + "text": "This allowed mixing of policies also enables implementations that might change policies for different granules of a vector register, for example, using undisturbed within a granule that is actively operated on but renaming to all 1s for granules in the tail.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma`", + "line_range": [ + 409, + 419 + ] + }, + { + "text": "In addition, except for mask load instructions, any element in the tail of a mask result can also be written with the value the mask-producing operation would have calculated with `vl`=VLMAX.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma`", + "line_range": [ + 421, + 429 + ] + }, + { + "text": "Furthermore, for mask-logical instructions and `vmsbf.m`, `vmsif.m`, `vmsof.m` mask-manipulation instructions, any element in the tail of the result can be written with the value the mask-producing operation would have calculated with `vl`=VLEN, SEW=8, and LMUL=8 (i.e., all bits of the mask register can be overwritten).", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma`", + "line_range": [ + 421, + 429 + ] + }, + { + "text": "NOTE: Mask tails are always treated as agnostic to reduce complexity of managing mask data, which can be written at bit granularity.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma`", + "line_range": [ + 431, + 438 + ] + }, + { + "text": "There appears to be little software need to support tail-undisturbed for mask register values.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma`", + "line_range": [ + 431, + 438 + ] + }, + { + "text": "Allowing mask-generating instructions to write back the result of the instruction avoids the need for logic to mask out the tail, except mask loads cannot write memory values to destination mask tails as this would imply accessing memory past software intent.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma`", + "line_range": [ + 431, + 438 + ] + }, + { + "text": "The assembly syntax adds two mandatory flags to the `vsetvli` instruction:", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma`", + "line_range": [ + 440, + 440 + ] + }, + { + "text": "---- ta Tail agnostic tu Tail undisturbed ma Mask agnostic mu Mask undisturbed", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma`", + "line_range": [ + 442, + 446 + ] + }, + { + "text": "vsetvli t0, a0, e32, m4, ta, ma Tail agnostic, mask agnostic vsetvli t0, a0, e32, m4, tu, ma Tail undisturbed, mask agnostic vsetvli t0, a0, e32, m4, ta, mu Tail agnostic, mask undisturbed vsetvli t0, a0, e32, m4, tu, mu Tail undisturbed, mask undisturbed ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma`", + "line_range": [ + 448, + 452 + ] + }, + { + "text": "NOTE: Prior to v0.9, when these flags were not specified on a `vsetvli`, they defaulted to mask-undisturbed/tail-undisturbed.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma`", + "line_range": [ + 454, + 461 + ] + }, + { + "text": "The use of `vsetvli` without these flags is deprecated, however, and specifying a flag setting is now mandatory.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma`", + "line_range": [ + 454, + 461 + ] + }, + { + "text": "The default should perhaps be tail-agnostic/mask-agnostic, so software has to specify when it cares about the non-participating elements, but given the historical meaning of the instruction prior to introduction of these flags, it was decided to always require them in future assembly code.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Tail Agnostic and Vector Mask Agnostic `vta` and `vma`", + "line_range": [ + 454, + 461 + ] + }, + { + "text": "The `vill` bit is used to encode that a previous `vset{i}vl{i}` instruction attempted to write an unsupported value to `vtype`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Type Illegal (`vill`)", + "line_range": [ + 465, + 466 + ] + }, + { + "text": "NOTE: The `vill` bit is held in bit XLEN-1 of the CSR to support checking for illegal values with a branch on the sign bit.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Type Illegal (`vill`)", + "line_range": [ + 468, + 469 + ] + }, + { + "text": "If the `vill` bit is set, then any attempt to execute a vector instruction that depends upon `vtype` will raise an illegal-instruction exception.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Type Illegal (`vill`)", + "line_range": [ + 471, + 473 + ] + }, + { + "text": "NOTE: `vset{i}vl{i}` and whole register loads and stores do not depend upon `vtype`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Type Illegal (`vill`)", + "line_range": [ + 475, + 476 + ] + }, + { + "text": "When the `vill` bit is set, the other XLEN-1 bits in `vtype` shall be zero.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Type (`vtype`) Register > Vector Type Illegal (`vill`)", + "line_range": [ + 478, + 479 + ] + }, + { + "text": "The XLEN-bit-wide read-only `vl` CSR can only be updated by the `vset{i}vl{i}` instructions, and the fault-only-first vector load instruction variants.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Length (`vl`) Register", + "line_range": [ + 483, + 486 + ] + }, + { + "text": "The `vl` register holds an unsigned integer specifying the number of elements to be updated with results from a vector instruction, as further detailed in .", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Length (`vl`) Register", + "line_range": [ + 488, + 491 + ] + }, + { + "text": "NOTE: The number of bits implemented in `vl` depends on the implementation's maximum vector length of the smallest supported type.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Length (`vl`) Register", + "line_range": [ + 493, + 497 + ] + }, + { + "text": "The smallest vector implementation with VLEN=32 and supporting SEW=8 would need at least six bits in `vl` to hold the values 0-32 (VLEN=32, with LMUL=8 and SEW=8, yields VLMAX=32).", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Length (`vl`) Register", + "line_range": [ + 493, + 497 + ] + }, + { + "text": "The XLEN-bit-wide read-only CSR `vlenb` holds the value VLEN/8, i.e., the vector register length in bytes.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Byte Length (`vlenb`) Register", + "line_range": [ + 501, + 503 + ] + }, + { + "text": "NOTE: The value in `vlenb` is a design-time constant in any implementation.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Byte Length (`vlenb`) Register", + "line_range": [ + 505, + 506 + ] + }, + { + "text": "NOTE: Without this CSR, several instructions are needed to calculate VLEN in bytes, and the code has to disturb current `vl` and `vtype` settings which require them to be saved and restored.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Byte Length (`vlenb`) Register", + "line_range": [ + 508, + 510 + ] + }, + { + "text": "The XLEN-bit-wide read-write `vstart` CSR specifies the index of the first element to be executed by a vector instruction, as described in .", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Start Index (`vstart`) Register", + "line_range": [ + 514, + 517 + ] + }, + { + "text": "Normally, `vstart` is only written by hardware on a trap on a vector instruction, with the `vstart` value representing the element on which the trap was taken (either a synchronous exception or an asynchronous interrupt), and at which execution should resume after a resumable trap is handled.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Start Index (`vstart`) Register", + "line_range": [ + 519, + 523 + ] + }, + { + "text": "All vector instructions are defined to begin execution with the element number given in the `vstart` CSR, leaving earlier elements in the destination vector undisturbed, and to reset the `vstart` CSR to zero at the end of execution.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Start Index (`vstart`) Register", + "line_range": [ + 525, + 528 + ] + }, + { + "text": "NOTE: All vector instructions, including `vset{i}vl{i}`, reset the `vstart` CSR to zero.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Start Index (`vstart`) Register", + "line_range": [ + 530, + 531 + ] + }, + { + "text": "`vstart` is not modified by vector instructions that raise illegal-instruction exceptions.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Start Index (`vstart`) Register", + "line_range": [ + 533, + 535 + ] + }, + { + "text": "The `vstart` CSR is defined to have only enough writable bits to hold the largest element index (one less than the maximum VLMAX).", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Start Index (`vstart`) Register", + "line_range": [ + 537, + 539 + ] + }, + { + "text": "NOTE: The maximum vector length is obtained with the largest LMUL setting (8) and the smallest SEW setting (8), so VLMAXmax = 8*VLEN/8 = VLEN.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Start Index (`vstart`) Register", + "line_range": [ + 541, + 543 + ] + }, + { + "text": "For example, for VLEN=256, `vstart` would have 8 bits to represent indices from 0 through 255.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Start Index (`vstart`) Register", + "line_range": [ + 541, + 543 + ] + }, + { + "text": "The use of `vstart` values greater than the largest element index for the current `vtype` setting is reserved.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Start Index (`vstart`) Register", + "line_range": [ + 545, + 547 + ] + }, + { + "text": "NOTE: It is recommended that implementations trap if `vstart` is out of bounds.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Start Index (`vstart`) Register", + "line_range": [ + 549, + 551 + ] + }, + { + "text": "It is not required to trap, as a possible future use of upper `vstart` bits is to store imprecise trap information.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Start Index (`vstart`) Register", + "line_range": [ + 549, + 551 + ] + }, + { + "text": "The `vstart` CSR is writable by unprivileged code, but non-zero `vstart` values may cause vector instructions to run substantially slower on some implementations, so `vstart` should not be used by application programmers. A few vector instructions cannot be executed with a non-zero `vstart` value and will raise an illegal-instruction exception as defined below.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Start Index (`vstart`) Register", + "line_range": [ + 553, + 558 + ] + }, + { + "text": "NOTE: Making `vstart` visible to unprivileged code supports user-level threading libraries.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Start Index (`vstart`) Register", + "line_range": [ + 560, + 561 + ] + }, + { + "text": "Implementations are permitted to raise illegal-instruction exceptions when attempting to execute a vector instruction with a value of `vstart` that the implementation can never produce when executing that same instruction with the same `vtype` setting.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Start Index (`vstart`) Register", + "line_range": [ + 563, + 567 + ] + }, + { + "text": "NOTE: For example, some implementations will never take interrupts during execution of a vector arithmetic instruction, instead waiting until the instruction completes to take the interrupt.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Start Index (`vstart`) Register", + "line_range": [ + 569, + 573 + ] + }, + { + "text": "Such implementations are permitted to raise an illegal-instruction exception when attempting to execute a vector arithmetic instruction when `vstart` is nonzero.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Start Index (`vstart`) Register", + "line_range": [ + 569, + 573 + ] + }, + { + "text": "When migrating a software thread between two harts with different microarchitectures, the `vstart` value might not be supported by the new hart microarchitecture.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Start Index (`vstart`) Register", + "line_range": [ + 575, + 581 + ] + }, + { + "text": "The runtime on the receiving hart might then have to emulate instruction execution up to the next supported `vstart` element position.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Start Index (`vstart`) Register", + "line_range": [ + 575, + 581 + ] + }, + { + "text": "Alternatively, migration events can be constrained to only occur at mutually supported `vstart` locations.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Start Index (`vstart`) Register", + "line_range": [ + 575, + 581 + ] + }, + { + "text": "The vector fixed-point rounding-mode register holds a two-bit read-write rounding-mode field in the least-significant bits (`vxrm[1:0]`).", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Fixed-Point Rounding Mode (`vxrm`) Register", + "line_range": [ + 584, + 588 + ] + }, + { + "text": "The upper bits, `vxrm[XLEN-1:2]`, should be written as zeros.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Fixed-Point Rounding Mode (`vxrm`) Register", + "line_range": [ + 584, + 588 + ] + }, + { + "text": "The vector fixed-point rounding-mode is given a separate CSR address to allow independent access, but is also reflected as a field in `vcsr`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Fixed-Point Rounding Mode (`vxrm`) Register", + "line_range": [ + 590, + 593 + ] + }, + { + "text": "NOTE: A new rounding mode can be set while saving the original rounding mode using a single `csrwi` instruction.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Fixed-Point Rounding Mode (`vxrm`) Register", + "line_range": [ + 595, + 596 + ] + }, + { + "text": "The fixed-point rounding algorithm is specified as follows.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Fixed-Point Rounding Mode (`vxrm`) Register", + "line_range": [ + 598, + 603 + ] + }, + { + "text": "Suppose the pre-rounding result is `v`, and `d` bits of that result are to be rounded off.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Fixed-Point Rounding Mode (`vxrm`) Register", + "line_range": [ + 598, + 603 + ] + }, + { + "text": "Then the rounded result is `(v >> d) + r`, where `r` depends on the rounding mode as specified in the following table.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Fixed-Point Rounding Mode (`vxrm`) Register", + "line_range": [ + 598, + 603 + ] + }, + { + "text": ".vxrm encoding //[cols=\"1,1,4,10,5\"] | 2+| `vxrm[1:0]` | Abbreviation | Rounding Mode | Rounding increment, `r`", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Fixed-Point Rounding Mode (`vxrm`) Register", + "line_range": [ + 605, + 609 + ] + }, + { + "text": "| 0 | 0 | rnu | round-to-nearest-up (add +0.5 LSB) | `v[d-1]` | 0 | 1 | rne | round-to-nearest-even | `v[d-1] & (v[d-2:0]{ne}0 \\| v[d])` | 1 | 0 | rdn | round-down | `0` | 1 | 1 | rod | round-to-odd (OR bits into LSB, aka \"jam\") | `!v[d] & v[d-1:0]{ne}0` |", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Fixed-Point Rounding Mode (`vxrm`) Register", + "line_range": [ + 611, + 615 + ] + }, + { + "text": "The rounding functions: ---- roundoffunsigned(v, d) = (unsigned(v) >> d) + r roundoffsigned(v, d) = (signed(v) >> d) + r ---- are used to represent this operation in the instruction descriptions below.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Fixed-Point Rounding Mode (`vxrm`) Register", + "line_range": [ + 617, + 622 + ] + }, + { + "text": "The `vxsat` CSR has a single read-write least-significant bit (`vxsat[0]`) that indicates if a fixed-point instruction has had to saturate an output value to fit into a destination format.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Fixed-Point Saturation Flag (`vxsat`)", + "line_range": [ + 626, + 630 + ] + }, + { + "text": "Bits `vxsat[XLEN-1:1]` should be written as zeros.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Fixed-Point Saturation Flag (`vxsat`)", + "line_range": [ + 626, + 630 + ] + }, + { + "text": "The `vxsat` bit is mirrored in `vcsr`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Fixed-Point Saturation Flag (`vxsat`)", + "line_range": [ + 632, + 633 + ] + }, + { + "text": "The `vxrm` and `vxsat` separate CSRs can also be accessed via fields in the XLEN-bit-wide vector control and status CSR, `vcsr`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Control and Status (`vcsr`) Register", + "line_range": [ + 637, + 639 + ] + }, + { + "text": ".vcsr layout [cols=\">2,4,10\"] | | Bits | Name | Description", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Control and Status (`vcsr`) Register", + "line_range": [ + 641, + 645 + ] + }, + { + "text": "| XLEN-1:3 | | Reserved | 2:1 | vxrm[1:0] | Fixed-point rounding mode | 0 | vxsat | Fixed-point accrued saturation flag |", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > Vector Control and Status (`vcsr`) Register", + "line_range": [ + 647, + 650 + ] + }, + { + "text": "The vector extension must have a consistent state at reset.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > State of Vector Extension at Reset", + "line_range": [ + 654, + 656 + ] + }, + { + "text": "In particular, `vtype` and `vl` must have values that can be read and then restored with a single `vsetvl` instruction.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > State of Vector Extension at Reset", + "line_range": [ + 654, + 656 + ] + }, + { + "text": "NOTE: It is recommended that at reset, `vtype.vill` is set, the remaining bits in `vtype` are zero, and `vl` is set to zero.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > State of Vector Extension at Reset", + "line_range": [ + 658, + 659 + ] + }, + { + "text": "The `vstart`, `vxrm`, `vxsat` CSRs can have arbitrary values at reset.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > State of Vector Extension at Reset", + "line_range": [ + 661, + 661 + ] + }, + { + "text": "NOTE: Most uses of the vector unit will require an initial `vset{i}vl{i}`, which will reset `vstart`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > State of Vector Extension at Reset", + "line_range": [ + 663, + 665 + ] + }, + { + "text": "The `vxrm` and `vxsat` fields should be reset explicitly in software before use.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > State of Vector Extension at Reset", + "line_range": [ + 663, + 665 + ] + }, + { + "text": "The vector registers can have arbitrary values at reset.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Extension Programmer's Model > State of Vector Extension at Reset", + "line_range": [ + 667, + 667 + ] + }, + { + "text": "The following diagrams illustrate how different width elements are packed into the bytes of a vector register depending on the current SEW and LMUL settings, as well as implementation VLEN.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State", + "line_range": [ + 671, + 675 + ] + }, + { + "text": "Elements are packed into each vector register with the least-significant byte in the lowest-numbered bits.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State", + "line_range": [ + 671, + 675 + ] + }, + { + "text": "The mapping was chosen to provide the simplest and most portable model for software, but might appear to incur large wiring cost for wider vector datapaths on certain operations.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State", + "line_range": [ + 677, + 682 + ] + }, + { + "text": "The vector instruction set was expressly designed to support implementations that internally rearrange vector data for different SEW to reduce datapath wiring costs, while externally preserving the simple software model.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State", + "line_range": [ + 677, + 682 + ] + }, + { + "text": "NOTE: For example, microarchitectures can track the EEW with which a vector register was written, and then insert additional scrambling operations to rearrange data if the register is accessed with a different EEW.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State", + "line_range": [ + 684, + 687 + ] + }, + { + "text": "When LMUL=1, elements are simply packed in order from the least-significant to most-significant bits of the vector register.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping for LMUL = 1", + "line_range": [ + 691, + 693 + ] + }, + { + "text": "NOTE: To increase readability, vector register layouts are drawn with bytes ordered from right to left with increasing byte address.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping for LMUL = 1", + "line_range": [ + 695, + 699 + ] + }, + { + "text": "Bits within an element are numbered in a little-endian format with increasing bit index from right to left corresponding to increasing magnitude.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping for LMUL = 1", + "line_range": [ + 695, + 699 + ] + }, + { + "text": "The element index is given in hexadecimal and is shown placed at the least-significant byte of the stored element.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping for LMUL = 1", + "line_range": [ + 704, + 705 + ] + }, + { + "text": "SEW=8b 3 2 1 0 SEW=16b 1 0 SEW=32b 0", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping for LMUL = 1", + "line_range": [ + 711, + 713 + ] + }, + { + "text": "SEW=8b 7 6 5 4 3 2 1 0 SEW=16b 3 2 1 0 SEW=32b 1 0 SEW=64b 0", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping for LMUL = 1", + "line_range": [ + 719, + 722 + ] + }, + { + "text": "Byte F E D C B A 9 8 7 6 5 4 3 2 1 0", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping for LMUL = 1", + "line_range": [ + 726, + 726 + ] + }, + { + "text": "SEW=8b F E D C B A 9 8 7 6 5 4 3 2 1 0 SEW=16b 7 6 5 4 3 2 1 0 SEW=32b 3 2 1 0 SEW=64b 1 0", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping for LMUL = 1", + "line_range": [ + 728, + 731 + ] + }, + { + "text": "Byte 1F1E1D1C1B1A19181716151413121110 F E D C B A 9 8 7 6 5 4 3 2 1 0", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping for LMUL = 1", + "line_range": [ + 735, + 735 + ] + }, + { + "text": "SEW=8b 1F1E1D1C1B1A19181716151413121110 F E D C B A 9 8 7 6 5 4 3 2 1 0 SEW=16b F E D C B A 9 8 7 6 5 4 3 2 1 0 SEW=32b 7 6 5 4 3 2 1 0 SEW=64b 3 2 1 0 ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping for LMUL = 1", + "line_range": [ + 737, + 741 + ] + }, + { + "text": "When LMUL < 1, only the first LMUL*VLEN/SEW elements in the vector register are used.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping for LMUL < 1", + "line_range": [ + 746, + 749 + ] + }, + { + "text": "The remaining space in the vector register is treated as part of the tail, and hence must obey the vta setting.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping for LMUL < 1", + "line_range": [ + 746, + 749 + ] + }, + { + "text": "---- Example, VLEN=128b, LMUL=1/4", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping for LMUL < 1", + "line_range": [ + 751, + 752 + ] + }, + { + "text": "Byte F E D C B A 9 8 7 6 5 4 3 2 1 0", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping for LMUL < 1", + "line_range": [ + 754, + 754 + ] + }, + { + "text": "SEW=8b - - - - - - - - - - - - 3 2 1 0 SEW=16b - - - - - - 1 0 SEW=32b - - - 0 ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping for LMUL < 1", + "line_range": [ + 756, + 759 + ] + }, + { + "text": "When vector registers are grouped, the elements of the vector register group are packed contiguously in element order beginning with the lowest-numbered vector register and moving to the next-highest-numbered vector register in the group once each vector register is filled.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping for LMUL > 1", + "line_range": [ + 763, + 768 + ] + }, + { + "text": "Byte 3 2 1 0 v2*n 3 2 1 0 v2*n+1 7 6 5 4", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping for LMUL > 1", + "line_range": [ + 775, + 777 + ] + }, + { + "text": "Byte 3 2 1 0 v2*n 1 0 v2*n+1 3 2", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping for LMUL > 1", + "line_range": [ + 781, + 783 + ] + }, + { + "text": "Byte 3 2 1 0 v4*n 1 0 v4*n+1 3 2 v4*n+2 5 4 v4*n+3 7 6", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping for LMUL > 1", + "line_range": [ + 787, + 791 + ] + }, + { + "text": "Byte 3 2 1 0 v4*n 0 v4*n+1 1 v4*n+2 2 v4*n+3 3", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping for LMUL > 1", + "line_range": [ + 795, + 799 + ] + }, + { + "text": "Byte 7 6 5 4 3 2 1 0 v2*n 1 0 v2*n+1 3 2", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping for LMUL > 1", + "line_range": [ + 803, + 805 + ] + }, + { + "text": "Byte 7 6 5 4 3 2 1 0 v4*n 1 0 v4*n+1 3 2 v4*n+2 5 4 v4*n+3 7 6", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping for LMUL > 1", + "line_range": [ + 809, + 813 + ] + }, + { + "text": "VLEN=128b, SEW=32b, LMUL=2", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping for LMUL > 1", + "line_range": [ + 815, + 815 + ] + }, + { + "text": "Byte F E D C B A 9 8 7 6 5 4 3 2 1 0 v2*n 3 2 1 0 v2*n+1 7 6 5 4", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping for LMUL > 1", + "line_range": [ + 817, + 819 + ] + }, + { + "text": "VLEN=128b, SEW=32b, LMUL=4", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping for LMUL > 1", + "line_range": [ + 821, + 821 + ] + }, + { + "text": "Byte F E D C B A 9 8 7 6 5 4 3 2 1 0 v4*n 3 2 1 0 v4*n+1 7 6 5 4 v4*n+2 B A 9 8 v4*n+3 F E D C ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping for LMUL > 1", + "line_range": [ + 823, + 828 + ] + }, + { + "text": "The vector ISA is designed to support mixed-width operations without requiring additional explicit rearrangement instructions.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping across Mixed-Width Operations", + "line_range": [ + 833, + 837 + ] + }, + { + "text": "The recommended software strategy when operating on multiple vectors with different precision values is to modify `vtype` dynamically to keep SEW/LMUL constant (and hence VLMAX constant).", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping across Mixed-Width Operations", + "line_range": [ + 833, + 837 + ] + }, + { + "text": "The following example shows four different packed element widths (8b, 16b, 32b, 64b) in a VLEN=128b implementation.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping across Mixed-Width Operations", + "line_range": [ + 839, + 843 + ] + }, + { + "text": "The vector register grouping factor (LMUL) is increased by the relative element size such that each group can hold the same number of vector elements (VLMAX=8 in this example) to simplify strip-mining code.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping across Mixed-Width Operations", + "line_range": [ + 839, + 843 + ] + }, + { + "text": "---- Example VLEN=128b, with SEW/LMUL=16", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping across Mixed-Width Operations", + "line_range": [ + 845, + 846 + ] + }, + { + "text": "Byte F E D C B A 9 8 7 6 5 4 3 2 1 0 vn - - - - - - - - 7 6 5 4 3 2 1 0 SEW=8b, LMUL=1/2", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping across Mixed-Width Operations", + "line_range": [ + 848, + 849 + ] + }, + { + "text": "vn 7 6 5 4 3 2 1 0 SEW=16b, LMUL=1", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping across Mixed-Width Operations", + "line_range": [ + 851, + 851 + ] + }, + { + "text": "v2*n 3 2 1 0 SEW=32b, LMUL=2 v2*n+1 7 6 5 4", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping across Mixed-Width Operations", + "line_range": [ + 853, + 854 + ] + }, + { + "text": "v4*n 1 0 SEW=64b, LMUL=4 v4*n+1 3 2 v4*n+2 5 4 v4*n+3 7 6 ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping across Mixed-Width Operations", + "line_range": [ + 856, + 860 + ] + }, + { + "text": "The following table shows each possible constant SEW/LMUL operating point for loops with mixed-width operations.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping across Mixed-Width Operations", + "line_range": [ + 862, + 868 + ] + }, + { + "text": "Each column represents a constant SEW/LMUL operating point.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping across Mixed-Width Operations", + "line_range": [ + 862, + 868 + ] + }, + { + "text": "Entries in table are the LMUL values that yield that column's SEW/LMUL value for the data width on that row.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping across Mixed-Width Operations", + "line_range": [ + 862, + 868 + ] + }, + { + "text": "In each column, an LMUL setting for a data width indicates that it can be aligned with the other data widths in the same column that also have an LMUL setting, such that all have the same VLMAX.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping across Mixed-Width Operations", + "line_range": [ + 862, + 868 + ] + }, + { + "text": "| | 7+^| SEW/LMUL | | 1 | 2 | 4 | 8 | 16 | 32 | 64", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping across Mixed-Width Operations", + "line_range": [ + 870, + 872 + ] + }, + { + "text": "| SEW= 8 | 8 | 4 | 2 | 1 | 1/2 | 1/4 | 1/8 | SEW= 16 | | 8 | 4 | 2 | 1 | 1/2 | 1/4 | SEW= 32 | | | 8 | 4 | 2 | 1 | 1/2 | SEW= 64 | | | | 8 | 4 | 2 | 1 |", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping across Mixed-Width Operations", + "line_range": [ + 874, + 878 + ] + }, + { + "text": "Larger LMUL settings can also used to simply increase vector length to reduce instruction fetch and dispatch overheads in cases where fewer vector register groups are needed.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mapping across Mixed-Width Operations", + "line_range": [ + 880, + 882 + ] + }, + { + "text": "A vector mask occupies only one vector register regardless of SEW and LMUL.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mask Register Layout", + "line_range": [ + 887, + 889 + ] + }, + { + "text": "Each element is allocated a single mask bit in a mask vector register.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mask Register Layout", + "line_range": [ + 891, + 894 + ] + }, + { + "text": "The mask bit for element i is located in bit i of the mask register, independent of SEW or LMUL.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Mapping of Vector Elements to Vector Register State > Mask Register Layout", + "line_range": [ + 891, + 894 + ] + }, + { + "text": "The instructions in the vector extension fit under two existing major opcodes (LOAD-FP and STORE-FP) and one new major opcode (OP-V).", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats", + "line_range": [ + 898, + 899 + ] + }, + { + "text": "Vector loads and stores are encoded within the scalar floating-point load and store major opcodes (LOAD-FP/STORE-FP).", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats", + "line_range": [ + 901, + 906 + ] + }, + { + "text": "The vector load and store encodings repurpose a portion of the standard scalar floating-point load/store 12-bit immediate field to provide further vector instruction encoding, with bit 25 holding the standard vector mask bit (see ).", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats", + "line_range": [ + 901, + 906 + ] + }, + { + "text": "Vector instructions can have scalar or vector source operands and produce scalar or vector results, and most vector instructions can be performed either unconditionally or conditionally under a mask.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats", + "line_range": [ + 914, + 916 + ] + }, + { + "text": "Vector loads and stores move bit patterns between vector register elements and memory.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats", + "line_range": [ + 918, + 920 + ] + }, + { + "text": "Vector arithmetic instructions operate on values held in vector register elements.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats", + "line_range": [ + 918, + 920 + ] + }, + { + "text": "Scalar operands can be immediates, or taken from the `x` registers, the `f` registers, or element 0 of a vector register.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Scalar Operands", + "line_range": [ + 924, + 928 + ] + }, + { + "text": "Scalar results are written to an `x` or `f` register or to element 0 of a vector register.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Scalar Operands", + "line_range": [ + 924, + 928 + ] + }, + { + "text": "Any vector register can be used to hold a scalar regardless of the current LMUL setting.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Scalar Operands", + "line_range": [ + 924, + 928 + ] + }, + { + "text": "NOTE: Zfinx (\"F in X\") is a new ISA extension where floating-point instructions take their arguments from the integer register file.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Scalar Operands", + "line_range": [ + 930, + 934 + ] + }, + { + "text": "The vector extension is also compatible with Zfinx, where the Zfinx vector extension has vector-scalar floating-point instructions taking their scalar argument from the `x` registers.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Scalar Operands", + "line_range": [ + 930, + 934 + ] + }, + { + "text": "NOTE: We considered but did not pursue overlaying the `f` registers on `v` registers.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Scalar Operands", + "line_range": [ + 936, + 943 + ] + }, + { + "text": "The adopted approach reduces vector register pressure, avoids interactions with the standard calling convention, simplifies high-performance scalar floating-point design, and provides compatibility with the Zfinx ISA option.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Scalar Operands", + "line_range": [ + 936, + 943 + ] + }, + { + "text": "Overlaying `f` with `v` would provide the advantage of lowering the number of state bits in some implementations, but complicates high-performance designs and would prevent compatibility with the Zfinx ISA option.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Scalar Operands", + "line_range": [ + 936, + 943 + ] + }, + { + "text": "Each vector operand has an effective element width (EEW) and an effective LMUL (EMUL) that is used to determine the size and location of all the elements within a vector register group.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Vector Operands", + "line_range": [ + 948, + 953 + ] + }, + { + "text": "By default, for most operands of most instructions, EEW=SEW and EMUL=LMUL.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Vector Operands", + "line_range": [ + 948, + 953 + ] + }, + { + "text": "Some vector instructions have source and destination vector operands with the same number of elements but different widths, so that EEW and EMUL differ from SEW and LMUL respectively but EEW/EMUL = SEW/LMUL.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Vector Operands", + "line_range": [ + 955, + 961 + ] + }, + { + "text": "For example, most widening arithmetic instructions have a source group with EEW=SEW and EMUL=LMUL but have a destination group with EEW=2*SEW and EMUL=2*LMUL.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Vector Operands", + "line_range": [ + 955, + 961 + ] + }, + { + "text": "Narrowing instructions have a source operand that has EEW=2*SEW and EMUL=2*LMUL but with a destination where EEW=SEW and EMUL=LMUL.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Vector Operands", + "line_range": [ + 955, + 961 + ] + }, + { + "text": "Vector operands or results may occupy one or more vector registers depending on EMUL, but are always specified using the lowest-numbered vector register in the group.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Vector Operands", + "line_range": [ + 963, + 967 + ] + }, + { + "text": "Using other than the lowest-numbered vector register to specify a vector register group is a reserved encoding.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Vector Operands", + "line_range": [ + 963, + 967 + ] + }, + { + "text": "A vector register cannot be used to provide source operands with more than one EEW for a single instruction. A mask register source is considered to have EEW=1 for this constraint.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Vector Operands", + "line_range": [ + 969, + 976 + ] + }, + { + "text": "An encoding that would result in the same vector register being read with two or more different EEWs, including when the vector register appears at different positions within two or more vector register groups, is reserved.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Vector Operands", + "line_range": [ + 969, + 976 + ] + }, + { + "text": "NOTE: In practice, there is no software benefit to reading the same register with different EEW in the same instruction, and this constraint reduces complexity for implementations that internally rearrange data dependent on EEW.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Vector Operands", + "line_range": [ + 978, + 981 + ] + }, + { + "text": "A destination vector register group can overlap a source vector register group only if one of the following holds:", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Vector Operands", + "line_range": [ + 983, + 985 + ] + }, + { + "text": "The destination EEW equals the source EEW. - The destination EEW is smaller than the source EEW, and the lowest-numbered register in the destination vector register group is the same as the lowest-numbered register in the source vector register group. (For example, when LMUL=1, `vnsrl.wi v0, v0, 3` is legal, but a destination of `v1` is not). - The destination EEW is greater than the source EEW, the source EMUL is at least 1, and the highest-numbered register in the destination vector register group is the same as the highest-numbered register in the source vector register group. (For example, when LMUL=8, `vzext.vf4 v0, v6` is legal, but a source of `v0`, `v2`, or `v4` is not).", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Vector Operands", + "line_range": [ + 987, + 998 + ] + }, + { + "text": "For the purpose of determining register group overlap constraints, mask elements have EEW=1.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Vector Operands", + "line_range": [ + 1000, + 1002 + ] + }, + { + "text": "NOTE: The overlap constraints are designed to support resumable exceptions in machines without register renaming.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Vector Operands", + "line_range": [ + 1004, + 1005 + ] + }, + { + "text": "Any instruction encoding that violates the overlap constraints is reserved.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Vector Operands", + "line_range": [ + 1007, + 1008 + ] + }, + { + "text": "When source and destination registers overlap and have different EEW, the instruction is mask- and tail-agnostic, regardless of the setting of the `vta` and `vma` bits in `vtype`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Vector Operands", + "line_range": [ + 1010, + 1013 + ] + }, + { + "text": "The largest vector register group used by an instruction can not be greater than 8 vector registers (i.e., EMUL{le}8), and if a vector instruction would require greater than 8 vector registers in a group, the instruction encoding is reserved.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Vector Operands", + "line_range": [ + 1015, + 1021 + ] + }, + { + "text": "For example, a widening operation that produces a widened vector register group result when LMUL=8 is reserved as this would imply a result EMUL=16.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Vector Operands", + "line_range": [ + 1015, + 1021 + ] + }, + { + "text": "Widened scalar values, e.g., input and output to a widening reduction operation, are held in the first element of a vector register and have EMUL=1.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Vector Operands", + "line_range": [ + 1023, + 1026 + ] + }, + { + "text": "Masking is supported on many vector instructions.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Vector Masking", + "line_range": [ + 1030, + 1035 + ] + }, + { + "text": "Element operations that are masked off (inactive) never generate exceptions.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Vector Masking", + "line_range": [ + 1030, + 1035 + ] + }, + { + "text": "The destination vector register elements corresponding to masked-off elements are handled with either a mask-undisturbed or mask-agnostic policy depending on the setting of the `vma` bit in `vtype` ().", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Vector Masking", + "line_range": [ + 1030, + 1035 + ] + }, + { + "text": "The mask value used to control execution of a masked vector instruction is always supplied by vector register `v0`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Vector Masking", + "line_range": [ + 1037, + 1039 + ] + }, + { + "text": "NOTE: Masks are held in vector registers, rather than in a separate mask register file, to reduce total architectural state and to simplify the ISA.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Vector Masking", + "line_range": [ + 1041, + 1042 + ] + }, + { + "text": "NOTE: Future vector extensions may provide longer instruction encodings with space for a full mask register specifier.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Vector Masking", + "line_range": [ + 1044, + 1045 + ] + }, + { + "text": "The destination vector register group for a masked vector instruction cannot overlap the source mask register (`v0`), unless the destination vector register is being written with a mask value (e.g., compares) or the scalar result of a reduction.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Vector Masking", + "line_range": [ + 1047, + 1052 + ] + }, + { + "text": "These instruction encodings are reserved.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Vector Masking", + "line_range": [ + 1047, + 1052 + ] + }, + { + "text": "NOTE: This constraint supports restart with a non-zero `vstart` value.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Vector Masking", + "line_range": [ + 1054, + 1054 + ] + }, + { + "text": "Other vector registers can be used to hold working mask values, and mask vector logical operations are provided to perform predicate calculations.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Vector Masking", + "line_range": [ + 1056, + 1058 + ] + }, + { + "text": "As specified in , mask destination tail elements are always treated as tail-agnostic, regardless of the setting of `vta`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Vector Masking", + "line_range": [ + 1060, + 1061 + ] + }, + { + "text": "Where available, masking is encoded in a single-bit `vm` field in the instruction (`inst[25]`).", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Vector Masking > Mask Encoding", + "line_range": [ + 1066, + 1068 + ] + }, + { + "text": "[cols=\"1,15\"] | | vm | Description", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Vector Masking > Mask Encoding", + "line_range": [ + 1070, + 1072 + ] + }, + { + "text": "| 0 | vector result, only where v0.mask[i] = 1 | 1 | unmasked |", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Vector Masking > Mask Encoding", + "line_range": [ + 1074, + 1076 + ] + }, + { + "text": "Vector masking is represented in assembler code as another vector operand, with `.t` indicating that the operation occurs when `v0.mask[i]` is `1` (`t` for \"true\").", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Vector Masking > Mask Encoding", + "line_range": [ + 1078, + 1081 + ] + }, + { + "text": "If no masking operand is specified, unmasked vector execution (`vm=1`) is assumed.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Vector Masking > Mask Encoding", + "line_range": [ + 1078, + 1081 + ] + }, + { + "text": "---- vop.v* v1, v2, v3, v0.t enabled where v0.mask[i]=1, vm=0 vop.v* v1, v2, v3 unmasked vector operation, vm=1 ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Vector Masking > Mask Encoding", + "line_range": [ + 1083, + 1086 + ] + }, + { + "text": "NOTE: Even though the current vector extensions only support one vector mask register `v0` and only the true form of predication, the assembly syntax writes it out in full to be compatible with future extensions that might add a mask register specifier and support both true and complement mask values.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Vector Masking > Mask Encoding", + "line_range": [ + 1088, + 1093 + ] + }, + { + "text": "The `.t` suffix on the masking operand also helps to visually encode the use of a mask.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Vector Masking > Mask Encoding", + "line_range": [ + 1088, + 1093 + ] + }, + { + "text": "NOTE: The `.mask` suffix is not part of the assembly syntax.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Vector Masking > Mask Encoding", + "line_range": [ + 1095, + 1097 + ] + }, + { + "text": "We only append it in contexts where a mask vector is subscripted, e.g., `v0.mask[i]`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Vector Masking > Mask Encoding", + "line_range": [ + 1095, + 1097 + ] + }, + { + "text": "The destination element indices operated on during a vector instruction's execution can be divided into three disjoint subsets.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Prestart, Active, Inactive, Body, and Tail Element Definitions", + "line_range": [ + 1102, + 1103 + ] + }, + { + "text": "The prestart elements are those whose element index is less than the initial value in the `vstart` register.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Prestart, Active, Inactive, Body, and Tail Element Definitions", + "line_range": [ + 1105, + 1106 + ] + }, + { + "text": "The prestart elements do not raise exceptions and do not update the destination vector register.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Prestart, Active, Inactive, Body, and Tail Element Definitions", + "line_range": [ + 1105, + 1106 + ] + }, + { + "text": "The body elements are those whose element index is greater than or equal to the initial value in the `vstart` register, and less than the current vector length setting in `vl`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Prestart, Active, Inactive, Body, and Tail Element Definitions", + "line_range": [ + 1108, + 1110 + ] + }, + { + "text": "The body can be split into two disjoint subsets:", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Prestart, Active, Inactive, Body, and Tail Element Definitions", + "line_range": [ + 1108, + 1110 + ] + }, + { + "text": "** The active elements during a vector instruction's execution are the elements within the body and where the current mask is enabled at that element position.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Prestart, Active, Inactive, Body, and Tail Element Definitions", + "line_range": [ + 1112, + 1114 + ] + }, + { + "text": "The active elements can raise exceptions and update the destination vector register group.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Prestart, Active, Inactive, Body, and Tail Element Definitions", + "line_range": [ + 1112, + 1114 + ] + }, + { + "text": "** The inactive elements are the elements within the body but where the current mask is disabled at that element position.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Prestart, Active, Inactive, Body, and Tail Element Definitions", + "line_range": [ + 1116, + 1118 + ] + }, + { + "text": "The inactive elements do not raise exceptions and do not update any destination vector register group unless masked agnostic is specified (`vtype.vma`=1), in which case inactive elements may be overwritten with 1s.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Prestart, Active, Inactive, Body, and Tail Element Definitions", + "line_range": [ + 1116, + 1118 + ] + }, + { + "text": "The tail elements during a vector instruction's execution are the elements past the current vector length setting specified in `vl`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Prestart, Active, Inactive, Body, and Tail Element Definitions", + "line_range": [ + 1120, + 1122 + ] + }, + { + "text": "The tail elements do not raise exceptions, and do not update any destination vector register group unless tail agnostic is specified (`vtype.vta`=1), in which case tail elements may be overwritten with 1s, or with the result of the instruction in the case of mask-producing instructions except for mask loads.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Prestart, Active, Inactive, Body, and Tail Element Definitions", + "line_range": [ + 1120, + 1122 + ] + }, + { + "text": "When LMUL < 1, the tail includes the elements past VLMAX that are held in the same vector register.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Prestart, Active, Inactive, Body, and Tail Element Definitions", + "line_range": [ + 1120, + 1122 + ] + }, + { + "text": "---- for element index x prestart(x) = (0 <= x < vstart) body(x) = (vstart <= x < vl) tail(x) = (vl <= x < max(VLMAX,VLEN/SEW)) mask(x) = unmasked || v0.mask[x] 1 active(x) = body(x) && mask(x) inactive(x) = body(x) && !mask(x) ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Prestart, Active, Inactive, Body, and Tail Element Definitions", + "line_range": [ + 1124, + 1132 + ] + }, + { + "text": "When `vstart` {ge} `vl`, there are no body elements, and no elements are updated in any destination vector register group, including that no tail elements are updated with agnostic values.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Prestart, Active, Inactive, Body, and Tail Element Definitions", + "line_range": [ + 1134, + 1137 + ] + }, + { + "text": "NOTE: As a consequence, when `vl`=0, no elements, including agnostic elements, are updated in the destination vector register group regardless of `vstart`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Prestart, Active, Inactive, Body, and Tail Element Definitions", + "line_range": [ + 1139, + 1141 + ] + }, + { + "text": "Instructions that write an `x` register or `f` register do so even when `vstart` {ge} `vl`, including when `vl`=0.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Prestart, Active, Inactive, Body, and Tail Element Definitions", + "line_range": [ + 1143, + 1145 + ] + }, + { + "text": "NOTE: Some instructions such as `vslidedown` and `vrgather` may read indices past `vl` or even VLMAX in source vector register groups.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Prestart, Active, Inactive, Body, and Tail Element Definitions", + "line_range": [ + 1147, + 1150 + ] + }, + { + "text": "The general policy is to return the value 0 when the index is greater than VLMAX in the source vector register group.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Instruction Formats > Prestart, Active, Inactive, Body, and Tail Element Definitions", + "line_range": [ + 1147, + 1150 + ] + }, + { + "text": "One of the common approaches to handling a large number of elements is \"strip mining\" where each iteration of a loop handles some number of elements, and the iterations continue until all elements have been processed.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`)", + "line_range": [ + 1155, + 1166 + ] + }, + { + "text": "The RISC-V vector specification provides direct, portable support for this approach.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`)", + "line_range": [ + 1155, + 1166 + ] + }, + { + "text": "The application specifies the total number of elements to be processed (the application vector length or AVL) as a candidate value for `vl`, and the hardware responds via a general-purpose register with the (frequently smaller) number of elements that the hardware will handle per iteration (stored in `vl`), based on the microarchitectural implementation and the `vtype` setting. A straightforward loop structure, shown in , depicts the ease with which the code keeps track of the remaining number of elements and the amount per iteration handled by hardware.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`)", + "line_range": [ + 1155, + 1166 + ] + }, + { + "text": "A set of instructions is provided to allow rapid configuration of the values in `vl` and `vtype` to match application needs.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`)", + "line_range": [ + 1168, + 1171 + ] + }, + { + "text": "The `vset{i}vl{i}` instructions set the `vtype` and `vl` CSRs based on their arguments, and write the new value of `vl` into `rd`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`)", + "line_range": [ + 1168, + 1171 + ] + }, + { + "text": "---- vsetvli rd, rs1, vtypei rd = new vl, rs1 = AVL, vtypei = new vtype setting vsetivli rd, uimm, vtypei rd = new vl, uimm = AVL, vtypei = new vtype setting vsetvl rd, rs1, rs2 rd = new vl, rs1 = AVL, rs2 = new vtype value ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`)", + "line_range": [ + 1173, + 1177 + ] + }, + { + "text": "The new `vtype` value is encoded in the immediate fields of `vsetvli` and `vsetivli`, and in the `rs2` register for `vsetvl`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > `vtype` encoding", + "line_range": [ + 1185, + 1187 + ] + }, + { + "text": "---- Suggested assembler names used for vset{i}vli vtypei immediate", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > `vtype` encoding", + "line_range": [ + 1189, + 1190 + ] + }, + { + "text": "e8 SEW=8b e16 SEW=16b e32 SEW=32b e64 SEW=64b", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > `vtype` encoding", + "line_range": [ + 1192, + 1195 + ] + }, + { + "text": "mf8 LMUL=1/8 mf4 LMUL=1/4 mf2 LMUL=1/2 m1 LMUL=1 m2 LMUL=2 m4 LMUL=4 m8 LMUL=8", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > `vtype` encoding", + "line_range": [ + 1197, + 1203 + ] + }, + { + "text": "Examples: vsetvli t0, a0, e8, m1, ta, ma SEW= 8, LMUL=1 vsetvli t0, a0, e8, m2, ta, ma SEW= 8, LMUL=2 vsetvli t0, a0, e32, mf2, ta, ma SEW=32, LMUL=1/2 ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > `vtype` encoding", + "line_range": [ + 1205, + 1209 + ] + }, + { + "text": "The `vsetvl` variant operates similarly to `vsetvli` except that it takes a `vtype` value from `rs2` and can be used for context restore.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > `vtype` encoding", + "line_range": [ + 1211, + 1212 + ] + }, + { + "text": "If the `vtype` value is not supported by the implementation, then the `vill` bit is set in `vtype`, the remaining bits in `vtype` are set to zero, and the `vl` register is also set to zero.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > `vtype` encoding > Unsupported `vtype` Values", + "line_range": [ + 1216, + 1218 + ] + }, + { + "text": "NOTE: Earlier drafts required a trap when setting `vtype` to an illegal value.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > `vtype` encoding > Unsupported `vtype` Values", + "line_range": [ + 1220, + 1227 + ] + }, + { + "text": "However, this would have added the first data-dependent trap on a CSR write to the ISA.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > `vtype` encoding > Unsupported `vtype` Values", + "line_range": [ + 1220, + 1227 + ] + }, + { + "text": "Implementations could choose to trap when illegal values are written to `vtype` instead of setting `vill`, to allow emulation to support new configurations for forward-compatibility.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > `vtype` encoding > Unsupported `vtype` Values", + "line_range": [ + 1220, + 1227 + ] + }, + { + "text": "The current scheme supports light-weight runtime interrogation of the supported vector unit configurations by checking if `vill` is clear for a given setting.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > `vtype` encoding > Unsupported `vtype` Values", + "line_range": [ + 1220, + 1227 + ] + }, + { + "text": "A `vtype` value with `vill` set is treated as an unsupported configuration.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > `vtype` encoding > Unsupported `vtype` Values", + "line_range": [ + 1229, + 1231 + ] + }, + { + "text": "Implementations must consider all bits of the `vtype` value to determine if the configuration is supported.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > `vtype` encoding > Unsupported `vtype` Values", + "line_range": [ + 1233, + 1236 + ] + }, + { + "text": "An unsupported value in any location within the `vtype` value must result in `vill` being set.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > `vtype` encoding > Unsupported `vtype` Values", + "line_range": [ + 1233, + 1236 + ] + }, + { + "text": "NOTE: In particular, all XLEN bits of the register `vtype` argument to the `vsetvl` instruction must be checked.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > `vtype` encoding > Unsupported `vtype` Values", + "line_range": [ + 1238, + 1242 + ] + }, + { + "text": "Implementations cannot ignore fields they do not implement.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > `vtype` encoding > Unsupported `vtype` Values", + "line_range": [ + 1238, + 1242 + ] + }, + { + "text": "All bits must be checked to ensure that new code assuming unsupported vector features in `vtype` traps instead of executing incorrectly on an older implementation.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > `vtype` encoding > Unsupported `vtype` Values", + "line_range": [ + 1238, + 1242 + ] + }, + { + "text": "The new vector length setting is based on AVL, which for `vsetvli` and `vsetvl` is encoded in the `rs1` and `rd` fields as follows:", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > AVL encoding", + "line_range": [ + 1246, + 1248 + ] + }, + { + "text": ".AVL used in `vsetvli` and `vsetvl` instructions [cols=\"2,2,10,10\"] | | `rd` | `rs1` | AVL value | Effect on `vl` | - | !x0 | Value in `x[rs1]` | Normal strip mining | !x0 | x0 | ~0 | Set `vl` to VLMAX | x0 | x0 | Value in `vl` register | Keep existing `vl` (of course, `vtype` may change) |", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > AVL encoding", + "line_range": [ + 1250, + 1258 + ] + }, + { + "text": "When rs1 is not `x0`, the AVL is an unsigned integer held in the `x` register specified by rs1, and the new `vl` value is also written to the `x` register specified by rd.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > AVL encoding", + "line_range": [ + 1260, + 1263 + ] + }, + { + "text": "When rs1=`x0` but rd!=`x0`, the maximum unsigned integer value (`~0`) is used as the AVL, and the resulting VLMAX is written to `vl` and also to the `x` register specified by `rd`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > AVL encoding", + "line_range": [ + 1265, + 1268 + ] + }, + { + "text": "When rs1=`x0` and rd=`x0`, the instructions operate as if the current vector length in `vl` is used as the AVL, and the resulting value is written to `vl`, but not to a destination register.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > AVL encoding", + "line_range": [ + 1270, + 1270 + ] + }, + { + "text": "This form can only be used when VLMAX and hence `vl` is not actually changed by the new SEW/LMUL ratio.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > AVL encoding", + "line_range": [ + 1270, + 1270 + ] + }, + { + "text": "Use of the instructions with a new SEW/LMUL ratio that would result in a change of VLMAX is reserved.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > AVL encoding", + "line_range": [ + 1270, + 1270 + ] + }, + { + "text": "Use of the instructions is also reserved if `vill` was 1 beforehand.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > AVL encoding", + "line_range": [ + 1270, + 1270 + ] + }, + { + "text": "Implementations may set `vill` in either case.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > AVL encoding", + "line_range": [ + 1270, + 1270 + ] + }, + { + "text": "NOTE: This last form of the instructions allows the `vtype` register to be changed while maintaining the current `vl`, provided VLMAX is not reduced.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > AVL encoding", + "line_range": [ + 1272, + 1280 + ] + }, + { + "text": "This design was chosen to ensure `vl` would always hold a legal value for current `vtype` setting.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > AVL encoding", + "line_range": [ + 1272, + 1280 + ] + }, + { + "text": "The current `vl` value can be read from the `vl` CSR.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > AVL encoding", + "line_range": [ + 1272, + 1280 + ] + }, + { + "text": "The `vl` value could be reduced by these instructions if the new SEW/LMUL ratio causes VLMAX to shrink, and so this case has been reserved as it is not clear this is a generally useful operation, and implementations can otherwise assume `vl` is not changed by these instructions to optimize their microarchitecture.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > AVL encoding", + "line_range": [ + 1272, + 1280 + ] + }, + { + "text": "For the `vsetivli` instruction, the AVL is encoded as a 5-bit zero-extended immediate (0--31) in the `rs1` field.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > AVL encoding", + "line_range": [ + 1282, + 1284 + ] + }, + { + "text": "NOTE: The encoding of AVL for `vsetivli` is the same as for regular CSR immediate values.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > AVL encoding", + "line_range": [ + 1286, + 1287 + ] + }, + { + "text": "NOTE: The `vsetivli` instruction provides more compact code when the dimensions of vectors are small and known to fit inside the vector registers, in which case there is no strip-mining overhead.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > AVL encoding", + "line_range": [ + 1289, + 1291 + ] + }, + { + "text": "The `vset{i}vl{i}` instructions first set VLMAX according to their `vtype` argument, then set `vl` obeying the following constraints:", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > Constraints on Setting `vl`", + "line_range": [ + 1296, + 1298 + ] + }, + { + "text": ". `vl = AVL` if `AVL {le} VLMAX` . `ceil(AVL / 2) {le} vl {le} VLMAX` if `AVL < (2 * VLMAX)` . `vl = VLMAX` if `AVL {ge} (2 * VLMAX)` .", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > Constraints on Setting `vl`", + "line_range": [ + 1300, + 1311 + ] + }, + { + "text": "Deterministic on any given implementation for same input AVL and VLMAX values .", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > Constraints on Setting `vl`", + "line_range": [ + 1300, + 1311 + ] + }, + { + "text": "These specific properties follow from the prior rules: .. `vl = 0` if `AVL = 0` .. `vl > 0` if `AVL > 0` .. `vl {le} VLMAX` .. `vl {le} AVL` .. a value read from `vl` when used as the AVL argument to `vset{i}vl{i}` results in the same value in `vl`, provided the resultant VLMAX equals the value of VLMAX at the time that `vl` was read", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > Constraints on Setting `vl`", + "line_range": [ + 1300, + 1311 + ] + }, + { + "text": "[NOTE] -- The `vl` setting rules are designed to be sufficiently strict to preserve `vl` behavior across register spills and context swaps for `AVL {le} VLMAX`, yet flexible enough to enable implementations to improve vector lane utilization for `AVL > VLMAX`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > Constraints on Setting `vl`", + "line_range": [ + 1313, + 1318 + ] + }, + { + "text": "For example, this permits an implementation to set `vl = ceil(AVL / 2)` for `VLMAX < AVL < 2*VLMAX` in order to evenly distribute work over the last two iterations of a strip-mine loop.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > Constraints on Setting `vl`", + "line_range": [ + 1320, + 1329 + ] + }, + { + "text": "Requirement 2 ensures that the first strip-mine iteration of reduction loops uses the largest vector length of all iterations, even in the case of `AVL < 2*VLMAX`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > Constraints on Setting `vl`", + "line_range": [ + 1320, + 1329 + ] + }, + { + "text": "This allows software to avoid needing to explicitly calculate a running maximum of vector lengths observed during a strip-mined loop.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > Constraints on Setting `vl`", + "line_range": [ + 1320, + 1329 + ] + }, + { + "text": "Requirement 2 also allows an implementation to set vl to VLMAX for `VLMAX < AVL < 2*VLMAX` --", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > Constraints on Setting `vl`", + "line_range": [ + 1320, + 1329 + ] + }, + { + "text": "The SEW and LMUL settings can be changed dynamically to provide high throughput on mixed-width operations in a single loop. ---- Example: Load 16-bit values, widen multiply to 32b, shift 32b result right by 3, store 32b values.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > Example of strip mining and changes to SEW", + "line_range": [ + 1334, + 1342 + ] + }, + { + "text": "On entry: a0 holds the total number of elements to process a1 holds the address of the source array a2 holds the address of the destination array", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > Example of strip mining and changes to SEW", + "line_range": [ + 1334, + 1342 + ] + }, + { + "text": "loop: vsetvli a3, a0, e16, m4, ta, ma vtype = 16-bit integer vectors; also update a3 with vl ( of elements this iteration) vle16.v v4, (a1) Get 16b vector slli t1, a3, 1 Multiply elements this iteration by 2 bytes/source element add a1, a1, t1 Bump pointer vwmul.vx v8, v4, x10 Widening multiply into 32b in ", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > Example of strip mining and changes to SEW", + "line_range": [ + 1344, + 1350 + ] + }, + { + "text": "vsetvli x0, x0, e32, m8, ta, ma Operate on 32b values vsrl.vi v8, v8, 3 vse32.v v8, (a2) Store vector of 32b elements slli t1, a3, 2 Multiply elements this iteration by 4 bytes/destination element add a2, a2, t1 Bump pointer sub a0, a0, a3 Decrement count by vl bnez a0, loop Any more? ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Configuration-Setting Instructions (`vsetvli`/`vsetivli`/`vsetvl`) > Example of strip mining and changes to SEW", + "line_range": [ + 1352, + 1359 + ] + }, + { + "text": "Vector loads and stores move values between vector registers and memory.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores", + "line_range": [ + 1364, + 1372 + ] + }, + { + "text": "Vector loads and stores can be masked, and they only access memory or raise exceptions for active elements.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores", + "line_range": [ + 1364, + 1372 + ] + }, + { + "text": "Masked vector loads do not update inactive elements in the destination vector register group, unless masked agnostic is specified (`vtype.vma`=1).", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores", + "line_range": [ + 1364, + 1372 + ] + }, + { + "text": "All vector loads and stores may generate and accept a non-zero `vstart` value.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores", + "line_range": [ + 1364, + 1372 + ] + }, + { + "text": "Vector loads and stores are encoded within the scalar floating-point load and store major opcodes (LOAD-FP/STORE-FP).", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Instruction Encoding", + "line_range": [ + 1376, + 1381 + ] + }, + { + "text": "The vector load and store encodings repurpose a portion of the standard scalar floating-point load/store 12-bit immediate field to provide further vector instruction encoding, with bit 25 holding the standard vector mask bit (see ).", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Instruction Encoding", + "line_range": [ + 1376, + 1381 + ] + }, + { + "text": "[cols=\"4,12\"] | | Field | Description", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Instruction Encoding", + "line_range": [ + 1385, + 1387 + ] + }, + { + "text": "| rs1[4:0] | specifies x register holding base address | rs2[4:0] | specifies x register holding stride | vs2[4:0] | specifies v register holding address offsets | vs3[4:0] | specifies v register holding store data | vd[4:0] | specifies v register destination of load | vm | specifies whether vector masking is enabled (0 = mask enabled, 1 = mask disabled) | width[2:0] | specifies size of memory elements, and distinguishes from FP scalar | mew | extended memory element width.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Instruction Encoding", + "line_range": [ + 1389, + 1400 + ] + }, + { + "text": "See | mop[1:0] | specifies memory addressing mode | nf[2:0] | specifies the number of fields in each segment, for segment load/stores | lumop[4:0]/sumop[4:0] | are additional fields encoding variants of unit-stride instructions |", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Instruction Encoding", + "line_range": [ + 1389, + 1400 + ] + }, + { + "text": "Vector memory unit-stride and constant-stride operations directly encode EEW of the data to be transferred statically in the instruction to reduce the number of `vtype` changes when accessing memory in a mixed-width routine.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Instruction Encoding", + "line_range": [ + 1402, + 1402 + ] + }, + { + "text": "Indexed operations use the explicit EEW encoding in the instruction to set the size of the indices used, and use SEW/LMUL to specify the data width.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Instruction Encoding", + "line_range": [ + 1402, + 1402 + ] + }, + { + "text": "The vector extension supports unit-stride, constant-stride, and indexed (scatter/gather) addressing modes.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Addressing Modes", + "line_range": [ + 1406, + 1408 + ] + }, + { + "text": "Vector load/store base registers and strides are taken from the GPR `x` registers.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Addressing Modes", + "line_range": [ + 1406, + 1408 + ] + }, + { + "text": "The base effective address for all vector accesses is given by the contents of the `x` register named in `rs1`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Addressing Modes", + "line_range": [ + 1410, + 1412 + ] + }, + { + "text": "Vector unit-stride operations access elements stored contiguously in memory starting from the base effective address.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Addressing Modes", + "line_range": [ + 1414, + 1416 + ] + }, + { + "text": "Vector constant-stride operations access the first memory element at the base effective address, and then access subsequent elements at address increments given by the byte offset contained in the `x` register specified by `rs2`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Addressing Modes", + "line_range": [ + 1418, + 1422 + ] + }, + { + "text": "Vector indexed operations add the contents of each element of the vector offset operand specified by `vs2` to the base effective address to give the effective address of each element.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Addressing Modes", + "line_range": [ + 1424, + 1430 + ] + }, + { + "text": "The data vector register group has EEW=SEW, EMUL=LMUL, while the offset vector register group has EEW encoded in the instruction and EMUL=(EEW/SEW)*LMUL.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Addressing Modes", + "line_range": [ + 1424, + 1430 + ] + }, + { + "text": "The vector offset operand is treated as a vector of byte-address offsets.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Addressing Modes", + "line_range": [ + 1432, + 1434 + ] + }, + { + "text": "NOTE: The indexed operations can also be used to access fields within a vector of objects, where the `vs2` vector holds pointers to the base of the objects and the scalar `x` register holds the offset of the member field in each object.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Addressing Modes", + "line_range": [ + 1436, + 1441 + ] + }, + { + "text": "Supporting this case is why the indexed operations were not defined to scale the element indices by the data EEW.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Addressing Modes", + "line_range": [ + 1436, + 1441 + ] + }, + { + "text": "If the vector offset elements are narrower than XLEN, they are zero-extended to XLEN before adding to the base effective address.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Addressing Modes", + "line_range": [ + 1443, + 1450 + ] + }, + { + "text": "If the vector offset elements are wider than XLEN, the least-significant XLEN bits are used in the address calculation.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Addressing Modes", + "line_range": [ + 1443, + 1450 + ] + }, + { + "text": "If the implementation does not support the EEW of the offset elements, the instruction is reserved.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Addressing Modes", + "line_range": [ + 1443, + 1450 + ] + }, + { + "text": "NOTE: A profile may place an upper limit on the maximum supported index EEW (e.g., only up to XLEN) smaller than ELEN.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Addressing Modes", + "line_range": [ + 1452, + 1453 + ] + }, + { + "text": "The vector addressing modes are encoded using the 2-bit `mop[1:0]` field.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Addressing Modes", + "line_range": [ + 1455, + 1456 + ] + }, + { + "text": ".encoding for loads [cols=\"1,1,7,6\"] | 2+| mop [1:0] | Description | Opcodes", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Addressing Modes", + "line_range": [ + 1458, + 1461 + ] + }, + { + "text": "| 0 | 0 | unit-stride | VLE | 0 | 1 | indexed-unordered | VLUXEI | 1 | 0 | constant-stride | VLSE | 1 | 1 | indexed-ordered | VLOXEI |", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Addressing Modes", + "line_range": [ + 1463, + 1467 + ] + }, + { + "text": ".encoding for stores [cols=\"1,1,7,6\"] | 2+| mop [1:0] | Description | Opcodes", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Addressing Modes", + "line_range": [ + 1469, + 1472 + ] + }, + { + "text": "| 0 | 0 | unit-stride | VSE | 0 | 1 | indexed-unordered | VSUXEI | 1 | 0 | constant-stride | VSSE | 1 | 1 | indexed-ordered | VSOXEI |", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Addressing Modes", + "line_range": [ + 1474, + 1478 + ] + }, + { + "text": "Vector unit-stride and constant-stride memory accesses do not guarantee ordering between individual element accesses.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Addressing Modes", + "line_range": [ + 1480, + 1485 + ] + }, + { + "text": "The vector indexed load and store memory operations have two forms, ordered and unordered.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Addressing Modes", + "line_range": [ + 1480, + 1485 + ] + }, + { + "text": "The indexed-ordered variants preserve element ordering on memory accesses.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Addressing Modes", + "line_range": [ + 1480, + 1485 + ] + }, + { + "text": "For unordered instructions (`mop[1:0]`!=11) there is no guarantee on element access order.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Addressing Modes", + "line_range": [ + 1487, + 1490 + ] + }, + { + "text": "If the accesses are to a strongly ordered IO region, the element accesses can be initiated in any order.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Addressing Modes", + "line_range": [ + 1487, + 1490 + ] + }, + { + "text": "NOTE: To provide ordered vector accesses to a strongly ordered IO region, the ordered indexed instructions should be used.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Addressing Modes", + "line_range": [ + 1492, + 1493 + ] + }, + { + "text": "For implementations with precise vector traps, exceptions on indexed-unordered stores must also be precise.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Addressing Modes", + "line_range": [ + 1495, + 1497 + ] + }, + { + "text": "Additional unit-stride vector addressing modes are encoded using the 5-bit `lumop` and `sumop` fields in the unit-stride load and store instruction encodings respectively.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Addressing Modes", + "line_range": [ + 1499, + 1501 + ] + }, + { + "text": ".lumop [cols=\"1,1,1,1,1,11\"] | 5+| lumop[4:0] | Description", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Addressing Modes", + "line_range": [ + 1503, + 1506 + ] + }, + { + "text": "| 0 | 0 | 0 | 0 | 0 | unit-stride load | 0 | 1 | 0 | 0 | 0 | unit-stride, whole register load | 0 | 1 | 0 | 1 | 1 | unit-stride, mask load, EEW=8 | 1 | 0 | 0 | 0 | 0 | unit-stride fault-only-first | x | x | x | x | x | other encodings reserved |", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Addressing Modes", + "line_range": [ + 1508, + 1513 + ] + }, + { + "text": ".sumop [cols=\"1,1,1,1,1,11\"] | 5+| sumop[4:0] | Description", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Addressing Modes", + "line_range": [ + 1515, + 1518 + ] + }, + { + "text": "| 0 | 0 | 0 | 0 | 0 | unit-stride store | 0 | 1 | 0 | 0 | 0 | unit-stride, whole register store | 0 | 1 | 0 | 1 | 1 | unit-stride, mask store, EEW=8 | x | x | x | x | x | other encodings reserved |", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Addressing Modes", + "line_range": [ + 1520, + 1524 + ] + }, + { + "text": "The `nf[2:0]` field encodes the number of fields in each segment.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Addressing Modes", + "line_range": [ + 1526, + 1532 + ] + }, + { + "text": "For regular vector loads and stores, `nf`=0, indicating that a single value is moved between a vector register group and memory at each element position.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Addressing Modes", + "line_range": [ + 1526, + 1532 + ] + }, + { + "text": "Larger values in the `nf` field are used to access multiple contiguous fields within a segment as described below in .", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Addressing Modes", + "line_range": [ + 1526, + 1532 + ] + }, + { + "text": "The `nf[2:0]` field also encodes the number of whole vector registers to transfer for the whole vector register load/store instructions.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Addressing Modes", + "line_range": [ + 1534, + 1536 + ] + }, + { + "text": "Vector loads and stores have an EEW encoded directly in the instruction.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Width Encoding", + "line_range": [ + 1541, + 1546 + ] + }, + { + "text": "The corresponding EMUL is calculated as EMUL = (EEW/SEW)*LMUL.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Width Encoding", + "line_range": [ + 1541, + 1546 + ] + }, + { + "text": "If the EMUL would be out of range (EMUL>8 or EMUL<1/8), the instruction encoding is reserved.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Width Encoding", + "line_range": [ + 1541, + 1546 + ] + }, + { + "text": "The vector register groups must have legal register specifiers for the selected EMUL, otherwise the instruction encoding is reserved.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Width Encoding", + "line_range": [ + 1541, + 1546 + ] + }, + { + "text": "Vector unit-stride and constant-stride use the EEW/EMUL encoded in the instruction for the data values, while vector indexed loads and stores use the EEW/EMUL encoded in the instruction for the index values and the SEW/LMUL encoded in `vtype` for the data values.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Width Encoding", + "line_range": [ + 1548, + 1552 + ] + }, + { + "text": "Vector loads and stores are encoded using width values that are not claimed by the standard scalar floating-point loads and stores.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Width Encoding", + "line_range": [ + 1554, + 1555 + ] + }, + { + "text": "Implementations must provide vector loads and stores with EEWs corresponding to all supported SEW settings.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Width Encoding", + "line_range": [ + 1557, + 1557 + ] + }, + { + "text": "Vector load/store encodings for unsupported EEW widths are reserved.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Width Encoding", + "line_range": [ + 1557, + 1557 + ] + }, + { + "text": ".Width encoding for vector loads and stores. [cols=\"5,1,1,1,1,>3,>3,>3,3\"] | | | mew 3+| width [2:0] | Mem bits | Data Reg bits | Index bits | Opcodes", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Width Encoding", + "line_range": [ + 1559, + 1562 + ] + }, + { + "text": "| Standard scalar FP | x | 0 | 0 | 1 | 16| FLEN | - | FLH/FSH | Standard scalar FP | x | 0 | 1 | 0 | 32| FLEN | - | FLW/FSW | Standard scalar FP | x | 0 | 1 | 1 | 64| FLEN | - | FLD/FSD | Standard scalar FP | x | 1 | 0 | 0 | 128| FLEN | - | FLQ/FSQ | Vector 8b element | 0 | 0 | 0 | 0 | 8| 8 | - | VLxE8/VSxE8 | Vector 16b element | 0 | 1 | 0 | 1 | 16| 16 | - | VLxE16/VSxE16 | Vector 32b element | 0 | 1 | 1 | 0 | 32| 32 | - | VLxE32/VSxE32 | Vector 64b element | 0 | 1 | 1 | 1 | 64| 64 | - | VLxE64/VSxE64 | Vector 8b index | 0 | 0 | 0 | 0 | SEW | SEW | 8 | VLxEI8/VSxEI8 | Vector 16b index | 0 | 1 | 0 | 1 | SEW | SEW | 16 | VLxEI16/VSxEI16 | Vector 32b index | 0 | 1 | 1 | 0 | SEW | SEW | 32 | VLxEI32/VSxEI32 | Vector 64b index | 0 | 1 | 1 | 1 | SEW | SEW | 64 | VLxEI64/VSxEI64 | Reserved | 1 | X | X | X | - | - | - | |", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Width Encoding", + "line_range": [ + 1564, + 1577 + ] + }, + { + "text": "Mem bits is the size of each element accessed in memory.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Width Encoding", + "line_range": [ + 1579, + 1579 + ] + }, + { + "text": "Data reg bits is the size of each data element accessed in register.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Width Encoding", + "line_range": [ + 1581, + 1581 + ] + }, + { + "text": "Index bits is the size of each index accessed in register.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Width Encoding", + "line_range": [ + 1583, + 1583 + ] + }, + { + "text": "The `mew` bit (`inst[28]`) when set is expected to be used to encode expanded memory sizes of 128 bits and above, but these encodings are currently reserved.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Width Encoding", + "line_range": [ + 1585, + 1588 + ] + }, + { + "text": "---- Vector unit-stride loads and stores", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Unit-Stride Instructions", + "line_range": [ + 1592, + 1593 + ] + }, + { + "text": "vd destination, rs1 base address, vm is mask encoding (v0.t or ) vle8.v vd, (rs1), vm 8-bit unit-stride load vle16.v vd, (rs1), vm 16-bit unit-stride load vle32.v vd, (rs1), vm 32-bit unit-stride load vle64.v vd, (rs1), vm 64-bit unit-stride load", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Unit-Stride Instructions", + "line_range": [ + 1595, + 1599 + ] + }, + { + "text": "vs3 store data, rs1 base address, vm is mask encoding (v0.t or ) vse8.v vs3, (rs1), vm 8-bit unit-stride store vse16.v vs3, (rs1), vm 16-bit unit-stride store vse32.v vs3, (rs1), vm 32-bit unit-stride store vse64.v vs3, (rs1), vm 64-bit unit-stride store ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Unit-Stride Instructions", + "line_range": [ + 1601, + 1606 + ] + }, + { + "text": "Additional unit-stride mask load and store instructions are provided to transfer mask values to/from memory.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Unit-Stride Instructions", + "line_range": [ + 1608, + 1614 + ] + }, + { + "text": "These operate similarly to unmasked byte loads or stores (EEW=8), except that the effective vector length is ``evl``=ceil(``vl``/8) (i.e. EMUL=1), and the destination register is always written with a tail-agnostic policy.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Unit-Stride Instructions", + "line_range": [ + 1608, + 1614 + ] + }, + { + "text": "---- Vector unit-stride mask load vlm.v vd, (rs1) Load byte vector of length ceil(vl/8)", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Unit-Stride Instructions", + "line_range": [ + 1616, + 1618 + ] + }, + { + "text": "Vector unit-stride mask store vsm.v vs3, (rs1) Store byte vector of length ceil(vl/8) ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Unit-Stride Instructions", + "line_range": [ + 1620, + 1622 + ] + }, + { + "text": "`vlm.v` and `vsm.v` are encoded with the same `width[2:0]`=0 encoding as `vle8.v` and `vse8.v`, but are distinguished by different `lumop` and `sumop` encodings.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Unit-Stride Instructions", + "line_range": [ + 1624, + 1627 + ] + }, + { + "text": "Since `vlm.v` and `vsm.v` operate as byte loads and stores, `vstart` is in units of bytes for these instructions.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Unit-Stride Instructions", + "line_range": [ + 1624, + 1627 + ] + }, + { + "text": "NOTE: `vlm.v` and `vsm.v` respect the `vill` field in `vtype`, as they depend on `vtype` indirectly through its constraints on `vl`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Unit-Stride Instructions", + "line_range": [ + 1629, + 1630 + ] + }, + { + "text": "NOTE: The previous assembler mnemonics `vle1.v` and `vse1.v` were confusing as length was handled differently for these instructions versus other element load/store instructions.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Unit-Stride Instructions", + "line_range": [ + 1632, + 1635 + ] + }, + { + "text": "To avoid software churn, these older assembly mnemonics are being retained as aliases.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Unit-Stride Instructions", + "line_range": [ + 1632, + 1635 + ] + }, + { + "text": "NOTE: The primary motivation to provide mask load and store is to support machines that internally rearrange data to reduce cross-datapath wiring.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Unit-Stride Instructions", + "line_range": [ + 1637, + 1642 + ] + }, + { + "text": "However, these instructions also provide a convenient mechanism to use packed bit vectors in memory as mask values, and also reduce the cost of mask spill/fill by reducing need to change `vl`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Unit-Stride Instructions", + "line_range": [ + 1637, + 1642 + ] + }, + { + "text": "---- Vector constant-stride loads and stores", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Constant-Stride Instructions", + "line_range": [ + 1646, + 1647 + ] + }, + { + "text": "vd destination, rs1 base address, rs2 byte constant-stride vlse8.v vd, (rs1), rs2, vm 8-bit constant-stride load vlse16.v vd, (rs1), rs2, vm 16-bit constant-stride load vlse32.v vd, (rs1), rs2, vm 32-bit constant-stride load vlse64.v vd, (rs1), rs2, vm 64-bit constant-stride load", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Constant-Stride Instructions", + "line_range": [ + 1649, + 1653 + ] + }, + { + "text": "vs3 store data, rs1 base address, rs2 byte constant-stride vsse8.v vs3, (rs1), rs2, vm 8-bit constant-stride store vsse16.v vs3, (rs1), rs2, vm 16-bit constant-stride store vsse32.v vs3, (rs1), rs2, vm 32-bit constant-stride store vsse64.v vs3, (rs1), rs2, vm 64-bit constant-stride store ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Constant-Stride Instructions", + "line_range": [ + 1655, + 1660 + ] + }, + { + "text": "Negative and zero strides are supported.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Constant-Stride Instructions", + "line_range": [ + 1662, + 1663 + ] + }, + { + "text": "Element accesses within a constant-stride instruction are unordered with respect to each other.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Constant-Stride Instructions", + "line_range": [ + 1665, + 1667 + ] + }, + { + "text": "When `rs2`=`x0`, then an implementation is allowed, but not required, to perform fewer memory operations than the number of active elements, and may perform different numbers of memory operations across different dynamic executions of the same static instruction.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Constant-Stride Instructions", + "line_range": [ + 1669, + 1673 + ] + }, + { + "text": "NOTE: Compilers must be aware to not use the `x0` form for rs2 when the immediate stride is `0` if the intent is to require all memory accesses are performed.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Constant-Stride Instructions", + "line_range": [ + 1675, + 1677 + ] + }, + { + "text": "When `rs2!=x0` and the value of `x[rs2]=0`, the implementation must perform one memory access for each active element (but these accesses will not be ordered).", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Constant-Stride Instructions", + "line_range": [ + 1679, + 1681 + ] + }, + { + "text": "NOTE: As with other architectural mandates, implementations must appear to perform each memory access.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Constant-Stride Instructions", + "line_range": [ + 1683, + 1688 + ] + }, + { + "text": "Microarchitectures are free to optimize away accesses that would not be observed by another agent, for example, in idempotent memory regions obeying RVWMO.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Constant-Stride Instructions", + "line_range": [ + 1683, + 1688 + ] + }, + { + "text": "For non-idempotent memory regions, where by definition each access can be observed by a device, the optimization would not be possible.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Constant-Stride Instructions", + "line_range": [ + 1683, + 1688 + ] + }, + { + "text": "When repeating ordered vector accesses to the same memory address are required, then an ordered indexed operation can be used.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Constant-Stride Instructions", + "line_range": [ + 1690, + 1691 + ] + }, + { + "text": "---- Vector indexed loads and stores", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Indexed Instructions", + "line_range": [ + 1695, + 1696 + ] + }, + { + "text": "Vector indexed-unordered load instructions vd destination, rs1 base address, vs2 byte offsets vluxei8.v vd, (rs1), vs2, vm unordered 8-bit indexed load of SEW data vluxei16.v vd, (rs1), vs2, vm unordered 16-bit indexed load of SEW data vluxei32.v vd, (rs1), vs2, vm unordered 32-bit indexed load of SEW data vluxei64.v vd, (rs1), vs2, vm unordered 64-bit indexed load of SEW data", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Indexed Instructions", + "line_range": [ + 1698, + 1703 + ] + }, + { + "text": "Vector indexed-ordered load instructions vd destination, rs1 base address, vs2 byte offsets vloxei8.v vd, (rs1), vs2, vm ordered 8-bit indexed load of SEW data vloxei16.v vd, (rs1), vs2, vm ordered 16-bit indexed load of SEW data vloxei32.v vd, (rs1), vs2, vm ordered 32-bit indexed load of SEW data vloxei64.v vd, (rs1), vs2, vm ordered 64-bit indexed load of SEW data", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Indexed Instructions", + "line_range": [ + 1705, + 1710 + ] + }, + { + "text": "Vector indexed-unordered store instructions vs3 store data, rs1 base address, vs2 byte offsets vsuxei8.v vs3, (rs1), vs2, vm unordered 8-bit indexed store of SEW data vsuxei16.v vs3, (rs1), vs2, vm unordered 16-bit indexed store of SEW data vsuxei32.v vs3, (rs1), vs2, vm unordered 32-bit indexed store of SEW data vsuxei64.v vs3, (rs1), vs2, vm unordered 64-bit indexed store of SEW data", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Indexed Instructions", + "line_range": [ + 1712, + 1717 + ] + }, + { + "text": "Vector indexed-ordered store instructions vs3 store data, rs1 base address, vs2 byte offsets vsoxei8.v vs3, (rs1), vs2, vm ordered 8-bit indexed store of SEW data vsoxei16.v vs3, (rs1), vs2, vm ordered 16-bit indexed store of SEW data vsoxei32.v vs3, (rs1), vs2, vm ordered 32-bit indexed store of SEW data vsoxei64.v vs3, (rs1), vs2, vm ordered 64-bit indexed store of SEW data ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Indexed Instructions", + "line_range": [ + 1719, + 1725 + ] + }, + { + "text": "NOTE: The assembler syntax for indexed loads and stores uses ``ei``x instead of ``e``x to indicate the statically encoded EEW is of the index not the data.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Indexed Instructions", + "line_range": [ + 1727, + 1729 + ] + }, + { + "text": "NOTE: The indexed operations mnemonics have a \"U\" or \"O\" to distinguish between unordered and ordered, while the other vector addressing modes have no character.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Indexed Instructions", + "line_range": [ + 1731, + 1736 + ] + }, + { + "text": "While this is perhaps a little less consistent, this approach minimizes disruption to existing software, as VSXEI previously meant \"ordered\" - and the opcode can be retained as an alias during transition to help reduce software churn.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Indexed Instructions", + "line_range": [ + 1731, + 1736 + ] + }, + { + "text": "The unit-stride fault-only-first load instructions are used to vectorize loops with data-dependent exit conditions (\"while\" loops).", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Unit-stride Fault-Only-First Loads", + "line_range": [ + 1740, + 1743 + ] + }, + { + "text": "These instructions execute as a regular load except that they will only take a trap caused by a synchronous exception on element 0.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Unit-stride Fault-Only-First Loads", + "line_range": [ + 1740, + 1743 + ] + }, + { + "text": "If element 0 raises an exception, `vl` is not modified, and the trap is taken.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Unit-stride Fault-Only-First Loads", + "line_range": [ + 1740, + 1743 + ] + }, + { + "text": "If an element > 0 raises an exception, the corresponding trap is not taken, and the vector length `vl` is reduced to the index of the element that would have raised an exception.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Unit-stride Fault-Only-First Loads", + "line_range": [ + 1740, + 1743 + ] + }, + { + "text": "Load instructions may overwrite active destination vector register group elements past the element index at which the trap is reported.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Unit-stride Fault-Only-First Loads", + "line_range": [ + 1745, + 1747 + ] + }, + { + "text": "Similarly, fault-only-first load instructions may update active destination elements past the element that causes trimming of the vector length (but not past the original vector length).", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Unit-stride Fault-Only-First Loads", + "line_range": [ + 1745, + 1747 + ] + }, + { + "text": "The values of these spurious updates do not have to correspond to the values in memory at the addressed memory locations.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Unit-stride Fault-Only-First Loads", + "line_range": [ + 1745, + 1747 + ] + }, + { + "text": "Non-idempotent memory locations can only be accessed when it is known the corresponding element load operation will not be restarted due to a trap or vector-length trimming.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Unit-stride Fault-Only-First Loads", + "line_range": [ + 1745, + 1747 + ] + }, + { + "text": "---- Vector unit-stride fault-only-first loads", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Unit-stride Fault-Only-First Loads", + "line_range": [ + 1749, + 1750 + ] + }, + { + "text": "vd destination, rs1 base address, vm is mask encoding (v0.t or ) vle8ff.v vd, (rs1), vm 8-bit unit-stride fault-only-first load vle16ff.v vd, (rs1), vm 16-bit unit-stride fault-only-first load vle32ff.v vd, (rs1), vm 32-bit unit-stride fault-only-first load vle64ff.v vd, (rs1), vm 64-bit unit-stride fault-only-first load ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Unit-stride Fault-Only-First Loads", + "line_range": [ + 1752, + 1757 + ] + }, + { + "text": "---- strlen example using unit-stride fault-only-first instruction", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Unit-stride Fault-Only-First Loads", + "line_range": [ + 1759, + 1760 + ] + }, + { + "text": "NOTE: There is a security concern with fault-on-first loads, as they can be used to probe for valid effective addresses.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Unit-stride Fault-Only-First Loads", + "line_range": [ + 1765, + 1776 + ] + }, + { + "text": "The unit-stride versions only allow probing a region immediately contiguous to a known region, and so reduce the security impact when used in unprivileged code.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Unit-stride Fault-Only-First Loads", + "line_range": [ + 1765, + 1776 + ] + }, + { + "text": "However, code running in S-mode can establish arbitrary page translations that allow probing of random guest physical addresses provided by a hypervisor.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Unit-stride Fault-Only-First Loads", + "line_range": [ + 1765, + 1776 + ] + }, + { + "text": "Constant-stride and scatter/gather fault-only-first instructions are not provided due to lack of encoding space, but they can also represent a larger security hole, allowing even unprivileged software to easily check multiple random pages for accessibility without experiencing a trap.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Unit-stride Fault-Only-First Loads", + "line_range": [ + 1765, + 1776 + ] + }, + { + "text": "This standard does not address possible security mitigations for fault-only-first instructions.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Unit-stride Fault-Only-First Loads", + "line_range": [ + 1765, + 1776 + ] + }, + { + "text": "Even when an exception is not raised, implementations are permitted to process fewer than `vl` elements and reduce `vl` accordingly, but if `vstart`=0 and `vl`>0, then at least one element must be processed.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Unit-stride Fault-Only-First Loads", + "line_range": [ + 1778, + 1781 + ] + }, + { + "text": "When the fault-only-first instruction takes a trap due to an interrupt, implementations should not reduce `vl` and should instead set a `vstart` value.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Unit-stride Fault-Only-First Loads", + "line_range": [ + 1783, + 1786 + ] + }, + { + "text": "When the fault-only-first instruction would trigger a debug data-watchpoint trap on an element after the first, implementations should not reduce `vl` but instead should trigger the debug trap as otherwise the event might be lost.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Unit-stride Fault-Only-First Loads", + "line_range": [ + 1788, + 1791 + ] + }, + { + "text": "The vector load/store segment instructions move multiple contiguous fields in memory to and from consecutively numbered vector registers.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions", + "line_range": [ + 1796, + 1797 + ] + }, + { + "text": "NOTE: The name \"segment\" reflects that the items moved are subarrays with homogeneous elements.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions", + "line_range": [ + 1799, + 1803 + ] + }, + { + "text": "These operations can be used to transpose arrays between memory and registers, and can support operations on \"array-of-structures\" datatypes by unpacking each field in a structure into a separate vector register.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions", + "line_range": [ + 1799, + 1803 + ] + }, + { + "text": "The three-bit `nf` field in the vector instruction encoding is an unsigned integer that contains one less than the number of fields per segment, NFIELDS.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions", + "line_range": [ + 1805, + 1808 + ] + }, + { + "text": ".NFIELDS Encoding [cols=\"1,1,1,13\"] | 3+| nf[2:0] | NFIELDS", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions", + "line_range": [ + 1810, + 1814 + ] + }, + { + "text": "| 0 | 0 | 0 | 1 | 0 | 0 | 1 | 2 | 0 | 1 | 0 | 3 | 0 | 1 | 1 | 4 | 1 | 0 | 0 | 5 | 1 | 0 | 1 | 6 | 1 | 1 | 0 | 7 | 1 | 1 | 1 | 8 |", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions", + "line_range": [ + 1816, + 1824 + ] + }, + { + "text": "The EMUL setting must be such that EMUL * NFIELDS {le} 8, otherwise the instruction encoding is reserved.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions", + "line_range": [ + 1826, + 1828 + ] + }, + { + "text": "NOTE: The product ceil(EMUL) * NFIELDS represents the number of underlying vector registers that will be touched by a segmented load or store instruction.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions", + "line_range": [ + 1830, + 1834 + ] + }, + { + "text": "This constraint makes this total no larger than 1/4 of the architectural register file, and the same as for regular operations with EMUL=8.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions", + "line_range": [ + 1830, + 1834 + ] + }, + { + "text": "Each field will be held in successively numbered vector register groups.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions", + "line_range": [ + 1836, + 1843 + ] + }, + { + "text": "When EMUL>1, each field will occupy a vector register group held in multiple successively numbered vector registers, and the vector register group for each field must follow the usual vector register alignment constraints (e.g., when EMUL=2 and NFIELDS=4, each field's vector register group must start at an even vector register, but does not have to start at a multiple of 8 vector register number).", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions", + "line_range": [ + 1836, + 1843 + ] + }, + { + "text": "If the vector register numbers accessed by the segment load or store would increment past 31, then the instruction encoding is reserved.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions", + "line_range": [ + 1845, + 1847 + ] + }, + { + "text": "NOTE: This constraint is to help allow for forward-compatibility with a possible future longer instruction encoding that has more addressable vector registers.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions", + "line_range": [ + 1849, + 1851 + ] + }, + { + "text": "The `vl` register gives the number of segments to move, which is equal to the number of elements transferred to each vector register group.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions", + "line_range": [ + 1853, + 1856 + ] + }, + { + "text": "Masking is also applied at the level of whole segments.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions", + "line_range": [ + 1853, + 1856 + ] + }, + { + "text": "For segment loads and stores, the individual memory accesses used to access fields within each segment are unordered with respect to each other even for ordered indexed segment loads and stores.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions", + "line_range": [ + 1858, + 1861 + ] + }, + { + "text": "The `vstart` value is in units of whole segments.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions", + "line_range": [ + 1863, + 1865 + ] + }, + { + "text": "If a trap occurs during access to a segment, it is implementation-defined whether a subset of the faulting segment's accesses are performed before the trap is taken.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions", + "line_range": [ + 1863, + 1865 + ] + }, + { + "text": "The vector unit-stride load and store segment instructions move packed contiguous segments into multiple destination vector register groups.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions > Vector Unit-Stride Segment Loads and Stores", + "line_range": [ + 1869, + 1871 + ] + }, + { + "text": "NOTE: Where the segments hold structures with heterogeneous-sized fields, software can later unpack individual structure fields using additional instructions after the segment load brings data into the vector registers.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions > Vector Unit-Stride Segment Loads and Stores", + "line_range": [ + 1873, + 1876 + ] + }, + { + "text": "The assembler prefixes `vlseg`/`vsseg` are used for unit-stride segment loads and stores respectively.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions > Vector Unit-Stride Segment Loads and Stores", + "line_range": [ + 1878, + 1879 + ] + }, + { + "text": "---- Format In this syntax, equals NFIELDS and is an integer in the range [2, 8]. vlsege.v vd, (rs1), vm Unit-stride segment load template vssege.v vs3, (rs1), vm Unit-stride segment store template", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions > Vector Unit-Stride Segment Loads and Stores", + "line_range": [ + 1881, + 1885 + ] + }, + { + "text": "Examples vlseg8e8.v vd, (rs1), vm Load eight vector registers with eight byte fields.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions > Vector Unit-Stride Segment Loads and Stores", + "line_range": [ + 1887, + 1888 + ] + }, + { + "text": "vsseg3e32.v vs3, (rs1), vm Store packed vector of 3*4-byte segments from vs3,vs3+1,vs3+2 to memory ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions > Vector Unit-Stride Segment Loads and Stores", + "line_range": [ + 1890, + 1891 + ] + }, + { + "text": "For loads, the `vd` register will hold the first field loaded from the segment.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions > Vector Unit-Stride Segment Loads and Stores", + "line_range": [ + 1893, + 1896 + ] + }, + { + "text": "For stores, the `vs3` register is read to provide the first field to be stored to each segment.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions > Vector Unit-Stride Segment Loads and Stores", + "line_range": [ + 1893, + 1896 + ] + }, + { + "text": "---- Example 1 Memory structure holds packed RGB pixels (24-bit data structure, 8bpp) vsetvli a1, t0, e8, m1, ta, ma vlseg3e8.v v8, (a0), vm v8 holds the red pixels v9 holds the green pixels v10 holds the blue pixels", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions > Vector Unit-Stride Segment Loads and Stores", + "line_range": [ + 1898, + 1905 + ] + }, + { + "text": "Example 2 Memory structure holds complex values, 32b for real and 32b for imaginary vsetvli a1, t0, e32, m1, ta, ma vlseg2e32.v v8, (a0), vm v8 holds real v9 holds imaginary ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions > Vector Unit-Stride Segment Loads and Stores", + "line_range": [ + 1907, + 1913 + ] + }, + { + "text": "There are also fault-only-first versions of the unit-stride instructions.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions > Vector Unit-Stride Segment Loads and Stores", + "line_range": [ + 1915, + 1915 + ] + }, + { + "text": "---- Template for vector fault-only-first unit-stride segment loads. vlsegeff.v vd, (rs1), vm Unit-stride fault-only-first segment loads ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions > Vector Unit-Stride Segment Loads and Stores", + "line_range": [ + 1917, + 1920 + ] + }, + { + "text": "For fault-only-first segment loads, if an exception is detected partway through accessing the zeroth segment, the trap is taken.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions > Vector Unit-Stride Segment Loads and Stores", + "line_range": [ + 1922, + 1929 + ] + }, + { + "text": "If an exception is detected partway through accessing a subsequent segment, `vl` is reduced to the index of that segment.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions > Vector Unit-Stride Segment Loads and Stores", + "line_range": [ + 1922, + 1929 + ] + }, + { + "text": "In both cases, it is implementation-defined whether a subset of the segment is loaded.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions > Vector Unit-Stride Segment Loads and Stores", + "line_range": [ + 1922, + 1929 + ] + }, + { + "text": "These instructions may overwrite destination vector register group elements past the point at which a trap is reported or past the point at which vector length is trimmed.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions > Vector Unit-Stride Segment Loads and Stores", + "line_range": [ + 1931, + 1934 + ] + }, + { + "text": "Vector constant-stride segment loads and stores move contiguous segments where each segment is separated by the byte-stride offset given in the `rs2` GPR argument.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions > Vector Constant-Stride Segment Loads and Stores", + "line_range": [ + 1938, + 1941 + ] + }, + { + "text": "NOTE: Negative and zero strides are supported.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions > Vector Constant-Stride Segment Loads and Stores", + "line_range": [ + 1943, + 1943 + ] + }, + { + "text": "---- Format vlssege.v vd, (rs1), rs2, vm Constant-stride segment loads vsssege.v vs3, (rs1), rs2, vm Constant-stride segment stores", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions > Vector Constant-Stride Segment Loads and Stores", + "line_range": [ + 1945, + 1948 + ] + }, + { + "text": "Examples vsetvli a1, t0, e8, m1, ta, ma vlsseg3e8.v v4, (x5), x6 Load bytes at addresses x5+i*x6 into v4[i], and bytes at addresses x5+i*x6+1 into v5[i], and bytes at addresses x5+i*x6+2 into v6[i].", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions > Vector Constant-Stride Segment Loads and Stores", + "line_range": [ + 1950, + 1954 + ] + }, + { + "text": "Examples vsetvli a1, t0, e32, m1, ta, ma vssseg2e32.v v2, (x5), x6 Store words from v2[i] to address x5+i*x6 and words from v3[i] to address x5+i*x6+4 ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions > Vector Constant-Stride Segment Loads and Stores", + "line_range": [ + 1956, + 1960 + ] + }, + { + "text": "Accesses to the fields within each segment can occur in any order, including the case where the byte stride is such that segments overlap in memory.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions > Vector Constant-Stride Segment Loads and Stores", + "line_range": [ + 1962, + 1965 + ] + }, + { + "text": "Vector indexed segment loads and stores move contiguous segments where each segment is located at an address given by adding the scalar base address in the `rs1` field to byte offsets in vector register `vs2`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions > Vector Indexed Segment Loads and Stores", + "line_range": [ + 1969, + 1969 + ] + }, + { + "text": "Both ordered and unordered forms are provided, where the ordered forms access segments in element order.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions > Vector Indexed Segment Loads and Stores", + "line_range": [ + 1969, + 1969 + ] + }, + { + "text": "However, even for the ordered form, accesses to the fields within an individual segment are not ordered with respect to each other.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions > Vector Indexed Segment Loads and Stores", + "line_range": [ + 1969, + 1969 + ] + }, + { + "text": "The data vector register group has EEW=SEW, EMUL=LMUL, while the index vector register group has EEW encoded in the instruction with EMUL=(EEW/SEW)*LMUL.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions > Vector Indexed Segment Loads and Stores", + "line_range": [ + 1971, + 1976 + ] + }, + { + "text": "The EMUL * NFIELDS {le} 8 constraint applies to the data vector register group.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions > Vector Indexed Segment Loads and Stores", + "line_range": [ + 1971, + 1976 + ] + }, + { + "text": "---- Format vluxsegei.v vd, (rs1), vs2, vm Indexed-unordered segment loads vloxsegei.v vd, (rs1), vs2, vm Indexed-ordered segment loads vsuxsegei.v vs3, (rs1), vs2, vm Indexed-unordered segment stores vsoxsegei.v vs3, (rs1), vs2, vm Indexed-ordered segment stores", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions > Vector Indexed Segment Loads and Stores", + "line_range": [ + 1978, + 1983 + ] + }, + { + "text": "Examples vsetvli a1, t0, e8, m1, ta, ma vluxseg3ei8.v v4, (x5), v3 Load bytes at addresses x5+v3[i] into v4[i], and bytes at addresses x5+v3[i]+1 into v5[i], and bytes at addresses x5+v3[i]+2 into v6[i].", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions > Vector Indexed Segment Loads and Stores", + "line_range": [ + 1985, + 1989 + ] + }, + { + "text": "Examples vsetvli a1, t0, e32, m1, ta, ma vsuxseg2ei32.v v2, (x5), v5 Store words from v2[i] to address x5+v5[i] and words from v3[i] to address x5+v5[i]+4 ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions > Vector Indexed Segment Loads and Stores", + "line_range": [ + 1991, + 1995 + ] + }, + { + "text": "For vector indexed segment loads, the destination vector register groups cannot overlap the source vector register group (specified by `vs2`), else the instruction encoding is reserved.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions > Vector Indexed Segment Loads and Stores", + "line_range": [ + 1997, + 2000 + ] + }, + { + "text": "NOTE: This constraint supports restart of indexed segment loads that raise exceptions partway through loading a structure.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Segment Instructions > Vector Indexed Segment Loads and Stores", + "line_range": [ + 2002, + 2003 + ] + }, + { + "text": "Format for Vector Load Whole Register Instructions under LOAD-FP major opcode", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "line_range": [ + 2007, + 2007 + ] + }, + { + "text": "[wavedrom,,svg] .... {reg: [ {bits: 7, name: 0x07, attr: 'VL*R*'}, {bits: 5, name: 'vd', attr: 'destination of load', type: 2}, {bits: 3, name: 'width'}, {bits: 5, name: 'rs1', attr: 'base address', type: 4}, {bits: 5, name: 8, attr: 'lumop'}, {bits: 1, name: 1, attr: 'vm'}, {bits: 2, name: 0x10000, attr: 'mop'}, {bits: 1, name: 'mew'}, {bits: 3, name: 'nf'}, ]} ....", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "line_range": [ + 2014, + 2027 + ] + }, + { + "text": "Format for Vector Store Whole Register Instructions under STORE-FP major opcode", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "line_range": [ + 2029, + 2029 + ] + }, + { + "text": "[wavedrom,,svg] .... {reg: [ {bits: 7, name: 0x27, attr: 'VS*R*'}, {bits: 5, name: 'vs3', attr: 'store data', type: 2}, {bits: 3, name: 0x1000}, {bits: 5, name: 'rs1', attr: 'base address', type: 4}, {bits: 5, name: 8, attr: 'sumop'}, {bits: 1, name: 1, attr: 'vm'}, {bits: 2, name: 0x100, attr: 'mop'}, {bits: 1, name: 0x100, attr: 'mew'}, {bits: 3, name: 'nf'}, ]} ....", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "line_range": [ + 2036, + 2049 + ] + }, + { + "text": "These instructions load and store whole vector register groups.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "line_range": [ + 2051, + 2051 + ] + }, + { + "text": "NOTE: These instructions are intended to be used to save and restore vector registers when the type or length of the current contents of the vector register is not known, or where modifying `vl` and `vtype` would be costly.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "line_range": [ + 2053, + 2059 + ] + }, + { + "text": "Examples include compiler register spills, vector function calls where values are passed in vector registers, interrupt handlers, and OS context switches.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "line_range": [ + 2053, + 2059 + ] + }, + { + "text": "Software can determine the number of bytes transferred by reading the `vlenb` register.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "line_range": [ + 2053, + 2059 + ] + }, + { + "text": "The load instructions have an EEW encoded in the `mew` and `width` fields following the pattern of regular unit-stride loads.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "line_range": [ + 2061, + 2063 + ] + }, + { + "text": "NOTE: Because in-register byte layouts are identical to in-memory byte layouts, the same data is written to the destination register group regardless of EEW.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "line_range": [ + 2065, + 2071 + ] + }, + { + "text": "Hence, it would have sufficed to provide only EEW=8 variants.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "line_range": [ + 2065, + 2071 + ] + }, + { + "text": "The full set of EEW variants is provided so that the encoded EEW can be used as a hint to indicate the destination register group will next be accessed with this EEW, which aids implementations that rearrange data internally.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "line_range": [ + 2065, + 2071 + ] + }, + { + "text": "The vector whole register store instructions are encoded similar to unmasked unit-stride store of elements with EEW=8.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "line_range": [ + 2073, + 2074 + ] + }, + { + "text": "The `nf` field encodes how many vector registers to load and store using the NFIELDS encoding (Figure ).", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "line_range": [ + 2076, + 2085 + ] + }, + { + "text": "The encoded number of registers must be a power of 2 and the vector register numbers must be aligned as with a vector register group, otherwise the instruction encoding is reserved. NFIELDS indicates the number of vector registers to transfer, numbered successively after the base.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "line_range": [ + 2076, + 2085 + ] + }, + { + "text": "Only NFIELDS values of 1, 2, 4, 8 are supported, with other values reserved.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "line_range": [ + 2076, + 2085 + ] + }, + { + "text": "When multiple registers are transferred, the lowest-numbered vector register is held in the lowest-numbered memory addresses and successive vector register numbers are placed contiguously in memory.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "line_range": [ + 2076, + 2085 + ] + }, + { + "text": "The instructions operate with an effective vector length, `evl`=NFIELDS*VLEN/EEW, regardless of current settings in `vtype` and `vl`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "line_range": [ + 2087, + 2095 + ] + }, + { + "text": "The usual property that no elements are written if `vstart` {ge} `vl` does not apply to these instructions.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "line_range": [ + 2087, + 2095 + ] + }, + { + "text": "Similarly, the property that the instructions are reserved if `vstart` exceeds the largest element index for the current `vtype` setting does not apply.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "line_range": [ + 2087, + 2095 + ] + }, + { + "text": "Instead, the instructions are reserved if `vstart` {ge} `evl`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "line_range": [ + 2087, + 2095 + ] + }, + { + "text": "The instructions operate similarly to unmasked unit-stride load and store instructions, with the base address passed in the scalar `x` register specified by `rs1`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "line_range": [ + 2097, + 2099 + ] + }, + { + "text": "Implementations are allowed to raise a misaligned address exception on whole register loads and stores if the base address is not naturally aligned to the larger of the size of the encoded EEW in bytes (EEW/8) or the implementation's smallest supported SEW size in bytes (SEW~MIN~/8).", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "line_range": [ + 2101, + 2106 + ] + }, + { + "text": "NOTE: Allowing misaligned exceptions to be raised based on non-alignment to the encoded EEW simplifies the implementation of these instructions.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "line_range": [ + 2108, + 2115 + ] + }, + { + "text": "Some subset implementations might not support smaller SEW widths, so are allowed to report misaligned exceptions for the smallest supported SEW even if larger than encoded EEW.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "line_range": [ + 2108, + 2115 + ] + }, + { + "text": "An extreme non-standard implementation might have SEW~MIN~>XLEN for example.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "line_range": [ + 2108, + 2115 + ] + }, + { + "text": "Software environments can mandate the minimum alignment requirements to support an ABI.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "line_range": [ + 2108, + 2115 + ] + }, + { + "text": "---- Format of whole register load and store instructions. vl1r.v v3, (a0) Pseudoinstruction equal to vl1re8.v", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "line_range": [ + 2117, + 2119 + ] + }, + { + "text": "vl1re8.v v3, (a0) Load v3 with VLEN/8 bytes held at address in a0 vl1re16.v v3, (a0) Load v3 with VLEN/16 halfwords held at address in a0 vl1re32.v v3, (a0) Load v3 with VLEN/32 words held at address in a0 vl1re64.v v3, (a0) Load v3 with VLEN/64 doublewords held at address in a0", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "line_range": [ + 2121, + 2124 + ] + }, + { + "text": "vl2r.v v2, (a0) Pseudoinstruction equal to vl2re8.v", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "line_range": [ + 2126, + 2126 + ] + }, + { + "text": "vl2re8.v v2, (a0) Load v2-v3 with 2*VLEN/8 bytes from address in a0 vl2re16.v v2, (a0) Load v2-v3 with 2*VLEN/16 halfwords held at address in a0 vl2re32.v v2, (a0) Load v2-v3 with 2*VLEN/32 words held at address in a0 vl2re64.v v2, (a0) Load v2-v3 with 2*VLEN/64 doublewords held at address in a0", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "line_range": [ + 2128, + 2131 + ] + }, + { + "text": "vl4r.v v4, (a0) Pseudoinstruction equal to vl4re8.v", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "line_range": [ + 2133, + 2133 + ] + }, + { + "text": "vl4re8.v v4, (a0) Load v4-v7 with 4*VLEN/8 bytes from address in a0 vl4re16.v v4, (a0) vl4re32.v v4, (a0) vl4re64.v v4, (a0)", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "line_range": [ + 2135, + 2138 + ] + }, + { + "text": "vl8r.v v8, (a0) Pseudoinstruction equal to vl8re8.v", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "line_range": [ + 2140, + 2140 + ] + }, + { + "text": "vl8re8.v v8, (a0) Load v8-v15 with 8*VLEN/8 bytes from address in a0 vl8re16.v v8, (a0) vl8re32.v v8, (a0) vl8re64.v v8, (a0)", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "line_range": [ + 2142, + 2145 + ] + }, + { + "text": "vs1r.v v3, (a1) Store v3 to address in a1 vs2r.v v2, (a1) Store v2-v3 to address in a1 vs4r.v v4, (a1) Store v4-v7 to address in a1 vs8r.v v8, (a1) Store v8-v15 to address in a1 ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "line_range": [ + 2147, + 2151 + ] + }, + { + "text": "NOTE: We have considered adding a whole register mask load instruction (`vl1rm.v`) but have decided to omit from initial extension.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "line_range": [ + 2153, + 2168 + ] + }, + { + "text": "The primary purpose would be to inform the microarchitecture that the data will be used as a mask.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "line_range": [ + 2153, + 2168 + ] + }, + { + "text": "The same effect can be achieved with the following code sequence, whose cost is at most four instructions.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "line_range": [ + 2153, + 2168 + ] + }, + { + "text": "Of these, the first could likely be removed as `vl` is often already in a scalar register, and the last might already be present if the following vector instruction needs a new SEW/LMUL.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "line_range": [ + 2153, + 2168 + ] + }, + { + "text": "So, in best case only two instructions (of which only one performs vector operations) are needed to synthesize the effect of the dedicated instruction: ---- csrr t0, vl Save current vl (potentially not needed) vsetvli t1, x0, e8, m8, ta, ma Maximum VLMAX vlm.v v0, (a0) Load mask register vsetvli x0, t0, Restore vl (potentially already present) ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Loads and Stores > Vector Load/Store Whole Register Instructions", + "line_range": [ + 2153, + 2168 + ] + }, + { + "text": "If an element accessed by a vector memory instruction is not naturally aligned to the size of the element, either the element is transferred successfully or an address-misaligned exception is raised on that element.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Memory Alignment Constraints", + "line_range": [ + 2173, + 2177 + ] + }, + { + "text": "Support for misaligned vector memory accesses is independent of an implementation's support for misaligned scalar memory accesses.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Memory Alignment Constraints", + "line_range": [ + 2179, + 2181 + ] + }, + { + "text": "NOTE: An implementation may have neither, one, or both scalar and vector memory accesses support some or all misaligned accesses in hardware. A separate PMA should be defined to determine if vector misaligned accesses are supported in the associated address range.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Memory Alignment Constraints", + "line_range": [ + 2183, + 2186 + ] + }, + { + "text": "Vector misaligned memory accesses follow the same rules for atomicity as scalar misaligned memory accesses.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Memory Alignment Constraints", + "line_range": [ + 2188, + 2190 + ] + }, + { + "text": "Vector memory instructions appear to execute in program order on the local hart.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Memory Consistency Model", + "line_range": [ + 2194, + 2196 + ] + }, + { + "text": "Vector memory instructions follow RVWMO at the instruction level.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Memory Consistency Model", + "line_range": [ + 2198, + 2199 + ] + }, + { + "text": "If the Ztso extension is implemented, vector memory instructions additionally follow RVTSO at the instruction level.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Memory Consistency Model", + "line_range": [ + 2198, + 2199 + ] + }, + { + "text": "Except for vector indexed-ordered loads and stores, element operations are unordered within the instruction.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Memory Consistency Model", + "line_range": [ + 2201, + 2203 + ] + }, + { + "text": "Vector indexed-ordered loads and stores read and write elements from/to memory in element order respectively, obeying RVWMO at the element level.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Memory Consistency Model", + "line_range": [ + 2205, + 2208 + ] + }, + { + "text": "NOTE: Ztso only imposes RVTSO at the instruction level; intra-instruction ordering follows RVWMO regardless of whether Ztso is implemented.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Memory Consistency Model", + "line_range": [ + 2210, + 2211 + ] + }, + { + "text": "NOTE: More formal definitions required.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Memory Consistency Model", + "line_range": [ + 2213, + 2213 + ] + }, + { + "text": "Instructions affected by the vector length register `vl` have a control dependency on `vl`, rather than a data dependency.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Memory Consistency Model", + "line_range": [ + 2215, + 2220 + ] + }, + { + "text": "Similarly, masked vector instructions have a control dependency on the source mask register, rather than a data dependency.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Memory Consistency Model", + "line_range": [ + 2215, + 2220 + ] + }, + { + "text": "NOTE: Treating the vector length and mask as control rather than data typically matches the semantics of the corresponding scalar code, where branch instructions ordinarily would have been used.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Memory Consistency Model", + "line_range": [ + 2222, + 2227 + ] + }, + { + "text": "Treating the mask as control allows masked vector load instructions to access memory before the mask value is known, without the need for a misspeculation-recovery mechanism.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Memory Consistency Model", + "line_range": [ + 2222, + 2227 + ] + }, + { + "text": "The vector arithmetic instructions use a new major opcode (OP-V = 1010111~2~) which neighbors OP-FP.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats", + "line_range": [ + 2231, + 2233 + ] + }, + { + "text": "The three-bit `funct3` field is used to define sub-categories of vector instructions.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats", + "line_range": [ + 2231, + 2233 + ] + }, + { + "text": "The `funct3` field encodes the operand type and source locations.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Vector Arithmetic Instruction encoding", + "line_range": [ + 2240, + 2240 + ] + }, + { + "text": ".funct3 [cols=\"1,1,1,3,5,5\"] | 3+| funct3[2:0] | Category | Operands | Type of scalar operand", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Vector Arithmetic Instruction encoding", + "line_range": [ + 2242, + 2245 + ] + }, + { + "text": "| 0 | 0 | 0 | OPIVV | vector-vector | N/A | 0 | 0 | 1 | OPFVV | vector-vector | N/A | 0 | 1 | 0 | OPMVV | vector-vector | N/A | 0 | 1 | 1 | OPIVI | vector-immediate | `imm[4:0]` | 1 | 0 | 0 | OPIVX | vector-scalar | GPR `x` register `rs1` | 1 | 0 | 1 | OPFVF | vector-scalar | FP `f` register `rs1` | 1 | 1 | 0 | OPMVX | vector-scalar | GPR `x` register `rs1` | 1 | 1 | 1 | OPCFG | scalars-imms | GPR `x` register `rs1` & `rs2`/`imm` |", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Vector Arithmetic Instruction encoding", + "line_range": [ + 2247, + 2255 + ] + }, + { + "text": "Integer operations are performed using unsigned or two's-complement signed integer arithmetic depending on the opcode.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Vector Arithmetic Instruction encoding", + "line_range": [ + 2257, + 2258 + ] + }, + { + "text": "NOTE: In this discussion, fixed-point operations are considered to be integer operations.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Vector Arithmetic Instruction encoding", + "line_range": [ + 2260, + 2261 + ] + }, + { + "text": "All standard vector floating-point arithmetic operations follow the IEEE 754-2008 arithmetic standard.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Vector Arithmetic Instruction encoding", + "line_range": [ + 2263, + 2267 + ] + }, + { + "text": "All vector floating-point operations use the dynamic rounding mode in the `frm` register.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Vector Arithmetic Instruction encoding", + "line_range": [ + 2263, + 2267 + ] + }, + { + "text": "Use of the `frm` field when it contains an invalid rounding mode by any vector floating-point instruction--even those that do not depend on the rounding mode, or when `vl`=0, or when `vstart` {ge} `vl`--is reserved.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Vector Arithmetic Instruction encoding", + "line_range": [ + 2263, + 2267 + ] + }, + { + "text": "NOTE: All vector floating-point code will rely on a valid value in `frm`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Vector Arithmetic Instruction encoding", + "line_range": [ + 2269, + 2272 + ] + }, + { + "text": "Implementations can make all vector FP instructions report exceptions when the rounding mode is invalid to simplify control logic.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Vector Arithmetic Instruction encoding", + "line_range": [ + 2269, + 2272 + ] + }, + { + "text": "Vector-vector operations take two vectors of operands from vector register groups specified by `vs2` and `vs1` respectively.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Vector Arithmetic Instruction encoding", + "line_range": [ + 2274, + 2276 + ] + }, + { + "text": "Vector-scalar operations can have three possible forms.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Vector Arithmetic Instruction encoding", + "line_range": [ + 2278, + 2280 + ] + }, + { + "text": "In all three forms, the vector register group operand is specified by `vs2`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Vector Arithmetic Instruction encoding", + "line_range": [ + 2278, + 2280 + ] + }, + { + "text": "The second scalar source operand comes from one of three alternative sources:", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Vector Arithmetic Instruction encoding", + "line_range": [ + 2278, + 2280 + ] + }, + { + "text": "For integer operations, the scalar can be a 5-bit immediate, `imm[4:0]`, encoded in the `rs1` field.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Vector Arithmetic Instruction encoding", + "line_range": [ + 2282, + 2283 + ] + }, + { + "text": "The value is sign-extended to SEW bits, unless otherwise specified.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Vector Arithmetic Instruction encoding", + "line_range": [ + 2282, + 2283 + ] + }, + { + "text": "For integer operations, the scalar can be taken from the scalar `x` register specified by `rs1`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Vector Arithmetic Instruction encoding", + "line_range": [ + 2285, + 2287 + ] + }, + { + "text": "If XLEN>SEW, the least-significant SEW bits of the `x` register are used, unless otherwise specified.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Vector Arithmetic Instruction encoding", + "line_range": [ + 2285, + 2287 + ] + }, + { + "text": "If XLEN \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Vector Arithmetic Instruction encoding", + "line_range": [ + 2285, + 2287 + ] + }, + { + "text": "For floating-point operations, the scalar can be taken from a scalar `f` register.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Vector Arithmetic Instruction encoding", + "line_range": [ + 2289, + 2295 + ] + }, + { + "text": "If FLEN > SEW, the value in the `f` registers is checked for a valid NaN-boxed value, in which case the least-significant SEW bits of the `f` register are used, else the canonical NaN value is used.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Vector Arithmetic Instruction encoding", + "line_range": [ + 2289, + 2295 + ] + }, + { + "text": "Vector instructions where any floating-point vector operand's EEW is not a supported floating-point type width (which includes when FLEN < SEW) are reserved.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Vector Arithmetic Instruction encoding", + "line_range": [ + 2289, + 2295 + ] + }, + { + "text": "NOTE: Some instructions zero-extend the 5-bit immediate, and denote this by naming the immediate `uimm` in the assembly syntax.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Vector Arithmetic Instruction encoding", + "line_range": [ + 2297, + 2298 + ] + }, + { + "text": "When adding a vector extension to the Zfinx/Zdinx/Zhinx extensions, floating-point scalar arguments are taken from the `x` registers.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Vector Arithmetic Instruction encoding", + "line_range": [ + 2300, + 2304 + ] + }, + { + "text": "NaN-boxing is not supported in these extensions, and so operands narrower than XLEN bits are not checked for a NaN box; bits XLEN-1:EEW are ignored.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Vector Arithmetic Instruction encoding", + "line_range": [ + 2300, + 2304 + ] + }, + { + "text": "For RV32Zdinx, EEW=64 scalar arguments are supplied by an `x`-register pair.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Vector Arithmetic Instruction encoding", + "line_range": [ + 2300, + 2304 + ] + }, + { + "text": "Vector arithmetic instructions are masked under control of the `vm` field.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Vector Arithmetic Instruction encoding", + "line_range": [ + 2306, + 2307 + ] + }, + { + "text": "---- Assembly syntax pattern for vector binary arithmetic instructions", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Vector Arithmetic Instruction encoding", + "line_range": [ + 2309, + 2310 + ] + }, + { + "text": "Operations returning vector results, masked by vm (v0.t, ) vop.vv vd, vs2, vs1, vm integer vector-vector vd[i] = vs2[i] op vs1[i] vop.vx vd, vs2, rs1, vm integer vector-scalar vd[i] = vs2[i] op x[rs1] vop.vi vd, vs2, imm, vm integer vector-immediate vd[i] = vs2[i] op imm", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Vector Arithmetic Instruction encoding", + "line_range": [ + 2312, + 2315 + ] + }, + { + "text": "vfop.vv vd, vs2, vs1, vm FP vector-vector operation vd[i] = vs2[i] fop vs1[i] vfop.vf vd, vs2, rs1, vm FP vector-scalar operation vd[i] = vs2[i] fop f[rs1] ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Vector Arithmetic Instruction encoding", + "line_range": [ + 2317, + 2319 + ] + }, + { + "text": "NOTE: In the encoding, `vs2` is the first operand, while `rs1/imm` is the second operand.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Vector Arithmetic Instruction encoding", + "line_range": [ + 2321, + 2325 + ] + }, + { + "text": "This is the opposite to the standard scalar ordering.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Vector Arithmetic Instruction encoding", + "line_range": [ + 2321, + 2325 + ] + }, + { + "text": "This arrangement retains the existing encoding conventions that instructions that read only one scalar register, read it from `rs1`, and that 5-bit immediates are sourced from the `rs1` field.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Vector Arithmetic Instruction encoding", + "line_range": [ + 2321, + 2325 + ] + }, + { + "text": "---- Assembly syntax pattern for vector ternary arithmetic instructions (multiply-add)", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Vector Arithmetic Instruction encoding", + "line_range": [ + 2327, + 2328 + ] + }, + { + "text": "Integer operations overwriting sum input vop.vv vd, vs1, vs2, vm vd[i] = vs1[i] * vs2[i] + vd[i] vop.vx vd, rs1, vs2, vm vd[i] = x[rs1] * vs2[i] + vd[i]", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Vector Arithmetic Instruction encoding", + "line_range": [ + 2330, + 2332 + ] + }, + { + "text": "Integer operations overwriting product input vop.vv vd, vs1, vs2, vm vd[i] = vs1[i] * vd[i] + vs2[i] vop.vx vd, rs1, vs2, vm vd[i] = x[rs1] * vd[i] + vs2[i]", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Vector Arithmetic Instruction encoding", + "line_range": [ + 2334, + 2336 + ] + }, + { + "text": "Floating-point operations overwriting sum input vfop.vv vd, vs1, vs2, vm vd[i] = vs1[i] * vs2[i] + vd[i] vfop.vf vd, rs1, vs2, vm vd[i] = f[rs1] * vs2[i] + vd[i]", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Vector Arithmetic Instruction encoding", + "line_range": [ + 2338, + 2340 + ] + }, + { + "text": "Floating-point operations overwriting product input vfop.vv vd, vs1, vs2, vm vd[i] = vs1[i] * vd[i] + vs2[i] vfop.vf vd, rs1, vs2, vm vd[i] = f[rs1] * vd[i] + vs2[i] ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Vector Arithmetic Instruction encoding", + "line_range": [ + 2342, + 2345 + ] + }, + { + "text": "NOTE: For ternary multiply-add operations, the assembler syntax always places the destination vector register first, followed by either `rs1` or `vs1`, then `vs2`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Vector Arithmetic Instruction encoding", + "line_range": [ + 2347, + 2351 + ] + }, + { + "text": "This ordering provides a more natural reading of the assembler for these ternary operations, as the multiply operands are always next to each other.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Vector Arithmetic Instruction encoding", + "line_range": [ + 2347, + 2351 + ] + }, + { + "text": "A few vector arithmetic instructions are defined to be widening operations where the destination vector register group has EEW=2*SEW and EMUL=2*LMUL.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Widening Vector Arithmetic Instructions", + "line_range": [ + 2356, + 2359 + ] + }, + { + "text": "These are generally given a `vw*` prefix on the opcode, or `vfw*` for vector floating-point instructions.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Widening Vector Arithmetic Instructions", + "line_range": [ + 2356, + 2359 + ] + }, + { + "text": "The first vector register group operand can be either single or double-width.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Widening Vector Arithmetic Instructions", + "line_range": [ + 2361, + 2362 + ] + }, + { + "text": "---- Assembly syntax pattern for vector widening arithmetic instructions", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Widening Vector Arithmetic Instructions", + "line_range": [ + 2364, + 2365 + ] + }, + { + "text": "Double-width result, two single-width sources: 2*SEW = SEW op SEW vwop.vv vd, vs2, vs1, vm integer vector-vector vd[i] = vs2[i] op vs1[i] vwop.vx vd, vs2, rs1, vm integer vector-scalar vd[i] = vs2[i] op x[rs1]", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Widening Vector Arithmetic Instructions", + "line_range": [ + 2367, + 2369 + ] + }, + { + "text": "Double-width result, first source double-width, second source single-width: 2*SEW = 2*SEW op SEW vwop.wv vd, vs2, vs1, vm integer vector-vector vd[i] = vs2[i] op vs1[i] vwop.wx vd, vs2, rs1, vm integer vector-scalar vd[i] = vs2[i] op x[rs1] ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Widening Vector Arithmetic Instructions", + "line_range": [ + 2371, + 2374 + ] + }, + { + "text": "NOTE: Originally, a `w` suffix was used on opcode, but this could be confused with the use of a `w` suffix to mean word-sized operations in doubleword integers, so the `w` was moved to prefix.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Widening Vector Arithmetic Instructions", + "line_range": [ + 2376, + 2378 + ] + }, + { + "text": "NOTE: The floating-point widening operations were changed to `vfw*` from `vwf*` to be more consistent with any scalar widening floating-point operations that will be written as `fw*`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Widening Vector Arithmetic Instructions", + "line_range": [ + 2380, + 2382 + ] + }, + { + "text": "Widening instruction encodings must follow the constraints in .", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Widening Vector Arithmetic Instructions", + "line_range": [ + 2384, + 2385 + ] + }, + { + "text": "A few instructions are provided to convert double-width source vectors into single-width destination vectors.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Narrowing Vector Arithmetic Instructions", + "line_range": [ + 2390, + 2395 + ] + }, + { + "text": "These instructions convert a vector register group specified by `vs2` with EEW/EMUL=2*SEW/2*LMUL to a vector register group with the current SEW/LMUL setting.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Narrowing Vector Arithmetic Instructions", + "line_range": [ + 2390, + 2395 + ] + }, + { + "text": "Where there is a second source vector register group (specified by `vs1`), this has the same (narrower) width as the result (i.e., EEW=SEW).", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Narrowing Vector Arithmetic Instructions", + "line_range": [ + 2390, + 2395 + ] + }, + { + "text": "NOTE: An alternative design decision would have been to treat SEW/LMUL as defining the size of the source vector register group.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Narrowing Vector Arithmetic Instructions", + "line_range": [ + 2397, + 2400 + ] + }, + { + "text": "The choice here is motivated by the belief the chosen approach will require fewer `vtype` changes.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Narrowing Vector Arithmetic Instructions", + "line_range": [ + 2397, + 2400 + ] + }, + { + "text": "NOTE: Compare operations that set a mask register are also implicitly a narrowing operation.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Narrowing Vector Arithmetic Instructions", + "line_range": [ + 2402, + 2403 + ] + }, + { + "text": "A `vn*` prefix on the opcode is used to distinguish these instructions in the assembler, or a `vfn*` prefix for narrowing floating-point opcodes.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Narrowing Vector Arithmetic Instructions", + "line_range": [ + 2405, + 2408 + ] + }, + { + "text": "The double-width source vector register group is signified by a `w` in the source operand suffix (e.g., `vnsra.wv`)", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Narrowing Vector Arithmetic Instructions", + "line_range": [ + 2405, + 2408 + ] + }, + { + "text": "---- Assembly syntax pattern for vector narrowing arithmetic instructions", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Narrowing Vector Arithmetic Instructions", + "line_range": [ + 2410, + 2411 + ] + }, + { + "text": "Single-width result vd, double-width source vs2, single-width source vs1/rs1 SEW = 2*SEW op SEW vnop.wv vd, vs2, vs1, vm integer vector-vector vd[i] = vs2[i] op vs1[i] vnop.wx vd, vs2, rs1, vm integer vector-scalar vd[i] = vs2[i] op x[rs1] ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Narrowing Vector Arithmetic Instructions", + "line_range": [ + 2413, + 2417 + ] + }, + { + "text": "Narrowing instruction encodings must follow the constraints in .", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Arithmetic Instruction Formats > Narrowing Vector Arithmetic Instructions", + "line_range": [ + 2419, + 2420 + ] + }, + { + "text": "A set of vector integer arithmetic instructions is provided.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions", + "line_range": [ + 2425, + 2426 + ] + }, + { + "text": "Unless otherwise stated, integer operations wrap around on overflow.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions", + "line_range": [ + 2425, + 2426 + ] + }, + { + "text": "Vector integer add and subtract are provided.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Single-Width Integer Add and Subtract", + "line_range": [ + 2430, + 2431 + ] + }, + { + "text": "Reverse-subtract instructions are also provided for the vector-scalar forms.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Single-Width Integer Add and Subtract", + "line_range": [ + 2430, + 2431 + ] + }, + { + "text": "---- Integer adds. vadd.vv vd, vs2, vs1, vm Vector-vector vadd.vx vd, vs2, rs1, vm vector-scalar vadd.vi vd, vs2, imm, vm vector-immediate", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Single-Width Integer Add and Subtract", + "line_range": [ + 2433, + 2437 + ] + }, + { + "text": "Integer subtract vsub.vv vd, vs2, vs1, vm Vector-vector vsub.vx vd, vs2, rs1, vm vector-scalar", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Single-Width Integer Add and Subtract", + "line_range": [ + 2439, + 2441 + ] + }, + { + "text": "Integer reverse subtract vrsub.vx vd, vs2, rs1, vm vd[i] = x[rs1] - vs2[i] vrsub.vi vd, vs2, imm, vm vd[i] = imm - vs2[i] ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Single-Width Integer Add and Subtract", + "line_range": [ + 2443, + 2446 + ] + }, + { + "text": "NOTE: A vector of integer values can be negated using a reverse-subtract instruction with a scalar operand of `x0`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Single-Width Integer Add and Subtract", + "line_range": [ + 2448, + 2450 + ] + }, + { + "text": "An assembly pseudoinstruction `vneg.v vd,vs` = `vrsub.vx vd,vs,x0` is provided.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Single-Width Integer Add and Subtract", + "line_range": [ + 2448, + 2450 + ] + }, + { + "text": "The widening add/subtract instructions are provided in both signed and unsigned variants, depending on whether the narrower source operands are first sign- or zero-extended before forming the double-width sum.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Widening Integer Add/Subtract", + "line_range": [ + 2454, + 2456 + ] + }, + { + "text": "---- Widening unsigned integer add/subtract, 2*SEW = SEW +/- SEW vwaddu.vv vd, vs2, vs1, vm vector-vector vwaddu.vx vd, vs2, rs1, vm vector-scalar vwsubu.vv vd, vs2, vs1, vm vector-vector vwsubu.vx vd, vs2, rs1, vm vector-scalar", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Widening Integer Add/Subtract", + "line_range": [ + 2458, + 2463 + ] + }, + { + "text": "Widening signed integer add/subtract, 2*SEW = SEW +/- SEW vwadd.vv vd, vs2, vs1, vm vector-vector vwadd.vx vd, vs2, rs1, vm vector-scalar vwsub.vv vd, vs2, vs1, vm vector-vector vwsub.vx vd, vs2, rs1, vm vector-scalar", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Widening Integer Add/Subtract", + "line_range": [ + 2465, + 2469 + ] + }, + { + "text": "Widening unsigned integer add/subtract, 2*SEW = 2*SEW +/- SEW vwaddu.wv vd, vs2, vs1, vm vector-vector vwaddu.wx vd, vs2, rs1, vm vector-scalar vwsubu.wv vd, vs2, vs1, vm vector-vector vwsubu.wx vd, vs2, rs1, vm vector-scalar", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Widening Integer Add/Subtract", + "line_range": [ + 2471, + 2475 + ] + }, + { + "text": "Widening signed integer add/subtract, 2*SEW = 2*SEW +/- SEW vwadd.wv vd, vs2, vs1, vm vector-vector vwadd.wx vd, vs2, rs1, vm vector-scalar vwsub.wv vd, vs2, vs1, vm vector-vector vwsub.wx vd, vs2, rs1, vm vector-scalar ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Widening Integer Add/Subtract", + "line_range": [ + 2477, + 2482 + ] + }, + { + "text": "NOTE: An integer value can be doubled in width using the widening add instructions with a scalar operand of `x0`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Widening Integer Add/Subtract", + "line_range": [ + 2484, + 2487 + ] + }, + { + "text": "Assembly pseudoinstructions `vwcvt.x.x.v vd,vs,vm` = `vwadd.vx vd,vs,x0,vm` and `vwcvtu.x.x.v vd,vs,vm` = `vwaddu.vx vd,vs,x0,vm` are provided.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Widening Integer Add/Subtract", + "line_range": [ + 2484, + 2487 + ] + }, + { + "text": "The vector integer extension instructions zero- or sign-extend a source vector integer operand with EEW less than SEW to fill SEW-sized elements in the destination.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Extension", + "line_range": [ + 2491, + 2495 + ] + }, + { + "text": "The EEW of the source is 1/2, 1/4, or 1/8 of SEW, while EMUL of the source is (EEW/SEW)*LMUL.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Extension", + "line_range": [ + 2491, + 2495 + ] + }, + { + "text": "The destination has EEW equal to SEW and EMUL equal to LMUL.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Extension", + "line_range": [ + 2491, + 2495 + ] + }, + { + "text": "---- vzext.vf2 vd, vs2, vm Zero-extend SEW/2 source to SEW destination vsext.vf2 vd, vs2, vm Sign-extend SEW/2 source to SEW destination vzext.vf4 vd, vs2, vm Zero-extend SEW/4 source to SEW destination vsext.vf4 vd, vs2, vm Sign-extend SEW/4 source to SEW destination vzext.vf8 vd, vs2, vm Zero-extend SEW/8 source to SEW destination vsext.vf8 vd, vs2, vm Sign-extend SEW/8 source to SEW destination ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Extension", + "line_range": [ + 2497, + 2504 + ] + }, + { + "text": "If the source EEW is not a supported width, or source EMUL would be below the minimum legal LMUL, the instruction encoding is reserved.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Extension", + "line_range": [ + 2506, + 2507 + ] + }, + { + "text": "NOTE: Standard vector load instructions access memory values that are the same size as the destination register elements.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Extension", + "line_range": [ + 2509, + 2517 + ] + }, + { + "text": "Some application code needs to operate on a range of operand widths in a wider element, for example, loading a byte from memory and adding to an eight-byte element.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Extension", + "line_range": [ + 2509, + 2517 + ] + }, + { + "text": "To avoid having to provide the cross-product of the number of vector load instructions by the number of data types (byte, word, halfword, and also signed/unsigned variants), we instead add explicit extension instructions that can be used if an appropriate widening arithmetic instruction is not available.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Extension", + "line_range": [ + 2509, + 2517 + ] + }, + { + "text": "To support multi-word integer arithmetic, instructions that operate on a carry bit are provided.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions", + "line_range": [ + 2521, + 2525 + ] + }, + { + "text": "For each operation (add or subtract), two instructions are provided: one to provide the result (SEW width), and the second to generate the carry output (single bit encoded as a mask boolean).", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions", + "line_range": [ + 2521, + 2525 + ] + }, + { + "text": "The carry inputs and outputs are represented using the mask register layout as described in .", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions", + "line_range": [ + 2527, + 2531 + ] + }, + { + "text": "Due to encoding constraints, the carry input must come from the implicit `v0` register, but carry outputs can be written to any vector register that respects the source/destination overlap restrictions.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions", + "line_range": [ + 2527, + 2531 + ] + }, + { + "text": "`vadc` and `vsbc` add or subtract the source operands and the carry-in or borrow-in, and write the result to vector register `vd`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions", + "line_range": [ + 2533, + 2537 + ] + }, + { + "text": "These instructions are encoded as masked instructions (`vm=0`), but they operate on and write back all body elements.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions", + "line_range": [ + 2533, + 2537 + ] + }, + { + "text": "Encodings corresponding to the unmasked versions (`vm=1`) are reserved.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions", + "line_range": [ + 2533, + 2537 + ] + }, + { + "text": "`vmadc` and `vmsbc` add or subtract the source operands, optionally add the carry-in or subtract the borrow-in if masked (`vm=0`), and write the resulting carry-out or borrow-out back to mask register `vd`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions", + "line_range": [ + 2539, + 2545 + ] + }, + { + "text": "If unmasked (`vm=1`), there is no carry-in or borrow-in.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions", + "line_range": [ + 2539, + 2545 + ] + }, + { + "text": "These instructions operate on and write back all body elements, even if masked.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions", + "line_range": [ + 2539, + 2545 + ] + }, + { + "text": "Because these instructions produce a mask value, they always operate with a tail-agnostic policy.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions", + "line_range": [ + 2539, + 2545 + ] + }, + { + "text": "---- Produce sum with carry.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions", + "line_range": [ + 2547, + 2548 + ] + }, + { + "text": "vd[i] = vs2[i] + vs1[i] + v0.mask[i] vadc.vvm vd, vs2, vs1, v0 Vector-vector", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions", + "line_range": [ + 2550, + 2551 + ] + }, + { + "text": "vd[i] = vs2[i] + x[rs1] + v0.mask[i] vadc.vxm vd, vs2, rs1, v0 Vector-scalar", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions", + "line_range": [ + 2553, + 2554 + ] + }, + { + "text": "vd[i] = vs2[i] + imm + v0.mask[i] vadc.vim vd, vs2, imm, v0 Vector-immediate", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions", + "line_range": [ + 2556, + 2557 + ] + }, + { + "text": "Produce carry out in mask register format", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions", + "line_range": [ + 2559, + 2559 + ] + }, + { + "text": "vd.mask[i] = carryout(vs2[i] + vs1[i] + v0.mask[i]) vmadc.vvm vd, vs2, vs1, v0 Vector-vector", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions", + "line_range": [ + 2561, + 2562 + ] + }, + { + "text": "vd.mask[i] = carryout(vs2[i] + x[rs1] + v0.mask[i]) vmadc.vxm vd, vs2, rs1, v0 Vector-scalar", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions", + "line_range": [ + 2564, + 2565 + ] + }, + { + "text": "vd.mask[i] = carryout(vs2[i] + imm + v0.mask[i]) vmadc.vim vd, vs2, imm, v0 Vector-immediate", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions", + "line_range": [ + 2567, + 2568 + ] + }, + { + "text": "vd.mask[i] = carryout(vs2[i] + vs1[i]) vmadc.vv vd, vs2, vs1 Vector-vector, no carry-in", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions", + "line_range": [ + 2570, + 2571 + ] + }, + { + "text": "vd.mask[i] = carryout(vs2[i] + x[rs1]) vmadc.vx vd, vs2, rs1 Vector-scalar, no carry-in", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions", + "line_range": [ + 2573, + 2574 + ] + }, + { + "text": "vd.mask[i] = carryout(vs2[i] + imm) vmadc.vi vd, vs2, imm Vector-immediate, no carry-in ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions", + "line_range": [ + 2576, + 2578 + ] + }, + { + "text": "Because implementing a carry propagation requires executing two instructions with unchanged inputs, destructive accumulations will require an additional move to obtain correct results.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions", + "line_range": [ + 2580, + 2582 + ] + }, + { + "text": "---- Example multi-word arithmetic sequence, accumulating into v4 vmadc.vvm v1, v4, v8, v0 Get carry into temp register v1 vadc.vvm v4, v4, v8, v0 Calc new sum vmmv.m v0, v1 Move temp carry into v0 for next word ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions", + "line_range": [ + 2584, + 2589 + ] + }, + { + "text": "The subtract with borrow instruction `vsbc` performs the equivalent function to support long word arithmetic for subtraction.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions", + "line_range": [ + 2591, + 2593 + ] + }, + { + "text": "There are no subtract with immediate instructions.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions", + "line_range": [ + 2591, + 2593 + ] + }, + { + "text": "---- Produce difference with borrow.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions", + "line_range": [ + 2595, + 2596 + ] + }, + { + "text": "vd[i] = vs2[i] - vs1[i] - v0.mask[i] vsbc.vvm vd, vs2, vs1, v0 Vector-vector", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions", + "line_range": [ + 2598, + 2599 + ] + }, + { + "text": "vd[i] = vs2[i] - x[rs1] - v0.mask[i] vsbc.vxm vd, vs2, rs1, v0 Vector-scalar", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions", + "line_range": [ + 2601, + 2602 + ] + }, + { + "text": "Produce borrow out in mask register format", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions", + "line_range": [ + 2604, + 2604 + ] + }, + { + "text": "vd.mask[i] = borrowout(vs2[i] - vs1[i] - v0.mask[i]) vmsbc.vvm vd, vs2, vs1, v0 Vector-vector", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions", + "line_range": [ + 2606, + 2607 + ] + }, + { + "text": "vd.mask[i] = borrowout(vs2[i] - x[rs1] - v0.mask[i]) vmsbc.vxm vd, vs2, rs1, v0 Vector-scalar", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions", + "line_range": [ + 2609, + 2610 + ] + }, + { + "text": "vd.mask[i] = borrowout(vs2[i] - vs1[i]) vmsbc.vv vd, vs2, vs1 Vector-vector, no borrow-in", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions", + "line_range": [ + 2612, + 2613 + ] + }, + { + "text": "vd.mask[i] = borrowout(vs2[i] - x[rs1]) vmsbc.vx vd, vs2, rs1 Vector-scalar, no borrow-in ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions", + "line_range": [ + 2615, + 2617 + ] + }, + { + "text": "For `vmsbc`, the borrow is defined to be 1 iff the difference, prior to truncation, is negative.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions", + "line_range": [ + 2619, + 2620 + ] + }, + { + "text": "For `vadc` and `vsbc`, the instruction encoding is reserved if the destination vector register is `v0`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions", + "line_range": [ + 2622, + 2623 + ] + }, + { + "text": "NOTE: This constraint corresponds to the constraint on masked vector operations that overwrite the mask register.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions", + "line_range": [ + 2625, + 2626 + ] + }, + { + "text": "---- Bitwise logical operations. vand.vv vd, vs2, vs1, vm Vector-vector vand.vx vd, vs2, rs1, vm vector-scalar vand.vi vd, vs2, imm, vm vector-immediate", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Bitwise Logical Instructions", + "line_range": [ + 2630, + 2635 + ] + }, + { + "text": "vor.vv vd, vs2, vs1, vm Vector-vector vor.vx vd, vs2, rs1, vm vector-scalar vor.vi vd, vs2, imm, vm vector-immediate", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Bitwise Logical Instructions", + "line_range": [ + 2637, + 2639 + ] + }, + { + "text": "vxor.vv vd, vs2, vs1, vm Vector-vector vxor.vx vd, vs2, rs1, vm vector-scalar vxor.vi vd, vs2, imm, vm vector-immediate ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Bitwise Logical Instructions", + "line_range": [ + 2641, + 2644 + ] + }, + { + "text": "NOTE: With an immediate of -1, scalar-immediate forms of the `vxor` instruction provide a bitwise NOT operation.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Bitwise Logical Instructions", + "line_range": [ + 2646, + 2648 + ] + }, + { + "text": "This is provided as an assembler pseudoinstruction `vnot.v vd,vs,vm` = `vxor.vi vd,vs,-1,vm`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Bitwise Logical Instructions", + "line_range": [ + 2646, + 2648 + ] + }, + { + "text": "A full set of vector shift instructions are provided, including logical shift left (`sll`), and logical (zero-extending `srl`) and arithmetic (sign-extending `sra`) shift right.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Single-Width Shift Instructions", + "line_range": [ + 2652, + 2659 + ] + }, + { + "text": "The data to be shifted is in the vector register group specified by `vs2` and the shift amount value can come from a vector register group `vs1`, a scalar integer register `rs1`, or a zero-extended 5-bit immediate.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Single-Width Shift Instructions", + "line_range": [ + 2652, + 2659 + ] + }, + { + "text": "Only the low lg2(SEW) bits of the shift-amount value are used to control the shift amount.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Single-Width Shift Instructions", + "line_range": [ + 2652, + 2659 + ] + }, + { + "text": "---- Bit shift operations vsll.vv vd, vs2, vs1, vm Vector-vector vsll.vx vd, vs2, rs1, vm vector-scalar vsll.vi vd, vs2, uimm, vm vector-immediate", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Single-Width Shift Instructions", + "line_range": [ + 2661, + 2665 + ] + }, + { + "text": "vsrl.vv vd, vs2, vs1, vm Vector-vector vsrl.vx vd, vs2, rs1, vm vector-scalar vsrl.vi vd, vs2, uimm, vm vector-immediate", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Single-Width Shift Instructions", + "line_range": [ + 2667, + 2669 + ] + }, + { + "text": "vsra.vv vd, vs2, vs1, vm Vector-vector vsra.vx vd, vs2, rs1, vm vector-scalar vsra.vi vd, vs2, uimm, vm vector-immediate ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Single-Width Shift Instructions", + "line_range": [ + 2671, + 2674 + ] + }, + { + "text": "The narrowing right shifts extract a smaller field from a wider operand and have both zero-extending (`srl`) and sign-extending (`sra`) forms.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Narrowing Integer Right Shift Instructions", + "line_range": [ + 2678, + 2684 + ] + }, + { + "text": "The shift amount can come from a vector register group, or a scalar `x` register, or a zero-extended 5-bit immediate.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Narrowing Integer Right Shift Instructions", + "line_range": [ + 2678, + 2684 + ] + }, + { + "text": "The low lg2(2*SEW) bits of the shift-amount value are used (e.g., the low 6 bits for a SEW=64-bit to SEW=32-bit narrowing operation).", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Narrowing Integer Right Shift Instructions", + "line_range": [ + 2678, + 2684 + ] + }, + { + "text": "---- Narrowing shift right logical, SEW = (2*SEW) >> SEW vnsrl.wv vd, vs2, vs1, vm vector-vector vnsrl.wx vd, vs2, rs1, vm vector-scalar vnsrl.wi vd, vs2, uimm, vm vector-immediate", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Narrowing Integer Right Shift Instructions", + "line_range": [ + 2686, + 2690 + ] + }, + { + "text": "Narrowing shift right arithmetic, SEW = (2*SEW) >> SEW vnsra.wv vd, vs2, vs1, vm vector-vector vnsra.wx vd, vs2, rs1, vm vector-scalar vnsra.wi vd, vs2, uimm, vm vector-immediate ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Narrowing Integer Right Shift Instructions", + "line_range": [ + 2692, + 2696 + ] + }, + { + "text": "NOTE: Future extensions might add support for versions that narrow to a destination that is 1/4 the width of the source.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Narrowing Integer Right Shift Instructions", + "line_range": [ + 2698, + 2699 + ] + }, + { + "text": "NOTE: An integer value can be halved in width using the narrowing integer shift instructions with a scalar operand of `x0`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Narrowing Integer Right Shift Instructions", + "line_range": [ + 2701, + 2703 + ] + }, + { + "text": "An assembly pseudoinstruction is provided `vncvt.x.x.w vd,vs,vm` = `vnsrl.wx vd,vs,x0,vm`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Narrowing Integer Right Shift Instructions", + "line_range": [ + 2701, + 2703 + ] + }, + { + "text": "The following integer compare instructions write 1 to the destination mask register element if the comparison evaluates to true, and 0 otherwise.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Compare Instructions", + "line_range": [ + 2707, + 2712 + ] + }, + { + "text": "The destination mask vector is always held in a single vector register, with a layout of elements as described in .", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Compare Instructions", + "line_range": [ + 2707, + 2712 + ] + }, + { + "text": "The destination mask vector register may be the same as the source vector mask register (`v0`).", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Compare Instructions", + "line_range": [ + 2707, + 2712 + ] + }, + { + "text": "---- Set if equal vmseq.vv vd, vs2, vs1, vm Vector-vector vmseq.vx vd, vs2, rs1, vm vector-scalar vmseq.vi vd, vs2, imm, vm vector-immediate", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Compare Instructions", + "line_range": [ + 2714, + 2718 + ] + }, + { + "text": "Set if not equal vmsne.vv vd, vs2, vs1, vm Vector-vector vmsne.vx vd, vs2, rs1, vm vector-scalar vmsne.vi vd, vs2, imm, vm vector-immediate", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Compare Instructions", + "line_range": [ + 2720, + 2723 + ] + }, + { + "text": "Set if less than, unsigned vmsltu.vv vd, vs2, vs1, vm Vector-vector vmsltu.vx vd, vs2, rs1, vm Vector-scalar", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Compare Instructions", + "line_range": [ + 2725, + 2727 + ] + }, + { + "text": "Set if less than, signed vmslt.vv vd, vs2, vs1, vm Vector-vector vmslt.vx vd, vs2, rs1, vm vector-scalar", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Compare Instructions", + "line_range": [ + 2729, + 2731 + ] + }, + { + "text": "Set if less than or equal, unsigned vmsleu.vv vd, vs2, vs1, vm Vector-vector vmsleu.vx vd, vs2, rs1, vm vector-scalar vmsleu.vi vd, vs2, imm, vm Vector-immediate", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Compare Instructions", + "line_range": [ + 2733, + 2736 + ] + }, + { + "text": "Set if less than or equal, signed vmsle.vv vd, vs2, vs1, vm Vector-vector vmsle.vx vd, vs2, rs1, vm vector-scalar vmsle.vi vd, vs2, imm, vm vector-immediate", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Compare Instructions", + "line_range": [ + 2738, + 2741 + ] + }, + { + "text": "Set if greater than, unsigned vmsgtu.vx vd, vs2, rs1, vm Vector-scalar vmsgtu.vi vd, vs2, imm, vm Vector-immediate", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Compare Instructions", + "line_range": [ + 2743, + 2745 + ] + }, + { + "text": "Set if greater than, signed vmsgt.vx vd, vs2, rs1, vm Vector-scalar vmsgt.vi vd, vs2, imm, vm Vector-immediate", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Compare Instructions", + "line_range": [ + 2747, + 2749 + ] + }, + { + "text": "Following two instructions are not provided directly Set if greater than or equal, unsigned vmsgeu.vx vd, vs2, rs1, vm Vector-scalar Set if greater than or equal, signed vmsge.vx vd, vs2, rs1, vm Vector-scalar ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Compare Instructions", + "line_range": [ + 2751, + 2756 + ] + }, + { + "text": "The following table indicates how all comparisons are implemented in native machine code.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Compare Instructions", + "line_range": [ + 2758, + 2759 + ] + }, + { + "text": "---- Comparison Assembler Mapping Assembler Pseudoinstruction", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Compare Instructions", + "line_range": [ + 2761, + 2762 + ] + }, + { + "text": "va < vb vmslt{u}.vv vd, va, vb, vm va <= vb vmsle{u}.vv vd, va, vb, vm va > vb vmslt{u}.vv vd, vb, va, vm vmsgt{u}.vv vd, va, vb, vm va >= vb vmsle{u}.vv vd, vb, va, vm vmsge{u}.vv vd, va, vb, vm", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Compare Instructions", + "line_range": [ + 2764, + 2767 + ] + }, + { + "text": "va < x vmslt{u}.vx vd, va, x, vm va <= x vmsle{u}.vx vd, va, x, vm va > x vmsgt{u}.vx vd, va, x, vm va >= x see below", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Compare Instructions", + "line_range": [ + 2769, + 2772 + ] + }, + { + "text": "va < i vmsle{u}.vi vd, va, i-1, vm vmslt{u}.vi vd, va, i, vm va <= i vmsle{u}.vi vd, va, i, vm va > i vmsgt{u}.vi vd, va, i, vm va >= i vmsgt{u}.vi vd, va, i-1, vm vmsge{u}.vi vd, va, i, vm", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Compare Instructions", + "line_range": [ + 2774, + 2777 + ] + }, + { + "text": "va, vb vector register groups x scalar integer register i immediate ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Compare Instructions", + "line_range": [ + 2779, + 2782 + ] + }, + { + "text": "NOTE: The immediate forms of `vmslt{u}.vi` are not provided as the immediate value can be decreased by 1 and the `vmsle{u}.vi` variants used instead.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Compare Instructions", + "line_range": [ + 2784, + 2790 + ] + }, + { + "text": "The `vmsle.vi` range is -16 to 15, resulting in an effective `vmslt.vi` range of -15 to 16.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Compare Instructions", + "line_range": [ + 2784, + 2790 + ] + }, + { + "text": "The `vmsleu.vi` range is 0 to 15 giving an effective `vmsltu.vi` range of 1 to 16 (Note, `vmsltu.vi` with immediate 0 is not useful as it is always false).", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Compare Instructions", + "line_range": [ + 2784, + 2790 + ] + }, + { + "text": "NOTE: Similarly, `vmsge{u}.vi` is not provided and the compare is implemented using `vmsgt{u}.vi` with the immediate decremented by one.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Compare Instructions", + "line_range": [ + 2792, + 2796 + ] + }, + { + "text": "The resulting effective `vmsge.vi` range is -15 to 16, and the resulting effective `vmsgeu.vi` range is 1 to 16 (Note, `vmsgeu.vi` with immediate 0 is not useful as it is always true).", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Compare Instructions", + "line_range": [ + 2792, + 2796 + ] + }, + { + "text": "NOTE: Because the 5-bit vector immediates are always sign-extended, when the high bit of the `simm5` immediate is set, `vmsleu.vi` and `vmsgtu.vi` also support unsigned immediate values in the range `2^SEW^-16` to `2^SEW^-1`, allowing corresponding `vmsltu.vi` and `vmsgeu.vi` compares against unsigned immediates in the range `2^SEW^-15` to `2^SEW^`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Compare Instructions", + "line_range": [ + 2798, + 2804 + ] + }, + { + "text": "Note that `vmsltu.vi` and `vmsgeu.vi` with immediate `2^SEW^` is not useful as it is always true or false, respectively.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Compare Instructions", + "line_range": [ + 2798, + 2804 + ] + }, + { + "text": "NOTE: The `vmsgt` forms for register scalar and immediates are provided to allow a single compare instruction to provide the correct polarity of mask value without using additional mask logical instructions.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Compare Instructions", + "line_range": [ + 2806, + 2809 + ] + }, + { + "text": "To reduce encoding space, the `vmsge{u}.vx` form is not directly provided, and so the `va {ge} x` case requires special treatment.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Compare Instructions", + "line_range": [ + 2811, + 2812 + ] + }, + { + "text": "NOTE: The `vmsge{u}.vx` could potentially be encoded in a non-orthogonal way under the unused OPIVI variant of `vmslt{u}`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Compare Instructions", + "line_range": [ + 2814, + 2821 + ] + }, + { + "text": "These would be the only instructions in OPIVI that use a scalar `x` register however.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Compare Instructions", + "line_range": [ + 2814, + 2821 + ] + }, + { + "text": "Alternatively, a further two funct6 encodings could be used, but these would have a different operand format (writes to mask register) than others in the same group of 8 funct6 encodings.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Compare Instructions", + "line_range": [ + 2814, + 2821 + ] + }, + { + "text": "The current PoR is to omit these instructions and to synthesize where needed as described below.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Compare Instructions", + "line_range": [ + 2814, + 2821 + ] + }, + { + "text": "The `vmsge{u}.vx` operation can be synthesized by reducing the value of `x` by 1 and using the `vmsgt{u}.vx` instruction, when it is known that this will not underflow the representation in `x`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Compare Instructions", + "line_range": [ + 2823, + 2825 + ] + }, + { + "text": "---- Sequences to synthesize vmsge{u}.vx instruction", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Compare Instructions", + "line_range": [ + 2827, + 2828 + ] + }, + { + "text": "addi t0, x, -1; vmsgt{u}.vx vd, va, t0, vm ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Compare Instructions", + "line_range": [ + 2832, + 2833 + ] + }, + { + "text": "The above sequence will usually be the most efficient implementation, but assembler pseudoinstructions can be provided for cases where the range of `x` is unknown.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Compare Instructions", + "line_range": [ + 2835, + 2837 + ] + }, + { + "text": "pseudoinstruction: vmsge{u}.vx vd, va, x expansion: vmslt{u}.vx vd, va, x; vmnand.mm vd, vd, vd", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Compare Instructions", + "line_range": [ + 2842, + 2843 + ] + }, + { + "text": "pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t expansion: vmslt{u}.vx vd, va, x, v0.t; vmxor.mm vd, vd, v0", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Compare Instructions", + "line_range": [ + 2847, + 2848 + ] + }, + { + "text": "pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt expansion: vmslt{u}.vx vt, va, x; vmandn.mm vd, vd, vt", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Compare Instructions", + "line_range": [ + 2852, + 2853 + ] + }, + { + "text": "pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt expansion: vmslt{u}.vx vt, va, x; vmandn.mm vt, v0, vt; vmandn.mm vd, vd, v0; vmor.mm vd, vt, vd", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Compare Instructions", + "line_range": [ + 2857, + 2858 + ] + }, + { + "text": "The vt argument to the pseudoinstruction must name a temporary vector register that is not same as vd and which will be clobbered by the pseudoinstruction ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Compare Instructions", + "line_range": [ + 2860, + 2862 + ] + }, + { + "text": "Compares effectively AND in the mask under a mask-undisturbed policy if the destination register is `v0`, e.g.,", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Compare Instructions", + "line_range": [ + 2864, + 2864 + ] + }, + { + "text": "---- (a < b) && (b < c) in two instructions when mask-undisturbed vmslt.vv v0, va, vb All body elements written vmslt.vv v0, vb, vc, v0.t Only update at set mask ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Compare Instructions", + "line_range": [ + 2866, + 2870 + ] + }, + { + "text": "Compares write mask registers, and so always operate under a tail-agnostic policy.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Compare Instructions", + "line_range": [ + 2872, + 2873 + ] + }, + { + "text": "Signed and unsigned integer minimum and maximum instructions are supported.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Min/Max Instructions", + "line_range": [ + 2877, + 2878 + ] + }, + { + "text": "---- Unsigned minimum vminu.vv vd, vs2, vs1, vm Vector-vector vminu.vx vd, vs2, rs1, vm vector-scalar", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Min/Max Instructions", + "line_range": [ + 2880, + 2883 + ] + }, + { + "text": "Signed minimum vmin.vv vd, vs2, vs1, vm Vector-vector vmin.vx vd, vs2, rs1, vm vector-scalar", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Min/Max Instructions", + "line_range": [ + 2885, + 2887 + ] + }, + { + "text": "Unsigned maximum vmaxu.vv vd, vs2, vs1, vm Vector-vector vmaxu.vx vd, vs2, rs1, vm vector-scalar", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Min/Max Instructions", + "line_range": [ + 2889, + 2891 + ] + }, + { + "text": "Signed maximum vmax.vv vd, vs2, vs1, vm Vector-vector vmax.vx vd, vs2, rs1, vm vector-scalar ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Min/Max Instructions", + "line_range": [ + 2893, + 2896 + ] + }, + { + "text": "The single-width multiply instructions perform a SEW-bit*SEW-bit multiply to generate a 2*SEW-bit product, then return one half of the product in the SEW-bit-wide destination.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Single-Width Integer Multiply Instructions", + "line_range": [ + 2900, + 2905 + ] + }, + { + "text": "The `*mul*` versions write the low half of the product to the destination register, while the `*mulh*` versions write the high half of the product to the destination register.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Single-Width Integer Multiply Instructions", + "line_range": [ + 2900, + 2905 + ] + }, + { + "text": "---- Signed multiply, returning low bits of product vmul.vv vd, vs2, vs1, vm Vector-vector vmul.vx vd, vs2, rs1, vm vector-scalar", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Single-Width Integer Multiply Instructions", + "line_range": [ + 2907, + 2910 + ] + }, + { + "text": "Signed multiply, returning high bits of product vmulh.vv vd, vs2, vs1, vm Vector-vector vmulh.vx vd, vs2, rs1, vm vector-scalar", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Single-Width Integer Multiply Instructions", + "line_range": [ + 2912, + 2914 + ] + }, + { + "text": "Unsigned multiply, returning high bits of product vmulhu.vv vd, vs2, vs1, vm Vector-vector vmulhu.vx vd, vs2, rs1, vm vector-scalar", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Single-Width Integer Multiply Instructions", + "line_range": [ + 2916, + 2918 + ] + }, + { + "text": "Signed(vs2)-Unsigned multiply, returning high bits of product vmulhsu.vv vd, vs2, vs1, vm Vector-vector vmulhsu.vx vd, vs2, rs1, vm vector-scalar ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Single-Width Integer Multiply Instructions", + "line_range": [ + 2920, + 2923 + ] + }, + { + "text": "NOTE: There is no `vmulhus.vx` opcode to return high half of unsigned-vector * signed-scalar product.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Single-Width Integer Multiply Instructions", + "line_range": [ + 2925, + 2927 + ] + }, + { + "text": "The scalar can be splatted to a vector, then a `vmulhsu.vv` used.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Single-Width Integer Multiply Instructions", + "line_range": [ + 2925, + 2927 + ] + }, + { + "text": "NOTE: The current `vmulh*` opcodes perform simple fractional multiplies, but with no option to scale, round, and/or saturate the result. A possible future extension can consider variants of `vmulh`, `vmulhu`, `vmulhsu` that use the `vxrm` rounding mode when discarding low half of product.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Single-Width Integer Multiply Instructions", + "line_range": [ + 2929, + 2934 + ] + }, + { + "text": "There is no possibility of overflow in these cases.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Single-Width Integer Multiply Instructions", + "line_range": [ + 2929, + 2934 + ] + }, + { + "text": "The divide and remainder instructions are equivalent to the RISC-V standard scalar integer multiply/divides, with the same results for extreme inputs.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Divide Instructions", + "line_range": [ + 2938, + 2940 + ] + }, + { + "text": "---- Unsigned divide. vdivu.vv vd, vs2, vs1, vm Vector-vector vdivu.vx vd, vs2, rs1, vm vector-scalar", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Divide Instructions", + "line_range": [ + 2942, + 2945 + ] + }, + { + "text": "Signed divide vdiv.vv vd, vs2, vs1, vm Vector-vector vdiv.vx vd, vs2, rs1, vm vector-scalar", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Divide Instructions", + "line_range": [ + 2947, + 2949 + ] + }, + { + "text": "Unsigned remainder vremu.vv vd, vs2, vs1, vm Vector-vector vremu.vx vd, vs2, rs1, vm vector-scalar", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Divide Instructions", + "line_range": [ + 2951, + 2953 + ] + }, + { + "text": "Signed remainder vrem.vv vd, vs2, vs1, vm Vector-vector vrem.vx vd, vs2, rs1, vm vector-scalar ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Divide Instructions", + "line_range": [ + 2955, + 2958 + ] + }, + { + "text": "NOTE: The decision to include integer divide and remainder was contentious.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Divide Instructions", + "line_range": [ + 2960, + 2964 + ] + }, + { + "text": "The argument in favor is that without a standard instruction, software would have to pick some algorithm to perform the operation, which would likely perform poorly on some microarchitectures versus others.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Divide Instructions", + "line_range": [ + 2960, + 2964 + ] + }, + { + "text": "NOTE: There is no instruction to perform a \"scalar divide by vector\" operation.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Divide Instructions", + "line_range": [ + 2966, + 2967 + ] + }, + { + "text": "The widening integer multiply instructions return the full 2*SEW-bit product from an SEW-bit*SEW-bit multiply.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Widening Integer Multiply Instructions", + "line_range": [ + 2971, + 2972 + ] + }, + { + "text": "---- Widening signed-integer multiply vwmul.vv vd, vs2, vs1, vm vector-vector vwmul.vx vd, vs2, rs1, vm vector-scalar", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Widening Integer Multiply Instructions", + "line_range": [ + 2974, + 2977 + ] + }, + { + "text": "Widening unsigned-integer multiply vwmulu.vv vd, vs2, vs1, vm vector-vector vwmulu.vx vd, vs2, rs1, vm vector-scalar", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Widening Integer Multiply Instructions", + "line_range": [ + 2979, + 2981 + ] + }, + { + "text": "Widening signed(vs2)-unsigned integer multiply vwmulsu.vv vd, vs2, vs1, vm vector-vector vwmulsu.vx vd, vs2, rs1, vm vector-scalar ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Widening Integer Multiply Instructions", + "line_range": [ + 2983, + 2986 + ] + }, + { + "text": "The integer multiply-add instructions are destructive and are provided in two forms, one that overwrites the addend or minuend (`vmacc`, `vnmsac`) and one that overwrites the first multiplicand (`vmadd`, `vnmsub`).", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Single-Width Integer Multiply-Add Instructions", + "line_range": [ + 2990, + 2993 + ] + }, + { + "text": "The low half of the product is added or subtracted from the third operand.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Single-Width Integer Multiply-Add Instructions", + "line_range": [ + 2995, + 2995 + ] + }, + { + "text": "NOTE: `sac` is intended to be read as \"subtract from accumulator\".", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Single-Width Integer Multiply-Add Instructions", + "line_range": [ + 2997, + 3000 + ] + }, + { + "text": "The opcode is `vnmsac` to match the (unfortunately counterintuitive) floating-point `fnmsub` instruction definition.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Single-Width Integer Multiply-Add Instructions", + "line_range": [ + 2997, + 3000 + ] + }, + { + "text": "Similarly for the `vnmsub` opcode.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Single-Width Integer Multiply-Add Instructions", + "line_range": [ + 2997, + 3000 + ] + }, + { + "text": "---- Integer multiply-add, overwrite addend vmacc.vv vd, vs1, vs2, vm vd[i] = (vs1[i] * vs2[i]) + vd[i] vmacc.vx vd, rs1, vs2, vm vd[i] = (x[rs1] * vs2[i]) + vd[i]", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Single-Width Integer Multiply-Add Instructions", + "line_range": [ + 3002, + 3005 + ] + }, + { + "text": "Integer multiply-sub, overwrite minuend vnmsac.vv vd, vs1, vs2, vm vd[i] = -(vs1[i] * vs2[i]) + vd[i] vnmsac.vx vd, rs1, vs2, vm vd[i] = -(x[rs1] * vs2[i]) + vd[i]", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Single-Width Integer Multiply-Add Instructions", + "line_range": [ + 3007, + 3009 + ] + }, + { + "text": "Integer multiply-add, overwrite multiplicand vmadd.vv vd, vs1, vs2, vm vd[i] = (vs1[i] * vd[i]) + vs2[i] vmadd.vx vd, rs1, vs2, vm vd[i] = (x[rs1] * vd[i]) + vs2[i]", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Single-Width Integer Multiply-Add Instructions", + "line_range": [ + 3011, + 3013 + ] + }, + { + "text": "Integer multiply-sub, overwrite multiplicand vnmsub.vv vd, vs1, vs2, vm vd[i] = -(vs1[i] * vd[i]) + vs2[i] vnmsub.vx vd, rs1, vs2, vm vd[i] = -(x[rs1] * vd[i]) + vs2[i] ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Single-Width Integer Multiply-Add Instructions", + "line_range": [ + 3015, + 3018 + ] + }, + { + "text": "The widening integer multiply-add instructions add the full 2*SEW-bit product from a SEW-bit*SEW-bit multiply to a 2*SEW-bit value and produce a 2*SEW-bit result.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Widening Integer Multiply-Add Instructions", + "line_range": [ + 3022, + 3025 + ] + }, + { + "text": "All combinations of signed and unsigned multiply operands are supported.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Widening Integer Multiply-Add Instructions", + "line_range": [ + 3022, + 3025 + ] + }, + { + "text": "---- Widening unsigned-integer multiply-add, overwrite addend vwmaccu.vv vd, vs1, vs2, vm vd[i] = (vs1[i] * vs2[i]) + vd[i] vwmaccu.vx vd, rs1, vs2, vm vd[i] = (x[rs1] * vs2[i]) + vd[i]", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Widening Integer Multiply-Add Instructions", + "line_range": [ + 3027, + 3030 + ] + }, + { + "text": "Widening signed-integer multiply-add, overwrite addend vwmacc.vv vd, vs1, vs2, vm vd[i] = (vs1[i] * vs2[i]) + vd[i] vwmacc.vx vd, rs1, vs2, vm vd[i] = (x[rs1] * vs2[i]) + vd[i]", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Widening Integer Multiply-Add Instructions", + "line_range": [ + 3032, + 3034 + ] + }, + { + "text": "Widening signed-unsigned-integer multiply-add, overwrite addend vwmaccsu.vv vd, vs1, vs2, vm vd[i] = (signed(vs1[i]) * unsigned(vs2[i])) + vd[i] vwmaccsu.vx vd, rs1, vs2, vm vd[i] = (signed(x[rs1]) * unsigned(vs2[i])) + vd[i]", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Widening Integer Multiply-Add Instructions", + "line_range": [ + 3036, + 3038 + ] + }, + { + "text": "Widening unsigned-signed-integer multiply-add, overwrite addend vwmaccus.vx vd, rs1, vs2, vm vd[i] = (unsigned(x[rs1]) * signed(vs2[i])) + vd[i] ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Widening Integer Multiply-Add Instructions", + "line_range": [ + 3040, + 3042 + ] + }, + { + "text": "The vector integer merge instructions combine two source operands based on a mask.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Merge Instructions", + "line_range": [ + 3046, + 3049 + ] + }, + { + "text": "Unlike regular arithmetic instructions, the merge operates on all body elements (i.e., the set of elements from `vstart` up to the current vector length in `vl`).", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Merge Instructions", + "line_range": [ + 3046, + 3049 + ] + }, + { + "text": "The `vmerge` instructions are encoded as masked instructions (`vm=0`).", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Merge Instructions", + "line_range": [ + 3051, + 3059 + ] + }, + { + "text": "The instructions combine two sources as follows.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Merge Instructions", + "line_range": [ + 3051, + 3059 + ] + }, + { + "text": "At elements where the mask value is zero, the first operand is copied to the destination element, otherwise the second operand is copied to the destination element.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Merge Instructions", + "line_range": [ + 3051, + 3059 + ] + }, + { + "text": "The first operand is always a vector register group specified by `vs2`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Merge Instructions", + "line_range": [ + 3051, + 3059 + ] + }, + { + "text": "The second operand is a vector register group specified by `vs1` or a scalar `x` register specified by `rs1` or a 5-bit sign-extended immediate.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Merge Instructions", + "line_range": [ + 3051, + 3059 + ] + }, + { + "text": "---- vmerge.vvm vd, vs2, vs1, v0 vd[i] = v0.mask[i] ? vs1[i] : vs2[i] vmerge.vxm vd, vs2, rs1, v0 vd[i] = v0.mask[i] ? x[rs1] : vs2[i] vmerge.vim vd, vs2, imm, v0 vd[i] = v0.mask[i] ? imm : vs2[i] ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Merge Instructions", + "line_range": [ + 3061, + 3065 + ] + }, + { + "text": "The vector integer move instructions copy a source operand to a vector register group.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Move Instructions", + "line_range": [ + 3069, + 3076 + ] + }, + { + "text": "The `vmv.v.v` variant copies a vector register group, whereas the `vmv.v.x` and `vmv.v.i` variants splat a scalar register or immediate to all active elements of the destination vector register group.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Move Instructions", + "line_range": [ + 3069, + 3076 + ] + }, + { + "text": "These instructions are encoded as unmasked instructions (`vm=1`).", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Move Instructions", + "line_range": [ + 3069, + 3076 + ] + }, + { + "text": "The first operand specifier (`vs2`) must contain `v0`, and any other vector register number in `vs2` is reserved.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Move Instructions", + "line_range": [ + 3069, + 3076 + ] + }, + { + "text": "---- vmv.v.v vd, vs1 vd[i] = vs1[i] vmv.v.x vd, rs1 vd[i] = x[rs1] vmv.v.i vd, imm vd[i] = imm ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Move Instructions", + "line_range": [ + 3078, + 3082 + ] + }, + { + "text": "NOTE: Mask values can be widened into SEW-width elements using a sequence `vmv.v.i vd, 0; vmerge.vim vd, vd, 1, v0`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Move Instructions", + "line_range": [ + 3084, + 3085 + ] + }, + { + "text": "NOTE: The vector integer move instructions share the encoding with the vector merge instructions, but with `vm=1` and `vs2=v0`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Move Instructions", + "line_range": [ + 3087, + 3088 + ] + }, + { + "text": "The form `vmv.v.v vd, vd`, which leaves body elements unchanged, can be used to indicate that the register will next be used with an EEW equal to SEW.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Move Instructions", + "line_range": [ + 3090, + 3092 + ] + }, + { + "text": "NOTE: Implementations that internally reorganize data according to EEW can shuffle the internal representation according to SEW.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Move Instructions", + "line_range": [ + 3094, + 3097 + ] + }, + { + "text": "Implementations that do not internally reorganize data can dynamically elide this instruction (aside from resetting `vstart` to 0).", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Move Instructions", + "line_range": [ + 3094, + 3097 + ] + }, + { + "text": "NOTE: The `vmv.v.v vd, vd` instruction is not a RISC-V HINT as a tail-agnostic setting may cause an architectural state change on some implementations.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Integer Arithmetic Instructions > Vector Integer Move Instructions", + "line_range": [ + 3099, + 3101 + ] + }, + { + "text": "The preceding set of integer arithmetic instructions is extended to support fixed-point arithmetic.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions", + "line_range": [ + 3106, + 3107 + ] + }, + { + "text": "A fixed-point number is a two's-complement signed or unsigned integer interpreted as the numerator in a fraction with an implicit denominator.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions", + "line_range": [ + 3109, + 3117 + ] + }, + { + "text": "The fixed-point instructions are intended to be applied to the numerators; it is the responsibility of software to manage the denominators.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions", + "line_range": [ + 3109, + 3117 + ] + }, + { + "text": "An N-bit element can hold two's-complement signed integers in the range -2^N-1^...+2^N-1^-1, and unsigned integers in the range 0 ... +2^N^-1.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions", + "line_range": [ + 3109, + 3117 + ] + }, + { + "text": "The fixed-point instructions help preserve precision in narrow operands by supporting scaling and rounding, and can handle overflow by saturating results into the destination format range.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions", + "line_range": [ + 3109, + 3117 + ] + }, + { + "text": "NOTE: The widening integer operations described above can also be used to avoid overflow.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions", + "line_range": [ + 3119, + 3120 + ] + }, + { + "text": "Saturating forms of integer add and subtract are provided, for both signed and unsigned integers.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions > Vector Single-Width Saturating Add and Subtract", + "line_range": [ + 3124, + 3127 + ] + }, + { + "text": "If the result would overflow the destination, the result is replaced with the closest representable value, and the `vxsat` bit is set.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions > Vector Single-Width Saturating Add and Subtract", + "line_range": [ + 3124, + 3127 + ] + }, + { + "text": "---- Saturating adds of unsigned integers. vsaddu.vv vd, vs2, vs1, vm Vector-vector vsaddu.vx vd, vs2, rs1, vm vector-scalar vsaddu.vi vd, vs2, imm, vm vector-immediate", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions > Vector Single-Width Saturating Add and Subtract", + "line_range": [ + 3129, + 3133 + ] + }, + { + "text": "Saturating adds of signed integers. vsadd.vv vd, vs2, vs1, vm Vector-vector vsadd.vx vd, vs2, rs1, vm vector-scalar vsadd.vi vd, vs2, imm, vm vector-immediate", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions > Vector Single-Width Saturating Add and Subtract", + "line_range": [ + 3135, + 3138 + ] + }, + { + "text": "Saturating subtract of unsigned integers. vssubu.vv vd, vs2, vs1, vm Vector-vector vssubu.vx vd, vs2, rs1, vm vector-scalar", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions > Vector Single-Width Saturating Add and Subtract", + "line_range": [ + 3140, + 3142 + ] + }, + { + "text": "Saturating subtract of signed integers. vssub.vv vd, vs2, vs1, vm Vector-vector vssub.vx vd, vs2, rs1, vm vector-scalar ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions > Vector Single-Width Saturating Add and Subtract", + "line_range": [ + 3144, + 3147 + ] + }, + { + "text": "The averaging add and subtract instructions right shift the result by one bit and round off the result according to the setting in `vxrm`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions > Vector Single-Width Averaging Add and Subtract", + "line_range": [ + 3151, + 3156 + ] + }, + { + "text": "Computation is performed in infinite precision before rounding and truncating.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions > Vector Single-Width Averaging Add and Subtract", + "line_range": [ + 3151, + 3156 + ] + }, + { + "text": "Both unsigned and signed versions are provided.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions > Vector Single-Width Averaging Add and Subtract", + "line_range": [ + 3151, + 3156 + ] + }, + { + "text": "For `vaaddu` and `vaadd` there can be no overflow in the result.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions > Vector Single-Width Averaging Add and Subtract", + "line_range": [ + 3151, + 3156 + ] + }, + { + "text": "For `vasub` and `vasubu`, overflow is ignored and the result wraps around.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions > Vector Single-Width Averaging Add and Subtract", + "line_range": [ + 3151, + 3156 + ] + }, + { + "text": "NOTE: For `vasub`, overflow occurs only when subtracting the smallest number from the largest number under `rnu` or `rne` rounding.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions > Vector Single-Width Averaging Add and Subtract", + "line_range": [ + 3158, + 3159 + ] + }, + { + "text": "Averaging adds of unsigned integers. vaaddu.vv vd, vs2, vs1, vm roundoffunsigned(vs2[i] + vs1[i], 1) vaaddu.vx vd, vs2, rs1, vm roundoffunsigned(vs2[i] + x[rs1], 1)", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions > Vector Single-Width Averaging Add and Subtract", + "line_range": [ + 3164, + 3166 + ] + }, + { + "text": "Averaging adds of signed integers. vaadd.vv vd, vs2, vs1, vm roundoffsigned(vs2[i] + vs1[i], 1) vaadd.vx vd, vs2, rs1, vm roundoffsigned(vs2[i] + x[rs1], 1)", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions > Vector Single-Width Averaging Add and Subtract", + "line_range": [ + 3168, + 3170 + ] + }, + { + "text": "Averaging subtract of unsigned integers. vasubu.vv vd, vs2, vs1, vm roundoffunsigned(vs2[i] - vs1[i], 1) vasubu.vx vd, vs2, rs1, vm roundoffunsigned(vs2[i] - x[rs1], 1)", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions > Vector Single-Width Averaging Add and Subtract", + "line_range": [ + 3174, + 3176 + ] + }, + { + "text": "Averaging subtract of signed integers. vasub.vv vd, vs2, vs1, vm roundoffsigned(vs2[i] - vs1[i], 1) vasub.vx vd, vs2, rs1, vm roundoffsigned(vs2[i] - x[rs1], 1) ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions > Vector Single-Width Averaging Add and Subtract", + "line_range": [ + 3178, + 3181 + ] + }, + { + "text": "The signed fractional multiply instruction produces a 2*SEW product of the two SEW inputs, then shifts the result right by SEW-1 bits, rounding these bits according to `vxrm`, then saturates the result to fit into SEW bits.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions > Vector Single-Width Fractional Multiply with Rounding and Saturation", + "line_range": [ + 3185, + 3189 + ] + }, + { + "text": "If the result causes saturation, the `vxsat` bit is set.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions > Vector Single-Width Fractional Multiply with Rounding and Saturation", + "line_range": [ + 3185, + 3189 + ] + }, + { + "text": "---- Signed saturating and rounding fractional multiply See vxrm description for rounding calculation vsmul.vv vd, vs2, vs1, vm vd[i] = clip(roundoffsigned(vs2[i]*vs1[i], SEW-1)) vsmul.vx vd, vs2, rs1, vm vd[i] = clip(roundoffsigned(vs2[i]*x[rs1], SEW-1)) ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions > Vector Single-Width Fractional Multiply with Rounding and Saturation", + "line_range": [ + 3191, + 3196 + ] + }, + { + "text": "When multiplying two N-bit signed numbers, the largest magnitude is obtained for -2^N-1^ * -2^N-1^ producing a result +2^2N-2^, which has a single (zero) sign bit when held in 2N bits.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions > Vector Single-Width Fractional Multiply with Rounding and Saturation", + "line_range": [ + 3198, + 3204 + ] + }, + { + "text": "All other products have two sign bits in 2N bits.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions > Vector Single-Width Fractional Multiply with Rounding and Saturation", + "line_range": [ + 3198, + 3204 + ] + }, + { + "text": "To retain greater precision in N result bits, the product is shifted right by one bit less than N, saturating the largest magnitude result but increasing result precision by one bit for all other products.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions > Vector Single-Width Fractional Multiply with Rounding and Saturation", + "line_range": [ + 3198, + 3204 + ] + }, + { + "text": "NOTE: We do not provide an equivalent fractional multiply where one input is unsigned, as these would retain all upper SEW bits and would not need to saturate.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions > Vector Single-Width Fractional Multiply with Rounding and Saturation", + "line_range": [ + 3206, + 3210 + ] + }, + { + "text": "This operation is partly covered by the `vmulhu` and `vmulhsu` instructions, for the case where rounding is simply truncation (`rdn`).", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions > Vector Single-Width Fractional Multiply with Rounding and Saturation", + "line_range": [ + 3206, + 3210 + ] + }, + { + "text": "These instructions shift the input value right, and round off the shifted out bits according to `vxrm`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions > Vector Single-Width Scaling Shift Instructions", + "line_range": [ + 3214, + 3220 + ] + }, + { + "text": "The scaling right shifts have both zero-extending (`vssrl`) and sign-extending (`vssra`) forms.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions > Vector Single-Width Scaling Shift Instructions", + "line_range": [ + 3214, + 3220 + ] + }, + { + "text": "The data to be shifted is in the vector register group specified by `vs2` and the shift amount value can come from a vector register group `vs1`, a scalar integer register `rs1`, or a zero-extended 5-bit immediate.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions > Vector Single-Width Scaling Shift Instructions", + "line_range": [ + 3214, + 3220 + ] + }, + { + "text": "Only the low lg2(SEW) bits of the shift-amount value are used to control the shift amount.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions > Vector Single-Width Scaling Shift Instructions", + "line_range": [ + 3214, + 3220 + ] + }, + { + "text": "---- Scaling shift right logical vssrl.vv vd, vs2, vs1, vm vd[i] = roundoffunsigned(vs2[i], vs1[i]) vssrl.vx vd, vs2, rs1, vm vd[i] = roundoffunsigned(vs2[i], x[rs1]) vssrl.vi vd, vs2, uimm, vm vd[i] = roundoffunsigned(vs2[i], uimm)", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions > Vector Single-Width Scaling Shift Instructions", + "line_range": [ + 3222, + 3226 + ] + }, + { + "text": "Scaling shift right arithmetic vssra.vv vd, vs2, vs1, vm vd[i] = roundoffsigned(vs2[i],vs1[i]) vssra.vx vd, vs2, rs1, vm vd[i] = roundoffsigned(vs2[i], x[rs1]) vssra.vi vd, vs2, uimm, vm vd[i] = roundoffsigned(vs2[i], uimm) ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions > Vector Single-Width Scaling Shift Instructions", + "line_range": [ + 3228, + 3232 + ] + }, + { + "text": "The `vnclip` instructions are used to pack a fixed-point value into a narrower destination.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions > Vector Narrowing Fixed-Point Clip Instructions", + "line_range": [ + 3236, + 3250 + ] + }, + { + "text": "The instructions support rounding, scaling, and saturation into the final destination format.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions > Vector Narrowing Fixed-Point Clip Instructions", + "line_range": [ + 3236, + 3250 + ] + }, + { + "text": "The source data is in the vector register group specified by `vs2`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions > Vector Narrowing Fixed-Point Clip Instructions", + "line_range": [ + 3236, + 3250 + ] + }, + { + "text": "The scaling shift amount value can come from a vector register group `vs1`, a scalar integer register `rs1`, or a zero-extended 5-bit immediate.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions > Vector Narrowing Fixed-Point Clip Instructions", + "line_range": [ + 3236, + 3250 + ] + }, + { + "text": "The low lg2(2*SEW) bits of the vector or scalar shift-amount value (e.g., the low 6 bits for a SEW=64-bit to SEW=32-bit narrowing operation) are used to control the right shift amount, which provides the scaling. ---- Narrowing unsigned clip SEW 2*SEW SEW vnclipu.wv vd, vs2, vs1, vm vd[i] = clip(roundoffunsigned(vs2[i], vs1[i])) vnclipu.wx vd, vs2, rs1, vm vd[i] = clip(roundoffunsigned(vs2[i], x[rs1])) vnclipu.wi vd, vs2, uimm, vm vd[i] = clip(roundoffunsigned(vs2[i], uimm))", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions > Vector Narrowing Fixed-Point Clip Instructions", + "line_range": [ + 3236, + 3250 + ] + }, + { + "text": "Narrowing signed clip vnclip.wv vd, vs2, vs1, vm vd[i] = clip(roundoffsigned(vs2[i], vs1[i])) vnclip.wx vd, vs2, rs1, vm vd[i] = clip(roundoffsigned(vs2[i], x[rs1])) vnclip.wi vd, vs2, uimm, vm vd[i] = clip(roundoffsigned(vs2[i], uimm)) ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions > Vector Narrowing Fixed-Point Clip Instructions", + "line_range": [ + 3252, + 3256 + ] + }, + { + "text": "For `vnclipu`/`vnclip`, the rounding mode is specified in the `vxrm` CSR.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions > Vector Narrowing Fixed-Point Clip Instructions", + "line_range": [ + 3258, + 3260 + ] + }, + { + "text": "Rounding occurs around the least-significant bit of the destination and before saturation.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions > Vector Narrowing Fixed-Point Clip Instructions", + "line_range": [ + 3258, + 3260 + ] + }, + { + "text": "For `vnclipu`, the shifted rounded source value is treated as an unsigned integer and saturates if the result would overflow the destination viewed as an unsigned integer.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions > Vector Narrowing Fixed-Point Clip Instructions", + "line_range": [ + 3262, + 3264 + ] + }, + { + "text": "NOTE: There is no single instruction that can saturate a signed value into an unsigned destination. A sequence of two vector instructions that first removes negative numbers by performing a max against 0 using `vmax` then clips the resulting unsigned value into the destination using `vnclipu` can be used if setting `vxsat` value for negative numbers is not required. A `vsetvli` is required between these two instructions to change SEW.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions > Vector Narrowing Fixed-Point Clip Instructions", + "line_range": [ + 3266, + 3272 + ] + }, + { + "text": "For `vnclip`, the shifted rounded source value is treated as a signed integer and saturates if the result would overflow the destination viewed as a signed integer.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions > Vector Narrowing Fixed-Point Clip Instructions", + "line_range": [ + 3274, + 3276 + ] + }, + { + "text": "If any destination element is saturated, the `vxsat` bit is set in the `vxsat` register.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Fixed-Point Arithmetic Instructions > Vector Narrowing Fixed-Point Clip Instructions", + "line_range": [ + 3278, + 3279 + ] + }, + { + "text": "The standard vector floating-point instructions treat elements as IEEE 754-2008-compatible values.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions", + "line_range": [ + 3284, + 3287 + ] + }, + { + "text": "If the EEW of a vector floating-point operand does not correspond to a supported IEEE floating-point type, the instruction encoding is reserved.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions", + "line_range": [ + 3284, + 3287 + ] + }, + { + "text": "NOTE: Whether floating-point is supported, and for which element widths, is determined by the specific vector extension.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions", + "line_range": [ + 3289, + 3294 + ] + }, + { + "text": "The current set of extensions include support for 32-bit and 64-bit floating-point values.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions", + "line_range": [ + 3289, + 3294 + ] + }, + { + "text": "When 16-bit and 128-bit element widths are added, they will be also be treated as IEEE 754-2008-compatible values.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions", + "line_range": [ + 3289, + 3294 + ] + }, + { + "text": "Other floating-point formats may be supported in future extensions.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions", + "line_range": [ + 3289, + 3294 + ] + }, + { + "text": "Vector floating-point instructions require the presence of base scalar floating-point extensions corresponding to the supported vector floating-point element widths.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions", + "line_range": [ + 3296, + 3298 + ] + }, + { + "text": "NOTE: In particular, future vector extensions supporting 16-bit half-precision floating-point values will also require some scalar half-precision floating-point support.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions", + "line_range": [ + 3300, + 3302 + ] + }, + { + "text": "If the floating-point unit status field `mstatus.FS` is `Off` then any attempt to execute a vector floating-point instruction will raise an illegal-instruction exception.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions", + "line_range": [ + 3304, + 3308 + ] + }, + { + "text": "Any vector floating-point instruction that modifies any floating-point extension state (i.e., floating-point CSRs or `f` registers) must set `mstatus.FS` to `Dirty`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions", + "line_range": [ + 3304, + 3308 + ] + }, + { + "text": "If the hypervisor extension is implemented and V=1, the `vsstatus.FS` field is additionally in effect for vector floating-point instructions.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions", + "line_range": [ + 3310, + 3316 + ] + }, + { + "text": "If `vsstatus.FS` or `mstatus.FS` is `Off` then any attempt to execute a vector floating-point instruction will raise an illegal-instruction exception.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions", + "line_range": [ + 3310, + 3316 + ] + }, + { + "text": "Any vector floating-point instruction that modifies any floating-point extension state (i.e., floating-point CSRs or `f` registers) must set both `mstatus.FS` and `vsstatus.FS` to `Dirty`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions", + "line_range": [ + 3310, + 3316 + ] + }, + { + "text": "The vector floating-point instructions have the same behavior as the scalar floating-point instructions with regard to NaNs.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions", + "line_range": [ + 3318, + 3319 + ] + }, + { + "text": "Scalar values for floating-point vector-scalar operations are sourced as described in .", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions", + "line_range": [ + 3321, + 3322 + ] + }, + { + "text": "A vector floating-point exception at any active floating-point element sets the standard FP exception flags in the `fflags` register.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Exception Flags", + "line_range": [ + 3326, + 3328 + ] + }, + { + "text": "Inactive elements do not set FP exception flags.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Exception Flags", + "line_range": [ + 3326, + 3328 + ] + }, + { + "text": "---- Floating-point add vfadd.vv vd, vs2, vs1, vm Vector-vector vfadd.vf vd, vs2, rs1, vm vector-scalar", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Single-Width Floating-Point Add/Subtract Instructions", + "line_range": [ + 3332, + 3336 + ] + }, + { + "text": "Floating-point subtract vfsub.vv vd, vs2, vs1, vm Vector-vector vfsub.vf vd, vs2, rs1, vm Vector-scalar vd[i] = vs2[i] - f[rs1] vfrsub.vf vd, vs2, rs1, vm Scalar-vector vd[i] = f[rs1] - vs2[i] ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Single-Width Floating-Point Add/Subtract Instructions", + "line_range": [ + 3338, + 3342 + ] + }, + { + "text": "---- Widening FP add/subtract, 2*SEW = SEW +/- SEW vfwadd.vv vd, vs2, vs1, vm vector-vector vfwadd.vf vd, vs2, rs1, vm vector-scalar vfwsub.vv vd, vs2, vs1, vm vector-vector vfwsub.vf vd, vs2, rs1, vm vector-scalar", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Widening Floating-Point Add/Subtract Instructions", + "line_range": [ + 3346, + 3352 + ] + }, + { + "text": "Widening FP add/subtract, 2*SEW = 2*SEW +/- SEW vfwadd.wv vd, vs2, vs1, vm vector-vector vfwadd.wf vd, vs2, rs1, vm vector-scalar vfwsub.wv vd, vs2, vs1, vm vector-vector vfwsub.wf vd, vs2, rs1, vm vector-scalar ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Widening Floating-Point Add/Subtract Instructions", + "line_range": [ + 3354, + 3359 + ] + }, + { + "text": "---- Floating-point multiply vfmul.vv vd, vs2, vs1, vm Vector-vector vfmul.vf vd, vs2, rs1, vm vector-scalar", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Single-Width Floating-Point Multiply/Divide Instructions", + "line_range": [ + 3363, + 3367 + ] + }, + { + "text": "Floating-point divide vfdiv.vv vd, vs2, vs1, vm Vector-vector vfdiv.vf vd, vs2, rs1, vm vector-scalar", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Single-Width Floating-Point Multiply/Divide Instructions", + "line_range": [ + 3369, + 3371 + ] + }, + { + "text": "Reverse floating-point divide vector = scalar / vector vfrdiv.vf vd, vs2, rs1, vm scalar-vector, vd[i] = f[rs1]/vs2[i] ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Single-Width Floating-Point Multiply/Divide Instructions", + "line_range": [ + 3373, + 3375 + ] + }, + { + "text": "---- Widening floating-point multiply vfwmul.vv vd, vs2, vs1, vm vector-vector vfwmul.vf vd, vs2, rs1, vm vector-scalar ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Widening Floating-Point Multiply", + "line_range": [ + 3379, + 3384 + ] + }, + { + "text": "All four varieties of fused multiply-add are provided, and in two destructive forms that overwrite one of the operands, either the addend or the first multiplicand.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Single-Width Floating-Point Fused Multiply-Add Instructions", + "line_range": [ + 3387, + 3389 + ] + }, + { + "text": "---- FP multiply-accumulate, overwrites addend vfmacc.vv vd, vs1, vs2, vm vd[i] = (vs1[i] * vs2[i]) + vd[i] vfmacc.vf vd, rs1, vs2, vm vd[i] = (f[rs1] * vs2[i]) + vd[i]", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Single-Width Floating-Point Fused Multiply-Add Instructions", + "line_range": [ + 3391, + 3394 + ] + }, + { + "text": "FP negate-(multiply-accumulate), overwrites subtrahend vfnmacc.vv vd, vs1, vs2, vm vd[i] = -(vs1[i] * vs2[i]) - vd[i] vfnmacc.vf vd, rs1, vs2, vm vd[i] = -(f[rs1] * vs2[i]) - vd[i]", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Single-Width Floating-Point Fused Multiply-Add Instructions", + "line_range": [ + 3396, + 3398 + ] + }, + { + "text": "FP multiply-subtract-accumulator, overwrites subtrahend vfmsac.vv vd, vs1, vs2, vm vd[i] = (vs1[i] * vs2[i]) - vd[i] vfmsac.vf vd, rs1, vs2, vm vd[i] = (f[rs1] * vs2[i]) - vd[i]", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Single-Width Floating-Point Fused Multiply-Add Instructions", + "line_range": [ + 3400, + 3402 + ] + }, + { + "text": "FP negate-(multiply-subtract-accumulator), overwrites minuend vfnmsac.vv vd, vs1, vs2, vm vd[i] = -(vs1[i] * vs2[i]) + vd[i] vfnmsac.vf vd, rs1, vs2, vm vd[i] = -(f[rs1] * vs2[i]) + vd[i]", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Single-Width Floating-Point Fused Multiply-Add Instructions", + "line_range": [ + 3404, + 3406 + ] + }, + { + "text": "FP multiply-add, overwrites multiplicand vfmadd.vv vd, vs1, vs2, vm vd[i] = (vs1[i] * vd[i]) + vs2[i] vfmadd.vf vd, rs1, vs2, vm vd[i] = (f[rs1] * vd[i]) + vs2[i]", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Single-Width Floating-Point Fused Multiply-Add Instructions", + "line_range": [ + 3408, + 3410 + ] + }, + { + "text": "FP negate-(multiply-add), overwrites multiplicand vfnmadd.vv vd, vs1, vs2, vm vd[i] = -(vs1[i] * vd[i]) - vs2[i] vfnmadd.vf vd, rs1, vs2, vm vd[i] = -(f[rs1] * vd[i]) - vs2[i]", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Single-Width Floating-Point Fused Multiply-Add Instructions", + "line_range": [ + 3412, + 3414 + ] + }, + { + "text": "FP multiply-sub, overwrites multiplicand vfmsub.vv vd, vs1, vs2, vm vd[i] = (vs1[i] * vd[i]) - vs2[i] vfmsub.vf vd, rs1, vs2, vm vd[i] = (f[rs1] * vd[i]) - vs2[i]", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Single-Width Floating-Point Fused Multiply-Add Instructions", + "line_range": [ + 3416, + 3418 + ] + }, + { + "text": "FP negate-(multiply-sub), overwrites multiplicand vfnmsub.vv vd, vs1, vs2, vm vd[i] = -(vs1[i] * vd[i]) + vs2[i] vfnmsub.vf vd, rs1, vs2, vm vd[i] = -(f[rs1] * vd[i]) + vs2[i] ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Single-Width Floating-Point Fused Multiply-Add Instructions", + "line_range": [ + 3420, + 3423 + ] + }, + { + "text": "NOTE: While we considered using the two unused rounding modes in the scalar FP FMA encoding to provide a few non-destructive FMAs, these would complicate microarchitectures by being the only maskable operation with three inputs and separate output.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Single-Width Floating-Point Fused Multiply-Add Instructions", + "line_range": [ + 3425, + 3428 + ] + }, + { + "text": "The widening floating-point fused multiply-add instructions all overwrite the wide addend with the result.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Widening Floating-Point Fused Multiply-Add Instructions", + "line_range": [ + 3432, + 3434 + ] + }, + { + "text": "The multiplier inputs are all SEW wide, while the addend and destination is 2*SEW bits wide.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Widening Floating-Point Fused Multiply-Add Instructions", + "line_range": [ + 3432, + 3434 + ] + }, + { + "text": "---- FP widening multiply-accumulate, overwrites addend vfwmacc.vv vd, vs1, vs2, vm vd[i] = (vs1[i] * vs2[i]) + vd[i] vfwmacc.vf vd, rs1, vs2, vm vd[i] = (f[rs1] * vs2[i]) + vd[i]", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Widening Floating-Point Fused Multiply-Add Instructions", + "line_range": [ + 3436, + 3439 + ] + }, + { + "text": "FP widening negate-(multiply-accumulate), overwrites addend vfwnmacc.vv vd, vs1, vs2, vm vd[i] = -(vs1[i] * vs2[i]) - vd[i] vfwnmacc.vf vd, rs1, vs2, vm vd[i] = -(f[rs1] * vs2[i]) - vd[i]", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Widening Floating-Point Fused Multiply-Add Instructions", + "line_range": [ + 3441, + 3443 + ] + }, + { + "text": "FP widening multiply-subtract-accumulator, overwrites addend vfwmsac.vv vd, vs1, vs2, vm vd[i] = (vs1[i] * vs2[i]) - vd[i] vfwmsac.vf vd, rs1, vs2, vm vd[i] = (f[rs1] * vs2[i]) - vd[i]", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Widening Floating-Point Fused Multiply-Add Instructions", + "line_range": [ + 3445, + 3447 + ] + }, + { + "text": "FP widening negate-(multiply-subtract-accumulator), overwrites addend vfwnmsac.vv vd, vs1, vs2, vm vd[i] = -(vs1[i] * vs2[i]) + vd[i] vfwnmsac.vf vd, rs1, vs2, vm vd[i] = -(f[rs1] * vs2[i]) + vd[i] ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Widening Floating-Point Fused Multiply-Add Instructions", + "line_range": [ + 3449, + 3452 + ] + }, + { + "text": "This is a unary vector-vector instruction.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Square-Root Instruction", + "line_range": [ + 3456, + 3457 + ] + }, + { + "text": "---- Floating-point square root vfsqrt.v vd, vs2, vm Vector-vector square root ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Square-Root Instruction", + "line_range": [ + 3459, + 3462 + ] + }, + { + "text": "---- Floating-point reciprocal square-root estimate to 7 bits. vfrsqrt7.v vd, vs2, vm ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Square-Root Estimate Instruction", + "line_range": [ + 3466, + 3469 + ] + }, + { + "text": "This is a unary vector-vector instruction that returns an estimate of 1/sqrt(x) accurate to 7 bits.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Square-Root Estimate Instruction", + "line_range": [ + 3471, + 3472 + ] + }, + { + "text": "NOTE: An earlier draft version had used the assembler name `vfrsqrte7` but this was deemed to cause confusion with the ``e``x notation for element width.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Square-Root Estimate Instruction", + "line_range": [ + 3474, + 3477 + ] + }, + { + "text": "The earlier name can be retained as alias in tool chains for backward compatibility.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Square-Root Estimate Instruction", + "line_range": [ + 3474, + 3477 + ] + }, + { + "text": "The following table describes the instruction's behavior for all classes of floating-point inputs:", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Square-Root Estimate Instruction", + "line_range": [ + 3479, + 3480 + ] + }, + { + "text": "[cols=\"1,1,1\"] | | Input | Output | Exceptions raised", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Square-Root Estimate Instruction", + "line_range": [ + 3482, + 3485 + ] + }, + { + "text": "| -{inf} {le} x < -0.0 | canonical NaN | NV | -0.0 | -{inf} | DZ | +0.0 | +{inf} | DZ | +0.0 < x < +{inf} | estimate of 1/sqrt(x) | | +{inf} | +0.0 | | qNaN | canonical NaN | | sNaN | canonical NaN | NV |", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Square-Root Estimate Instruction", + "line_range": [ + 3487, + 3494 + ] + }, + { + "text": "NOTE: All positive normal and subnormal inputs produce normal outputs.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Square-Root Estimate Instruction", + "line_range": [ + 3496, + 3496 + ] + }, + { + "text": "NOTE: The output value is independent of the dynamic rounding mode.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Square-Root Estimate Instruction", + "line_range": [ + 3498, + 3498 + ] + }, + { + "text": "For the non-exceptional cases, the low bit of the exponent and the six high bits of significand (after the leading one) are concatenated and used to address the following table.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Square-Root Estimate Instruction", + "line_range": [ + 3500, + 3508 + ] + }, + { + "text": "The output of the table becomes the seven high bits of the result significand (after the leading one); the remainder of the result significand is zero.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Square-Root Estimate Instruction", + "line_range": [ + 3500, + 3508 + ] + }, + { + "text": "Subnormal inputs are normalized and the exponent adjusted appropriately before the lookup.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Square-Root Estimate Instruction", + "line_range": [ + 3500, + 3508 + ] + }, + { + "text": "The output exponent is chosen to make the result approximate the reciprocal of the square root of the argument.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Square-Root Estimate Instruction", + "line_range": [ + 3500, + 3508 + ] + }, + { + "text": "More precisely, the result is computed as follows.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Square-Root Estimate Instruction", + "line_range": [ + 3510, + 3518 + ] + }, + { + "text": "Let the normalized input exponent be equal to the input exponent if the input is normal, or 0 minus the number of leading zeros in the significand otherwise.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Square-Root Estimate Instruction", + "line_range": [ + 3510, + 3518 + ] + }, + { + "text": "If the input is subnormal, the normalized input significand is given by shifting the input significand left by 1 minus the normalized input exponent, discarding the leading 1 bit.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Square-Root Estimate Instruction", + "line_range": [ + 3510, + 3518 + ] + }, + { + "text": "The output exponent equals floor((3*B - 1 - the normalized input exponent) / 2), where B is the exponent bias.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Square-Root Estimate Instruction", + "line_range": [ + 3510, + 3518 + ] + }, + { + "text": "The output sign equals the input sign.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Square-Root Estimate Instruction", + "line_range": [ + 3510, + 3518 + ] + }, + { + "text": "The following table gives the seven MSBs of the output significand as a function of the LSB of the normalized input exponent and the six MSBs of the normalized input significand; the other bits of the output significand are zero.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Square-Root Estimate Instruction", + "line_range": [ + 3520, + 3522 + ] + }, + { + "text": "NOTE: For example, when SEW=32, vfrsqrt7(0x00718abc ({approx} 1.043e-38)) = 0x5f080000 ({approx} 9.800e18), and vfrsqrt7(0x7f765432 ({approx} 3.274e38)) = 0x1f820000 ({approx} 5.506e-20).", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Square-Root Estimate Instruction", + "line_range": [ + 3526, + 3526 + ] + }, + { + "text": "NOTE: The 7 bit accuracy was chosen as it requires 0,1,2,3 Newton-Raphson iterations to converge to close to bfloat16, FP16, FP32, FP64 accuracy respectively.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Square-Root Estimate Instruction", + "line_range": [ + 3528, + 3531 + ] + }, + { + "text": "Future instructions can be defined with greater estimate accuracy.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Square-Root Estimate Instruction", + "line_range": [ + 3528, + 3531 + ] + }, + { + "text": "---- Floating-point reciprocal estimate to 7 bits. vfrec7.v vd, vs2, vm ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Estimate Instruction", + "line_range": [ + 3535, + 3538 + ] + }, + { + "text": "NOTE: An earlier draft version had used the assembler name `vfrece7` but this was deemed to cause confusion with ``e``x notation for element width.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Estimate Instruction", + "line_range": [ + 3540, + 3543 + ] + }, + { + "text": "The earlier name can be retained as alias in tool chains for backward compatibility.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Estimate Instruction", + "line_range": [ + 3540, + 3543 + ] + }, + { + "text": "This is a unary vector-vector instruction that returns an estimate of 1/x accurate to 7 bits.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Estimate Instruction", + "line_range": [ + 3545, + 3546 + ] + }, + { + "text": "The following table describes the instruction's behavior for all classes of floating-point inputs, where B is the exponent bias:", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Estimate Instruction", + "line_range": [ + 3548, + 3549 + ] + }, + { + "text": "[cols=\"1,1,1,1\"] | | Input (x) | Rounding Mode | Output (y {approx} 1/x) | Exceptions raised", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Estimate Instruction", + "line_range": [ + 3551, + 3554 + ] + }, + { + "text": "| -{inf} | any | -0.0 | | -2^B+1^ < x {le} -2^B^ (normal) | any | -2^-(B+1)^ {ge} y > -2^-B^ (subnormal, sig=01...) | | -2^B^ < x {le} -2^B-1^ (normal) | any | -2^-B^ {ge} y > -2^-B+1^ (subnormal, sig=1...) | | -2^B-1^ < x {le} -2^-B+1^ (normal) | any | -2^-B+1^ {ge} y > -2^B-1^ (normal) | | -2^-B+1^ < x {le} -2^-B^ (subnormal, sig=1...) | any | -2^B-1^ {ge} y > -2^B^ (normal) | | -2^-B^ < x {le} -2^-(B+1)^ (subnormal, sig=01...) | any | -2^B^ {ge} y > -2^B+1^ (normal) | | -2^-(B+1)^ < x < -0.0 (subnormal, sig=00...) | RUP, RTZ | greatest-mag. negative finite value | NX, OF | -2^-(B+1)^ < x < -0.0 (subnormal, sig=00...) | RDN, RNE, RMM | -{inf} | NX, OF | -0.0 | any | -{inf} | DZ | +0.0 | any | +{inf} | DZ | +0.0 < x < 2^-(B+1)^ (subnormal, sig=00...) | RUP, RNE, RMM | +{inf} | NX, OF | +0.0 < x < 2^-(B+1)^ (subnormal, sig=00...) | RDN, RTZ | greatest finite value | NX, OF | 2^-(B+1)^ {le} x < 2^-B^ (subnormal, sig=01...) | any | 2^B+1^ > y {ge} 2^B^ (normal) | | 2^-B^ {le} x < 2^-B+1^ (subnormal, sig=1...) | any | 2^B^ > y {ge} 2^B-1^ (normal) | | 2^-B+1^ {le} x < 2^B-1^ (normal) | any | 2^B-1^ > y {ge} 2^-B+1^ (normal) | | 2^B-1^ {le} x < 2^B^ (normal) | any | 2^-B+1^ > y {ge} 2^-B^ (subnormal, sig=1...) | | 2^B^ {le} x < 2^B+1^ (normal) | any | 2^-B^ > y {ge} 2^-(B+1)^ (subnormal, sig=01...) | | +{inf} | any | +0.0 | | qNaN | any | canonical NaN | | sNaN | any | canonical NaN | NV |", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Estimate Instruction", + "line_range": [ + 3556, + 3576 + ] + }, + { + "text": "NOTE: Subnormal inputs with magnitude at least 2^-(B+1)^ produce normal outputs; other subnormal inputs produce infinite outputs.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Estimate Instruction", + "line_range": [ + 3578, + 3581 + ] + }, + { + "text": "Normal inputs with magnitude at least 2^B-1^ produce subnormal outputs; other normal inputs produce normal outputs.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Estimate Instruction", + "line_range": [ + 3578, + 3581 + ] + }, + { + "text": "NOTE: The output value depends on the dynamic rounding mode when the overflow exception is raised.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Estimate Instruction", + "line_range": [ + 3583, + 3584 + ] + }, + { + "text": "For the non-exceptional cases, the seven high bits of significand (after the leading one) are used to address the following table.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Estimate Instruction", + "line_range": [ + 3586, + 3593 + ] + }, + { + "text": "The output of the table becomes the seven high bits of the result significand (after the leading one); the remainder of the result significand is zero.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Estimate Instruction", + "line_range": [ + 3586, + 3593 + ] + }, + { + "text": "Subnormal inputs are normalized and the exponent adjusted appropriately before the lookup.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Estimate Instruction", + "line_range": [ + 3586, + 3593 + ] + }, + { + "text": "The output exponent is chosen to make the result approximate the reciprocal of the argument, and subnormal outputs are denormalized accordingly.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Estimate Instruction", + "line_range": [ + 3586, + 3593 + ] + }, + { + "text": "More precisely, the result is computed as follows.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Estimate Instruction", + "line_range": [ + 3595, + 3601 + ] + }, + { + "text": "Let the normalized input exponent be equal to the input exponent if the input is normal, or 0 minus the number of leading zeros in the significand otherwise.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Estimate Instruction", + "line_range": [ + 3595, + 3601 + ] + }, + { + "text": "The normalized output exponent equals (2*B - 1 - the normalized input exponent).", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Estimate Instruction", + "line_range": [ + 3595, + 3601 + ] + }, + { + "text": "If the normalized output exponent is outside the range [-1, 2*B], the result corresponds to one of the exceptional cases in the table above.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Estimate Instruction", + "line_range": [ + 3595, + 3601 + ] + }, + { + "text": "If the input is subnormal, the normalized input significand is given by shifting the input significand left by 1 minus the normalized input exponent, discarding the leading 1 bit.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Estimate Instruction", + "line_range": [ + 3603, + 3609 + ] + }, + { + "text": "Otherwise, the normalized input significand equals the input significand.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Estimate Instruction", + "line_range": [ + 3603, + 3609 + ] + }, + { + "text": "The following table gives the seven MSBs of the normalized output significand as a function of the seven MSBs of the normalized input significand; the other bits of the normalized output significand are zero.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Estimate Instruction", + "line_range": [ + 3603, + 3609 + ] + }, + { + "text": "If the normalized output exponent is 0 or -1, the result is subnormal: the output exponent is 0, and the output significand is given by concatenating a 1 bit to the left of the normalized output significand, then shifting that quantity right by 1 minus the normalized output exponent.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Estimate Instruction", + "line_range": [ + 3613, + 3619 + ] + }, + { + "text": "Otherwise, the output exponent equals the normalized output exponent, and the output significand equals the normalized output significand.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Estimate Instruction", + "line_range": [ + 3613, + 3619 + ] + }, + { + "text": "The output sign equals the input sign.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Estimate Instruction", + "line_range": [ + 3613, + 3619 + ] + }, + { + "text": "NOTE: For example, when SEW=32, vfrec7(0x00718abc ({approx} 1.043e-38)) = 0x7e900000 ({approx} 9.570e37), and vfrec7(0x7f765432 ({approx} 3.274e38)) = 0x00214000 ({approx} 3.053e-39).", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Estimate Instruction", + "line_range": [ + 3621, + 3621 + ] + }, + { + "text": "NOTE: The 7 bit accuracy was chosen as it requires 0,1,2,3 Newton-Raphson iterations to converge to close to bfloat16, FP16, FP32, FP64 accuracy respectively.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Estimate Instruction", + "line_range": [ + 3623, + 3626 + ] + }, + { + "text": "Future instructions can be defined with greater estimate accuracy.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Reciprocal Estimate Instruction", + "line_range": [ + 3623, + 3626 + ] + }, + { + "text": "The vector floating-point `vfmin` and `vfmax` instructions have the same behavior as the corresponding scalar floating-point instructions in version 2.2 of the RISC-V F/D/Q extension: they perform the `minimumNumber` or `maximumNumber` operation on active elements.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point MIN/MAX Instructions", + "line_range": [ + 3630, + 3633 + ] + }, + { + "text": "---- Floating-point minimum vfmin.vv vd, vs2, vs1, vm Vector-vector vfmin.vf vd, vs2, rs1, vm vector-scalar", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point MIN/MAX Instructions", + "line_range": [ + 3635, + 3638 + ] + }, + { + "text": "Floating-point maximum vfmax.vv vd, vs2, vs1, vm Vector-vector vfmax.vf vd, vs2, rs1, vm vector-scalar ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point MIN/MAX Instructions", + "line_range": [ + 3640, + 3643 + ] + }, + { + "text": "Vector versions of the scalar sign-injection instructions.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Sign-Injection Instructions", + "line_range": [ + 3647, + 3648 + ] + }, + { + "text": "The result takes all bits except the sign bit from the vector `vs2` operands.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Sign-Injection Instructions", + "line_range": [ + 3647, + 3648 + ] + }, + { + "text": "---- vfsgnj.vv vd, vs2, vs1, vm Vector-vector vfsgnj.vf vd, vs2, rs1, vm vector-scalar", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Sign-Injection Instructions", + "line_range": [ + 3650, + 3652 + ] + }, + { + "text": "vfsgnjn.vv vd, vs2, vs1, vm Vector-vector vfsgnjn.vf vd, vs2, rs1, vm vector-scalar", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Sign-Injection Instructions", + "line_range": [ + 3654, + 3655 + ] + }, + { + "text": "vfsgnjx.vv vd, vs2, vs1, vm Vector-vector vfsgnjx.vf vd, vs2, rs1, vm vector-scalar ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Sign-Injection Instructions", + "line_range": [ + 3657, + 3659 + ] + }, + { + "text": "NOTE: A vector of floating-point values can be negated using a sign-injection instruction with both source operands set to the same vector operand.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Sign-Injection Instructions", + "line_range": [ + 3661, + 3663 + ] + }, + { + "text": "An assembly pseudoinstruction is provided: `vfneg.v vd,vs` = `vfsgnjn.vv vd,vs,vs`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Sign-Injection Instructions", + "line_range": [ + 3661, + 3663 + ] + }, + { + "text": "NOTE: The absolute value of a vector of floating-point elements can be calculated using a sign-injection instruction with both source operands set to the same vector operand.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Sign-Injection Instructions", + "line_range": [ + 3665, + 3668 + ] + }, + { + "text": "An assembly pseudoinstruction is provided: `vfabs.v vd,vs` = `vfsgnjx.vv vd,vs,vs`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Sign-Injection Instructions", + "line_range": [ + 3665, + 3668 + ] + }, + { + "text": "These vector FP compare instructions compare two source operands and write the comparison result to a mask register.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Compare Instructions", + "line_range": [ + 3672, + 3678 + ] + }, + { + "text": "The destination mask vector is always held in a single vector register, with a layout of elements as described in .", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Compare Instructions", + "line_range": [ + 3672, + 3678 + ] + }, + { + "text": "The destination mask vector register may be the same as the source vector mask register (`v0`).", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Compare Instructions", + "line_range": [ + 3672, + 3678 + ] + }, + { + "text": "Compares write mask registers, and so always operate under a tail-agnostic policy.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Compare Instructions", + "line_range": [ + 3672, + 3678 + ] + }, + { + "text": "The compare instructions follow the semantics of the scalar floating-point compare instructions. `vmfeq` and `vmfne` raise the invalid operation exception only on signaling NaN inputs. `vmflt`, `vmfle`, `vmfgt`, and `vmfge` raise the invalid operation exception on both signaling and quiet NaN inputs. `vmfne` writes 1 to the destination element when either operand is NaN, whereas the other compares write 0 when either operand is NaN.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Compare Instructions", + "line_range": [ + 3680, + 3687 + ] + }, + { + "text": "---- Compare equal vmfeq.vv vd, vs2, vs1, vm Vector-vector vmfeq.vf vd, vs2, rs1, vm vector-scalar", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Compare Instructions", + "line_range": [ + 3689, + 3692 + ] + }, + { + "text": "Compare not equal vmfne.vv vd, vs2, vs1, vm Vector-vector vmfne.vf vd, vs2, rs1, vm vector-scalar", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Compare Instructions", + "line_range": [ + 3694, + 3696 + ] + }, + { + "text": "Compare less than vmflt.vv vd, vs2, vs1, vm Vector-vector vmflt.vf vd, vs2, rs1, vm vector-scalar", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Compare Instructions", + "line_range": [ + 3698, + 3700 + ] + }, + { + "text": "Compare less than or equal vmfle.vv vd, vs2, vs1, vm Vector-vector vmfle.vf vd, vs2, rs1, vm vector-scalar", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Compare Instructions", + "line_range": [ + 3702, + 3704 + ] + }, + { + "text": "Compare greater than vmfgt.vf vd, vs2, rs1, vm vector-scalar", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Compare Instructions", + "line_range": [ + 3706, + 3707 + ] + }, + { + "text": "Compare greater than or equal vmfge.vf vd, vs2, rs1, vm vector-scalar ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Compare Instructions", + "line_range": [ + 3709, + 3711 + ] + }, + { + "text": "---- Comparison Assembler Mapping Assembler pseudoinstruction", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Compare Instructions", + "line_range": [ + 3713, + 3714 + ] + }, + { + "text": "va < vb vmflt.vv vd, va, vb, vm va <= vb vmfle.vv vd, va, vb, vm va > vb vmflt.vv vd, vb, va, vm vmfgt.vv vd, va, vb, vm va >= vb vmfle.vv vd, vb, va, vm vmfge.vv vd, va, vb, vm", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Compare Instructions", + "line_range": [ + 3716, + 3719 + ] + }, + { + "text": "va < f vmflt.vf vd, va, f, vm va <= f vmfle.vf vd, va, f, vm va > f vmfgt.vf vd, va, f, vm va >= f vmfge.vf vd, va, f, vm", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Compare Instructions", + "line_range": [ + 3721, + 3724 + ] + }, + { + "text": "va, vb vector register groups f scalar floating-point register ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Compare Instructions", + "line_range": [ + 3726, + 3728 + ] + }, + { + "text": "NOTE: Providing all forms is necessary to correctly handle unordered compares for NaNs.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Compare Instructions", + "line_range": [ + 3730, + 3731 + ] + }, + { + "text": "NOTE: C99 floating-point quiet compares can be implemented by masking the signaling compares when either input is NaN, as follows.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Compare Instructions", + "line_range": [ + 3733, + 3736 + ] + }, + { + "text": "When the comparand is a non-NaN constant, the middle two instructions can be omitted.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Compare Instructions", + "line_range": [ + 3733, + 3736 + ] + }, + { + "text": "---- Example of implementing isgreater() vmfeq.vv v0, va, va Only set where A is not NaN. vmfeq.vv v1, vb, vb Only set where B is not NaN. vmand.mm v0, v0, v1 Only set where A and B are ordered, vmfgt.vv v0, va, vb, v0.t so only set flags on ordered values. ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Compare Instructions", + "line_range": [ + 3738, + 3744 + ] + }, + { + "text": "NOTE: In the above sequence, it is tempting to mask the second `vmfeq` instruction and remove the `vmand` instruction, but this more efficient sequence incorrectly fails to raise the invalid exception when an element of `va` contains a quiet NaN and the corresponding element in `vb` contains a signaling NaN.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Compare Instructions", + "line_range": [ + 3746, + 3750 + ] + }, + { + "text": "This is a unary vector-vector instruction that operates in the same way as the scalar classify instruction.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Classify Instruction", + "line_range": [ + 3754, + 3755 + ] + }, + { + "text": "---- vfclass.v vd, vs2, vm Vector-vector ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Classify Instruction", + "line_range": [ + 3757, + 3759 + ] + }, + { + "text": "The 10-bit mask produced by this instruction is placed in the least-significant bits of the result elements.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Classify Instruction", + "line_range": [ + 3761, + 3765 + ] + }, + { + "text": "The upper (SEW-10) bits of the result are filled with zeros.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Classify Instruction", + "line_range": [ + 3761, + 3765 + ] + }, + { + "text": "The instruction is only defined for SEW=16b and above, so the result will always fit in the destination elements.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Classify Instruction", + "line_range": [ + 3761, + 3765 + ] + }, + { + "text": "A vector-scalar floating-point merge instruction is provided, which operates on all body elements from `vstart` up to the current vector length in `vl` regardless of mask value.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Merge Instruction", + "line_range": [ + 3769, + 3771 + ] + }, + { + "text": "The `vfmerge.vfm` instruction is encoded as a masked instruction (`vm=0`).", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Merge Instruction", + "line_range": [ + 3773, + 3776 + ] + }, + { + "text": "At elements where the mask value is zero, the first vector operand is copied to the destination element, otherwise a scalar floating-point register value is copied to the destination element.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Merge Instruction", + "line_range": [ + 3773, + 3776 + ] + }, + { + "text": "---- vfmerge.vfm vd, vs2, rs1, v0 vd[i] = v0.mask[i] ? f[rs1] : vs2[i] ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Merge Instruction", + "line_range": [ + 3778, + 3780 + ] + }, + { + "text": "The vector floating-point move instruction splats a floating-point scalar operand to a vector register group.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Move Instruction", + "line_range": [ + 3784, + 3789 + ] + }, + { + "text": "The instruction copies a scalar `f` register value to all active elements of a vector register group.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Move Instruction", + "line_range": [ + 3784, + 3789 + ] + }, + { + "text": "This instruction is encoded as an unmasked instruction (`vm=1`).", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Move Instruction", + "line_range": [ + 3784, + 3789 + ] + }, + { + "text": "The instruction must have the `vs2` field set to `v0`, with all other values for `vs2` reserved.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Move Instruction", + "line_range": [ + 3784, + 3789 + ] + }, + { + "text": "---- vfmv.v.f vd, rs1 vd[i] = f[rs1] ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Move Instruction", + "line_range": [ + 3791, + 3793 + ] + }, + { + "text": "NOTE: The `vfmv.v.f` instruction shares the encoding with the `vfmerge.vfm` instruction, but with `vm=1` and `vs2=v0`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Vector Floating-Point Move Instruction", + "line_range": [ + 3795, + 3796 + ] + }, + { + "text": "Conversion operations are provided to convert to and from floating-point values and unsigned and signed integers, where both source and destination are SEW wide.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Single-Width Floating-Point/Integer Type-Convert Instructions", + "line_range": [ + 3800, + 3802 + ] + }, + { + "text": "---- vfcvt.xu.f.v vd, vs2, vm Convert float to unsigned integer. vfcvt.x.f.v vd, vs2, vm Convert float to signed integer.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Single-Width Floating-Point/Integer Type-Convert Instructions", + "line_range": [ + 3804, + 3806 + ] + }, + { + "text": "vfcvt.rtz.xu.f.v vd, vs2, vm Convert float to unsigned integer, truncating. vfcvt.rtz.x.f.v vd, vs2, vm Convert float to signed integer, truncating.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Single-Width Floating-Point/Integer Type-Convert Instructions", + "line_range": [ + 3808, + 3809 + ] + }, + { + "text": "vfcvt.f.xu.v vd, vs2, vm Convert unsigned integer to float. vfcvt.f.x.v vd, vs2, vm Convert signed integer to float. ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Single-Width Floating-Point/Integer Type-Convert Instructions", + "line_range": [ + 3811, + 3813 + ] + }, + { + "text": "The conversions follow the same rules on exceptional conditions as the scalar conversion instructions.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Single-Width Floating-Point/Integer Type-Convert Instructions", + "line_range": [ + 3815, + 3818 + ] + }, + { + "text": "The conversions use the dynamic rounding mode in `frm`, except for the `rtz` variants, which round towards zero.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Single-Width Floating-Point/Integer Type-Convert Instructions", + "line_range": [ + 3815, + 3818 + ] + }, + { + "text": "NOTE: The `rtz` variants are provided to accelerate truncating conversions from floating-point to integer, as is common in languages like C and Java.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Single-Width Floating-Point/Integer Type-Convert Instructions", + "line_range": [ + 3820, + 3821 + ] + }, + { + "text": "A set of conversion instructions is provided to convert between narrower integer and floating-point datatypes to a type of twice the width.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Widening Floating-Point/Integer Type-Convert Instructions", + "line_range": [ + 3825, + 3827 + ] + }, + { + "text": "---- vfwcvt.xu.f.v vd, vs2, vm Convert float to double-width unsigned integer. vfwcvt.x.f.v vd, vs2, vm Convert float to double-width signed integer.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Widening Floating-Point/Integer Type-Convert Instructions", + "line_range": [ + 3829, + 3831 + ] + }, + { + "text": "vfwcvt.rtz.xu.f.v vd, vs2, vm Convert float to double-width unsigned integer, truncating. vfwcvt.rtz.x.f.v vd, vs2, vm Convert float to double-width signed integer, truncating.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Widening Floating-Point/Integer Type-Convert Instructions", + "line_range": [ + 3833, + 3834 + ] + }, + { + "text": "vfwcvt.f.xu.v vd, vs2, vm Convert unsigned integer to double-width float. vfwcvt.f.x.v vd, vs2, vm Convert signed integer to double-width float.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Widening Floating-Point/Integer Type-Convert Instructions", + "line_range": [ + 3836, + 3837 + ] + }, + { + "text": "vfwcvt.f.f.v vd, vs2, vm Convert single-width float to double-width float. ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Widening Floating-Point/Integer Type-Convert Instructions", + "line_range": [ + 3839, + 3840 + ] + }, + { + "text": "These instructions have the same constraints on vector register overlap as other widening instructions (see ).", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Widening Floating-Point/Integer Type-Convert Instructions", + "line_range": [ + 3842, + 3843 + ] + }, + { + "text": "NOTE: A double-width IEEE floating-point value can always represent a single-width integer exactly.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Widening Floating-Point/Integer Type-Convert Instructions", + "line_range": [ + 3845, + 3846 + ] + }, + { + "text": "NOTE: A double-width IEEE floating-point value can always represent a single-width IEEE floating-point value exactly.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Widening Floating-Point/Integer Type-Convert Instructions", + "line_range": [ + 3848, + 3849 + ] + }, + { + "text": "NOTE: A full set of floating-point widening conversions is not supported as single instructions, but any widening conversion can be implemented as several doubling steps with equivalent results and no additional exception flags raised.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Widening Floating-Point/Integer Type-Convert Instructions", + "line_range": [ + 3851, + 3854 + ] + }, + { + "text": "A set of conversion instructions is provided to convert wider integer and floating-point datatypes to a type of half the width.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Narrowing Floating-Point/Integer Type-Convert Instructions", + "line_range": [ + 3858, + 3859 + ] + }, + { + "text": "---- vfncvt.xu.f.w vd, vs2, vm Convert double-width float to unsigned integer. vfncvt.x.f.w vd, vs2, vm Convert double-width float to signed integer.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Narrowing Floating-Point/Integer Type-Convert Instructions", + "line_range": [ + 3861, + 3863 + ] + }, + { + "text": "vfncvt.rtz.xu.f.w vd, vs2, vm Convert double-width float to unsigned integer, truncating. vfncvt.rtz.x.f.w vd, vs2, vm Convert double-width float to signed integer, truncating.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Narrowing Floating-Point/Integer Type-Convert Instructions", + "line_range": [ + 3865, + 3866 + ] + }, + { + "text": "vfncvt.f.xu.w vd, vs2, vm Convert double-width unsigned integer to float. vfncvt.f.x.w vd, vs2, vm Convert double-width signed integer to float.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Narrowing Floating-Point/Integer Type-Convert Instructions", + "line_range": [ + 3868, + 3869 + ] + }, + { + "text": "vfncvt.f.f.w vd, vs2, vm Convert double-width float to single-width float. vfncvt.rod.f.f.w vd, vs2, vm Convert double-width float to single-width float, rounding towards odd. ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Narrowing Floating-Point/Integer Type-Convert Instructions", + "line_range": [ + 3871, + 3874 + ] + }, + { + "text": "These instructions have the same constraints on vector register overlap as other narrowing instructions (see ).", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Narrowing Floating-Point/Integer Type-Convert Instructions", + "line_range": [ + 3876, + 3877 + ] + }, + { + "text": "NOTE: A full set of floating-point narrowing conversions is not supported as single instructions.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Narrowing Floating-Point/Integer Type-Convert Instructions", + "line_range": [ + 3879, + 3884 + ] + }, + { + "text": "Conversions can be implemented in a sequence of halving steps.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Narrowing Floating-Point/Integer Type-Convert Instructions", + "line_range": [ + 3879, + 3884 + ] + }, + { + "text": "Results are equivalently rounded and the same exception flags are raised if all but the last halving step use round-towards-odd (`vfncvt.rod.f.f.w`).", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Narrowing Floating-Point/Integer Type-Convert Instructions", + "line_range": [ + 3879, + 3884 + ] + }, + { + "text": "Only the final step should use the desired rounding mode.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Narrowing Floating-Point/Integer Type-Convert Instructions", + "line_range": [ + 3879, + 3884 + ] + }, + { + "text": "NOTE: For `vfncvt.rod.f.f.w`, a finite value that exceeds the range of the destination format is converted to the destination format's largest finite value with the same sign.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Floating-Point Instructions > Narrowing Floating-Point/Integer Type-Convert Instructions", + "line_range": [ + 3886, + 3887 + ] + }, + { + "text": "Vector reduction operations take a vector register group of elements and a scalar held in element 0 of a vector register, and perform a reduction using some binary operator, to produce a scalar result in element 0 of a vector register.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations", + "line_range": [ + 3891, + 3897 + ] + }, + { + "text": "The scalar input and output operands are held in element 0 of a single vector register, not a vector register group, so any vector register can be the scalar source or destination of a vector reduction regardless of LMUL setting.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations", + "line_range": [ + 3891, + 3897 + ] + }, + { + "text": "The destination vector register can overlap the source operands, including the mask register.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations", + "line_range": [ + 3899, + 3900 + ] + }, + { + "text": "NOTE: Vector reductions read and write the scalar operand and result into element 0 of a vector register instead of a scalar register to avoid a loss of decoupling with the scalar processor, and to support future polymorphic use with future types not supported in the scalar unit.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations", + "line_range": [ + 3902, + 3906 + ] + }, + { + "text": "Inactive elements from the source vector register group are excluded from the reduction, but the scalar operand is always included regardless of the mask values.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations", + "line_range": [ + 3908, + 3910 + ] + }, + { + "text": "The other elements in the destination vector register ( 0 < index < VLEN/SEW) are considered the tail and are managed with the current tail agnostic/undisturbed policy.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations", + "line_range": [ + 3912, + 3914 + ] + }, + { + "text": "If `vl`=0, no operation is performed and the destination register is not updated.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations", + "line_range": [ + 3916, + 3917 + ] + }, + { + "text": "NOTE: This choice of behavior for `vl`=0 reduces implementation complexity as it is consistent with other operations on vector register state.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations", + "line_range": [ + 3919, + 3930 + ] + }, + { + "text": "For the common case that the source and destination scalar operand are the same vector register, this behavior also produces the expected result.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations", + "line_range": [ + 3919, + 3930 + ] + }, + { + "text": "For the uncommon case that the source and destination scalar operand are in different vector registers, this instruction will not copy the source into the destination when `vl`=0.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations", + "line_range": [ + 3919, + 3930 + ] + }, + { + "text": "However, it is expected that in most of these cases it will be statically known that `vl` is not zero.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations", + "line_range": [ + 3919, + 3930 + ] + }, + { + "text": "In other cases, a check for `vl`=0 will have to be added to ensure that the source scalar is copied to the destination (e.g., by explicitly setting `vl`=1 and performing a register-register copy).", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations", + "line_range": [ + 3919, + 3930 + ] + }, + { + "text": "Traps on vector reduction instructions are always reported with a `vstart` of 0.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations", + "line_range": [ + 3932, + 3934 + ] + }, + { + "text": "Vector reduction operations raise an illegal-instruction exception if `vstart` is non-zero.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations", + "line_range": [ + 3932, + 3934 + ] + }, + { + "text": "The assembler syntax for a reduction operation is `vredop.vs`, where the `.vs` suffix denotes the first operand is a vector register group and the second operand is a scalar stored in element 0 of a vector register.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations", + "line_range": [ + 3936, + 3939 + ] + }, + { + "text": "All operands and results of single-width reduction instructions have the same SEW width.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations > Vector Single-Width Integer Reduction Instructions", + "line_range": [ + 3944, + 3945 + ] + }, + { + "text": "Overflows wrap around on arithmetic sums.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations > Vector Single-Width Integer Reduction Instructions", + "line_range": [ + 3944, + 3945 + ] + }, + { + "text": "---- Simple reductions, where [*] denotes all active elements: vredsum.vs vd, vs2, vs1, vm vd[0] = sum( vs1[0] , vs2[*] ) vredmaxu.vs vd, vs2, vs1, vm vd[0] = maxu( vs1[0] , vs2[*] ) vredmax.vs vd, vs2, vs1, vm vd[0] = max( vs1[0] , vs2[*] ) vredminu.vs vd, vs2, vs1, vm vd[0] = minu( vs1[0] , vs2[*] ) vredmin.vs vd, vs2, vs1, vm vd[0] = min( vs1[0] , vs2[*] ) vredand.vs vd, vs2, vs1, vm vd[0] = and( vs1[0] , vs2[*] ) vredor.vs vd, vs2, vs1, vm vd[0] = or( vs1[0] , vs2[*] ) vredxor.vs vd, vs2, vs1, vm vd[0] = xor( vs1[0] , vs2[*] ) ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations > Vector Single-Width Integer Reduction Instructions", + "line_range": [ + 3947, + 3957 + ] + }, + { + "text": "The unsigned `vwredsumu.vs` instruction zero-extends the SEW-wide vector elements before summing them, then adds the 2*SEW-width scalar element, and stores the result in a 2*SEW-width scalar element.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations > Vector Widening Integer Reduction Instructions", + "line_range": [ + 3962, + 3964 + ] + }, + { + "text": "The `vwredsum.vs` instruction sign-extends the SEW-wide vector elements before summing them.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations > Vector Widening Integer Reduction Instructions", + "line_range": [ + 3966, + 3967 + ] + }, + { + "text": "For both `vwredsumu.vs` and `vwredsum.vs`, overflows wrap around.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations > Vector Widening Integer Reduction Instructions", + "line_range": [ + 3969, + 3969 + ] + }, + { + "text": "---- Unsigned sum reduction into double-width accumulator vwredsumu.vs vd, vs2, vs1, vm 2*SEW = 2*SEW + sum(zero-extend(SEW))", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations > Vector Widening Integer Reduction Instructions", + "line_range": [ + 3971, + 3973 + ] + }, + { + "text": "Signed sum reduction into double-width accumulator vwredsum.vs vd, vs2, vs1, vm 2*SEW = 2*SEW + sum(sign-extend(SEW)) ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations > Vector Widening Integer Reduction Instructions", + "line_range": [ + 3975, + 3977 + ] + }, + { + "text": "---- Simple reductions. vfredosum.vs vd, vs2, vs1, vm Ordered sum vfredusum.vs vd, vs2, vs1, vm Unordered sum vfredmax.vs vd, vs2, vs1, vm Maximum value vfredmin.vs vd, vs2, vs1, vm Minimum value ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations > Vector Single-Width Floating-Point Reduction Instructions", + "line_range": [ + 3982, + 3988 + ] + }, + { + "text": "NOTE: Older assembler mnemonic `vfredsum` is retained as alias for `vfredusum`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations > Vector Single-Width Floating-Point Reduction Instructions", + "line_range": [ + 3990, + 3990 + ] + }, + { + "text": "The `vfredosum` instruction must sum the floating-point values in element order, starting with the scalar in `vs1[0]`--that is, it performs the computation:", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations > Vector Single-Width Floating-Point Reduction Instructions > Vector Ordered Single-Width Floating-Point Sum Reduction", + "line_range": [ + 3994, + 3996 + ] + }, + { + "text": "---- vd[0] = (((vs1[0] + vs2[0]) + vs2[1]) + ...) + vs2[vl-1] ---- where each addition operates identically to the scalar floating-point instructions in terms of raising exception flags and generating or propagating special values.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations > Vector Single-Width Floating-Point Reduction Instructions > Vector Ordered Single-Width Floating-Point Sum Reduction", + "line_range": [ + 3998, + 4003 + ] + }, + { + "text": "NOTE: The ordered reduction supports compiler auto-vectorization, while the unordered FP sum allows for faster implementations.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations > Vector Single-Width Floating-Point Reduction Instructions > Vector Ordered Single-Width Floating-Point Sum Reduction", + "line_range": [ + 4005, + 4006 + ] + }, + { + "text": "When the operation is masked (`vm=0`), the masked-off elements do not affect the result or the exception flags.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations > Vector Single-Width Floating-Point Reduction Instructions > Vector Ordered Single-Width Floating-Point Sum Reduction", + "line_range": [ + 4008, + 4009 + ] + }, + { + "text": "If no elements are active, no additions are performed, so the scalar in `vs1[0]` is simply copied to the destination register, without canonicalizing NaN values and without setting any exception flags.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations > Vector Single-Width Floating-Point Reduction Instructions > Vector Ordered Single-Width Floating-Point Sum Reduction", + "line_range": [ + 4011, + 4015 + ] + }, + { + "text": "This behavior preserves the handling of NaNs, exceptions, and rounding when auto-vectorizing a scalar summation loop.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations > Vector Single-Width Floating-Point Reduction Instructions > Vector Ordered Single-Width Floating-Point Sum Reduction", + "line_range": [ + 4011, + 4015 + ] + }, + { + "text": "The unordered sum reduction instruction, `vfredusum`, provides an implementation more freedom in performing the reduction.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations > Vector Single-Width Floating-Point Reduction Instructions > Vector Unordered Single-Width Floating-Point Sum Reduction", + "line_range": [ + 4019, + 4020 + ] + }, + { + "text": "The implementation must produce a result equivalent to a reduction tree composed of binary operator nodes, with the inputs being elements from the source vector register group (`vs2`) and the source scalar value (`vs1[0]`).", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations > Vector Single-Width Floating-Point Reduction Instructions > Vector Unordered Single-Width Floating-Point Sum Reduction", + "line_range": [ + 4022, + 4042 + ] + }, + { + "text": "Each operator in the tree accepts two inputs and produces one result.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations > Vector Single-Width Floating-Point Reduction Instructions > Vector Unordered Single-Width Floating-Point Sum Reduction", + "line_range": [ + 4022, + 4042 + ] + }, + { + "text": "Each operator first computes an exact sum as a RISC-V scalar floating-point addition with infinite exponent range and precision, then converts this exact sum to a floating-point format with range and precision each at least as great as the element floating-point format indicated by SEW, rounding using the currently active floating-point dynamic rounding mode and raising exception flags as necessary. A different floating-point range and precision may be chosen for the result of each operator. A node where one input is derived only from elements masked-off or beyond the active vector length may either treat that input as the additive identity of the appropriate EEW or simply copy the other input to its output.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations > Vector Single-Width Floating-Point Reduction Instructions > Vector Unordered Single-Width Floating-Point Sum Reduction", + "line_range": [ + 4022, + 4042 + ] + }, + { + "text": "The rounded result from the root node in the tree is converted (rounded again, using the dynamic rounding mode) to the standard floating-point format indicated by SEW.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations > Vector Single-Width Floating-Point Reduction Instructions > Vector Unordered Single-Width Floating-Point Sum Reduction", + "line_range": [ + 4022, + 4042 + ] + }, + { + "text": "An implementation is allowed to add an additional additive identity to the final result.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations > Vector Single-Width Floating-Point Reduction Instructions > Vector Unordered Single-Width Floating-Point Sum Reduction", + "line_range": [ + 4022, + 4042 + ] + }, + { + "text": "The additive identity is +0.0 when rounding down (towards -{inf}) or -0.0 for all other rounding modes.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations > Vector Single-Width Floating-Point Reduction Instructions > Vector Unordered Single-Width Floating-Point Sum Reduction", + "line_range": [ + 4044, + 4045 + ] + }, + { + "text": "The reduction tree structure must be deterministic for a given value in `vtype` and `vl`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations > Vector Single-Width Floating-Point Reduction Instructions > Vector Unordered Single-Width Floating-Point Sum Reduction", + "line_range": [ + 4047, + 4048 + ] + }, + { + "text": "NOTE: As a consequence of this definition, implementations need not propagate NaN payloads through the reduction tree when no elements are active.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations > Vector Single-Width Floating-Point Reduction Instructions > Vector Unordered Single-Width Floating-Point Sum Reduction", + "line_range": [ + 4050, + 4056 + ] + }, + { + "text": "In particular, if no elements are active and the scalar input is NaN, implementations are permitted to canonicalize the NaN and, if the NaN is signaling, set the invalid exception flag.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations > Vector Single-Width Floating-Point Reduction Instructions > Vector Unordered Single-Width Floating-Point Sum Reduction", + "line_range": [ + 4050, + 4056 + ] + }, + { + "text": "Implementations are alternatively permitted to pass through the original NaN and set no exception flags, as with `vfredosum`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations > Vector Single-Width Floating-Point Reduction Instructions > Vector Unordered Single-Width Floating-Point Sum Reduction", + "line_range": [ + 4050, + 4056 + ] + }, + { + "text": "NOTE: The `vfredosum` instruction is a valid implementation of the `vfredusum` instruction.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations > Vector Single-Width Floating-Point Reduction Instructions > Vector Unordered Single-Width Floating-Point Sum Reduction", + "line_range": [ + 4058, + 4059 + ] + }, + { + "text": "The `vfredmin` and `vfredmax` instructions reduce the scalar argument in `vs1[0]` and active elements in `vs2` using the `minimumNumber` and `maximumNumber` operations, respectively.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations > Vector Single-Width Floating-Point Reduction Instructions > Vector Single-Width Floating-Point Max and Min Reductions", + "line_range": [ + 4063, + 4065 + ] + }, + { + "text": "NOTE: Floating-point max and min reductions should return the same final value and raise the same exception flags regardless of operation order.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations > Vector Single-Width Floating-Point Reduction Instructions > Vector Single-Width Floating-Point Max and Min Reductions", + "line_range": [ + 4067, + 4069 + ] + }, + { + "text": "If no elements are active, the scalar in `vs1[0]` is simply copied to the destination register, without canonicalizing NaN values and without setting any exception flags.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations > Vector Single-Width Floating-Point Reduction Instructions > Vector Single-Width Floating-Point Max and Min Reductions", + "line_range": [ + 4071, + 4073 + ] + }, + { + "text": "Widening forms of the sum reductions are provided that read and write a double-width reduction result.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations > Vector Widening Floating-Point Reduction Instructions", + "line_range": [ + 4078, + 4079 + ] + }, + { + "text": "---- Simple reductions. vfwredosum.vs vd, vs2, vs1, vm Ordered sum vfwredusum.vs vd, vs2, vs1, vm Unordered sum ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations > Vector Widening Floating-Point Reduction Instructions", + "line_range": [ + 4081, + 4085 + ] + }, + { + "text": "NOTE: Older assembler mnemonic `vfwredsum` is retained as alias for `vfwredusum`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations > Vector Widening Floating-Point Reduction Instructions", + "line_range": [ + 4087, + 4087 + ] + }, + { + "text": "The reduction of the SEW-width elements is performed as in the single-width reduction case, with the elements in `vs2` promoted to 2*SEW bits before adding to the 2*SEW-bit accumulator.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations > Vector Widening Floating-Point Reduction Instructions", + "line_range": [ + 4089, + 4091 + ] + }, + { + "text": "NOTE: `vfwredosum.vs` handles inactive elements and NaN payloads analogously to `vfredosum.vs`; `vfwredusum.vs` does so analogously to `vfredusum.vs`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Reduction Operations > Vector Widening Floating-Point Reduction Instructions", + "line_range": [ + 4093, + 4094 + ] + }, + { + "text": "Several instructions are provided to help operate on mask values held in a vector register.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions", + "line_range": [ + 4099, + 4100 + ] + }, + { + "text": "Vector mask-register logical operations operate on mask registers.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Mask-Register Logical Instructions", + "line_range": [ + 4105, + 4110 + ] + }, + { + "text": "Each element in a mask register is a single bit, so these instructions all operate on single vector registers regardless of the setting of the `vlmul` field in `vtype`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Mask-Register Logical Instructions", + "line_range": [ + 4105, + 4110 + ] + }, + { + "text": "They do not change the value of `vlmul`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Mask-Register Logical Instructions", + "line_range": [ + 4105, + 4110 + ] + }, + { + "text": "The destination vector register may be the same as either source vector register.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Mask-Register Logical Instructions", + "line_range": [ + 4105, + 4110 + ] + }, + { + "text": "As with other vector instructions, the elements with indices less than `vstart` are unchanged, and `vstart` is reset to zero after execution.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Mask-Register Logical Instructions", + "line_range": [ + 4112, + 4117 + ] + }, + { + "text": "Vector mask logical instructions are always unmasked, so there are no inactive elements, and the encodings with `vm=0` are reserved.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Mask-Register Logical Instructions", + "line_range": [ + 4112, + 4117 + ] + }, + { + "text": "Mask elements past `vl`, the tail elements, are always updated with a tail-agnostic policy.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Mask-Register Logical Instructions", + "line_range": [ + 4112, + 4117 + ] + }, + { + "text": "---- vmand.mm vd, vs2, vs1 vd.mask[i] = vs2.mask[i] && vs1.mask[i] vmnand.mm vd, vs2, vs1 vd.mask[i] = !(vs2.mask[i] && vs1.mask[i]) vmandn.mm vd, vs2, vs1 vd.mask[i] = vs2.mask[i] && !vs1.mask[i] vmxor.mm vd, vs2, vs1 vd.mask[i] = vs2.mask[i] ^^ vs1.mask[i] vmor.mm vd, vs2, vs1 vd.mask[i] = vs2.mask[i] || vs1.mask[i] vmnor.mm vd, vs2, vs1 vd.mask[i] = !(vs2.mask[i] || vs1.mask[i]) vmorn.mm vd, vs2, vs1 vd.mask[i] = vs2.mask[i] || !vs1.mask[i] vmxnor.mm vd, vs2, vs1 vd.mask[i] = !(vs2.mask[i] ^^ vs1.mask[i]) ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Mask-Register Logical Instructions", + "line_range": [ + 4119, + 4129 + ] + }, + { + "text": "NOTE: The previous assembler mnemonics `vmandnot` and `vmornot` have been changed to `vmandn` and `vmorn` to be consistent with the equivalent scalar instructions.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Mask-Register Logical Instructions", + "line_range": [ + 4131, + 4134 + ] + }, + { + "text": "The old `vmandnot` and `vmornot` mnemonics can be retained as assembler aliases for compatibility.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Mask-Register Logical Instructions", + "line_range": [ + 4131, + 4134 + ] + }, + { + "text": "Several assembler pseudoinstructions are defined as shorthand for common uses of mask logical operations: ---- vmmv.m vd, vs => vmand.mm vd, vs, vs Copy mask register vmclr.m vd => vmxor.mm vd, vd, vd Clear mask register vmset.m vd => vmxnor.mm vd, vd, vd Set mask register vmnot.m vd, vs => vmnand.mm vd, vs, vs Invert bits ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Mask-Register Logical Instructions", + "line_range": [ + 4136, + 4143 + ] + }, + { + "text": "NOTE: The `vmmv.m` instruction was previously called `vmcpy.m`, but with new layout it is more consistent to name as a \"mv\" because bits are copied without interpretation.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Mask-Register Logical Instructions", + "line_range": [ + 4145, + 4151 + ] + }, + { + "text": "The `vmcpy.m` assembler pseudoinstruction can be retained for compatibility.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Mask-Register Logical Instructions", + "line_range": [ + 4145, + 4151 + ] + }, + { + "text": "For implementations that internally rearrange bits according to EEW, a `vmmv.m` instruction with same source and destination can be used as idiom to force an internal reformat into a mask vector.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Mask-Register Logical Instructions", + "line_range": [ + 4145, + 4151 + ] + }, + { + "text": "The set of eight mask logical instructions can generate any of the 16 possibly binary logical functions of the two input masks:", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Mask-Register Logical Instructions", + "line_range": [ + 4153, + 4154 + ] + }, + { + "text": "[cols=\"1,1,1,1,12\"] | 4+| inputs |", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Mask-Register Logical Instructions", + "line_range": [ + 4156, + 4158 + ] + }, + { + "text": "| 0 | 0 | 1 | 1 | src1 | 0 | 1 | 0 | 1 | src2 |", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Mask-Register Logical Instructions", + "line_range": [ + 4160, + 4162 + ] + }, + { + "text": "[cols=\"1,1,1,1,6,6\"] | 4+| output | instruction | pseudoinstruction", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Mask-Register Logical Instructions", + "line_range": [ + 4164, + 4166 + ] + }, + { + "text": "| 0 | 0 | 0 | 0 | vmxor.mm vd, vd, vd | vmclr.m vd | 1 | 0 | 0 | 0 | vmnor.mm vd, src1, src2 | | 0 | 1 | 0 | 0 | vmandn.mm vd, src2, src1 | | 1 | 1 | 0 | 0 | vmnand.mm vd, src1, src1 | vmnot.m vd, src1 | 0 | 0 | 1 | 0 | vmandn.mm vd, src1, src2 | | 1 | 0 | 1 | 0 | vmnand.mm vd, src2, src2 | vmnot.m vd, src2 | 0 | 1 | 1 | 0 | vmxor.mm vd, src1, src2 | | 1 | 1 | 1 | 0 | vmnand.mm vd, src1, src2 | | 0 | 0 | 0 | 1 | vmand.mm vd, src1, src2 | | 1 | 0 | 0 | 1 | vmxnor.mm vd, src1, src2 | | 0 | 1 | 0 | 1 | vmand.mm vd, src2, src2 | vmmv.m vd, src2 | 1 | 1 | 0 | 1 | vmorn.mm vd, src2, src1 | | 0 | 0 | 1 | 1 | vmand.mm vd, src1, src1 | vmmv.m vd, src1 | 1 | 0 | 1 | 1 | vmorn.mm vd, src1, src2 | | 0 | 1 | 1 | 1 | vmor.mm vd, src1, src2 | | 1 | 1 | 1 | 1 | vmxnor.mm vd, vd, vd | vmset.m vd |", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Mask-Register Logical Instructions", + "line_range": [ + 4168, + 4184 + ] + }, + { + "text": "NOTE: The vector mask logical instructions are designed to be easily fused with a following masked vector operation to effectively expand the number of predicate registers by moving values into `v0` before use.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Mask-Register Logical Instructions", + "line_range": [ + 4186, + 4189 + ] + }, + { + "text": "---- vcpop.m rd, vs2, vm ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector count population in mask `vcpop.m`", + "line_range": [ + 4194, + 4196 + ] + }, + { + "text": "NOTE: This instruction previously had the assembler mnemonic `vpopc.m` but was renamed to be consistent with the scalar instruction.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector count population in mask `vcpop.m`", + "line_range": [ + 4198, + 4201 + ] + }, + { + "text": "The assembler instruction alias `vpopc.m` is being retained for software compatibility.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector count population in mask `vcpop.m`", + "line_range": [ + 4198, + 4201 + ] + }, + { + "text": "The source operand is a single vector register holding mask register values as described in .", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector count population in mask `vcpop.m`", + "line_range": [ + 4203, + 4204 + ] + }, + { + "text": "The `vcpop.m` instruction counts the number of mask elements of the active elements of the vector source mask register that have the value 1 and writes the result to a scalar `x` register.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector count population in mask `vcpop.m`", + "line_range": [ + 4206, + 4208 + ] + }, + { + "text": "The operation can be performed under a mask, in which case only the masked elements are counted.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector count population in mask `vcpop.m`", + "line_range": [ + 4210, + 4211 + ] + }, + { + "text": "---- vcpop.m rd, vs2, v0.t x[rd] = sumi ( vs2.mask[i] && v0.mask[i] ) ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector count population in mask `vcpop.m`", + "line_range": [ + 4213, + 4215 + ] + }, + { + "text": "The `vcpop.m` instruction writes `x[rd]` even if `vl`=0 (with the value 0, since no mask elements are active).", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector count population in mask `vcpop.m`", + "line_range": [ + 4217, + 4218 + ] + }, + { + "text": "Traps on `vcpop.m` are always reported with a `vstart` of 0.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector count population in mask `vcpop.m`", + "line_range": [ + 4220, + 4222 + ] + }, + { + "text": "The `vcpop.m` instruction will raise an illegal-instruction exception if `vstart` is non-zero.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector count population in mask `vcpop.m`", + "line_range": [ + 4220, + 4222 + ] + }, + { + "text": "---- vfirst.m rd, vs2, vm ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > `vfirst` find-first-set mask bit", + "line_range": [ + 4226, + 4228 + ] + }, + { + "text": "The `vfirst` instruction finds the lowest-numbered active element of the source mask vector that has the value 1 and writes that element's index to a GPR.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > `vfirst` find-first-set mask bit", + "line_range": [ + 4230, + 4233 + ] + }, + { + "text": "If no active element has the value 1, -1 is written to the GPR.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > `vfirst` find-first-set mask bit", + "line_range": [ + 4230, + 4233 + ] + }, + { + "text": "NOTE: Software can assume that any negative value (highest bit set) corresponds to no element found, as vector lengths will never reach 2^(XLEN-1)^ on any implementation.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > `vfirst` find-first-set mask bit", + "line_range": [ + 4235, + 4237 + ] + }, + { + "text": "The `vfirst.m` instruction writes `x[rd]` even if `vl`=0 (with the value -1, since no mask elements are active).", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > `vfirst` find-first-set mask bit", + "line_range": [ + 4239, + 4240 + ] + }, + { + "text": "Traps on `vfirst` are always reported with a `vstart` of 0.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > `vfirst` find-first-set mask bit", + "line_range": [ + 4242, + 4244 + ] + }, + { + "text": "The `vfirst` instruction will raise an illegal-instruction exception if `vstart` is non-zero.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > `vfirst` find-first-set mask bit", + "line_range": [ + 4242, + 4244 + ] + }, + { + "text": "7 6 5 4 3 2 1 0 Element number", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > `vmsbf.m` set-before-first mask bit", + "line_range": [ + 4253, + 4253 + ] + }, + { + "text": "1 0 0 1 0 1 0 0 v3 contents vmsbf.m v2, v3 0 0 0 0 0 0 1 1 v2 contents", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > `vmsbf.m` set-before-first mask bit", + "line_range": [ + 4255, + 4257 + ] + }, + { + "text": "1 0 0 1 0 1 0 1 v3 contents vmsbf.m v2, v3 0 0 0 0 0 0 0 0 v2", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > `vmsbf.m` set-before-first mask bit", + "line_range": [ + 4259, + 4261 + ] + }, + { + "text": "0 0 0 0 0 0 0 0 v3 contents vmsbf.m v2, v3 1 1 1 1 1 1 1 1 v2", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > `vmsbf.m` set-before-first mask bit", + "line_range": [ + 4263, + 4265 + ] + }, + { + "text": "1 1 0 0 0 0 1 1 v0 vcontents 1 0 0 1 0 1 0 0 v3 contents vmsbf.m v2, v3, v0.t 0 1 x x x x 1 1 v2 contents ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > `vmsbf.m` set-before-first mask bit", + "line_range": [ + 4267, + 4271 + ] + }, + { + "text": "The `vmsbf.m` instruction takes a mask register as input and writes results to a mask register.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > `vmsbf.m` set-before-first mask bit", + "line_range": [ + 4273, + 4278 + ] + }, + { + "text": "The instruction writes a 1 to all active mask elements before the first active source element that is a 1, then writes a 0 to that element and all following active elements.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > `vmsbf.m` set-before-first mask bit", + "line_range": [ + 4273, + 4278 + ] + }, + { + "text": "If there is no set bit in the active elements of the source vector, then all active elements in the destination are written with a 1.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > `vmsbf.m` set-before-first mask bit", + "line_range": [ + 4273, + 4278 + ] + }, + { + "text": "The tail elements in the destination mask register are updated under a tail-agnostic policy.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > `vmsbf.m` set-before-first mask bit", + "line_range": [ + 4280, + 4281 + ] + }, + { + "text": "Traps on `vmsbf.m` are always reported with a `vstart` of 0.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > `vmsbf.m` set-before-first mask bit", + "line_range": [ + 4283, + 4285 + ] + }, + { + "text": "The `vmsbf` instruction will raise an illegal-instruction exception if `vstart` is non-zero.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > `vmsbf.m` set-before-first mask bit", + "line_range": [ + 4283, + 4285 + ] + }, + { + "text": "The destination register cannot overlap the source register and, if masked, cannot overlap the mask register (`v0`).", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > `vmsbf.m` set-before-first mask bit", + "line_range": [ + 4287, + 4288 + ] + }, + { + "text": "The vector mask set-including-first instruction is similar to set-before-first, except it also includes the element with a set bit.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > `vmsif.m` set-including-first mask bit", + "line_range": [ + 4292, + 4293 + ] + }, + { + "text": "7 6 5 4 3 2 1 0 Element number", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > `vmsif.m` set-including-first mask bit", + "line_range": [ + 4300, + 4300 + ] + }, + { + "text": "1 0 0 1 0 1 0 0 v3 contents vmsif.m v2, v3 0 0 0 0 0 1 1 1 v2 contents", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > `vmsif.m` set-including-first mask bit", + "line_range": [ + 4302, + 4304 + ] + }, + { + "text": "1 0 0 1 0 1 0 1 v3 contents vmsif.m v2, v3 0 0 0 0 0 0 0 1 v2", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > `vmsif.m` set-including-first mask bit", + "line_range": [ + 4306, + 4308 + ] + }, + { + "text": "1 1 0 0 0 0 1 1 v0 vcontents 1 0 0 1 0 1 0 0 v3 contents vmsif.m v2, v3, v0.t 1 1 x x x x 1 1 v2 contents ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > `vmsif.m` set-including-first mask bit", + "line_range": [ + 4310, + 4314 + ] + }, + { + "text": "The tail elements in the destination mask register are updated under a tail-agnostic policy.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > `vmsif.m` set-including-first mask bit", + "line_range": [ + 4316, + 4317 + ] + }, + { + "text": "Traps on `vmsif.m` are always reported with a `vstart` of 0.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > `vmsif.m` set-including-first mask bit", + "line_range": [ + 4319, + 4321 + ] + }, + { + "text": "The `vmsif` instruction will raise an illegal-instruction exception if `vstart` is non-zero.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > `vmsif.m` set-including-first mask bit", + "line_range": [ + 4319, + 4321 + ] + }, + { + "text": "The destination register cannot overlap the source register and, if masked, cannot overlap the mask register (`v0`).", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > `vmsif.m` set-including-first mask bit", + "line_range": [ + 4323, + 4324 + ] + }, + { + "text": "The vector mask set-only-first instruction is similar to set-before-first, except it only sets the first element with a bit set, if any.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > `vmsof.m` set-only-first mask bit", + "line_range": [ + 4328, + 4330 + ] + }, + { + "text": "7 6 5 4 3 2 1 0 Element number", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > `vmsof.m` set-only-first mask bit", + "line_range": [ + 4337, + 4337 + ] + }, + { + "text": "1 0 0 1 0 1 0 0 v3 contents vmsof.m v2, v3 0 0 0 0 0 1 0 0 v2 contents", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > `vmsof.m` set-only-first mask bit", + "line_range": [ + 4339, + 4341 + ] + }, + { + "text": "1 0 0 1 0 1 0 1 v3 contents vmsof.m v2, v3 0 0 0 0 0 0 0 1 v2", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > `vmsof.m` set-only-first mask bit", + "line_range": [ + 4343, + 4345 + ] + }, + { + "text": "1 1 0 0 0 0 1 1 v0 vcontents 1 1 0 1 0 1 0 0 v3 contents vmsof.m v2, v3, v0.t 0 1 x x x x 0 0 v2 contents ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > `vmsof.m` set-only-first mask bit", + "line_range": [ + 4347, + 4351 + ] + }, + { + "text": "The tail elements in the destination mask register are updated under a tail-agnostic policy.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > `vmsof.m` set-only-first mask bit", + "line_range": [ + 4353, + 4354 + ] + }, + { + "text": "Traps on `vmsof.m` are always reported with a `vstart` of 0.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > `vmsof.m` set-only-first mask bit", + "line_range": [ + 4356, + 4358 + ] + }, + { + "text": "The `vmsof` instruction will raise an illegal-instruction exception if `vstart` is non-zero.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > `vmsof.m` set-only-first mask bit", + "line_range": [ + 4356, + 4358 + ] + }, + { + "text": "The destination register cannot overlap the source register and, if masked, cannot overlap the mask register (`v0`).", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > `vmsof.m` set-only-first mask bit", + "line_range": [ + 4360, + 4361 + ] + }, + { + "text": "The following is an example of vectorizing a data-dependent exit loop.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Example using vector mask instructions", + "line_range": [ + 4365, + 4365 + ] + }, + { + "text": "---- include::example/strcpy.s[lines=4..-1] ---- ---- include::example/strncpy.s[lines=4..-1] ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Example using vector mask instructions", + "line_range": [ + 4367, + 4372 + ] + }, + { + "text": "The `viota.m` instruction reads a source vector mask register and writes to each element of the destination vector register group the sum of all the bits of elements in the mask register whose index is less than the element, e.g., a parallel prefix sum of the mask values.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Iota Instruction", + "line_range": [ + 4376, + 4380 + ] + }, + { + "text": "This instruction can be masked, in which case only the enabled elements contribute to the sum.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Iota Instruction", + "line_range": [ + 4382, + 4383 + ] + }, + { + "text": "7 6 5 4 3 2 1 0 Element number", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Iota Instruction", + "line_range": [ + 4390, + 4390 + ] + }, + { + "text": "1 0 0 1 0 0 0 1 v2 contents viota.m v4, v2 Unmasked 2 2 2 1 1 1 1 0 v4 result", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Iota Instruction", + "line_range": [ + 4392, + 4394 + ] + }, + { + "text": "1 1 1 0 1 0 1 1 v0 contents 1 0 0 1 0 0 0 1 v2 contents 2 3 4 5 6 7 8 9 v4 contents viota.m v4, v2, v0.t Masked, vtype.vma=0 1 1 1 5 1 7 1 0 v4 results ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Iota Instruction", + "line_range": [ + 4396, + 4401 + ] + }, + { + "text": "The result value is zero-extended to fill the destination element if SEW is wider than the result.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Iota Instruction", + "line_range": [ + 4403, + 4405 + ] + }, + { + "text": "If the result value would overflow the destination SEW, the least-significant SEW bits are retained.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Iota Instruction", + "line_range": [ + 4403, + 4405 + ] + }, + { + "text": "Traps on `viota.m` are always reported with a `vstart` of 0, and execution is always restarted from the beginning when resuming after a trap handler.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Iota Instruction", + "line_range": [ + 4407, + 4410 + ] + }, + { + "text": "An illegal-instruction exception is raised if `vstart` is non-zero.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Iota Instruction", + "line_range": [ + 4407, + 4410 + ] + }, + { + "text": "The destination register group cannot overlap the source register and, if masked, cannot overlap the mask register (`v0`).", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Iota Instruction", + "line_range": [ + 4412, + 4413 + ] + }, + { + "text": "The `viota.m` instruction can be combined with memory scatter instructions (indexed stores) to perform vector compress functions.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Iota Instruction", + "line_range": [ + 4415, + 4416 + ] + }, + { + "text": "---- Compact non-zero elements from input memory array to output memory array sizet compactnonzero(sizet n, const int* in, int* out) { sizet i; int *p = out; for (i=0; i \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Iota Instruction", + "line_range": [ + 4418, + 4438 + ] + }, + { + "text": "compactnonzero: li a6, 0 Clear count of non-zero elements loop: vsetvli a5, a0, e32, m8, ta, ma 32-bit integers vle32.v v8, (a1) Load input vector sub a0, a0, a5 Decrement number done slli a5, a5, 2 Multiply by four bytes vmsne.vi v0, v8, 0 Locate non-zero values add a1, a1, a5 Bump input pointer vcpop.m a5, v0 Count number of elements set in v0 viota.m v16, v0 Get destination offsets of active elements add a6, a6, a5 Accumulate number of elements vsll.vi v16, v16, 2, v0.t Multiply offsets by four bytes slli a5, a5, 2 Multiply number of non-zero elements by four bytes vsuxei32.v v8, (a2), v16, v0.t Scatter using scaled viota results under mask add a2, a2, a5 Bump output pointer bnez a0, loop Any more?", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Iota Instruction", + "line_range": [ + 4440, + 4456 + ] + }, + { + "text": "mv a0, a6 Return count ret ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Iota Instruction", + "line_range": [ + 4458, + 4460 + ] + }, + { + "text": "The `vid.v` instruction writes each element's index to the destination vector register group, from 0 to `vl`-1.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Element Index Instruction", + "line_range": [ + 4464, + 4465 + ] + }, + { + "text": "---- vid.v vd, vm Write element ID to destination. ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Element Index Instruction", + "line_range": [ + 4467, + 4469 + ] + }, + { + "text": "The instruction can be masked.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Element Index Instruction", + "line_range": [ + 4471, + 4472 + ] + }, + { + "text": "Masking does not change the index value written to active elements.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Element Index Instruction", + "line_range": [ + 4471, + 4472 + ] + }, + { + "text": "The `vs2` field of the instruction must be set to `v0`, otherwise the encoding is reserved.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Element Index Instruction", + "line_range": [ + 4474, + 4475 + ] + }, + { + "text": "The result value is zero-extended to fill the destination element if SEW is wider than the result.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Element Index Instruction", + "line_range": [ + 4477, + 4479 + ] + }, + { + "text": "If the result value would overflow the destination SEW, the least-significant SEW bits are retained.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Element Index Instruction", + "line_range": [ + 4477, + 4479 + ] + }, + { + "text": "NOTE: Microarchitectures can implement `vid.v` instruction using the same datapath as `viota.m` but with an implicit set mask source.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Mask Instructions > Vector Element Index Instruction", + "line_range": [ + 4481, + 4482 + ] + }, + { + "text": "A range of permutation instructions are provided to move elements around within the vector registers.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions", + "line_range": [ + 4487, + 4488 + ] + }, + { + "text": "The integer scalar read/write instructions transfer a single value between a scalar `x` register and element 0 of a vector register.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Integer Scalar Move Instructions", + "line_range": [ + 4492, + 4494 + ] + }, + { + "text": "The instructions ignore LMUL and vector register groups.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Integer Scalar Move Instructions", + "line_range": [ + 4492, + 4494 + ] + }, + { + "text": "---- vmv.x.s rd, vs2 x[rd] = vs2[0] (vs1=0) vmv.s.x vd, rs1 vd[0] = x[rs1] (vs2=0) ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Integer Scalar Move Instructions", + "line_range": [ + 4496, + 4499 + ] + }, + { + "text": "The `vmv.x.s` instruction copies a single SEW-wide element from index 0 of the source vector register to a destination integer register.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Integer Scalar Move Instructions", + "line_range": [ + 4501, + 4504 + ] + }, + { + "text": "If SEW > XLEN, the least-significant XLEN bits are transferred and the upper SEW-XLEN bits are ignored.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Integer Scalar Move Instructions", + "line_range": [ + 4501, + 4504 + ] + }, + { + "text": "If SEW < XLEN, the value is sign-extended to XLEN bits.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Integer Scalar Move Instructions", + "line_range": [ + 4501, + 4504 + ] + }, + { + "text": "NOTE: `vmv.x.s` performs its operation even if `vstart` {ge} `vl` or `vl`=0.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Integer Scalar Move Instructions", + "line_range": [ + 4506, + 4506 + ] + }, + { + "text": "The `vmv.s.x` instruction copies the scalar integer register to element 0 of the destination vector register.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Integer Scalar Move Instructions", + "line_range": [ + 4508, + 4513 + ] + }, + { + "text": "If SEW < XLEN, the least-significant bits are copied and the upper XLEN-SEW bits are ignored.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Integer Scalar Move Instructions", + "line_range": [ + 4508, + 4513 + ] + }, + { + "text": "If SEW > XLEN, the value is sign-extended to SEW bits.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Integer Scalar Move Instructions", + "line_range": [ + 4508, + 4513 + ] + }, + { + "text": "The other elements in the destination vector register ( 0 < index < VLEN/SEW) are treated as tail elements using the current tail agnostic/undisturbed policy.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Integer Scalar Move Instructions", + "line_range": [ + 4508, + 4513 + ] + }, + { + "text": "If `vstart` {ge} `vl`, no operation is performed and the destination register is not updated.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Integer Scalar Move Instructions", + "line_range": [ + 4508, + 4513 + ] + }, + { + "text": "NOTE: As a consequence, when `vl`=0, no elements are updated in the destination vector register group, regardless of `vstart`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Integer Scalar Move Instructions", + "line_range": [ + 4515, + 4516 + ] + }, + { + "text": "The encodings corresponding to the masked versions (`vm=0`) of `vmv.x.s` and `vmv.s.x` are reserved.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Integer Scalar Move Instructions", + "line_range": [ + 4518, + 4519 + ] + }, + { + "text": "The floating-point scalar read/write instructions transfer a single value between a scalar `f` register and element 0 of a vector register.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Floating-Point Scalar Move Instructions", + "line_range": [ + 4524, + 4526 + ] + }, + { + "text": "The instructions ignore LMUL and vector register groups.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Floating-Point Scalar Move Instructions", + "line_range": [ + 4524, + 4526 + ] + }, + { + "text": "---- vfmv.f.s rd, vs2 f[rd] = vs2[0] (rs1=0) vfmv.s.f vd, rs1 vd[0] = f[rs1] (vs2=0) ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Floating-Point Scalar Move Instructions", + "line_range": [ + 4528, + 4531 + ] + }, + { + "text": "The `vfmv.f.s` instruction copies a single SEW-wide element from index 0 of the source vector register to a destination scalar floating-point register.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Floating-Point Scalar Move Instructions", + "line_range": [ + 4533, + 4535 + ] + }, + { + "text": "NOTE: `vfmv.f.s` performs its operation even if `vstart` {ge} `vl` or `vl`=0.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Floating-Point Scalar Move Instructions", + "line_range": [ + 4537, + 4537 + ] + }, + { + "text": "The `vfmv.s.f` instruction copies the scalar floating-point register to element 0 of the destination vector register.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Floating-Point Scalar Move Instructions", + "line_range": [ + 4539, + 4544 + ] + }, + { + "text": "The other elements in the destination vector register ( 0 < index < VLEN/SEW) are treated as tail elements using the current tail agnostic/undisturbed policy.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Floating-Point Scalar Move Instructions", + "line_range": [ + 4539, + 4544 + ] + }, + { + "text": "If `vstart` {ge} `vl`, no operation is performed and the destination register is not updated.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Floating-Point Scalar Move Instructions", + "line_range": [ + 4539, + 4544 + ] + }, + { + "text": "NOTE: As a consequence, when `vl`=0, no elements are updated in the destination vector register group, regardless of `vstart`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Floating-Point Scalar Move Instructions", + "line_range": [ + 4546, + 4547 + ] + }, + { + "text": "The encodings corresponding to the masked versions (`vm=0`) of `vfmv.f.s` and `vfmv.s.f` are reserved.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Floating-Point Scalar Move Instructions", + "line_range": [ + 4549, + 4550 + ] + }, + { + "text": "The slide instructions move elements up and down a vector register group.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions", + "line_range": [ + 4554, + 4555 + ] + }, + { + "text": "NOTE: The slide operations can be implemented much more efficiently than using the arbitrary register gather instruction.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions", + "line_range": [ + 4557, + 4561 + ] + }, + { + "text": "Implementations may optimize certain OFFSET values for `vslideup` and `vslidedown`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions", + "line_range": [ + 4557, + 4561 + ] + }, + { + "text": "In particular, power-of-2 offsets may operate substantially faster than other offsets.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions", + "line_range": [ + 4557, + 4561 + ] + }, + { + "text": "For all of the `vslideup`, `vslidedown`, `v[f]slide1up`, and `v[f]slide1down` instructions, if `vstart` {ge} `vl`, the instruction performs no operation and leaves the destination vector register unchanged.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions", + "line_range": [ + 4563, + 4565 + ] + }, + { + "text": "NOTE: As a consequence, when `vl`=0, no elements are updated in the destination vector register group, regardless of `vstart`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions", + "line_range": [ + 4567, + 4568 + ] + }, + { + "text": "The tail agnostic/undisturbed policy is followed for tail elements.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions", + "line_range": [ + 4570, + 4570 + ] + }, + { + "text": "The slide instructions may be masked, with mask element i controlling whether destination element i is written.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions", + "line_range": [ + 4572, + 4574 + ] + }, + { + "text": "The mask undisturbed/agnostic policy is followed for inactive elements.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions", + "line_range": [ + 4572, + 4574 + ] + }, + { + "text": "---- vslideup.vx vd, vs2, rs1, vm vd[i+x[rs1]] = vs2[i] vslideup.vi vd, vs2, uimm, vm vd[i+uimm] = vs2[i] ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-up Instructions", + "line_range": [ + 4578, + 4581 + ] + }, + { + "text": "For `vslideup`, the value in `vl` specifies the maximum number of destination elements that are written.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-up Instructions", + "line_range": [ + 4583, + 4589 + ] + }, + { + "text": "The start index (OFFSET) for the destination can be either specified using an unsigned integer in the `x` register specified by `rs1`, or a 5-bit immediate, zero-extended to XLEN bits.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-up Instructions", + "line_range": [ + 4583, + 4589 + ] + }, + { + "text": "If XLEN > SEW, OFFSET is not truncated to SEW bits.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-up Instructions", + "line_range": [ + 4583, + 4589 + ] + }, + { + "text": "Destination elements OFFSET through `vl`-1 are written if unmasked and if OFFSET < `vl`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-up Instructions", + "line_range": [ + 4583, + 4589 + ] + }, + { + "text": "---- vslideup behavior for destination elements (vstart < vl)", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-up Instructions", + "line_range": [ + 4591, + 4592 + ] + }, + { + "text": "OFFSET is amount to slideup, either from x register or a 5-bit immediate", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-up Instructions", + "line_range": [ + 4594, + 4594 + ] + }, + { + "text": "0 <= i < min(vl, max(vstart, OFFSET)) Unchanged max(vstart, OFFSET) <= i < vl vd[i] = vs2[i-OFFSET] if v0.mask[i] enabled vl <= i < VLMAX Follow tail policy ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-up Instructions", + "line_range": [ + 4596, + 4599 + ] + }, + { + "text": "The destination vector register group for `vslideup` cannot overlap the source vector register group, otherwise the instruction encoding is reserved.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-up Instructions", + "line_range": [ + 4601, + 4603 + ] + }, + { + "text": "NOTE: The non-overlap constraint avoids WAR hazards on the input vectors during execution, and enables restart with non-zero `vstart`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-up Instructions", + "line_range": [ + 4605, + 4607 + ] + }, + { + "text": "---- vslidedown.vx vd, vs2, rs1, vm vd[i] = vs2[i+x[rs1]] vslidedown.vi vd, vs2, uimm, vm vd[i] = vs2[i+uimm] ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-down Instructions", + "line_range": [ + 4611, + 4614 + ] + }, + { + "text": "For `vslidedown`, the value in `vl` specifies the maximum number of destination elements that are written.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-down Instructions", + "line_range": [ + 4616, + 4619 + ] + }, + { + "text": "The remaining elements past `vl` are handled according to the current tail policy ().", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-down Instructions", + "line_range": [ + 4616, + 4619 + ] + }, + { + "text": "The start index (OFFSET) for the source can be either specified using an unsigned integer in the `x` register specified by `rs1`, or a 5-bit immediate, zero-extended to XLEN bits.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-down Instructions", + "line_range": [ + 4621, + 4624 + ] + }, + { + "text": "If XLEN > SEW, OFFSET is not truncated to SEW bits.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-down Instructions", + "line_range": [ + 4621, + 4624 + ] + }, + { + "text": "---- vslidedown behavior for source elements for element i in slide (vstart < vl) 0 <= i+OFFSET < VLMAX src[i] = vs2[i+OFFSET] VLMAX <= i+OFFSET src[i] = 0", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-down Instructions", + "line_range": [ + 4626, + 4629 + ] + }, + { + "text": "vslidedown behavior for destination element i in slide (vstart < vl) 0 <= i < vstart Unchanged vstart <= i < vl vd[i] = src[i] if v0.mask[i] enabled vl <= i < VLMAX Follow tail policy ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-down Instructions", + "line_range": [ + 4631, + 4635 + ] + }, + { + "text": "Variants of slide are provided that only move by one element but which also allow a scalar integer value to be inserted at the vacated element position.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-1-up", + "line_range": [ + 4639, + 4641 + ] + }, + { + "text": "---- vslide1up.vx vd, vs2, rs1, vm vd[0]=x[rs1], vd[i+1] = vs2[i] ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-1-up", + "line_range": [ + 4643, + 4645 + ] + }, + { + "text": "The `vslide1up` instruction places the `x` register argument at location 0 of the destination vector register group, provided that element 0 is active, otherwise the destination element update follows the current mask agnostic/undisturbed policy.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-1-up", + "line_range": [ + 4647, + 4652 + ] + }, + { + "text": "If XLEN < SEW, the value is sign-extended to SEW bits.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-1-up", + "line_range": [ + 4647, + 4652 + ] + }, + { + "text": "If XLEN > SEW, the least-significant bits are copied over and the high XLEN-SEW bits are ignored.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-1-up", + "line_range": [ + 4647, + 4652 + ] + }, + { + "text": "The remaining active `vl`-1 elements are copied over from index i in the source vector register group to index i+1 in the destination vector register group.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-1-up", + "line_range": [ + 4654, + 4656 + ] + }, + { + "text": "The `vl` register specifies the maximum number of destination vector register elements updated with source values, and remaining elements past `vl` are handled according to the current tail policy ().", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-1-up", + "line_range": [ + 4658, + 4661 + ] + }, + { + "text": "---- vslide1up behavior when vl > 0", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-1-up", + "line_range": [ + 4663, + 4664 + ] + }, + { + "text": "i < vstart unchanged 0 = i = vstart vd[i] = x[rs1] if v0.mask[i] enabled max(vstart, 1) <= i < vl vd[i] = vs2[i-1] if v0.mask[i] enabled vl <= i < VLMAX Follow tail policy ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-1-up", + "line_range": [ + 4666, + 4670 + ] + }, + { + "text": "The `vslide1up` instruction requires that the destination vector register group does not overlap the source vector register group.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-1-up", + "line_range": [ + 4672, + 4674 + ] + }, + { + "text": "Otherwise, the instruction encoding is reserved.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-1-up", + "line_range": [ + 4672, + 4674 + ] + }, + { + "text": "---- vfslide1up.vf vd, vs2, rs1, vm vd[0]=f[rs1], vd[i+1] = vs2[i] ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Floating-Point Slide-1-up Instruction", + "line_range": [ + 4680, + 4682 + ] + }, + { + "text": "The `vfslide1up` instruction is defined analogously to `vslide1up`, but sources its scalar argument from an `f` register.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Floating-Point Slide-1-up Instruction", + "line_range": [ + 4684, + 4685 + ] + }, + { + "text": "The `vslide1down` instruction copies the first `vl`-1 active elements values from index i+1 in the source vector register group to index i in the destination vector register group.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-1-down Instruction", + "line_range": [ + 4689, + 4691 + ] + }, + { + "text": "The `vl` register specifies the maximum number of destination vector register elements written with source values, and remaining elements past `vl` are handled according to the current tail policy ().", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-1-down Instruction", + "line_range": [ + 4693, + 4696 + ] + }, + { + "text": "---- vslide1down.vx vd, vs2, rs1, vm vd[i] = vs2[i+1], vd[vl-1]=x[rs1] ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-1-down Instruction", + "line_range": [ + 4698, + 4700 + ] + }, + { + "text": "The `vslide1down` instruction places the `x` register argument at location `vl`-1 in the destination vector register, provided that element `vl-1` is active, otherwise the destination element update follows the current mask agnostic/undisturbed policy.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-1-down Instruction", + "line_range": [ + 4702, + 4708 + ] + }, + { + "text": "If XLEN < SEW, the value is sign-extended to SEW bits.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-1-down Instruction", + "line_range": [ + 4702, + 4708 + ] + }, + { + "text": "If XLEN > SEW, the least-significant bits are copied over and the high SEW-XLEN bits are ignored.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-1-down Instruction", + "line_range": [ + 4702, + 4708 + ] + }, + { + "text": "i < vstart unchanged vstart <= i < vl-1 vd[i] = vs2[i+1] if v0.mask[i] enabled vstart <= i = vl-1 vd[vl-1] = x[rs1] if v0.mask[i] enabled vl <= i < VLMAX Follow tail policy ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-1-down Instruction", + "line_range": [ + 4713, + 4717 + ] + }, + { + "text": "NOTE: The `vslide1down` instruction can be used to load values into a vector register without using memory and without disturbing other vector registers.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-1-down Instruction", + "line_range": [ + 4719, + 4723 + ] + }, + { + "text": "This provides a path for debuggers to modify the contents of a vector register, albeit slowly, with multiple repeated `vslide1down` invocations.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Slide-1-down Instruction", + "line_range": [ + 4719, + 4723 + ] + }, + { + "text": "---- vfslide1down.vf vd, vs2, rs1, vm vd[i] = vs2[i+1], vd[vl-1]=f[rs1] ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Floating-Point Slide-1-down Instruction", + "line_range": [ + 4728, + 4730 + ] + }, + { + "text": "The `vfslide1down` instruction is defined analogously to `vslide1down`, but sources its scalar argument from an `f` register.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Slide Instructions > Vector Floating-Point Slide-1-down Instruction", + "line_range": [ + 4732, + 4733 + ] + }, + { + "text": "The vector register gather instructions read elements from a first source vector register group at locations given by a second source vector register group.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Register Gather Instructions", + "line_range": [ + 4737, + 4745 + ] + }, + { + "text": "The index values in the second vector are treated as unsigned integers.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Register Gather Instructions", + "line_range": [ + 4737, + 4745 + ] + }, + { + "text": "The source vector can be read at any index < VLMAX regardless of `vl`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Register Gather Instructions", + "line_range": [ + 4737, + 4745 + ] + }, + { + "text": "The maximum number of elements to write to the destination register is given by `vl`, and the remaining elements past `vl` are handled according to the current tail policy ().", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Register Gather Instructions", + "line_range": [ + 4737, + 4745 + ] + }, + { + "text": "The operation can be masked, and the mask undisturbed/agnostic policy is followed for inactive elements.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Register Gather Instructions", + "line_range": [ + 4737, + 4745 + ] + }, + { + "text": "---- vrgather.vv vd, vs2, vs1, vm vd[i] = (vs1[i] >= VLMAX) ? 0 : vs2[vs1[i]]; vrgatherei16.vv vd, vs2, vs1, vm vd[i] = (vs1[i] >= VLMAX) ? 0 : vs2[vs1[i]]; ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Register Gather Instructions", + "line_range": [ + 4747, + 4751 + ] + }, + { + "text": "The `vrgather.vv` form uses SEW/LMUL for both the data and indices.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Register Gather Instructions", + "line_range": [ + 4753, + 4755 + ] + }, + { + "text": "The `vrgatherei16.vv` form uses SEW/LMUL for the data in `vs2` but EEW=16 and EMUL = (16/SEW)*LMUL for the indices in `vs1`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Register Gather Instructions", + "line_range": [ + 4753, + 4755 + ] + }, + { + "text": "When SEW=8, `vrgather.vv` can only reference vector elements 0-255.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Register Gather Instructions", + "line_range": [ + 4757, + 4760 + ] + }, + { + "text": "The `vrgatherei16` form can index 64K elements, and can also be used to reduce the register capacity needed to hold indices when SEW > 16.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Register Gather Instructions", + "line_range": [ + 4757, + 4760 + ] + }, + { + "text": "If an element index is out of range ( `vs1[i]` {ge} VLMAX ) then zero is returned for the element value.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Register Gather Instructions", + "line_range": [ + 4762, + 4763 + ] + }, + { + "text": "Vector-scalar and vector-immediate forms of the register gather are also provided.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Register Gather Instructions", + "line_range": [ + 4765, + 4771 + ] + }, + { + "text": "These read one element from the source vector at the given index, and write this value to the active elements of the destination vector register.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Register Gather Instructions", + "line_range": [ + 4765, + 4771 + ] + }, + { + "text": "The index value in the scalar register and the immediate, zero-extended to XLEN bits, are treated as unsigned integers.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Register Gather Instructions", + "line_range": [ + 4765, + 4771 + ] + }, + { + "text": "If XLEN > SEW, the index value is not truncated to SEW bits.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Register Gather Instructions", + "line_range": [ + 4765, + 4771 + ] + }, + { + "text": "NOTE: These forms allow any vector element to be \"splatted\" to an entire vector.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Register Gather Instructions", + "line_range": [ + 4773, + 4773 + ] + }, + { + "text": "---- vrgather.vx vd, vs2, rs1, vm vd[i] = (x[rs1] >= VLMAX) ? 0 : vs2[x[rs1]] vrgather.vi vd, vs2, uimm, vm vd[i] = (uimm >= VLMAX) ? 0 : vs2[uimm] ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Register Gather Instructions", + "line_range": [ + 4775, + 4778 + ] + }, + { + "text": "For any `vrgather` instruction, the destination vector register group cannot overlap with the source vector register groups, otherwise the instruction encoding is reserved.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Register Gather Instructions", + "line_range": [ + 4780, + 4782 + ] + }, + { + "text": "The vector compress instruction allows elements selected by a vector mask register from a source vector register group to be packed into contiguous elements at the start of the destination vector register group.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Compress Instruction", + "line_range": [ + 4786, + 4789 + ] + }, + { + "text": "---- vcompress.vm vd, vs2, vs1 Compress into vd elements of vs2 where vs1 is enabled ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Compress Instruction", + "line_range": [ + 4791, + 4793 + ] + }, + { + "text": "The vector mask register specified by `vs1` indicates which of the first `vl` elements of vector register group `vs2` should be extracted and packed into contiguous elements at the beginning of vector register `vd`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Compress Instruction", + "line_range": [ + 4795, + 4800 + ] + }, + { + "text": "The remaining elements of `vd` are treated as tail elements according to the current tail policy ().", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Compress Instruction", + "line_range": [ + 4795, + 4800 + ] + }, + { + "text": "---- Example use of vcompress instruction", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Compress Instruction", + "line_range": [ + 4802, + 4803 + ] + }, + { + "text": "8 7 6 5 4 3 2 1 0 Element number", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Compress Instruction", + "line_range": [ + 4805, + 4805 + ] + }, + { + "text": "1 1 0 1 0 0 1 0 1 v0 8 7 6 5 4 3 2 1 0 v1 1 2 3 4 5 6 7 8 9 v2 vsetivli t0, 9, e8, m1, tu, ma vcompress.vm v2, v1, v0 1 2 3 4 8 7 5 2 0 v2 ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Compress Instruction", + "line_range": [ + 4807, + 4813 + ] + }, + { + "text": "T`vcompress` is encoded as an unmasked instruction (`vm=1`).", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Compress Instruction", + "line_range": [ + 4815, + 4816 + ] + }, + { + "text": "The equivalent masked instruction (`vm=0`) is reserved.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Compress Instruction", + "line_range": [ + 4815, + 4816 + ] + }, + { + "text": "The destination vector register group cannot overlap the source vector register group or the source mask register, otherwise the instruction encoding is reserved.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Compress Instruction", + "line_range": [ + 4818, + 4820 + ] + }, + { + "text": "A trap on a `vcompress` instruction is always reported with a `vstart` of 0.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Compress Instruction", + "line_range": [ + 4822, + 4824 + ] + }, + { + "text": "Executing a `vcompress` instruction with a non-zero `vstart` raises an illegal-instruction exception.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Compress Instruction", + "line_range": [ + 4822, + 4824 + ] + }, + { + "text": "NOTE: Although possible, `vcompress` is one of the more difficult instructions to restart with a non-zero `vstart`, so assumption is implementations will choose not do that but will instead restart from element 0.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Compress Instruction", + "line_range": [ + 4826, + 4830 + ] + }, + { + "text": "This does mean elements in destination register after `vstart` will already have been updated.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Compress Instruction", + "line_range": [ + 4826, + 4830 + ] + }, + { + "text": "There is no inverse `vdecompress` provided, as this operation can be readily synthesized using iota and a masked vrgather:", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Compress Instruction > Synthesizing `vdecompress`", + "line_range": [ + 4834, + 4835 + ] + }, + { + "text": "---- Desired functionality of 'vdecompress' 7 6 5 4 3 2 1 0 vid", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Compress Instruction > Synthesizing `vdecompress`", + "line_range": [ + 4837, + 4839 + ] + }, + { + "text": "e d c b a packed vector of 5 elements 1 0 0 1 1 1 0 1 mask vector of 8 elements p q r s t u v w destination register before vdecompress", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Compress Instruction > Synthesizing `vdecompress`", + "line_range": [ + 4841, + 4843 + ] + }, + { + "text": "e q r d c b v a result of vdecompress ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Compress Instruction > Synthesizing `vdecompress`", + "line_range": [ + 4845, + 4846 + ] + }, + { + "text": "---- v0 holds mask v1 holds packed data v11 holds input expanded vector and result viota.m v10, v0 Calc iota from mask in v0 vrgather.vv v11, v1, v10, v0.t Expand into destination ---- ---- p q r s t u v w v11 destination register e d c b a v1 source vector 1 0 0 1 1 1 0 1 v0 mask vector", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Compress Instruction > Synthesizing `vdecompress`", + "line_range": [ + 4848, + 4858 + ] + }, + { + "text": "4 4 4 3 2 1 1 0 v10 result of viota.m e q r d c b v a v11 destination after vrgather using viota.m under mask ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Vector Compress Instruction > Synthesizing `vdecompress`", + "line_range": [ + 4860, + 4862 + ] + }, + { + "text": "The `vmvr.v` instructions copy whole vector registers (i.e., all VLEN bits) and can copy whole vector register groups.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Whole Vector Register Move", + "line_range": [ + 4866, + 4870 + ] + }, + { + "text": "The `nr` value in the opcode is the number of individual vector registers, NREG, to copy.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Whole Vector Register Move", + "line_range": [ + 4866, + 4870 + ] + }, + { + "text": "The instructions operate as if EEW=SEW, EMUL = NREG, effective length `evl`= EMUL * VLEN/SEW.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Whole Vector Register Move", + "line_range": [ + 4866, + 4870 + ] + }, + { + "text": "NOTE: These instructions are intended to aid compilers to shuffle vector registers without needing to know or change `vl`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Whole Vector Register Move", + "line_range": [ + 4872, + 4873 + ] + }, + { + "text": "The usual property that no elements are written if `vstart` {ge} `vl` does not apply to these instructions.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Whole Vector Register Move", + "line_range": [ + 4875, + 4880 + ] + }, + { + "text": "Similarly, the property that the instructions are reserved if `vstart` exceeds the largest element index for the current `vtype` setting does not apply.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Whole Vector Register Move", + "line_range": [ + 4875, + 4880 + ] + }, + { + "text": "Instead, the instructions are reserved if `vstart` {ge} `evl`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Whole Vector Register Move", + "line_range": [ + 4875, + 4880 + ] + }, + { + "text": "If `vd` is equal to `vs2`, the instruction does not change any vector register state.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Whole Vector Register Move", + "line_range": [ + 4882, + 4886 + ] + }, + { + "text": "Implementations that rearrange data internally can treat this instruction as a hint that the register group will next be accessed with an EEW equal to SEW.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Whole Vector Register Move", + "line_range": [ + 4882, + 4886 + ] + }, + { + "text": "The instruction is encoded as an OPIVI instruction.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Whole Vector Register Move", + "line_range": [ + 4888, + 4891 + ] + }, + { + "text": "The number of vector registers to copy is encoded in the low three bits of the `simm` field (`simm[2:0]`) using the same encoding as the `nf[2:0]` field for memory instructions (Figure ), i.e., `simm[2:0]` = NREG-1.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Whole Vector Register Move", + "line_range": [ + 4888, + 4891 + ] + }, + { + "text": "The value of NREG must be 1, 2, 4, or 8, and values of `simm[4:0]` other than 0, 1, 3, and 7 are reserved.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Whole Vector Register Move", + "line_range": [ + 4893, + 4894 + ] + }, + { + "text": "NOTE: A future extension may support other numbers of registers to be moved.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Whole Vector Register Move", + "line_range": [ + 4896, + 4896 + ] + }, + { + "text": "NOTE: The instruction uses the same funct6 encoding as the `vsmul` instruction but with an immediate operand, and only the unmasked version (`vm=1`).", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Whole Vector Register Move", + "line_range": [ + 4898, + 4902 + ] + }, + { + "text": "This encoding is chosen as it is close to the related `vmerge` encoding, and it is unlikely the `vsmul` instruction would benefit from an immediate form.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Whole Vector Register Move", + "line_range": [ + 4898, + 4902 + ] + }, + { + "text": "---- vmvr.v vd, vs2 General form", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Whole Vector Register Move", + "line_range": [ + 4904, + 4905 + ] + }, + { + "text": "vmv1r.v v1, v2 Copy v1=v2 vmv2r.v v10, v12 Copy v10=v12; v11=v13 vmv4r.v v4, v8 Copy v4=v8; v5=v9; v6=v10; v7=v11 vmv8r.v v0, v8 Copy v0=v8; v1=v9; ...; v7=v15 ----", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Whole Vector Register Move", + "line_range": [ + 4907, + 4911 + ] + }, + { + "text": "The source and destination vector register numbers must be aligned appropriately for the vector register group size, and encodings with other vector register numbers are reserved.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Whole Vector Register Move", + "line_range": [ + 4913, + 4915 + ] + }, + { + "text": "NOTE: A future extension may relax the vector register alignment restrictions.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Permutation Instructions > Whole Vector Register Move", + "line_range": [ + 4917, + 4918 + ] + }, + { + "text": "On a trap during a vector instruction (caused by either a synchronous exception or an asynchronous interrupt), the existing `*epc` CSR is written with a pointer to the trapping vector instruction, while the `vstart` CSR contains the element index on which the trap was taken.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Exception Handling", + "line_range": [ + 4922, + 4926 + ] + }, + { + "text": "NOTE: We chose to add a `vstart` CSR to allow resumption of a partially executed vector instruction to reduce interrupt latencies and to simplify forward-progress guarantees.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Exception Handling", + "line_range": [ + 4928, + 4936 + ] + }, + { + "text": "This is similar to the scheme in the IBM 3090 vector facility.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Exception Handling", + "line_range": [ + 4928, + 4936 + ] + }, + { + "text": "To ensure forward progress without the `vstart` CSR, implementations would have to guarantee an entire vector instruction can always complete atomically without generating a trap.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Exception Handling", + "line_range": [ + 4928, + 4936 + ] + }, + { + "text": "This is particularly difficult to ensure in the presence of constant-stride or scatter/gather operations and demand-paged virtual memory.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Exception Handling", + "line_range": [ + 4928, + 4936 + ] + }, + { + "text": "NOTE: We assume most supervisor-mode environments with demand-paging will require precise vector traps.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Exception Handling > Precise vector traps", + "line_range": [ + 4940, + 4941 + ] + }, + { + "text": "Precise vector traps require that:", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Exception Handling > Precise vector traps", + "line_range": [ + 4943, + 4943 + ] + }, + { + "text": ". all instructions older than the trapping vector instruction have committed their results . no instructions newer than the trapping vector instruction have altered architectural state . any operations within the trapping vector instruction affecting result elements preceding the index in the `vstart` CSR have committed their results . no operations within the trapping vector instruction affecting elements at or following the `vstart` CSR have altered architectural state except if restarting and completing the affected vector instruction will nevertheless produce the correct final state.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Exception Handling > Precise vector traps", + "line_range": [ + 4945, + 4948 + ] + }, + { + "text": "We relax the last requirement to allow elements following `vstart` to have been updated at the time the trap is reported, provided that re-executing the instruction from the given `vstart` will correctly overwrite those elements.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Exception Handling > Precise vector traps", + "line_range": [ + 4950, + 4953 + ] + }, + { + "text": "In idempotent memory regions, vector store instructions may have updated elements in memory past the element causing a synchronous trap.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Exception Handling > Precise vector traps", + "line_range": [ + 4955, + 4959 + ] + }, + { + "text": "Non-idempotent memory regions must not have been updated for indices equal to or greater than the element that caused a synchronous trap during a vector store instruction.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Exception Handling > Precise vector traps", + "line_range": [ + 4955, + 4959 + ] + }, + { + "text": "Except where noted above, vector instructions are allowed to overwrite their inputs, and so in most cases, the vector instruction restart must be from the `vstart` element index.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Exception Handling > Precise vector traps", + "line_range": [ + 4961, + 4966 + ] + }, + { + "text": "However, there are a number of cases where this overwrite is prohibited to enable execution of the vector instructions to be idempotent and hence restartable from an earlier index location.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Exception Handling > Precise vector traps", + "line_range": [ + 4961, + 4966 + ] + }, + { + "text": "Implementations must ensure forward progress can be eventually guaranteed for the element or segment reported by `vstart`.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Exception Handling > Precise vector traps", + "line_range": [ + 4968, + 4969 + ] + }, + { + "text": "Imprecise vector traps are traps that are not precise.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Exception Handling > Imprecise vector traps", + "line_range": [ + 4973, + 4978 + ] + }, + { + "text": "In particular, instructions newer than `*epc` may have committed results, and instructions older than `*epc` may have not completed execution.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Exception Handling > Imprecise vector traps", + "line_range": [ + 4973, + 4978 + ] + }, + { + "text": "Imprecise traps are primarily intended to be used in situations where reporting an error and terminating execution is the appropriate response.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Exception Handling > Imprecise vector traps", + "line_range": [ + 4973, + 4978 + ] + }, + { + "text": "NOTE: A profile might specify that interrupts are precise while other traps are imprecise.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Exception Handling > Imprecise vector traps", + "line_range": [ + 4980, + 4983 + ] + }, + { + "text": "We assume many embedded implementations will generate only imprecise traps for vector instructions on fatal errors, as they will not require resumable traps.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Exception Handling > Imprecise vector traps", + "line_range": [ + 4980, + 4983 + ] + }, + { + "text": "Imprecise traps shall report the faulting element in `vstart` for traps caused by synchronous vector exceptions.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Exception Handling > Imprecise vector traps", + "line_range": [ + 4985, + 4986 + ] + }, + { + "text": "There is no support for imprecise traps in the current standard extensions.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Exception Handling > Imprecise vector traps", + "line_range": [ + 4988, + 4988 + ] + }, + { + "text": "Some profiles may choose to provide a privileged mode bit to select between precise and imprecise vector traps.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Exception Handling > Selectable precise/imprecise traps", + "line_range": [ + 4992, + 4997 + ] + }, + { + "text": "Imprecise mode would run at high-performance but possibly make it difficult to discern error causes, while precise mode would run more slowly, but support debugging of errors albeit with a possibility of not experiencing the same errors as in imprecise mode.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Exception Handling > Selectable precise/imprecise traps", + "line_range": [ + 4992, + 4997 + ] + }, + { + "text": "This mechanism is not defined in the current standard extensions.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Exception Handling > Selectable precise/imprecise traps", + "line_range": [ + 4999, + 4999 + ] + }, + { + "text": "Another trap mode can support swappable state in the vector unit, where on a trap, special instructions can save and restore the vector unit microarchitectural state, to allow execution to continue correctly around imprecise traps.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Exception Handling > Swappable traps", + "line_range": [ + 5003, + 5006 + ] + }, + { + "text": "This mechanism is not defined in the current standard extensions.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Exception Handling > Swappable traps", + "line_range": [ + 5008, + 5008 + ] + }, + { + "text": "NOTE: A future extension might define a standard way of saving and restoring opaque microarchitectural state from a vector unit implementation to support context switching with imprecise traps.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Exception Handling > Swappable traps", + "line_range": [ + 5010, + 5012 + ] + }, + { + "text": "This section describes the standard vector extensions. A set of smaller extensions intended for embedded use are named with a \"Zve\" prefix, while a larger vector extension designed for application processors is named as a single-letter V extension. A set of vector length extension names with prefix \"Zvl\" are also provided.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions", + "line_range": [ + 5017, + 5022 + ] + }, + { + "text": "The initial vector extensions are designed to act as a base for additional vector extensions in various domains, including cryptography and machine learning.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions", + "line_range": [ + 5024, + 5026 + ] + }, + { + "text": "All standard vector extensions have a minimum required VLEN as described below. A set of vector length extensions are provided to increase the minimum vector length of a vector extension.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > Zvl*: Minimum Vector Length Extensions", + "line_range": [ + 5030, + 5032 + ] + }, + { + "text": "NOTE: The vector length extensions can be used to either specify additional software or architecture profile requirements, or to advertise hardware capabilities.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > Zvl*: Minimum Vector Length Extensions", + "line_range": [ + 5034, + 5036 + ] + }, + { + "text": ".Vector length extensions [cols=\"1,1\"] | | Extension | Minimum VLEN", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > Zvl*: Minimum Vector Length Extensions", + "line_range": [ + 5038, + 5042 + ] + }, + { + "text": "| Zvl32b | 32 | Zvl64b | 64 | Zvl128b | 128 | Zvl256b | 256 | Zvl512b | 512 | Zvl1024b | 1024 |", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > Zvl*: Minimum Vector Length Extensions", + "line_range": [ + 5044, + 5050 + ] + }, + { + "text": "NOTE: Longer vector length extensions should follow the same pattern.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > Zvl*: Minimum Vector Length Extensions", + "line_range": [ + 5052, + 5052 + ] + }, + { + "text": "NOTE: Every vector length extension effectively includes all shorter vector length extensions.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > Zvl*: Minimum Vector Length Extensions", + "line_range": [ + 5054, + 5055 + ] + }, + { + "text": "NOTE: Explicit use of the Zvl32b extension string is not required for any standard vector extension as they all effectively mandate at least this minimum, but the string can be useful when stating hardware capabilities.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > Zvl*: Minimum Vector Length Extensions", + "line_range": [ + 5057, + 5060 + ] + }, + { + "text": "The following five standard extensions are defined to provide varying degrees of vector support and are intended for use with embedded processors.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > Zve*: Vector Extensions for Embedded Processors", + "line_range": [ + 5064, + 5069 + ] + }, + { + "text": "Any of these extensions can be added to base ISAs with XLEN=32 or XLEN=64.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > Zve*: Vector Extensions for Embedded Processors", + "line_range": [ + 5064, + 5069 + ] + }, + { + "text": "The table lists the minimum VLEN and supported EEWs for each extension as well as what floating-point types are supported.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > Zve*: Vector Extensions for Embedded Processors", + "line_range": [ + 5064, + 5069 + ] + }, + { + "text": ".Embedded vector extensions [cols=\"1,1,2,1,1\"] | | Extension | Minimum VLEN | Supported EEW | FP32 | FP64", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > Zve*: Vector Extensions for Embedded Processors", + "line_range": [ + 5071, + 5075 + ] + }, + { + "text": "| Zve32x | 32 | 8, 16, 32 | N | N | Zve32f | 32 | 8, 16, 32 | Y | N | Zve64x | 64 | 8, 16, 32, 64 | N | N | Zve64f | 64 | 8, 16, 32, 64 | Y | N | Zve64d | 64 | 8, 16, 32, 64 | Y | Y |", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > Zve*: Vector Extensions for Embedded Processors", + "line_range": [ + 5077, + 5082 + ] + }, + { + "text": "The Zve32f and Zve64x extensions depend on the Zve32x extension.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > Zve*: Vector Extensions for Embedded Processors", + "line_range": [ + 5084, + 5086 + ] + }, + { + "text": "The Zve64f extension depends on the Zve32f and Zve64x extensions.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > Zve*: Vector Extensions for Embedded Processors", + "line_range": [ + 5084, + 5086 + ] + }, + { + "text": "The Zve64d extension depends on the Zve64f extension.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > Zve*: Vector Extensions for Embedded Processors", + "line_range": [ + 5084, + 5086 + ] + }, + { + "text": "All Zve* extensions have precise traps.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > Zve*: Vector Extensions for Embedded Processors", + "line_range": [ + 5088, + 5088 + ] + }, + { + "text": "NOTE: There is currently no standard support for handling imprecise traps, so standard extensions have to provide precise traps.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > Zve*: Vector Extensions for Embedded Processors", + "line_range": [ + 5090, + 5091 + ] + }, + { + "text": "All Zve* extensions provide support for EEW of 8, 16, and 32, and Zve64* extensions also support EEW of 64.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > Zve*: Vector Extensions for Embedded Processors", + "line_range": [ + 5093, + 5094 + ] + }, + { + "text": "All Zve* extensions support the vector configuration instructions ().", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > Zve*: Vector Extensions for Embedded Processors", + "line_range": [ + 5096, + 5097 + ] + }, + { + "text": "All Zve* extensions support all vector load and store instructions (), except Zve64* extensions do not support EEW=64 for index values when XLEN=32.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > Zve*: Vector Extensions for Embedded Processors", + "line_range": [ + 5099, + 5101 + ] + }, + { + "text": "All Zve* extensions support all vector integer instructions (), except that the `vmulh` integer multiply variants that return the high half of the product (`vmulh.vv`, `vmulh.vx`, `vmulhu.vv`, `vmulhu.vx`, `vmulhsu.vv`, `vmulhsu.vx`) are not included for EEW=64 in Zve64*.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > Zve*: Vector Extensions for Embedded Processors", + "line_range": [ + 5103, + 5107 + ] + }, + { + "text": "NOTE: Producing the high-word of a product can take substantial additional gates for large EEW.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > Zve*: Vector Extensions for Embedded Processors", + "line_range": [ + 5109, + 5110 + ] + }, + { + "text": "All Zve* extensions support all vector fixed-point arithmetic instructions (), except that `vsmul.vv` and `vsmul.vx` are not included in EEW=64 in Zve64*.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > Zve*: Vector Extensions for Embedded Processors", + "line_range": [ + 5112, + 5114 + ] + }, + { + "text": "NOTE: As with `vmulh`, `vsmul` requires a large amount of additional logic, and 64-bit fixed-point multiplies are relatively rare.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > Zve*: Vector Extensions for Embedded Processors", + "line_range": [ + 5116, + 5117 + ] + }, + { + "text": "All Zve* extensions support all vector integer single-width and widening reduction operations (, ).", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > Zve*: Vector Extensions for Embedded Processors", + "line_range": [ + 5119, + 5121 + ] + }, + { + "text": "All Zve* extensions support all vector mask instructions ().", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > Zve*: Vector Extensions for Embedded Processors", + "line_range": [ + 5123, + 5124 + ] + }, + { + "text": "All Zve* extensions support all vector permutation instructions (), except that Zve32x and Zve64x do not include those with floating-point operands, and Zve64f does not include those with EEW=64 floating-point operands.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > Zve*: Vector Extensions for Embedded Processors", + "line_range": [ + 5126, + 5129 + ] + }, + { + "text": "The Zve32x extension depends on the Zicsr extension.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > Zve*: Vector Extensions for Embedded Processors", + "line_range": [ + 5131, + 5136 + ] + }, + { + "text": "The Zve32f and Zve64f extensions depend upon the F extension, and implement all vector floating-point instructions () for floating-point operands with EEW=32.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > Zve*: Vector Extensions for Embedded Processors", + "line_range": [ + 5131, + 5136 + ] + }, + { + "text": "Vector single-width floating-point reduction operations () for EEW=32 are supported.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > Zve*: Vector Extensions for Embedded Processors", + "line_range": [ + 5131, + 5136 + ] + }, + { + "text": "The Zve64d extension depends upon the D extension, and implements all vector floating-point instructions () for floating-point operands with EEW=32 or EEW=64 (including widening instructions and conversions between FP32 and FP64).", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > Zve*: Vector Extensions for Embedded Processors", + "line_range": [ + 5138, + 5145 + ] + }, + { + "text": "Vector single-width floating-point reductions () for EEW=32 and EEW=64 are supported as well as widening reductions from FP32 to FP64.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > Zve*: Vector Extensions for Embedded Processors", + "line_range": [ + 5138, + 5145 + ] + }, + { + "text": "The single-letter V extension is intended for use in application processor profiles.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > V: Vector Extension for Application Processors", + "line_range": [ + 5149, + 5150 + ] + }, + { + "text": "The `misa.v` bit is set for implementations providing `misa` and supporting V.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > V: Vector Extension for Application Processors", + "line_range": [ + 5152, + 5153 + ] + }, + { + "text": "The V vector extension has precise traps.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > V: Vector Extension for Application Processors", + "line_range": [ + 5155, + 5155 + ] + }, + { + "text": "The V vector extension depends upon the Zvl128b and Zve64d extensions.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > V: Vector Extension for Application Processors", + "line_range": [ + 5157, + 5157 + ] + }, + { + "text": "NOTE: The value of 128 was chosen as a compromise for application processors.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > V: Vector Extension for Application Processors", + "line_range": [ + 5159, + 5166 + ] + }, + { + "text": "Providing a larger VLEN allows strip-mining code to be elided in some cases for short vectors, but also increases the size of the minimum implementation.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > V: Vector Extension for Application Processors", + "line_range": [ + 5159, + 5166 + ] + }, + { + "text": "Note that larger LMUL can be used to avoid strip mining for longer known-size application vectors at the cost of having fewer available vector register groups.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > V: Vector Extension for Application Processors", + "line_range": [ + 5159, + 5166 + ] + }, + { + "text": "For example, an LMUL of 8 allows vectors of up to sixteen 64-bit elements to be processed without strip mining using four vector register groups.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > V: Vector Extension for Application Processors", + "line_range": [ + 5159, + 5166 + ] + }, + { + "text": "The V extension supports EEW of 8, 16, and 32, and 64.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > V: Vector Extension for Application Processors", + "line_range": [ + 5168, + 5168 + ] + }, + { + "text": "The V extension supports the vector configuration instructions ().", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > V: Vector Extension for Application Processors", + "line_range": [ + 5170, + 5171 + ] + }, + { + "text": "The V extension supports all vector load and store instructions (), except the V extension does not support EEW=64 for index values when XLEN=32.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > V: Vector Extension for Application Processors", + "line_range": [ + 5173, + 5175 + ] + }, + { + "text": "The V extension supports all vector integer instructions ().", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > V: Vector Extension for Application Processors", + "line_range": [ + 5177, + 5178 + ] + }, + { + "text": "The V extension supports all vector fixed-point arithmetic instructions ().", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > V: Vector Extension for Application Processors", + "line_range": [ + 5180, + 5181 + ] + }, + { + "text": "The V extension supports all vector integer single-width and widening reduction operations (, ).", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > V: Vector Extension for Application Processors", + "line_range": [ + 5183, + 5185 + ] + }, + { + "text": "The V extension supports all vector mask instructions ().", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > V: Vector Extension for Application Processors", + "line_range": [ + 5187, + 5188 + ] + }, + { + "text": "The V extension supports all vector permutation instructions ().", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > V: Vector Extension for Application Processors", + "line_range": [ + 5190, + 5191 + ] + }, + { + "text": "The V extension depends upon the F and D extensions, and implements all vector floating-point instructions () for floating-point operands with EEW=32 or EEW=64 (including widening instructions and conversions between FP32 and FP64).", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > V: Vector Extension for Application Processors", + "line_range": [ + 5193, + 5199 + ] + }, + { + "text": "Vector single-width floating-point reductions () for EEW=32 and EEW=64 are supported as well as widening reductions from FP32 to FP64.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > V: Vector Extension for Application Processors", + "line_range": [ + 5193, + 5199 + ] + }, + { + "text": "The Zvfhmin extension provides minimal support for vectors of IEEE 754-2008 binary16 values, adding conversions to and from binary32.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > Zvfhmin: Vector Extension for Minimal Half-Precision Floating-Point", + "line_range": [ + 5204, + 5209 + ] + }, + { + "text": "When the Zvfhmin extension is implemented, the `vfwcvt.f.f.v` and `vfncvt.f.f.w` instructions become defined when SEW=16.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > Zvfhmin: Vector Extension for Minimal Half-Precision Floating-Point", + "line_range": [ + 5204, + 5209 + ] + }, + { + "text": "The EEW=16 floating-point operands of these instructions use the binary16 format.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > Zvfhmin: Vector Extension for Minimal Half-Precision Floating-Point", + "line_range": [ + 5204, + 5209 + ] + }, + { + "text": "The Zvfhmin extension depends on the Zve32f extension.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > Zvfhmin: Vector Extension for Minimal Half-Precision Floating-Point", + "line_range": [ + 5211, + 5211 + ] + }, + { + "text": "The Zvfh extension provides support for vectors of IEEE 754-2008 binary16 values.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > Zvfh: Vector Extension for Half-Precision Floating-Point", + "line_range": [ + 5216, + 5224 + ] + }, + { + "text": "When the Zvfh extension is implemented, all instructions in , , , , , and become defined when SEW=16.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > Zvfh: Vector Extension for Half-Precision Floating-Point", + "line_range": [ + 5216, + 5224 + ] + }, + { + "text": "The EEW=16 floating-point operands of these instructions use the binary16 format.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > Zvfh: Vector Extension for Half-Precision Floating-Point", + "line_range": [ + 5216, + 5224 + ] + }, + { + "text": "Additionally, conversions between 8-bit integers and binary16 values are provided.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > Zvfh: Vector Extension for Half-Precision Floating-Point", + "line_range": [ + 5226, + 5229 + ] + }, + { + "text": "The floating-point-to-integer narrowing conversions (`vfncvt[.rtz].x[u].f.w`) and integer-to-floating-point widening conversions (`vfwcvt.f.x[u].v`) become defined when SEW=8.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > Zvfh: Vector Extension for Half-Precision Floating-Point", + "line_range": [ + 5226, + 5229 + ] + }, + { + "text": "The Zvfh extension depends on the Zve32f and Zfhmin extensions.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > Zvfh: Vector Extension for Half-Precision Floating-Point", + "line_range": [ + 5231, + 5231 + ] + }, + { + "text": "NOTE: Requiring basic scalar half-precision support makes Zvfh's vector-scalar instructions substantially more useful.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > Zvfh: Vector Extension for Half-Precision Floating-Point", + "line_range": [ + 5233, + 5237 + ] + }, + { + "text": "We considered requiring more complete scalar half-precision support, but we reasoned that, for many half-precision vector workloads, performing the scalar computation in single-precision will suffice.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Standard Vector Extensions > Zvfh: Vector Extension for Half-Precision Floating-Point", + "line_range": [ + 5233, + 5237 + ] + }, + { + "text": "Some vector instructions treat operands as a vector of one or more element groups, where each element group is a fixed number of elements.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Element Groups", + "line_range": [ + 5242, + 5248 + ] + }, + { + "text": "For example, complex numbers can be viewed as a two-element group (one real element and one imaginary element).", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Element Groups", + "line_range": [ + 5242, + 5248 + ] + }, + { + "text": "As another example, the SHA-256 cryptographic instructions in the Zvknha extension operate on 128-bit values represented as a 4-element group of 32-bit elements.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Element Groups", + "line_range": [ + 5242, + 5248 + ] + }, + { + "text": "This section describes recommendations and terminology for generic instruction set design for vector instructions that operate on element groups.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Element Groups", + "line_range": [ + 5250, + 5252 + ] + }, + { + "text": "The element group size (EGS) is the number of elements in one group, and must be a power-of-two (POT).", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Element Groups > Element Group Size", + "line_range": [ + 5256, + 5257 + ] + }, + { + "text": "NOTE: Support for non-POT EGS was considered but causes many practical complications and so has been dropped.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Element Groups > Element Group Size", + "line_range": [ + 5259, + 5266 + ] + }, + { + "text": "Error checking for `vl` is a little more difficult.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Element Groups > Element Group Size", + "line_range": [ + 5259, + 5266 + ] + }, + { + "text": "For LMUL>1, non-POT EGSs will result in groups straddling the individual vector registers in a vector register group.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Element Groups > Element Group Size", + "line_range": [ + 5259, + 5266 + ] + }, + { + "text": "Non-POT EGS can also cause large increases in the lowest-common-multiple of element group sizes, which adds constraints to `vl` setting in order to avoid splitting an element group across strip-mine iterations in vector-length-agnostic code.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Element Groups > Element Group Size", + "line_range": [ + 5259, + 5266 + ] + }, + { + "text": "The element group size is statically encoded in the instruction, often implicitly as part of the opcode.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Element Groups > Element Group Size", + "line_range": [ + 5268, + 5269 + ] + }, + { + "text": "Vector instructions with EGS > VLMAX are reserved.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Element Groups > Element Group Size", + "line_range": [ + 5271, + 5271 + ] + }, + { + "text": "NOTE: The vector instructions in the base V vector ISA can be viewed as all having an element group size of 1 for all operands statically encoded in the instruction.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Element Groups > Element Group Size", + "line_range": [ + 5273, + 5275 + ] + }, + { + "text": "NOTE: Many operations only make sense with a certain number of elements per group (e.g., complex operations require a element group size of 2 and SHA-256 requires an element group size of 4).", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Element Groups > Element Group Size", + "line_range": [ + 5277, + 5279 + ] + }, + { + "text": "Each source and destination operand to a vector instruction might be defined as either a single element group or a vector of element groups.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Element Groups > Setting `vl`", + "line_range": [ + 5283, + 5287 + ] + }, + { + "text": "When an operand is a vector of element groups, the `vl` setting must correspond to an integer multiple of the element group size, with other values of `vl` reserved.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Element Groups > Setting `vl`", + "line_range": [ + 5283, + 5287 + ] + }, + { + "text": "NOTE: For example, a SHA-256 instruction would require that `vl` is a multiple of 4.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Element Groups > Setting `vl`", + "line_range": [ + 5289, + 5290 + ] + }, + { + "text": "When element group instructions are present, an additional constraint is placed on the setting of `vl` based on an AVL value (augmenting ). EGSMAX is the largest EGS supported by the implementation.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Element Groups > Setting `vl`", + "line_range": [ + 5292, + 5297 + ] + }, + { + "text": "When AVL > VLMAX, the value of `vl` must be set to either VLMAX or a positive integer multiple of EGSMAX.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Element Groups > Setting `vl`", + "line_range": [ + 5292, + 5297 + ] + }, + { + "text": "NOTE: As the base vector extension only has element group size of 1, this constraint is backwards-compatible.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Element Groups > Setting `vl`", + "line_range": [ + 5299, + 5300 + ] + }, + { + "text": "NOTE: This constraint prevents element groups being broken across strip-mining iterations in vector-length-agnostic code when a VLMAX-size vector would otherwise be able to accommodate a whole number of element groups.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Element Groups > Setting `vl`", + "line_range": [ + 5302, + 5305 + ] + }, + { + "text": "If EEW is encoded statically in the instruction, or if an instruction has multiple operands containing vectors of element groups with different EEW, an appropriate SEW must be chosen for `vsetvl` instructions.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Element Groups > Setting `vl`", + "line_range": [ + 5307, + 5310 + ] + }, + { + "text": "NOTE: Additional constraints may be required for some element group instructions to ensure legal length values for all operands.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Element Groups > Setting `vl`", + "line_range": [ + 5312, + 5313 + ] + }, + { + "text": "The `vtype` SEW can be used to indicate or calculate the effective element size (EEW) of one or more operands of an element group instruction.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Element Groups > Determining EEW", + "line_range": [ + 5317, + 5321 + ] + }, + { + "text": "Where the operand is an element group, SEW and EEW refer to the number of bits in each individual element within a group not the number of bits in the group as a whole.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Element Groups > Determining EEW", + "line_range": [ + 5317, + 5321 + ] + }, + { + "text": "Alternatively, the opcode might encode EEW of all operands statically and ignore the value of SEW when the operation only makes sense for a single size on each operand.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Element Groups > Determining EEW", + "line_range": [ + 5323, + 5325 + ] + }, + { + "text": "NOTE: Many operations are only defined for one EEW, e.g., SHA-256 requires EEW=32.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Element Groups > Determining EEW", + "line_range": [ + 5327, + 5333 + ] + }, + { + "text": "Encoding EEWs statically in the instruction removes a dynamic dependency on the SEW value and the need to check for errors in SEW values.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Element Groups > Determining EEW", + "line_range": [ + 5327, + 5333 + ] + }, + { + "text": "However, ignoring SEW also prevents reuse of the static opcode with a different dynamic SEW, and in many cases, the SEW setting will be needed for regular vector instructions used to process the individual elements in the vector.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Element Groups > Determining EEW", + "line_range": [ + 5327, + 5333 + ] + }, + { + "text": "The `vtype` LMUL setting can be used to indicate or calculate the effective length multiplier (EMUL) for one or more operands.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Element Groups > Determining EMUL", + "line_range": [ + 5337, + 5344 + ] + }, + { + "text": "Element group instructions tend to exhibit a much wider range of relationships between various operand EEW/EMUL values.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Element Groups > Determining EMUL", + "line_range": [ + 5337, + 5344 + ] + }, + { + "text": "For example, an instruction might take a vector of length N of 4-element groups with EEW=8b and reduce each group to produce a vector length N of 1-element groups with EEW=32b.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Element Groups > Determining EMUL", + "line_range": [ + 5337, + 5344 + ] + }, + { + "text": "In this case, the input and output EMUL values are equal even though the EEW settings differ by a factor of 4.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Element Groups > Determining EMUL", + "line_range": [ + 5337, + 5344 + ] + }, + { + "text": "Each source and destination operand to a vector instruction may have a different element group size, different EMUL, and/or different EEW.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Element Groups > Determining EMUL", + "line_range": [ + 5346, + 5347 + ] + }, + { + "text": "The element group width (EGW) is the number of bits in the element group as a whole.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Element Groups > Element Group Width", + "line_range": [ + 5351, + 5356 + ] + }, + { + "text": "For example, the SHA-256 instructions in the Zvknha extension operate on an EGW of 128, with EGS=4 and EEW=32.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Element Groups > Element Group Width", + "line_range": [ + 5351, + 5356 + ] + }, + { + "text": "It is possible to use LMUL to concatenate multiple vector registers together to support larger EGW>VLEN.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Element Groups > Element Group Width", + "line_range": [ + 5351, + 5356 + ] + }, + { + "text": "If software using large-EGW instructions need be portable across a range of implementations, some of which may have VLEN1, then software can only use a subset of the architectural registers.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Element Groups > Element Group Width", + "line_range": [ + 5358, + 5362 + ] + }, + { + "text": "Profiles can set minimum VLEN requirements to inform authors of such software.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Element Groups > Element Group Width", + "line_range": [ + 5358, + 5362 + ] + }, + { + "text": "NOTE: Element group operations by their nature will gather data from across a wider portion of a vector datapath than regular vector instructions.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Element Groups > Element Group Width", + "line_range": [ + 5364, + 5369 + ] + }, + { + "text": "Some element group instructions might allow temporal execution of individual element operations in a larger group, while others will require all EGW bits of a group to be presented to a functional unit at the same time.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Element Groups > Element Group Width", + "line_range": [ + 5364, + 5369 + ] + }, + { + "text": "No ratified extensions include masked element-group instructions.", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Element Groups > Masking", + "line_range": [ + 5373, + 5377 + ] + }, + { + "text": "Future extensions might extend the element-group scheme to support element-level masking, or might define the concept of a mask element group (which might, e.g., update the destination element group if any mask bit in the mask element group is set).", + "section": "Preamble > \"V\" Extension for Vector Operations, Version 1.0 > Vector Element Groups > Masking", + "line_range": [ + 5373, + 5377 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__vector-crypto.json b/tools/llm-extraction/data/output/raw_chunks/src__vector-crypto.json new file mode 100644 index 0000000000..f6b218ce9c --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__vector-crypto.json @@ -0,0 +1,5366 @@ +{ + "source_file": "src/vector-crypto.adoc", + "total": 670, + "sentences": [ + { + "text": "This chapter describes the Vector Cryptography extensions to the RISC-V Instruction Set Architecture.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0", + "line_range": [ + 2, + 3 + ] + }, + { + "text": "This chapter describes the RISC-V vector cryptography extensions.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction", + "line_range": [ + 8, + 14 + ] + }, + { + "text": "All instructions described here are based on the Vector registers.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction", + "line_range": [ + 8, + 14 + ] + }, + { + "text": "The instructions are designed to be highly performant, with large application and server-class cores being the main target. describes cryptographic instructions for smaller cores which do not implement the vector extension.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction", + "line_range": [ + 8, + 14 + ] + }, + { + "text": "Cryptography is a specialized subject, requiring people with many different backgrounds to cooperate in its secure and efficient implementation.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Intended Audience", + "line_range": [ + 19, + 24 + ] + }, + { + "text": "Where possible, we have written this specification to be understandable by all, though we recognize that the motivations and references to algorithms or other specifications and standards may be unfamiliar to those who are not domain experts.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Intended Audience", + "line_range": [ + 19, + 24 + ] + }, + { + "text": "This specification anticipates being read and acted on by various people with different backgrounds.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Intended Audience", + "line_range": [ + 26, + 33 + ] + }, + { + "text": "We have tried to capture these backgrounds here, with a brief explanation of what we expect them to know, and how it relates to the specification.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Intended Audience", + "line_range": [ + 26, + 33 + ] + }, + { + "text": "We hope this aids people's understanding of which aspects of the specification are particularly relevant to them, and which they may (safely!) ignore or pass to a colleague.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Intended Audience", + "line_range": [ + 26, + 33 + ] + }, + { + "text": "Cryptographers and cryptographic software developers:: These are the people we expect to write code using the instructions in this specification.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Intended Audience", + "line_range": [ + 35, + 40 + ] + }, + { + "text": "They should understand the motivations for the instructions we include, and be familiar with most of the algorithms and outside standards to which we refer.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Intended Audience", + "line_range": [ + 35, + 40 + ] + }, + { + "text": "Computer architects:: We do not expect architects to have a cryptography background.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Intended Audience", + "line_range": [ + 42, + 47 + ] + }, + { + "text": "We nonetheless expect architects to be able to examine our instructions for implementation issues, understand how the instructions will be used in context, and advise on how best to fit the functionality the cryptographers want.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Intended Audience", + "line_range": [ + 42, + 47 + ] + }, + { + "text": "Digital design engineers & micro-architects:: These are the people who will implement the specification inside a core.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Intended Audience", + "line_range": [ + 49, + 56 + ] + }, + { + "text": "Again, no cryptography expertise is assumed, but we expect them to interpret the specification and anticipate any hardware implementation issues, e.g., where high-frequency design considerations apply, or where latency/area tradeoffs exist etc.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Intended Audience", + "line_range": [ + 49, + 56 + ] + }, + { + "text": "In particular, they should be aware of the literature around efficiently implementing AES and SM4 SBoxes in hardware.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Intended Audience", + "line_range": [ + 49, + 56 + ] + }, + { + "text": "Verification engineers:: These people are responsible for ensuring the correct implementation of the extensions in hardware.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Intended Audience", + "line_range": [ + 58, + 63 + ] + }, + { + "text": "No cryptography background is assumed.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Intended Audience", + "line_range": [ + 58, + 63 + ] + }, + { + "text": "We expect them to identify interesting test cases from the specification.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Intended Audience", + "line_range": [ + 58, + 63 + ] + }, + { + "text": "An understanding of their real-world usage will help with this.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Intended Audience", + "line_range": [ + 58, + 63 + ] + }, + { + "text": "These are by no means the only people concerned with the specification, but they are the ones we considered most while writing it.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Intended Audience", + "line_range": [ + 65, + 66 + ] + }, + { + "text": "RISC-V maintains a link:https://github.com/riscv/sail-riscv[formal model] of the ISA specification, implemented in the Sail ISA specification language cite:[sail].", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Sail Specifications", + "line_range": [ + 71, + 77 + ] + }, + { + "text": "Note that Sail refers to the specification language itself, and that there is a model of RISC-V, written using Sail.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Sail Specifications", + "line_range": [ + 71, + 77 + ] + }, + { + "text": "It was our intention to include actual Sail code in this specification.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Sail Specifications", + "line_range": [ + 79, + 87 + ] + }, + { + "text": "However, the Vector Crypto Sail model needs the Vector Sail model as a basis on which to build.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Sail Specifications", + "line_range": [ + 79, + 87 + ] + }, + { + "text": "This Vector Cryptography extensions specification was completed before there was an approved RISC-V Vector Sail Model.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Sail Specifications", + "line_range": [ + 79, + 87 + ] + }, + { + "text": "Therefore, we don't have any Sail code to include in the instruction descriptions.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Sail Specifications", + "line_range": [ + 79, + 87 + ] + }, + { + "text": "Instead we have included Sail-like pseudocode.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Sail Specifications", + "line_range": [ + 79, + 87 + ] + }, + { + "text": "While we have endeavored to adhere to Sail syntax, we have taken some liberties for the sake of simplicity where we believe that that our intent is clear to the reader.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Sail Specifications", + "line_range": [ + 79, + 87 + ] + }, + { + "text": "For the sake of brevity, our pseudocode does not include the handling of masks or tail elements.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Sail Specifications", + "line_range": [ + 89, + 93 + ] + }, + { + "text": "We follow the undisturbed and agnostic policies for masks and tails as described in the *RISC-V \"V\" Vector Extension* specification.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Sail Specifications", + "line_range": [ + 89, + 93 + ] + }, + { + "text": "Furthermore, the code does not explicitly handle overlap and SEW constraints; these are, however, explicitly stated in the text.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Sail Specifications", + "line_range": [ + 89, + 93 + ] + }, + { + "text": "In many cases the pseudocode includes calls to supporting functions which are too verbose to include directly in the specification.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Sail Specifications", + "line_range": [ + 95, + 99 + ] + }, + { + "text": "This supporting code is listed in .", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Sail Specifications", + "line_range": [ + 95, + 99 + ] + }, + { + "text": "The link:https://alasdair.github.io/manual.html[Sail Manual] is recommended reading in order to best understand the code snippets.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Sail Specifications", + "line_range": [ + 101, + 106 + ] + }, + { + "text": "Also, link:https://github.com/billmcspadden-riscv/sail/blob/cookbookbr/cookbook/doc/TheSailCookbookComplete.pdf[The Sail Programming Language: A Sail Cookbook] is a good reference.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Sail Specifications", + "line_range": [ + 101, + 106 + ] + }, + { + "text": "For the latest RISC-V Sail model, refer to the formal model GitHub link:https://github.com/riscv/sail-riscv[repository].", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Sail Specifications", + "line_range": [ + 108, + 110 + ] + }, + { + "text": "In creating this extension, we tried to adhere to the following policies:", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Policies", + "line_range": [ + 116, + 117 + ] + }, + { + "text": "Where there is a choice between: 1) supporting diverse implementation strategies for an algorithm or 2) supporting a single implementation style which is more performant / less expensive; the vector crypto extensions will pick the more constrained but performant option.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Policies", + "line_range": [ + 119, + 129 + ] + }, + { + "text": "This fits a common pattern in other parts of the RISC-V specifications, where recommended (but not required) instruction sequences for performing particular tasks are given as an example, such that both hardware and software implementers can optimize for only a single use-case.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Policies", + "line_range": [ + 119, + 129 + ] + }, + { + "text": "The extensions will be designed to support existing standardized cryptographic constructs well.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Policies", + "line_range": [ + 131, + 138 + ] + }, + { + "text": "It will not try to support proposed standards, or cryptographic constructs which exist only in academia.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Policies", + "line_range": [ + 131, + 138 + ] + }, + { + "text": "Cryptographic standards which are settled upon concurrently with or after the RISC-V vector cryptographic extensions standardization will be dealt with by future RISC-V vector cryptographic standard extensions.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Policies", + "line_range": [ + 131, + 138 + ] + }, + { + "text": "Historically, there has been some discussion cite:[LSYRR:04] on how newly supported operations in general-purpose computing might enable new bases for cryptographic algorithms.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Policies", + "line_range": [ + 140, + 146 + ] + }, + { + "text": "The standard will not try to anticipate new useful low-level operations which may be useful as building blocks for future cryptographic constructs.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Policies", + "line_range": [ + 140, + 146 + ] + }, + { + "text": "Regarding side-channel countermeasures: Where relevant, proposed instructions must aim to remove the possibility of any timing side-channels.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Policies", + "line_range": [ + 148, + 152 + ] + }, + { + "text": "All instructions shall be implemented with data-independent timing.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Policies", + "line_range": [ + 148, + 152 + ] + }, + { + "text": "That is, the latency of the execution of these instructions shall not vary with different input values.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Policies", + "line_range": [ + 148, + 152 + ] + }, + { + "text": "Many vector crypto instructions operate on operands that are wider than elements (which are currently limited to 64 bits wide).", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Element Groups", + "line_range": [ + 157, + 162 + ] + }, + { + "text": "Typically, these operands are 128- and 256-bits wide.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Element Groups", + "line_range": [ + 157, + 162 + ] + }, + { + "text": "In many cases, these operands are comprised of smaller operands that are combined (for example, each SHA-2 operand is comprised of 4 words).", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Element Groups", + "line_range": [ + 157, + 162 + ] + }, + { + "text": "However, in other cases these operands are a single value (for example, in the AES round instructions, each operand is 128-bit block or round key).", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Element Groups", + "line_range": [ + 157, + 162 + ] + }, + { + "text": "We treat these operands as a vector of one or more element groups", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Element Groups", + "line_range": [ + 164, + 164 + ] + }, + { + "text": "Each vector crypto instruction that operates on element groups explicitly specifies their three defining parameters: EGW, EGS, and EEW.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Element Groups", + "line_range": [ + 166, + 167 + ] + }, + { + "text": "| | Instruction Group | Extension | EGW | EEW | EGS", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Element Groups", + "line_range": [ + 169, + 176 + ] + }, + { + "text": "| AES | | 128 | 32 | 4 | SHA256 | | 128 | 32 | 4 | SHA512 | | 256 | 64 | 4 | GCM | | 128 | 32 | 4 | SM4 | | 128 | 32 | 4 | SM3 | | 256 | 32 | 8 |", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Element Groups", + "line_range": [ + 178, + 184 + ] + }, + { + "text": "For all of the vector crypto instructions in this specification, `EEW`=`SEW`.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Element Groups", + "line_range": [ + 186, + 187 + ] + }, + { + "text": "A *Vector Element Group* is a vector of one or more element groups. - A *Scalar Element Group* is a single element group.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Element Groups", + "line_range": [ + 189, + 190 + ] + }, + { + "text": "Element groups can be formed across registers in implementations where `VLEN`< `EGW` by using an `LMUL`>1.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Element Groups", + "line_range": [ + 192, + 193 + ] + }, + { + "text": "As with all vector instructions, the number of elements processed is specified by the vector length `vl`.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Element Groups", + "line_range": [ + 195, + 199 + ] + }, + { + "text": "The number of element groups operated upon is then `vl`/`EGS`.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Element Groups", + "line_range": [ + 195, + 199 + ] + }, + { + "text": "Likewise the starting element group is `vstart`/`EGS`.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Element Groups", + "line_range": [ + 195, + 199 + ] + }, + { + "text": "See for limitations on `vl` and `vstart` for vector crypto instructions.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Element Groups", + "line_range": [ + 195, + 199 + ] + }, + { + "text": "All standard vector instruction constraints specified by RVV 1.0 apply to Vector Crypto instructions.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Instruction Constraints", + "line_range": [ + 209, + 210 + ] + }, + { + "text": "In addition to those constraints a few additional specific constraints are introduced.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Instruction Constraints", + "line_range": [ + 209, + 210 + ] + }, + { + "text": "The following is a quick reference for the various constraints of specific Vector Crypto instructions.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Instruction Constraints", + "line_range": [ + 212, + 212 + ] + }, + { + "text": "vl and vstart constraints:: Since `vl` and `vstart` refer to elements, Vector Crypto instructions that use elements groups (See ) require that these values are an integer multiple of the Element Group Size (`EGS`).", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Instruction Constraints", + "line_range": [ + 214, + 217 + ] + }, + { + "text": "Instructions that violate the `vl` or `vstart` requirements are reserved.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Instruction Constraints", + "line_range": [ + 219, + 219 + ] + }, + { + "text": "| vaes* | 4 | vsha2* | 4 | vg* | 4 | vsm3* | 8 | vsm4* | 4", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Instruction Constraints", + "line_range": [ + 227, + 231 + ] + }, + { + "text": "LMUL constraints:: For element-group instructions, `LMUL`*`VLEN` must always be at least as large as `EGW`, otherwise an illegal-instruction exception is raised, even if `vl`=0.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Instruction Constraints", + "line_range": [ + 235, + 237 + ] + }, + { + "text": "| | Instructions | SEW | EGW", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Instruction Constraints", + "line_range": [ + 239, + 244 + ] + }, + { + "text": "| vaes* | 32 | 128 | vsha2* | 32 | 128 | vsha2* | 64 | 256 | vg* | 32 | 128 | vsm3* | 32 | 256 | vsm4* | 32 | 128", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Instruction Constraints", + "line_range": [ + 246, + 251 + ] + }, + { + "text": "SEW constraints:: Some Vector Crypto instructions are only defined for a specific `SEW`.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Instruction Constraints", + "line_range": [ + 255, + 257 + ] + }, + { + "text": "In such a case all other `SEW` values are reserved.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Instruction Constraints", + "line_range": [ + 255, + 257 + ] + }, + { + "text": "| | Instructions | Required SEW", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Instruction Constraints", + "line_range": [ + 259, + 263 + ] + }, + { + "text": "| vaes* | 32 | Zvknha: vsha2* | 32 | Zvknhb: vsha2* | 32 or 64 | vclmul[h] | 64 | vg* | 32 | vsm3* | 32 | vsm4* | 32", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Instruction Constraints", + "line_range": [ + 265, + 271 + ] + }, + { + "text": "Vector/Scalar constraints:: This specification defines new vector/scalar (.vs) instructions that uses *Scalar Element Groups*.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Instruction Constraints", + "line_range": [ + 275, + 276 + ] + }, + { + "text": "The *Scalar Element Group* operand has `EMUL = ceil(EGW / VLEN)`.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Instruction Constraints", + "line_range": [ + 275, + 276 + ] + }, + { + "text": "In the case of the `.vs` instructions defined in this specification, `vs2` holds a 128-bit scalar element group.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Instruction Constraints", + "line_range": [ + 278, + 283 + ] + }, + { + "text": "For implementations with `VLEN` ≥ 128, `vs2` refers to a single register.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Instruction Constraints", + "line_range": [ + 278, + 283 + ] + }, + { + "text": "Thus, the `vd` register group must not overlap the `vs2` register.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Instruction Constraints", + "line_range": [ + 278, + 283 + ] + }, + { + "text": "However, in implementations where `VLEN` < 128, `vs2` refers to a register group comprised of the number of registers needed to hold the 128-bit scalar element group.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Instruction Constraints", + "line_range": [ + 278, + 283 + ] + }, + { + "text": "In this case, the `vd` register group must not overlap this `vs2` register group.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Instruction Constraints", + "line_range": [ + 278, + 283 + ] + }, + { + "text": "| | Instruction | Register | Cannot Overlap", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Instruction Constraints", + "line_range": [ + 285, + 290 + ] + }, + { + "text": "| vaes*.vs | vs2 | vd | vsm4r.vs | vs2 | vd | vsha2c[hl] | vs1, vs2 | vd | vsha2ms | vs1, vs2 | vd | vsm3me | vs2 | vd | vsm3c | vs2 | vd", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Instruction Constraints", + "line_range": [ + 292, + 297 + ] + }, + { + "text": "The RISC-V Vector Extension defines three encodings for Vector-Scalar operations which get their scalar operand from a GPR or FP register:", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Vector-Scalar Instructions", + "line_range": [ + 308, + 308 + ] + }, + { + "text": "OPIVX: Scalar GPR x register - OPFVF: Scalar FP f register - OPMVX: Scalar GPR x register", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Vector-Scalar Instructions", + "line_range": [ + 310, + 312 + ] + }, + { + "text": "However, the Vector Extensions include Vector Reduction Operations which can also be considered Vector-Scalar operations because a scalar operand is provided from element 0 of vector register `vs1`.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Vector-Scalar Instructions", + "line_range": [ + 314, + 317 + ] + }, + { + "text": "The vector operand is provided in vector register group `vs2`.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Vector-Scalar Instructions", + "line_range": [ + 314, + 317 + ] + }, + { + "text": "These reduction operations all use the `.vs` suffix in their mnemonics.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Vector-Scalar Instructions", + "line_range": [ + 314, + 317 + ] + }, + { + "text": "Additionally, the reduction operations all produce a scalar result in element 0 of the destination register, `vd`.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Vector-Scalar Instructions", + "line_range": [ + 314, + 317 + ] + }, + { + "text": "The Vector Crypto Extensions define Vector-Scalar instructions that are similar to these Vector Reduction Operations in that they get a scalar operand from a vector register.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Vector-Scalar Instructions", + "line_range": [ + 319, + 324 + ] + }, + { + "text": "However, they differ in that they get a scalar element group (see ) from `vs2` and they return vector results to `vd`, which is also a source vector operand.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Vector-Scalar Instructions", + "line_range": [ + 319, + 324 + ] + }, + { + "text": "These Vector-Scalar crypto instructions also use the `.vs` suffix in their mnemonics.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Vector-Scalar Instructions", + "line_range": [ + 319, + 324 + ] + }, + { + "text": "These instructions enable a single key, specified as a scalar element group in `vs2`, to be applied to each element group of register group `vd`.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Vector-Scalar Instructions", + "line_range": [ + 326, + 327 + ] + }, + { + "text": "The following contains some guidelines that enable the portability of vector-crypto-based code to implementations with different values for `VLEN`", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Software Portability", + "line_range": [ + 348, + 349 + ] + }, + { + "text": "Application Processors:: Application processors are expected to follow the V-extension and will therefore have `VLEN` {ge} 128.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Software Portability", + "line_range": [ + 351, + 352 + ] + }, + { + "text": "However, the SHA-512 and SM3 instructions have an `EGW`=256.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Software Portability", + "line_range": [ + 359, + 364 + ] + }, + { + "text": "Implementations with `VLEN` = 128, require that `LMUL` is doubled for these instructions in order to create 256-bit elements across a pair of registers.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Software Portability", + "line_range": [ + 359, + 364 + ] + }, + { + "text": "Code written with this doubling of `LMUL` will not affect the results returned by implementations with `VLEN` {ge} 256 because `vl` controls how many element groups are processed.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Software Portability", + "line_range": [ + 359, + 364 + ] + }, + { + "text": "Therefore, we recommend that libraries that implement SHA-512 and SM3 employ this doubling of `LMUL` to ensure that the software can run on all implementation with `VLEN` {ge} 128.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Software Portability", + "line_range": [ + 359, + 364 + ] + }, + { + "text": "While the doubling of `LMUL` for these instructions is safe for implementations with `VLEN` {ge} 256, it may be less optimal as it will result in unnecessary register pressure and might exact a performance penalty in some microarchitectures.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Software Portability", + "line_range": [ + 366, + 370 + ] + }, + { + "text": "Therefore, we suggest that in addition to providing portable code for SHA-512 and SM3, libraries should also include more optimal code for these instructions when `VLEN` {ge} 256. //", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Software Portability", + "line_range": [ + 366, + 370 + ] + }, + { + "text": "| | Algorithm | Instructions | VLEN | LMUL", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Software Portability", + "line_range": [ + 372, + 378 + ] + }, + { + "text": "| SHA-512 | vsha2* | 64 | vl/2 | SM3 | vsm3* | 32 | vl/4 |", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Software Portability", + "line_range": [ + 380, + 382 + ] + }, + { + "text": "Embedded processors will typically have implementations with `VLEN` < 128.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Software Portability", + "line_range": [ + 393, + 394 + ] + }, + { + "text": "This will require code to be written with larger `LMUL` values to enable the element groups to be formed.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Software Portability", + "line_range": [ + 393, + 394 + ] + }, + { + "text": "The `.vs` instructions require scalar element groups of `EGW`=128.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Software Portability", + "line_range": [ + 396, + 398 + ] + }, + { + "text": "On implementations with `VLEN` < 128, these scalar element groups will necessarily be formed across registers.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Software Portability", + "line_range": [ + 396, + 398 + ] + }, + { + "text": "This is different from most scalars in vector instructions that typically consume part of a single register.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Introduction > Software Portability", + "line_range": [ + 396, + 398 + ] + }, + { + "text": "The section introduces all of the extensions in the Vector Cryptography Instruction Set Extension Specification.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview", + "line_range": [ + 411, + 412 + ] + }, + { + "text": "The and Vector Crypto Extensions --and accordingly the composite extensions , , , and -- depend on Zve64x.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview", + "line_range": [ + 414, + 416 + ] + }, + { + "text": "All of the other Vector Crypto Extensions depend on `Zve32x`.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview", + "line_range": [ + 418, + 418 + ] + }, + { + "text": "`Zvknhb` implies `Zvknha`.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview", + "line_range": [ + 420, + 420 + ] + }, + { + "text": "If `Zve32x` is supported then `Zvkb` or `Zvbb` provide support for EEW of 8, 16, and 32.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview", + "line_range": [ + 422, + 422 + ] + }, + { + "text": "If `Zve64x` is supported then `Zvkb` or `Zvbb` also add support for EEW 64.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview", + "line_range": [ + 422, + 422 + ] + }, + { + "text": "All cryptography-specific instructions defined in this Vector Crypto specification (i.e., those in , , , and but not ,, or ) shall be executed with data-independent execution latency as defined in the .", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview", + "line_range": [ + 427, + 432 + ] + }, + { + "text": "It is important to note that the Vector Crypto instructions are independent of the implementation of the `Zkt` extension and do not require that `Zkt` is implemented.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview", + "line_range": [ + 427, + 432 + ] + }, + { + "text": "This specification includes a extension that, when implemented, requires certain vector instructions (including , , and ) to be executed with data-independent execution latency.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview", + "line_range": [ + 434, + 435 + ] + }, + { + "text": "Detection of individual cryptography extensions uses the unified software-based RISC-V discovery method.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview", + "line_range": [ + 437, + 438 + ] + }, + { + "text": "Vector basic bit-manipulation instructions.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvbb` - Vector Basic Bit-manipulation", + "line_range": [ + 445, + 445 + ] + }, + { + "text": "| vandn.[vv,vx] | | vbrev.v | | vbrev8.v | | vrev8.v | | vclz.v | | vctz.v | | vcpop.v | | vrol.[vv,vx] | | vror.[vv,vx,vi] | | vwsll.[vv,vx,vi] |", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvbb` - Vector Basic Bit-manipulation", + "line_range": [ + 453, + 462 + ] + }, + { + "text": "General purpose carry-less multiplication instructions which are commonly used in cryptography and hashing (e.g., Elliptic curve cryptography, GHASH, CRC).", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvbc` - Vector Carry-less Multiplication", + "line_range": [ + 471, + 472 + ] + }, + { + "text": "These instructions are only defined for `SEW`=64.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvbc` - Vector Carry-less Multiplication", + "line_range": [ + 474, + 474 + ] + }, + { + "text": "| |Mnemonic |Instruction | vclmul.[vv,vx] | | vclmulh.[vv,vx] |", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvbc` - Vector Carry-less Multiplication", + "line_range": [ + 476, + 482 + ] + }, + { + "text": "Vector bit-manipulation instructions that are essential for implementing common cryptographic workloads securely & efficiently.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvkb` - Vector Cryptography Bit-manipulation", + "line_range": [ + 491, + 493 + ] + }, + { + "text": "| vandn.[vv,vx] | // | vbrev.v | | vbrev8.v | | vrev8.v | // | vclz.v | // | vctz.v | // | vcpop.v | | vrol.[vv,vx] | | vror.[vv,vx,vi] | // | vwsll.[vv,vx,vi] | |", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvkb` - Vector Cryptography Bit-manipulation", + "line_range": [ + 501, + 511 + ] + }, + { + "text": "Instructions to enable the efficient implementation of GHASH~H~ which is used in Galois/Counter Mode (GCM) and Galois Message Authentication Code (GMAC).", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvkg` - Vector GCM/GMAC", + "line_range": [ + 518, + 519 + ] + }, + { + "text": "All of these instructions work on 128-bit element groups comprised of four 32-bit elements.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvkg` - Vector GCM/GMAC", + "line_range": [ + 521, + 521 + ] + }, + { + "text": "GHASH~H~ is defined in the // link:https://csrc.nist.gov/publications/detail/sp/800-38d/final[NIST Special Publication 800-38D] \"Recommendation for Block Cipher Modes of Operation: Galois/Counter Mode (GCM) and GMAC\" cite:[nist:gcm] (NIST Specification).", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvkg` - Vector GCM/GMAC", + "line_range": [ + 523, + 527 + ] + }, + { + "text": "To help avoid side-channel timing attacks, these instructions shall be implemented with data-independent timing.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvkg` - Vector GCM/GMAC", + "line_range": [ + 529, + 529 + ] + }, + { + "text": "The number of element groups to be processed is `vl`/`EGS`. `vl` must be set to the number of `SEW=32` elements to be processed and therefore must be a multiple of `EGS=4`. + Likewise, `vstart` must be a multiple of `EGS=4`.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvkg` - Vector GCM/GMAC", + "line_range": [ + 531, + 534 + ] + }, + { + "text": "|SEW |EGW |Mnemonic |Instruction | 32 | 128 | vghsh.vv | | 32 | 128 | vgmul.vv |", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvkg` - Vector GCM/GMAC", + "line_range": [ + 540, + 545 + ] + }, + { + "text": "Instructions for accelerating encryption, decryption and key-schedule functions of the AES block cipher as defined in Federal Information Processing Standards Publication 197 cite:[nist:fips:197]", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvkned` - NIST Suite: Vector AES Block Cipher", + "line_range": [ + 554, + 558 + ] + }, + { + "text": "All of these instructions work on 128-bit element groups comprised of four 32-bit elements.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvkned` - NIST Suite: Vector AES Block Cipher", + "line_range": [ + 560, + 561 + ] + }, + { + "text": "For the best performance, it is suggested that these instruction be implemented on systems with `VLEN`>=128.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvkned` - NIST Suite: Vector AES Block Cipher", + "line_range": [ + 563, + 565 + ] + }, + { + "text": "On systems with `VLEN`<128, element groups may be formed by concatenating 32-bit elements from two or four registers by using an LMUL =2 and LMUL=4 respectively.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvkned` - NIST Suite: Vector AES Block Cipher", + "line_range": [ + 563, + 565 + ] + }, + { + "text": "To help avoid side-channel timing attacks, these instructions shall be implemented with data-independent timing.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvkned` - NIST Suite: Vector AES Block Cipher", + "line_range": [ + 571, + 571 + ] + }, + { + "text": "The number of element groups to be processed is `vl`/`EGS`. `vl` must be set to the number of `SEW=32` elements to be processed and therefore must be a multiple of `EGS=4`. + Likewise, `vstart` must be a multiple of `EGS=4`.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvkned` - NIST Suite: Vector AES Block Cipher", + "line_range": [ + 573, + 576 + ] + }, + { + "text": "| |SEW |EGW |Mnemonic |Instruction", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvkned` - NIST Suite: Vector AES Block Cipher", + "line_range": [ + 578, + 584 + ] + }, + { + "text": "| 32| 128 | vaesef.[vv,vs] | | 32| 128 | vaesem.[vv,vs] | | 32| 128 | vaesdf.[vv,vs] | | 32| 128 | vaesdm.[vv,vs] | | 32| 128 | vaeskf1.vi | | 32| 128 | vaeskf2.vi | | 32| 128 | vaesz.vs | |", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvkned` - NIST Suite: Vector AES Block Cipher", + "line_range": [ + 586, + 593 + ] + }, + { + "text": "Instructions for accelerating SHA-2 as defined in FIPS PUB 180-4 Secure Hash Standard (SHS) cite:[nist:fips:180:4]", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvknh[ab]` - NIST Suite: Vector SHA-2 Secure Hash", + "line_range": [ + 600, + 601 + ] + }, + { + "text": "`SEW` differentiates between SHA-256 (`SEW`=32) and SHA-512 (`SEW`=64).", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvknh[ab]` - NIST Suite: Vector SHA-2 Secure Hash", + "line_range": [ + 603, + 603 + ] + }, + { + "text": "SHA-256: these instructions work on 128-bit element groups comprised of four 32-bit elements. - SHA-512: these instructions work on 256-bit element groups comprised of four 64-bit elements.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvknh[ab]` - NIST Suite: Vector SHA-2 Secure Hash", + "line_range": [ + 605, + 606 + ] + }, + { + "text": "| |SEW |EGW |SHA-2 |Extension", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvknh[ab]` - NIST Suite: Vector SHA-2 Secure Hash", + "line_range": [ + 608, + 614 + ] + }, + { + "text": "|32 | 128 | SHA-256 | Zvknha, Zvknhb |64 | 256 | SHA-512 | Zvknhb |", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvknh[ab]` - NIST Suite: Vector SHA-2 Secure Hash", + "line_range": [ + 616, + 618 + ] + }, + { + "text": "Zvknhb supports SHA-256 and SHA-512. - Zvknha supports only SHA-256.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvknh[ab]` - NIST Suite: Vector SHA-2 Secure Hash", + "line_range": [ + 622, + 623 + ] + }, + { + "text": "SHA-256 implementations with VLEN < 128 require LMUL>1 to combine 32-bit elements from register groups to provide all four elements of the element group.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvknh[ab]` - NIST Suite: Vector SHA-2 Secure Hash", + "line_range": [ + 631, + 632 + ] + }, + { + "text": "SHA-512 implementations with VLEN < 256 require LMUL>1 to combine 64-bit elements from register groups to provide all four elements of the element group.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvknh[ab]` - NIST Suite: Vector SHA-2 Secure Hash", + "line_range": [ + 634, + 635 + ] + }, + { + "text": "To help avoid side-channel timing attacks, these instructions shall be implemented with data-independent timing.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvknh[ab]` - NIST Suite: Vector SHA-2 Secure Hash", + "line_range": [ + 640, + 640 + ] + }, + { + "text": "The number of element groups to be processed is `vl`/`EGS`. `vl` must be set to the number of `SEW` elements to be processed and therefore must be a multiple of `EGS=4`. + Likewise, `vstart` must be a multiple of `EGS=4`.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvknh[ab]` - NIST Suite: Vector SHA-2 Secure Hash", + "line_range": [ + 650, + 653 + ] + }, + { + "text": "| // |`VLENmin` |Mnemonic |Instruction", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvknh[ab]` - NIST Suite: Vector SHA-2 Secure Hash", + "line_range": [ + 655, + 660 + ] + }, + { + "text": "Instructions for accelerating encryption, decryption, and key-schedule functions of the SM4 block cipher.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvksed` - ShangMi Suite: SM4 Block Cipher", + "line_range": [ + 673, + 675 + ] + }, + { + "text": "The SM4 block cipher is specified in 32907-2016: \\{SM4} Block Cipher Algorithm cite:[gbt:sm4]", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvksed` - ShangMi Suite: SM4 Block Cipher", + "line_range": [ + 677, + 678 + ] + }, + { + "text": "There are other various sources available that describe the SM4 block cipher.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvksed` - ShangMi Suite: SM4 Block Cipher", + "line_range": [ + 680, + 683 + ] + }, + { + "text": "While not the final version of the standard, link:https://www.rfc-editor.org/rfc/rfc8998.html[RFC 8998 ShangMi (SM) Cipher Suites for TLS 1.3] is useful and easy to access.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvksed` - ShangMi Suite: SM4 Block Cipher", + "line_range": [ + 680, + 683 + ] + }, + { + "text": "All of these instructions work on 128-bit element groups comprised of four 32-bit elements.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvksed` - ShangMi Suite: SM4 Block Cipher", + "line_range": [ + 687, + 688 + ] + }, + { + "text": "To help avoid side-channel timing attacks, these instructions shall be implemented with data-independent timing.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvksed` - ShangMi Suite: SM4 Block Cipher", + "line_range": [ + 694, + 694 + ] + }, + { + "text": "The number of element groups to be processed is `vl`/`EGS`. `vl` must be set to the number of `SEW=32` elements to be processed and therefore must be a multiple of `EGS=4`. + Likewise, `vstart` must be a multiple of `EGS=4`.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvksed` - ShangMi Suite: SM4 Block Cipher", + "line_range": [ + 696, + 699 + ] + }, + { + "text": "| |SEW |EGW |Mnemonic |Instruction", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvksed` - ShangMi Suite: SM4 Block Cipher", + "line_range": [ + 701, + 707 + ] + }, + { + "text": "| 32 | 128 | vsm4k.vi | | 32 | 128 | vsm4r.[vv,vs] | |", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvksed` - ShangMi Suite: SM4 Block Cipher", + "line_range": [ + 709, + 711 + ] + }, + { + "text": "Instructions for accelerating functions of the SM3 Hash Function.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvksh` - ShangMi Suite: SM3 Secure Hash", + "line_range": [ + 718, + 719 + ] + }, + { + "text": "The SM3 secure hash algorithm is specified in 32905-2016: SM3 Cryptographic Hash Algorithm cite:[gbt:sm3]", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvksh` - ShangMi Suite: SM3 Secure Hash", + "line_range": [ + 721, + 722 + ] + }, + { + "text": "There are other various sources available that describe the SM3 secure hash.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvksh` - ShangMi Suite: SM3 Secure Hash", + "line_range": [ + 724, + 727 + ] + }, + { + "text": "While not the final version of the standard, link:https://www.rfc-editor.org/rfc/rfc8998.html[RFC 8998 ShangMi (SM) Cipher Suites for TLS 1.3] is useful and easy to access.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvksh` - ShangMi Suite: SM3 Secure Hash", + "line_range": [ + 724, + 727 + ] + }, + { + "text": "All of these instructions work on 256-bit element groups comprised of eight 32-bit elements.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvksh` - ShangMi Suite: SM3 Secure Hash", + "line_range": [ + 731, + 732 + ] + }, + { + "text": "Implementations with VLEN < 256 require LMUL>1 to combine 32-bit elements from register groups to provide all eight elements of the element group.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvksh` - ShangMi Suite: SM3 Secure Hash", + "line_range": [ + 734, + 735 + ] + }, + { + "text": "To help avoid side-channel timing attacks, these instructions shall be implemented with data-independent timing.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvksh` - ShangMi Suite: SM3 Secure Hash", + "line_range": [ + 746, + 746 + ] + }, + { + "text": "The number of element groups to be processed is `vl`/`EGS`. `vl` must be set to the number of `SEW=32` elements to be processed and therefore must be a multiple of `EGS=8`. + Likewise, `vstart` must be a multiple of `EGS=8`.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvksh` - ShangMi Suite: SM3 Secure Hash", + "line_range": [ + 748, + 751 + ] + }, + { + "text": "| | SEW | EGW | Mnemonic | Instruction", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvksh` - ShangMi Suite: SM3 Secure Hash", + "line_range": [ + 753, + 759 + ] + }, + { + "text": "| 32 | 256 | vsm3me.vv | | 32 | 256 | vsm3c.vi | |", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvksh` - ShangMi Suite: SM3 Secure Hash", + "line_range": [ + 761, + 763 + ] + }, + { + "text": "This extension is shorthand for the following set of other extensions:", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvkn` - NIST Algorithm Suite", + "line_range": [ + 770, + 770 + ] + }, + { + "text": "| |Included Extension |Description", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvkn` - NIST Algorithm Suite", + "line_range": [ + 772, + 776 + ] + }, + { + "text": "| Zvkned | | Zvknhb | // | Zvbb | | Zvkb | // | Zvbc | | Zvkt | |", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvkn` - NIST Algorithm Suite", + "line_range": [ + 778, + 784 + ] + }, + { + "text": "This extension is shorthand for the following set of other extensions:", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvknc` - NIST Algorithm Suite with carry-less multiply", + "line_range": [ + 792, + 792 + ] + }, + { + "text": "| |Included Extension |Description", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvknc` - NIST Algorithm Suite with carry-less multiply", + "line_range": [ + 794, + 798 + ] + }, + { + "text": "This extension is shorthand for the following set of other extensions:", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvkng` - NIST Algorithm Suite with GCM", + "line_range": [ + 810, + 810 + ] + }, + { + "text": "| |Included Extension |Description", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvkng` - NIST Algorithm Suite with GCM", + "line_range": [ + 812, + 816 + ] + }, + { + "text": "This extension is shorthand for the following set of other extensions:", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvks` - ShangMi Algorithm Suite", + "line_range": [ + 828, + 828 + ] + }, + { + "text": "| |Included Extension |Description", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvks` - ShangMi Algorithm Suite", + "line_range": [ + 830, + 834 + ] + }, + { + "text": "| Zvksed | | Zvksh | // | Zvbb | | Zvkb | // | Zvbc | | Zvkt | |", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvks` - ShangMi Algorithm Suite", + "line_range": [ + 836, + 842 + ] + }, + { + "text": "This extension is shorthand for the following set of other extensions:", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvksc` - ShangMi Algorithm Suite with carry-less multiplication", + "line_range": [ + 850, + 850 + ] + }, + { + "text": "| |Included Extension |Description", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvksc` - ShangMi Algorithm Suite with carry-less multiplication", + "line_range": [ + 852, + 856 + ] + }, + { + "text": "This extension is shorthand for the following set of other extensions:", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvksg` - ShangMi Algorithm Suite with GCM", + "line_range": [ + 868, + 868 + ] + }, + { + "text": "| |Included Extension |Description", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvksg` - ShangMi Algorithm Suite with GCM", + "line_range": [ + 870, + 874 + ] + }, + { + "text": "The Zvkt extension requires all implemented instructions from the following list to be executed with data-independent execution latency as defined in the .", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvkt` - Vector Data-Independent Execution Latency", + "line_range": [ + 886, + 888 + ] + }, + { + "text": "Data-independent execution latency (DIEL) applies to all data operands of an instruction, even those that are not a part of the body or that are inactive.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvkt` - Vector Data-Independent Execution Latency", + "line_range": [ + 890, + 897 + ] + }, + { + "text": "However, DIEL does not apply to other values such as vl, vtype, and the mask (when used to control execution of a masked vector instruction).", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvkt` - Vector Data-Independent Execution Latency", + "line_range": [ + 890, + 897 + ] + }, + { + "text": "Also, DIEL does not apply to constant values specified in the instruction encoding such as the use of the zero register (`x0`), and, in the case of immediate forms of an instruction, the values in the immediate fields (i.e., imm, and uimm).", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvkt` - Vector Data-Independent Execution Latency", + "line_range": [ + 890, + 897 + ] + }, + { + "text": "In some cases --- which are explicitly specified in the lists below --- operands that are used as control rather than data are exempt from DIEL.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvkt` - Vector Data-Independent Execution Latency", + "line_range": [ + 899, + 901 + ] + }, + { + "text": "vandn.v[vx] - vclz.v - vcpop.v - vctz.v - vbrev.v - vbrev8.v - vrev8.v - vrol.v[vx] - vror.v[vxi] - vwsll.[vv,vx,vi]", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvkt` - Vector Data-Independent Execution Latency > All <> instructions", + "line_range": [ + 905, + 914 + ] + }, + { + "text": "v[r]sub.v[vx] - vadd.v[ivx] - vsub.v[vx] - vwadd[u].[vw][vx] - vwsub[u].[vw][vx]", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvkt` - Vector Data-Independent Execution Latency > add/sub", + "line_range": [ + 920, + 924 + ] + }, + { + "text": "vadc.v[ivx]m - vmadc.v[ivx][m] - vmsbc.v[vx]m - vsbc.v[vx]m", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvkt` - Vector Data-Independent Execution Latency > add/sub with carry", + "line_range": [ + 927, + 930 + ] + }, + { + "text": "vmseq.v[vxi] - vmsgt[u].v[xi] - vmsle[u].v[xi] - vmslt[u].v[xi] - vmsne.v[ivx]", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvkt` - Vector Data-Independent Execution Latency > compare and set", + "line_range": [ + 933, + 937 + ] + }, + { + "text": "vmv.s.x - vmv.v.[ivxs] - vmv[1248]r.v", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvkt` - Vector Data-Independent Execution Latency > copy", + "line_range": [ + 940, + 942 + ] + }, + { + "text": "vsext.vf[248] - vzext.vf[248]", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvkt` - Vector Data-Independent Execution Latency > extend", + "line_range": [ + 945, + 946 + ] + }, + { + "text": "vand.v[ivx] - vm[n]or.mm - vmand[n].mm - vmnand.mm - vmorn.mm - vmx[n]or.mm - vor.v[ivx] - vxor.v[ivx]", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvkt` - Vector Data-Independent Execution Latency > logical", + "line_range": [ + 949, + 956 + ] + }, + { + "text": "vmul[h].v[vx] - vmulh[s]u.v[vx] - vwmul.v[vx] - vwmul[s]u.v[vx]", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvkt` - Vector Data-Independent Execution Latency > multiply", + "line_range": [ + 959, + 962 + ] + }, + { + "text": "vmacc.v[vx] - vmadd.v[vx] - vnmsac.v[vx] - vnmsub.v[vx] - vwmacc.v[vx] - vwmacc[s]u.v[vx] - vwmaccus.vx", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvkt` - Vector Data-Independent Execution Latency > multiply-add", + "line_range": [ + 965, + 971 + ] + }, + { + "text": "In the `.vv` and `.xv` forms of the `vrgather[ei16]` instructions, the values in `vs1` and `rs1` are used for control and therefore are exempt from DIEL.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvkt` - Vector Data-Independent Execution Latency > permute", + "line_range": [ + 977, + 978 + ] + }, + { + "text": "vrgather.v[ivx] - vrgatherei16.vv", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvkt` - Vector Data-Independent Execution Latency > permute", + "line_range": [ + 980, + 981 + ] + }, + { + "text": "vnsr[al].w[ivx] - vsll.v[ivx] - vsr[al].v[ivx]", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvkt` - Vector Data-Independent Execution Latency > shift", + "line_range": [ + 986, + 988 + ] + }, + { + "text": "vslide1[up|down].vx - vfslide1[up|down].vf", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvkt` - Vector Data-Independent Execution Latency > slide", + "line_range": [ + 991, + 992 + ] + }, + { + "text": "In the vslide[up|down].vx instructions, the value in `rs1` is used for control (i.e., slide amount) and therefore is exempt from DIEL.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Extensions Overview > `Zvkt` - Vector Data-Independent Execution Latency > slide", + "line_range": [ + 994, + 996 + ] + }, + { + "text": "Synopsis:: Vector AES final-round decryption", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesdf.[vv,vs]", + "line_range": [ + 1005, + 1006 + ] + }, + { + "text": "Mnemonic:: vaesdf.vv vd, vs2 + vaesdf.vs vd, vs2", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesdf.[vv,vs]", + "line_range": [ + 1008, + 1010 + ] + }, + { + "text": "Encoding (Vector-Vector):: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 'OP-VE'}, {bits: 5, name: 'vd'}, {bits: 3, name: 'OPMVV'}, {bits: 5, name: '00001'}, {bits: 5, name: 'vs2'}, {bits: 1, name: '1'}, {bits: 6, name: '101000'}, ]} ....", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesdf.[vv,vs]", + "line_range": [ + 1012, + 1024 + ] + }, + { + "text": "Encoding (Vector-Scalar):: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 'OP-VE'}, {bits: 5, name: 'vd'}, {bits: 3, name: 'OPMVV'}, {bits: 5, name: '00001'}, {bits: 5, name: 'vs2'}, {bits: 1, name: '1'}, {bits: 6, name: '101001'}, ]} ....", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesdf.[vv,vs]", + "line_range": [ + 1026, + 1041 + ] + }, + { + "text": "Reserved Encodings:: * `SEW` is any value other than 32 * Only for the `.vs` form: the `vd` register group overlaps the `vs2` scalar element group", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesdf.[vv,vs]", + "line_range": [ + 1026, + 1041 + ] + }, + { + "text": "| |Register |Direction |EGW |EGS |EEW |Definition", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesdf.[vv,vs]", + "line_range": [ + 1045, + 1053 + ] + }, + { + "text": "| Vd | input | 128 | 4 | 32 | round state | Vs2 | input | 128 | 4 | 32 | round key | Vd | output | 128 | 4 | 32 | new round state |", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesdf.[vv,vs]", + "line_range": [ + 1055, + 1058 + ] + }, + { + "text": "Description:: A final-round AES block cipher decryption is performed.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesdf.[vv,vs]", + "line_range": [ + 1060, + 1061 + ] + }, + { + "text": "The InvShiftRows and InvSubBytes steps are applied to each round state element group from `vd`.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesdf.[vv,vs]", + "line_range": [ + 1063, + 1065 + ] + }, + { + "text": "This is then XORed with the round key in either the corresponding element group in `vs2` (vector-vector form) or scalar element group in `vs2` (vector-scalar form).", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesdf.[vv,vs]", + "line_range": [ + 1063, + 1065 + ] + }, + { + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated upon.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesdf.[vv,vs]", + "line_range": [ + 1067, + 1068 + ] + }, + { + "text": "Operation:: [source,sail] -- function clause execute (VAESDF(vs2, vd, suffix)) = { if(LMUL*VLEN < EGW) then { handleillegal(); // illegal-instruction exception RETIREFAIL } else {", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesdf.[vv,vs]", + "line_range": [ + 1072, + 1079 + ] + }, + { + "text": "eglen = (vl/EGS) egstart = (vstart/EGS)", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesdf.[vv,vs]", + "line_range": [ + 1081, + 1082 + ] + }, + { + "text": "foreach (i from egstart to eglen-1) { let keyelem = if suffix \"vv\" then i else 0; let state : bits(128) = getvelem(vd, EGW=128, i); let rkey : bits(128) = getvelem(vs2, EGW=128, keyelem); let sr : bits(128) = aesshiftrowsinv(state); let sb : bits(128) = aessubbytesinv(sr); let ark : bits(128) = sb ^ rkey; setvelem(vd, EGW=128, i, ark); } RETIRESUCCESS } } --", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesdf.[vv,vs]", + "line_range": [ + 1084, + 1096 + ] + }, + { + "text": "Synopsis:: Vector AES middle-round decryption", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesdm.[vv,vs]", + "line_range": [ + 1106, + 1107 + ] + }, + { + "text": "Mnemonic:: vaesdm.vv vd, vs2 + vaesdm.vs vd, vs2", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesdm.[vv,vs]", + "line_range": [ + 1109, + 1111 + ] + }, + { + "text": "Encoding (Vector-Vector):: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 'OP-VE'}, {bits: 5, name: 'vd'}, {bits: 3, name: 'OPMVV'}, {bits: 5, name: '00000'}, {bits: 5, name: 'vs2'}, {bits: 1, name: '1'}, {bits: 6, name: '101000'}, ]} ....", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesdm.[vv,vs]", + "line_range": [ + 1113, + 1125 + ] + }, + { + "text": "Encoding (Vector-Scalar):: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 'OP-VE'}, {bits: 5, name: 'vd'}, {bits: 3, name: 'OPMVV'}, {bits: 5, name: '00000'}, {bits: 5, name: 'vs2'}, {bits: 1, name: '1'}, {bits: 6, name: '101001'}, ]} ....", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesdm.[vv,vs]", + "line_range": [ + 1127, + 1142 + ] + }, + { + "text": "Reserved Encodings:: * `SEW` is any value other than 32 * Only for the `.vs` form: the `vd` register group overlaps the `vs2` scalar element group", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesdm.[vv,vs]", + "line_range": [ + 1127, + 1142 + ] + }, + { + "text": "| |Register |Direction |EGW |EGS |EEW |Definition", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesdm.[vv,vs]", + "line_range": [ + 1146, + 1154 + ] + }, + { + "text": "| Vd | input | 128 | 4 | 32 | round state | Vs2 | input | 128 | 4 | 32 | round key | Vd | output | 128 | 4 | 32 | new round state |", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesdm.[vv,vs]", + "line_range": [ + 1156, + 1159 + ] + }, + { + "text": "Description:: A middle-round AES block cipher decryption is performed.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesdm.[vv,vs]", + "line_range": [ + 1161, + 1162 + ] + }, + { + "text": "The InvShiftRows and InvSubBytes steps are applied to each round state element group from `vd`.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesdm.[vv,vs]", + "line_range": [ + 1164, + 1167 + ] + }, + { + "text": "This is then XORed with the round key in either the corresponding element group in `vs2` (vector-vector form) or the scalar element group in `vs2` (vector-scalar form).", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesdm.[vv,vs]", + "line_range": [ + 1164, + 1167 + ] + }, + { + "text": "The result is then applied to the InvMixColumns step.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesdm.[vv,vs]", + "line_range": [ + 1164, + 1167 + ] + }, + { + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated upon. // // The number of element groups to be processed is `vl`/`EGS`. // `vl` must be set to the number of `SEW=32` elements to be processed and // therefore must be a multiple of `EGS=4`. + // Likewise, `vstart` must be a multiple of `EGS=4`.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesdm.[vv,vs]", + "line_range": [ + 1169, + 1175 + ] + }, + { + "text": "Operation:: [source,sail] -- function clause execute (VAESDM(vs2, vd, suffix)) = { if(LMUL*VLEN < EGW) then { handleillegal(); // illegal-instruction exception RETIREFAIL } else {", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesdm.[vv,vs]", + "line_range": [ + 1177, + 1184 + ] + }, + { + "text": "eglen = (vl/EGS) egstart = (vstart/EGS)", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesdm.[vv,vs]", + "line_range": [ + 1186, + 1187 + ] + }, + { + "text": "foreach (i from egstart to eglen-1) { let keyelem = if suffix \"vv\" then i else 0; let state : bits(128) = getvelem(vd, EGW=128, i); let rkey : bits(128) = getvelem(vs2, EGW=128, keyelem); let sr : bits(128) = aesshiftrowsinv(state); let sb : bits(128) = aessubbytesinv(sr); let ark : bits(128) = sb ^ rkey; let mix : bits(128) = aesmixcolumnsinv(ark); setvelem(vd, EGW=128, i, mix); } RETIRESUCCESS } } --", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesdm.[vv,vs]", + "line_range": [ + 1189, + 1202 + ] + }, + { + "text": "Synopsis:: Vector AES final-round encryption", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesef.[vv,vs]", + "line_range": [ + 1212, + 1213 + ] + }, + { + "text": "Mnemonic:: vaesef.vv vd, vs2 + vaesef.vs vd, vs2", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesef.[vv,vs]", + "line_range": [ + 1215, + 1217 + ] + }, + { + "text": "Encoding (Vector-Vector):: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 'OP-VE'}, {bits: 5, name: 'vd'}, {bits: 3, name: 'OPMVV'}, {bits: 5, name: '00011'}, {bits: 5, name: 'vs2'}, {bits: 1, name: '1'}, {bits: 6, name: '101000'}, ]} ....", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesef.[vv,vs]", + "line_range": [ + 1219, + 1231 + ] + }, + { + "text": "Encoding (Vector-Scalar):: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 'OP-VE'}, {bits: 5, name: 'vd'}, {bits: 3, name: 'OPMVV'}, {bits: 5, name: '00011'}, {bits: 5, name: 'vs2'}, {bits: 1, name: '1'}, {bits: 6, name: '101001'}, ]} ....", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesef.[vv,vs]", + "line_range": [ + 1233, + 1248 + ] + }, + { + "text": "Reserved Encodings:: * `SEW` is any value other than 32 * Only for the `.vs` form: the `vd` register group overlaps the `vs2` scalar element group", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesef.[vv,vs]", + "line_range": [ + 1233, + 1248 + ] + }, + { + "text": "| |Register |Direction |EGW |EGS |EEW |Definition", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesef.[vv,vs]", + "line_range": [ + 1252, + 1260 + ] + }, + { + "text": "| vd | input | 128 | 4 | 32 | round state | vs2 | input | 128 | 4 | 32 | round key | vd | output | 128 | 4 | 32 | new round state |", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesef.[vv,vs]", + "line_range": [ + 1262, + 1265 + ] + }, + { + "text": "Description:: A final-round encryption function of the AES block cipher is performed.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesef.[vv,vs]", + "line_range": [ + 1267, + 1268 + ] + }, + { + "text": "The SubBytes and ShiftRows steps are applied to each round state element group from `vd`.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesef.[vv,vs]", + "line_range": [ + 1270, + 1272 + ] + }, + { + "text": "This is then XORed with the round key in either the corresponding element group in `vs2` (vector-vector form) or the scalar element group in `vs2` (vector-scalar form).", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesef.[vv,vs]", + "line_range": [ + 1270, + 1272 + ] + }, + { + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated upon. // // The number of element groups to be processed is `vl`/`EGS`. // `vl` must be set to the number of `SEW=32` elements to be processed and // therefore must be a multiple of `EGS=4`. + // Likewise, `vstart` must be a multiple of `EGS=4`.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesef.[vv,vs]", + "line_range": [ + 1274, + 1280 + ] + }, + { + "text": "Operation:: [source,sail] -- function clause execute (VAESEF(vs2, vd, suffix) = { if(LMUL*VLEN < EGW) then { handleillegal(); // illegal-instruction exception RETIREFAIL } else {", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesef.[vv,vs]", + "line_range": [ + 1282, + 1289 + ] + }, + { + "text": "eglen = (vl/EGS) egstart = (vstart/EGS)", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesef.[vv,vs]", + "line_range": [ + 1291, + 1292 + ] + }, + { + "text": "foreach (i from egstart to eglen-1) { let keyelem = if suffix \"vv\" then i else 0; let state : bits(128) = getvelem(vd, EGW=128, i); let rkey : bits(128) = getvelem(vs2, EGW=128, keyelem); let sb : bits(128) = aessubbytesfwd(state); let sr : bits(128) = aesshiftrowsfwd(sb); let ark : bits(128) = sr ^ rkey; setvelem(vd, EGW=128, i, ark); } RETIRESUCCESS } } --", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesef.[vv,vs]", + "line_range": [ + 1294, + 1306 + ] + }, + { + "text": "Synopsis:: Vector AES middle-round encryption", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesem.[vv,vs]", + "line_range": [ + 1317, + 1318 + ] + }, + { + "text": "Mnemonic:: vaesem.vv vd, vs2 + vaesem.vs vd, vs2", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesem.[vv,vs]", + "line_range": [ + 1320, + 1322 + ] + }, + { + "text": "Encoding (Vector-Vector):: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 'OP-VE'}, {bits: 5, name: 'vd'}, {bits: 3, name: 'OPMVV'}, {bits: 5, name: '00010'}, {bits: 5, name: 'vs2'}, {bits: 1, name: '1'}, {bits: 6, name: '101000'}, ]} ....", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesem.[vv,vs]", + "line_range": [ + 1324, + 1336 + ] + }, + { + "text": "Encoding (Vector-Scalar):: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 'OP-VE'}, {bits: 5, name: 'vd'}, {bits: 3, name: 'OPMVV'}, {bits: 5, name: '00010'}, {bits: 5, name: 'vs2'}, {bits: 1, name: '1'}, {bits: 6, name: '101001'}, ]} ....", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesem.[vv,vs]", + "line_range": [ + 1338, + 1353 + ] + }, + { + "text": "Reserved Encodings:: * `SEW` is any value other than 32 * Only for the `.vs` form: the `vd` register group overlaps the `vs2` scalar element group", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesem.[vv,vs]", + "line_range": [ + 1338, + 1353 + ] + }, + { + "text": "| |Register |Direction |EGW |EGS |EEW |Definition", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesem.[vv,vs]", + "line_range": [ + 1357, + 1365 + ] + }, + { + "text": "| Vd | input | 128 | 4 | 32 | round state | Vs2 | input | 128 | 4 | 32 | Round key | Vd | output | 128 | 4 | 32 | new round state |", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesem.[vv,vs]", + "line_range": [ + 1367, + 1370 + ] + }, + { + "text": "Description:: A middle-round encryption function of the AES block cipher is performed.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesem.[vv,vs]", + "line_range": [ + 1372, + 1373 + ] + }, + { + "text": "The SubBytes, ShiftRows, and MixColumns steps are applied to each round state element group from `vd`.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesem.[vv,vs]", + "line_range": [ + 1375, + 1377 + ] + }, + { + "text": "This is then XORed with the round key in either the corresponding element group in `vs2` (vector-vector form) or the scalar element group in `vs2` (vector-scalar form).", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesem.[vv,vs]", + "line_range": [ + 1375, + 1377 + ] + }, + { + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated upon. // // The number of element groups to be processed is `vl`/`EGS`. // `vl` must be set to the number of `SEW=32` elements to be processed and // therefore must be a multiple of `EGS=4`. + // Likewise, `vstart` must be a multiple of `EGS=4`.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesem.[vv,vs]", + "line_range": [ + 1379, + 1385 + ] + }, + { + "text": "Operation:: [source,sail] -- function clause execute (VAESEM(vs2, vd, suffix)) = { if(LMUL*VLEN < EGW) then { handleillegal(); // illegal-instruction exception RETIREFAIL } else {", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesem.[vv,vs]", + "line_range": [ + 1387, + 1394 + ] + }, + { + "text": "eglen = (vl/EGS) egstart = (vstart/EGS)", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesem.[vv,vs]", + "line_range": [ + 1396, + 1397 + ] + }, + { + "text": "foreach (i from egstart to eglen-1) { let keyelem = if suffix \"vv\" then i else 0; let state : bits(128) = getvelem(vd, EGW=128, i); let rkey : bits(128) = getvelem(vs2, EGW=128, keyelem); let sb : bits(128) = aessubbytesfwd(state); let sr : bits(128) = aesshiftrowsfwd(sb); let mix : bits(128) = aesmixcolumnsfwd(sr); let ark : bits(128) = mix ^ rkey; setvelem(vd, EGW=128, i, ark); } RETIRESUCCESS } } --", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesem.[vv,vs]", + "line_range": [ + 1399, + 1412 + ] + }, + { + "text": "Synopsis:: Vector AES-128 Forward KeySchedule generation", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaeskf1.vi", + "line_range": [ + 1423, + 1424 + ] + }, + { + "text": "Mnemonic:: vaeskf1.vi vd, vs2, uimm", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaeskf1.vi", + "line_range": [ + 1426, + 1427 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 'OP-VE'}, {bits: 5, name: 'vd'}, {bits: 3, name: 'OPMVV'}, {bits: 5, name: 'uimm'}, {bits: 5, name: 'vs2'}, {bits: 1, name: '1'}, {bits: 6, name: '100010'}, ]} ....", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaeskf1.vi", + "line_range": [ + 1429, + 1443 + ] + }, + { + "text": "Reserved Encodings:: * `SEW` is any value other than 32", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaeskf1.vi", + "line_range": [ + 1429, + 1443 + ] + }, + { + "text": "| |Register |Direction |EGW |EGS |EEW |Definition", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaeskf1.vi", + "line_range": [ + 1447, + 1455 + ] + }, + { + "text": "| uimm | input | - | - | - | Round Number (rnd) | Vs2 | input | 128 | 4 | 32 | Current round key | Vd | output | 128 | 4 | 32 | Next round key |", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaeskf1.vi", + "line_range": [ + 1457, + 1460 + ] + }, + { + "text": "Description:: A single round of the forward AES-128 KeySchedule is performed.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaeskf1.vi", + "line_range": [ + 1462, + 1463 + ] + }, + { + "text": "The round number, which ranges from 1 to 10, comes from `uimm[3:0]`; `uimm[4]` is ignored.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaeskf1.vi", + "line_range": [ + 1472, + 1477 + ] + }, + { + "text": "The out-of-range `uimm[3:0]` values of 0 and 11-15 are mapped to in-range values by inverting `uimm[3]`.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaeskf1.vi", + "line_range": [ + 1472, + 1477 + ] + }, + { + "text": "Thus, 0 maps to 8, and 11-15 maps to 3-7.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaeskf1.vi", + "line_range": [ + 1472, + 1477 + ] + }, + { + "text": "The round number is used to specify a round constant which is used in generating the first round key word.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaeskf1.vi", + "line_range": [ + 1472, + 1477 + ] + }, + { + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated upon.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaeskf1.vi", + "line_range": [ + 1479, + 1480 + ] + }, + { + "text": "Operation:: [source,Sail] -- function clause execute (VAESKF1(rnd, vd, vs2)) = { if(LMUL*VLEN < EGW) then { handleillegal(); // illegal-instruction exception RETIREFAIL } else {", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaeskf1.vi", + "line_range": [ + 1491, + 1498 + ] + }, + { + "text": "eglen = (vl/EGS) egstart = (vstart/EGS)", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaeskf1.vi", + "line_range": [ + 1503, + 1504 + ] + }, + { + "text": "foreach (i from egstart to eglen-1) { let CurrentRoundKey[3:0] : bits(128) = getvelem(vs2, EGW=128, i); let w[0] : bits(32) = aessubwordfwd(aesrotword(CurrentRoundKey[3])) XOR aesdecodercon(r) XOR CurrentRoundKey[0] let w[1] : bits(32) = w[0] XOR CurrentRoundKey[1] let w[2] : bits(32) = w[1] XOR CurrentRoundKey[2] let w[3] : bits(32) = w[2] XOR CurrentRoundKey[3] setvelem(vd, EGW=128, i, w[3:0]); } RETIRESUCCESS } }", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaeskf1.vi", + "line_range": [ + 1508, + 1519 + ] + }, + { + "text": "Synopsis:: Vector AES-256 Forward KeySchedule generation", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaeskf2.vi", + "line_range": [ + 1533, + 1534 + ] + }, + { + "text": "Mnemonic:: vaeskf2.vi vd, vs2, uimm", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaeskf2.vi", + "line_range": [ + 1536, + 1537 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 'OP-VE'}, {bits: 5, name: 'vd'}, {bits: 3, name: 'OPMVV'}, {bits: 5, name: 'uimm'}, {bits: 5, name: 'vs2'}, {bits: 1, name: '1'}, {bits: 6, name: '101010'}, ]} ....", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaeskf2.vi", + "line_range": [ + 1539, + 1553 + ] + }, + { + "text": "Reserved Encodings:: * `SEW` is any value other than 32", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaeskf2.vi", + "line_range": [ + 1539, + 1553 + ] + }, + { + "text": "| |Register |Direction |EGW |EGS |EEW |Definition", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaeskf2.vi", + "line_range": [ + 1557, + 1565 + ] + }, + { + "text": "| Vd | input | 128 | 4 | 32 | Previous Round key | uimm | input | - | - | - | Round Number (rnd) | Vs2 | input | 128 | 4 | 32 | Current Round key | Vd | output | 128 | 4 | 32 | Next round key |", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaeskf2.vi", + "line_range": [ + 1567, + 1571 + ] + }, + { + "text": "Description:: A single round of the forward AES-256 KeySchedule is performed.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaeskf2.vi", + "line_range": [ + 1573, + 1574 + ] + }, + { + "text": "The round number, which ranges from 2 to 14, comes from `uimm[3:0]`; `uimm[4]` is ignored.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaeskf2.vi", + "line_range": [ + 1584, + 1587 + ] + }, + { + "text": "The out-of-range `uimm[3:0]` values of 0-1 and 15 are mapped to in-range values by inverting `uimm[3]`.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaeskf2.vi", + "line_range": [ + 1584, + 1587 + ] + }, + { + "text": "Thus, 0-1 maps to 8-9, and 15 maps to 7.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaeskf2.vi", + "line_range": [ + 1584, + 1587 + ] + }, + { + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated upon.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaeskf2.vi", + "line_range": [ + 1589, + 1590 + ] + }, + { + "text": "Operation:: [source,Sail] -- function clause execute (VAESKF2(rnd, vd, vs2)) = { if(LMUL*VLEN < EGW) then { handleillegal(); // illegal-instruction exception RETIREFAIL } else {", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaeskf2.vi", + "line_range": [ + 1599, + 1606 + ] + }, + { + "text": "eglen = (vl/EGS) egstart = (vstart/EGS)", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaeskf2.vi", + "line_range": [ + 1611, + 1612 + ] + }, + { + "text": "foreach (i from egstart to eglen-1) { let CurrentRoundKey[3:0] : bits(128) = getvelem(vs2, EGW=128, i); let RoundKeyB[3:0] : bits(128) = getvelem(vd, EGW=128, i); // Previous round key", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaeskf2.vi", + "line_range": [ + 1614, + 1616 + ] + }, + { + "text": "let w[0] : bits(32) = if (rnd[0]1) then aessubwordfwd(CurrentRoundKey[3]) XOR RoundKeyB[0]; else aessubwordfwd(aesrotword(CurrentRoundKey[3])) XOR aesdecodercon((rnd>>1) - 1) XOR RoundKeyB[0]; w[1] : bits(32) = w[0] XOR RoundKeyB[1] w[2] : bits(32) = w[1] XOR RoundKeyB[2] w[3] : bits(32) = w[2] XOR RoundKeyB[3] setvelem(vd, EGW=128, i, w[3:0]); } RETIRESUCCESS } } --", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaeskf2.vi", + "line_range": [ + 1618, + 1630 + ] + }, + { + "text": "Synopsis:: Vector AES round zero encryption/decryption", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesz.vs", + "line_range": [ + 1640, + 1641 + ] + }, + { + "text": "Mnemonic:: vaesz.vs vd, vs2", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesz.vs", + "line_range": [ + 1643, + 1644 + ] + }, + { + "text": "Encoding (Vector-Scalar):: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 'OP-VE'}, {bits: 5, name: 'vd'}, {bits: 3, name: 'OPMVV'}, {bits: 5, name: '00111'}, {bits: 5, name: 'vs2'}, {bits: 1, name: '1'}, {bits: 6, name: '101001'}, ]} ....", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesz.vs", + "line_range": [ + 1646, + 1661 + ] + }, + { + "text": "Reserved Encodings:: * `SEW` is any value other than 32 * The `vd` register group overlaps the `vs2` register", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesz.vs", + "line_range": [ + 1646, + 1661 + ] + }, + { + "text": "| |Register |Direction |EGW |EGS |EEW |Definition", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesz.vs", + "line_range": [ + 1665, + 1673 + ] + }, + { + "text": "| vd | input | 128 | 4 | 32 | round state | vs2 | input | 128 | 4 | 32 | round key | vd | output | 128 | 4 | 32 | new round state |", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesz.vs", + "line_range": [ + 1675, + 1678 + ] + }, + { + "text": "Description:: A round-0 AES block cipher operation is performed.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesz.vs", + "line_range": [ + 1680, + 1681 + ] + }, + { + "text": "This operation is used for both encryption and decryption.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesz.vs", + "line_range": [ + 1680, + 1681 + ] + }, + { + "text": "There is only a `.vs` form of the instruction. `Vs2` holds a scalar element group that is used as the round key for all of the round state element groups.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesz.vs", + "line_range": [ + 1683, + 1688 + ] + }, + { + "text": "The new round state output of each element group is produced by XORing the round key with each element group of `vd`.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesz.vs", + "line_range": [ + 1683, + 1688 + ] + }, + { + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated upon.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesz.vs", + "line_range": [ + 1690, + 1691 + ] + }, + { + "text": "Operation:: [source,sail] -- function clause execute (VAESZ(vs2, vd) = { if(((vstart%EGS)<>0) | (LMUL*VLEN < EGW)) then { handleillegal(); // illegal-instruction exception RETIREFAIL } else {", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesz.vs", + "line_range": [ + 1699, + 1706 + ] + }, + { + "text": "eglen = (vl/EGS) egstart = (vstart/EGS)", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesz.vs", + "line_range": [ + 1708, + 1709 + ] + }, + { + "text": "foreach (i from egstart to eglen-1) { let state : bits(128) = getvelem(vd, EGW=128, i); let rkey : bits(128) = getvelem(vs2, EGW=128, 0); let ark : bits(128) = state ^ rkey; setvelem(vd, EGW=128, i, ark); } RETIRESUCCESS } } --", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vaesz.vs", + "line_range": [ + 1711, + 1720 + ] + }, + { + "text": "Synopsis:: Bitwise And-Not", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vandn.[vv,vx]", + "line_range": [ + 1730, + 1731 + ] + }, + { + "text": "Mnemonic:: vandn.vv vd, vs2, vs1, vm + vandn.vx vd, vs2, rs1, vm", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vandn.[vv,vx]", + "line_range": [ + 1733, + 1735 + ] + }, + { + "text": "Encoding (Vector-Vector):: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 'OP-V'}, {bits: 5, name: 'vd'}, {bits: 3, name: 'OPIVV'}, {bits: 5, name: 'vs1'}, {bits: 5, name: 'vs2'}, {bits: 1, name: 'vm'}, {bits: 6, name: '000001'}, ]} ....", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vandn.[vv,vx]", + "line_range": [ + 1737, + 1749 + ] + }, + { + "text": "Encoding (Vector-Scalar):: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 'OP-V'}, {bits: 5, name: 'vd'}, {bits: 3, name: 'OPIVX'}, {bits: 5, name: 'rs1'}, {bits: 5, name: 'vs2'}, {bits: 1, name: 'vm'}, {bits: 6, name: '000001'}, ]} ....", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vandn.[vv,vx]", + "line_range": [ + 1751, + 1763 + ] + }, + { + "text": "| |Register |Direction |Definition", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vandn.[vv,vx]", + "line_range": [ + 1767, + 1772 + ] + }, + { + "text": "| Vs1 | input | Op1 (to be inverted) | Vs2 | input | Op2 | Vd | output | Result |", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vandn.[vv,vx]", + "line_range": [ + 1774, + 1777 + ] + }, + { + "text": "| |Register |Direction |Definition", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vandn.[vv,vx]", + "line_range": [ + 1781, + 1786 + ] + }, + { + "text": "| Rs1 | input | Op1 (to be inverted) | Vs2 | input | Op2 | Vd | output | Result |", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vandn.[vv,vx]", + "line_range": [ + 1788, + 1791 + ] + }, + { + "text": "Description:: A bitwise and-not operation is performed.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vandn.[vv,vx]", + "line_range": [ + 1793, + 1794 + ] + }, + { + "text": "Each bit of `Op1` is inverted and logically ANDed with the corresponding bits in `vs2`.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vandn.[vv,vx]", + "line_range": [ + 1796, + 1799 + ] + }, + { + "text": "In the vector-scalar version, `Op1` is the sign-extended or truncated value in scalar register `rs1`.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vandn.[vv,vx]", + "line_range": [ + 1796, + 1799 + ] + }, + { + "text": "In the vector-vector version, `Op1` is `vs1`.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vandn.[vv,vx]", + "line_range": [ + 1796, + 1799 + ] + }, + { + "text": "[NOTE] .Note on necessity of instruction This instruction is performance-critical to SHA3.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vandn.[vv,vx]", + "line_range": [ + 1804, + 1810 + ] + }, + { + "text": "Specifically, the Chi step of the FIPS 202 Keccak Permutation.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vandn.[vv,vx]", + "line_range": [ + 1804, + 1810 + ] + }, + { + "text": "Emulating it via 2 instructions is expected to have significant performance impact.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vandn.[vv,vx]", + "line_range": [ + 1804, + 1810 + ] + }, + { + "text": "The `.vv` form of the instruction is what is needed for SHA3; the `.vx` form was added for completeness.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vandn.[vv,vx]", + "line_range": [ + 1804, + 1810 + ] + }, + { + "text": "Operation:: [source,sail] -- function clause execute (VANDN(vs2, vs1, vd, suffix)) = { foreach (i from vstart to vl-1) { let op1 = match suffix { \"vv\" => getvelem(vs1, SEW, i), \"vx\" => sextortruncatetosew(X(vs1)) }; let op2 = getvelem(vs2, SEW, i); setvelem(vd, EEW=SEW, i, ~op1 & op2); } RETIRESUCCESS }", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vandn.[vv,vx]", + "line_range": [ + 1812, + 1825 + ] + }, + { + "text": "Synopsis:: Vector Reverse Bits in Elements", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vbrev.v", + "line_range": [ + 1838, + 1839 + ] + }, + { + "text": "Mnemonic:: vbrev.v vd, vs2, vm", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vbrev.v", + "line_range": [ + 1841, + 1842 + ] + }, + { + "text": "Encoding (Vector):: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 'OP-V'}, {bits: 5, name: 'vd'}, {bits: 3, name: 'OPMVV'}, {bits: 5, name: '01010'}, {bits: 5, name: 'vs2'}, {bits: 1, name: 'vm'}, {bits: 6, name: '010010'}, ]} ....", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vbrev.v", + "line_range": [ + 1844, + 1856 + ] + }, + { + "text": "| |Register |Direction |Definition", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vbrev.v", + "line_range": [ + 1860, + 1865 + ] + }, + { + "text": "| Vs2 | input | Input elements | Vd | output | Elements with bits reversed |", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vbrev.v", + "line_range": [ + 1867, + 1869 + ] + }, + { + "text": "Description:: A bit reversal is performed on the bits of each element.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vbrev.v", + "line_range": [ + 1871, + 1872 + ] + }, + { + "text": "Operation:: [source,sail] -- function clause execute (VBREV(vs2)) = {", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vbrev.v", + "line_range": [ + 1874, + 1877 + ] + }, + { + "text": "foreach (i from vstart to vl-1) { let input = getvelem(vs2, SEW, i); let output : bits(SEW) = 0; foreach (i from 0 to SEW-1) let output[SEW-1-i] = input[i]; setvelem(vd, SEW, i, output) } RETIRESUCCESS } --", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vbrev.v", + "line_range": [ + 1879, + 1888 + ] + }, + { + "text": "Synopsis:: Vector Reverse Bits in Bytes", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vbrev8.v", + "line_range": [ + 1898, + 1899 + ] + }, + { + "text": "Mnemonic:: vbrev8.v vd, vs2, vm", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vbrev8.v", + "line_range": [ + 1901, + 1902 + ] + }, + { + "text": "Encoding (Vector):: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 'OP-V'}, {bits: 5, name: 'vd'}, {bits: 3, name: 'OPMVV'}, {bits: 5, name: '01000'}, {bits: 5, name: 'vs2'}, {bits: 1, name: 'vm'}, {bits: 6, name: '010010'}, ]} ....", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vbrev8.v", + "line_range": [ + 1904, + 1916 + ] + }, + { + "text": "| |Register |Direction |Definition", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vbrev8.v", + "line_range": [ + 1920, + 1925 + ] + }, + { + "text": "| Vs2 | input | Input elements | Vd | output | Elements with bit-reversed bytes |", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vbrev8.v", + "line_range": [ + 1927, + 1929 + ] + }, + { + "text": "Description:: A bit reversal is performed on the bits of each byte.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vbrev8.v", + "line_range": [ + 1931, + 1932 + ] + }, + { + "text": "Operation:: [source,sail] -- function clause execute (VBREV8(vs2)) = {", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vbrev8.v", + "line_range": [ + 1937, + 1940 + ] + }, + { + "text": "foreach (i from vstart to vl-1) { let input = getvelem(vs2, SEW, i); let output : bits(SEW) = 0; foreach (i from 0 to SEW-8 by 8) let output[i+7..i] = reversebitsinbyte(input[i+7..i]); setvelem(vd, SEW, i, output) } RETIRESUCCESS } --", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vbrev8.v", + "line_range": [ + 1942, + 1951 + ] + }, + { + "text": "Synopsis:: Vector Carry-less Multiply by vector or scalar - returning low half of product.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vclmul.[vv,vx]", + "line_range": [ + 1962, + 1963 + ] + }, + { + "text": "Mnemonic:: vclmul.vv vd, vs2, vs1, vm + vclmul.vx vd, vs2, rs1, vm", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vclmul.[vv,vx]", + "line_range": [ + 1965, + 1967 + ] + }, + { + "text": "Encoding (Vector-Vector):: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 'OP-V'}, {bits: 5, name: 'vd'}, {bits: 3, name: 'OPMVV'}, {bits: 5, name: 'vs1'}, {bits: 5, name: 'vs2'}, {bits: 1, name: 'vm'}, {bits: 6, name: '001100'}, ]} ....", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vclmul.[vv,vx]", + "line_range": [ + 1969, + 1981 + ] + }, + { + "text": "Encoding (Vector-Scalar):: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 'OP-V'}, {bits: 5, name: 'vd'}, {bits: 3, name: 'OPMVX'}, {bits: 5, name: 'rs1'}, {bits: 5, name: 'vs2'}, {bits: 1, name: 'vm'}, {bits: 6, name: '001100'}, ]} ....", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vclmul.[vv,vx]", + "line_range": [ + 1983, + 1997 + ] + }, + { + "text": "Reserved Encodings:: * `SEW` is any value other than 64", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vclmul.[vv,vx]", + "line_range": [ + 1983, + 1997 + ] + }, + { + "text": "| |Register |Direction |Definition", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vclmul.[vv,vx]", + "line_range": [ + 2001, + 2006 + ] + }, + { + "text": "| Vs1/Rs1 | input | multiplier | Vs2 | input | multiplicand | Vd | output | carry-less product low |", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vclmul.[vv,vx]", + "line_range": [ + 2008, + 2011 + ] + }, + { + "text": "Description:: Produces the low half of 128-bit carry-less product.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vclmul.[vv,vx]", + "line_range": [ + 2013, + 2014 + ] + }, + { + "text": "Each 64-bit element in the `vs2` vector register is carry-less multiplied by either each 64-bit element in `vs1` (vector-vector), or the 64-bit value from integer register `rs1` (vector-scalar).", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vclmul.[vv,vx]", + "line_range": [ + 2016, + 2019 + ] + }, + { + "text": "The result is the least significant 64 bits of the carry-less product.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vclmul.[vv,vx]", + "line_range": [ + 2016, + 2019 + ] + }, + { + "text": "Operation:: [source,sail] --", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vclmul.[vv,vx]", + "line_range": [ + 2021, + 2023 + ] + }, + { + "text": "function clause execute (VCLMUL(vs2, vs1, vd, suffix)) = {", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vclmul.[vv,vx]", + "line_range": [ + 2025, + 2025 + ] + }, + { + "text": "foreach (i from vstart to vl-1) { let op1 : bits (64) = if suffix \"vv\" then getvelem(vs1,i) else zextortruncatetosew(X(vs1)); let op2 : bits (64) = getvelem(vs2,i); let product : bits (64) = clmul(op1,op2,SEW); setvelem(vd, i, product); } RETIRESUCCESS }", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vclmul.[vv,vx]", + "line_range": [ + 2027, + 2035 + ] + }, + { + "text": "function clmul(x, y, width) = { let result : bits(width) = zeros(); foreach (i from 0 to (width - 1)) { if y[i] 1 then result = result ^ (x << i); } result } --", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vclmul.[vv,vx]", + "line_range": [ + 2037, + 2044 + ] + }, + { + "text": "Synopsis:: Vector Carry-less Multiply by vector or scalar - returning high half of product.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vclmulh.[vv,vx]", + "line_range": [ + 2055, + 2056 + ] + }, + { + "text": "Mnemonic:: vclmulh.vv vd, vs2, vs1, vm + vclmulh.vx vd, vs2, rs1, vm", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vclmulh.[vv,vx]", + "line_range": [ + 2058, + 2060 + ] + }, + { + "text": "Encoding (Vector-Vector):: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 'OP-V'}, {bits: 5, name: 'vd'}, {bits: 3, name: 'OPMVV'}, {bits: 5, name: 'vs1'}, {bits: 5, name: 'vs2'}, {bits: 1, name: 'vm'}, {bits: 6, name: '001101'}, ]} ....", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vclmulh.[vv,vx]", + "line_range": [ + 2062, + 2074 + ] + }, + { + "text": "Encoding (Vector-Scalar):: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 'OP-V'}, {bits: 5, name: 'vd'}, {bits: 3, name: 'OPMVX'}, {bits: 5, name: 'rs1'}, {bits: 5, name: 'vs2'}, {bits: 1, name: 'vm'}, {bits: 6, name: '001101'}, ]} ....", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vclmulh.[vv,vx]", + "line_range": [ + 2076, + 2090 + ] + }, + { + "text": "Reserved Encodings:: * `SEW` is any value other than 64", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vclmulh.[vv,vx]", + "line_range": [ + 2076, + 2090 + ] + }, + { + "text": "| |Register |Direction |Definition", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vclmulh.[vv,vx]", + "line_range": [ + 2094, + 2099 + ] + }, + { + "text": "| Vs1 | input | multiplier | Vs2 | input | multiplicand | Vd | output | carry-less product high |", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vclmulh.[vv,vx]", + "line_range": [ + 2101, + 2104 + ] + }, + { + "text": "Description:: Produces the high half of 128-bit carry-less product.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vclmulh.[vv,vx]", + "line_range": [ + 2106, + 2107 + ] + }, + { + "text": "Each 64-bit element in the `vs2` vector register is carry-less multiplied by either each 64-bit element in `vs1` (vector-vector), or the 64-bit value from integer register `rs1` (vector-scalar).", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vclmulh.[vv,vx]", + "line_range": [ + 2109, + 2112 + ] + }, + { + "text": "The result is the most significant 64 bits of the carry-less product.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vclmulh.[vv,vx]", + "line_range": [ + 2109, + 2112 + ] + }, + { + "text": "Operation:: [source,sail] -- function clause execute (VCLMULH(vs2, vs1, vd, suffix)) = {", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vclmulh.[vv,vx]", + "line_range": [ + 2117, + 2120 + ] + }, + { + "text": "foreach (i from vstart to vl-1) { let op1 : bits (64) = if suffix \"vv\" then getvelem(vs1,i) else zextortruncatetosew(X(vs1)); let op2 : bits (64) = getvelem(vs2, i); let product : bits (64) = clmulh(op1, op2, SEW); setvelem(vd, i, product); } RETIRESUCCESS }", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vclmulh.[vv,vx]", + "line_range": [ + 2122, + 2130 + ] + }, + { + "text": "function clmulh(x, y, width) = { let result : bits(width) = 0; foreach (i from 1 to (width - 1)) { if y[i] 1 then result = result ^ (x >> (width - i)); } result }", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vclmulh.[vv,vx]", + "line_range": [ + 2132, + 2138 + ] + }, + { + "text": "Synopsis:: Vector Count Leading Zeros", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vclz.v", + "line_range": [ + 2150, + 2151 + ] + }, + { + "text": "Mnemonic:: vclz.v vd, vs2, vm", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vclz.v", + "line_range": [ + 2153, + 2154 + ] + }, + { + "text": "Encoding (Vector):: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 'OP-V'}, {bits: 5, name: 'vd'}, {bits: 3, name: 'OPMVV'}, {bits: 5, name: '01100'}, {bits: 5, name: 'vs2'}, {bits: 1, name: 'vm'}, {bits: 6, name: '010010'}, ]} ....", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vclz.v", + "line_range": [ + 2156, + 2168 + ] + }, + { + "text": "| |Register |Direction |Definition", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vclz.v", + "line_range": [ + 2172, + 2177 + ] + }, + { + "text": "| Vs2 | input | Input elements | Vd | output | Count of leading zero bits |", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vclz.v", + "line_range": [ + 2179, + 2181 + ] + }, + { + "text": "Description:: A leading zero count is performed on each element.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vclz.v", + "line_range": [ + 2183, + 2184 + ] + }, + { + "text": "The result for zero-valued inputs is the value SEW.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vclz.v", + "line_range": [ + 2186, + 2186 + ] + }, + { + "text": "Operation:: [source,sail] -- function clause execute (VCLZ(vs2)) = {", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vclz.v", + "line_range": [ + 2188, + 2191 + ] + }, + { + "text": "foreach (i from vstart to vl-1) { let input = getvelem(vs2, SEW, i); for (j = (SEW - 1); j >= 0; j--) if [input[j]] 0b1 then break; setvelem(vd, SEW, i, SEW - 1 - j) } RETIRESUCCESS } --", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vclz.v", + "line_range": [ + 2193, + 2201 + ] + }, + { + "text": "Synopsis:: Count the number of bits set in each element", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vcpop.v", + "line_range": [ + 2209, + 2210 + ] + }, + { + "text": "Mnemonic:: vcpop.v vd, vs2, vm", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vcpop.v", + "line_range": [ + 2212, + 2213 + ] + }, + { + "text": "Encoding (Vector):: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 'OP-V'}, {bits: 5, name: 'vd'}, {bits: 3, name: 'OPMVV'}, {bits: 5, name: '01110'}, {bits: 5, name: 'vs2'}, {bits: 1, name: 'vm'}, {bits: 6, name: '010010'}, ]} ....", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vcpop.v", + "line_range": [ + 2215, + 2227 + ] + }, + { + "text": "| |Register |Direction |Definition", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vcpop.v", + "line_range": [ + 2231, + 2236 + ] + }, + { + "text": "| Vs2 | input | Input elements | Vd | output | Count of bits set |", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vcpop.v", + "line_range": [ + 2238, + 2240 + ] + }, + { + "text": "Description:: A population count is performed on each element.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vcpop.v", + "line_range": [ + 2242, + 2243 + ] + }, + { + "text": "Operation:: [source,sail] -- function clause execute (VCPOP(vs2)) = {", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vcpop.v", + "line_range": [ + 2245, + 2248 + ] + }, + { + "text": "foreach (i from vstart to vl-1) { let input = getvelem(vs2, SEW, i); let output : bits(SEW) = 0; for (j = 0; j < SEW; j++) output = output + input[j]; setvelem(vd, SEW, i, output) } RETIRESUCCESS } --", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vcpop.v", + "line_range": [ + 2250, + 2259 + ] + }, + { + "text": "Synopsis:: Vector Count Trailing Zeros", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vctz.v", + "line_range": [ + 2267, + 2268 + ] + }, + { + "text": "Mnemonic:: vctz.v vd, vs2, vm", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vctz.v", + "line_range": [ + 2270, + 2271 + ] + }, + { + "text": "Encoding (Vector):: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 'OP-V'}, {bits: 5, name: 'vd'}, {bits: 3, name: 'OPMVV'}, {bits: 5, name: '01101'}, {bits: 5, name: 'vs2'}, {bits: 1, name: 'vm'}, {bits: 6, name: '010010'}, ]} ....", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vctz.v", + "line_range": [ + 2273, + 2285 + ] + }, + { + "text": "| |Register |Direction |Definition", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vctz.v", + "line_range": [ + 2289, + 2294 + ] + }, + { + "text": "| Vs2 | input | Input elements | Vd | output | Count of trailing zero bits |", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vctz.v", + "line_range": [ + 2296, + 2298 + ] + }, + { + "text": "Description:: A trailing zero count is performed on each element.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vctz.v", + "line_range": [ + 2300, + 2301 + ] + }, + { + "text": "Operation:: [source,sail] -- function clause execute (VCTZ(vs2)) = {", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vctz.v", + "line_range": [ + 2305, + 2308 + ] + }, + { + "text": "foreach (i from vstart to vl-1) { let input = getvelem(vs2, SEW, i); for (j = 0; j < SEW; j++) if [input[j]] 0b1 then break; setvelem(vd, SEW, i, j) } RETIRESUCCESS } --", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vctz.v", + "line_range": [ + 2310, + 2318 + ] + }, + { + "text": "Synopsis:: Vector Add-Multiply over GHASH Galois-Field", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vghsh.vv", + "line_range": [ + 2328, + 2329 + ] + }, + { + "text": "Mnemonic:: vghsh.vv vd, vs2, vs1", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vghsh.vv", + "line_range": [ + 2331, + 2332 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 'OP-VE'}, {bits: 5, name: 'vd'}, {bits: 3, name: 'OPMVV'}, {bits: 5, name: 'vs1'}, {bits: 5, name: 'vs2'}, {bits: 1, name: '1'}, {bits: 6, name: '101100'}, ]} ....", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vghsh.vv", + "line_range": [ + 2334, + 2348 + ] + }, + { + "text": "Reserved Encodings:: * `SEW` is any value other than 32", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vghsh.vv", + "line_range": [ + 2334, + 2348 + ] + }, + { + "text": "| |Register |Direction |EGW |EGS |SEW |Definition", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vghsh.vv", + "line_range": [ + 2352, + 2360 + ] + }, + { + "text": "| Vd | input | 128 | 4 | 32 | Partial hash (Y~i~) | Vs1 | input | 128 | 4 | 32 | Cipher text (X~i~) | Vs2 | input | 128 | 4 | 32 | Hash Subkey (H) | Vd | output | 128 | 4 | 32 | Partial-hash (Y~i+1~) |", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vghsh.vv", + "line_range": [ + 2362, + 2366 + ] + }, + { + "text": "Description:: A single \"iteration\" of the GHASH~H~ algorithm is performed.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vghsh.vv", + "line_range": [ + 2368, + 2369 + ] + }, + { + "text": "This instruction treats all of the inputs and outputs as 128-bit polynomials and performs operations over GF[2].", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vghsh.vv", + "line_range": [ + 2371, + 2375 + ] + }, + { + "text": "It produces the next partial hash (Y~i+1~) by adding the current partial hash (Y~i~) to the cipher text block (X~i~) and then multiplying (over GF(2^128^)) this sum by the Hash Subkey (H).", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vghsh.vv", + "line_range": [ + 2371, + 2375 + ] + }, + { + "text": "The multiplication over GF(2^128^) is a carry-less multiply of two 128-bit polynomials modulo GHASH's irreducible polynomial (x^128^ + x^7^ + x^2^ + x + 1).", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vghsh.vv", + "line_range": [ + 2377, + 2378 + ] + }, + { + "text": "The operation can be compactly defined as // Y~i+1~ = (Y~i~ {interpunct} H) ^ X~i~ Y~i+1~ = ((Y~i~ ^ X~i~) {interpunct} H)", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vghsh.vv", + "line_range": [ + 2380, + 2382 + ] + }, + { + "text": "The NIST specification (see ) orders the coefficients from left to right x~0~x~1~x~2~...x~127~ for a polynomial x~0~ + x~1~u +x~2~ u^2^ + ... + x~127~u^127^.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vghsh.vv", + "line_range": [ + 2384, + 2389 + ] + }, + { + "text": "This can be viewed as a collection of byte elements in memory with the byte containing the lowest coefficients (i.e., 0,1,2,3,4,5,6,7) residing at the lowest memory address.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vghsh.vv", + "line_range": [ + 2384, + 2389 + ] + }, + { + "text": "Since the bits in the bytes are reversed, this instruction internally performs bit swaps within bytes to put the bits in the standard ordering (e.g., 7,6,5,4,3,2,1,0).", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vghsh.vv", + "line_range": [ + 2384, + 2389 + ] + }, + { + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated upon.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vghsh.vv", + "line_range": [ + 2391, + 2392 + ] + }, + { + "text": "Operation:: [source,pseudocode] -- function clause execute (VGHSH(vs2, vs1, vd)) = { // operands are input with bits reversed in each byte if(LMUL*VLEN < EGW) then { handleillegal(); // illegal-instruction exception RETIREFAIL } else {", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vghsh.vv", + "line_range": [ + 2394, + 2402 + ] + }, + { + "text": "eglen = (vl/EGS) egstart = (vstart/EGS)", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vghsh.vv", + "line_range": [ + 2404, + 2405 + ] + }, + { + "text": "foreach (i from egstart to eglen-1) { let Y = getvelem(vd,EGW=128,i); // current partial-hash let X = getvelem(vs1,EGW=128,i); // block cipher output let H = brev8(getvelem(vs2,EGW=128,i)); // Hash subkey", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vghsh.vv", + "line_range": [ + 2407, + 2410 + ] + }, + { + "text": "for (int bit = 0; bit < 128; bit++) { if bittobool(S[bit]) Z ^= H", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vghsh.vv", + "line_range": [ + 2416, + 2418 + ] + }, + { + "text": "bool reduce = bittobool(H[127]); H = H << 1; // left shift H by 1 if (reduce) H ^= 0x87; // Reduce using x^7 + x^2 + x^1 + 1 polynomial }", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vghsh.vv", + "line_range": [ + 2420, + 2424 + ] + }, + { + "text": "let result = brev8(Z); // bit reverse bytes to get back to GCM standard ordering setvelem(vd, EGW=128, i, result); } RETIRESUCCESS } } --", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vghsh.vv", + "line_range": [ + 2426, + 2432 + ] + }, + { + "text": "Synopsis:: Vector Multiply over GHASH Galois-Field", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vgmul.vv", + "line_range": [ + 2442, + 2443 + ] + }, + { + "text": "Mnemonic:: vgmul.vv vd, vs2", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vgmul.vv", + "line_range": [ + 2445, + 2446 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 'OP-VE'}, {bits: 5, name: 'vd'}, {bits: 3, name: 'OPMVV'}, {bits: 5, name: '10001'}, {bits: 5, name: 'vs2'}, {bits: 1, name: '1'}, {bits: 6, name: '101000'}, ]} ....", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vgmul.vv", + "line_range": [ + 2448, + 2462 + ] + }, + { + "text": "Reserved Encodings:: * `SEW` is any value other than 32", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vgmul.vv", + "line_range": [ + 2448, + 2462 + ] + }, + { + "text": "| |Register |Direction |EGW |EGS |SEW |Definition", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vgmul.vv", + "line_range": [ + 2466, + 2474 + ] + }, + { + "text": "| Vd | input | 128 | 4 | 32 | Multiplier | Vs2 | input | 128 | 4 | 32 | Multiplicand | Vd | output | 128 | 4 | 32 | Product |", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vgmul.vv", + "line_range": [ + 2476, + 2479 + ] + }, + { + "text": "Description:: A GHASH~H~ multiply is performed.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vgmul.vv", + "line_range": [ + 2481, + 2482 + ] + }, + { + "text": "This instruction treats all of the inputs and outputs as 128-bit polynomials and performs operations over GF[2].", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vgmul.vv", + "line_range": [ + 2484, + 2486 + ] + }, + { + "text": "It produces the product over GF(2^128^) of the two 128-bit inputs.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vgmul.vv", + "line_range": [ + 2484, + 2486 + ] + }, + { + "text": "The multiplication over GF(2^128^) is a carry-less multiply of two 128-bit polynomials modulo GHASH's irreducible polynomial (x^128^ + x^7^ + x^2^ + x + 1).", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vgmul.vv", + "line_range": [ + 2488, + 2489 + ] + }, + { + "text": "The NIST specification (see ) orders the coefficients from left to right x~0~x~1~x~2~...x~127~ for a polynomial x~0~ + x~1~u +x~2~ u^2^ + ... + x~127~u^127^.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vgmul.vv", + "line_range": [ + 2491, + 2496 + ] + }, + { + "text": "This can be viewed as a collection of byte elements in memory with the byte containing the lowest coefficients (i.e., 0,1,2,3,4,5,6,7) residing at the lowest memory address.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vgmul.vv", + "line_range": [ + 2491, + 2496 + ] + }, + { + "text": "Since the bits in the bytes are reversed, This instruction internally performs bit swaps within bytes to put the bits in the standard ordering (e.g., 7,6,5,4,3,2,1,0).", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vgmul.vv", + "line_range": [ + 2491, + 2496 + ] + }, + { + "text": "This instruction must always be implemented such that its execution latency does not depend on the data being operated upon.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vgmul.vv", + "line_range": [ + 2498, + 2499 + ] + }, + { + "text": "Operation:: [source,pseudocode] -- function clause execute (VGMUL(vs2, vs1, vd)) = { // operands are input with bits reversed in each byte if(LMUL*VLEN < EGW) then { handleillegal(); // illegal-instruction exception RETIREFAIL } else {", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vgmul.vv", + "line_range": [ + 2501, + 2509 + ] + }, + { + "text": "eglen = (vl/EGS) egstart = (vstart/EGS)", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vgmul.vv", + "line_range": [ + 2511, + 2512 + ] + }, + { + "text": "foreach (i from egstart to eglen-1) { let Y = brev8(getvelem(vd,EGW=128,i)); // Multiplier let H = brev8(getvelem(vs2,EGW=128,i)); // Multiplicand let Z : bits(128) = 0;", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vgmul.vv", + "line_range": [ + 2514, + 2517 + ] + }, + { + "text": "for (int bit = 0; bit < 128; bit++) { if bittobool(Y[bit]) Z ^= H", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vgmul.vv", + "line_range": [ + 2519, + 2521 + ] + }, + { + "text": "bool reduce = bittobool(H[127]); H = H << 1; // left shift H by 1 if (reduce) H ^= 0x87; // Reduce using x^7 + x^2 + x^1 + 1 polynomial }", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vgmul.vv", + "line_range": [ + 2523, + 2527 + ] + }, + { + "text": "let result = brev8(Z); setvelem(vd, EGW=128, i, result); } RETIRESUCCESS } } --", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vgmul.vv", + "line_range": [ + 2529, + 2535 + ] + }, + { + "text": "Synopsis:: Vector Reverse Bytes", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vrev8.v", + "line_range": [ + 2546, + 2547 + ] + }, + { + "text": "Mnemonic:: vrev8.v vd, vs2, vm", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vrev8.v", + "line_range": [ + 2549, + 2550 + ] + }, + { + "text": "Encoding (Vector):: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 'OP-V'}, {bits: 5, name: 'vd'}, {bits: 3, name: 'OPMVV'}, {bits: 5, name: '01001'}, {bits: 5, name: 'vs2'}, {bits: 1, name: 'vm'}, {bits: 6, name: '010010'}, ]} ....", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vrev8.v", + "line_range": [ + 2552, + 2564 + ] + }, + { + "text": "| |Register |Direction |Definition", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vrev8.v", + "line_range": [ + 2568, + 2573 + ] + }, + { + "text": "| Vs2 | input | Input elements | Vd | output | Byte-reversed elements |", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vrev8.v", + "line_range": [ + 2575, + 2577 + ] + }, + { + "text": "Description:: A byte reversal is performed on each element of `vs2`, effectively performing an endian swap.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vrev8.v", + "line_range": [ + 2579, + 2580 + ] + }, + { + "text": "Operation:: [source,sail] -- function clause execute (VREV8(vs2)) = { foreach (i from vstart to vl-1) { input = getvelem(vs2, SEW, i); let output : SEW = 0; let j = SEW - 1; foreach (k from 0 to (SEW - 8) by 8) { output[k..(k + 7)] = input[(j - 7)..j]; j = j - 8; setvelem(vd, SEW, i, output) } RETIRESUCCESS } --", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vrev8.v", + "line_range": [ + 2585, + 2600 + ] + }, + { + "text": "Synopsis:: Vector rotate left by vector/scalar.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vrol.[vv,vx]", + "line_range": [ + 2611, + 2612 + ] + }, + { + "text": "Mnemonic:: vrol.vv vd, vs2, vs1, vm + vrol.vx vd, vs2, rs1, vm +", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vrol.[vv,vx]", + "line_range": [ + 2614, + 2616 + ] + }, + { + "text": "Encoding (Vector-Vector):: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 'OP-V'}, {bits: 5, name: 'vd'}, {bits: 3, name: 'OPIVV'}, {bits: 5, name: 'vs1'}, {bits: 5, name: 'vs2'}, {bits: 1, name: 'vm'}, {bits: 6, name: '010101'}, ]} ....", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vrol.[vv,vx]", + "line_range": [ + 2618, + 2630 + ] + }, + { + "text": "Encoding (Vector-Scalar):: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 'OP-V'}, {bits: 5, name: 'vd'}, {bits: 3, name: 'OPIVX'}, {bits: 5, name: 'rs1'}, {bits: 5, name: 'vs2'}, {bits: 1, name: 'vm'}, {bits: 6, name: '010101'}, ]} ....", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vrol.[vv,vx]", + "line_range": [ + 2632, + 2644 + ] + }, + { + "text": "| |Register |Direction |Definition", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vrol.[vv,vx]", + "line_range": [ + 2648, + 2653 + ] + }, + { + "text": "| Vs1 | input | Rotate amount | Vs2 | input | Data | Vd | output | Rotated data |", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vrol.[vv,vx]", + "line_range": [ + 2655, + 2658 + ] + }, + { + "text": "| |Register |Direction |Definition", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vrol.[vv,vx]", + "line_range": [ + 2662, + 2667 + ] + }, + { + "text": "| Rs1 | input | Rotate amount | Vs2 | input | Data | Vd | output | Rotated data |", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vrol.[vv,vx]", + "line_range": [ + 2669, + 2672 + ] + }, + { + "text": "Description:: A bitwise left rotation is performed on each element of `vs2`", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vrol.[vv,vx]", + "line_range": [ + 2674, + 2675 + ] + }, + { + "text": "The elements in `vs2` are rotated left by the rotate amount specified by either the corresponding elements of `vs1` (vector-vector), or integer register `rs1` (vector-scalar).", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vrol.[vv,vx]", + "line_range": [ + 2677, + 2681 + ] + }, + { + "text": "Only the low log2(`SEW`) bits of the rotate-amount value are used, all other bits are ignored.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vrol.[vv,vx]", + "line_range": [ + 2677, + 2681 + ] + }, + { + "text": "Operation:: [source,sail] -- function clause execute (VROLVV(vs2, vs1, vd)) = { foreach (i from vstart to vl - 1) { setvelem(vd, EEW=SEW, i, getvelem(vs2, i) <<< (getvelem(vs1, i) & (SEW-1)) ) } RETIRESUCCESS }", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vrol.[vv,vx]", + "line_range": [ + 2686, + 2696 + ] + }, + { + "text": "function clause execute (VROLVX(vs2, rs1, vd)) = { foreach (i from vstart to vl - 1) { setvelem(vd, EEW=SEW, i, getvelem(vs2, i) <<< (X(rs1) & (SEW-1)) ) } RETIRESUCCESS }", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vrol.[vv,vx]", + "line_range": [ + 2698, + 2705 + ] + }, + { + "text": "Synopsis:: Vector rotate right by vector/scalar/immediate.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vror.[vv,vx,vi]", + "line_range": [ + 2718, + 2719 + ] + }, + { + "text": "Mnemonic:: vror.vv vd, vs2, vs1, vm + vror.vx vd, vs2, rs1, vm + vror.vi vd, vs2, uimm, vm", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vror.[vv,vx,vi]", + "line_range": [ + 2721, + 2724 + ] + }, + { + "text": "Encoding (Vector-Vector):: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 'OP-V'}, {bits: 5, name: 'vd'}, {bits: 3, name: 'OPIVV'}, {bits: 5, name: 'vs1'}, {bits: 5, name: 'vs2'}, {bits: 1, name: 'vm'}, {bits: 6, name: '010100'}, ]} ....", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vror.[vv,vx,vi]", + "line_range": [ + 2726, + 2738 + ] + }, + { + "text": "Encoding (Vector-Scalar):: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 'OP-V'}, {bits: 5, name: 'vd'}, {bits: 3, name: 'OPIVX'}, {bits: 5, name: 'rs1'}, {bits: 5, name: 'vs2'}, {bits: 1, name: 'vm'}, {bits: 6, name: '010100'}, ]} ....", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vror.[vv,vx,vi]", + "line_range": [ + 2740, + 2752 + ] + }, + { + "text": "Encoding (Vector-Immediate):: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 'OP-V'}, {bits: 5, name: 'vd'}, {bits: 3, name: 'OPIVI'}, {bits: 5, name: 'uimm[4:0]'}, {bits: 5, name: 'vs2'}, {bits: 1, name: 'vm'}, {bits: 1, name: 'i5'}, {bits: 5, name: '01010'}, ]} ....", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vror.[vv,vx,vi]", + "line_range": [ + 2754, + 2767 + ] + }, + { + "text": "| |Register |Direction |Definition", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vror.[vv,vx,vi]", + "line_range": [ + 2771, + 2776 + ] + }, + { + "text": "| Vs1 | input | Rotate amount | Vs2 | input | Data | Vd | output | Rotated data |", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vror.[vv,vx,vi]", + "line_range": [ + 2778, + 2781 + ] + }, + { + "text": "Vector-Scalar/Immediate Arguments::", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vror.[vv,vx,vi]", + "line_range": [ + 2783, + 2783 + ] + }, + { + "text": "| |Register |Direction |Definition", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vror.[vv,vx,vi]", + "line_range": [ + 2785, + 2790 + ] + }, + { + "text": "| Rs1/imm | input | Rotate amount | Vs2 | input | Data | Vd | output | Rotated data |", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vror.[vv,vx,vi]", + "line_range": [ + 2792, + 2795 + ] + }, + { + "text": "Description:: A bitwise right rotation is performed on each element of `vs2`.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vror.[vv,vx,vi]", + "line_range": [ + 2797, + 2798 + ] + }, + { + "text": "The elements in `vs2` are rotated right by the rotate amount specified by either the corresponding elements of `vs1` (vector-vector), integer register `rs1` (vector-scalar), or an immediate value (vector-immediate).", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vror.[vv,vx,vi]", + "line_range": [ + 2800, + 2804 + ] + }, + { + "text": "Only the low log2(`SEW`) bits of the rotate-amount value are used, all other bits are ignored.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vror.[vv,vx,vi]", + "line_range": [ + 2800, + 2804 + ] + }, + { + "text": "Operation:: [source,sail] -- function clause execute (VRORVV(vs2, vs1, vd)) = { foreach (i from vstart to vl - 1) { setvelem(vd, EEW=SEW, i, getvelem(vs2, i) >>> (getvelem(vs1, i) & (SEW-1)) ) } RETIRESUCCESS }", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vror.[vv,vx,vi]", + "line_range": [ + 2809, + 2819 + ] + }, + { + "text": "function clause execute (VRORVX(vs2, rs1, vd)) = { foreach (i from vstart to vl - 1) { setvelem(vd, EEW=SEW, i, getvelem(vs2, i) >>> (X(rs1) & (SEW-1)) ) } RETIRESUCCESS }", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vror.[vv,vx,vi]", + "line_range": [ + 2821, + 2828 + ] + }, + { + "text": "function clause execute (VRORVI(vs2, uimm[5:0], vd)) = { foreach (i from vstart to vl - 1) { setvelem(vd, EEW=SEW, i, getvelem(vs2, i) >>> (uimm[5:0] & (SEW-1)) ) } RETIRESUCCESS } --", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vror.[vv,vx,vi]", + "line_range": [ + 2830, + 2838 + ] + }, + { + "text": "Synopsis:: Vector SHA-2 two rounds of compression.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsha2c[hl].vv", + "line_range": [ + 2850, + 2851 + ] + }, + { + "text": "Mnemonic:: vsha2ch.vv vd, vs2, vs1 + vsha2cl.vv vd, vs2, vs1", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsha2c[hl].vv", + "line_range": [ + 2853, + 2855 + ] + }, + { + "text": "Encoding (Vector-Vector) High part:: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 'OP-VE'}, {bits: 5, name: 'vd'}, {bits: 3, name: 'OPMVV'}, {bits: 5, name: 'vs1'}, {bits: 5, name: 'vs2'}, {bits: 1, name: '1'}, {bits: 6, name: '101110'}, ]} ....", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsha2c[hl].vv", + "line_range": [ + 2857, + 2869 + ] + }, + { + "text": "Encoding (Vector-Vector) Low part:: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 'OP-VE'}, {bits: 5, name: 'vd'}, {bits: 3, name: 'OPMVV'}, {bits: 5, name: 'vs1'}, {bits: 5, name: 'vs2'}, {bits: 1, name: '1'}, {bits: 6, name: '101111'}, ]} ....", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsha2c[hl].vv", + "line_range": [ + 2871, + 2887 + ] + }, + { + "text": "Reserved Encodings:: * `zvknha`: `SEW` is any value other than 32 * `zvknhb`: `SEW` is any value other than 32 or 64 * The `vd` register group overlaps with either `vs1` or `vs2`", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsha2c[hl].vv", + "line_range": [ + 2871, + 2887 + ] + }, + { + "text": "| |Register |Direction |EGW |EGS |EEW |Definition", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsha2c[hl].vv", + "line_range": [ + 2891, + 2899 + ] + }, + { + "text": "| Vd | input | 4*SEW | 4 | SEW | current state {c, d, g, h} | Vs1 | input | 4*SEW | 4 | SEW | MessageSched plus constant[3:0] | Vs2 | input | 4*SEW | 4 | SEW | current state {a, b, e, f} | Vd | output | 4*SEW | 4 | SEW | next state {a, b, e, f} |", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsha2c[hl].vv", + "line_range": [ + 2901, + 2905 + ] + }, + { + "text": "Description:: - `SEW`=32: 2 rounds of SHA-256 compression are performed (`zvknha` and `zvknhb`) - `SEW`=64: 2 rounds of SHA-512 compression are performed (`zvknhb`)", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsha2c[hl].vv", + "line_range": [ + 2907, + 2909 + ] + }, + { + "text": "Two words of `vs1` are processed with the 8 words of current state held in `vd` and `vs2` to perform two rounds of hash computation producing four words of the next state.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsha2c[hl].vv", + "line_range": [ + 2911, + 2914 + ] + }, + { + "text": "[NOTE] .Note to software developers The NIST standard (see ) requires the final hash to be in big-endian byte ordering within SEW-sized words.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsha2c[hl].vv", + "line_range": [ + 2931, + 2938 + ] + }, + { + "text": "Since this instruction treats all words as little-endian, software needs to perform an endian swap on the final output of this instruction after all of the message blocks have been processed.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsha2c[hl].vv", + "line_range": [ + 2931, + 2938 + ] + }, + { + "text": "Operation:: [source,sail] -- function clause execute (VSHA2c(vs2, vs1, vd)) = { if(LMUL*VLEN < EGW) then { handleillegal(); // illegal-instruction exception RETIREFAIL } else {", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsha2c[hl].vv", + "line_range": [ + 2965, + 2972 + ] + }, + { + "text": "eglen = (vl/EGS) egstart = (vstart/EGS)", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsha2c[hl].vv", + "line_range": [ + 2974, + 2975 + ] + }, + { + "text": "foreach (i from egstart to eglen-1) { let {a @ b @ e @ f} : bits(4*SEW) = getvelem(vs2, 4*SEW, i); let {c @ d @ g @ h} : bits(4*SEW) = getvelem(vd, 4*SEW, i); let MessageSchedPlusC[3:0] : bits(4*SEW) = getvelem(vs1, 4*SEW, i); let {W1, W0} VSHA2cl ? MessageSchedPlusC[1:0] : MessageSchedPlusC[3:2]; // l vs h difference is the words selected", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsha2c[hl].vv", + "line_range": [ + 2977, + 2981 + ] + }, + { + "text": "let T1 : bits(SEW) = h + sum1(e) + ch(e,f,g) + W0; let T2 : bits(SEW) = sum0(a) + maj(a,b,c); h = g; g = f; f = e; e = d + T1; d = c; c = b; b = a; a = T1 + T2;", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsha2c[hl].vv", + "line_range": [ + 2983, + 2992 + ] + }, + { + "text": "T1 = h + sum1(e) + ch(e,f,g) + W1; T2 = sum0(a) + maj(a,b,c); h = g; g = f; f = e; e = d + T1; d = c; c = b; b = a; a = T1 + T2; setvelem(vd, 4*SEW, i, {a @ b @ e @ f}); } RETIRESUCCESS } }", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsha2c[hl].vv", + "line_range": [ + 2994, + 3008 + ] + }, + { + "text": "function sum0(x) = { match SEW { 32 => rotr(x,2) XOR rotr(x,13) XOR rotr(x,22), 64 => rotr(x,28) XOR rotr(x,34) XOR rotr(x,39) } }", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsha2c[hl].vv", + "line_range": [ + 3010, + 3015 + ] + }, + { + "text": "function sum1(x) = { match SEW { 32 => rotr(x,6) XOR rotr(x,11) XOR rotr(x,25), 64 => rotr(x,14) XOR rotr(x,18) XOR rotr(x,41) } }", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsha2c[hl].vv", + "line_range": [ + 3017, + 3022 + ] + }, + { + "text": "function ch(x, y, z) = ((x & y) ^ ((~x) & z))", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsha2c[hl].vv", + "line_range": [ + 3024, + 3024 + ] + }, + { + "text": "function maj(x, y, z) = ((x & y) ^ (x & z) ^ (y & z))", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsha2c[hl].vv", + "line_range": [ + 3026, + 3026 + ] + }, + { + "text": "function ROTR(x,n) = (x >> n) | (x << SEW - n)", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsha2c[hl].vv", + "line_range": [ + 3028, + 3028 + ] + }, + { + "text": "Synopsis:: Vector SHA-2 message schedule.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsha2ms.vv", + "line_range": [ + 3044, + 3045 + ] + }, + { + "text": "Mnemonic:: vsha2ms.vv vd, vs2, vs1", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsha2ms.vv", + "line_range": [ + 3047, + 3048 + ] + }, + { + "text": "Encoding (Vector-Vector):: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 'OP-VE'}, {bits: 5, name: 'vd'}, {bits: 3, name: 'OPMVV'}, {bits: 5, name: 'vs1'}, {bits: 5, name: 'vs2'}, {bits: 1, name: '1'}, {bits: 6, name: '101101'}, ]} ....", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsha2ms.vv", + "line_range": [ + 3050, + 3067 + ] + }, + { + "text": "Reserved Encodings:: * `zvknha`: `SEW` is any value other than 32 * `zvknhb`: `SEW` is any value other than 32 or 64 * The `vd` register group overlaps with either `vs1` or `vs2` Arguments::", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsha2ms.vv", + "line_range": [ + 3050, + 3067 + ] + }, + { + "text": "| |Register |Direction |EGW |EGS |EEW |Definition", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsha2ms.vv", + "line_range": [ + 3069, + 3077 + ] + }, + { + "text": "| Vd | input | 4*SEW | 4 | SEW | Message words {W[3], W[2], W[1], W[0]} | Vs2 | input | 4*SEW | 4 | SEW | Message words {W[11], W[10], W[9], W[4]} | Vs1 | input | 4*SEW | 4 | SEW | Message words {W[15], W[14], -, W[12]} | Vd | output | 4*SEW | 4 | SEW | Message words {W[19], W[18], W[17], W[16]} |", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsha2ms.vv", + "line_range": [ + 3079, + 3083 + ] + }, + { + "text": "Description:: - `SEW`=32: Four rounds of SHA-256 message schedule expansion are performed (`zvknha` and `zvknhb`) - `SEW`=64: Four rounds of SHA-512 message schedule expansion are performed (`zvknhb`)", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsha2ms.vv", + "line_range": [ + 3085, + 3087 + ] + }, + { + "text": "Eleven of the last 16 `SEW`-sized message-schedule words from `vd` (oldest), `vs2`, and `vs1` (most recent) are processed to produce the next 4 message-schedule words.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsha2ms.vv", + "line_range": [ + 3089, + 3091 + ] + }, + { + "text": "[NOTE] .Note to software developers The first 16 SEW-sized words of the message schedule come from the message block in big-endian byte order.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsha2ms.vv", + "line_range": [ + 3093, + 3098 + ] + }, + { + "text": "Since this instruction treats all words as little endian, software is required to endian swap these words.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsha2ms.vv", + "line_range": [ + 3093, + 3098 + ] + }, + { + "text": "All of the subsequent message schedule words are produced by this instruction and therefore do not require an endian swap.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsha2ms.vv", + "line_range": [ + 3100, + 3102 + ] + }, + { + "text": "[NOTE] .Note to software developers Software is required to pack the words into element groups as shown above in the arguments table.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsha2ms.vv", + "line_range": [ + 3104, + 3114 + ] + }, + { + "text": "The indices indicate the relate age with lower indices indicating older words. // [NOTE] // // W~13~ is not used by the instruction. //", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsha2ms.vv", + "line_range": [ + 3104, + 3114 + ] + }, + { + "text": "[NOTE] .Note to software developers The {W~11~, W~10~, W~9~, W~4~} element group can easily be formed by using a vector vmerge instruction with the appropriate mask (for example with `vl=4` and `4b0001` as the 4 mask bits)", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsha2ms.vv", + "line_range": [ + 3134, + 3139 + ] + }, + { + "text": "`vmerge.vvm {W~11~, W~10~, W~9~, W~4~}, {W~11~, W~10~, W~9~, W~8~}, {W~7~, W~6~, W~5~, W~4~}, V0`", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsha2ms.vv", + "line_range": [ + 3141, + 3142 + ] + }, + { + "text": "Operation:: [source,sail] -- function clause execute (VSHA2ms(vs2, vs1, vd)) = { // SEW32 = SHA-256 // SEW64 = SHA-512 if(LMUL*VLEN < EGW) then { handleillegal(); // illegal-instruction exception RETIREFAIL } else {", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsha2ms.vv", + "line_range": [ + 3165, + 3174 + ] + }, + { + "text": "eglen = (vl/EGS) egstart = (vstart/EGS)", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsha2ms.vv", + "line_range": [ + 3176, + 3177 + ] + }, + { + "text": "foreach (i from egstart to eglen-1) { {W[3] @ W[2] @ W[1] @ W[0]} : bits(EGW) = getvelem(vd, EGW, i); {W[11] @ W[10] @ W[9] @ W[4]} : bits(EGW) = getvelem(vs2, EGW, i); {W[15] @ W[14] @ W[13] @ W[12]} : bits(EGW) = getvelem(vs1, EGW, i);", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsha2ms.vv", + "line_range": [ + 3179, + 3182 + ] + }, + { + "text": "W[16] = sig1(W[14]) + W[9] + sig0(W[1]) + W[0]; W[17] = sig1(W[15]) + W[10] + sig0(W[2]) + W[1]; W[18] = sig1(W[16]) + W[11] + sig0(W[3]) + W[2]; W[19] = sig1(W[17]) + W[12] + sig0(W[4]) + W[3];", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsha2ms.vv", + "line_range": [ + 3184, + 3187 + ] + }, + { + "text": "setvelem(vd, EGW, i, {W[19] @ W[18] @ W[17] @ W[16]}); } RETIRESUCCESS } }", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsha2ms.vv", + "line_range": [ + 3189, + 3193 + ] + }, + { + "text": "function sig0(x) = { match SEW { 32 => (ROTR(x,7) XOR ROTR(x,18) XOR SHR(x,3)), 64 => (ROTR(x,1) XOR ROTR(x,8) XOR SHR(x,7))); } }", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsha2ms.vv", + "line_range": [ + 3195, + 3200 + ] + }, + { + "text": "function sig1(x) = { match SEW { 32 => (ROTR(x,17) XOR ROTR(x,19) XOR SHR(x,10), 64 => ROTR(x,19) XOR ROTR(x,61) XOR SHR(x,6)); } }", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsha2ms.vv", + "line_range": [ + 3202, + 3207 + ] + }, + { + "text": "function ROTR(x,n) = (x >> n) | (x n", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsha2ms.vv", + "line_range": [ + 3209, + 3210 + ] + }, + { + "text": "Synopsis:: Vector SM3 Compression", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm3c.vi", + "line_range": [ + 3222, + 3223 + ] + }, + { + "text": "Mnemonic:: vsm3c.vi vd, vs2, uimm", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm3c.vi", + "line_range": [ + 3225, + 3226 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 'OP-VE'}, {bits: 5, name: 'vd'}, {bits: 3, name: 'OPMVV'}, {bits: 5, name: 'uimm'}, {bits: 5, name: 'vs2'}, {bits: 1, name: '1'}, {bits: 6, name: '101011'}, ]} ....", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm3c.vi", + "line_range": [ + 3228, + 3243 + ] + }, + { + "text": "Reserved Encodings:: * `SEW` is any value other than 32 * The `vd` register group overlaps with the `vs2` register group", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm3c.vi", + "line_range": [ + 3228, + 3243 + ] + }, + { + "text": "| |Register |Direction |EGW |EGS |EEW |Definition", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm3c.vi", + "line_range": [ + 3247, + 3255 + ] + }, + { + "text": "| Vd | input | 256 | 8 | 32 | Current state {H,G.F,E,D,C,B,A} | uimm | input | - | - | - | round number (rnds) | Vs2 | input | 256 | 8 | 32 | Message words {-,-,w[5],w[4],-,-,w[1],w[0]} | Vd | output | 256 | 8 | 32 | Next state {H,G.F,E,D,C,B,A} |", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm3c.vi", + "line_range": [ + 3257, + 3261 + ] + }, + { + "text": "Description:: Two rounds of SM3 compression are performed.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm3c.vi", + "line_range": [ + 3263, + 3264 + ] + }, + { + "text": "The current state of eight 32-bit words is read in as an element group from `vd`.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm3c.vi", + "line_range": [ + 3266, + 3273 + ] + }, + { + "text": "Eight 32-bit message words are read in as an element group from `vs2`, although only four of them are used.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm3c.vi", + "line_range": [ + 3266, + 3273 + ] + }, + { + "text": "All of the 32-bit input words are byte-swapped from big endian to little endian.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm3c.vi", + "line_range": [ + 3266, + 3273 + ] + }, + { + "text": "These inputs are processed somewhat differently based on the round group (as specified in rnds), and the next state is generated as an element group of eight 32-bit words.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm3c.vi", + "line_range": [ + 3266, + 3273 + ] + }, + { + "text": "The next state of eight 32-bit words are generated, swapped from little endian to big endian, and are returned in an eight-element group.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm3c.vi", + "line_range": [ + 3266, + 3273 + ] + }, + { + "text": "The round number is provided by the 5-bit `rnds` unsigned immediate.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm3c.vi", + "line_range": [ + 3275, + 3277 + ] + }, + { + "text": "Legal values are 0 - 31 and indicate which group of two rounds are being performed.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm3c.vi", + "line_range": [ + 3275, + 3277 + ] + }, + { + "text": "For example, if rnds=1, then rounds 2 and 3 are being performed.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm3c.vi", + "line_range": [ + 3275, + 3277 + ] + }, + { + "text": "Operation:: [source,sail] -- function clause execute (VSM3C(rnds, vs2, vd)) = { if(LMUL*VLEN < EGW) then { handleillegal(); // illegal-instruction exception RETIREFAIL } else {", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm3c.vi", + "line_range": [ + 3297, + 3304 + ] + }, + { + "text": "eglen = (vl/EGS) egstart = (vstart/EGS)", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm3c.vi", + "line_range": [ + 3306, + 3307 + ] + }, + { + "text": "foreach (i from egstart to eglen-1) {", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm3c.vi", + "line_range": [ + 3309, + 3309 + ] + }, + { + "text": "let w5 = : bits(32) rev8(w5i); let w4 = : bits(32) rev8(w4i); let w1 = : bits(32) rev8(w1i); let w0 = : bits(32) rev8(w0i);", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm3c.vi", + "line_range": [ + 3327, + 3330 + ] + }, + { + "text": "let x0 :bits(32) = w0 ^ w4; // W'[0] let x1 :bits(32) = w1 ^ w5; // W'[1]", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm3c.vi", + "line_range": [ + 3332, + 3333 + ] + }, + { + "text": "let j = 2 * rnds; let ss1 : bits(32) = ROL32(ROL32(A, 12) + E + ROL32(Tj(j), j % 32), 7); let ss2 : bits(32) = ss1 ^ ROL32(A, 12); let tt1 : bits(32) = FFj(A, B, C, j) + D + ss2 + x0; let tt2 : bits(32) = GGj(E, F, G, j) + H + ss1 + w0; D = C; let : bits(32) C1 = ROL32(B, 9); B = A; let A1 : bits(32) = tt1; H = G; let G1 : bits(32) = ROL32(F, 19); F = E; let E1 : bits(32) = P0(tt2);", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm3c.vi", + "line_range": [ + 3335, + 3347 + ] + }, + { + "text": "j = 2 * rnds + 1; ss1 = ROL32(ROL32(A1, 12) + E1 + ROL32(Tj(j), j % 32), 7); ss2 = ss1 ^ ROL32(A1, 12); tt1 = FFj(A1, B, C1, j) + D + ss2 + x1; tt2 = GGj(E1, F, G1, j) + H + ss1 + w1; D = C1; let C2 : bits(32) = ROL32(B, 9); B = A1; let A2 : bits(32) = tt1; H = G1; let G2 = : bits(32) ROL32(F, 19); F = E1; let E2 = : bits(32) P0(tt2);", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm3c.vi", + "line_range": [ + 3349, + 3361 + ] + }, + { + "text": "function FF1(X, Y, Z) = ((X) ^ (Y) ^ (Z)) function FF2(X, Y, Z) =", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm3c.vi", + "line_range": [ + 3372, + 3373 + ] + }, + { + "text": "function FFj(X, Y, Z, J) = (((J) <= 15) ? FF1(X, Y, Z) : FF2(X, Y, Z))", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm3c.vi", + "line_range": [ + 3375, + 3375 + ] + }, + { + "text": "function GG1(X, Y, Z) = ((X) ^ (Y) ^ (Z)) function GG2(X, Y, Z) = . function GGj(X, Y, Z, J) = (((J) <= 15) ? GG1(X, Y, Z) : GG2(X, Y, Z))", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm3c.vi", + "line_range": [ + 3377, + 3380 + ] + }, + { + "text": "function Tj(J) = (((J) <= 15) ? (0x79CC4519) : (0x7A879D8A))", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm3c.vi", + "line_range": [ + 3382, + 3382 + ] + }, + { + "text": "function P0(X) = ((X) ^ ROL32((X), 9) ^ ROL32((X), 17))", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm3c.vi", + "line_range": [ + 3384, + 3384 + ] + }, + { + "text": "Synopsis:: Vector SM3 Message Expansion", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm3me.vv", + "line_range": [ + 3396, + 3397 + ] + }, + { + "text": "Mnemonic:: vsm3me.vv vd, vs2, vs1", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm3me.vv", + "line_range": [ + 3399, + 3400 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 'OP-VE'}, {bits: 5, name: 'vd'}, {bits: 3, name: 'OPMVV'}, {bits: 5, name: 'vs1'}, {bits: 5, name: 'vs2'}, {bits: 1, name: '1'}, {bits: 6, name: '100000'}, ]} ....", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm3me.vv", + "line_range": [ + 3402, + 3417 + ] + }, + { + "text": "Reserved Encodings:: * `SEW` is any value other than 32 * The `vd` register group overlaps with the `vs2` register group.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm3me.vv", + "line_range": [ + 3402, + 3417 + ] + }, + { + "text": "| |Register |Direction |EGW |EGS |EEW |Definition", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm3me.vv", + "line_range": [ + 3421, + 3429 + ] + }, + { + "text": "| Vs1 | input | 256 | 8 | 32 | Message words W[7:0] | Vs2 | input | 256 | 8 | 32 | Message words W[15:8] | Vd | output | 256 | 8 | 32 | Message words W[23:16] |", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm3me.vv", + "line_range": [ + 3431, + 3434 + ] + }, + { + "text": "Description:: Eight rounds of SM3 message expansion are performed.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm3me.vv", + "line_range": [ + 3436, + 3437 + ] + }, + { + "text": "The sixteen most recent 32-bit message words are read in as two eight-element groups from `vs1` and `vs2`.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm3me.vv", + "line_range": [ + 3439, + 3444 + ] + }, + { + "text": "Each of these words is swapped from big endian to little endian.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm3me.vv", + "line_range": [ + 3439, + 3444 + ] + }, + { + "text": "The next eight 32-bit message words are generated, swapped from little endian to big endian, and are returned in an eight-element group.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm3me.vv", + "line_range": [ + 3439, + 3444 + ] + }, + { + "text": "Operation:: [source,sail] -- function clause execute (VSM3ME(vs2, vs1)) = { if(LMUL*VLEN < EGW) then { handleillegal(); // illegal-instruction exception RETIREFAIL } else {", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm3me.vv", + "line_range": [ + 3458, + 3465 + ] + }, + { + "text": "eglen = (vl/EGS) egstart = (vstart/EGS)", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm3me.vv", + "line_range": [ + 3467, + 3468 + ] + }, + { + "text": "foreach (i from egstart to eglen-1) { let w[7:0] : bits(256) = getvelem(vs1, 256, i); let w[15:8] : bits(256) = getvelem(vs2, 256, i);", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm3me.vv", + "line_range": [ + 3470, + 3472 + ] + }, + { + "text": "function P1(X) ((X) ^ ROL32((X), 15) ^ ROL32((X), 23))", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm3me.vv", + "line_range": [ + 3519, + 3519 + ] + }, + { + "text": "function ZVKSHW(M16, M9, M3, M13, M6) = \\ (P1( (M16) ^ (M9) ^ ROL32((M3), 15) ) ^ ROL32((M13), 7) ^ (M6)) --", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm3me.vv", + "line_range": [ + 3521, + 3523 + ] + }, + { + "text": "Synopsis:: Vector SM4 KeyExpansion", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm4k.vi", + "line_range": [ + 3535, + 3536 + ] + }, + { + "text": "Mnemonic:: vsm4k.vi vd, vs2, uimm", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm4k.vi", + "line_range": [ + 3538, + 3539 + ] + }, + { + "text": "Encoding:: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 'OP-VE'}, {bits: 5, name: 'vd'}, {bits: 3, name: 'OPMVV'}, {bits: 5, name: 'uimm'}, {bits: 5, name: 'vs2'}, {bits: 1, name: '1'}, {bits: 6, name: '100001'}, ]} ....", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm4k.vi", + "line_range": [ + 3541, + 3555 + ] + }, + { + "text": "Reserved Encodings:: * `SEW` is any value other than 32", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm4k.vi", + "line_range": [ + 3541, + 3555 + ] + }, + { + "text": "| |Register |Direction |EGW |EGS |EEW |Definition", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm4k.vi", + "line_range": [ + 3559, + 3567 + ] + }, + { + "text": "| uimm | input | - | - | - | Round group (rnd) | Vs2 | input | 128 | 4 | 32 | Current 4 round keys rK[0:3] | Vd | output | 128 | 4 | 32 | Next 4 round keys rK'[0:3] |", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm4k.vi", + "line_range": [ + 3569, + 3572 + ] + }, + { + "text": "Description:: Four rounds of the SM4 Key Expansion are performed.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm4k.vi", + "line_range": [ + 3574, + 3575 + ] + }, + { + "text": "Four round keys are read in as a 4-element group from `vs2`.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm4k.vi", + "line_range": [ + 3577, + 3580 + ] + }, + { + "text": "Each of the next four round keys are generated by iteratively XORing the last three round keys with a constant that is indexed by the Round Group Number, performing a byte-wise substitution, and then performing XORs between rotated versions of this value and the corresponding current round key.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm4k.vi", + "line_range": [ + 3577, + 3580 + ] + }, + { + "text": "The Round group number (`rnd`) comes from `uimm[2:0]`; the bits in `uimm[4:3]` are ignored.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm4k.vi", + "line_range": [ + 3582, + 3585 + ] + }, + { + "text": "Round group numbers range from 0 to 7 and indicate which group of four round keys are being generated.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm4k.vi", + "line_range": [ + 3582, + 3585 + ] + }, + { + "text": "Round Keys range from 0-31.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm4k.vi", + "line_range": [ + 3582, + 3585 + ] + }, + { + "text": "For example, if `rnd`=1, then round keys 4, 5, 6, and 7 are being generated.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm4k.vi", + "line_range": [ + 3582, + 3585 + ] + }, + { + "text": ".System Parameters | |FK |constant", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm4k.vi", + "line_range": [ + 3594, + 3599 + ] + }, + { + "text": "| 0 | A3B1BAC6 | 1 | 56AA3350 | 2 | 677D9197 | 3 | B27022DC |", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm4k.vi", + "line_range": [ + 3601, + 3605 + ] + }, + { + "text": "| 0 | A3B1BAC6 | 1 | 56AA3350 | 2 | 677D9197 | 3 | B27022DC | ////", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm4k.vi", + "line_range": [ + 3615, + 3620 + ] + }, + { + "text": "| 0 | A3B1BAC6 | 1 | 56AA3350 | 2 | 677D9197 | 3 | B27022DC | ////", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm4k.vi", + "line_range": [ + 3650, + 3655 + ] + }, + { + "text": "Operation:: [source,sail] --", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm4k.vi", + "line_range": [ + 3657, + 3659 + ] + }, + { + "text": "function clause execute (vsm4k(uimm, vs2)) = { if(LMUL*VLEN < EGW) then { handleillegal(); // illegal-instruction exception RETIREFAIL } else {", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm4k.vi", + "line_range": [ + 3661, + 3665 + ] + }, + { + "text": "eglen = (vl/EGS) egstart = (vstart/EGS)", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm4k.vi", + "line_range": [ + 3667, + 3668 + ] + }, + { + "text": "let B : bits(32) = 0; let S : bits(32) = 0; let rk4 : bits(32) = 0; let rk5 : bits(32) = 0; let rk6 : bits(32) = 0; let rk7 : bits(32) = 0; let rnd : bits(3) = uimm[2:0]; // Lower 3 bits", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm4k.vi", + "line_range": [ + 3670, + 3676 + ] + }, + { + "text": "foreach (i from egstart to eglen-1) { let (rk3 @ rk2 @ rk1 @ rk0) : bits(128) = getvelem(vs2, 128, i);", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm4k.vi", + "line_range": [ + 3678, + 3679 + ] + }, + { + "text": "B = rk1 ^ rk2 ^ rk3 ^ ck(4 * rnd); S = sm4subword(B); rk4 = ROUNDKEY(rk0, S);", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm4k.vi", + "line_range": [ + 3681, + 3683 + ] + }, + { + "text": "B = rk2 ^ rk3 ^ rk4 ^ ck(4 * rnd + 1); S = sm4subword(B); rk5 = ROUNDKEY(rk1, S);", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm4k.vi", + "line_range": [ + 3685, + 3687 + ] + }, + { + "text": "B = rk3 ^ rk4 ^ rk5 ^ ck(4 * rnd + 2); S = sm4subword(B); rk6 = ROUNDKEY(rk2, S);", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm4k.vi", + "line_range": [ + 3689, + 3691 + ] + }, + { + "text": "B = rk4 ^ rk5 ^ rk6 ^ ck(4 * rnd + 3); S = sm4subword(B); rk7 = ROUNDKEY(rk3, S);", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm4k.vi", + "line_range": [ + 3693, + 3695 + ] + }, + { + "text": "val roundkey : bits(32) -> bits(32) function ROUNDKEY(X, S) = ((X) ^ ((S) ^ ROL32((S), 13) ^ ROL32((S), 23)))", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm4k.vi", + "line_range": [ + 3704, + 3705 + ] + }, + { + "text": "Synopsis:: Vector SM4 Rounds", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm4r.[vv,vs]", + "line_range": [ + 3734, + 3735 + ] + }, + { + "text": "Mnemonic:: vsm4r.vv vd, vs2 + vsm4r.vs vd, vs2", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm4r.[vv,vs]", + "line_range": [ + 3737, + 3739 + ] + }, + { + "text": "Encoding (Vector-Vector):: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 'OP-VE'}, {bits: 5, name: 'vd'}, {bits: 3, name: 'OPMVV'}, {bits: 5, name: '10000'}, {bits: 5, name: 'vs2'}, {bits: 1, name: '1'}, {bits: 6, name: '101000'}, ]} ....", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm4r.[vv,vs]", + "line_range": [ + 3741, + 3753 + ] + }, + { + "text": "Encoding (Vector-Scalar):: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 'OP-VE'}, {bits: 5, name: 'vd'}, {bits: 3, name: 'OPMVV'}, {bits: 5, name: '10000'}, {bits: 5, name: 'vs2'}, {bits: 1, name: '1'}, {bits: 6, name: '101001'}, ]} ....", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm4r.[vv,vs]", + "line_range": [ + 3755, + 3770 + ] + }, + { + "text": "Reserved Encodings:: * `SEW` is any value other than 32 * Only for the `.vs` form: the `vd` register group overlaps the `vs2` register", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm4r.[vv,vs]", + "line_range": [ + 3755, + 3770 + ] + }, + { + "text": "| |Register |Direction |EGW |EGS |EEW |Definition", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm4r.[vv,vs]", + "line_range": [ + 3774, + 3782 + ] + }, + { + "text": "| Vd | input | 128 | 4 | 32 | Current state X[0:3] | Vs2 | input | 128 | 4 | 32 | Round keys rk[0:3] | Vd | output | 128 | 4 | 32 | Next state X'[0:3] |", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm4r.[vv,vs]", + "line_range": [ + 3784, + 3787 + ] + }, + { + "text": "Description:: Four rounds of SM4 Encryption/Decryption are performed.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm4r.[vv,vs]", + "line_range": [ + 3789, + 3790 + ] + }, + { + "text": "The four words of current state are read as a 4-element group from `vd` and the round keys are read from either the corresponding 4-element group in `vs2` (vector-vector form) or the scalar element group in `vs2` (vector-scalar form).", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm4r.[vv,vs]", + "line_range": [ + 3792, + 3800 + ] + }, + { + "text": "The next four words of state are generated by iteratively XORing the last three words of the state with the corresponding round key, performing a byte-wise substitution, and then performing XORs between rotated versions of this value and the corresponding current state.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm4r.[vv,vs]", + "line_range": [ + 3792, + 3800 + ] + }, + { + "text": "Operation:: [source,pseudocode] -- function clause execute (VSM4R(vd, vs2)) = { if(LMUL*VLEN < EGW) then { handleillegal(); // illegal-instruction exception RETIREFAIL } else {", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm4r.[vv,vs]", + "line_range": [ + 3807, + 3814 + ] + }, + { + "text": "eglen = (vl/EGS) egstart = (vstart/EGS)", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm4r.[vv,vs]", + "line_range": [ + 3816, + 3817 + ] + }, + { + "text": "let B : bits(32) = 0; let S : bits(32) = 0; let rk0 : bits(32) = 0; let rk1 : bits(32) = 0; let rk2 : bits(32) = 0; let rk3 : bits(32) = 0; let x0 : bits(32) = 0; let x1 : bits(32) = 0; let x2 : bits(32) = 0; let x3 : bits(32) = 0; let x4 : bits(32) = 0; let x5 : bits(32) = 0; let x6 : bits(32) = 0; let x7 : bits(32) = 0;", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm4r.[vv,vs]", + "line_range": [ + 3819, + 3832 + ] + }, + { + "text": "let keyelem : bits(32) = 0;", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm4r.[vv,vs]", + "line_range": [ + 3834, + 3834 + ] + }, + { + "text": "foreach (i from egstart to eglen-1) { keyelem = if suffix \"vv\" then i else 0; {rk3 @ rk2 @ rk1 @ rk0} : bits(128) = getvelem(vs2, EGW=128, keyelem); {x3 @ x2 @ x1 @ x0} : bits(128) = getvelem(vd, EGW=128, i);", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm4r.[vv,vs]", + "line_range": [ + 3836, + 3839 + ] + }, + { + "text": "B = x1 ^ x2 ^ x3 ^ rk0; S = sm4subword(B); x4 = sm4round(x0, S);", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm4r.[vv,vs]", + "line_range": [ + 3841, + 3843 + ] + }, + { + "text": "B = x2 ^ x3 ^ x4 ^ rk1; S = sm4subword(B); x5= sm4round(x1, S);", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm4r.[vv,vs]", + "line_range": [ + 3845, + 3847 + ] + }, + { + "text": "B = x3 ^ x4 ^ x5 ^ rk2; S = sm4subword(B); x6 = sm4round(x2, S);", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm4r.[vv,vs]", + "line_range": [ + 3849, + 3851 + ] + }, + { + "text": "B = x4 ^ x5 ^ x6 ^ rk3; S = sm4subword(B); x7 = sm4round(x3, S);", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm4r.[vv,vs]", + "line_range": [ + 3853, + 3855 + ] + }, + { + "text": "setvelem(vd, EGW=128, i, (x7 @ x6 @ x5 @ x4));", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm4r.[vv,vs]", + "line_range": [ + 3857, + 3857 + ] + }, + { + "text": "val sm4round : bits(32) -> bits(32) function sm4round(X, S) = \\ ((X) ^ ((S) ^ ROL32((S), 2) ^ ROL32((S), 10) ^ ROL32((S), 18) ^ ROL32((S), 24)))", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vsm4r.[vv,vs]", + "line_range": [ + 3864, + 3866 + ] + }, + { + "text": "Synopsis:: Vector widening shift left logical by vector/scalar/immediate.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vwsll.[vv,vx,vi]", + "line_range": [ + 3878, + 3879 + ] + }, + { + "text": "Mnemonic:: vwsll.vv vd, vs2, vs1, vm + vwsll.vx vd, vs2, rs1, vm + vwsll.vi vd, vs2, uimm, vm", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vwsll.[vv,vx,vi]", + "line_range": [ + 3881, + 3884 + ] + }, + { + "text": "Encoding (Vector-Vector):: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 'OP-V'}, {bits: 5, name: 'vd'}, {bits: 3, name: 'OPIVV'}, {bits: 5, name: 'vs1'}, {bits: 5, name: 'vs2'}, {bits: 1, name: 'vm'}, {bits: 6, name: '110101'}, ]} ....", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vwsll.[vv,vx,vi]", + "line_range": [ + 3886, + 3898 + ] + }, + { + "text": "Encoding (Vector-Scalar):: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 'OP-V'}, {bits: 5, name: 'vd'}, {bits: 3, name: 'OPIVX'}, {bits: 5, name: 'rs1'}, {bits: 5, name: 'vs2'}, {bits: 1, name: 'vm'}, {bits: 6, name: '110101'}, ]} ....", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vwsll.[vv,vx,vi]", + "line_range": [ + 3900, + 3912 + ] + }, + { + "text": "Encoding (Vector-Immediate):: [wavedrom, , svg] .... {reg:[ {bits: 7, name: 'OP-V'}, {bits: 5, name: 'vd'}, {bits: 3, name: 'OPIVI'}, {bits: 5, name: 'uimm[4:0]'}, {bits: 5, name: 'vs2'}, {bits: 1, name: 'vm'}, {bits: 6, name: '110101'}, ]} ....", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vwsll.[vv,vx,vi]", + "line_range": [ + 3914, + 3926 + ] + }, + { + "text": "| |Register |Direction |Definition", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vwsll.[vv,vx,vi]", + "line_range": [ + 3930, + 3935 + ] + }, + { + "text": "| Vs1 | input | Shift amount | Vs2 | input | Data | Vd | output | Shifted data |", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vwsll.[vv,vx,vi]", + "line_range": [ + 3937, + 3940 + ] + }, + { + "text": "Vector-Scalar/Immediate Arguments::", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vwsll.[vv,vx,vi]", + "line_range": [ + 3942, + 3942 + ] + }, + { + "text": "| |Register |Direction |EEW |Definition", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vwsll.[vv,vx,vi]", + "line_range": [ + 3944, + 3950 + ] + }, + { + "text": "| Rs1/imm | input | SEW | Shift amount | Vs2 | input | SEW | Data | Vd | output | 2*SEW | Shifted data |", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vwsll.[vv,vx,vi]", + "line_range": [ + 3952, + 3955 + ] + }, + { + "text": "Description:: A widening logical shift left is performed on each element of `vs2`.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vwsll.[vv,vx,vi]", + "line_range": [ + 3957, + 3958 + ] + }, + { + "text": "The elements in `vs2` are zero-extended to 2*`SEW` bits, then shifted left by the shift amount specified by either the corresponding elements of `vs1` (vector-vector), integer register `rs1` (vector-scalar), or an immediate value (vector-immediate).", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vwsll.[vv,vx,vi]", + "line_range": [ + 3960, + 3965 + ] + }, + { + "text": "Only the low log2(2*`SEW`) bits of the shift-amount value are used, all other bits are ignored.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vwsll.[vv,vx,vi]", + "line_range": [ + 3960, + 3965 + ] + }, + { + "text": "Operation:: [source,sail] -- function clause execute (VWSLLVV(vs2, vs1, vd)) = { foreach (i from vstart to vl - 1) { setvelem(vd, EEW=2*SEW, i, getvelem(vs2, i) << (getvelem(vs1, i) & ((2*SEW)-1)) ) } RETIRESUCCESS }", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vwsll.[vv,vx,vi]", + "line_range": [ + 3967, + 3977 + ] + }, + { + "text": "function clause execute (VWSLLVX(vs2, rs1, vd)) = { foreach (i from vstart to vl - 1) { setvelem(vd, EEW=2*SEW, i, getvelem(vs2, i) << (X(rs1) & ((2*SEW)-1)) ) } RETIRESUCCESS }", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vwsll.[vv,vx,vi]", + "line_range": [ + 3979, + 3986 + ] + }, + { + "text": "function clause execute (VWSLLVI(vs2, uimm[4:0], vd)) = { foreach (i from vstart to vl - 1) { setvelem(vd, EEW=2*SEW, i, getvelem(vs2, i) << (uimm[4:0] & ((2*SEW)-1)) ) } RETIRESUCCESS } --", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Instructions > vwsll.[vv,vx,vi]", + "line_range": [ + 3988, + 3996 + ] + }, + { + "text": "OP-VE (0x77) Crypto Vector instructions except Zvbb and Zvbc", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Crypto Vector Cryptographic Instructions", + "line_range": [ + 4008, + 4009 + ] + }, + { + "text": "| funct3 | | | | | funct3 | | | | funct3 | | | | OPIVV |V| | | | OPMVV |V| | | OPFVV |V| | | OPIVX | |X| | | OPMVX | |X| | OPFVF | |F| | OPIVI | | |I| | | | | | | | | |", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Crypto Vector Cryptographic Instructions", + "line_range": [ + 4016, + 4020 + ] + }, + { + "text": "| 5+^| funct6 4+^| funct6 4+^| funct6", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Crypto Vector Cryptographic Instructions", + "line_range": [ + 4025, + 4026 + ] + }, + { + "text": "|100000||||| 100000 |V| | vsm3me | 100000 | | | | 100001 | | | | | 100001 |V| | vsm4k.vi | 100001 | | | | 100010 | | | | | 100010 |V| | vaeskf1.vi | 100010 | | | | 100011 | | | | | 100011 | | | | 100011 | | | | 100100 | | | | | 100100 | | | | 100100 | | | | 100101 | | | | | 100101 | | | | 100101 | | | | 100110 | | | | | 100110 | | | | 100110 | | | | 100111 | | | | | 100111 | | | | 100111 | | | | | | | | | | | | | | | | | 101000 | | | | | 101000 |V| | *VAES.vv* | 101000 | | | | 101001 | | | | | 101001 |V| | *VAES.vs* | 101001 | | | | 101010 | | | | | 101010 |V| | vaeskf2.vi | 101010 | | | | 101011 | | | | | 101011 |V| | vsm3c.vi | 101011 | | | | 101100 | | | | | 101100 |V| | vghsh | 101100 | | | | 101101 | | | | | 101101 |V| | vsha2ms | 101101 | | | | 101110 | | | | | 101110 |V| | vsha2ch | 101110 | | | | 101111 | | | | | 101111 |V| | vsha2cl | 101111 | | | |", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Crypto Vector Cryptographic Instructions", + "line_range": [ + 4028, + 4045 + ] + }, + { + "text": ".VAES.vv and VAES.vs encoding space [cols=\"2,14\"] | |vs1|", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Crypto Vector Cryptographic Instructions", + "line_range": [ + 4049, + 4052 + ] + }, + { + "text": "| 00000 | vaesdm | 00001 | vaesdf | 00010 | vaesem | 00011 | vaesef | 00111 | vaesz | 10000 | vsm4r | 10001 | vgmul |", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Crypto Vector Cryptographic Instructions", + "line_range": [ + 4054, + 4061 + ] + }, + { + "text": "OP-V (0x57) *Zvbb*, *Zvkb*, and *Zvbc* Vector instructions *in bold* // | 5+| Integer 4+| Integer 4+| FP", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Vector Bitmanip and Carry-less Multiply Instructions", + "line_range": [ + 4066, + 4071 + ] + }, + { + "text": "| funct3 | | | | | funct3 | | | | funct3 | | | | OPIVV |V| | | | OPMVV |V| | | OPFVV |V| | | OPIVX | |X| | | OPMVX | |X| | OPFVF | |F| | OPIVI | | |I| | | | | | | | | |", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Vector Bitmanip and Carry-less Multiply Instructions", + "line_range": [ + 4073, + 4077 + ] + }, + { + "text": "| 000000 |V|X|I| vadd | 000000 |V| | vredsum | 000000 |V|F| vfadd | 000001 |V|X| | *vandn* | 000001 |V| | vredand | 000001 |V| | vfredusum | 000010 |V|X| | vsub | 000010 |V| | vredor | 000010 |V|F| vfsub | 000011 | |X|I| vrsub | 000011 |V| | vredxor | 000011 |V| | vfredosum | 000100 |V|X| | vminu | 000100 |V| | vredminu | 000100 |V|F| vfmin | 000101 |V|X| | vmin | 000101 |V| | vredmin | 000101 |V| | vfredmin | 000110 |V|X| | vmaxu | 000110 |V| | vredmaxu | 000110 |V|F| vfmax | 000111 |V|X| | vmax | 000111 |V| | vredmax | 000111 |V| | vfredmax | 001000 | | | | | 001000 |V|X| vaaddu | 001000 |V|F| vfsgnj | 001001 |V|X|I| vand | 001001 |V|X| vaadd | 001001 |V|F| vfsgnjn | 001010 |V|X|I| vor | 001010 |V|X| vasubu | 001010 |V|F| vfsgnjx | 001011 |V|X|I| vxor | 001011 |V|X| vasub | 001011 | | | | 001100 |V|X|I| vrgather | 001100 |V|X| *vclmul* | 001100 | | | | 001101 | | | | | 001101 |V|X| *vclmulh* | 001101 | | | | 001110 | |X|I| vslideup | 001110 | |X| vslide1up | 001110 | |F| vfslide1up | 001110 |V| | | vrgatherei16| | | | | | | | | 001111 | |X|I| vslidedown | 001111 | |X| vslide1down | 001111 | |F| vfslide1down |", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Vector Bitmanip and Carry-less Multiply Instructions", + "line_range": [ + 4084, + 4101 + ] + }, + { + "text": "| 5+| funct6 4+| funct6 4+| funct6", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Vector Bitmanip and Carry-less Multiply Instructions", + "line_range": [ + 4103, + 4105 + ] + }, + { + "text": "| 010000 |V|X|I| vadc | 010000 |V| | VWXUNARY0 | 010000 |V| | VWFUNARY0 | | | | | | 010000 | |X| VRXUNARY0 | 010000 | |F| VRFUNARY0 | 010001 |V|X|I| vmadc | 010001 | | | | 010001 | | | | 010010 |V|X| | vsbc | 010010 |V| | VXUNARY0 | 010010 |V| | VFUNARY0 | 010011 |V|X| | vmsbc | 010011 | | | | 010011 |V| | VFUNARY1 | 010100 |V|X| | *vror* | 010100 |V| | VMUNARY0 | 010100 | | | | 010101 |V|X| | *vrol* | 010101 | | | | 010101 | | | | 01010x | | |I| *vror* | | | | | | | | | 010110 | | | | | 010110 | | | | 010110 | | | | 010111 |V|X|I| vmerge/vmv | 010111 |V| | vcompress | 010111 | |F| vfmerge/vfmv | 011000 |V|X|I| vmseq | 011000 |V| | vmandn | 011000 |V|F| vmfeq | 011001 |V|X|I| vmsne | 011001 |V| | vmand | 011001 |V|F| vmfle | 011010 |V|X| | vmsltu | 011010 |V| | vmor | 011010 | | | | 011011 |V|X| | vmslt | 011011 |V| | vmxor | 011011 |V|F| vmflt | 011100 |V|X|I| vmsleu | 011100 |V| | vmorn | 011100 |V|F| vmfne | 011101 |V|X|I| vmsle | 011101 |V| | vmnand | 011101 | |F| vmfgt | 011110 | |X|I| vmsgtu | 011110 |V| | vmnor | 011110 | | | | 011111 | |X|I| vmsgt | 011111 |V| | vmxnor | 011111 | |F| vmfge |", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Vector Bitmanip and Carry-less Multiply Instructions", + "line_range": [ + 4107, + 4125 + ] + }, + { + "text": "| 5+| funct6 4+| funct6 4+| funct6", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Vector Bitmanip and Carry-less Multiply Instructions", + "line_range": [ + 4127, + 4129 + ] + }, + { + "text": "| 100000 |V|X|I| vsaddu | 100000 |V|X| vdivu | 100000 |V|F| vfdiv | 100001 |V|X|I| vsadd | 100001 |V|X| vdiv | 100001 | |F| vfrdiv | 100010 |V|X| | vssubu | 100010 |V|X| vremu | 100010 | | | | 100011 |V|X| | vssub | 100011 |V|X| vrem | 100011 | | | | 100100 | | | | | 100100 |V|X| vmulhu | 100100 |V|F| vfmul | 100101 |V|X|I| vsll | 100101 |V|X| vmul | 100101 | | | | 100110 | | | | | 100110 |V|X| vmulhsu | 100110 | | | | 100111 |V|X| | vsmul | 100111 |V|X| vmulh | 100111 | |F| vfrsub | 100111 | | |I| vmvr | | | | | | | | | 101000 |V|X|I| vsrl | 101000 | | | | 101000 |V|F| vfmadd | 101001 |V|X|I| vsra | 101001 |V|X| vmadd | 101001 |V|F| vfnmadd | 101010 |V|X|I| vssrl | 101010 | | | | 101010 |V|F| vfmsub | 101011 |V|X|I| vssra | 101011 |V|X| vnmsub | 101011 |V|F| vfnmsub | 101100 |V|X|I| vnsrl | 101100 | | | | 101100 |V|F| vfmacc | 101101 |V|X|I| vnsra | 101101 |V|X| vmacc | 101101 |V|F| vfnmacc | 101110 |V|X|I| vnclipu | 101110 | | | | 101110 |V|F| vfmsac | 101111 |V|X|I| vnclip | 101111 |V|X| vnmsac | 101111 |V|F| vfnmsac |", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Vector Bitmanip and Carry-less Multiply Instructions", + "line_range": [ + 4131, + 4148 + ] + }, + { + "text": "| 5+| funct6 4+| funct6 4+| funct6", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Vector Bitmanip and Carry-less Multiply Instructions", + "line_range": [ + 4150, + 4152 + ] + }, + { + "text": "| 110000 |V| | | vwredsumu | 110000 |V|X| vwaddu | 110000 |V|F| vfwadd | 110001 |V| | | vwredsum | 110001 |V|X| vwadd | 110001 |V| | vfwredusum | 110010 | | | | | 110010 |V|X| vwsubu | 110010 |V|F| vfwsub | 110011 | | | | | 110011 |V|X| vwsub | 110011 |V| | vfwredosum | 110100 | | | | | 110100 |V|X| vwaddu.w | 110100 |V|F| vfwadd.w | 110101 |V|X|I| *vwsll* | 110101 |V|X| vwadd.w | 110101 | | | | 110110 | | | | | 110110 |V|X| vwsubu.w | 110110 |V|F| vfwsub.w | 110111 | | | | | 110111 |V|X| vwsub.w | 110111 | | | | 111000 | | | | | 111000 |V|X| vwmulu | 111000 |V|F| vfwmul | 111001 | | | | | 111001 | | | | 111001 | | | | 111010 | | | | | 111010 |V|X| vwmulsu | 111010 | | | | 111011 | | | | | 111011 |V|X| vwmul | 111011 | | | | 111100 | | | | | 111100 |V|X| vwmaccu | 111100 |V|F| vfwmacc | 111101 | | | | | 111101 |V|X| vwmacc | 111101 |V|F| vfwnmacc | 111110 | | | | | 111110 | |X| vwmaccus | 111110 |V|F| vfwmsac | 111111 | | | | | 111111 |V|X| vwmaccsu | 111111 |V|F| vfwnmsac |", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Vector Bitmanip and Carry-less Multiply Instructions", + "line_range": [ + 4154, + 4170 + ] + }, + { + "text": "| 00010 | vzext.vf8 | 00011 | vsext.vf8 | 00100 | vzext.vf4 | 00101 | vsext.vf4 | 00110 | vzext.vf2 | 00111 | vsext.vf2 | 01000 | *vbrev8* | 01001 | *vrev8* | 01010 | *vbrev* | 01100 | *vclz* | 01101 | *vctz* | 01110 | *vcpop*", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Vector Bitmanip and Carry-less Multiply Instructions", + "line_range": [ + 4180, + 4191 + ] + }, + { + "text": "This section contains the supporting Sail code referenced by the instruction descriptions throughout the specification.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Supporting Sail Code", + "line_range": [ + 4198, + 4202 + ] + }, + { + "text": "The link:https://alasdair.github.io/manual.html[Sail Manual] is recommended reading in order to best understand the supporting code.", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Supporting Sail Code", + "line_range": [ + 4198, + 4202 + ] + }, + { + "text": "[source,sail] ---- val xt2 : bits(8) -> bits(8) function xt2(x) = { (x << 1) ^ (if bittobool(x[7]) then 0x1b else 0x00) }", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Supporting Sail Code", + "line_range": [ + 4204, + 4210 + ] + }, + { + "text": "val xt3 : bits(8) -> bits(8) function xt3(x) = x ^ xt2(x)", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Supporting Sail Code", + "line_range": [ + 4212, + 4213 + ] + }, + { + "text": "val gfmul : (bits(8), bits(4)) -> bits(8) function gfmul( x, y) = { (if bittobool(y[0]) then x else 0x00) ^ (if bittobool(y[1]) then xt2( x) else 0x00) ^ (if bittobool(y[2]) then xt2(xt2( x)) else 0x00) ^ (if bittobool(y[3]) then xt2(xt2(xt2(x))) else 0x00) }", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Supporting Sail Code", + "line_range": [ + 4215, + 4222 + ] + }, + { + "text": "val aesmixcolumnbytefwd : bits(8) -> bits(32) function aesmixcolumnbytefwd(so) = { gfmul(so, 0x3) @ so @ so @ gfmul(so, 0x2) }", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Supporting Sail Code", + "line_range": [ + 4224, + 4228 + ] + }, + { + "text": "val aesmixcolumnbyteinv : bits(8) -> bits(32) function aesmixcolumnbyteinv(so) = { gfmul(so, 0xb) @ gfmul(so, 0xd) @ gfmul(so, 0x9) @ gfmul(so, 0xe) }", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Supporting Sail Code", + "line_range": [ + 4230, + 4234 + ] + }, + { + "text": "val aesmixcolumnfwd : bits(32) -> bits(32) function aesmixcolumnfwd(x) = { let s0 : bits (8) = x[ 7.. 0]; let s1 : bits (8) = x[15.. 8]; let s2 : bits (8) = x[23..16]; let s3 : bits (8) = x[31..24]; let b0 : bits (8) = xt2(s0) ^ xt3(s1) ^ (s2) ^ (s3); let b1 : bits (8) = (s0) ^ xt2(s1) ^ xt3(s2) ^ (s3); let b2 : bits (8) = (s0) ^ (s1) ^ xt2(s2) ^ xt3(s3); let b3 : bits (8) = xt3(s0) ^ (s1) ^ (s2) ^ xt2(s3); b3 @ b2 @ b1 @ b0 }", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Supporting Sail Code", + "line_range": [ + 4236, + 4248 + ] + }, + { + "text": "val aesmixcolumninv : bits(32) -> bits(32) function aesmixcolumninv(x) = { let s0 : bits (8) = x[ 7.. 0]; let s1 : bits (8) = x[15.. 8]; let s2 : bits (8) = x[23..16]; let s3 : bits (8) = x[31..24]; let b0 : bits (8) = gfmul(s0, 0xE) ^ gfmul(s1, 0xB) ^ gfmul(s2, 0xD) ^ gfmul(s3, 0x9); let b1 : bits (8) = gfmul(s0, 0x9) ^ gfmul(s1, 0xE) ^ gfmul(s2, 0xB) ^ gfmul(s3, 0xD); let b2 : bits (8) = gfmul(s0, 0xD) ^ gfmul(s1, 0x9) ^ gfmul(s2, 0xE) ^ gfmul(s3, 0xB); let b3 : bits (8) = gfmul(s0, 0xB) ^ gfmul(s1, 0xD) ^ gfmul(s2, 0x9) ^ gfmul(s3, 0xE); b3 @ b2 @ b1 @ b0 }", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Supporting Sail Code", + "line_range": [ + 4250, + 4262 + ] + }, + { + "text": "val aesdecodercon : bits(4) -> bits(32) function aesdecodercon(r) = { match r { 0x0 => 0x00000001, 0x1 => 0x00000002, 0x2 => 0x00000004, 0x3 => 0x00000008, 0x4 => 0x00000010, 0x5 => 0x00000020, 0x6 => 0x00000040, 0x7 => 0x00000080, 0x8 => 0x0000001b, 0x9 => 0x00000036, 0xA => 0x00000000, 0xB => 0x00000000, 0xC => 0x00000000, 0xD => 0x00000000, 0xE => 0x00000000, 0xF => 0x00000000 } }", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Supporting Sail Code", + "line_range": [ + 4264, + 4284 + ] + }, + { + "text": "let sm4sboxtable : list(bits(8)) = [| 0xD6, 0x90, 0xE9, 0xFE, 0xCC, 0xE1, 0x3D, 0xB7, 0x16, 0xB6, 0x14, 0xC2, 0x28, 0xFB, 0x2C, 0x05, 0x2B, 0x67, 0x9A, 0x76, 0x2A, 0xBE, 0x04, 0xC3, 0xAA, 0x44, 0x13, 0x26, 0x49, 0x86, 0x06, 0x99, 0x9C, 0x42, 0x50, 0xF4, 0x91, 0xEF, 0x98, 0x7A, 0x33, 0x54, 0x0B, 0x43, 0xED, 0xCF, 0xAC, 0x62, 0xE4, 0xB3, 0x1C, 0xA9, 0xC9, 0x08, 0xE8, 0x95, 0x80, 0xDF, 0x94, 0xFA, 0x75, 0x8F, 0x3F, 0xA6, 0x47, 0x07, 0xA7, 0xFC, 0xF3, 0x73, 0x17, 0xBA, 0x83, 0x59, 0x3C, 0x19, 0xE6, 0x85, 0x4F, 0xA8, 0x68, 0x6B, 0x81, 0xB2, 0x71, 0x64, 0xDA, 0x8B, 0xF8, 0xEB, 0x0F, 0x4B, 0x70, 0x56, 0x9D, 0x35, 0x1E, 0x24, 0x0E, 0x5E, 0x63, 0x58, 0xD1, 0xA2, 0x25, 0x22, 0x7C, 0x3B, 0x01, 0x21, 0x78, 0x87, 0xD4, 0x00, 0x46, 0x57, 0x9F, 0xD3, 0x27, 0x52, 0x4C, 0x36, 0x02, 0xE7, 0xA0, 0xC4, 0xC8, 0x9E, 0xEA, 0xBF, 0x8A, 0xD2, 0x40, 0xC7, 0x38, 0xB5, 0xA3, 0xF7, 0xF2, 0xCE, 0xF9, 0x61, 0x15, 0xA1, 0xE0, 0xAE, 0x5D, 0xA4, 0x9B, 0x34, 0x1A, 0x55, 0xAD, 0x93, 0x32, 0x30, 0xF5, 0x8C, 0xB1, 0xE3, 0x1D, 0xF6, 0xE2, 0x2E, 0x82, 0x66, 0xCA, 0x60, 0xC0, 0x29, 0x23, 0xAB, 0x0D, 0x53, 0x4E, 0x6F, 0xD5, 0xDB, 0x37, 0x45, 0xDE, 0xFD, 0x8E, 0x2F, 0x03, 0xFF, 0x6A, 0x72, 0x6D, 0x6C, 0x5B, 0x51, 0x8D, 0x1B, 0xAF, 0x92, 0xBB, 0xDD, 0xBC, 0x7F, 0x11, 0xD9, 0x5C, 0x41, 0x1F, 0x10, 0x5A, 0xD8, 0x0A, 0xC1, 0x31, 0x88, 0xA5, 0xCD, 0x7B, 0xBD, 0x2D, 0x74, 0xD0, 0x12, 0xB8, 0xE5, 0xB4, 0xB0, 0x89, 0x69, 0x97, 0x4A, 0x0C, 0x96, 0x77, 0x7E, 0x65, 0xB9, 0xF1, 0x09, 0xC5, 0x6E, 0xC6, 0x84, 0x18, 0xF0, 0x7D, 0xEC, 0x3A, 0xDC, 0x4D, 0x20, 0x79, 0xEE, 0x5F, 0x3E, 0xD7, 0xCB, 0x39, 0x48 |]", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Supporting Sail Code", + "line_range": [ + 4286, + 4308 + ] + }, + { + "text": "let aessboxfwdtable : list(bits(8)) = [| 0x63, 0x7c, 0x77, 0x7b, 0xf2, 0x6b, 0x6f, 0xc5, 0x30, 0x01, 0x67, 0x2b, 0xfe, 0xd7, 0xab, 0x76, 0xca, 0x82, 0xc9, 0x7d, 0xfa, 0x59, 0x47, 0xf0, 0xad, 0xd4, 0xa2, 0xaf, 0x9c, 0xa4, 0x72, 0xc0, 0xb7, 0xfd, 0x93, 0x26, 0x36, 0x3f, 0xf7, 0xcc, 0x34, 0xa5, 0xe5, 0xf1, 0x71, 0xd8, 0x31, 0x15, 0x04, 0xc7, 0x23, 0xc3, 0x18, 0x96, 0x05, 0x9a, 0x07, 0x12, 0x80, 0xe2, 0xeb, 0x27, 0xb2, 0x75, 0x09, 0x83, 0x2c, 0x1a, 0x1b, 0x6e, 0x5a, 0xa0, 0x52, 0x3b, 0xd6, 0xb3, 0x29, 0xe3, 0x2f, 0x84, 0x53, 0xd1, 0x00, 0xed, 0x20, 0xfc, 0xb1, 0x5b, 0x6a, 0xcb, 0xbe, 0x39, 0x4a, 0x4c, 0x58, 0xcf, 0xd0, 0xef, 0xaa, 0xfb, 0x43, 0x4d, 0x33, 0x85, 0x45, 0xf9, 0x02, 0x7f, 0x50, 0x3c, 0x9f, 0xa8, 0x51, 0xa3, 0x40, 0x8f, 0x92, 0x9d, 0x38, 0xf5, 0xbc, 0xb6, 0xda, 0x21, 0x10, 0xff, 0xf3, 0xd2, 0xcd, 0x0c, 0x13, 0xec, 0x5f, 0x97, 0x44, 0x17, 0xc4, 0xa7, 0x7e, 0x3d, 0x64, 0x5d, 0x19, 0x73, 0x60, 0x81, 0x4f, 0xdc, 0x22, 0x2a, 0x90, 0x88, 0x46, 0xee, 0xb8, 0x14, 0xde, 0x5e, 0x0b, 0xdb, 0xe0, 0x32, 0x3a, 0x0a, 0x49, 0x06, 0x24, 0x5c, 0xc2, 0xd3, 0xac, 0x62, 0x91, 0x95, 0xe4, 0x79, 0xe7, 0xc8, 0x37, 0x6d, 0x8d, 0xd5, 0x4e, 0xa9, 0x6c, 0x56, 0xf4, 0xea, 0x65, 0x7a, 0xae, 0x08, 0xba, 0x78, 0x25, 0x2e, 0x1c, 0xa6, 0xb4, 0xc6, 0xe8, 0xdd, 0x74, 0x1f, 0x4b, 0xbd, 0x8b, 0x8a, 0x70, 0x3e, 0xb5, 0x66, 0x48, 0x03, 0xf6, 0x0e, 0x61, 0x35, 0x57, 0xb9, 0x86, 0xc1, 0x1d, 0x9e, 0xe1, 0xf8, 0x98, 0x11, 0x69, 0xd9, 0x8e, 0x94, 0x9b, 0x1e, 0x87, 0xe9, 0xce, 0x55, 0x28, 0xdf, 0x8c, 0xa1, 0x89, 0x0d, 0xbf, 0xe6, 0x42, 0x68, 0x41, 0x99, 0x2d, 0x0f, 0xb0, 0x54, 0xbb, 0x16 |]", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Supporting Sail Code", + "line_range": [ + 4310, + 4331 + ] + }, + { + "text": "let aessboxinvtable : list(bits(8)) = [| 0x52, 0x09, 0x6a, 0xd5, 0x30, 0x36, 0xa5, 0x38, 0xbf, 0x40, 0xa3, 0x9e, 0x81, 0xf3, 0xd7, 0xfb, 0x7c, 0xe3, 0x39, 0x82, 0x9b, 0x2f, 0xff, 0x87, 0x34, 0x8e, 0x43, 0x44, 0xc4, 0xde, 0xe9, 0xcb, 0x54, 0x7b, 0x94, 0x32, 0xa6, 0xc2, 0x23, 0x3d, 0xee, 0x4c, 0x95, 0x0b, 0x42, 0xfa, 0xc3, 0x4e, 0x08, 0x2e, 0xa1, 0x66, 0x28, 0xd9, 0x24, 0xb2, 0x76, 0x5b, 0xa2, 0x49, 0x6d, 0x8b, 0xd1, 0x25, 0x72, 0xf8, 0xf6, 0x64, 0x86, 0x68, 0x98, 0x16, 0xd4, 0xa4, 0x5c, 0xcc, 0x5d, 0x65, 0xb6, 0x92, 0x6c, 0x70, 0x48, 0x50, 0xfd, 0xed, 0xb9, 0xda, 0x5e, 0x15, 0x46, 0x57, 0xa7, 0x8d, 0x9d, 0x84, 0x90, 0xd8, 0xab, 0x00, 0x8c, 0xbc, 0xd3, 0x0a, 0xf7, 0xe4, 0x58, 0x05, 0xb8, 0xb3, 0x45, 0x06, 0xd0, 0x2c, 0x1e, 0x8f, 0xca, 0x3f, 0x0f, 0x02, 0xc1, 0xaf, 0xbd, 0x03, 0x01, 0x13, 0x8a, 0x6b, 0x3a, 0x91, 0x11, 0x41, 0x4f, 0x67, 0xdc, 0xea, 0x97, 0xf2, 0xcf, 0xce, 0xf0, 0xb4, 0xe6, 0x73, 0x96, 0xac, 0x74, 0x22, 0xe7, 0xad, 0x35, 0x85, 0xe2, 0xf9, 0x37, 0xe8, 0x1c, 0x75, 0xdf, 0x6e, 0x47, 0xf1, 0x1a, 0x71, 0x1d, 0x29, 0xc5, 0x89, 0x6f, 0xb7, 0x62, 0x0e, 0xaa, 0x18, 0xbe, 0x1b, 0xfc, 0x56, 0x3e, 0x4b, 0xc6, 0xd2, 0x79, 0x20, 0x9a, 0xdb, 0xc0, 0xfe, 0x78, 0xcd, 0x5a, 0xf4, 0x1f, 0xdd, 0xa8, 0x33, 0x88, 0x07, 0xc7, 0x31, 0xb1, 0x12, 0x10, 0x59, 0x27, 0x80, 0xec, 0x5f, 0x60, 0x51, 0x7f, 0xa9, 0x19, 0xb5, 0x4a, 0x0d, 0x2d, 0xe5, 0x7a, 0x9f, 0x93, 0xc9, 0x9c, 0xef, 0xa0, 0xe0, 0x3b, 0x4d, 0xae, 0x2a, 0xf5, 0xb0, 0xc8, 0xeb, 0xbb, 0x3c, 0x83, 0x53, 0x99, 0x61, 0x17, 0x2b, 0x04, 0x7e, 0xba, 0x77, 0xd6, 0x26, 0xe1, 0x69, 0x14, 0x63, 0x55, 0x21, 0x0c, 0x7d |]", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Supporting Sail Code", + "line_range": [ + 4333, + 4354 + ] + }, + { + "text": "val sboxlookup : (bits(8), list(bits(8))) -> bits(8) function sboxlookup(x, table) = { match (x, table) { (0x00, t0::tn) => t0, ( y, t0::tn) => sboxlookup(x - 0x01, tn) } }", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Supporting Sail Code", + "line_range": [ + 4356, + 4365 + ] + }, + { + "text": "val aessboxfwd : bits(8) -> bits(8) function aessboxfwd(x) = sboxlookup(x, aessboxfwdtable)", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Supporting Sail Code", + "line_range": [ + 4367, + 4369 + ] + }, + { + "text": "val aessboxinv : bits(8) -> bits(8) function aessboxinv(x) = sboxlookup(x, aessboxinvtable)", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Supporting Sail Code", + "line_range": [ + 4371, + 4373 + ] + }, + { + "text": "val aessubwordfwd : bits(32) -> bits(32) function aessubwordfwd(x) = { aessboxfwd(x[31..24]) @ aessboxfwd(x[23..16]) @ aessboxfwd(x[15.. 8]) @ aessboxfwd(x[ 7.. 0]) }", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Supporting Sail Code", + "line_range": [ + 4375, + 4384 + ] + }, + { + "text": "val aessubwordinv : bits(32) -> bits(32) function aessubwordinv(x) = { aessboxinv(x[31..24]) @ aessboxinv(x[23..16]) @ aessboxinv(x[15.. 8]) @ aessboxinv(x[ 7.. 0]) }", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Supporting Sail Code", + "line_range": [ + 4386, + 4395 + ] + }, + { + "text": "val sm4sbox : bits(8) -> bits(8) function sm4sbox(x) = sboxlookup(x, sm4sboxtable)", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Supporting Sail Code", + "line_range": [ + 4397, + 4399 + ] + }, + { + "text": "val aesgetcolumn : (bits(128), nat) -> bits(32) function aesgetcolumn(state,c) = (state >> (tobits(7, 32 * c)))[31..0]", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Supporting Sail Code", + "line_range": [ + 4401, + 4402 + ] + }, + { + "text": "val aesapplyfwdsboxtoeachbyte : bits(64) -> bits(64) function aesapplyfwdsboxtoeachbyte(x) = { aessboxfwd(x[63..56]) @ aessboxfwd(x[55..48]) @ aessboxfwd(x[47..40]) @ aessboxfwd(x[39..32]) @ aessboxfwd(x[31..24]) @ aessboxfwd(x[23..16]) @ aessboxfwd(x[15.. 8]) @ aessboxfwd(x[ 7.. 0]) }", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Supporting Sail Code", + "line_range": [ + 4404, + 4417 + ] + }, + { + "text": "val aesapplyinvsboxtoeachbyte : bits(64) -> bits(64) function aesapplyinvsboxtoeachbyte(x) = { aessboxinv(x[63..56]) @ aessboxinv(x[55..48]) @ aessboxinv(x[47..40]) @ aessboxinv(x[39..32]) @ aessboxinv(x[31..24]) @ aessboxinv(x[23..16]) @ aessboxinv(x[15.. 8]) @ aessboxinv(x[ 7.. 0]) }", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Supporting Sail Code", + "line_range": [ + 4419, + 4432 + ] + }, + { + "text": "val getbyte : (bits(64), int) -> bits(8) function getbyte(x, i) = (x >> tobits(6, i * 8))[7..0]", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Supporting Sail Code", + "line_range": [ + 4438, + 4439 + ] + }, + { + "text": "val aesrv64shiftrowsfwd : (bits(64), bits(64)) -> bits(64) function aesrv64shiftrowsfwd(rs2, rs1) = { getbyte(rs1, 3) @ getbyte(rs2, 6) @ getbyte(rs2, 1) @ getbyte(rs1, 4) @ getbyte(rs2, 7) @ getbyte(rs2, 2) @ getbyte(rs1, 5) @ getbyte(rs1, 0) }", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Supporting Sail Code", + "line_range": [ + 4441, + 4451 + ] + }, + { + "text": "val aesrv64shiftrowsinv : (bits(64), bits(64)) -> bits(64) function aesrv64shiftrowsinv(rs2, rs1) = { getbyte(rs2, 3) @ getbyte(rs2, 6) @ getbyte(rs1, 1) @ getbyte(rs1, 4) @ getbyte(rs1, 7) @ getbyte(rs2, 2) @ getbyte(rs2, 5) @ getbyte(rs1, 0) }", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Supporting Sail Code", + "line_range": [ + 4453, + 4463 + ] + }, + { + "text": "val aesshiftrowsfwd : bits(128) -> bits(128) function aesshiftrowsfwd(x) = { let ic3 : bits(32) = aesgetcolumn(x, 3); let ic2 : bits(32) = aesgetcolumn(x, 2); let ic1 : bits(32) = aesgetcolumn(x, 1); let ic0 : bits(32) = aesgetcolumn(x, 0); let oc0 : bits(32) = ic3[31..24] @ ic2[23..16] @ ic1[15.. 8] @ ic0[ 7.. 0]; let oc1 : bits(32) = ic0[31..24] @ ic3[23..16] @ ic2[15.. 8] @ ic1[ 7.. 0]; let oc2 : bits(32) = ic1[31..24] @ ic0[23..16] @ ic3[15.. 8] @ ic2[ 7.. 0]; let oc3 : bits(32) = ic2[31..24] @ ic1[23..16] @ ic0[15.. 8] @ ic3[ 7.. 0]; (oc3 @ oc2 @ oc1 @ oc0) }", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Supporting Sail Code", + "line_range": [ + 4465, + 4480 + ] + }, + { + "text": "val aesshiftrowsinv : bits(128) -> bits(128) function aesshiftrowsinv(x) = { let ic3 : bits(32) = aesgetcolumn(x, 3); let ic2 : bits(32) = aesgetcolumn(x, 2); let ic1 : bits(32) = aesgetcolumn(x, 1); let ic0 : bits(32) = aesgetcolumn(x, 0); let oc0 : bits(32) = ic1[31..24] @ ic2[23..16] @ ic3[15.. 8] @ ic0[ 7.. 0]; let oc1 : bits(32) = ic2[31..24] @ ic3[23..16] @ ic0[15.. 8] @ ic1[ 7.. 0]; let oc2 : bits(32) = ic3[31..24] @ ic0[23..16] @ ic1[15.. 8] @ ic2[ 7.. 0]; let oc3 : bits(32) = ic0[31..24] @ ic1[23..16] @ ic2[15.. 8] @ ic3[ 7.. 0]; (oc3 @ oc2 @ oc1 @ oc0) }", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Supporting Sail Code", + "line_range": [ + 4482, + 4497 + ] + }, + { + "text": "val aessubbytesfwd : bits(128) -> bits(128) function aessubbytesfwd(x) = { let oc0 : bits(32) = aessubwordfwd(aesgetcolumn(x, 0)); let oc1 : bits(32) = aessubwordfwd(aesgetcolumn(x, 1)); let oc2 : bits(32) = aessubwordfwd(aesgetcolumn(x, 2)); let oc3 : bits(32) = aessubwordfwd(aesgetcolumn(x, 3)); (oc3 @ oc2 @ oc1 @ oc0) }", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Supporting Sail Code", + "line_range": [ + 4499, + 4509 + ] + }, + { + "text": "val aessubbytesinv : bits(128) -> bits(128) function aessubbytesinv(x) = { let oc0 : bits(32) = aessubwordinv(aesgetcolumn(x, 0)); let oc1 : bits(32) = aessubwordinv(aesgetcolumn(x, 1)); let oc2 : bits(32) = aessubwordinv(aesgetcolumn(x, 2)); let oc3 : bits(32) = aessubwordinv(aesgetcolumn(x, 3)); (oc3 @ oc2 @ oc1 @ oc0) }", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Supporting Sail Code", + "line_range": [ + 4511, + 4521 + ] + }, + { + "text": "val aesmixcolumnsfwd : bits(128) -> bits(128) function aesmixcolumnsfwd(x) = { let oc0 : bits(32) = aesmixcolumnfwd(aesgetcolumn(x, 0)); let oc1 : bits(32) = aesmixcolumnfwd(aesgetcolumn(x, 1)); let oc2 : bits(32) = aesmixcolumnfwd(aesgetcolumn(x, 2)); let oc3 : bits(32) = aesmixcolumnfwd(aesgetcolumn(x, 3)); (oc3 @ oc2 @ oc1 @ oc0) }", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Supporting Sail Code", + "line_range": [ + 4523, + 4533 + ] + }, + { + "text": "val aesmixcolumnsinv : bits(128) -> bits(128) function aesmixcolumnsinv(x) = { let oc0 : bits(32) = aesmixcolumninv(aesgetcolumn(x, 0)); let oc1 : bits(32) = aesmixcolumninv(aesgetcolumn(x, 1)); let oc2 : bits(32) = aesmixcolumninv(aesgetcolumn(x, 2)); let oc3 : bits(32) = aesmixcolumninv(aesgetcolumn(x, 3)); (oc3 @ oc2 @ oc1 @ oc0) }", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Supporting Sail Code", + "line_range": [ + 4535, + 4545 + ] + }, + { + "text": "val aesrotword : bits(32) -> bits(32) function aesrotword(x) = { let a0 : bits (8) = x[ 7.. 0]; let a1 : bits (8) = x[15.. 8]; let a2 : bits (8) = x[23..16]; let a3 : bits (8) = x[31..24]; (a0 @ a3 @ a2 @ a1) }", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Supporting Sail Code", + "line_range": [ + 4550, + 4557 + ] + }, + { + "text": "val brev : bits(SEW) -> bits(SEW) function brev(x) = { let output : bits(SEW) = 0; foreach (i from 0 to SEW-8 by 8) output[i+7..i] = reversebitsinbyte(input[i+7..i]); output }", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Supporting Sail Code", + "line_range": [ + 4559, + 4565 + ] + }, + { + "text": "val reversebitsinbyte : bits(8) -> bits(8) function reversebitsinbyte(x) = { let output : bits(8) = 0; foreach (i from 0 to 7) output[i] = x[7-i]); output }", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Supporting Sail Code", + "line_range": [ + 4567, + 4573 + ] + }, + { + "text": "val rev8 : bits(SEW) -> bits(SEW) function rev8(x) = { // endian swap let output : bits(SEW) = 0; let j = SEW - 1; foreach (k from 0 to (SEW - 8) by 8) { output[k..(k + 7)] = x[(j - 7)..j]; j = j - 8; output } RETIRESUCCESS", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Supporting Sail Code", + "line_range": [ + 4575, + 4584 + ] + }, + { + "text": "val rol32 : bits(32) -> bits(32) function ROL32(x,n) = (X (32 - N))", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Supporting Sail Code", + "line_range": [ + 4586, + 4587 + ] + }, + { + "text": "val sm4subword : bits(32) -> bits(32) function sm4subword(x) = { sm4sbox(x[31..24]) @ sm4sbox(x[23..16]) @ sm4sbox(x[15.. 8]) @ sm4sbox(x[ 7.. 0]) } ----", + "section": "Preamble > Cryptography Extensions: Vector Instructions, Version 1.0 > Supporting Sail Code", + "line_range": [ + 4589, + 4596 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/raw_chunks/src__zc.json b/tools/llm-extraction/data/output/raw_chunks/src__zc.json new file mode 100644 index 0000000000..026d687737 --- /dev/null +++ b/tools/llm-extraction/data/output/raw_chunks/src__zc.json @@ -0,0 +1,3438 @@ +{ + "source_file": "src/zc.adoc", + "total": 429, + "sentences": [ + { + "text": "Zc* is a group of extensions that define subsets of the existing C extension (Zca, Zcd, Zcf) and new extensions which only contain 16-bit encodings.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zc* Overview", + "line_range": [ + 5, + 5 + ] + }, + { + "text": "Zcm* all reuse the encodings for c.fld, c.fsd, c.fldsp, c.fsdsp.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zc* Overview", + "line_range": [ + 7, + 7 + ] + }, + { + "text": ".Zc* extension overview [width=\"100%\",options=header,cols=\"3,1,1,1,1,1,1\"] | |Instruction |Zca |Zcf |Zcd |Zcb |Zcmp |Zcmt 7+|*The Zca extension is added as way to refer to instructions in the C extension that do not include the floating-point loads and stores* |C excl. c.f* |yes | | | | | 7+|*The Zcf extension is added as a way to refer to compressed single-precision floating-point load/stores* |c.flw | |rv32 | | | | |c.flwsp | |rv32 | | | | |c.fsw | |rv32 | | | | |c.fswsp | |rv32 | | | | 7+|*The Zcd extension is added as a way to refer to compressed double-precision floating-point load/stores* |c.fld | | |yes | | | |c.fldsp | | |yes | | | |c.fsd | | |yes | | | |c.fsdsp | | |yes | | | 7+|*Simple operations for use on all architectures* |c.lbu | | | |yes | | |c.lh | | | |yes | | |c.lhu | | | |yes | | |c.sb | | | |yes | | |c.sh | | | |yes | | |c.zext.b | | | |yes | | |c.sext.b | | | |yes | | |c.zext.h | | | |yes | | |c.sext.h | | | |yes | | |c.zext.w | | | |yes | | |c.mul | | | |yes | | |c.not | | | |yes | | 7+|*PUSH/POP and double move which overlap with c.fsdsp.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zc* Overview", + "line_range": [ + 9, + 48 + ] + }, + { + "text": "Complex operations intended for embedded CPUs* |cm.push | | | | |yes | |cm.pop | | | | |yes | |cm.popret | | | | |yes | |cm.popretz | | | | |yes | |cm.mva01s | | | | |yes | |cm.mvsa01 | | | | |yes | 7+|*Table jump which overlaps with c.fsdsp.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zc* Overview", + "line_range": [ + 9, + 48 + ] + }, + { + "text": "Complex operations intended for embedded CPUs* |cm.jt | | | | | |yes |cm.jalt | | | | | |yes |", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zc* Overview", + "line_range": [ + 9, + 48 + ] + }, + { + "text": "The C extension is the superset of the following extensions:", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > C", + "line_range": [ + 53, + 53 + ] + }, + { + "text": "Zca * Zcf if F is specified (RV32 only) * Zcd if D is specified", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > C", + "line_range": [ + 55, + 57 + ] + }, + { + "text": "As C defines the same instructions as Zca, Zcf, and Zcd, the rule is that:", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > C", + "line_range": [ + 59, + 59 + ] + }, + { + "text": "C always implies Zca * C+F implies Zcf (RV32 only) * C+D implies Zcd", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > C", + "line_range": [ + 61, + 63 + ] + }, + { + "text": "The Zce extension is intended to be used for microcontrollers, and includes all relevant Zc extensions.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zce", + "line_range": [ + 68, + 68 + ] + }, + { + "text": "Specifying Zce on RV32 without F includes Zca, Zcb, Zcmp, Zcmt * Specifying Zce on RV32 with F includes Zca, Zcb, Zcmp, Zcmt and Zcf * Specifying Zce on RV64 always includes Zca, Zcb, Zcmp, Zcmt ** Zcf doesn't exist for RV64", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zce", + "line_range": [ + 70, + 73 + ] + }, + { + "text": "Therefore common ISA strings can be updated as follows to include the relevant Zc extensions, for example:", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zce", + "line_range": [ + 75, + 75 + ] + }, + { + "text": "RV32IMCZcbZcmpZcmt is equivalent to RV32IMZce * RV32IMFCZcbZcmpZcmt is equivalent to RV32IMFZce", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zce", + "line_range": [ + 77, + 78 + ] + }, + { + "text": "MISA.C is set if the following extensions are selected:", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > MISA.C", + "line_range": [ + 83, + 83 + ] + }, + { + "text": "* Zca and not F * Zca, Zcf and F (but not D) is specified (RV32 only) * Zca, Zcf and Zcd if D is specified (RV32 only) ** this configuration excludes Zcmp, Zcmt * Zca, Zcd if D is specified (RV64 only) ** this configuration excludes Zcmp, Zcmt", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > MISA.C", + "line_range": [ + 85, + 91 + ] + }, + { + "text": "The Zca extension is added as way to refer to instructions in the C extension that do not include the floating-point loads and stores.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zca", + "line_range": [ + 96, + 96 + ] + }, + { + "text": "Therefore it excluded all 16-bit floating point loads and stores: c.flw, c.flwsp, c.fsw, c.fswsp, c.fld, c.fldsp, c.fsd, c.fsdsp.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zca", + "line_range": [ + 98, + 98 + ] + }, + { + "text": "Zcf is the existing set of compressed single precision floating point loads and stores: c.flw, c.flwsp, c.fsw, c.fswsp.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcf (RV32 only)", + "line_range": [ + 103, + 103 + ] + }, + { + "text": "Zcf is only relevant to RV32, it cannot be specified for RV64.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcf (RV32 only)", + "line_range": [ + 105, + 105 + ] + }, + { + "text": "The Zcf extension depends on the and F extensions.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcf (RV32 only)", + "line_range": [ + 107, + 107 + ] + }, + { + "text": "Zcd is the existing set of compressed double precision floating point loads and stores: c.fld, c.fldsp, c.fsd, c.fsdsp.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcd", + "line_range": [ + 112, + 112 + ] + }, + { + "text": "The Zcd extension depends on the and D extensions.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcd", + "line_range": [ + 114, + 114 + ] + }, + { + "text": "Zcb has simple code-size saving instructions which are easy to implement on all CPUs.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb", + "line_range": [ + 119, + 119 + ] + }, + { + "text": "All encodings are currently reserved for all architectures, and have no conflicts with any existing extensions.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb", + "line_range": [ + 121, + 121 + ] + }, + { + "text": "NOTE: Zcb can be implemented on any CPU as the instructions are 16-bit versions of existing 32-bit instructions from the application class profile.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb", + "line_range": [ + 123, + 123 + ] + }, + { + "text": "The Zcb extension depends on the extension.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb", + "line_range": [ + 125, + 125 + ] + }, + { + "text": "As shown on the individual instruction pages, many of the instructions in Zcb depend upon another extension being implemented.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb", + "line_range": [ + 127, + 127 + ] + }, + { + "text": "For example, c.mul is only implemented if M or Zmmul is implemented, and c.sext.b is only implemented if Zbb is implemented.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb", + "line_range": [ + 127, + 127 + ] + }, + { + "text": "The c.mul encoding uses the CA register format along with other instructions such as c.sub, c.xor etc.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb", + "line_range": [ + 129, + 129 + ] + }, + { + "text": "c.sext.w is a pseudoinstruction for c.addiw rd, 0 (RV64)", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb", + "line_range": [ + 133, + 133 + ] + }, + { + "text": "| |RV32 |RV64 |Mnemonic |Instruction", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb", + "line_range": [ + 135, + 140 + ] + }, + { + "text": "|yes |yes |c.lbu rd', uimm(rs1') |", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb", + "line_range": [ + 142, + 145 + ] + }, + { + "text": "|yes |yes |c.lhu rd', uimm(rs1') |", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb", + "line_range": [ + 147, + 150 + ] + }, + { + "text": "|yes |yes |c.lh rd', uimm(rs1') |", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb", + "line_range": [ + 152, + 155 + ] + }, + { + "text": "|yes |yes |c.sb rs2', uimm(rs1') |", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb", + "line_range": [ + 157, + 160 + ] + }, + { + "text": "|yes |yes |c.sh rs2', uimm(rs1') |", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb", + "line_range": [ + 162, + 165 + ] + }, + { + "text": "|yes |yes |c.zext.b rsd' |", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb", + "line_range": [ + 167, + 170 + ] + }, + { + "text": "|yes |yes |c.sext.b rsd' |", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb", + "line_range": [ + 172, + 175 + ] + }, + { + "text": "|yes |yes |c.zext.h rsd' |", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb", + "line_range": [ + 177, + 180 + ] + }, + { + "text": "|yes |yes |c.sext.h rsd' |", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb", + "line_range": [ + 182, + 185 + ] + }, + { + "text": "|yes |yes |c.mul rsd', rs2' |", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb", + "line_range": [ + 197, + 200 + ] + }, + { + "text": "The Zcmp extension is a set of instructions which may be executed as a series of existing 32-bit RISC-V instructions.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcmp", + "line_range": [ + 209, + 209 + ] + }, + { + "text": "This extension reuses some encodings from c.fsdsp.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcmp", + "line_range": [ + 211, + 212 + ] + }, + { + "text": "Therefore it is incompatible with , which is included when C and D extensions are both present.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcmp", + "line_range": [ + 211, + 212 + ] + }, + { + "text": "NOTE: Zcmp is primarily targeted at embedded class CPUs due to implementation complexity.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcmp", + "line_range": [ + 214, + 214 + ] + }, + { + "text": "Additionally, it is not compatible with application class profiles.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcmp", + "line_range": [ + 214, + 214 + ] + }, + { + "text": "The Zcmp extension depends on the extension.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcmp", + "line_range": [ + 216, + 216 + ] + }, + { + "text": "The PUSH/POP assembly syntax uses several variables, the meaning of which are:", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcmp", + "line_range": [ + 218, + 218 + ] + }, + { + "text": "reglist is a list containing 1 to 13 registers (ra and 0 to 12 s registers) ** valid values: \\{ra}, \\{ra, s0}, \\{ra, s0-s1}, \\{ra, s0-s2}, ..., \\{ra, s0-s8}, \\{ra, s0-s9}, \\{ra, s0-s11} ** note that \\{ra, s0-s10} is not valid, giving 12 lists not 13 for better encoding * stackadj is the total size of the stack frame. ** valid values vary with register list length and the specific encoding, see the instruction pages for details.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcmp", + "line_range": [ + 220, + 224 + ] + }, + { + "text": "| |RV32 |RV64 |Mnemonic |Instruction", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcmp", + "line_range": [ + 226, + 231 + ] + }, + { + "text": "|yes |yes |cm.push \\{reglist}, -stackadj |", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcmp", + "line_range": [ + 233, + 236 + ] + }, + { + "text": "|yes |yes |cm.pop \\{reglist}, stackadj |", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcmp", + "line_range": [ + 238, + 241 + ] + }, + { + "text": "|yes |yes |cm.popret \\{reglist}, stackadj |", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcmp", + "line_range": [ + 243, + 246 + ] + }, + { + "text": "|yes |yes |cm.popretz \\{reglist}, stackadj |", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcmp", + "line_range": [ + 248, + 251 + ] + }, + { + "text": "|yes |yes |cm.mva01s rs1', rs2' |", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcmp", + "line_range": [ + 253, + 256 + ] + }, + { + "text": "|yes |yes |cm.mvsa01 r1s', r2s' |", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcmp", + "line_range": [ + 258, + 261 + ] + }, + { + "text": "Zcmt adds the table jump instructions and also adds the jvt CSR.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcmt", + "line_range": [ + 270, + 271 + ] + }, + { + "text": "The jvt CSR requires a state enable if Smstateen is implemented.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcmt", + "line_range": [ + 270, + 271 + ] + }, + { + "text": "This extension reuses some encodings from c.fsdsp.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcmt", + "line_range": [ + 273, + 274 + ] + }, + { + "text": "Therefore it is incompatible with , which is included when C and D extensions are both present.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcmt", + "line_range": [ + 273, + 274 + ] + }, + { + "text": "NOTE: Zcmt is primarily targeted at embedded class CPUs due to implementation complexity.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcmt", + "line_range": [ + 276, + 276 + ] + }, + { + "text": "Additionally, it is not compatible with RVA profiles.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcmt", + "line_range": [ + 276, + 276 + ] + }, + { + "text": "The Zcmt extension depends on the and Zicsr extensions.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcmt", + "line_range": [ + 278, + 278 + ] + }, + { + "text": "| |RV32 |RV64 |Mnemonic |Instruction", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcmt", + "line_range": [ + 280, + 285 + ] + }, + { + "text": "|yes |yes |cm.jalt index |", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcmt", + "line_range": [ + 292, + 295 + ] + }, + { + "text": "Several instructions in this specification use the following new instruction formats.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zc instruction formats", + "line_range": [ + 302, + 302 + ] + }, + { + "text": "| | Format | instructions | 15:10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | CLB | c.lbu | funct6 3+| rs1' 2+| uimm 3+| rd' 2+| op | CSB | c.sb | funct6 3+| rs1' 2+| uimm 3+| rs2' 2+| op | CLH | c.lhu, c.lh | funct6 3+| rs1' | funct1 | uimm 3+| rd' 2+| op | CSH | c.sh | funct6 3+| rs1' | funct1 | uimm 3+| rs2' 2+| op | CU | c.[sz]ext.*, c.not | funct6 3+| rd'/rs1' 5+| funct5 2+| op | CMMV | cm.mvsa01 cm.mva01s| funct6 3+| r1s' 2+| funct2 3+| r2s' 2+| op | CMJT | cm.jt cm.jalt | funct6 8+| index 2+| op | CMPP | cm.push*, cm.pop* | funct6 2+| funct2 4+| urlist 2+| spimm 2+| op |", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zc instruction formats", + "line_range": [ + 304, + 315 + ] + }, + { + "text": "[insns-clbu,reftext=\"Load unsigned byte, 16-bit encoding\"]", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions", + "line_range": [ + 322, + 322 + ] + }, + { + "text": "Load unsigned byte, 16-bit encoding", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.lbu", + "line_range": [ + 327, + 327 + ] + }, + { + "text": "[wavedrom, , svg] .... {reg:[ { bits: 2, name: 0x0, attr: ['C0'] }, { bits: 3, name: 'rd\\'' }, { bits: 2, name: 'uimm[0|1]' }, { bits: 3, name: 'rs1\\'' }, { bits: 3, name: 0x0 }, { bits: 3, name: 0x4, attr: ['FUNCT3'] }, ],config:{bits:16}} ....", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.lbu", + "line_range": [ + 335, + 345 + ] + }, + { + "text": "The immediate offset is formed as follows:", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.lbu", + "line_range": [ + 347, + 347 + ] + }, + { + "text": "[source,sail] -- uimm[31:2] = 0; uimm[1] = encoding[5]; uimm[0] = encoding[6]; --", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.lbu", + "line_range": [ + 349, + 354 + ] + }, + { + "text": "This instruction loads a byte from the memory address formed by adding rs1' to the zero extended immediate uimm.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.lbu", + "line_range": [ + 358, + 358 + ] + }, + { + "text": "The resulting byte is zero extended to XLEN bits and is written to rd'.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.lbu", + "line_range": [ + 358, + 358 + ] + }, + { + "text": "None //32-bit equivalent: //", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.lbu", + "line_range": [ + 362, + 364 + ] + }, + { + "text": "[source,sail] ---- //This is not SAIL, it's pseudocode.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.lbu", + "line_range": [ + 368, + 370 + ] + }, + { + "text": "The SAIL hasn't been written yet.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.lbu", + "line_range": [ + 368, + 370 + ] + }, + { + "text": "X(rdc) = EXTZ(mem[X(rs1c)+EXTZ(uimm)][7..0]); ----", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.lbu", + "line_range": [ + 372, + 373 + ] + }, + { + "text": "<<< [insns-clhu,reftext=\"Load unsigned halfword, 16-bit encoding\"]", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.lbu", + "line_range": [ + 375, + 376 + ] + }, + { + "text": "Load unsigned halfword, 16-bit encoding", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.lhu", + "line_range": [ + 381, + 381 + ] + }, + { + "text": "[wavedrom, , svg] .... {reg:[ { bits: 2, name: 0x0, attr: ['C0'] }, { bits: 3, name: 'rd\\'' }, { bits: 1, name: 'uimm[1]' }, { bits: 1, name: 0x0 }, { bits: 3, name: 'rs1\\'' }, { bits: 3, name: 0x1 }, { bits: 3, name: 0x4, attr: ['FUNCT3'] }, ],config:{bits:16}} ....", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.lhu", + "line_range": [ + 389, + 400 + ] + }, + { + "text": "The immediate offset is formed as follows:", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.lhu", + "line_range": [ + 402, + 402 + ] + }, + { + "text": "[source,sail] ---- uimm[31:2] = 0; uimm[1] = encoding[5]; uimm[0] = 0; ----", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.lhu", + "line_range": [ + 404, + 409 + ] + }, + { + "text": "This instruction loads a halfword from the memory address formed by adding rs1' to the zero extended immediate uimm.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.lhu", + "line_range": [ + 413, + 413 + ] + }, + { + "text": "The resulting halfword is zero extended to XLEN bits and is written to rd'.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.lhu", + "line_range": [ + 413, + 413 + ] + }, + { + "text": "None //32-bit equivalent: // //", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.lhu", + "line_range": [ + 417, + 420 + ] + }, + { + "text": "[source,sail] -- //This is not SAIL, it's pseudocode.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.lhu", + "line_range": [ + 424, + 426 + ] + }, + { + "text": "The SAIL hasn't been written yet.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.lhu", + "line_range": [ + 424, + 426 + ] + }, + { + "text": "X(rdc) = EXTZ(loadmem[X(rs1c)+EXTZ(uimm)][15..0]); --", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.lhu", + "line_range": [ + 428, + 429 + ] + }, + { + "text": "<<< [insns-clh,reftext=\"Load signed halfword, 16-bit encoding\"]", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.lhu", + "line_range": [ + 431, + 432 + ] + }, + { + "text": "Load signed halfword, 16-bit encoding", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.lh", + "line_range": [ + 437, + 437 + ] + }, + { + "text": "[wavedrom, , svg] .... {reg:[ { bits: 2, name: 0x0, attr: ['C0'] }, { bits: 3, name: 'rd\\'' }, { bits: 1, name: 'uimm[1]' }, { bits: 1, name: 0x1 }, { bits: 3, name: 'rs1\\'' }, { bits: 3, name: 0x1 }, { bits: 3, name: 0x4, attr: ['FUNCT3'] }, ],config:{bits:16}} ....", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.lh", + "line_range": [ + 445, + 456 + ] + }, + { + "text": "The immediate offset is formed as follows:", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.lh", + "line_range": [ + 458, + 458 + ] + }, + { + "text": "[source,sail] ---- uimm[31:2] = 0; uimm[1] = encoding[5]; uimm[0] = 0; ----", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.lh", + "line_range": [ + 460, + 465 + ] + }, + { + "text": "This instruction loads a halfword from the memory address formed by adding rs1' to the zero extended immediate uimm.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.lh", + "line_range": [ + 469, + 469 + ] + }, + { + "text": "The resulting halfword is sign extended to XLEN bits and is written to rd'.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.lh", + "line_range": [ + 469, + 469 + ] + }, + { + "text": "None //32-bit equivalent: // //", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.lh", + "line_range": [ + 473, + 476 + ] + }, + { + "text": "[source,sail] ---- //This is not SAIL, it's pseudocode.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.lh", + "line_range": [ + 480, + 482 + ] + }, + { + "text": "The SAIL hasn't been written yet.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.lh", + "line_range": [ + 480, + 482 + ] + }, + { + "text": "X(rdc) = EXTS(loadmem[X(rs1c)+EXTZ(uimm)][15..0]); ----", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.lh", + "line_range": [ + 484, + 485 + ] + }, + { + "text": "<<< [insns-csb,reftext=\"Store byte, 16-bit encoding\"]", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.lh", + "line_range": [ + 487, + 488 + ] + }, + { + "text": "Store byte, 16-bit encoding", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.sb", + "line_range": [ + 493, + 493 + ] + }, + { + "text": "[wavedrom, , svg] .... {reg:[ { bits: 2, name: 0x0, attr: ['C0'] }, { bits: 3, name: 'rs2\\'' }, { bits: 2, name: 'uimm[0|1]' }, { bits: 3, name: 'rs1\\'' }, { bits: 3, name: 0x2 }, { bits: 3, name: 0x4, attr: ['FUNCT3'] }, ],config:{bits:16}} ....", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.sb", + "line_range": [ + 501, + 511 + ] + }, + { + "text": "The immediate offset is formed as follows:", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.sb", + "line_range": [ + 513, + 513 + ] + }, + { + "text": "[source,sail] ---- uimm[31:2] = 0; uimm[1] = encoding[5]; uimm[0] = encoding[6]; ----", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.sb", + "line_range": [ + 515, + 520 + ] + }, + { + "text": "This instruction stores the least significant byte of rs2' to the memory address formed by adding rs1' to the zero extended immediate uimm.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.sb", + "line_range": [ + 524, + 524 + ] + }, + { + "text": "None // //32-bit equivalent: // //", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.sb", + "line_range": [ + 528, + 532 + ] + }, + { + "text": "[source,sail] -- //This is not SAIL, it's pseudocode.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.sb", + "line_range": [ + 536, + 538 + ] + }, + { + "text": "The SAIL hasn't been written yet.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.sb", + "line_range": [ + 536, + 538 + ] + }, + { + "text": "mem[X(rs1c)+EXTZ(uimm)][7..0] = X(rs2c) --", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.sb", + "line_range": [ + 540, + 541 + ] + }, + { + "text": "<<< [insns-csh,reftext=\"Store halfword, 16-bit encoding\"]", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.sb", + "line_range": [ + 543, + 544 + ] + }, + { + "text": "Store halfword, 16-bit encoding", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.sh", + "line_range": [ + 549, + 549 + ] + }, + { + "text": "[wavedrom, , svg] .... {reg:[ { bits: 2, name: 0x0, attr: ['C0'] }, { bits: 3, name: 'rs2\\'' }, { bits: 1, name: 'uimm[1]' }, { bits: 1, name: '0' }, { bits: 3, name: 'rs1\\'' }, { bits: 3, name: 0x3 }, { bits: 3, name: 0x4, attr: ['FUNCT3'] }, ],config:{bits:16}} ....", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.sh", + "line_range": [ + 557, + 568 + ] + }, + { + "text": "The immediate offset is formed as follows:", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.sh", + "line_range": [ + 570, + 570 + ] + }, + { + "text": "[source,sail] ---- uimm[31:2] = 0; uimm[1] = encoding[5]; uimm[0] = 0; ----", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.sh", + "line_range": [ + 572, + 577 + ] + }, + { + "text": "This instruction stores the least significant halfword of rs2' to the memory address formed by adding rs1' to the zero extended immediate uimm.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.sh", + "line_range": [ + 581, + 581 + ] + }, + { + "text": "None // //32-bit equivalent: // //", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.sh", + "line_range": [ + 585, + 589 + ] + }, + { + "text": "Operation:: [source,sail] ---- //This is not SAIL, it's pseudocode.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.sh", + "line_range": [ + 591, + 594 + ] + }, + { + "text": "The SAIL hasn't been written yet.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.sh", + "line_range": [ + 591, + 594 + ] + }, + { + "text": "mem[X(rs1c)+EXTZ(uimm)][15..0] = X(rs2c) ----", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.sh", + "line_range": [ + 596, + 597 + ] + }, + { + "text": "<<< [insns-czextb,reftext=\"Zero extend byte, 16-bit encoding\"]", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.sh", + "line_range": [ + 599, + 600 + ] + }, + { + "text": "Zero extend byte, 16-bit encoding", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.zext.b", + "line_range": [ + 605, + 605 + ] + }, + { + "text": "[wavedrom, , svg] .... {reg:[ { bits: 2, name: 0x1, attr: ['C1'] }, { bits: 3, name: 0x0, attr: ['C.ZEXT.B'] }, { bits: 2, name: 0x3, attr: ['FUNCT2'] }, { bits: 3, name: 'rd\\'/rs1\\'', attr: ['SRCDST'] }, { bits: 3, name: 0x7 }, { bits: 3, name: 0x4, attr: ['FUNCT3'] }, ],config:{bits:16}} ....", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.zext.b", + "line_range": [ + 613, + 623 + ] + }, + { + "text": "This instruction takes a single source/destination operand.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.zext.b", + "line_range": [ + 627, + 629 + ] + }, + { + "text": "It zero-extends the least-significant byte of the operand to XLEN bits by inserting zeros into all of the bits more significant than 7.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.zext.b", + "line_range": [ + 627, + 629 + ] + }, + { + "text": "[source,asm] ---- andi rd'/rs1', rd'/rs1', 0xff ----", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.zext.b", + "line_range": [ + 637, + 640 + ] + }, + { + "text": "[source,sail] ---- X(rsdc) = EXTZ(X(rsdc)[7..0]); ----", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.zext.b", + "line_range": [ + 644, + 647 + ] + }, + { + "text": "<<< [insns-csextb,reftext=\"Sign extend byte, 16-bit encoding\"]", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.zext.b", + "line_range": [ + 649, + 650 + ] + }, + { + "text": "Sign extend byte, 16-bit encoding", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.sext.b", + "line_range": [ + 655, + 655 + ] + }, + { + "text": "[wavedrom, , svg] .... {reg:[ { bits: 2, name: 0x1, attr: ['C1'] }, { bits: 3, name: 0x1, attr: ['C.SEXT.B'] }, { bits: 2, name: 0x3, attr: ['FUNCT2'] }, { bits: 3, name: 'rd\\'/rs1\\'', attr: ['SRCDST'] }, { bits: 3, name: 0x7 }, { bits: 3, name: 0x4, attr: ['FUNCT3'] }, ],config:{bits:16}} ....", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.sext.b", + "line_range": [ + 663, + 673 + ] + }, + { + "text": "This instruction takes a single source/destination operand.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.sext.b", + "line_range": [ + 677, + 679 + ] + }, + { + "text": "It sign-extends the least-significant byte in the operand to XLEN bits by copying the most-significant bit in the byte (i.e., bit 7) to all of the more-significant bits.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.sext.b", + "line_range": [ + 677, + 679 + ] + }, + { + "text": "Zbb is also required. // //32-bit equivalent: // // from Zbb", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.sext.b", + "line_range": [ + 683, + 687 + ] + }, + { + "text": "The SAIL module variable for rd'/rs1' is called rsdc.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.sext.b", + "line_range": [ + 691, + 691 + ] + }, + { + "text": "[source,sail] ---- X(rsdc) = EXTS(X(rsdc)[7..0]); ----", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.sext.b", + "line_range": [ + 695, + 698 + ] + }, + { + "text": "<<< [insns-czexth,reftext=\"Zero extend halfword, 16-bit encoding\"]", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.sext.b", + "line_range": [ + 700, + 701 + ] + }, + { + "text": "Zero extend halfword, 16-bit encoding", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.zext.h", + "line_range": [ + 706, + 706 + ] + }, + { + "text": "[wavedrom, , svg] .... {reg:[ { bits: 2, name: 0x1, attr: ['C1'] }, { bits: 3, name: 0x2, attr: ['C.ZEXT.H'] }, { bits: 2, name: 0x3, attr: ['FUNCT2'] }, { bits: 3, name: 'rd\\'/rs1\\'', attr: ['SRCDST'] }, { bits: 3, name: 0x7 }, { bits: 3, name: 0x4, attr: ['FUNCT3'] }, ],config:{bits:16}} ....", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.zext.h", + "line_range": [ + 714, + 724 + ] + }, + { + "text": "This instruction takes a single source/destination operand.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.zext.h", + "line_range": [ + 728, + 730 + ] + }, + { + "text": "It zero-extends the least-significant halfword of the operand to XLEN bits by inserting zeros into all of the bits more significant than 15.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.zext.h", + "line_range": [ + 728, + 730 + ] + }, + { + "text": "Zbb is also required. // //32-bit equivalent: // // from Zbb", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.zext.h", + "line_range": [ + 734, + 738 + ] + }, + { + "text": "[source,sail] ---- X(rsdc) = EXTZ(X(rsdc)[15..0]); ----", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.zext.h", + "line_range": [ + 742, + 745 + ] + }, + { + "text": "<<< [insns-csexth,reftext=\"Sign extend halfword, 16-bit encoding\"]", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.zext.h", + "line_range": [ + 747, + 748 + ] + }, + { + "text": "Sign extend halfword, 16-bit encoding", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.sext.h", + "line_range": [ + 753, + 753 + ] + }, + { + "text": "[wavedrom, , svg] .... {reg:[ { bits: 2, name: 0x1, attr: ['C1'] }, { bits: 3, name: 0x3, attr: ['C.SEXT.H'] }, { bits: 2, name: 0x3, attr: ['FUNCT2'] }, { bits: 3, name: 'rd\\'/rs1\\'', attr: ['SRCDST'] }, { bits: 3, name: 0x7 }, { bits: 3, name: 0x4, attr: ['FUNCT3'] }, ],config:{bits:16}} ....", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.sext.h", + "line_range": [ + 761, + 771 + ] + }, + { + "text": "This instruction takes a single source/destination operand.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.sext.h", + "line_range": [ + 775, + 777 + ] + }, + { + "text": "It sign-extends the least-significant halfword in the operand to XLEN bits by copying the most-significant bit in the halfword (i.e., bit 15) to all of the more-significant bits.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.sext.h", + "line_range": [ + 775, + 777 + ] + }, + { + "text": "Zbb is also required. // //32-bit equivalent: // // from Zbb", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.sext.h", + "line_range": [ + 781, + 785 + ] + }, + { + "text": "[source,sail] ---- X(rsdc) = EXTS(X(rsdc)[15..0]); ----", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.sext.h", + "line_range": [ + 789, + 792 + ] + }, + { + "text": "<<< [insns-czextw,reftext=\"Zero extend word, 16-bit encoding\"]", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.sext.h", + "line_range": [ + 794, + 795 + ] + }, + { + "text": "Zero extend word, 16-bit encoding", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.zext.w", + "line_range": [ + 800, + 800 + ] + }, + { + "text": "[wavedrom, , svg] .... {reg:[ { bits: 2, name: 0x1, attr: ['C1'] }, { bits: 3, name: 0x4, attr: ['C.ZEXT.W'] }, { bits: 2, name: 0x3, attr: ['FUNCT2'] }, { bits: 3, name: 'rd\\'/rs1\\'', attr: ['SRCDST'] }, { bits: 3, name: 0x7 }, { bits: 3, name: 0x4, attr: ['FUNCT3'] }, ],config:{bits:16}} ....", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.zext.w", + "line_range": [ + 808, + 818 + ] + }, + { + "text": "This instruction takes a single source/destination operand.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.zext.w", + "line_range": [ + 822, + 824 + ] + }, + { + "text": "It zero-extends the least-significant word of the operand to XLEN bits by inserting zeros into all of the bits more significant than 31.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.zext.w", + "line_range": [ + 822, + 824 + ] + }, + { + "text": "[source,asm] ---- add.uw rd'/rs1', rd'/rs1', zero ----", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.zext.w", + "line_range": [ + 832, + 835 + ] + }, + { + "text": "[source,sail] ---- X(rsdc) = EXTZ(X(rsdc)[31..0]); ----", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.zext.w", + "line_range": [ + 839, + 842 + ] + }, + { + "text": "<<< [insns-cnot,reftext=\"Bitwise not, 16-bit encoding\"]", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.zext.w", + "line_range": [ + 844, + 845 + ] + }, + { + "text": "Bitwise not, 16-bit encoding", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.not", + "line_range": [ + 850, + 850 + ] + }, + { + "text": "[wavedrom, , svg] .... {reg:[ { bits: 2, name: 0x1, attr: ['C1'] }, { bits: 3, name: 0x5, attr: ['C.NOT'] }, { bits: 2, name: 0x3, attr: ['FUNCT2'] }, { bits: 3, name: 'rd\\'/rs1\\'', attr: ['SRCDST'] }, { bits: 3, name: 0x7 }, { bits: 3, name: 0x4, attr: ['FUNCT3'] }, ],config:{bits:16}} ....", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.not", + "line_range": [ + 858, + 868 + ] + }, + { + "text": "This instruction takes the one's complement of rd'/rs1' and writes the result to the same register.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.not", + "line_range": [ + 872, + 872 + ] + }, + { + "text": "[source,asm] ---- xori rd'/rs1', rd'/rs1', -1 ----", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.not", + "line_range": [ + 880, + 883 + ] + }, + { + "text": "[source,sail] ---- X(rsdc) = X(rsdc) XOR -1; ----", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.not", + "line_range": [ + 887, + 890 + ] + }, + { + "text": "<<< [insns-cmul,reftext=\"Multiply, 16-bit encoding\"]", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.not", + "line_range": [ + 892, + 893 + ] + }, + { + "text": "[wavedrom, , svg] .... {reg:[ { bits: 2, name: 0x1, attr: ['C1'] }, { bits: 3, name: 'rs2\\'', attr: ['SRC2'] }, { bits: 2, name: 0x2, attr: ['FUNCT2'] }, { bits: 3, name: 'rd\\'/rs1\\'', attr: ['SRCDST'] }, { bits: 3, name: 0x7 }, { bits: 3, name: 0x4, attr: ['FUNCT3'] }, ],config:{bits:16}} ....", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.mul", + "line_range": [ + 906, + 916 + ] + }, + { + "text": "This instruction multiplies XLEN bits of the source operands from rsd' and rs2' and writes the lowest XLEN bits of the result to rsd'.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.mul", + "line_range": [ + 920, + 920 + ] + }, + { + "text": "M or Zmmul must be configured. // //32-bit equivalent: // //", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.mul", + "line_range": [ + 924, + 928 + ] + }, + { + "text": "[source,sail] ---- let resultwide = tobits(2 * sizeof(xlen), signed(X(rsdc)) * signed(X(rs2c))); X(rsdc) = resultwide[(sizeof(xlen) - 1) .. 0]; ----", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.mul", + "line_range": [ + 932, + 936 + ] + }, + { + "text": "[insns-pushpop,reftext=\"PUSH/POP Register Instructions\"]", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Zcb instructions > c.mul", + "line_range": [ + 940, + 940 + ] + }, + { + "text": "These instructions are collectively referred to as PUSH/POP:", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions", + "line_range": [ + 943, + 943 + ] + }, + { + "text": "The term PUSH refers to cm.push.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions", + "line_range": [ + 950, + 950 + ] + }, + { + "text": "The term POP refers to cm.pop.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions", + "line_range": [ + 952, + 952 + ] + }, + { + "text": "The term POPRET refers to cm.popret and cm.popretz.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions", + "line_range": [ + 954, + 954 + ] + }, + { + "text": "Common details for these instructions are in this section.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions", + "line_range": [ + 956, + 956 + ] + }, + { + "text": "PUSH, POP, POPRET are used to reduce the size of function prologues and epilogues.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > PUSH/POP functional overview", + "line_range": [ + 960, + 960 + ] + }, + { + "text": "The PUSH instruction ** adjusts the stack pointer to create the stack frame ** pushes (stores) the registers specified in the register list to the stack frame", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > PUSH/POP functional overview", + "line_range": [ + 962, + 964 + ] + }, + { + "text": "The POP instruction ** pops (loads) the registers in the register list from the stack frame ** adjusts the stack pointer to destroy the stack frame", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > PUSH/POP functional overview", + "line_range": [ + 966, + 968 + ] + }, + { + "text": "The POPRET instructions ** pop (load) the registers in the register list from the stack frame ** cm.popretz also moves zero into a0 as the return value ** adjust the stack pointer to destroy the stack frame ** execute a ret instruction to return from the function", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > PUSH/POP functional overview", + "line_range": [ + 970, + 974 + ] + }, + { + "text": "This example gives an illustration of the use of PUSH and POPRET.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > Example usage", + "line_range": [ + 979, + 979 + ] + }, + { + "text": "The function processMarkers in the EMBench benchmark picojpeg in the following file on github: https://github.com/embench/embench-iot/blob/master/src/picojpeg/libpicojpeg.c[libpicojpeg.c]", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > Example usage", + "line_range": [ + 981, + 981 + ] + }, + { + "text": "The prologue and epilogue compile with GCC10 to:", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > Example usage", + "line_range": [ + 983, + 983 + ] + }, + { + "text": "0001098a : 1098a: 711d addi sp,sp,-96 ;cm.push(1) 1098c: c8ca sw s2,80(sp) ;cm.push(2) 1098e: c6ce sw s3,76(sp) ;cm.push(3) 10990: c4d2 sw s4,72(sp) ;cm.push(4) 10992: ce86 sw ra,92(sp) ;cm.push(5) 10994: cca2 sw s0,88(sp) ;cm.push(6) 10996: caa6 sw s1,84(sp) ;cm.push(7) 10998: c2d6 sw s5,68(sp) ;cm.push(8) 1099a: c0da sw s6,64(sp) ;cm.push(9) 1099c: de5e sw s7,60(sp) ;cm.push(10) 1099e: dc62 sw s8,56(sp) ;cm.push(11) 109a0: da66 sw s9,52(sp) ;cm.push(12) 109a2: d86a sw s10,48(sp);cm.push(13) 109a4: d66e sw s11,44(sp);cm.push(14) ... 109f4: 4501 li a0,0 ;cm.popretz(1) 109f6: 40f6 lw ra,92(sp) ;cm.popretz(2) 109f8: 4466 lw s0,88(sp) ;cm.popretz(3) 109fa: 44d6 lw s1,84(sp) ;cm.popretz(4) 109fc: 4946 lw s2,80(sp) ;cm.popretz(5) 109fe: 49b6 lw s3,76(sp) ;cm.popretz(6) 10a00: 4a26 lw s4,72(sp) ;cm.popretz(7) 10a02: 4a96 lw s5,68(sp) ;cm.popretz(8) 10a04: 4b06 lw s6,64(sp) ;cm.popretz(9) 10a06: 5bf2 lw s7,60(sp) ;cm.popretz(10) 10a08: 5c62 lw s8,56(sp) ;cm.popretz(11) 10a0a: 5cd2 lw s9,52(sp) ;cm.popretz(12) 10a0c: 5d42 lw s10,48(sp);cm.popretz(13) 10a0e: 5db2 lw s11,44(sp);cm.popretz(14) 10a10: 6125 addi sp,sp,96 ;cm.popretz(15) 10a12: 8082 ret ;cm.popretz(16) ----", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > Example usage", + "line_range": [ + 988, + 1020 + ] + }, + { + "text": "with the GCC option -msave-restore the output is the following:", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > Example usage", + "line_range": [ + 1024, + 1024 + ] + }, + { + "text": "[source,asm] ---- 0001080e : 1080e: 73a012ef jal t0,11f48 10812: 1101 addi sp,sp,-32 ... 10862: 4501 li a0,0 10864: 6105 addi sp,sp,32 10866: 71e0106f j 11f84 ----", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > Example usage", + "line_range": [ + 1026, + 1035 + ] + }, + { + "text": "with PUSH/POPRET this reduces to", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > Example usage", + "line_range": [ + 1037, + 1037 + ] + }, + { + "text": "[source,asm] ---- 0001080e : 1080e: b8fa cm.push \\{ra,s0-s11},-96 ... 10866: bcfa cm.popretz \\{ra,s0-s11}, 96 ----", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > Example usage", + "line_range": [ + 1039, + 1045 + ] + }, + { + "text": "The prologue / epilogue reduce from 60-bytes in the original code, to 14-bytes with -msave-restore, and to 4-bytes with PUSH and POPRET.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > Example usage", + "line_range": [ + 1047, + 1050 + ] + }, + { + "text": "As well as reducing the code-size PUSH and POPRET eliminate the branches from calling the millicode save/restore routines and so may also perform better.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > Example usage", + "line_range": [ + 1047, + 1050 + ] + }, + { + "text": "The instructions all automatically adjust the stack pointer by enough to cover the memory required for the registers being saved or restored.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > Example usage > Stack pointer adjustment handling", + "line_range": [ + 1056, + 1058 + ] + }, + { + "text": "Additionally the spimm field in the encoding allows the stack pointer to be adjusted in additional increments of 16-bytes.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > Example usage > Stack pointer adjustment handling", + "line_range": [ + 1056, + 1058 + ] + }, + { + "text": "There is only a small restricted range available in the encoding; if the range is insufficient then a separate c.addi16sp can be used to increase the range.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > Example usage > Stack pointer adjustment handling", + "line_range": [ + 1056, + 1058 + ] + }, + { + "text": "There is no support for the \\{ra, s0-s10} register list without also adding s11.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > Example usage > Register list handling", + "line_range": [ + 1062, + 1062 + ] + }, + { + "text": "Therefore the \\{ra, s0-s11} register list must be used in this case.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > Example usage > Register list handling", + "line_range": [ + 1062, + 1062 + ] + }, + { + "text": "[pushpop-idempotent-memory]", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > Example usage > Register list handling", + "line_range": [ + 1064, + 1064 + ] + }, + { + "text": "Correct execution requires that sp refers to idempotent memory (also see ), because the core must be able to handle traps detected during the sequence.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > PUSH/POP Fault handling", + "line_range": [ + 1067, + 1070 + ] + }, + { + "text": "The entire PUSH/POP sequence is re-executed after returning from the trap handler, and multiple traps are possible during the sequence.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > PUSH/POP Fault handling", + "line_range": [ + 1067, + 1070 + ] + }, + { + "text": "If a trap occurs during the sequence then xEPC is updated with the PC of the instruction, xTVAL (if not read-only-zero) updated with the bad address if it was an access fault and xCAUSE updated with the type of trap.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > PUSH/POP Fault handling", + "line_range": [ + 1072, + 1072 + ] + }, + { + "text": "NOTE: It is implementation defined whether interrupts can also be taken during the sequence execution.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > PUSH/POP Fault handling", + "line_range": [ + 1074, + 1075 + ] + }, + { + "text": "From a software perspective the PUSH sequence appears as:", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > Software view of execution > Software view of the PUSH sequence", + "line_range": [ + 1082, + 1082 + ] + }, + { + "text": "A sequence of stores writing the bytes required by the pseudocode ** The bytes may be written in any order. ** The bytes may be grouped into larger accesses. ** Any of the bytes may be written multiple times. * A stack pointer adjustment", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > Software view of execution > Software view of the PUSH sequence", + "line_range": [ + 1084, + 1088 + ] + }, + { + "text": "The stack pointer adjustment must only be committed only when it is certain that the entire PUSH instruction will commit.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > Software view of execution > Software view of the PUSH sequence", + "line_range": [ + 1090, + 1090 + ] + }, + { + "text": "Stores may also return imprecise faults from the bus.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > Software view of execution > Software view of the PUSH sequence", + "line_range": [ + 1092, + 1095 + ] + }, + { + "text": "It is platform defined whether the core implementation waits for the bus responses before continuing to the final stage of the sequence, or handles errors responses after completing the PUSH instruction.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > Software view of execution > Software view of the PUSH sequence", + "line_range": [ + 1092, + 1095 + ] + }, + { + "text": "[source,asm] ---- cm.push \\{ra, s0-s5}, -64 ----", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > Software view of execution > Software view of the PUSH sequence", + "line_range": [ + 1101, + 1104 + ] + }, + { + "text": "[source,asm] ---- any bytes from sp-1 to sp-28 may be written multiple times before the instruction completes therefore these updates may be visible in the interrupt/exception handler below the stack pointer sw s5, -4(sp) sw s4, -8(sp) sw s3,-12(sp) sw s2,-16(sp) sw s1,-20(sp) sw s0,-24(sp) sw ra,-28(sp)", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > Software view of execution > Software view of the PUSH sequence", + "line_range": [ + 1108, + 1119 + ] + }, + { + "text": "this must only execute once, and will only execute after all stores completed without any precise faults, therefore this update is only visible in the interrupt/exception handler if cm.push has completed addi sp, sp, -64 ----", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > Software view of execution > Software view of the PUSH sequence", + "line_range": [ + 1121, + 1125 + ] + }, + { + "text": "From a software perspective the POP/POPRET sequence appears as:", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > Software view of execution > Software view of the POP/POPRET sequence", + "line_range": [ + 1129, + 1129 + ] + }, + { + "text": "A sequence of loads reading the bytes required by the pseudocode. ** The bytes may be loaded in any order. ** The bytes may be grouped into larger accesses. ** Any of the bytes may be loaded multiple times. * A stack pointer adjustment * An optional `li a0, 0` * An optional `ret`", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > Software view of execution > Software view of the POP/POPRET sequence", + "line_range": [ + 1131, + 1137 + ] + }, + { + "text": "If a trap occurs during the sequence, then any loads which were executed before the trap may update architectural state.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > Software view of execution > Software view of the POP/POPRET sequence", + "line_range": [ + 1139, + 1141 + ] + }, + { + "text": "The loads will be re-executed once the trap handler completes, so the values will be overwritten.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > Software view of execution > Software view of the POP/POPRET sequence", + "line_range": [ + 1139, + 1141 + ] + }, + { + "text": "Therefore it is permitted for an implementation to update some of the destination registers before taking a fault.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > Software view of execution > Software view of the POP/POPRET sequence", + "line_range": [ + 1139, + 1141 + ] + }, + { + "text": "The optional `li a0, 0`, stack pointer adjustment and optional `ret` must only be committed only when it is certain that the entire POP/POPRET instruction will commit.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > Software view of execution > Software view of the POP/POPRET sequence", + "line_range": [ + 1143, + 1143 + ] + }, + { + "text": "For POPRET once the stack pointer adjustment has been committed the `ret` must execute.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > Software view of execution > Software view of the POP/POPRET sequence", + "line_range": [ + 1145, + 1145 + ] + }, + { + "text": "[source,asm] ---- cm.popretz \\{ra, s0-s3}, 32; ----", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > Software view of execution > Software view of the POP/POPRET sequence", + "line_range": [ + 1150, + 1153 + ] + }, + { + "text": "[source,asm] ---- any or all of these load instructions may execute multiple times therefore these updates may be visible in the interrupt/exception handler lw s3, 28(sp) lw s2, 24(sp) lw s1, 20(sp) lw s0, 16(sp) lw ra, 12(sp)", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > Software view of execution > Software view of the POP/POPRET sequence", + "line_range": [ + 1157, + 1165 + ] + }, + { + "text": "these must only execute once, will only execute after all loads complete successfully all instructions must execute atomically therefore these updates are not visible in the interrupt/exception handler li a0, 0 addi sp, sp, 32 ret ----", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > Software view of execution > Software view of the POP/POPRET sequence", + "line_range": [ + 1167, + 1173 + ] + }, + { + "text": "An implementation may have a requirement to issue a PUSH/POP instruction to non-idempotent memory.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > Non-idempotent memory handling", + "line_range": [ + 1178, + 1178 + ] + }, + { + "text": "If the core implementation does not support PUSH/POP to non-idempotent memories, the core may use an idempotency PMA to detect it and take a load (POP/POPRET) or store (PUSH) access-fault exception in order to avoid unpredictable results.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > Non-idempotent memory handling", + "line_range": [ + 1180, + 1181 + ] + }, + { + "text": "Software should only use these instructions on non-idempotent memory regions when software can tolerate the required memory accesses being issued repeatedly in the case that they cause exceptions.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > Non-idempotent memory handling", + "line_range": [ + 1183, + 1184 + ] + }, + { + "text": "The examples are included show the load/store series expansion and the stack adjustment.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > Example RV32I PUSH/POP sequences", + "line_range": [ + 1190, + 1191 + ] + }, + { + "text": "Examples of cm.popret and cm.popretz are not included, as the difference in the expanded sequence from cm.pop is trivial in all cases.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > Example RV32I PUSH/POP sequences", + "line_range": [ + 1190, + 1191 + ] + }, + { + "text": "Encoding: rlist=7, spimm=3", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > Example RV32I PUSH/POP sequences > cm.push \\{ra, s0-s2}, -64", + "line_range": [ + 1195, + 1195 + ] + }, + { + "text": "[source,asm] ---- sw s2, -4(sp); sw s1, -8(sp); sw s0, -12(sp); sw ra, -16(sp); addi sp, sp, -64; ----", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > Example RV32I PUSH/POP sequences > cm.push \\{ra, s0-s2}, -64", + "line_range": [ + 1199, + 1206 + ] + }, + { + "text": "Encoding: rlist=15, spimm=3", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > Example RV32I PUSH/POP sequences > cm.push \\{ra, s0-s11}, -112", + "line_range": [ + 1210, + 1210 + ] + }, + { + "text": "[source,asm] ---- sw s11, -4(sp); sw s10, -8(sp); sw s9, -12(sp); sw s8, -16(sp); sw s7, -20(sp); sw s6, -24(sp); sw s5, -28(sp); sw s4, -32(sp); sw s3, -36(sp); sw s2, -40(sp); sw s1, -44(sp); sw s0, -48(sp); sw ra, -52(sp); addi sp, sp, -112; ----", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > Example RV32I PUSH/POP sequences > cm.push \\{ra, s0-s11}, -112", + "line_range": [ + 1214, + 1230 + ] + }, + { + "text": "Encoding: rlist=4, spimm=0", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > Example RV32I PUSH/POP sequences > cm.pop \\{ra}, 16", + "line_range": [ + 1236, + 1236 + ] + }, + { + "text": "[source,asm] ---- lw ra, 12(sp); addi sp, sp, 16; ----", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > Example RV32I PUSH/POP sequences > cm.pop \\{ra}, 16", + "line_range": [ + 1240, + 1244 + ] + }, + { + "text": "Encoding: rlist=8, spimm=1", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > Example RV32I PUSH/POP sequences > cm.pop \\{ra, s0-s3}, 48", + "line_range": [ + 1248, + 1248 + ] + }, + { + "text": "[source,asm] ---- lw s3, 44(sp); lw s2, 40(sp); lw s1, 36(sp); lw s0, 32(sp); lw ra, 28(sp); addi sp, sp, 48; ----", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > Example RV32I PUSH/POP sequences > cm.pop \\{ra, s0-s3}, 48", + "line_range": [ + 1252, + 1260 + ] + }, + { + "text": "Encoding: rlist=9, spimm=2", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > Example RV32I PUSH/POP sequences > cm.pop \\{ra, s0-s4}, 64", + "line_range": [ + 1264, + 1264 + ] + }, + { + "text": "[source,asm] ---- lw s4, 60(sp); lw s3, 56(sp); lw s2, 52(sp); lw s1, 48(sp); lw s0, 44(sp); lw ra, 40(sp); addi sp, sp, 64; ----", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > Example RV32I PUSH/POP sequences > cm.pop \\{ra, s0-s4}, 64", + "line_range": [ + 1268, + 1277 + ] + }, + { + "text": "<<< [insns-cmpush,reftext=\"cm.push\"]", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > Example RV32I PUSH/POP sequences > cm.pop \\{ra, s0-s4}, 64", + "line_range": [ + 1279, + 1280 + ] + }, + { + "text": "Create stack frame: store ra and 0 to 12 saved registers to the stack frame, optionally allocate additional stack space.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.push", + "line_range": [ + 1286, + 1286 + ] + }, + { + "text": "cm.push \\{reglist}, -stackadj", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.push", + "line_range": [ + 1290, + 1290 + ] + }, + { + "text": "[wavedrom, , svg] .... {reg:[ { bits: 2, name: 0x2, attr: ['C2'] }, { bits: 2, name: 'spimm', attr: [] }, { bits: 4, name: 'rlist', attr: [] }, { bits: 5, name: 0x18, attr: [] }, { bits: 3, name: 0x5, attr: ['FUNCT3'] }, ],config:{bits:16}} ....", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.push", + "line_range": [ + 1294, + 1303 + ] + }, + { + "text": "[source,asm] -- cm.push \\{reglist}, -stackadj cm.push {xreglist}, -stackadj --", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.push", + "line_range": [ + 1307, + 1311 + ] + }, + { + "text": "The variables used in the assembly syntax are defined below.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.push", + "line_range": [ + 1313, + 1313 + ] + }, + { + "text": "switch (rlist){ case 4: \\{reglist=\"ra\"; xreglist=\"x1\";} case 5: \\{reglist=\"ra, s0\"; xreglist=\"x1, x8\";} case 6: \\{reglist=\"ra, s0-s1\"; xreglist=\"x1, x8-x9\";} default: reserved(); } stackadj = stackadjbase + spimm * 16; ----", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.push", + "line_range": [ + 1319, + 1326 + ] + }, + { + "text": "[source,sail] ---- RV32I, RV64: switch (rlist){ case 4: \\{reglist=\"ra\"; xreglist=\"x1\";} case 5: \\{reglist=\"ra, s0\"; xreglist=\"x1, x8\";} case 6: \\{reglist=\"ra, s0-s1\"; xreglist=\"x1, x8-x9\";} case 7: \\{reglist=\"ra, s0-s2\"; xreglist=\"x1, x8-x9, x18\";} case 8: \\{reglist=\"ra, s0-s3\"; xreglist=\"x1, x8-x9, x18-x19\";} case 9: \\{reglist=\"ra, s0-s4\"; xreglist=\"x1, x8-x9, x18-x20\";} case 10: \\{reglist=\"ra, s0-s5\"; xreglist=\"x1, x8-x9, x18-x21\";} case 11: \\{reglist=\"ra, s0-s6\"; xreglist=\"x1, x8-x9, x18-x22\";} case 12: \\{reglist=\"ra, s0-s7\"; xreglist=\"x1, x8-x9, x18-x23\";} case 13: \\{reglist=\"ra, s0-s8\"; xreglist=\"x1, x8-x9, x18-x24\";} case 14: \\{reglist=\"ra, s0-s9\"; xreglist=\"x1, x8-x9, x18-x25\";} //note - to include s10, s11 must also be included case 15: \\{reglist=\"ra, s0-s11\"; xreglist=\"x1, x8-x9, x18-x27\";} default: reserved(); } stackadj = stackadjbase + spimm * 16; ----", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.push", + "line_range": [ + 1328, + 1348 + ] + }, + { + "text": "Valid values: stackadj = [16|32|48|64]; ----", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.push", + "line_range": [ + 1354, + 1357 + ] + }, + { + "text": "switch (rlist) { case 4.. 7: stackadjbase = 16; case 8..11: stackadjbase = 32; case 12..14: stackadjbase = 48; case 15: stackadjbase = 64; }", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.push", + "line_range": [ + 1363, + 1368 + ] + }, + { + "text": "Valid values: switch (rlist) { case 4.. 7: stackadj = [16|32|48| 64]; case 8..11: stackadj = [32|48|64| 80]; case 12..14: stackadj = [48|64|80| 96]; case 15: stackadj = [64|80|96|112]; } ----", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.push", + "line_range": [ + 1370, + 1377 + ] + }, + { + "text": "switch (rlist) { case 4.. 5: stackadjbase = 16; case 6.. 7: stackadjbase = 32; case 8.. 9: stackadjbase = 48; case 10..11: stackadjbase = 64; case 12..13: stackadjbase = 80; case 14: stackadjbase = 96; case 15: stackadjbase = 112; }", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.push", + "line_range": [ + 1383, + 1391 + ] + }, + { + "text": "Valid values: switch (rlist) { case 4.. 5: stackadj = [ 16| 32| 48| 64]; case 6.. 7: stackadj = [ 32| 48| 64| 80]; case 8.. 9: stackadj = [ 48| 64| 80| 96]; case 10..11: stackadj = [ 64| 80| 96|112]; case 12..13: stackadj = [ 80| 96|112|128]; case 14: stackadj = [ 96|112|128|144]; case 15: stackadj = [112|128|144|160]; } ----", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.push", + "line_range": [ + 1393, + 1403 + ] + }, + { + "text": "This instruction pushes (stores) the registers in reglist to the memory below the stack pointer, and then creates the stack frame by decrementing the stack pointer by stackadj, including any additional stack space requested by the value of spimm.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.push", + "line_range": [ + 1408, + 1410 + ] + }, + { + "text": "For further information see .", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.push", + "line_range": [ + 1412, + 1412 + ] + }, + { + "text": "Stack Adjustment Calculation:", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.push", + "line_range": [ + 1414, + 1414 + ] + }, + { + "text": "stackadjbase is the minimum number of bytes, in multiples of 16-byte address increments, required to cover the registers in the list.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.push", + "line_range": [ + 1416, + 1416 + ] + }, + { + "text": "spimm is the number of additional 16-byte address increments allocated for the stack frame.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.push", + "line_range": [ + 1418, + 1418 + ] + }, + { + "text": "The total stack adjustment represents the total size of the stack frame, which is stackadjbase added to spimm scaled by 16, as defined above.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.push", + "line_range": [ + 1420, + 1421 + ] + }, + { + "text": "No direct equivalent encoding exists", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.push", + "line_range": [ + 1429, + 1429 + ] + }, + { + "text": "The first section of pseudocode may be executed multiple times before the instruction successfully completes.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.push", + "line_range": [ + 1433, + 1433 + ] + }, + { + "text": "[source,sail] ---- //This is not SAIL, it's pseudocode.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.push", + "line_range": [ + 1435, + 1437 + ] + }, + { + "text": "The SAIL hasn't been written yet.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.push", + "line_range": [ + 1435, + 1437 + ] + }, + { + "text": "if (XLEN32) bytes=4; else bytes=8;", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.push", + "line_range": [ + 1439, + 1439 + ] + }, + { + "text": "addr=sp-bytes; for(i in 27,26,25,24,23,22,21,20,19,18,9,8,1) { //if register i is in xreglist if (xreglist[i]) { switch(bytes) { 4: asm(\"sw x[i], 0(addr)\"); 8: asm(\"sd x[i], 0(addr)\"); } addr-=bytes; } } ----", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.push", + "line_range": [ + 1441, + 1452 + ] + }, + { + "text": "The final section of pseudocode executes atomically, and only executes if the section above completes without any exceptions or interrupts.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.push", + "line_range": [ + 1454, + 1454 + ] + }, + { + "text": "[source,sail] ---- //This is not SAIL, it's pseudocode.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.push", + "line_range": [ + 1456, + 1458 + ] + }, + { + "text": "The SAIL hasn't been written yet.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.push", + "line_range": [ + 1456, + 1458 + ] + }, + { + "text": "<<< [insns-cmpop,reftext=\"cm.pop\"]", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.push", + "line_range": [ + 1463, + 1464 + ] + }, + { + "text": "Destroy stack frame: load ra and 0 to 12 saved registers from the stack frame, deallocate the stack frame.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.pop", + "line_range": [ + 1470, + 1470 + ] + }, + { + "text": "cm.pop \\{reglist}, stackadj", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.pop", + "line_range": [ + 1474, + 1474 + ] + }, + { + "text": "[wavedrom, , svg] .... {reg:[ { bits: 2, name: 0x2, attr: ['C2'] }, { bits: 2, name: 'spimm', attr: [] }, { bits: 4, name: 'rlist', attr: [] }, { bits: 5, name: 0x1a, attr: [] }, { bits: 3, name: 0x5, attr: ['FUNCT3'] }, ],config:{bits:16}} ....", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.pop", + "line_range": [ + 1478, + 1487 + ] + }, + { + "text": "[source,asm] ---- cm.pop \\{reglist}, stackadj cm.pop {xreglist}, stackadj ----", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.pop", + "line_range": [ + 1491, + 1495 + ] + }, + { + "text": "The variables used in the assembly syntax are defined below.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.pop", + "line_range": [ + 1497, + 1497 + ] + }, + { + "text": "[source,sail] ---- RV32E: switch (rlist){ case 4: \\{reglist=\"ra\"; xreglist=\"x1\";} case 5: \\{reglist=\"ra, s0\"; xreglist=\"x1, x8\";} case 6: \\{reglist=\"ra, s0-s1\"; xreglist=\"x1, x8-x9\";} default: reserved(); } stackadj = stackadjbase + spimm * 16; ----", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.pop", + "line_range": [ + 1499, + 1509 + ] + }, + { + "text": "[source,sail] ---- RV32I, RV64: switch (rlist){ case 4: \\{reglist=\"ra\"; xreglist=\"x1\";} case 5: \\{reglist=\"ra, s0\"; xreglist=\"x1, x8\";} case 6: \\{reglist=\"ra, s0-s1\"; xreglist=\"x1, x8-x9\";} case 7: \\{reglist=\"ra, s0-s2\"; xreglist=\"x1, x8-x9, x18\";} case 8: \\{reglist=\"ra, s0-s3\"; xreglist=\"x1, x8-x9, x18-x19\";} case 9: \\{reglist=\"ra, s0-s4\"; xreglist=\"x1, x8-x9, x18-x20\";} case 10: \\{reglist=\"ra, s0-s5\"; xreglist=\"x1, x8-x9, x18-x21\";} case 11: \\{reglist=\"ra, s0-s6\"; xreglist=\"x1, x8-x9, x18-x22\";} case 12: \\{reglist=\"ra, s0-s7\"; xreglist=\"x1, x8-x9, x18-x23\";} case 13: \\{reglist=\"ra, s0-s8\"; xreglist=\"x1, x8-x9, x18-x24\";} case 14: \\{reglist=\"ra, s0-s9\"; xreglist=\"x1, x8-x9, x18-x25\";} //note - to include s10, s11 must also be included case 15: \\{reglist=\"ra, s0-s11\"; xreglist=\"x1, x8-x9, x18-x27\";} default: reserved(); } stackadj = stackadjbase + spimm * 16; ----", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.pop", + "line_range": [ + 1511, + 1531 + ] + }, + { + "text": "Valid values: stackadj = [16|32|48|64]; ----", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.pop", + "line_range": [ + 1537, + 1540 + ] + }, + { + "text": "switch (rlist) { case 4.. 7: stackadjbase = 16; case 8..11: stackadjbase = 32; case 12..14: stackadjbase = 48; case 15: stackadjbase = 64; }", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.pop", + "line_range": [ + 1546, + 1551 + ] + }, + { + "text": "Valid values: switch (rlist) { case 4.. 7: stackadj = [16|32|48| 64]; case 8..11: stackadj = [32|48|64| 80]; case 12..14: stackadj = [48|64|80| 96]; case 15: stackadj = [64|80|96|112]; } ----", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.pop", + "line_range": [ + 1553, + 1560 + ] + }, + { + "text": "switch (rlist) { case 4.. 5: stackadjbase = 16; case 6.. 7: stackadjbase = 32; case 8.. 9: stackadjbase = 48; case 10..11: stackadjbase = 64; case 12..13: stackadjbase = 80; case 14: stackadjbase = 96; case 15: stackadjbase = 112; }", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.pop", + "line_range": [ + 1566, + 1574 + ] + }, + { + "text": "Valid values: switch (rlist) { case 4.. 5: stackadj = [ 16| 32| 48| 64]; case 6.. 7: stackadj = [ 32| 48| 64| 80]; case 8.. 9: stackadj = [ 48| 64| 80| 96]; case 10..11: stackadj = [ 64| 80| 96|112]; case 12..13: stackadj = [ 80| 96|112|128]; case 14: stackadj = [ 96|112|128|144]; case 15: stackadj = [112|128|144|160]; } ----", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.pop", + "line_range": [ + 1576, + 1586 + ] + }, + { + "text": "This instruction pops (loads) the registers in reglist from stack memory, and then adjusts the stack pointer by stackadj.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.pop", + "line_range": [ + 1592, + 1593 + ] + }, + { + "text": "For further information see .", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.pop", + "line_range": [ + 1595, + 1595 + ] + }, + { + "text": "Stack Adjustment Calculation:", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.pop", + "line_range": [ + 1597, + 1597 + ] + }, + { + "text": "stackadjbase is the minimum number of bytes, in multiples of 16-byte address increments, required to cover the registers in the list.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.pop", + "line_range": [ + 1599, + 1599 + ] + }, + { + "text": "spimm is the number of additional 16-byte address increments allocated for the stack frame.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.pop", + "line_range": [ + 1601, + 1601 + ] + }, + { + "text": "The total stack adjustment represents the total size of the stack frame, which is stackadjbase added to spimm scaled by 16, as defined above.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.pop", + "line_range": [ + 1603, + 1604 + ] + }, + { + "text": "No direct equivalent encoding exists", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.pop", + "line_range": [ + 1612, + 1612 + ] + }, + { + "text": "The first section of pseudocode may be executed multiple times before the instruction successfully completes.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.pop", + "line_range": [ + 1616, + 1616 + ] + }, + { + "text": "[source,sail] ---- //This is not SAIL, it's pseudocode.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.pop", + "line_range": [ + 1618, + 1620 + ] + }, + { + "text": "The SAIL hasn't been written yet.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.pop", + "line_range": [ + 1618, + 1620 + ] + }, + { + "text": "if (XLEN32) bytes=4; else bytes=8;", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.pop", + "line_range": [ + 1622, + 1622 + ] + }, + { + "text": "addr=sp+stackadj-bytes; for(i in 27,26,25,24,23,22,21,20,19,18,9,8,1) { //if register i is in xreglist if (xreglist[i]) { switch(bytes) { 4: asm(\"lw x[i], 0(addr)\"); 8: asm(\"ld x[i], 0(addr)\"); } addr-=bytes; } } ----", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.pop", + "line_range": [ + 1624, + 1635 + ] + }, + { + "text": "The final section of pseudocode executes atomically, and only executes if the section above completes without any exceptions or interrupts.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.pop", + "line_range": [ + 1637, + 1637 + ] + }, + { + "text": "[source,sail] ---- //This is not SAIL, it's pseudocode.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.pop", + "line_range": [ + 1639, + 1641 + ] + }, + { + "text": "The SAIL hasn't been written yet.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.pop", + "line_range": [ + 1639, + 1641 + ] + }, + { + "text": "<<< [insns-cmpopretz,reftext=\"cm.popretz\"]", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.pop", + "line_range": [ + 1646, + 1647 + ] + }, + { + "text": "Destroy stack frame: load ra and 0 to 12 saved registers from the stack frame, deallocate the stack frame, move zero into a0, return to ra.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.popretz", + "line_range": [ + 1652, + 1652 + ] + }, + { + "text": "cm.popretz \\{reglist}, stackadj", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.popretz", + "line_range": [ + 1656, + 1656 + ] + }, + { + "text": "[wavedrom, , svg] .... {reg:[ { bits: 2, name: 0x2, attr: ['C2'] }, { bits: 2, name: 'spimm\\[5:4\\]', attr: [] }, { bits: 4, name: 'rlist', attr: [] }, { bits: 5, name: 0x1c, attr: [] }, { bits: 3, name: 0x5, attr: ['FUNCT3'] }, ],config:{bits:16}} ....", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.popretz", + "line_range": [ + 1660, + 1669 + ] + }, + { + "text": "[source,sail] ---- cm.popretz \\{reglist}, stackadj cm.popretz {xreglist}, stackadj ----", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.popretz", + "line_range": [ + 1673, + 1677 + ] + }, + { + "text": "[source,sail] ---- RV32E: switch (rlist){ case 4: \\{reglist=\"ra\"; xreglist=\"x1\";} case 5: \\{reglist=\"ra, s0\"; xreglist=\"x1, x8\";} case 6: \\{reglist=\"ra, s0-s1\"; xreglist=\"x1, x8-x9\";} default: reserved(); } stackadj = stackadjbase + spimm * 16; ----", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.popretz", + "line_range": [ + 1679, + 1689 + ] + }, + { + "text": "[source,sail] ---- RV32I, RV64:", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.popretz", + "line_range": [ + 1691, + 1693 + ] + }, + { + "text": "switch (rlist){ case 4: \\{reglist=\"ra\"; xreglist=\"x1\";} case 5: \\{reglist=\"ra, s0\"; xreglist=\"x1, x8\";} case 6: \\{reglist=\"ra, s0-s1\"; xreglist=\"x1, x8-x9\";} case 7: \\{reglist=\"ra, s0-s2\"; xreglist=\"x1, x8-x9, x18\";} case 8: \\{reglist=\"ra, s0-s3\"; xreglist=\"x1, x8-x9, x18-x19\";} case 9: \\{reglist=\"ra, s0-s4\"; xreglist=\"x1, x8-x9, x18-x20\";} case 10: \\{reglist=\"ra, s0-s5\"; xreglist=\"x1, x8-x9, x18-x21\";} case 11: \\{reglist=\"ra, s0-s6\"; xreglist=\"x1, x8-x9, x18-x22\";} case 12: \\{reglist=\"ra, s0-s7\"; xreglist=\"x1, x8-x9, x18-x23\";} case 13: \\{reglist=\"ra, s0-s8\"; xreglist=\"x1, x8-x9, x18-x24\";} case 14: \\{reglist=\"ra, s0-s9\"; xreglist=\"x1, x8-x9, x18-x25\";} //note - to include s10, s11 must also be included case 15: \\{reglist=\"ra, s0-s11\"; xreglist=\"x1, x8-x9, x18-x27\";} default: reserved(); } stackadj = stackadjbase + spimm * 16; ----", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.popretz", + "line_range": [ + 1695, + 1712 + ] + }, + { + "text": "Valid values: stackadj = [16|32|48|64]; ----", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.popretz", + "line_range": [ + 1718, + 1721 + ] + }, + { + "text": "switch (rlist) { case 4.. 7: stackadjbase = 16; case 8..11: stackadjbase = 32; case 12..14: stackadjbase = 48; case 15: stackadjbase = 64; }", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.popretz", + "line_range": [ + 1727, + 1732 + ] + }, + { + "text": "Valid values: switch (rlist) { case 4.. 7: stackadj = [16|32|48| 64]; case 8..11: stackadj = [32|48|64| 80]; case 12..14: stackadj = [48|64|80| 96]; case 15: stackadj = [64|80|96|112]; } ----", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.popretz", + "line_range": [ + 1734, + 1741 + ] + }, + { + "text": "switch (rlist) { case 4.. 5: stackadjbase = 16; case 6.. 7: stackadjbase = 32; case 8.. 9: stackadjbase = 48; case 10..11: stackadjbase = 64; case 12..13: stackadjbase = 80; case 14: stackadjbase = 96; case 15: stackadjbase = 112; }", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.popretz", + "line_range": [ + 1747, + 1755 + ] + }, + { + "text": "Valid values: switch (rlist) { case 4.. 5: stackadj = [ 16| 32| 48| 64]; case 6.. 7: stackadj = [ 32| 48| 64| 80]; case 8.. 9: stackadj = [ 48| 64| 80| 96]; case 10..11: stackadj = [ 64| 80| 96|112]; case 12..13: stackadj = [ 80| 96|112|128]; case 14: stackadj = [ 96|112|128|144]; case 15: stackadj = [112|128|144|160]; } ----", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.popretz", + "line_range": [ + 1757, + 1767 + ] + }, + { + "text": "This instruction pops (loads) the registers in reglist from stack memory, adjusts the stack pointer by stackadj, moves zero into a0 and then returns to ra.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.popretz", + "line_range": [ + 1773, + 1773 + ] + }, + { + "text": "For further information see .", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.popretz", + "line_range": [ + 1775, + 1775 + ] + }, + { + "text": "Stack Adjustment Calculation:", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.popretz", + "line_range": [ + 1777, + 1777 + ] + }, + { + "text": "stackadjbase is the minimum number of bytes, in multiples of 16-byte address increments, required to cover the registers in the list.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.popretz", + "line_range": [ + 1779, + 1779 + ] + }, + { + "text": "spimm is the number of additional 16-byte address increments allocated for the stack frame.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.popretz", + "line_range": [ + 1781, + 1781 + ] + }, + { + "text": "The total stack adjustment represents the total size of the stack frame, which is stackadjbase added to spimm scaled by 16, as defined above.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.popretz", + "line_range": [ + 1783, + 1783 + ] + }, + { + "text": "No direct equivalent encoding exists", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.popretz", + "line_range": [ + 1791, + 1791 + ] + }, + { + "text": "The first section of pseudocode may be executed multiple times before the instruction successfully completes.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.popretz", + "line_range": [ + 1795, + 1795 + ] + }, + { + "text": "[source,sail] ---- //This is not SAIL, it's pseudocode.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.popretz", + "line_range": [ + 1797, + 1799 + ] + }, + { + "text": "The SAIL hasn't been written yet.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.popretz", + "line_range": [ + 1797, + 1799 + ] + }, + { + "text": "if (XLEN32) bytes=4; else bytes=8;", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.popretz", + "line_range": [ + 1801, + 1801 + ] + }, + { + "text": "addr=sp+stackadj-bytes; for(i in 27,26,25,24,23,22,21,20,19,18,9,8,1) { //if register i is in xreglist if (xreglist[i]) { switch(bytes) { 4: asm(\"lw x[i], 0(addr)\"); 8: asm(\"ld x[i], 0(addr)\"); } addr-=bytes; } } ----", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.popretz", + "line_range": [ + 1803, + 1814 + ] + }, + { + "text": "The final section of pseudocode executes atomically, and only executes if the section above completes without any exceptions or interrupts.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.popretz", + "line_range": [ + 1816, + 1816 + ] + }, + { + "text": "[source,sail] ---- //This is not SAIL, it's pseudocode.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.popretz", + "line_range": [ + 1818, + 1820 + ] + }, + { + "text": "The SAIL hasn't been written yet.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.popretz", + "line_range": [ + 1818, + 1820 + ] + }, + { + "text": "asm(\"li a0, 0\"); sp+=stackadj; asm(\"ret\"); ----", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.popretz", + "line_range": [ + 1822, + 1825 + ] + }, + { + "text": "<<< [insns-cmpopret,reftext=\"cm.popret\"]", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.popretz", + "line_range": [ + 1827, + 1828 + ] + }, + { + "text": "Destroy stack frame: load ra and 0 to 12 saved registers from the stack frame, deallocate the stack frame, return to ra.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.popret", + "line_range": [ + 1834, + 1834 + ] + }, + { + "text": "cm.popret \\{reglist}, stackadj", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.popret", + "line_range": [ + 1838, + 1838 + ] + }, + { + "text": "[wavedrom, , svg] .... {reg:[ { bits: 2, name: 0x2, attr: ['C2'] }, { bits: 2, name: 'spimm', attr: [] }, { bits: 4, name: 'rlist', attr: [] }, { bits: 5, name: 0x1e, attr: [] }, { bits: 3, name: 0x5, attr: ['FUNCT3'] }, ],config:{bits:16}} ....", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.popret", + "line_range": [ + 1842, + 1851 + ] + }, + { + "text": "[source,sail] ---- cm.popret \\{reglist}, stackadj cm.popret {xreglist}, stackadj ----", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.popret", + "line_range": [ + 1855, + 1859 + ] + }, + { + "text": "The variables used in the assembly syntax are defined below.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.popret", + "line_range": [ + 1861, + 1861 + ] + }, + { + "text": "switch (rlist){ case 4: \\{reglist=\"ra\"; xreglist=\"x1\";} case 5: \\{reglist=\"ra, s0\"; xreglist=\"x1, x8\";} case 6: \\{reglist=\"ra, s0-s1\"; xreglist=\"x1, x8-x9\";} default: reserved(); } stackadj = stackadjbase + spimm * 16; ----", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.popret", + "line_range": [ + 1867, + 1874 + ] + }, + { + "text": "[source,sail] ---- RV32I, RV64:", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.popret", + "line_range": [ + 1876, + 1878 + ] + }, + { + "text": "switch (rlist){ case 4: \\{reglist=\"ra\"; xreglist=\"x1\";} case 5: \\{reglist=\"ra, s0\"; xreglist=\"x1, x8\";} case 6: \\{reglist=\"ra, s0-s1\"; xreglist=\"x1, x8-x9\";} case 7: \\{reglist=\"ra, s0-s2\"; xreglist=\"x1, x8-x9, x18\";} case 8: \\{reglist=\"ra, s0-s3\"; xreglist=\"x1, x8-x9, x18-x19\";} case 9: \\{reglist=\"ra, s0-s4\"; xreglist=\"x1, x8-x9, x18-x20\";} case 10: \\{reglist=\"ra, s0-s5\"; xreglist=\"x1, x8-x9, x18-x21\";} case 11: \\{reglist=\"ra, s0-s6\"; xreglist=\"x1, x8-x9, x18-x22\";} case 12: \\{reglist=\"ra, s0-s7\"; xreglist=\"x1, x8-x9, x18-x23\";} case 13: \\{reglist=\"ra, s0-s8\"; xreglist=\"x1, x8-x9, x18-x24\";} case 14: \\{reglist=\"ra, s0-s9\"; xreglist=\"x1, x8-x9, x18-x25\";} //note - to include s10, s11 must also be included case 15: \\{reglist=\"ra, s0-s11\"; xreglist=\"x1, x8-x9, x18-x27\";} default: reserved(); } stackadj = stackadjbase + spimm * 16; ----", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.popret", + "line_range": [ + 1880, + 1897 + ] + }, + { + "text": "Valid values: stackadj = [16|32|48|64]; ----", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.popret", + "line_range": [ + 1903, + 1906 + ] + }, + { + "text": "switch (rlist) { case 4.. 7: stackadjbase = 16; case 8..11: stackadjbase = 32; case 12..14: stackadjbase = 48; case 15: stackadjbase = 64; }", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.popret", + "line_range": [ + 1912, + 1917 + ] + }, + { + "text": "Valid values: switch (rlist) { case 4.. 7: stackadj = [16|32|48| 64]; case 8..11: stackadj = [32|48|64| 80]; case 12..14: stackadj = [48|64|80| 96]; case 15: stackadj = [64|80|96|112]; } ----", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.popret", + "line_range": [ + 1919, + 1926 + ] + }, + { + "text": "switch (rlist) { case 4.. 5: stackadjbase = 16; case 6.. 7: stackadjbase = 32; case 8.. 9: stackadjbase = 48; case 10..11: stackadjbase = 64; case 12..13: stackadjbase = 80; case 14: stackadjbase = 96; case 15: stackadjbase = 112; }", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.popret", + "line_range": [ + 1932, + 1940 + ] + }, + { + "text": "Valid values: switch (rlist) { case 4.. 5: stackadj = [ 16| 32| 48| 64]; case 6.. 7: stackadj = [ 32| 48| 64| 80]; case 8.. 9: stackadj = [ 48| 64| 80| 96]; case 10..11: stackadj = [ 64| 80| 96|112]; case 12..13: stackadj = [ 80| 96|112|128]; case 14: stackadj = [ 96|112|128|144]; case 15: stackadj = [112|128|144|160]; } ----", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.popret", + "line_range": [ + 1942, + 1952 + ] + }, + { + "text": "This instruction pops (loads) the registers in reglist from stack memory, adjusts the stack pointer by stackadj and then returns to ra.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.popret", + "line_range": [ + 1958, + 1958 + ] + }, + { + "text": "For further information see .", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.popret", + "line_range": [ + 1960, + 1960 + ] + }, + { + "text": "Stack Adjustment Calculation:", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.popret", + "line_range": [ + 1962, + 1962 + ] + }, + { + "text": "stackadjbase is the minimum number of bytes, in multiples of 16-byte address increments, required to cover the registers in the list.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.popret", + "line_range": [ + 1964, + 1964 + ] + }, + { + "text": "spimm is the number of additional 16-byte address increments allocated for the stack frame.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.popret", + "line_range": [ + 1966, + 1966 + ] + }, + { + "text": "The total stack adjustment represents the total size of the stack frame, which is stackadjbase added to spimm scaled by 16, as defined above.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.popret", + "line_range": [ + 1968, + 1968 + ] + }, + { + "text": "No direct equivalent encoding exists", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.popret", + "line_range": [ + 1976, + 1976 + ] + }, + { + "text": "The first section of pseudocode may be executed multiple times before the instruction successfully completes.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.popret", + "line_range": [ + 1980, + 1980 + ] + }, + { + "text": "[source,sail] ---- //This is not SAIL, it's pseudocode.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.popret", + "line_range": [ + 1982, + 1984 + ] + }, + { + "text": "The SAIL hasn't been written yet.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.popret", + "line_range": [ + 1982, + 1984 + ] + }, + { + "text": "if (XLEN32) bytes=4; else bytes=8;", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.popret", + "line_range": [ + 1986, + 1986 + ] + }, + { + "text": "addr=sp+stackadj-bytes; for(i in 27,26,25,24,23,22,21,20,19,18,9,8,1) { //if register i is in xreglist if (xreglist[i]) { switch(bytes) { 4: asm(\"lw x[i], 0(addr)\"); 8: asm(\"ld x[i], 0(addr)\"); } addr-=bytes; } } ----", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.popret", + "line_range": [ + 1988, + 1999 + ] + }, + { + "text": "The final section of pseudocode executes atomically, and only executes if the section above completes without any exceptions or interrupts.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.popret", + "line_range": [ + 2001, + 2001 + ] + }, + { + "text": "[source,sail] ---- //This is not SAIL, it's pseudocode.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.popret", + "line_range": [ + 2003, + 2005 + ] + }, + { + "text": "The SAIL hasn't been written yet.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.popret", + "line_range": [ + 2003, + 2005 + ] + }, + { + "text": "sp+=stackadj; asm(\"ret\"); ----", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.popret", + "line_range": [ + 2007, + 2009 + ] + }, + { + "text": "[insns-cmmvsa01,reftext=\"Move a0-a1 into two different s0-s7 registers\"]", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.popret", + "line_range": [ + 2013, + 2013 + ] + }, + { + "text": "Move a0-a1 into two registers of s0-s7", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.mvsa01", + "line_range": [ + 2018, + 2018 + ] + }, + { + "text": "[wavedrom, , svg] .... {reg:[ { bits: 2, name: 0x2, attr: ['C2'] }, { bits: 3, name: 'r2s\\'', attr: [] }, { bits: 2, name: 0x1, attr: [] }, { bits: 3, name: 'r1s\\'', attr: [] }, { bits: 3, name: 0x3, attr: [] }, { bits: 3, name: 0x5, attr: ['FUNCT3'] }, ],config:{bits:16}} ....", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.mvsa01", + "line_range": [ + 2026, + 2036 + ] + }, + { + "text": "[source,asm] ---- cm.mvsa01 r1s', r2s' ----", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.mvsa01", + "line_range": [ + 2040, + 2043 + ] + }, + { + "text": "Description:: This instruction moves a0 into r1s' and a1 into r2s'. r1s' and r2s' must be different.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.mvsa01", + "line_range": [ + 2045, + 2047 + ] + }, + { + "text": "The execution is atomic, so it is not possible to observe state where only one of r1s' or r2s' has been updated.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.mvsa01", + "line_range": [ + 2045, + 2047 + ] + }, + { + "text": "The encoding uses sreg number specifiers instead of xreg number specifiers to save encoding space.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.mvsa01", + "line_range": [ + 2049, + 2050 + ] + }, + { + "text": "The mapping between them is specified in the pseudocode below.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.mvsa01", + "line_range": [ + 2049, + 2050 + ] + }, + { + "text": "No direct equivalent encoding exists.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.mvsa01", + "line_range": [ + 2058, + 2058 + ] + }, + { + "text": "[source,sail] ---- //This is not SAIL, it's pseudocode.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.mvsa01", + "line_range": [ + 2062, + 2072 + ] + }, + { + "text": "The SAIL hasn't been written yet. if (RV32E && (r1sc>1 || r2sc>1)) { reserved(); } xreg1 = {r1sc[2:1]>0,r1sc[2:1]0,r1sc[2:0]}; xreg2 = {r2sc[2:1]>0,r2sc[2:1]0,r2sc[2:0]}; X[xreg1] = X[10]; X[xreg2] = X[11]; ----", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.mvsa01", + "line_range": [ + 2062, + 2072 + ] + }, + { + "text": "[insns-cmmva01s,reftext=\"Move two s0-s7 registers into a0-a1\"]", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.mvsa01", + "line_range": [ + 2076, + 2076 + ] + }, + { + "text": "Move two s0-s7 registers into a0-a1", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.mva01s", + "line_range": [ + 2081, + 2081 + ] + }, + { + "text": "[wavedrom, , svg] .... {reg:[ { bits: 2, name: 0x2, attr: ['C2'] }, { bits: 3, name: 'r2s\\'', attr: [] }, { bits: 2, name: 0x3, attr: [] }, { bits: 3, name: 'r1s\\'', attr: [] }, { bits: 3, name: 0x3, attr: [] }, { bits: 3, name: 0x5, attr: ['FUNCT3'] }, ],config:{bits:16}} ....", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.mva01s", + "line_range": [ + 2089, + 2099 + ] + }, + { + "text": "[source,asm] ---- cm.mva01s r1s', r2s' ----", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.mva01s", + "line_range": [ + 2103, + 2106 + ] + }, + { + "text": "Description:: This instruction moves r1s' into a0 and r2s' into a1.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.mva01s", + "line_range": [ + 2108, + 2110 + ] + }, + { + "text": "The execution is atomic, so it is not possible to observe state where only one of a0 or a1 have been updated.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.mva01s", + "line_range": [ + 2108, + 2110 + ] + }, + { + "text": "The encoding uses sreg number specifiers instead of xreg number specifiers to save encoding space.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.mva01s", + "line_range": [ + 2112, + 2113 + ] + }, + { + "text": "The mapping between them is specified in the pseudocode below.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.mva01s", + "line_range": [ + 2112, + 2113 + ] + }, + { + "text": "No direct equivalent encoding exists.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.mva01s", + "line_range": [ + 2121, + 2121 + ] + }, + { + "text": "[source,sail] ---- //This is not SAIL, it's pseudocode.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.mva01s", + "line_range": [ + 2125, + 2135 + ] + }, + { + "text": "The SAIL hasn't been written yet. if (RV32E && (r1sc>1 || r2sc>1)) { reserved(); } xreg1 = {r1sc[2:1]>0,r1sc[2:1]0,r1sc[2:0]}; xreg2 = {r2sc[2:1]>0,r2sc[2:1]0,r2sc[2:0]}; X[10] = X[xreg1]; X[11] = X[xreg2]; ----", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.mva01s", + "line_range": [ + 2125, + 2135 + ] + }, + { + "text": "[insns-tablejump,reftext=\"Table Jump Overview\"]", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > PUSH/POP register instructions > cm.mva01s", + "line_range": [ + 2139, + 2139 + ] + }, + { + "text": "cm.jt () and cm.jalt () are referred to as table jump.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Table Jump Overview", + "line_range": [ + 2142, + 2142 + ] + }, + { + "text": "Table jump uses a 256-entry XLEN wide table in instruction memory to contain function addresses.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Table Jump Overview", + "line_range": [ + 2144, + 2145 + ] + }, + { + "text": "The table must be a minimum of 64-byte aligned.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Table Jump Overview", + "line_range": [ + 2144, + 2145 + ] + }, + { + "text": "Table entries follow the current data endianness.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Table Jump Overview", + "line_range": [ + 2147, + 2147 + ] + }, + { + "text": "This is different from normal instruction fetch which is always little-endian.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Table Jump Overview", + "line_range": [ + 2147, + 2147 + ] + }, + { + "text": "cm.jt and cm.jalt encodings index the table, giving access to functions within the full XLEN wide address space.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Table Jump Overview", + "line_range": [ + 2149, + 2149 + ] + }, + { + "text": "This is used as a form of dictionary compression to reduce the code size of jal / auipc+jalr / jr / auipc+jr instructions.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Table Jump Overview", + "line_range": [ + 2151, + 2151 + ] + }, + { + "text": "Table jump allows the linker to replace the following instruction sequences with a cm.jt or cm.jalt encoding, and an entry in the table:", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Table Jump Overview", + "line_range": [ + 2153, + 2153 + ] + }, + { + "text": "32-bit j calls * 32-bit jal ra calls * 64-bit auipc+jr calls to fixed locations * 64-bit auipc+jalr ra calls to fixed locations ** The auipc+jr/jalr sequence is used because the offset from the PC is out of the ±1{nbsp}MB range.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Table Jump Overview", + "line_range": [ + 2155, + 2159 + ] + }, + { + "text": "If a return address stack is implemented, then as cm.jalt is equivalent to jal ra, it pushes to the stack.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Table Jump Overview", + "line_range": [ + 2161, + 2161 + ] + }, + { + "text": "The base of the table is in the jvt CSR (see ), each table entry is XLEN bits.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Table Jump Overview > jvt", + "line_range": [ + 2165, + 2165 + ] + }, + { + "text": "If the same function is called with and without linking then it must have two entries in the table.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Table Jump Overview > jvt", + "line_range": [ + 2167, + 2168 + ] + }, + { + "text": "This is typically caused by the same function being called with and without tail calling.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Table Jump Overview > jvt", + "line_range": [ + 2167, + 2168 + ] + }, + { + "text": "[tablejump-fault-handling]", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Table Jump Overview > jvt", + "line_range": [ + 2170, + 2170 + ] + }, + { + "text": "For a table jump instruction, the table entry that the instruction selects is considered an extension of the instruction itself.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Table Jump Overview > Table Jump Fault handling", + "line_range": [ + 2173, + 2176 + ] + }, + { + "text": "Hence, the execution of a table jump instruction involves two instruction fetches, the first to read the instruction (cm.jt/cm.jalt) and the second to read from the jump vector table (JVT).", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Table Jump Overview > Table Jump Fault handling", + "line_range": [ + 2173, + 2176 + ] + }, + { + "text": "Both instruction fetches are implicit reads, and both require execute permission; read permission is irrelevant.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Table Jump Overview > Table Jump Fault handling", + "line_range": [ + 2173, + 2176 + ] + }, + { + "text": "It is recommended that the second fetch be ignored for hardware triggers and breakpoints.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Table Jump Overview > Table Jump Fault handling", + "line_range": [ + 2173, + 2176 + ] + }, + { + "text": "Memory writes to the jump vector table require an instruction barrier (fence.i) to guarantee that they are visible to the instruction fetch.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Table Jump Overview > Table Jump Fault handling", + "line_range": [ + 2178, + 2178 + ] + }, + { + "text": "Multiple contexts may have different jump vector tables. JVT may be switched between them without an instruction barrier if the tables have not been updated in memory since the last fence.i.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Table Jump Overview > Table Jump Fault handling", + "line_range": [ + 2180, + 2181 + ] + }, + { + "text": "If an exception occurs on either instruction fetch, xEPC is set to the PC of the table jump instruction, xCAUSE is set as expected for the type of fault and xTVAL (if not set to zero) contains the fetch address which caused the fault.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Table Jump Overview > Table Jump Fault handling", + "line_range": [ + 2183, + 2183 + ] + }, + { + "text": "<<< [csrs-jvt,reftext=\"jvt CSR, table jump base vector and control register\"]", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Table Jump Overview > Table Jump Fault handling", + "line_range": [ + 2185, + 2186 + ] + }, + { + "text": "Table jump base vector and control register", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Table Jump Overview > jvt CSR", + "line_range": [ + 2191, + 2191 + ] + }, + { + "text": "[wavedrom, , svg] .... {reg:[ { bits: 6, name: 'mode', attr: ['6'] }, { bits: 26, name: 'base[XLEN-1:6] (WARL)', attr: ['XLEN-6'] }, ],config:{bits:32}} ....", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Table Jump Overview > jvt CSR", + "line_range": [ + 2203, + 2209 + ] + }, + { + "text": "[wavedrom, , svg] .... {reg:[ { bits: 6, name: 'mode', attr: ['6'] }, { bits: 58, name: 'base[XLEN-1:6] (WARL)', attr: ['XLEN-6'] }, ],config:{bits:64}} ....", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Table Jump Overview > jvt CSR", + "line_range": [ + 2213, + 2219 + ] + }, + { + "text": "The jvt register is an XLEN-bit *WARL* read/write register that holds the jump table configuration, consisting of the jump table base address (BASE) and the jump table mode (MODE).", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Table Jump Overview > jvt CSR", + "line_range": [ + 2223, + 2223 + ] + }, + { + "text": "If is implemented then jvt must also be implemented, but can contain a read-only value.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Table Jump Overview > jvt CSR", + "line_range": [ + 2225, + 2226 + ] + }, + { + "text": "If jvt is writable, the set of values the register may hold can vary by implementation.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Table Jump Overview > jvt CSR", + "line_range": [ + 2225, + 2226 + ] + }, + { + "text": "The value in the BASE field must always be aligned on a 64-byte boundary.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Table Jump Overview > jvt CSR", + "line_range": [ + 2225, + 2226 + ] + }, + { + "text": "Note that the CSR contains only bits XLEN-1 through 6 of the address base.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Table Jump Overview > jvt CSR", + "line_range": [ + 2225, + 2226 + ] + }, + { + "text": "When computing jump-table accesses, the lower six bits of base are filled with zeroes to obtain an XLEN-bit jump-table base address jvt.base that is always aligned on a 64-byte boundary.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Table Jump Overview > jvt CSR", + "line_range": [ + 2225, + 2226 + ] + }, + { + "text": "jvt.base is a virtual address, whenever virtual memory is enabled.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Table Jump Overview > jvt CSR", + "line_range": [ + 2228, + 2228 + ] + }, + { + "text": "The memory pointed to by jvt.base is treated as instruction memory for the purpose of executing table jump instructions, implying execute access permission.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Table Jump Overview > jvt CSR", + "line_range": [ + 2230, + 2230 + ] + }, + { + "text": "[JVT-config-table] .jvt.mode definition [width=\"60%\",options=header] | | jvt.mode | Comment | 000000 | Jump table mode | others | *reserved for future standard use* |", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Table Jump Overview > jvt CSR", + "line_range": [ + 2232, + 2239 + ] + }, + { + "text": "jvt.mode is a *WARL* field, so can only be programmed to modes which are implemented.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Table Jump Overview > jvt CSR", + "line_range": [ + 2241, + 2242 + ] + }, + { + "text": "Therefore the discovery mechanism is to attempt to program different modes and read back the values to see which are available.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Table Jump Overview > jvt CSR", + "line_range": [ + 2241, + 2242 + ] + }, + { + "text": "Jump table mode must be implemented.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Table Jump Overview > jvt CSR", + "line_range": [ + 2241, + 2242 + ] + }, + { + "text": "jvt CSR adds architectural state to the system software context (such as an OS process), therefore must be saved/restored on context switches. <<< [insns-cmjt,reftext=\"Jump via table\"]", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Table Jump Overview > jvt CSR", + "line_range": [ + 2246, + 2248 + ] + }, + { + "text": "[wavedrom, , svg] .... {reg:[ { bits: 2, name: 0x2, attr: ['C2'] }, { bits: 8, name: 'index', attr: [] }, { bits: 3, name: 0x0, attr: [] }, { bits: 3, name: 0x5, attr: ['FUNCT3'] }, ],config:{bits:16}} ....", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Table Jump Overview > cm.jt", + "line_range": [ + 2261, + 2269 + ] + }, + { + "text": "[source,asm] ---- cm.jt index ----", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Table Jump Overview > cm.jt", + "line_range": [ + 2273, + 2276 + ] + }, + { + "text": "cm.jt reads an entry from the jump vector table in memory and jumps to the address that was read.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Table Jump Overview > cm.jt", + "line_range": [ + 2280, + 2280 + ] + }, + { + "text": "For further information see .", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Table Jump Overview > cm.jt", + "line_range": [ + 2282, + 2282 + ] + }, + { + "text": "No direct equivalent encoding exists.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Table Jump Overview > cm.jt", + "line_range": [ + 2290, + 2290 + ] + }, + { + "text": "[insns-cmjt-SAIL,reftext=\"cm.jt SAIL code\"] Operation::", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Table Jump Overview > cm.jt", + "line_range": [ + 2294, + 2295 + ] + }, + { + "text": "[source,sail] ---- //This is not SAIL, it's pseudocode.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Table Jump Overview > cm.jt", + "line_range": [ + 2297, + 2299 + ] + }, + { + "text": "The SAIL hasn't been written yet.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Table Jump Overview > cm.jt", + "line_range": [ + 2297, + 2299 + ] + }, + { + "text": "tableaddress is temporary internal state, it doesn't represent a real register InstMemory is byte indexed", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Table Jump Overview > cm.jt", + "line_range": [ + 2301, + 2302 + ] + }, + { + "text": "switch(XLEN) { 32: tableaddress[XLEN-1:0] = jvt.base + (index<<2); 64: tableaddress[XLEN-1:0] = jvt.base + (index<<3); }", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Table Jump Overview > cm.jt", + "line_range": [ + 2304, + 2307 + ] + }, + { + "text": "<<< [insns-cmjalt,reftext=\"Jump and link via table\"]", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Table Jump Overview > cm.jt", + "line_range": [ + 2314, + 2315 + ] + }, + { + "text": "jump via table with optional link", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Table Jump Overview > cm.jalt", + "line_range": [ + 2320, + 2320 + ] + }, + { + "text": "[wavedrom, , svg] .... {reg:[ { bits: 2, name: 0x2, attr: ['C2'] }, { bits: 8, name: 'index', attr: [] }, { bits: 3, name: 0x0, attr: [] }, { bits: 3, name: 0x5, attr: ['FUNCT3'] }, ],config:{bits:16}} ....", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Table Jump Overview > cm.jalt", + "line_range": [ + 2328, + 2336 + ] + }, + { + "text": "[source,asm] ---- cm.jalt index ----", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Table Jump Overview > cm.jalt", + "line_range": [ + 2340, + 2343 + ] + }, + { + "text": "cm.jalt reads an entry from the jump vector table in memory and jumps to the address that was read, linking to ra.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Table Jump Overview > cm.jalt", + "line_range": [ + 2347, + 2347 + ] + }, + { + "text": "For further information see .", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Table Jump Overview > cm.jalt", + "line_range": [ + 2349, + 2349 + ] + }, + { + "text": "No direct equivalent encoding exists.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Table Jump Overview > cm.jalt", + "line_range": [ + 2357, + 2357 + ] + }, + { + "text": "[insns-cmjalt-SAIL,reftext=\"cm.jalt SAIL code\"] Operation::", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Table Jump Overview > cm.jalt", + "line_range": [ + 2361, + 2362 + ] + }, + { + "text": "[source,sail] ---- //This is not SAIL, it's pseudocode.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Table Jump Overview > cm.jalt", + "line_range": [ + 2364, + 2366 + ] + }, + { + "text": "The SAIL hasn't been written yet.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Table Jump Overview > cm.jalt", + "line_range": [ + 2364, + 2366 + ] + }, + { + "text": "tableaddress is temporary internal state, it doesn't represent a real register InstMemory is byte indexed", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Table Jump Overview > cm.jalt", + "line_range": [ + 2368, + 2369 + ] + }, + { + "text": "switch(XLEN) { 32: tableaddress[XLEN-1:0] = jvt.base + (index<<2); 64: tableaddress[XLEN-1:0] = jvt.base + (index<<3); }", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Table Jump Overview > cm.jalt", + "line_range": [ + 2371, + 2374 + ] + }, + { + "text": "ra = pc+2; pc = InstMemory[tableaddress][XLEN-1:0]&~0x1; // Clear bit 0.", + "section": "Preamble > \"Zc*\" Extension for Code Size Reduction, Version 1.0.0 > Table Jump Overview > cm.jalt", + "line_range": [ + 2378, + 2379 + ] + } + ] +} \ No newline at end of file diff --git a/tools/llm-extraction/data/output/udb_chunks.json b/tools/llm-extraction/data/output/udb_chunks.json new file mode 100644 index 0000000000..cd012ebe99 --- /dev/null +++ b/tools/llm-extraction/data/output/udb_chunks.json @@ -0,0 +1,22860 @@ +[ + { + "chunk_id": "chunk_f687a651", + "source": "udb_param", + "source_file": "std/isa/param/ARCH_ID_VALUE.yaml", + "section": "ARCH_ID_VALUE", + "text": "Parameter ARCH_ID_VALUE The value of `marchid`\nThe combination of mvendorid and marchid should uniquely identify the type of hart microarchitecture that is implemented.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_3b3663a6", + "source": "udb_param", + "source_file": "std/isa/param/ASID_WIDTH.yaml", + "section": "ASID_WIDTH", + "text": "Parameter ASID_WIDTH Number of implemented ASID bits. Maximum is 16 for XLEN==64, and 9 for XLEN==32 Schema: type=integer, range=[0, 16]. Defined by: S.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "confidence": "high", + "defined_by": "S" + }, + { + "chunk_id": "chunk_c2235c0e", + "source": "udb_param", + "source_file": "std/isa/param/CACHE_BLOCK_SIZE.yaml", + "section": "CACHE_BLOCK_SIZE", + "text": "Parameter CACHE_BLOCK_SIZE The observable size of a cache block, in bytes Schema: type=integer, range=[1, 18446744073709551615].", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d0582733", + "source": "udb_param", + "source_file": "std/isa/param/CONFIG_PTR_ADDRESS.yaml", + "section": "CONFIG_PTR_ADDRESS", + "text": "Parameter CONFIG_PTR_ADDRESS The value returned from `mconfigptr` Defined by: Sm.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "confidence": "high", + "defined_by": "Sm" + }, + { + "chunk_id": "chunk_d7c5646e", + "source": "udb_param", + "source_file": "std/isa/param/COUNTINHIBIT_EN.yaml", + "section": "COUNTINHIBIT_EN", + "text": "Parameter COUNTINHIBIT_EN Indicates which hardware performance monitor counters can be disabled from `mcountinhibit`.\n\nAn unimplemented counter cannot be specified, i.e., if HPM_COUNTER_EN[3] is false,\nit would be illegal to set COUNTINHIBIT_EN[3] to true.\n\nCOUNTINHIBIT_EN[1] can never be true, since it corresponds to `mcountinhibit.TM`,\nwhich is always read-only-0. Schema: type=array. Defined by: Sm.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "confidence": "high", + "defined_by": "Sm" + }, + { + "chunk_id": "chunk_8ce66656", + "source": "udb_param", + "source_file": "std/isa/param/DBG_HCONTEXT_WIDTH.yaml", + "section": "DBG_HCONTEXT_WIDTH", + "text": "Parameter DBG_HCONTEXT_WIDTH Specifies the size of HCONTEXT Schema: type=integer, range=[0, 14]. Defined by: Sdtrig.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "confidence": "high", + "defined_by": "Sdtrig" + }, + { + "chunk_id": "chunk_618f2bc2", + "source": "udb_param", + "source_file": "std/isa/param/DBG_SCONTEXT_WIDTH.yaml", + "section": "DBG_SCONTEXT_WIDTH", + "text": "Parameter DBG_SCONTEXT_WIDTH Specifies the size of SCONTEXT Schema: type=integer, range=[0, 32]. Defined by: Sdtrig.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "confidence": "high", + "defined_by": "Sdtrig" + }, + { + "chunk_id": "chunk_0c623cbd", + "source": "udb_param", + "source_file": "std/isa/param/DCSR_MPRVEN_TYPE.yaml", + "section": "DCSR_MPRVEN_TYPE", + "text": "Parameter DCSR_MPRVEN_TYPE Implementation of dcsr.MPRVEN is optional.\nIt may be tied to either 0 or 1.\n\nBehavior of the dcsr.MPRVEN bit:\n * 'read-only-0': tied to 0\n * 'read-only-1': tied to 1\n * 'rw': read-write Schema: type=string, enum: read-only-0, read-only-1, rw. Defined by: Sdtrig.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "confidence": "high", + "defined_by": "Sdtrig" + }, + { + "chunk_id": "chunk_8d944160", + "source": "udb_param", + "source_file": "std/isa/param/DCSR_STEPIE_TYPE.yaml", + "section": "DCSR_STEPIE_TYPE", + "text": "Parameter DCSR_STEPIE_TYPE Implementation of dcsr.STEPIE is optional.\nIt may be tied to either 0 or 1.\n\nBehavior of the dcsr.STEPIE bit:\n * 'read-only-0': tied to 0\n * 'read-only-1': tied to 1\n * 'rw': read-write Schema: type=string, enum: read-only-0, read-only-1, rw. Defined by: Sdtrig.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "confidence": "high", + "defined_by": "Sdtrig" + }, + { + "chunk_id": "chunk_ab4a6597", + "source": "udb_param", + "source_file": "std/isa/param/DCSR_STOPCOUNT_TYPE.yaml", + "section": "DCSR_STOPCOUNT_TYPE", + "text": "Parameter DCSR_STOPCOUNT_TYPE Implementation of dcsr.STOPCOUNT is optional.\nIt may be tied to either 0 or 1.\n\nBehavior of the dcsr.STOPCOUNT bit:\n * 'read-only-0': tied to 0\n * 'read-only-1': tied to 1\n * 'rw': read-write Schema: type=string, enum: read-only-0, read-only-1, rw. Defined by: Sdtrig.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "confidence": "high", + "defined_by": "Sdtrig" + }, + { + "chunk_id": "chunk_9e4f061d", + "source": "udb_param", + "source_file": "std/isa/param/DCSR_STOPTIME_TYPE.yaml", + "section": "DCSR_STOPTIME_TYPE", + "text": "Parameter DCSR_STOPTIME_TYPE Implementation of dcsr.STOPTIME is optional.\nIt may be tied to either 0 or 1.\n\nBehavior of the dcsr.STOPTIME bit:\n * 'read-only-0': tied to 0\n * 'read-only-1': tied to 1\n * 'rw': read-write Schema: type=string, enum: read-only-0, read-only-1, rw. Defined by: Sdtrig.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "confidence": "high", + "defined_by": "Sdtrig" + }, + { + "chunk_id": "chunk_4718f75a", + "source": "udb_param", + "source_file": "std/isa/param/ELEN.yaml", + "section": "ELEN", + "text": "Parameter ELEN The maximum size in bits of a vector element that any operation can produce or consume. Schema: type=integer. Defined by: Zvl32b.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "confidence": "high", + "defined_by": "Zvl32b" + }, + { + "chunk_id": "chunk_28b37f81", + "source": "udb_param", + "source_file": "std/isa/param/FOLLOW_VTYPE_RESET_RECOMMENDATION.yaml", + "section": "FOLLOW_VTYPE_RESET_RECOMMENDATION", + "text": "Parameter FOLLOW_VTYPE_RESET_RECOMMENDATION It is recommended that at reset, vtype.vill is set, the remaining bits in vtype are zero, and vl is set to zero.\nIf this parameter is set to true, this recommendation is followed. If it is false, at reset the respective fields\nwill be UNDEFINED_LEGAL. Schema: type=boolean. Defined by: Zvl32b.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "Zvl32b" + }, + { + "chunk_id": "chunk_50ec874e", + "source": "udb_param", + "source_file": "std/isa/param/FORCE_UPGRADE_CBO_INVAL_TO_FLUSH.yaml", + "section": "FORCE_UPGRADE_CBO_INVAL_TO_FLUSH", + "text": "Parameter FORCE_UPGRADE_CBO_INVAL_TO_FLUSH When true, an implementation prohibits setting `menvcfg.CBIE` == `11` such that all `cbo.inval`\ninstructions either trap (when `menvcfg.CBIE` == '00') or flush (when `menvcfg.CBIE` == '01').\n\nWhen false, an implementation allows a true INVAL operation for `cbo.inval`, and thus supports\nthe setting `menvcfg.CBIE` == `11`. Schema: type=boolean. Defined by: Zicbom.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "Zicbom" + }, + { + "chunk_id": "chunk_360c80f3", + "source": "udb_param", + "source_file": "std/isa/param/GSTAGE_MODE_BARE.yaml", + "section": "GSTAGE_MODE_BARE", + "text": "Parameter GSTAGE_MODE_BARE Whether or not writing mode=Bare is supported in the `hgatp` register. Schema: type=boolean. Defined by: H.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "H" + }, + { + "chunk_id": "chunk_92e4a588", + "source": "udb_param", + "source_file": "std/isa/param/HCONTEXT_AVAILABLE.yaml", + "section": "HCONTEXT_AVAILABLE", + "text": "Parameter HCONTEXT_AVAILABLE Specifies if HCONTEXT is available Schema: type=boolean. Defined by: Sdtrig.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "Sdtrig" + }, + { + "chunk_id": "chunk_4b125db6", + "source": "udb_param", + "source_file": "std/isa/param/HCOUNTENABLE_EN.yaml", + "section": "HCOUNTENABLE_EN", + "text": "Parameter HCOUNTENABLE_EN Indicates which counters can delegated via `hcounteren`\n\nAn unimplemented counter cannot be specified, i.e., if\nHPM_COUNTER_EN[3] is false, it would be illegal to set\nHCOUNTENABLE_EN[3] to true.\n\nHCOUNTENABLE_EN[0:2] must all be false if `Zicntr` is not implemented.\nHCOUNTENABLE_EN[3:31] must all be false if `Zihpm` is not implemented. Schema: type=array. Defined by: H.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "confidence": "high", + "defined_by": "H" + }, + { + "chunk_id": "chunk_126afe3a", + "source": "udb_param", + "source_file": "std/isa/param/HPM_COUNTER_EN.yaml", + "section": "HPM_COUNTER_EN", + "text": "Parameter HPM_COUNTER_EN List of HPM counters that are enabled.\nThere is one entry for each hpmcounter.\n\nThe first three entries *must* be false (as they correspond to CY, IR, TM in, _e.g._ `mhmpcountinhibit`)\nIndex 3 in HPM_COUNTER_EN corresponds to mhpmcounter3.\nIndex 31 in HPM_COUNTER_EN corresponds to mhpmcounter31. Schema: type=array. Defined by: Sm.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "confidence": "high", + "defined_by": "Sm" + }, + { + "chunk_id": "chunk_cf08450d", + "source": "udb_param", + "source_file": "std/isa/param/HPM_EVENTS.yaml", + "section": "HPM_EVENTS", + "text": "Parameter HPM_EVENTS List of defined event numbers that can be written into mhpmeventN Schema: type=array.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_253df1ee", + "source": "udb_param", + "source_file": "std/isa/param/HSTATEEN_AIA_TYPE.yaml", + "section": "HSTATEEN_AIA_TYPE", + "text": "Parameter HSTATEEN_AIA_TYPE Behavior of the hstateen0.AIA bit:\n\n * 'rw': read-write\n * 'read-only-0': read-only, fixed to 0\n * 'read-only-1': read-only, fixed to 1 Schema: type=string, enum: rw, read-only-0, read-only-1.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_e98d5e2e", + "source": "udb_param", + "source_file": "std/isa/param/HSTATEEN_CONTEXT_TYPE.yaml", + "section": "HSTATEEN_CONTEXT_TYPE", + "text": "Parameter HSTATEEN_CONTEXT_TYPE Behavior of the hstateen0.CONTEXT bit:\n\n * 'rw': read-write\n * 'read-only-0': read-only, fixed to 0\n * 'read-only-1': read-only, fixed to 1 Schema: type=string, enum: rw, read-only-0, read-only-1.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_320a39e0", + "source": "udb_param", + "source_file": "std/isa/param/HSTATEEN_CSRIND_TYPE.yaml", + "section": "HSTATEEN_CSRIND_TYPE", + "text": "Parameter HSTATEEN_CSRIND_TYPE Behavior of the hstateen0.CSRIND bit:\n\n * 'rw': read-write\n * 'read-only-0': read-only, fixed to 0\n * 'read-only-1': read-only, fixed to 1 Schema: type=string, enum: rw, read-only-0, read-only-1.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_666a650b", + "source": "udb_param", + "source_file": "std/isa/param/HSTATEEN_ENVCFG_TYPE.yaml", + "section": "HSTATEEN_ENVCFG_TYPE", + "text": "Parameter HSTATEEN_ENVCFG_TYPE Behavior of the hstateen0.ENVCFG bit:\n\n * 'rw': read-write\n * 'read-only-0': read-only, fixed to 0\n * 'read-only-1': read-only, fixed to 1 Schema: type=string, enum: rw, read-only-0, read-only-1.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_75d89c33", + "source": "udb_param", + "source_file": "std/isa/param/HSTATEEN_IMSIC_TYPE.yaml", + "section": "HSTATEEN_IMSIC_TYPE", + "text": "Parameter HSTATEEN_IMSIC_TYPE Behavior of the hstateen0.IMSIC bit:\n\n * 'rw': read-write\n * 'read-only-0': read-only, fixed to 0\n * 'read-only-1': read-only, fixed to 1 Schema: type=string, enum: rw, read-only-0, read-only-1.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_f9c8d6e7", + "source": "udb_param", + "source_file": "std/isa/param/HSTATEEN_JVT_TYPE.yaml", + "section": "HSTATEEN_JVT_TYPE", + "text": "Parameter HSTATEEN_JVT_TYPE Behavior of the hstateen0.JVT bit:\n\n * 'rw': read-write\n * 'read-only-0': read-only, fixed to 0\n * 'read-only-1': read-only, fixed to 1 Schema: type=string, enum: rw, read-only-0, read-only-1.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_b1099a96", + "source": "udb_param", + "source_file": "std/isa/param/HW_MSTATUS_FS_DIRTY_UPDATE.yaml", + "section": "HW_MSTATUS_FS_DIRTY_UPDATE", + "text": "Parameter HW_MSTATUS_FS_DIRTY_UPDATE Indicates whether or not hardware will write to `mstatus.FS`\n\nValues are:\n[separator=\"!\"]\n!===\nh! never ! Hardware never writes `mstatus.FS`\nh! precise ! Hardware writes `mstatus.FS` to the Dirty (3) state precisely when F registers are modified\nh! imprecise ! Hardware writes `mstatus.FS` imprecisely. This will result in a call to unpredictable() on any attempt to read `mstatus` or write FP state.\n!=== Schema: type=string, enum: never, precise, imprecise.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ef1a8e6a", + "source": "udb_param", + "source_file": "std/isa/param/HW_MSTATUS_VS_DIRTY_UPDATE.yaml", + "section": "HW_MSTATUS_VS_DIRTY_UPDATE", + "text": "Parameter HW_MSTATUS_VS_DIRTY_UPDATE Indicates whether or not hardware will write to `mstatus.VS`\n\nValues are:\n[separator=\"!\"]\n!===\nh! never ! Hardware never writes `mstatus.VS`\nh! precise ! Hardware writes `mstatus.VS` to the Dirty (3) state precisely when V registers are modified\nh! imprecise ! Hardware writes `mstatus.VS` imprecisely. This will result in a call to unpredictable() on any attempt to read `mstatus` or write vector state.\n!=== Schema: type=string, enum: never, precise, imprecise.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_f0bb7fdf", + "source": "udb_param", + "source_file": "std/isa/param/IGNORE_INVALID_VSATP_MODE_WRITES_WHEN_V_EQ_ZERO.yaml", + "section": "IGNORE_INVALID_VSATP_MODE_WRITES_WHEN_V_EQ_ZERO", + "text": "Parameter IGNORE_INVALID_VSATP_MODE_WRITES_WHEN_V_EQ_ZERO Whether writes from M-mode, U-mode, or S-mode to vsatp with an illegal mode setting are\nignored (as they are with satp), or if they are treated as WARL, leading to undpredictable\nbehavior. Schema: type=boolean. Defined by: H.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "H" + }, + { + "chunk_id": "chunk_c19fa591", + "source": "udb_param", + "source_file": "std/isa/param/IMPRECISE_VECTOR_TRAP_SETTABLE.yaml", + "section": "IMPRECISE_VECTOR_TRAP_SETTABLE", + "text": "Parameter IMPRECISE_VECTOR_TRAP_SETTABLE Some profiles may provide a privileged configuration bit that selects\nbetween precise and imprecise vector trap behavior, allowing flexibility\nin how traps and partial updates are reported. Schema: type=boolean. Defined by: Zvl32b.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "Zvl32b" + }, + { + "chunk_id": "chunk_64b9d973", + "source": "udb_param", + "source_file": "std/isa/param/IMP_ID_VALUE.yaml", + "section": "IMP_ID_VALUE", + "text": "Parameter IMP_ID_VALUE A unique encoding of the version of the processor implementation.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "unknown", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_5ee47fb5", + "source": "udb_param", + "source_file": "std/isa/param/JVT_BASE_MASK.yaml", + "section": "JVT_BASE_MASK", + "text": "Parameter JVT_BASE_MASK Mask representing the implemented bits of jvt.BASE.\nIncludes the implicitly-zero bits of jvt.BASE, so JVT_BASE_MASK[5:0] must always be 0. Schema: type=integer, range=[64, 576460752303423487].", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_846dc7a3", + "source": "udb_param", + "source_file": "std/isa/param/JVT_BASE_TYPE.yaml", + "section": "JVT_BASE_TYPE", + "text": "Parameter JVT_BASE_TYPE Type of the jvt.BASE CSR field. One of:\n\n* mask: jvt.BASE contains one or more implemented bits, which are indicated by JVT_BASE_MASK.\n* custom: Custom behavior. Will cause hart to enter 'unpredictable' state on a write to jvt.BASE. Schema: type=string, enum: mask, custom. Defined by: Zcmt.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "confidence": "high", + "defined_by": "Zcmt" + }, + { + "chunk_id": "chunk_ca136c92", + "source": "udb_param", + "source_file": "std/isa/param/JVT_READ_ONLY.yaml", + "section": "JVT_READ_ONLY", + "text": "Parameter JVT_READ_ONLY If Zcmt is implemented, JVT is implemented, but can contain a read-only value Schema: type=boolean. Defined by: Zcmt.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "Zcmt" + }, + { + "chunk_id": "chunk_0e4fcac7", + "source": "udb_param", + "source_file": "std/isa/param/LEGAL_VSTART.yaml", + "section": "LEGAL_VSTART", + "text": "Parameter LEGAL_VSTART Implementations may raise illegal-instruction exceptions for vector\ninstructions that specify a `vstart` value the implementation can never\nproduce under the same `vtype` configuration (e.g., due to restrictions\non supported strides or alignments). Schema: type=string, enum: 1_stride, 2_stride, 4_stride, custom. Defined by: Zvl32b.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "confidence": "high", + "defined_by": "Zvl32b" + }, + { + "chunk_id": "chunk_4ca8ba6e", + "source": "udb_param", + "source_file": "std/isa/param/LRSC_FAIL_ON_NON_EXACT_LRSC.yaml", + "section": "LRSC_FAIL_ON_NON_EXACT_LRSC", + "text": "Parameter LRSC_FAIL_ON_NON_EXACT_LRSC Whether or not a Store Conditional fails if its physical address and size do not\nexactly match the physical address and size of the last Load Reserved in program order\n(independent of whether or not the SC is in the current reservation set) Schema: type=boolean. Defined by: Zalrsc.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "Zalrsc" + }, + { + "chunk_id": "chunk_43152a7d", + "source": "udb_param", + "source_file": "std/isa/param/LRSC_FAIL_ON_VA_SYNONYM.yaml", + "section": "LRSC_FAIL_ON_VA_SYNONYM", + "text": "Parameter LRSC_FAIL_ON_VA_SYNONYM Whether or not an `sc.l`/`sc.d` will fail if its VA does not match the VA of the prior\n`lr.l`/`lr.d`, even if the physical address of the SC and LR are the same Schema: type=boolean. Defined by: Zalrsc.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "Zalrsc" + }, + { + "chunk_id": "chunk_a8cf4bbe", + "source": "udb_param", + "source_file": "std/isa/param/LRSC_MISALIGNED_BEHAVIOR.yaml", + "section": "LRSC_MISALIGNED_BEHAVIOR", + "text": "Parameter LRSC_MISALIGNED_BEHAVIOR What to do when an LR/SC address is misaligned and MISALIGNED_AMO == false.\n\n * 'always raise misaligned exception': self-explainitory\n * 'always raise access fault': self-explainitory\n * 'custom': Custom behavior; misaligned LR/SC may sometimes raise a misaligned exception and sometimes raise a access fault. Will lead to an 'unpredictable' call on any misaligned LR/SC access Schema: type=string, enum: always raise misaligned exception, always raise access fault, custom. Defined by: Zalrsc.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "confidence": "high", + "defined_by": "Zalrsc" + }, + { + "chunk_id": "chunk_beae6078", + "source": "udb_param", + "source_file": "std/isa/param/LRSC_RESERVATION_STRATEGY.yaml", + "section": "LRSC_RESERVATION_STRATEGY", + "text": "Parameter LRSC_RESERVATION_STRATEGY Strategy used to handle reservation sets.\n\n * \"reserve naturally-aligned 64-byte region\": Always reserve the 64-byte block containing the LR/SC address\n * \"reserve naturally-aligned 128-byte region\": Always reserve the 128-byte block containing the LR/SC address\n * \"reserve exactly enough to cover the access\": Always reserve exactly the LR/SC access, and no more\n * \"custom\": Custom behavior, leading to an 'unpredictable' call on any LR/SC Schema: type=string, enum: reserve naturally-aligned 64-byte region, reserve naturally-aligned 128-byte region, reserve exactly enough to cover the access, custom. Defined by: Zalrsc.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "confidence": "high", + "defined_by": "Zalrsc" + }, + { + "chunk_id": "chunk_9f546811", + "source": "udb_param", + "source_file": "std/isa/param/MARCHID_IMPLEMENTED.yaml", + "section": "MARCHID_IMPLEMENTED", + "text": "Parameter MARCHID_IMPLEMENTED * false: `marchid` is not implemented, and must be read-only-0\n* true: `marchid` is implemented, and the value is determined by `ARCH_ID_VALUE` Schema: type=boolean. Defined by: Sm.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "Sm" + }, + { + "chunk_id": "chunk_c81e11f1", + "source": "udb_param", + "source_file": "std/isa/param/MCID_WIDTH.yaml", + "section": "MCID_WIDTH", + "text": "Parameter MCID_WIDTH Number of bits used for the Monitoring Counter ID field (MCID).\nDefault is 12. Schema: type=integer, range=[1, 12]. Defined by: Ssqosid.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "confidence": "high", + "defined_by": "Ssqosid" + }, + { + "chunk_id": "chunk_dd1ff8e5", + "source": "udb_param", + "source_file": "std/isa/param/MCONTEXT_AVAILABLE.yaml", + "section": "MCONTEXT_AVAILABLE", + "text": "Parameter MCONTEXT_AVAILABLE Specifies if MCONTEXT is available Schema: type=boolean. Defined by: Sdtrig.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "Sdtrig" + }, + { + "chunk_id": "chunk_779dd3a9", + "source": "udb_param", + "source_file": "std/isa/param/MCOUNTENABLE_EN.yaml", + "section": "MCOUNTENABLE_EN", + "text": "Parameter MCOUNTENABLE_EN Indicates which counters can be delegated via `mcounteren`.\n\nAn unimplemented counter cannot be specified, i.e., if\nHPM_COUNTER_EN[3] is false, it would be illegal to set\nMCOUNTENABLE_EN[3] to true.\n\nMCOUNTENABLE_EN[0:2] must all be false if `Zicntr` is not implemented.\nMCOUNTENABLE_EN[3:31] must all be false if `Zihpm` is not implemented. Schema: type=array. Defined by: Sm.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "confidence": "high", + "defined_by": "Sm" + }, + { + "chunk_id": "chunk_da393550", + "source": "udb_param", + "source_file": "std/isa/param/MCTRCTL_CORSWAPINH_IMPLEMENTED.yaml", + "section": "MCTRCTL_CORSWAPINH_IMPLEMENTED", + "text": "Parameter MCTRCTL_CORSWAPINH_IMPLEMENTED Whether or not mctrctl.CORSWAPINH is implemented.\n\nWhen not implemented mctrctl.CORSWAPINH will be read-only-zero. Schema: type=boolean. Defined by: Smctr.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "Smctr" + }, + { + "chunk_id": "chunk_d46269d0", + "source": "udb_param", + "source_file": "std/isa/param/MCTRCTL_CUSTOM_IMPLEMENTED.yaml", + "section": "MCTRCTL_CUSTOM_IMPLEMENTED", + "text": "Parameter MCTRCTL_CUSTOM_IMPLEMENTED Whether or not mctrctl.CUSTOM is implemented.\n\nWhen not implemented mctrctl.CUSTOM will be read-only-zero. Schema: type=boolean. Defined by: Smctr.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "Smctr" + }, + { + "chunk_id": "chunk_9048f5d5", + "source": "udb_param", + "source_file": "std/isa/param/MCTRCTL_DIRCALLINH_IMPLEMENTED.yaml", + "section": "MCTRCTL_DIRCALLINH_IMPLEMENTED", + "text": "Parameter MCTRCTL_DIRCALLINH_IMPLEMENTED Whether or not mctrctl.DIRCALLINH is implemented.\n\nWhen not implemented mctrctl.DIRCALLINH will be read-only-zero. Schema: type=boolean. Defined by: Smctr.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "Smctr" + }, + { + "chunk_id": "chunk_39ade3fa", + "source": "udb_param", + "source_file": "std/isa/param/MCTRCTL_DIRJMPINH_IMPLEMENTED.yaml", + "section": "MCTRCTL_DIRJMPINH_IMPLEMENTED", + "text": "Parameter MCTRCTL_DIRJMPINH_IMPLEMENTED Whether or not mctrctl.DIRJMPINH is implemented.\n\nWhen not implemented mctrctl.DIRJMPINH will be read-only-zero. Schema: type=boolean. Defined by: Smctr.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "Smctr" + }, + { + "chunk_id": "chunk_fe3fc768", + "source": "udb_param", + "source_file": "std/isa/param/MCTRCTL_DIRLJMPINH_IMPLEMENTED.yaml", + "section": "MCTRCTL_DIRLJMPINH_IMPLEMENTED", + "text": "Parameter MCTRCTL_DIRLJMPINH_IMPLEMENTED Whether or not mctrctl.DIRLJMPINH is implemented.\n\nWhen not implemented mctrctl.DIRLJMPINH will be read-only-zero. Schema: type=boolean. Defined by: Smctr.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "Smctr" + }, + { + "chunk_id": "chunk_40de2850", + "source": "udb_param", + "source_file": "std/isa/param/MCTRCTL_EXCINH_IMPLEMENTED.yaml", + "section": "MCTRCTL_EXCINH_IMPLEMENTED", + "text": "Parameter MCTRCTL_EXCINH_IMPLEMENTED Whether or not mctrctl.EXCINH is implemented.\n\nWhen not implemented mctrctl.EXCINH will be read-only-zero. Schema: type=boolean. Defined by: Smctr.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "Smctr" + }, + { + "chunk_id": "chunk_5408289e", + "source": "udb_param", + "source_file": "std/isa/param/MCTRCTL_INDCALLINH_IMPLEMENTED.yaml", + "section": "MCTRCTL_INDCALLINH_IMPLEMENTED", + "text": "Parameter MCTRCTL_INDCALLINH_IMPLEMENTED Whether or not mctrctl.INDCALLINH is implemented.\n\nWhen not implemented mctrctl.INDCALLINH will be read-only-zero. Schema: type=boolean. Defined by: Smctr.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "Smctr" + }, + { + "chunk_id": "chunk_6c0869ec", + "source": "udb_param", + "source_file": "std/isa/param/MCTRCTL_INDJMPINH_IMPLEMENTED.yaml", + "section": "MCTRCTL_INDJMPINH_IMPLEMENTED", + "text": "Parameter MCTRCTL_INDJMPINH_IMPLEMENTED Whether or not mctrctl.INDJMPINH is implemented.\n\nWhen not implemented mctrctl.INDJMPINH will be read-only-zero. Schema: type=boolean. Defined by: Smctr.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "Smctr" + }, + { + "chunk_id": "chunk_cf23f234", + "source": "udb_param", + "source_file": "std/isa/param/MCTRCTL_INDLJMPINH_IMPLEMENTED.yaml", + "section": "MCTRCTL_INDLJMPINH_IMPLEMENTED", + "text": "Parameter MCTRCTL_INDLJMPINH_IMPLEMENTED Whether or not mctrctl.INDLJMPINH is implemented.\n\nWhen not implemented mctrctl.INDLJMPINH will be read-only-zero. Schema: type=boolean. Defined by: Smctr.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "Smctr" + }, + { + "chunk_id": "chunk_a536fdff", + "source": "udb_param", + "source_file": "std/isa/param/MCTRCTL_INTRINH_IMPLEMENTED.yaml", + "section": "MCTRCTL_INTRINH_IMPLEMENTED", + "text": "Parameter MCTRCTL_INTRINH_IMPLEMENTED Whether or not mctrctl.INTRINH is implemented.\n\nWhen not implemented mctrctl.INTRINH will be read-only-zero. Schema: type=boolean. Defined by: Smctr.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "Smctr" + }, + { + "chunk_id": "chunk_85c5ac8a", + "source": "udb_param", + "source_file": "std/isa/param/MCTRCTL_MTE_IMPLEMENTED.yaml", + "section": "MCTRCTL_MTE_IMPLEMENTED", + "text": "Parameter MCTRCTL_MTE_IMPLEMENTED Whether or not mctrctl.MTE is implemented.\n\nWhen not implemented mctrctl.MTE will be read-only-zero. Schema: type=boolean. Defined by: Smctr.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "Smctr" + }, + { + "chunk_id": "chunk_e37bd51a", + "source": "udb_param", + "source_file": "std/isa/param/MCTRCTL_NTBREN_IMPLEMENTED.yaml", + "section": "MCTRCTL_NTBREN_IMPLEMENTED", + "text": "Parameter MCTRCTL_NTBREN_IMPLEMENTED Whether or not mctrctl.NTBREN is implemented.\n\nWhen not implemented mctrctl.NTBREN will be read-only-zero. Schema: type=boolean. Defined by: Smctr.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "Smctr" + }, + { + "chunk_id": "chunk_55aa3b8b", + "source": "udb_param", + "source_file": "std/isa/param/MCTRCTL_RASEMU_IMPLEMENTED.yaml", + "section": "MCTRCTL_RASEMU_IMPLEMENTED", + "text": "Parameter MCTRCTL_RASEMU_IMPLEMENTED Whether or not mctrctl.RASEMU is implemented.\n\nWhen not implemented mctrctl.RASEMU will be read-only-zero. Schema: type=boolean. Defined by: Smctr.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "Smctr" + }, + { + "chunk_id": "chunk_8a080745", + "source": "udb_param", + "source_file": "std/isa/param/MCTRCTL_RETINH_IMPLEMENTED.yaml", + "section": "MCTRCTL_RETINH_IMPLEMENTED", + "text": "Parameter MCTRCTL_RETINH_IMPLEMENTED Whether or not mctrctl.RETINH is implemented.\n\nWhen not implemented mctrctl.RETINH will be read-only-zero. Schema: type=boolean. Defined by: Smctr.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "Smctr" + }, + { + "chunk_id": "chunk_b401451a", + "source": "udb_param", + "source_file": "std/isa/param/MCTRCTL_STE_IMPLEMENTED.yaml", + "section": "MCTRCTL_STE_IMPLEMENTED", + "text": "Parameter MCTRCTL_STE_IMPLEMENTED Whether or not mctrctl.STE is implemented.\n\nWhen not implemented mctrctl.STE will be read-only-zero. Schema: type=boolean. Defined by: Smctr.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "Smctr" + }, + { + "chunk_id": "chunk_82683ae2", + "source": "udb_param", + "source_file": "std/isa/param/MCTRCTL_TKBRINH_IMPLEMENTED.yaml", + "section": "MCTRCTL_TKBRINH_IMPLEMENTED", + "text": "Parameter MCTRCTL_TKBRINH_IMPLEMENTED Whether or not mctrctl.TKBRINH is implemented.\n\nWhen not implemented mctrctl.TKBRINH will be read-only-zero. Schema: type=boolean. Defined by: Smctr.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "Smctr" + }, + { + "chunk_id": "chunk_9dee24fc", + "source": "udb_param", + "source_file": "std/isa/param/MCTRCTL_TRETINH_IMPLEMENTED.yaml", + "section": "MCTRCTL_TRETINH_IMPLEMENTED", + "text": "Parameter MCTRCTL_TRETINH_IMPLEMENTED Whether or not mctrctl.TRETINH is implemented.\n\nWhen not implemented mctrctl.TRETINH will be read-only-zero. Schema: type=boolean. Defined by: Smctr.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "Smctr" + }, + { + "chunk_id": "chunk_243d3390", + "source": "udb_param", + "source_file": "std/isa/param/MIMPID_IMPLEMENTED.yaml", + "section": "MIMPID_IMPLEMENTED", + "text": "Parameter MIMPID_IMPLEMENTED * false: `mimpid` is not implemented, and must be read-only-0\n* true: `mimpid` is implemented, and the value is determined by `IMP_ID_VALUE` Schema: type=boolean. Defined by: Sm.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "Sm" + }, + { + "chunk_id": "chunk_a54d919a", + "source": "udb_param", + "source_file": "std/isa/param/MISALIGNED_AMO.yaml", + "section": "MISALIGNED_AMO", + "text": "Parameter MISALIGNED_AMO Whether or not the implementation supports misaligned atomics in main memory Schema: type=boolean. Defined by: Zaamo.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "Zaamo" + }, + { + "chunk_id": "chunk_7302a60d", + "source": "udb_param", + "source_file": "std/isa/param/MISALIGNED_LDST.yaml", + "section": "MISALIGNED_LDST", + "text": "Parameter MISALIGNED_LDST Does the implementation perform non-atomic misaligned loads and stores to main memory\n(does *not* affect misaligned support to device memory)?\nIf not, the implementation always throws a misaligned exception. Schema: type=boolean. Defined by: Sm.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "Sm" + }, + { + "chunk_id": "chunk_b34f46e7", + "source": "udb_param", + "source_file": "std/isa/param/MISALIGNED_LDST_EXCEPTION_PRIORITY.yaml", + "section": "MISALIGNED_LDST_EXCEPTION_PRIORITY", + "text": "Parameter MISALIGNED_LDST_EXCEPTION_PRIORITY The relative priority of a load/store/AMO exception vs. load/store/AMO page-fault\nor access-fault exceptions.\n\nMay be one of:\n\n[separator=\"!\"]\n!===\n! low ! Misaligned load/store/AMO exceptions are always lower priority than load/store/AMO page-fault and access-fault exceptions.\n! high ! Misaligned load/store/AMO exceptions are always higher priority than load/store/AMO page-fault and access-fault exceptions.\n!===\n\nMISALIGNED_LDST_EXCEPTION_PRIORITY cannot be \"high\" when MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE\nis non-zero, since the atomicity of an access cannot be determined in that case until after\naddress translation. Schema: type=string, enum: low, high. Defined by: Sm.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "confidence": "high", + "defined_by": "Sm" + }, + { + "chunk_id": "chunk_77d4fd7a", + "source": "udb_param", + "source_file": "std/isa/param/MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE.yaml", + "section": "MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE", + "text": "Parameter MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE When MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE is 0, the hart\ncannot atomically perform a misaligned load/store/AMO. When a power of two, the hart can\natomically load/store/AMO a misaligned access that is fully contained in a\nMISALIGNED_MAX_ATOMICITY_GRANULE_SIZE-aligned region.\n\n[NOTE]\nEven if the hart is capable of performing a misaligned load/store/AMO atomically,\na misaligned exception may still occur if the access does not have the appropriate\nMisaligned Atomicity Granule PMA set. Schema: type=integer, enum: 0, 2, 4, 8, 16, 32, 64, 128.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_6c48f153", + "source": "udb_param", + "source_file": "std/isa/param/MISALIGNED_SPLIT_STRATEGY.yaml", + "section": "MISALIGNED_SPLIT_STRATEGY", + "text": "Parameter MISALIGNED_SPLIT_STRATEGY Options:\n\n * sequential_bytes: The load/store appears to be broken into byte-sized accesses that processed sequentially from smallest address to largest address\n * custom: Something else. Will result in a call to unpredictable() in the execution Schema: type=string, enum: sequential_bytes, custom.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_4848101a", + "source": "udb_param", + "source_file": "std/isa/param/MISA_CSR_IMPLEMENTED.yaml", + "section": "MISA_CSR_IMPLEMENTED", + "text": "Parameter MISA_CSR_IMPLEMENTED Options:\n\n true::\n The `misa` CSR returns a non-zero value.\n\n false::\n The `misa` CSR is read-only-0. Schema: type=boolean. Defined by: Sm.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "Sm" + }, + { + "chunk_id": "chunk_4c2347ae", + "source": "udb_param", + "source_file": "std/isa/param/MSTATEEN_AIA_TYPE.yaml", + "section": "MSTATEEN_AIA_TYPE", + "text": "Parameter MSTATEEN_AIA_TYPE Behavior of the mstateen0.AIA bit:\n\n * 'rw': read-write\n * 'read-only-0': read-only, fixed to 0\n * 'read-only-1': read-only, fixed to 1 Schema: type=string, enum: rw, read-only-0, read-only-1.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_cac2da3d", + "source": "udb_param", + "source_file": "std/isa/param/MSTATEEN_CONTEXT_TYPE.yaml", + "section": "MSTATEEN_CONTEXT_TYPE", + "text": "Parameter MSTATEEN_CONTEXT_TYPE Behavior of the mstateen0.CONTEXT bit:\n\n * 'rw': read-write\n * 'read-only-0': read-only, fixed to 0\n * 'read-only-1': read-only, fixed to 1 Schema: type=string, enum: rw, read-only-0, read-only-1.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_57bcc61a", + "source": "udb_param", + "source_file": "std/isa/param/MSTATEEN_CSRIND_TYPE.yaml", + "section": "MSTATEEN_CSRIND_TYPE", + "text": "Parameter MSTATEEN_CSRIND_TYPE Behavior of the mstateen0.CSRIND bit:\n\n * 'rw': read-write\n * 'read-only-0': read-only, fixed to 0\n * 'read-only-1': read-only, fixed to 1 Schema: type=string, enum: rw, read-only-0, read-only-1.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_0d1fdb67", + "source": "udb_param", + "source_file": "std/isa/param/MSTATEEN_ENVCFG_TYPE.yaml", + "section": "MSTATEEN_ENVCFG_TYPE", + "text": "Parameter MSTATEEN_ENVCFG_TYPE Behavior of the mstateen0.ENVCFG bit:\n\n * 'rw': read-write\n * 'read-only-0': read-only, fixed to 0\n * 'read-only-1': read-only, fixed to 1 Schema: type=string, enum: rw, read-only-0, read-only-1.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_f4e937cb", + "source": "udb_param", + "source_file": "std/isa/param/MSTATEEN_IMSIC_TYPE.yaml", + "section": "MSTATEEN_IMSIC_TYPE", + "text": "Parameter MSTATEEN_IMSIC_TYPE Behavior of the mstateen0.IMSIC bit:\n\n * 'rw': read-write\n * 'read-only-0': read-only, fixed to 0\n * 'read-only-1': read-only, fixed to 1 Schema: type=string, enum: rw, read-only-0, read-only-1.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_b5b8720c", + "source": "udb_param", + "source_file": "std/isa/param/MSTATEEN_JVT_TYPE.yaml", + "section": "MSTATEEN_JVT_TYPE", + "text": "Parameter MSTATEEN_JVT_TYPE Behavior of the mstateen0.JVT bit:\n\n * 'rw': read-write\n * 'read-only-0': read-only, fixed to 0\n * 'read-only-1': read-only, fixed to 1 Schema: type=string, enum: rw, read-only-0, read-only-1.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_8d6f9ccb", + "source": "udb_param", + "source_file": "std/isa/param/MSTATUS_FS_LEGAL_VALUES.yaml", + "section": "MSTATUS_FS_LEGAL_VALUES", + "text": "Parameter MSTATUS_FS_LEGAL_VALUES The set of values that mstatus.FS supports. Schema: type=array.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_4ca49058", + "source": "udb_param", + "source_file": "std/isa/param/MSTATUS_TVM_IMPLEMENTED.yaml", + "section": "MSTATUS_TVM_IMPLEMENTED", + "text": "Parameter MSTATUS_TVM_IMPLEMENTED Whether or not mstatus.TVM is implemented.\n\nWhen not implemented mstatus.TVM will be read-only-zero. Schema: type=boolean. Defined by: S.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "S" + }, + { + "chunk_id": "chunk_fae51d77", + "source": "udb_param", + "source_file": "std/isa/param/MSTATUS_VS_LEGAL_VALUES.yaml", + "section": "MSTATUS_VS_LEGAL_VALUES", + "text": "Parameter MSTATUS_VS_LEGAL_VALUES The set of values that mstatus.VS will accept from a software write. Schema: type=array.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_371bbba7", + "source": "udb_param", + "source_file": "std/isa/param/MTVAL_WIDTH.yaml", + "section": "MTVAL_WIDTH", + "text": "Parameter MTVAL_WIDTH The number of implemented bits in the `mtval` CSR.\nThis is the CSR that may be written when a trap is taken into M-mode with exception-specific information to\nassist software in handling the trap (e.g., address associated with exception).\n\nMust be greater than or equal to _max_(`PHYS_ADDR_WIDTH`, `VA_SIZE`) Schema: type=integer, range=[0, 64]. Defined by: Sm.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "confidence": "high", + "defined_by": "Sm" + }, + { + "chunk_id": "chunk_01f59663", + "source": "udb_param", + "source_file": "std/isa/param/MTVEC_ACCESS.yaml", + "section": "MTVEC_ACCESS", + "text": "Parameter MTVEC_ACCESS Options:\n\n ro::\n `mtvec` is read-only.\n\n rw::\n `mtvec` is read-write, but may not accept all values. Schema: type=string, enum: ro, rw. Defined by: Sm.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "confidence": "high", + "defined_by": "Sm" + }, + { + "chunk_id": "chunk_def78c41", + "source": "udb_param", + "source_file": "std/isa/param/MTVEC_BASE_ALIGNMENT_DIRECT.yaml", + "section": "MTVEC_BASE_ALIGNMENT_DIRECT", + "text": "Parameter MTVEC_BASE_ALIGNMENT_DIRECT Minimum alignment of the base pointer. Because `mtvec` excludes the two least-significant bits of\nthe base, the minimum alignment cannot be less than 4. Schema: enum: 4, 8, 16, 32, 64, 128, 256, 512.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_2850fa16", + "source": "udb_param", + "source_file": "std/isa/param/MTVEC_BASE_ALIGNMENT_VECTORED.yaml", + "section": "MTVEC_BASE_ALIGNMENT_VECTORED", + "text": "Parameter MTVEC_BASE_ALIGNMENT_VECTORED Because `mtvec` excludes the two least-significant bits of\nthe base, the minimum alignment cannot be less than 4. Schema: enum: 4, 8, 16, 32, 64, 128, 256, 512.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_0ac73c0d", + "source": "udb_param", + "source_file": "std/isa/param/MTVEC_ILLEGAL_WRITE_BEHAVIOR.yaml", + "section": "MTVEC_ILLEGAL_WRITE_BEHAVIOR", + "text": "Parameter MTVEC_ILLEGAL_WRITE_BEHAVIOR Options:\n\n retain::\n When either `mtvec.MODE` or `mtvec.BASE` is illegal, `mtvec` will retain its current value\n\n custom::\n When either `mtvec.MODE` or `mtvec.BASE` is illegal, `mtvec` will obtain an unpredictable value\n\nOther values may be added over time once other common behaviors are identified. Schema: enum: retain, custom. Defined by: Sm.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "confidence": "high", + "defined_by": "Sm" + }, + { + "chunk_id": "chunk_0234815f", + "source": "udb_param", + "source_file": "std/isa/param/MTVEC_MODES.yaml", + "section": "MTVEC_MODES", + "text": "Parameter MTVEC_MODES Options:\n\n 0::\n Direct; All traps set `pc` to `mtvec.BASE`\n 1::\n Vectored; Asynchronous interrupts set `pc` to `mtvec.BASE` + 4 x cause.\n\nIf only one mode is given, `mtvec.MODE` is assumed to be read-only with that value.\nOtherwise, `mtvec.MODE` is read-write. Schema: type=array. Defined by: Sm.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "confidence": "high", + "defined_by": "Sm" + }, + { + "chunk_id": "chunk_4447a0ed", + "source": "udb_param", + "source_file": "std/isa/param/MUTABLE_MISA_A.yaml", + "section": "MUTABLE_MISA_A", + "text": "Parameter MUTABLE_MISA_A When the `A` extensions is supported, indicates whether or not\nthe extension can be disabled in the `misa.A` bit. Schema: type=boolean.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_2772c7a4", + "source": "udb_param", + "source_file": "std/isa/param/MUTABLE_MISA_B.yaml", + "section": "MUTABLE_MISA_B", + "text": "Parameter MUTABLE_MISA_B Indicates whether or not the `B` extension can be disabled with the `misa.B` bit. Schema: type=boolean.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_99027e65", + "source": "udb_param", + "source_file": "std/isa/param/MUTABLE_MISA_C.yaml", + "section": "MUTABLE_MISA_C", + "text": "Parameter MUTABLE_MISA_C Indicates whether or not the `C` extension can be disabled with the `misa.C` bit. Schema: type=boolean.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_43f30531", + "source": "udb_param", + "source_file": "std/isa/param/MUTABLE_MISA_D.yaml", + "section": "MUTABLE_MISA_D", + "text": "Parameter MUTABLE_MISA_D Indicates whether or not the `D` extension can be disabled with the `misa.D` bit. Schema: type=boolean.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_f23c620d", + "source": "udb_param", + "source_file": "std/isa/param/MUTABLE_MISA_F.yaml", + "section": "MUTABLE_MISA_F", + "text": "Parameter MUTABLE_MISA_F Indicates whether or not the `F` extension can be disabled with the `misa.F` bit. Schema: type=boolean.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_0b970325", + "source": "udb_param", + "source_file": "std/isa/param/MUTABLE_MISA_H.yaml", + "section": "MUTABLE_MISA_H", + "text": "Parameter MUTABLE_MISA_H Indicates whether or not the `H` extension can be disabled with the `misa.H` bit. Schema: type=boolean.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_c3012f9b", + "source": "udb_param", + "source_file": "std/isa/param/MUTABLE_MISA_M.yaml", + "section": "MUTABLE_MISA_M", + "text": "Parameter MUTABLE_MISA_M Indicates whether or not the `M` extension can be disabled with the `misa.M` bit. Schema: type=boolean.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_69237b7a", + "source": "udb_param", + "source_file": "std/isa/param/MUTABLE_MISA_Q.yaml", + "section": "MUTABLE_MISA_Q", + "text": "Parameter MUTABLE_MISA_Q Indicates whether or not the `Q` extension can be disabled with the `misa.Q` bit. Schema: type=boolean.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_9a9e1022", + "source": "udb_param", + "source_file": "std/isa/param/MUTABLE_MISA_S.yaml", + "section": "MUTABLE_MISA_S", + "text": "Parameter MUTABLE_MISA_S Indicates whether or not the `S` extension can be disabled with the `misa.S` bit. Schema: type=boolean.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_7318155d", + "source": "udb_param", + "source_file": "std/isa/param/MUTABLE_MISA_U.yaml", + "section": "MUTABLE_MISA_U", + "text": "Parameter MUTABLE_MISA_U Indicates whether or not the `U` extension can be disabled with the `misa.U` bit. Schema: type=boolean.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_1160299a", + "source": "udb_param", + "source_file": "std/isa/param/MUTABLE_MISA_V.yaml", + "section": "MUTABLE_MISA_V", + "text": "Parameter MUTABLE_MISA_V Indicates whether or not the `V` extension can be disabled with the `misa.V` bit. Schema: type=boolean.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_0d586a9c", + "source": "udb_param", + "source_file": "std/isa/param/MXLEN.yaml", + "section": "MXLEN", + "text": "Parameter MXLEN XLEN in machine mode, specified in bits Schema: type=integer, enum: 32, 64. Defined by: Sm.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "confidence": "high", + "defined_by": "Sm" + }, + { + "chunk_id": "chunk_bee752cb", + "source": "udb_param", + "source_file": "std/isa/param/M_MODE_ENDIANNESS.yaml", + "section": "M_MODE_ENDIANNESS", + "text": "Parameter M_MODE_ENDIANNESS Options:\n\n[separator=\"!\"]\n!===\nh! little ! M-mode data is always little endian\nh! big ! M-mode data is always big endian\nh! dynamic ! M-mode data can be either little or big endian,\n depending on the CSR field `mstatus.MBE`\n!=== Schema: type=string, enum: little, big, dynamic. Defined by: Sm.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "confidence": "high", + "defined_by": "Sm" + }, + { + "chunk_id": "chunk_d81d16f5", + "source": "udb_param", + "source_file": "std/isa/param/NUM_EXTERNAL_GUEST_INTERRUPTS.yaml", + "section": "NUM_EXTERNAL_GUEST_INTERRUPTS", + "text": "Parameter NUM_EXTERNAL_GUEST_INTERRUPTS Number of supported virtualized guest interrupts\n\nCorresponds to the `GEILEN` parameter in the RVI specs Schema: type=integer, range=[1, 63]. Defined by: H.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "confidence": "high", + "defined_by": "H" + }, + { + "chunk_id": "chunk_bc8e69b3", + "source": "udb_param", + "source_file": "std/isa/param/NUM_PMP_ENTRIES.yaml", + "section": "NUM_PMP_ENTRIES", + "text": "Parameter NUM_PMP_ENTRIES Number of implemented PMP entries. Can be any value between 0-64, inclusive.\n\nThe architecture mandates that the number of implemented PMP registers\nmust appear to be 0, 16, or 64.\n\nTherefore, pmp registers will behave as follows according to NUN_PMP_ENTRIES:\n\n[separator=\"!\"]\n!===\n! NUM_PMP_ENTRIES ! pmpaddr<0-15> / pmpcfg<0-3> ! pmpaddr<16-63> / pmpcfg<4-15>\n! 0 ! N ! N\n! 1-16 ! Y ! N\n! 17-64 ! Y ! Y\n!===\n\n** N = Not implemented; access will cause `IllegalInstruction`\n if TRAP_ON_UNIMPLEMENTED_CSR is true\n** Y = Implemented; access will not cause an exception (from M-mode), but register\n may be read-only-zero if NUM_PMP_ENTRIES is less than the corresponding register\n\n[NOTE]\n`pmpcfgN` for an odd N never exists when XLEN == 64\n\nWhen NUM_PMP_ENTRIES is not exactly 0, 16, or 64, some extant pmp registers,\nand associated pmpNcfg, will be read-only zero (but will never cause an exception). Schema: type=integer, range=[0, 64]. Defined by: Sm.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "confidence": "high", + "defined_by": "Sm" + }, + { + "chunk_id": "chunk_96ae033c", + "source": "udb_param", + "source_file": "std/isa/param/PHYS_ADDR_WIDTH.yaml", + "section": "PHYS_ADDR_WIDTH", + "text": "Parameter PHYS_ADDR_WIDTH Implementation-defined size of the physical address space. Schema: type=integer, range=[1, 64]. Defined by: Sm.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "confidence": "high", + "defined_by": "Sm" + }, + { + "chunk_id": "chunk_73a5235f", + "source": "udb_param", + "source_file": "std/isa/param/PMA_GRANULARITY.yaml", + "section": "PMA_GRANULARITY", + "text": "Parameter PMA_GRANULARITY Generally, for systems with an MMU, should not be smaller than 12,\nas that would preclude caching PMA results in the TLB along with\nvirtual memory translations Schema: type=integer, range=[2, 66]. Defined by: Sm.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "confidence": "high", + "defined_by": "Sm" + }, + { + "chunk_id": "chunk_0567c576", + "source": "udb_param", + "source_file": "std/isa/param/PMLEN.yaml", + "section": "PMLEN", + "text": "Parameter PMLEN The number of high-order bits of an address that are masked by the\npointer masking facility. Schema: type=integer.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_eb36b3fc", + "source": "udb_param", + "source_file": "std/isa/param/PMP_GRANULARITY.yaml", + "section": "PMP_GRANULARITY", + "text": "Parameter PMP_GRANULARITY log2 of the smallest supported PMP region.\n\nGenerally, for systems with an MMU, should not be smaller than 12,\nas that would preclude caching PMP results in the TLB along with\nvirtual memory translations\n\nNote that PMP_GRANULARITY is equal to G+2 (not G) as described in\nthe privileged architecture. Schema: type=integer, range=[2, 66]. Defined by: Sm.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "confidence": "high", + "defined_by": "Sm" + }, + { + "chunk_id": "chunk_d41ccb87", + "source": "udb_param", + "source_file": "std/isa/param/PRECISE_SYNCHRONOUS_EXCEPTIONS.yaml", + "section": "PRECISE_SYNCHRONOUS_EXCEPTIONS", + "text": "Parameter PRECISE_SYNCHRONOUS_EXCEPTIONS If false, any exception not otherwise mandated to precise (e.g., PMP violation)\nwill cause execution to enter an unpredictable state. Schema: type=boolean. Defined by: Sm.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "Sm" + }, + { + "chunk_id": "chunk_23a2547e", + "source": "udb_param", + "source_file": "std/isa/param/RCID_WIDTH.yaml", + "section": "RCID_WIDTH", + "text": "Parameter RCID_WIDTH Number of bits used for the Resource Control ID field (RCID).\nDefault is 12. Schema: type=integer, range=[1, 12]. Defined by: Ssqosid.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "confidence": "high", + "defined_by": "Ssqosid" + }, + { + "chunk_id": "chunk_1bef0d5a", + "source": "udb_param", + "source_file": "std/isa/param/REPORT_CAUSE_IN_MTVAL_ON_LANDING_PAD_SOFTWARE_CHECK.yaml", + "section": "REPORT_CAUSE_IN_MTVAL_ON_LANDING_PAD_SOFTWARE_CHECK", + "text": "Parameter REPORT_CAUSE_IN_MTVAL_ON_LANDING_PAD_SOFTWARE_CHECK When true, `mtval` is written with the shadow stack cause (code=18) when a SoftwareCheck exception is raised into M-mode due to a landing pad error.\n\nWhen false, `mtval` is written with 0. Schema: type=boolean. Defined by: Zicfilp.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "Zicfilp" + }, + { + "chunk_id": "chunk_12e369ea", + "source": "udb_param", + "source_file": "std/isa/param/REPORT_CAUSE_IN_MTVAL_ON_SHADOW_STACK_SOFTWARE_CHECK.yaml", + "section": "REPORT_CAUSE_IN_MTVAL_ON_SHADOW_STACK_SOFTWARE_CHECK", + "text": "Parameter REPORT_CAUSE_IN_MTVAL_ON_SHADOW_STACK_SOFTWARE_CHECK When true, `mtval` is written with the shadow stack cause (code=3) when a SoftwareCheck exception is raised into M-mode due to a shadow stack pop check instruction.\n\nWhen false, `mtval` is written with 0. Schema: type=boolean. Defined by: Zicfiss.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "Zicfiss" + }, + { + "chunk_id": "chunk_ed4f703a", + "source": "udb_param", + "source_file": "std/isa/param/REPORT_CAUSE_IN_STVAL_ON_LANDING_PAD_SOFTWARE_CHECK.yaml", + "section": "REPORT_CAUSE_IN_STVAL_ON_LANDING_PAD_SOFTWARE_CHECK", + "text": "Parameter REPORT_CAUSE_IN_STVAL_ON_LANDING_PAD_SOFTWARE_CHECK When true, `stval` is written with the shadow stack cause (code=18) when a SoftwareCheck exception is raised into S-mode due to a landing pad error.\n\nWhen false, `stval` is written with 0. Schema: type=boolean. Defined by: Zicfilp.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "Zicfilp" + }, + { + "chunk_id": "chunk_1601641e", + "source": "udb_param", + "source_file": "std/isa/param/REPORT_CAUSE_IN_STVAL_ON_SHADOW_STACK_SOFTWARE_CHECK.yaml", + "section": "REPORT_CAUSE_IN_STVAL_ON_SHADOW_STACK_SOFTWARE_CHECK", + "text": "Parameter REPORT_CAUSE_IN_STVAL_ON_SHADOW_STACK_SOFTWARE_CHECK When true, `stval` is written with the shadow stack cause (code=3) when a SoftwareCheck exception is raised into S-mode due to a shadow stack pop check instruction.\n\nWhen false, `stval` is written with 0. Schema: type=boolean. Defined by: Zicfiss.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "Zicfiss" + }, + { + "chunk_id": "chunk_b310645d", + "source": "udb_param", + "source_file": "std/isa/param/REPORT_CAUSE_IN_VSTVAL_ON_LANDING_PAD_SOFTWARE_CHECK.yaml", + "section": "REPORT_CAUSE_IN_VSTVAL_ON_LANDING_PAD_SOFTWARE_CHECK", + "text": "Parameter REPORT_CAUSE_IN_VSTVAL_ON_LANDING_PAD_SOFTWARE_CHECK When true, `vstval` is written with the shadow stack cause (code=18) when a SoftwareCheck exception is raised into VS-mode due to a landing pad error.\n\nWhen false, `vstval` is written with 0. Schema: type=boolean. Defined by: Zicfilp.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "Zicfilp" + }, + { + "chunk_id": "chunk_4c88311a", + "source": "udb_param", + "source_file": "std/isa/param/REPORT_CAUSE_IN_VSTVAL_ON_SHADOW_STACK_SOFTWARE_CHECK.yaml", + "section": "REPORT_CAUSE_IN_VSTVAL_ON_SHADOW_STACK_SOFTWARE_CHECK", + "text": "Parameter REPORT_CAUSE_IN_VSTVAL_ON_SHADOW_STACK_SOFTWARE_CHECK When true, `vstval` is written with the shadow stack cause (code=3) when a SoftwareCheck exception is raised into VS-mode due to a shadow stack pop check instruction.\n\nWhen false, `vstval` is written with 0. Schema: type=boolean. Defined by: Zicfiss.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "Zicfiss" + }, + { + "chunk_id": "chunk_96f16acb", + "source": "udb_param", + "source_file": "std/isa/param/REPORT_ENCODING_IN_MTVAL_ON_ILLEGAL_INSTRUCTION.yaml", + "section": "REPORT_ENCODING_IN_MTVAL_ON_ILLEGAL_INSTRUCTION", + "text": "Parameter REPORT_ENCODING_IN_MTVAL_ON_ILLEGAL_INSTRUCTION Options:\n\n * true: `mtval` is written with the encoding of an instruction causing an IllegalInstruction exception\n * false: `mtval` is written with 0 when an instruction causes an IllegalInstruction exception. Schema: type=boolean. Defined by: Sm.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "Sm" + }, + { + "chunk_id": "chunk_44df6c85", + "source": "udb_param", + "source_file": "std/isa/param/REPORT_ENCODING_IN_STVAL_ON_ILLEGAL_INSTRUCTION.yaml", + "section": "REPORT_ENCODING_IN_STVAL_ON_ILLEGAL_INSTRUCTION", + "text": "Parameter REPORT_ENCODING_IN_STVAL_ON_ILLEGAL_INSTRUCTION When true, `stval` is written with the encoding of an instruction that causes an\n`IllegalInstruction` exception.\n\nWhen false `stval` is written with 0 when an `IllegalInstruction` exception occurs. Schema: type=boolean. Defined by: S.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "S" + }, + { + "chunk_id": "chunk_109d5de8", + "source": "udb_param", + "source_file": "std/isa/param/REPORT_ENCODING_IN_VSTVAL_ON_ILLEGAL_INSTRUCTION.yaml", + "section": "REPORT_ENCODING_IN_VSTVAL_ON_ILLEGAL_INSTRUCTION", + "text": "Parameter REPORT_ENCODING_IN_VSTVAL_ON_ILLEGAL_INSTRUCTION When true, `vstval` is written with the encoding of an instruction that causes an\n`IllegalInstruction` exception.\n\nWhen false `vstval` is written with 0 when an `IllegalInstruction` exception occurs. Schema: type=boolean. Defined by: H.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "H" + }, + { + "chunk_id": "chunk_5fe44d32", + "source": "udb_param", + "source_file": "std/isa/param/REPORT_ENCODING_IN_VSTVAL_ON_VIRTUAL_INSTRUCTION.yaml", + "section": "REPORT_ENCODING_IN_VSTVAL_ON_VIRTUAL_INSTRUCTION", + "text": "Parameter REPORT_ENCODING_IN_VSTVAL_ON_VIRTUAL_INSTRUCTION When true, `vstval` is written with the encoding of an instruction that causes an\n`VirualInstruction` exception.\n\nWhen false `vstval` is written with 0 when an `VirtualInstruction` exception occurs. Schema: type=boolean. Defined by: H.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "H" + }, + { + "chunk_id": "chunk_2da8b762", + "source": "udb_param", + "source_file": "std/isa/param/REPORT_GPA_IN_HTVAL_ON_GUEST_PAGE_FAULT.yaml", + "section": "REPORT_GPA_IN_HTVAL_ON_GUEST_PAGE_FAULT", + "text": "Parameter REPORT_GPA_IN_HTVAL_ON_GUEST_PAGE_FAULT When true, `htval` is written with the Guest Physical Address, shifted right by 2, that\ncaused a `GuestPageFault` exception.\n\nWhen false, `htval` is written with 0 when a `GuestPageFault` exception occurs. Schema: type=boolean. Defined by: H.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "H" + }, + { + "chunk_id": "chunk_a479a208", + "source": "udb_param", + "source_file": "std/isa/param/REPORT_GPA_IN_TVAL_ON_INSTRUCTION_GUEST_PAGE_FAULT.yaml", + "section": "REPORT_GPA_IN_TVAL_ON_INSTRUCTION_GUEST_PAGE_FAULT", + "text": "Parameter REPORT_GPA_IN_TVAL_ON_INSTRUCTION_GUEST_PAGE_FAULT Whether or not GPA >> 2 is written into htval/mtval2 when an instruction guest page fault occurs.\n\nIf false, 0 will be written into htval/mtval2 on an instruction guest page fault. Schema: type=boolean. Defined by: H.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "H" + }, + { + "chunk_id": "chunk_9f305bf2", + "source": "udb_param", + "source_file": "std/isa/param/REPORT_GPA_IN_TVAL_ON_INTERMEDIATE_GUEST_PAGE_FAULT.yaml", + "section": "REPORT_GPA_IN_TVAL_ON_INTERMEDIATE_GUEST_PAGE_FAULT", + "text": "Parameter REPORT_GPA_IN_TVAL_ON_INTERMEDIATE_GUEST_PAGE_FAULT Whether or not GPA >> 2 is written into htval/mtval2 when a guest page fault occurs while\nwalking a VS-mode page table.\n\nIf false, 0 will be written into htval/mtval2 on an intermediate guest page fault. Schema: type=boolean. Defined by: H.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "H" + }, + { + "chunk_id": "chunk_28cb12a1", + "source": "udb_param", + "source_file": "std/isa/param/REPORT_GPA_IN_TVAL_ON_LOAD_GUEST_PAGE_FAULT.yaml", + "section": "REPORT_GPA_IN_TVAL_ON_LOAD_GUEST_PAGE_FAULT", + "text": "Parameter REPORT_GPA_IN_TVAL_ON_LOAD_GUEST_PAGE_FAULT Whether or not GPA >> 2 is written into htval/mtval2 when a load guest page fault occurs.\n\nIf false, 0 will be written into htval/mtval2 on a load guest page fault. Schema: type=boolean. Defined by: H.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "H" + }, + { + "chunk_id": "chunk_58ac6496", + "source": "udb_param", + "source_file": "std/isa/param/REPORT_GPA_IN_TVAL_ON_STORE_AMO_GUEST_PAGE_FAULT.yaml", + "section": "REPORT_GPA_IN_TVAL_ON_STORE_AMO_GUEST_PAGE_FAULT", + "text": "Parameter REPORT_GPA_IN_TVAL_ON_STORE_AMO_GUEST_PAGE_FAULT Whether or not GPA >> 2 is written into htval/mtval2 when a store/amo guest page fault occurs.\n\nIf false, 0 will be written into htval/mtval2 on a store/amo guest page fault. Schema: type=boolean. Defined by: H.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "H" + }, + { + "chunk_id": "chunk_4ee73ce4", + "source": "udb_param", + "source_file": "std/isa/param/REPORT_VA_IN_MTVAL_ON_BREAKPOINT.yaml", + "section": "REPORT_VA_IN_MTVAL_ON_BREAKPOINT", + "text": "Parameter REPORT_VA_IN_MTVAL_ON_BREAKPOINT Options:\n\n * true: `mtval` is written with the virtual PC of an EBREAK instruction (same information as `mepc`).\n * false: `mtval` is written with 0 on an EBREAK instruction.\n\nRegardless, `mtval` is always written with a virtual PC when an external breakpoint is generated Schema: type=boolean. Defined by: Sm.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "Sm" + }, + { + "chunk_id": "chunk_205fa6f9", + "source": "udb_param", + "source_file": "std/isa/param/REPORT_VA_IN_MTVAL_ON_INSTRUCTION_ACCESS_FAULT.yaml", + "section": "REPORT_VA_IN_MTVAL_ON_INSTRUCTION_ACCESS_FAULT", + "text": "Parameter REPORT_VA_IN_MTVAL_ON_INSTRUCTION_ACCESS_FAULT Options:\n\n * true: `mtval` is written with the virtual address of a fetch causing the access fault\n * false: `mtval` is written with 0 when a fetch causes an access fault Schema: type=boolean. Defined by: Sm.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "Sm" + }, + { + "chunk_id": "chunk_f739c66d", + "source": "udb_param", + "source_file": "std/isa/param/REPORT_VA_IN_MTVAL_ON_INSTRUCTION_MISALIGNED.yaml", + "section": "REPORT_VA_IN_MTVAL_ON_INSTRUCTION_MISALIGNED", + "text": "Parameter REPORT_VA_IN_MTVAL_ON_INSTRUCTION_MISALIGNED Options:\n\n * true: `mtval` is written with the virtual address of a trapping misaligned fetch\n * false: `mtval` is written with 0 when a misaligned fetch traps Schema: type=boolean. Defined by: Sm.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "Sm" + }, + { + "chunk_id": "chunk_b3a751f6", + "source": "udb_param", + "source_file": "std/isa/param/REPORT_VA_IN_MTVAL_ON_INSTRUCTION_PAGE_FAULT.yaml", + "section": "REPORT_VA_IN_MTVAL_ON_INSTRUCTION_PAGE_FAULT", + "text": "Parameter REPORT_VA_IN_MTVAL_ON_INSTRUCTION_PAGE_FAULT When true, `mtval` is written with the virtual PC of an instructino when fetch causes an\n`InstructionPageFault`.\n\nWHen false, `mtval` is written with 0 when an instruction fetch causes an\n`InstructionPageFault`. Schema: type=boolean. Defined by: S.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "S" + }, + { + "chunk_id": "chunk_3f4a34df", + "source": "udb_param", + "source_file": "std/isa/param/REPORT_VA_IN_MTVAL_ON_LOAD_ACCESS_FAULT.yaml", + "section": "REPORT_VA_IN_MTVAL_ON_LOAD_ACCESS_FAULT", + "text": "Parameter REPORT_VA_IN_MTVAL_ON_LOAD_ACCESS_FAULT Options:\n\n * true: `mtval` is written with the virtual address of a load causing the access fault\n * false: `mtval` is written with 0 when a load causes an access fault Schema: type=boolean. Defined by: Sm.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "Sm" + }, + { + "chunk_id": "chunk_d9f3b7ec", + "source": "udb_param", + "source_file": "std/isa/param/REPORT_VA_IN_MTVAL_ON_LOAD_MISALIGNED.yaml", + "section": "REPORT_VA_IN_MTVAL_ON_LOAD_MISALIGNED", + "text": "Parameter REPORT_VA_IN_MTVAL_ON_LOAD_MISALIGNED Options:\n\n * true: `mtval` is written with the virtual address of a trapping misaligned load.\n * false: `mtval` is written with 0 when a misaligned load traps. Schema: type=boolean. Defined by: Sm.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "Sm" + }, + { + "chunk_id": "chunk_aa55b061", + "source": "udb_param", + "source_file": "std/isa/param/REPORT_VA_IN_MTVAL_ON_LOAD_PAGE_FAULT.yaml", + "section": "REPORT_VA_IN_MTVAL_ON_LOAD_PAGE_FAULT", + "text": "Parameter REPORT_VA_IN_MTVAL_ON_LOAD_PAGE_FAULT When true, `mtval` is written with the virtual address of a load when it causes a\n`LoadPageFault`.\n\nWHen false, `mtval` is written with 0 when a load causes a `LoadPageFault`. Schema: type=boolean. Defined by: S.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "S" + }, + { + "chunk_id": "chunk_4fb7d0e1", + "source": "udb_param", + "source_file": "std/isa/param/REPORT_VA_IN_MTVAL_ON_STORE_AMO_ACCESS_FAULT.yaml", + "section": "REPORT_VA_IN_MTVAL_ON_STORE_AMO_ACCESS_FAULT", + "text": "Parameter REPORT_VA_IN_MTVAL_ON_STORE_AMO_ACCESS_FAULT Options:\n\n * true: `mtval` is written with the virtual address of a store or AMO causing the access fault\n * false: `mtval` is written with 0 when a store or AMO causes an access fault Schema: type=boolean. Defined by: Sm.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "Sm" + }, + { + "chunk_id": "chunk_048e2cb0", + "source": "udb_param", + "source_file": "std/isa/param/REPORT_VA_IN_MTVAL_ON_STORE_AMO_MISALIGNED.yaml", + "section": "REPORT_VA_IN_MTVAL_ON_STORE_AMO_MISALIGNED", + "text": "Parameter REPORT_VA_IN_MTVAL_ON_STORE_AMO_MISALIGNED Options:\n\n * true: `mtval` is written with the virtual address of a trapping misaligned store or AMO.\n * false: `mtval` is written with 0 when a misaligned store or AMO traps. Schema: type=boolean. Defined by: Sm.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "Sm" + }, + { + "chunk_id": "chunk_02393f81", + "source": "udb_param", + "source_file": "std/isa/param/REPORT_VA_IN_MTVAL_ON_STORE_AMO_PAGE_FAULT.yaml", + "section": "REPORT_VA_IN_MTVAL_ON_STORE_AMO_PAGE_FAULT", + "text": "Parameter REPORT_VA_IN_MTVAL_ON_STORE_AMO_PAGE_FAULT When true, `mtval` is written with the virtual address of a store when it causes a\n`StoreAmoPageFault`.\n\nWHen false, `mtval` is written with 0 when a store causes a `StoreAmoPageFault`. Schema: type=boolean. Defined by: S.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "S" + }, + { + "chunk_id": "chunk_1567a2ca", + "source": "udb_param", + "source_file": "std/isa/param/REPORT_VA_IN_STVAL_ON_BREAKPOINT.yaml", + "section": "REPORT_VA_IN_STVAL_ON_BREAKPOINT", + "text": "Parameter REPORT_VA_IN_STVAL_ON_BREAKPOINT When true, `stval` is written with the virtual PC of the EBREAK instruction (same information as `mepc`).\n\nWhen false, `stval` is written with 0 on an EBREAK instruction.\n\nRegardless, `stval` is always written with a virtual PC when an external breakpoint is generated Schema: type=boolean. Defined by: S.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "S" + }, + { + "chunk_id": "chunk_50159008", + "source": "udb_param", + "source_file": "std/isa/param/REPORT_VA_IN_STVAL_ON_INSTRUCTION_ACCESS_FAULT.yaml", + "section": "REPORT_VA_IN_STVAL_ON_INSTRUCTION_ACCESS_FAULT", + "text": "Parameter REPORT_VA_IN_STVAL_ON_INSTRUCTION_ACCESS_FAULT When true, `stval` is written with the virtual PC of an instructino when fetch causes an\n`InstructionAccessFault`.\n\nWHen false, `stval` is written with 0 when an instruction fetch causes an\n`InstructionAccessFault`. Schema: type=boolean. Defined by: S.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "S" + }, + { + "chunk_id": "chunk_0afd5321", + "source": "udb_param", + "source_file": "std/isa/param/REPORT_VA_IN_STVAL_ON_INSTRUCTION_MISALIGNED.yaml", + "section": "REPORT_VA_IN_STVAL_ON_INSTRUCTION_MISALIGNED", + "text": "Parameter REPORT_VA_IN_STVAL_ON_INSTRUCTION_MISALIGNED When true, `stval` is written with the virtual PC when an instruction fetch is misaligned.\n\nWhen false, `stval` is written with 0 when an instruction fetch is misaligned.\n\nNote that when IALIGN=16 (i.e., when the `C` or one of the `Zc*` extensions are implemented),\nit is impossible to generate a misaligned fetch, and so this parameter has no effect. Schema: type=boolean. Defined by: S.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "S" + }, + { + "chunk_id": "chunk_2125b728", + "source": "udb_param", + "source_file": "std/isa/param/REPORT_VA_IN_STVAL_ON_INSTRUCTION_PAGE_FAULT.yaml", + "section": "REPORT_VA_IN_STVAL_ON_INSTRUCTION_PAGE_FAULT", + "text": "Parameter REPORT_VA_IN_STVAL_ON_INSTRUCTION_PAGE_FAULT When true, `stval` is written with the virtual PC of an instructino when fetch causes an\n`InstructionPageFault`.\n\nWHen false, `stval` is written with 0 when an instruction fetch causes an\n`InstructionPageFault`. Schema: type=boolean. Defined by: S.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "S" + }, + { + "chunk_id": "chunk_ea916c47", + "source": "udb_param", + "source_file": "std/isa/param/REPORT_VA_IN_STVAL_ON_LOAD_ACCESS_FAULT.yaml", + "section": "REPORT_VA_IN_STVAL_ON_LOAD_ACCESS_FAULT", + "text": "Parameter REPORT_VA_IN_STVAL_ON_LOAD_ACCESS_FAULT When true, `stval` is written with the virtual address of a load when it causes a\n`LoadAccessFault`.\n\nWHen false, `stval` is written with 0 when a load causes a `LoadAccessFault`. Schema: type=boolean. Defined by: S.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "S" + }, + { + "chunk_id": "chunk_526fbea6", + "source": "udb_param", + "source_file": "std/isa/param/REPORT_VA_IN_STVAL_ON_LOAD_MISALIGNED.yaml", + "section": "REPORT_VA_IN_STVAL_ON_LOAD_MISALIGNED", + "text": "Parameter REPORT_VA_IN_STVAL_ON_LOAD_MISALIGNED When true, `stval` is written with the virtual address of a load instruction when the\naddress is misaligned and MISALIGNED_LDST is false.\n\nWhen false, `stval` is written with 0 when a load address is misaligned and\nMISALIGNED_LDST is false. Schema: type=boolean. Defined by: S.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "S" + }, + { + "chunk_id": "chunk_17a9a881", + "source": "udb_param", + "source_file": "std/isa/param/REPORT_VA_IN_STVAL_ON_LOAD_PAGE_FAULT.yaml", + "section": "REPORT_VA_IN_STVAL_ON_LOAD_PAGE_FAULT", + "text": "Parameter REPORT_VA_IN_STVAL_ON_LOAD_PAGE_FAULT When true, `stval` is written with the virtual address of a load when it causes a\n`LoadPageFault`.\n\nWHen false, `stval` is written with 0 when a load causes a `LoadPageFault`. Schema: type=boolean. Defined by: S.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "S" + }, + { + "chunk_id": "chunk_5ffbf135", + "source": "udb_param", + "source_file": "std/isa/param/REPORT_VA_IN_STVAL_ON_STORE_AMO_ACCESS_FAULT.yaml", + "section": "REPORT_VA_IN_STVAL_ON_STORE_AMO_ACCESS_FAULT", + "text": "Parameter REPORT_VA_IN_STVAL_ON_STORE_AMO_ACCESS_FAULT When true, `stval` is written with the virtual address of a store when it causes a\n`StoreAmoAccessFault`.\n\nWHen false, `stval` is written with 0 when a store causes a `StoreAmoAccessFault`. Schema: type=boolean. Defined by: S.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "S" + }, + { + "chunk_id": "chunk_6e36cf2c", + "source": "udb_param", + "source_file": "std/isa/param/REPORT_VA_IN_STVAL_ON_STORE_AMO_MISALIGNED.yaml", + "section": "REPORT_VA_IN_STVAL_ON_STORE_AMO_MISALIGNED", + "text": "Parameter REPORT_VA_IN_STVAL_ON_STORE_AMO_MISALIGNED When true, `stval` is written with the virtual address of a store instruction when the\naddress is misaligned and MISALIGNED_LDST is false.\n\nWhen false, `stval` is written with 0 when a store address is misaligned and\nMISALIGNED_LDST is false. Schema: type=boolean. Defined by: S.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "S" + }, + { + "chunk_id": "chunk_42626020", + "source": "udb_param", + "source_file": "std/isa/param/REPORT_VA_IN_STVAL_ON_STORE_AMO_PAGE_FAULT.yaml", + "section": "REPORT_VA_IN_STVAL_ON_STORE_AMO_PAGE_FAULT", + "text": "Parameter REPORT_VA_IN_STVAL_ON_STORE_AMO_PAGE_FAULT When true, `stval` is written with the virtual address of a store when it causes a\n`StoreAmoPageFault`.\n\nWHen false, `stval` is written with 0 when a store causes a `StoreAmoPageFault`. Schema: type=boolean. Defined by: S.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "S" + }, + { + "chunk_id": "chunk_099f842d", + "source": "udb_param", + "source_file": "std/isa/param/REPORT_VA_IN_VSTVAL_ON_BREAKPOINT.yaml", + "section": "REPORT_VA_IN_VSTVAL_ON_BREAKPOINT", + "text": "Parameter REPORT_VA_IN_VSTVAL_ON_BREAKPOINT When true, `vstval` is written with the virtual PC of the EBREAK instruction (same information as `mepc`).\n\nWhen false, `vstval` is written with 0 on an EBREAK instruction.\n\nRegardless, `vstval` is always written with a virtual PC when an external breakpoint is generated. Schema: type=boolean. Defined by: H.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "H" + }, + { + "chunk_id": "chunk_4c686bcd", + "source": "udb_param", + "source_file": "std/isa/param/REPORT_VA_IN_VSTVAL_ON_INSTRUCTION_ACCESS_FAULT.yaml", + "section": "REPORT_VA_IN_VSTVAL_ON_INSTRUCTION_ACCESS_FAULT", + "text": "Parameter REPORT_VA_IN_VSTVAL_ON_INSTRUCTION_ACCESS_FAULT When true, `vstval` is written with the virtual PC of an instructino when fetch causes an\n`InstructionAccessFault`.\n\nWHen false, `vstval` is written with 0 when an instruction fetch causes an\n`InstructionAccessFault`. Schema: type=boolean. Defined by: H.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "H" + }, + { + "chunk_id": "chunk_33591af8", + "source": "udb_param", + "source_file": "std/isa/param/REPORT_VA_IN_VSTVAL_ON_INSTRUCTION_MISALIGNED.yaml", + "section": "REPORT_VA_IN_VSTVAL_ON_INSTRUCTION_MISALIGNED", + "text": "Parameter REPORT_VA_IN_VSTVAL_ON_INSTRUCTION_MISALIGNED When true, `vstval` is written with the virtual PC when an instruction fetch is misaligned.\n\nWhen false, `vstval` is written with 0 when an instruction fetch is misaligned.\n\nNote that when IALIGN=16 (i.e., when the `C` or one of the `Zc*` extensions are implemented),\nit is impossible to generate a misaligned fetch, and so this parameter has no effect. Schema: type=boolean. Defined by: H.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "H" + }, + { + "chunk_id": "chunk_92e6ec77", + "source": "udb_param", + "source_file": "std/isa/param/REPORT_VA_IN_VSTVAL_ON_INSTRUCTION_PAGE_FAULT.yaml", + "section": "REPORT_VA_IN_VSTVAL_ON_INSTRUCTION_PAGE_FAULT", + "text": "Parameter REPORT_VA_IN_VSTVAL_ON_INSTRUCTION_PAGE_FAULT When true, `vstval` is written with the virtual PC of an instructino when fetch causes an\n`InstructionPageFault`.\n\nWHen false, `vstval` is written with 0 when an instruction fetch causes an\n`InstructionPageFault`. Schema: type=boolean. Defined by: H.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "H" + }, + { + "chunk_id": "chunk_b5ea30dc", + "source": "udb_param", + "source_file": "std/isa/param/REPORT_VA_IN_VSTVAL_ON_LOAD_ACCESS_FAULT.yaml", + "section": "REPORT_VA_IN_VSTVAL_ON_LOAD_ACCESS_FAULT", + "text": "Parameter REPORT_VA_IN_VSTVAL_ON_LOAD_ACCESS_FAULT When true, `vstval` is written with the virtual address of a load when it causes a\n`LoadAccessFault`.\n\nWHen false, `vstval` is written with 0 when a load causes a `LoadAccessFault`. Schema: type=boolean. Defined by: H.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "H" + }, + { + "chunk_id": "chunk_c41f929c", + "source": "udb_param", + "source_file": "std/isa/param/REPORT_VA_IN_VSTVAL_ON_LOAD_MISALIGNED.yaml", + "section": "REPORT_VA_IN_VSTVAL_ON_LOAD_MISALIGNED", + "text": "Parameter REPORT_VA_IN_VSTVAL_ON_LOAD_MISALIGNED When true, `vstval` is written with the virtual address of a load instruction when the\naddress is misaligned and MISALIGNED_LDST is false.\n\nWhen false, `vstval` is written with 0 when a load address is misaligned and\nMISALIGNED_LDST is false. Schema: type=boolean. Defined by: H.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "H" + }, + { + "chunk_id": "chunk_440c5b50", + "source": "udb_param", + "source_file": "std/isa/param/REPORT_VA_IN_VSTVAL_ON_LOAD_PAGE_FAULT.yaml", + "section": "REPORT_VA_IN_VSTVAL_ON_LOAD_PAGE_FAULT", + "text": "Parameter REPORT_VA_IN_VSTVAL_ON_LOAD_PAGE_FAULT When true, `vstval` is written with the virtual address of a load when it causes a\n`LoadPageFault`.\n\nWHen false, `vstval` is written with 0 when a load causes a `LoadPageFault`. Schema: type=boolean. Defined by: H.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "H" + }, + { + "chunk_id": "chunk_25b192dd", + "source": "udb_param", + "source_file": "std/isa/param/REPORT_VA_IN_VSTVAL_ON_STORE_AMO_ACCESS_FAULT.yaml", + "section": "REPORT_VA_IN_VSTVAL_ON_STORE_AMO_ACCESS_FAULT", + "text": "Parameter REPORT_VA_IN_VSTVAL_ON_STORE_AMO_ACCESS_FAULT When true, `vstval` is written with the virtual address of a store when it causes a\n`StoreAmoAccessFault`.\n\nWHen false, `vstval` is written with 0 when a store causes a `StoreAmoAccessFault`. Schema: type=boolean. Defined by: H.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "H" + }, + { + "chunk_id": "chunk_9373734f", + "source": "udb_param", + "source_file": "std/isa/param/REPORT_VA_IN_VSTVAL_ON_STORE_AMO_MISALIGNED.yaml", + "section": "REPORT_VA_IN_VSTVAL_ON_STORE_AMO_MISALIGNED", + "text": "Parameter REPORT_VA_IN_VSTVAL_ON_STORE_AMO_MISALIGNED When true, `vstval` is written with the virtual address of a store instruction when the\naddress is misaligned and MISALIGNED_LDST is false.\n\nWhen false, `vstval` is written with 0 when a store address is misaligned and\nMISALIGNED_LDST is false. Schema: type=boolean. Defined by: H.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "H" + }, + { + "chunk_id": "chunk_0f9c8ae7", + "source": "udb_param", + "source_file": "std/isa/param/REPORT_VA_IN_VSTVAL_ON_STORE_AMO_PAGE_FAULT.yaml", + "section": "REPORT_VA_IN_VSTVAL_ON_STORE_AMO_PAGE_FAULT", + "text": "Parameter REPORT_VA_IN_VSTVAL_ON_STORE_AMO_PAGE_FAULT When true, `vstval` is written with the virtual address of a store when it causes a\n`StoreAmoPageFault`.\n\nWHen false, `vstval` is written with 0 when a store causes a `StoreAmoPageFault`. Schema: type=boolean. Defined by: H.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "H" + }, + { + "chunk_id": "chunk_dbb9a9b9", + "source": "udb_param", + "source_file": "std/isa/param/RESERVED_VSET_X0X0_VILL_SET.yaml", + "section": "RESERVED_VSET_X0X0_VILL_SET", + "text": "Parameter RESERVED_VSET_X0X0_VILL_SET When rs1 = x0 and rd = x0, vset instructions act as if the current\nvector length in `vl` is used as the AVL. If `vill` is set or the\nconfiguration is reserved, implementations may set `vill` to indicate\nunsupported use of these encodings. Schema: type=string, enum: never, always, custom. Defined by: Zvl32b.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "confidence": "high", + "defined_by": "Zvl32b" + }, + { + "chunk_id": "chunk_8df7198b", + "source": "udb_param", + "source_file": "std/isa/param/RESERVED_VSET_X0X0_VLMAX_CHANGE.yaml", + "section": "RESERVED_VSET_X0X0_VLMAX_CHANGE", + "text": "Parameter RESERVED_VSET_X0X0_VLMAX_CHANGE When rs1=x0 and rd=x0, the instructions operate as if the current vector length in vl is used as the AVL.\nUse of the vset instructions with a new SEW/LMUL ratio that would result in a change of VLMAX is reserved.\nImplementations may set vill in either case. Schema: type=string, enum: never, always, custom. Defined by: Zvl32b.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "confidence": "high", + "defined_by": "Zvl32b" + }, + { + "chunk_id": "chunk_f570683c", + "source": "udb_param", + "source_file": "std/isa/param/RVV_VL_WHEN_AVL_LT_DOUBLE_VLMAX.yaml", + "section": "RVV_VL_WHEN_AVL_LT_DOUBLE_VLMAX", + "text": "Parameter RVV_VL_WHEN_AVL_LT_DOUBLE_VLMAX The value assigned to VL when AVL < 2*VLMAX. Schema: type=string, enum: ceil(AVL/2), VLMAX, custom. Defined by: Zvl32b.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "confidence": "high", + "defined_by": "Zvl32b" + }, + { + "chunk_id": "chunk_42b0346d", + "source": "udb_param", + "source_file": "std/isa/param/SATP_MODE_BARE.yaml", + "section": "SATP_MODE_BARE", + "text": "Parameter SATP_MODE_BARE Whether or not satp.MODE == Bare is supported. Schema: type=boolean. Defined by: S.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "S" + }, + { + "chunk_id": "chunk_046f7b66", + "source": "udb_param", + "source_file": "std/isa/param/SCOUNTENABLE_EN.yaml", + "section": "SCOUNTENABLE_EN", + "text": "Parameter SCOUNTENABLE_EN Indicates which counters can delegated via `scounteren`\n\nAn unimplemented counter cannot be specified, i.e., if\nHPM_COUNTER_EN[3] is false, it would be illegal to set\nSCOUNTENABLE_EN[3] to true.\n\nSCOUNTENABLE_EN[0:2] must all be false if `Zicntr` is not implemented.\nSCOUNTENABLE_EN[3:31] must all be false if `Zihpm` is not implemented. Schema: type=array. Defined by: Sm.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "confidence": "high", + "defined_by": "Sm" + }, + { + "chunk_id": "chunk_0428ab09", + "source": "udb_param", + "source_file": "std/isa/param/SEW_MIN.yaml", + "section": "SEW_MIN", + "text": "Parameter SEW_MIN Implementations must provide fractional LMUL settings that allow the\nnarrowest supported element width (SEW) to occupy a fractional\nportion of a vector register relative to the widest supported SEW.\nIn general, implementations must support LMUL >= SEW_MIN/ELEN, where\nSEW_MIN is the narrowest supported SEW and ELEN is the widest SEW. Schema: type=integer, enum: 8, 16, 32, 64. Defined by: Zvl32b.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "confidence": "high", + "defined_by": "Zvl32b" + }, + { + "chunk_id": "chunk_0cf7ca28", + "source": "udb_param", + "source_file": "std/isa/param/SSTATEEN_JVT_TYPE.yaml", + "section": "SSTATEEN_JVT_TYPE", + "text": "Parameter SSTATEEN_JVT_TYPE Behavior of the sstateen0.JVT bit:\n\n * 'rw': read-write\n * 'read-only-0': read-only, fixed to 0\n * 'read-only-1': read-only, fixed to 1 Schema: type=string, enum: rw, read-only-0, read-only-1.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_3e6de1d9", + "source": "udb_param", + "source_file": "std/isa/param/STVAL_WIDTH.yaml", + "section": "STVAL_WIDTH", + "text": "Parameter STVAL_WIDTH The number of implemented bits in `stval`.\n\nMust be greater than or equal to _max_(`PHYS_ADDR_WIDTH`, `VA_SIZE`) Schema: type=integer, range=[None, 18446744073709551615]. Defined by: S.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "confidence": "high", + "defined_by": "S" + }, + { + "chunk_id": "chunk_2e14b3d0", + "source": "udb_param", + "source_file": "std/isa/param/STVEC_MODE_DIRECT.yaml", + "section": "STVEC_MODE_DIRECT", + "text": "Parameter STVEC_MODE_DIRECT Whether or not `stvec.MODE` supports Direct (0). Schema: type=boolean. Defined by: S.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "S" + }, + { + "chunk_id": "chunk_47d47fef", + "source": "udb_param", + "source_file": "std/isa/param/STVEC_MODE_VECTORED.yaml", + "section": "STVEC_MODE_VECTORED", + "text": "Parameter STVEC_MODE_VECTORED Whether or not `stvec.MODE` supports Vectored (1). Schema: type=boolean. Defined by: S.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "S" + }, + { + "chunk_id": "chunk_bcf6f132", + "source": "udb_param", + "source_file": "std/isa/param/SUPPORT_FRACTIONAL_LMUL_BEYOND_REQUIRED.yaml", + "section": "SUPPORT_FRACTIONAL_LMUL_BEYOND_REQUIRED", + "text": "Parameter SUPPORT_FRACTIONAL_LMUL_BEYOND_REQUIRED For a given supported fractional LMUL setting, implementations must\nprovide support for SEW settings covering the range from SEW_MIN\nup to LMUL * ELEN, inclusive. This ensures types narrower than the\nmaximum SEW are supported when fractional LMULs are selected. Schema: type=string, enum: no_unrequired_supported, custom. Defined by: Zvl32b.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "confidence": "high", + "defined_by": "Zvl32b" + }, + { + "chunk_id": "chunk_b18c46e2", + "source": "udb_param", + "source_file": "std/isa/param/SV32X4_TRANSLATION.yaml", + "section": "SV32X4_TRANSLATION", + "text": "Parameter SV32X4_TRANSLATION Whether or not Sv32x4 translation mode is supported. Schema: type=boolean.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_c748066f", + "source": "udb_param", + "source_file": "std/isa/param/SV32_VSMODE_TRANSLATION.yaml", + "section": "SV32_VSMODE_TRANSLATION", + "text": "Parameter SV32_VSMODE_TRANSLATION Whether or not Sv32 translation is supported in first-stage (VS-stage)\ntranslation. Schema: type=boolean.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_79544334", + "source": "udb_param", + "source_file": "std/isa/param/SV39X4_TRANSLATION.yaml", + "section": "SV39X4_TRANSLATION", + "text": "Parameter SV39X4_TRANSLATION Whether or not Sv39x4 translation mode is supported. Schema: type=boolean.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_a6b5277a", + "source": "udb_param", + "source_file": "std/isa/param/SV39_VSMODE_TRANSLATION.yaml", + "section": "SV39_VSMODE_TRANSLATION", + "text": "Parameter SV39_VSMODE_TRANSLATION Whether or not Sv39 translation is supported in first-stage (VS-stage)\ntranslation. Schema: type=boolean.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_705f8a05", + "source": "udb_param", + "source_file": "std/isa/param/SV48X4_TRANSLATION.yaml", + "section": "SV48X4_TRANSLATION", + "text": "Parameter SV48X4_TRANSLATION Whether or not Sv48x4 translation mode is supported. Schema: type=boolean.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_9243d8bf", + "source": "udb_param", + "source_file": "std/isa/param/SV48_VSMODE_TRANSLATION.yaml", + "section": "SV48_VSMODE_TRANSLATION", + "text": "Parameter SV48_VSMODE_TRANSLATION Whether or not Sv48 translation is supported in first-stage (VS-stage)\ntranslation. Schema: type=boolean.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d8edfb13", + "source": "udb_param", + "source_file": "std/isa/param/SV57X4_TRANSLATION.yaml", + "section": "SV57X4_TRANSLATION", + "text": "Parameter SV57X4_TRANSLATION Whether or not Sv57x4 translation mode is supported. Schema: type=boolean.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_25fe01ba", + "source": "udb_param", + "source_file": "std/isa/param/SV57_VSMODE_TRANSLATION.yaml", + "section": "SV57_VSMODE_TRANSLATION", + "text": "Parameter SV57_VSMODE_TRANSLATION Whether or not Sv57 translation is supported in first-stage (VS-stage)\ntranslation. Schema: type=boolean.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_0d3dc05e", + "source": "udb_param", + "source_file": "std/isa/param/SXLEN.yaml", + "section": "SXLEN", + "text": "Parameter SXLEN Set of XLENs supported in S-mode. Can be one of:\n\n * 32: SXLEN is always 32\n * 64: SXLEN is always 64\n * [32, 64]: SXLEN can be changed (via mstatus.SXL) between 32 and 64 Schema: type=array. Defined by: S.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "confidence": "high", + "defined_by": "S" + }, + { + "chunk_id": "chunk_49b102d5", + "source": "udb_param", + "source_file": "std/isa/param/S_MODE_ENDIANNESS.yaml", + "section": "S_MODE_ENDIANNESS", + "text": "Parameter S_MODE_ENDIANNESS Endianness of data in S-mode. Can be one of:\n\n * little: S-mode data is always little endian\n * big: S-mode data is always big endian\n * dynamic: S-mode data can be either little or big endian,\n depending on the CSR field `mstatus.SBE` Schema: type=string, enum: little, big, dynamic. Defined by: S.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "confidence": "high", + "defined_by": "S" + }, + { + "chunk_id": "chunk_3a6c9b8f", + "source": "udb_param", + "source_file": "std/isa/param/TIME_CSR_IMPLEMENTED.yaml", + "section": "TIME_CSR_IMPLEMENTED", + "text": "Parameter TIME_CSR_IMPLEMENTED Whether or not a real hardware `time` CSR exists. Implementations can either provide a real\nCSR or emulate access at M-mode.\n\nPossible values:\n\ntrue::\n `time`/`timeh` exists, and accessing it will not cause an IllegalInstruction trap\n\nfalse::\n `time`/`timeh` does not exist.\n Accessing the CSR will cause an IllegalInstruction trap or enter an unpredictable state,\n depending on TRAP_ON_UNIMPLEMENTED_CSR.\n Privileged software may emulate the `time` CSR, or may pass the exception to a lower level. Schema: type=boolean. Defined by: Zicntr.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "Zicntr" + }, + { + "chunk_id": "chunk_1d0d12a1", + "source": "udb_param", + "source_file": "std/isa/param/TINST_VALUE_ON_BREAKPOINT.yaml", + "section": "TINST_VALUE_ON_BREAKPOINT", + "text": "Parameter TINST_VALUE_ON_BREAKPOINT Value written into htinst/mtinst on a Breakpoint exception from VU/VS-mode.\n\nPossible values:\n * \"always zero\": Always write the value zero\n * \"custom\": Write a custom value, which results in UNPREDICTABLE Schema: type=string, enum: always zero, custom. Defined by: H.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "confidence": "high", + "defined_by": "H" + }, + { + "chunk_id": "chunk_b870aaf0", + "source": "udb_param", + "source_file": "std/isa/param/TINST_VALUE_ON_FINAL_INSTRUCTION_GUEST_PAGE_FAULT.yaml", + "section": "TINST_VALUE_ON_FINAL_INSTRUCTION_GUEST_PAGE_FAULT", + "text": "Parameter TINST_VALUE_ON_FINAL_INSTRUCTION_GUEST_PAGE_FAULT Value to write into htval/mtval2 when there is a guest page fault on a final translation.\n\nPossible values:\n * \"always zero\": Always write the value zero\n * \"always pseudoinstruction\": Always write the pseudoinstruction Schema: type=string, enum: always zero, always pseudoinstruction. Defined by: H.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "confidence": "high", + "defined_by": "H" + }, + { + "chunk_id": "chunk_df9e00ad", + "source": "udb_param", + "source_file": "std/isa/param/TINST_VALUE_ON_FINAL_LOAD_GUEST_PAGE_FAULT.yaml", + "section": "TINST_VALUE_ON_FINAL_LOAD_GUEST_PAGE_FAULT", + "text": "Parameter TINST_VALUE_ON_FINAL_LOAD_GUEST_PAGE_FAULT Value to write into htval/mtval2 when there is a guest page fault on a final translation.\n\nPossible values:\n * \"always zero\": Always write the value zero\n * \"always pseudoinstruction\": Always write the pseudoinstruction\n * \"always transformed standard instruction\": Always write the transformation of the standard instruction encoding\n * \"custom\": A custom value, which will cause an UNPREDICTABLE event. Schema: type=string, enum: always zero, always pseudoinstruction, always transformed standard instruction, custom. Defined by: H.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "confidence": "high", + "defined_by": "H" + }, + { + "chunk_id": "chunk_f3862416", + "source": "udb_param", + "source_file": "std/isa/param/TINST_VALUE_ON_FINAL_STORE_AMO_GUEST_PAGE_FAULT.yaml", + "section": "TINST_VALUE_ON_FINAL_STORE_AMO_GUEST_PAGE_FAULT", + "text": "Parameter TINST_VALUE_ON_FINAL_STORE_AMO_GUEST_PAGE_FAULT Value to write into htval/mtval2 when there is a guest page fault on a final translation.\n\nPossible values:\n * \"always zero\": Always write the value zero\n * \"always pseudoinstruction\": Always write the pseudoinstruction\n * \"always transformed standard instruction\": Always write the transformation of the standard instruction encoding\n * \"custom\": A custom value, which will cause an UNPREDICTABLE event. Schema: type=string, enum: always zero, always pseudoinstruction, always transformed standard instruction, custom. Defined by: H.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "confidence": "high", + "defined_by": "H" + }, + { + "chunk_id": "chunk_ee42dc16", + "source": "udb_param", + "source_file": "std/isa/param/TINST_VALUE_ON_INSTRUCTION_ADDRESS_MISALIGNED.yaml", + "section": "TINST_VALUE_ON_INSTRUCTION_ADDRESS_MISALIGNED", + "text": "Parameter TINST_VALUE_ON_INSTRUCTION_ADDRESS_MISALIGNED Value written into htinst/mtinst when there is an instruction address misaligned exception.\n\nPossible values:\n * \"always zero\": Always write the value zero\n * \"custom\": Write a custom value, which results in UNPREDICTABLE Schema: type=string, enum: always zero, custom. Defined by: H.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "confidence": "high", + "defined_by": "H" + }, + { + "chunk_id": "chunk_db5b27f1", + "source": "udb_param", + "source_file": "std/isa/param/TINST_VALUE_ON_LOAD_ACCESS_FAULT.yaml", + "section": "TINST_VALUE_ON_LOAD_ACCESS_FAULT", + "text": "Parameter TINST_VALUE_ON_LOAD_ACCESS_FAULT Value written into htinst/mtinst on an AccessFault exception from VU/VS-mode.\n\nPossible values:\n * \"always zero\": Always write the value zero\n * \"always transformed standard instruction\": Always write a transformed standard instruction as defined by H\n * \"custom\": Write a custom value, which results in UNPREDICTABLE Schema: type=string, enum: always zero, always transformed standard instruction, custom. Defined by: H.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "confidence": "high", + "defined_by": "H" + }, + { + "chunk_id": "chunk_2497e0b4", + "source": "udb_param", + "source_file": "std/isa/param/TINST_VALUE_ON_LOAD_ADDRESS_MISALIGNED.yaml", + "section": "TINST_VALUE_ON_LOAD_ADDRESS_MISALIGNED", + "text": "Parameter TINST_VALUE_ON_LOAD_ADDRESS_MISALIGNED Value written into htinst/mtinst on a VirtualInstruction exception from VU/VS-mode.\n\nPossible values:\n * \"always zero\": Always write the value zero\n * \"always transformed standard instruction\": Always write a transformed standard instruction as defined by H\n * \"custom\": Write a custom value, which results in UNPREDICTABLE Schema: type=string, enum: always zero, always transformed standard instruction, custom. Defined by: H.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "confidence": "high", + "defined_by": "H" + }, + { + "chunk_id": "chunk_84533d2a", + "source": "udb_param", + "source_file": "std/isa/param/TINST_VALUE_ON_LOAD_PAGE_FAULT.yaml", + "section": "TINST_VALUE_ON_LOAD_PAGE_FAULT", + "text": "Parameter TINST_VALUE_ON_LOAD_PAGE_FAULT Value written into htinst/mtinst on a LoadPageFault exception from VU/VS-mode.\n\nPossible values:\n * \"always zero\": Always write the value zero\n * \"always transformed standard instruction\": Always write a transformed standard instruction as defined by H\n * \"custom\": Write a custom value, which results in UNPREDICTABLE Schema: type=string, enum: always zero, always transformed standard instruction, custom. Defined by: H.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "confidence": "high", + "defined_by": "H" + }, + { + "chunk_id": "chunk_abebfdd9", + "source": "udb_param", + "source_file": "std/isa/param/TINST_VALUE_ON_MCALL.yaml", + "section": "TINST_VALUE_ON_MCALL", + "text": "Parameter TINST_VALUE_ON_MCALL Value written into htinst/mtinst on a MCall exception from VU/VS-mode.\n\nPossible values:\n * \"always zero\": Always write the value zero\n * \"custom\": Write a custom value, which results in UNPREDICTABLE Schema: type=string, enum: always zero, custom. Defined by: H.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "confidence": "high", + "defined_by": "H" + }, + { + "chunk_id": "chunk_08899032", + "source": "udb_param", + "source_file": "std/isa/param/TINST_VALUE_ON_SCALL.yaml", + "section": "TINST_VALUE_ON_SCALL", + "text": "Parameter TINST_VALUE_ON_SCALL Value written into htinst/mtinst on a SCall exception from VU/VS-mode.\n\nPossible values:\n * \"always zero\": Always write the value zero\n * \"custom\": Write a custom value, which results in UNPREDICTABLE Schema: type=string, enum: always zero, custom. Defined by: H.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "confidence": "high", + "defined_by": "H" + }, + { + "chunk_id": "chunk_04b6ec40", + "source": "udb_param", + "source_file": "std/isa/param/TINST_VALUE_ON_STORE_AMO_ACCESS_FAULT.yaml", + "section": "TINST_VALUE_ON_STORE_AMO_ACCESS_FAULT", + "text": "Parameter TINST_VALUE_ON_STORE_AMO_ACCESS_FAULT Value written into htinst/mtinst on an AccessFault exception from VU/VS-mode.\n\nPossible values:\n * \"always zero\": Always write the value zero\n * \"always transformed standard instruction\": Always write a transformed standard instruction as defined by H\n * \"custom\": Write a custom value, which results in UNPREDICTABLE Schema: type=string, enum: always zero, always transformed standard instruction, custom. Defined by: H.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "confidence": "high", + "defined_by": "H" + }, + { + "chunk_id": "chunk_1bbfdc76", + "source": "udb_param", + "source_file": "std/isa/param/TINST_VALUE_ON_STORE_AMO_ADDRESS_MISALIGNED.yaml", + "section": "TINST_VALUE_ON_STORE_AMO_ADDRESS_MISALIGNED", + "text": "Parameter TINST_VALUE_ON_STORE_AMO_ADDRESS_MISALIGNED Value written into htinst/mtinst on a VirtualInstruction exception from VU/VS-mode.\n\nPossible values:\n * \"always zero\": Always write the value zero\n * \"always transformed standard instruction\": Always write a transformed standard instruction as defined by H\n * \"custom\": Write a custom value, which results in UNPREDICTABLE Schema: type=string, enum: always zero, always transformed standard instruction, custom. Defined by: H.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "confidence": "high", + "defined_by": "H" + }, + { + "chunk_id": "chunk_e3c58520", + "source": "udb_param", + "source_file": "std/isa/param/TINST_VALUE_ON_STORE_AMO_PAGE_FAULT.yaml", + "section": "TINST_VALUE_ON_STORE_AMO_PAGE_FAULT", + "text": "Parameter TINST_VALUE_ON_STORE_AMO_PAGE_FAULT Value written into htinst/mtinst on a StoreAmoPageFault exception from VU/VS-mode.\n\nPossible values:\n * \"always zero\": Always write the value zero\n * \"always transformed standard instruction\": Always write a transformed standard instruction as defined by H\n * \"custom\": Write a custom value, which results in UNPREDICTABLE Schema: type=string, enum: always zero, always transformed standard instruction, custom. Defined by: H.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "confidence": "high", + "defined_by": "H" + }, + { + "chunk_id": "chunk_edf68a2c", + "source": "udb_param", + "source_file": "std/isa/param/TINST_VALUE_ON_UCALL.yaml", + "section": "TINST_VALUE_ON_UCALL", + "text": "Parameter TINST_VALUE_ON_UCALL Value written into htinst/mtinst on a UCall exception from VU/VS-mode.\n\nPossible values:\n * \"always zero\": Always write the value zero\n * \"custom\": Write a custom value, which results in UNPREDICTABLE Schema: type=string, enum: always zero, custom. Defined by: H.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "confidence": "high", + "defined_by": "H" + }, + { + "chunk_id": "chunk_894ec0a5", + "source": "udb_param", + "source_file": "std/isa/param/TINST_VALUE_ON_VIRTUAL_INSTRUCTION.yaml", + "section": "TINST_VALUE_ON_VIRTUAL_INSTRUCTION", + "text": "Parameter TINST_VALUE_ON_VIRTUAL_INSTRUCTION Value written into htinst/mtinst on a VirtualInstruction exception from VU/VS-mode.\n\nPossible values:\n * \"always zero\": Always write the value zero\n * \"custom\": Write a custom value, which results in UNPREDICTABLE Schema: type=string, enum: always zero, custom. Defined by: H.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "confidence": "high", + "defined_by": "H" + }, + { + "chunk_id": "chunk_e7224aca", + "source": "udb_param", + "source_file": "std/isa/param/TINST_VALUE_ON_VSCALL.yaml", + "section": "TINST_VALUE_ON_VSCALL", + "text": "Parameter TINST_VALUE_ON_VSCALL Value written into htinst/mtinst on a VSCall exception from VU/VS-mode.\n\nPossible values:\n * \"always zero\": Always write the value zero\n * \"custom\": Write a custom value, which results in UNPREDICTABLE Schema: type=string, enum: always zero, custom. Defined by: H.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "confidence": "high", + "defined_by": "H" + }, + { + "chunk_id": "chunk_7b80fb3e", + "source": "udb_param", + "source_file": "std/isa/param/TRAP_ON_EBREAK.yaml", + "section": "TRAP_ON_EBREAK", + "text": "Parameter TRAP_ON_EBREAK The spec states that implementations may handle EBREAKs transparently\nwithout raising a trap, in which case the EEI must provide a builtin. Schema: type=boolean. Defined by: Sm.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "Sm" + }, + { + "chunk_id": "chunk_e7487470", + "source": "udb_param", + "source_file": "std/isa/param/TRAP_ON_ECALL_FROM_M.yaml", + "section": "TRAP_ON_ECALL_FROM_M", + "text": "Parameter TRAP_ON_ECALL_FROM_M The spec states that implementations may handle ECALLs transparently\nwithout raising a trap, in which case the EEI must provide a builtin. Schema: type=boolean. Defined by: Sm.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "Sm" + }, + { + "chunk_id": "chunk_a1288d8a", + "source": "udb_param", + "source_file": "std/isa/param/TRAP_ON_ECALL_FROM_S.yaml", + "section": "TRAP_ON_ECALL_FROM_S", + "text": "Parameter TRAP_ON_ECALL_FROM_S Whether or not an ECALL-from-S-mode causes a synchronous exception.\n\nThe spec states that implementations may handle ECALLs transparently\nwithout raising a trap, in which case the EEI must provide a builtin. Schema: type=boolean. Defined by: S.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "S" + }, + { + "chunk_id": "chunk_43b459df", + "source": "udb_param", + "source_file": "std/isa/param/TRAP_ON_ECALL_FROM_U.yaml", + "section": "TRAP_ON_ECALL_FROM_U", + "text": "Parameter TRAP_ON_ECALL_FROM_U Whether or not an ECALL-from-U-mode causes a synchronous exception.\n\nThe spec states that implementations may handle ECALLs transparently\nwithout raising a trap, in which case the EEI must provide a builtin. Schema: type=boolean. Defined by: U.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "U" + }, + { + "chunk_id": "chunk_ac382b50", + "source": "udb_param", + "source_file": "std/isa/param/TRAP_ON_ECALL_FROM_VS.yaml", + "section": "TRAP_ON_ECALL_FROM_VS", + "text": "Parameter TRAP_ON_ECALL_FROM_VS Whether or not an ECALL-from-VS-mode causes a synchronous exception.\n\nThe spec states that implementations may handle ECALLs transparently\nwithout raising a trap, in which case the EEI must provide a builtin. Schema: type=boolean. Defined by: H.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "H" + }, + { + "chunk_id": "chunk_150832f9", + "source": "udb_param", + "source_file": "std/isa/param/TRAP_ON_ILLEGAL_WLRL.yaml", + "section": "TRAP_ON_ILLEGAL_WLRL", + "text": "Parameter TRAP_ON_ILLEGAL_WLRL Options:\n\n * true: Writing an illegal value to a WLRL CSR field will cause an IllegalInstruction exception.\n * false: Writing an illegal value to a WLRL CSR field causes unpredictable behavior. Schema: type=boolean. Defined by: Sm.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "Sm" + }, + { + "chunk_id": "chunk_1337a9a3", + "source": "udb_param", + "source_file": "std/isa/param/TRAP_ON_RESERVED_INSTRUCTION.yaml", + "section": "TRAP_ON_RESERVED_INSTRUCTION", + "text": "Parameter TRAP_ON_RESERVED_INSTRUCTION Options:\n\n * true: Fetching an unimplemented and/or undefined instruction from the standard/reserved opcode space will cause an IllegalInstruction exception.\n * false: Fetching an unimplemented and/or undefined instruction from the standard/reserved opcose space causes unpredictable behavior.\n\nTRAP_ON_RESERVED_INSTRUCTION may be false while TRAP_ON_UNIMPLEMENTED_INSTRUCTION is true\nwhen a custom instruction is implemented in the standard/reserved opcode space. Schema: type=boolean. Defined by: Sm.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "Sm" + }, + { + "chunk_id": "chunk_7f98b808", + "source": "udb_param", + "source_file": "std/isa/param/TRAP_ON_SFENCE_VMA_WHEN_SATP_MODE_IS_READ_ONLY.yaml", + "section": "TRAP_ON_SFENCE_VMA_WHEN_SATP_MODE_IS_READ_ONLY", + "text": "Parameter TRAP_ON_SFENCE_VMA_WHEN_SATP_MODE_IS_READ_ONLY For implementations that make `satp`.MODE read-only zero\n(always Bare, _i.e._, no virtual translation is implemented),\nattempts to execute an SFENCE.VMA instruction might raise an\nillegal-instruction exception.\n\nTRAP_ON_SFENCE_VMA_WHEN_SATP_MODE_IS_READ_ONLY indicates whether\nor not that exception occurs.\n\nTRAP_ON_SFENCE_VMA_WHEN_SATP_MODE_IS_READ_ONLY has no effect when\nsome virtual translation mode is supported. Schema: type=boolean.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_cbda3bf3", + "source": "udb_param", + "source_file": "std/isa/param/TRAP_ON_UNIMPLEMENTED_CSR.yaml", + "section": "TRAP_ON_UNIMPLEMENTED_CSR", + "text": "Parameter TRAP_ON_UNIMPLEMENTED_CSR Options:\n\n * true: Accessing an unimplemented CSR (via a `Zicsr` instruction) will cause an IllegalInstruction exception.\n * false: Accessing an unimplemented CSR (via a `Zicsr` instruction) will cause unpredictable behavior. Schema: type=boolean. Defined by: Sm.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "Sm" + }, + { + "chunk_id": "chunk_ae474934", + "source": "udb_param", + "source_file": "std/isa/param/TRAP_ON_UNIMPLEMENTED_INSTRUCTION.yaml", + "section": "TRAP_ON_UNIMPLEMENTED_INSTRUCTION", + "text": "Parameter TRAP_ON_UNIMPLEMENTED_INSTRUCTION Options:\n\n * true: Fetching an unimplemented instruction will cause an IllegalInstruction exception.\n * false: Fetching an unimplemented instruction causes unpredictable behavior.\n\nAn unimplemented instruction is any instruction encoding that is not defined by the implementation.\nCustom instructions are considered implemented. Schema: type=boolean. Defined by: Sm.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "Sm" + }, + { + "chunk_id": "chunk_350af6a4", + "source": "udb_param", + "source_file": "std/isa/param/UXLEN.yaml", + "section": "UXLEN", + "text": "Parameter UXLEN Set of XLENs supported in U-mode. When both 32 and 64 are supported, SXLEN can be changed,\nvia mstatus.UXL, between 32 and 64. Schema: type=array. Defined by: U.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "confidence": "high", + "defined_by": "U" + }, + { + "chunk_id": "chunk_08e7524a", + "source": "udb_param", + "source_file": "std/isa/param/U_MODE_ENDIANNESS.yaml", + "section": "U_MODE_ENDIANNESS", + "text": "Parameter U_MODE_ENDIANNESS Endianness of data in U-mode. Can be one of:\n\n * little: U-mode data is always little endian\n * big: U-mode data is always big endian\n * dynamic: U-mode data can be either little or big endian,\n depending on the CSR field `mstatus.UBE` Schema: type=string, enum: little, big, dynamic. Defined by: U.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "confidence": "high", + "defined_by": "U" + }, + { + "chunk_id": "chunk_e6cabe43", + "source": "udb_param", + "source_file": "std/isa/param/VECTOR_FF_NO_EXCEPTION_TRIM.yaml", + "section": "VECTOR_FF_NO_EXCEPTION_TRIM", + "text": "Parameter VECTOR_FF_NO_EXCEPTION_TRIM Implementations may process fewer than `vl` elements and reduce `vl`\neven when no exception occurs. However, if `vstart` == 0 and `vl` > 0,\nat least one element must be processed. Schema: type=boolean. Defined by: Zvl32b.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "Zvl32b" + }, + { + "chunk_id": "chunk_08b78d62", + "source": "udb_param", + "source_file": "std/isa/param/VECTOR_FF_SEG_EXCEPTION_PARTIAL_LOAD.yaml", + "section": "VECTOR_FF_SEG_EXCEPTION_PARTIAL_LOAD", + "text": "Parameter VECTOR_FF_SEG_EXCEPTION_PARTIAL_LOAD For fault-only-first segment loads, if an exception occurs partway\nthrough the zeroth segment, the trap is taken. If it occurs in a\nsubsequent segment, `vl` may be reduced to the index of that segment.\nIt is implementation-defined whether a partial subset of the segment\nis loaded before the trap. Schema: type=string, enum: no_subsegment_loaded, custom. Defined by: Zvl32b.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "confidence": "high", + "defined_by": "Zvl32b" + }, + { + "chunk_id": "chunk_946066f7", + "source": "udb_param", + "source_file": "std/isa/param/VECTOR_FF_UPDATE_PAST_TRIM.yaml", + "section": "VECTOR_FF_UPDATE_PAST_TRIM", + "text": "Parameter VECTOR_FF_UPDATE_PAST_TRIM Fault-only-first (FF) load instructions may update active destination\nelements beyond the index that causes vector-length trimming, but not\npast the original `vl`. These spurious updates need not reflect the\ntrue memory contents; non-idempotent memory should only be accessed\nwhen the load is guaranteed not to be retried. Schema: type=string, enum: update_none, custom. Defined by: Zvl32b.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "confidence": "high", + "defined_by": "Zvl32b" + }, + { + "chunk_id": "chunk_7d5c7f9b", + "source": "udb_param", + "source_file": "std/isa/param/VECTOR_LOAD_PAST_TRAP.yaml", + "section": "VECTOR_LOAD_PAST_TRAP", + "text": "Parameter VECTOR_LOAD_PAST_TRAP Vector load instructions may overwrite active destination vector register\ngroup elements past the element index where a trap is reported; the\nbehavior for elements beyond the trap index is implementation-defined. Schema: type=boolean. Defined by: Zvl32b.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "Zvl32b" + }, + { + "chunk_id": "chunk_41e6bdd0", + "source": "udb_param", + "source_file": "std/isa/param/VECTOR_LOAD_SEG_FF_OVERWRITE_ELEMENTS_AFTER_FAULT.yaml", + "section": "VECTOR_LOAD_SEG_FF_OVERWRITE_ELEMENTS_AFTER_FAULT", + "text": "Parameter VECTOR_LOAD_SEG_FF_OVERWRITE_ELEMENTS_AFTER_FAULT Fault-only-first segment load instructions may overwrite destination\nvector register group elements beyond the point where a trap is\nreported or where `vl` is trimmed; the exact values written may be\nimplementation-defined. Schema: type=string, enum: no_overwrite, custom. Defined by: Zvl32b.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "confidence": "high", + "defined_by": "Zvl32b" + }, + { + "chunk_id": "chunk_566d04d0", + "source": "udb_param", + "source_file": "std/isa/param/VECTOR_LS_INDEX_MAX_EEW.yaml", + "section": "VECTOR_LS_INDEX_MAX_EEW", + "text": "Parameter VECTOR_LS_INDEX_MAX_EEW A profile may place an upper limit on the maximum supported index EEW\nused by vector load/store indexing. For example, some profiles may\nlimit indexing to sizes no larger than XLEN or a fixed EEW value. Schema: type=string, enum: 8, 16, 32, 64, XLEN. Defined by: Zvl32b.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "confidence": "high", + "defined_by": "Zvl32b" + }, + { + "chunk_id": "chunk_48c5f308", + "source": "udb_param", + "source_file": "std/isa/param/VECTOR_LS_MISALIGNED_LEGAL.yaml", + "section": "VECTOR_LS_MISALIGNED_LEGAL", + "text": "Parameter VECTOR_LS_MISALIGNED_LEGAL If an element accessed by a vector memory instruction is not naturally aligned to the size of the element,\neither the element is transferred successfully or an address misaligned exception is raised on that element.\nSupport for misaligned vector memory accesses is independent of an implementation's support for misaligned scalar memory accesses. Schema: type=boolean. Defined by: Zvl32b.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "Zvl32b" + }, + { + "chunk_id": "chunk_5c9d3b04", + "source": "udb_param", + "source_file": "std/isa/param/VECTOR_LS_SEG_PARTIAL_ACCESS.yaml", + "section": "VECTOR_LS_SEG_PARTIAL_ACCESS", + "text": "Parameter VECTOR_LS_SEG_PARTIAL_ACCESS If a trap occurs during access to a segment, it is implementation-defined\nwhether some, all, or none of that segment's element accesses are\nperformed before the trap is taken. Schema: type=boolean. Defined by: Zvl32b.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "Zvl32b" + }, + { + "chunk_id": "chunk_f8ccc6aa", + "source": "udb_param", + "source_file": "std/isa/param/VECTOR_LS_WHOLEREG_MISALIGNED_LEGAL.yaml", + "section": "VECTOR_LS_WHOLEREG_MISALIGNED_LEGAL", + "text": "Parameter VECTOR_LS_WHOLEREG_MISALIGNED_LEGAL Implementations may raise a misaligned address exception for whole-register\nloads/stores if the base address is not aligned to the maximum of the\nencoded EEW size (in bytes) or the implementation's smallest supported\nSEW (in bytes). Schema: type=boolean. Defined by: Zvl32b.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "Zvl32b" + }, + { + "chunk_id": "chunk_0021554f", + "source": "udb_param", + "source_file": "std/isa/param/VENDOR_ID_BANK.yaml", + "section": "VENDOR_ID_BANK", + "text": "Parameter VENDOR_ID_BANK Encodes the number of one-byte continuation codes in the Bank field of `mvendorid`.\n\niN JEDEC’s parlance, the bank number is one greater than the number of continuation codes; hence, the mvendorid Bank field encodes a value that is one less than the JEDEC bank number. Schema: type=integer, range=[0, 33554431]. Defined by: Sm.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "confidence": "high", + "defined_by": "Sm" + }, + { + "chunk_id": "chunk_8a4cb654", + "source": "udb_param", + "source_file": "std/isa/param/VENDOR_ID_OFFSET.yaml", + "section": "VENDOR_ID_OFFSET", + "text": "Parameter VENDOR_ID_OFFSET Encodes the final byte of a JEDEC manufactor ID, discarding the parity bit. Schema: type=integer, range=[0, 127]. Defined by: Sm.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "confidence": "high", + "defined_by": "Sm" + }, + { + "chunk_id": "chunk_f4d13c31", + "source": "udb_param", + "source_file": "std/isa/param/VFREDUSUM_FINAL_NODE_ELEMENT_BEHAVIOR.yaml", + "section": "VFREDUSUM_FINAL_NODE_ELEMENT_BEHAVIOR", + "text": "Parameter VFREDUSUM_FINAL_NODE_ELEMENT_BEHAVIOR Implementations are permitted to insert an additional additive identity\ninto the final reduction result, which may affect the final outcome\nwhen no active elements are present. Schema: type=string, enum: additive_identity, copy. Defined by: Zvl32b.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "confidence": "high", + "defined_by": "Zvl32b" + }, + { + "chunk_id": "chunk_c5e52c0f", + "source": "udb_param", + "source_file": "std/isa/param/VFREDUSUM_INACTIVE_NODE_ELEMENT_BEHAVIOR.yaml", + "section": "VFREDUSUM_INACTIVE_NODE_ELEMENT_BEHAVIOR", + "text": "Parameter VFREDUSUM_INACTIVE_NODE_ELEMENT_BEHAVIOR A reduction node that receives an input derived solely from masked-off\nelements or elements beyond `vl` may either treat that input as the\nadditive identity for the appropriate element width or copy the other\ninput through unchanged to the node output. Schema: type=string, enum: additive_identity, copy. Defined by: Zvl32b.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "confidence": "high", + "defined_by": "Zvl32b" + }, + { + "chunk_id": "chunk_a7c91e19", + "source": "udb_param", + "source_file": "std/isa/param/VFREDUSUM_NAN.yaml", + "section": "VFREDUSUM_NAN", + "text": "Parameter VFREDUSUM_NAN The reduction tree structure must be deterministic for a given `vtype`\nand `vl`; as a consequence, implementations need not preserve NaN\npayloads when no elements are active. If no elements are active and the\nscalar input is NaN, implementations may canonicalize it (and raise an\nexception if it is a signaling NaN) or pass it through unchanged. Schema: type=string, enum: no_change, custom. Defined by: Zvl32b.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "confidence": "high", + "defined_by": "Zvl32b" + }, + { + "chunk_id": "chunk_e17310ac", + "source": "udb_param", + "source_file": "std/isa/param/VFREDUSUM_NODE_ROUNDING_BEHAVIOR.yaml", + "section": "VFREDUSUM_NODE_ROUNDING_BEHAVIOR", + "text": "Parameter VFREDUSUM_NODE_ROUNDING_BEHAVIOR Each reduction operator computes an exact sum using an ideal scalar\nfloating-point addition, then converts that result into a floating-\npoint format with range and precision at least as large as the element\nSEW, rounding with the current dynamic rounding mode and raising\nexceptions as needed. Implementations may choose the exact range and\nprecision per operator. Schema: type=string, enum: SEW_precision, custom. Defined by: Zvl32b.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "confidence": "high", + "defined_by": "Zvl32b" + }, + { + "chunk_id": "chunk_c9bfbc59", + "source": "udb_param", + "source_file": "std/isa/param/VILL_SET_ON_RESERVED_VTYPE.yaml", + "section": "VILL_SET_ON_RESERVED_VTYPE", + "text": "Parameter VILL_SET_ON_RESERVED_VTYPE Use of vtype encodings with LMUL < SEW_MIN/ELEN is reserved. Implementations\nmay set the `vill` status bit to indicate such vtype encodings are\nunsupported, providing a software-visible indication of invalid vtype\nselections. Schema: type=boolean. Defined by: Zvl32b.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "Zvl32b" + }, + { + "chunk_id": "chunk_217e43a0", + "source": "udb_param", + "source_file": "std/isa/param/VLEN.yaml", + "section": "VLEN", + "text": "Parameter VLEN The number of bits in a single vector register. Schema: type=integer. Defined by: Zvl32b.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "confidence": "high", + "defined_by": "Zvl32b" + }, + { + "chunk_id": "chunk_4e20f67c", + "source": "udb_param", + "source_file": "std/isa/param/VMID_WIDTH.yaml", + "section": "VMID_WIDTH", + "text": "Parameter VMID_WIDTH Number of bits supported in `hgatp.VMID` (i.e., the supported width of a virtual machine ID). Schema: type=integer, range=[0, 14]. Defined by: H.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "confidence": "high", + "defined_by": "H" + }, + { + "chunk_id": "chunk_2dada451", + "source": "udb_param", + "source_file": "std/isa/param/VSSTAGE_MODE_BARE.yaml", + "section": "VSSTAGE_MODE_BARE", + "text": "Parameter VSSTAGE_MODE_BARE Whether or not writing mode=Bare is supported in the `vsatp` register. Schema: type=boolean. Defined by: H.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "H" + }, + { + "chunk_id": "chunk_0390b5d4", + "source": "udb_param", + "source_file": "std/isa/param/VSSTATUS_VS_EXISTS.yaml", + "section": "VSSTATUS_VS_EXISTS", + "text": "Parameter VSSTATUS_VS_EXISTS Some implementations provide a `vsstatus.VS` field even when the `misa.V`\nbit is clear. This parameter indicates whether `vsstatus.VS` exists\nindependently of the `misa.V` setting. Schema: type=boolean. Defined by: Zvl32b.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "Zvl32b" + }, + { + "chunk_id": "chunk_e4143399", + "source": "udb_param", + "source_file": "std/isa/param/VSTVEC_MODE_DIRECT.yaml", + "section": "VSTVEC_MODE_DIRECT", + "text": "Parameter VSTVEC_MODE_DIRECT Whether or not `vstvec.MODE` supports Direct (0). Schema: type=boolean. Defined by: H.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "H" + }, + { + "chunk_id": "chunk_b3d5b516", + "source": "udb_param", + "source_file": "std/isa/param/VSTVEC_MODE_VECTORED.yaml", + "section": "VSTVEC_MODE_VECTORED", + "text": "Parameter VSTVEC_MODE_VECTORED Whether or not `stvec.MODE` supports Vectored (1). Schema: type=boolean. Defined by: H.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "binary", + "confidence": "high", + "defined_by": "H" + }, + { + "chunk_id": "chunk_5088d1c9", + "source": "udb_param", + "source_file": "std/isa/param/VSXLEN.yaml", + "section": "VSXLEN", + "text": "Parameter VSXLEN Set of XLENs supported in VS-mode. Can be one of:\n\n * [32]: VSXLEN is always 32\n * [64]: VSXLEN is always 64\n * [32, 64]: VSXLEN can be changed (via `hstatus.VSXL`) between 32 and 64 Schema: type=array. Defined by: H.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "confidence": "high", + "defined_by": "H" + }, + { + "chunk_id": "chunk_c2ebd9c6", + "source": "udb_param", + "source_file": "std/isa/param/VS_MODE_ENDIANNESS.yaml", + "section": "VS_MODE_ENDIANNESS", + "text": "Parameter VS_MODE_ENDIANNESS Endianness of data in VS-mode. Can be one of:\n\n * little: VS-mode data is always little endian\n * big: VS-mode data is always big endian\n * dynamic: VS-mode data can be either little or big endian,\n depending on the CSR field `hstatus.VSBE` Schema: type=string, enum: little, big, dynamic. Defined by: H.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "confidence": "high", + "defined_by": "H" + }, + { + "chunk_id": "chunk_0b9689e5", + "source": "udb_param", + "source_file": "std/isa/param/VUXLEN.yaml", + "section": "VUXLEN", + "text": "Parameter VUXLEN Set of XLENs supported in VU-mode. When both 32 and 64 are supported, VUXLEN can be changed\nvia `vsstatus.UXL`. Schema: type=array. Defined by: H.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "range", + "confidence": "high", + "defined_by": "H" + }, + { + "chunk_id": "chunk_7c7bc7d3", + "source": "udb_param", + "source_file": "std/isa/param/VU_MODE_ENDIANNESS.yaml", + "section": "VU_MODE_ENDIANNESS", + "text": "Parameter VU_MODE_ENDIANNESS Endianness of data in VU-mode. Can be one of:\n\n * little: VU-mode data is always little endian\n * big: VU-mode data is always big endian\n * dynamic: VU-mode data can be either little or big endian,\n depending on the CSR field `vsstatus.UBE` Schema: type=string, enum: little, big, dynamic. Defined by: H.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "enum", + "confidence": "high", + "defined_by": "H" + }, + { + "chunk_id": "chunk_81fa8d95", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/F/fcsr.yaml", + "section": "fcsr", + "text": "CSR fcsr (address=3, priv=U): The floating-point control and status register, `fcsr`, is a RISC-V\ncontrol and status register (CSR). It is a 32-bit read/write register\nthat selects the dynamic rounding mode for floating-point arithmetic\noperations and holds the accrued exception flags, as shown in <>.\n\n[[fcsr, Floating-Poi", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "F" + }, + { + "chunk_id": "chunk_72ab2753", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/F/fcsr.yaml", + "section": "fcsr.FRM", + "text": "CSR fcsr field FRM (bits=7-5) Rounding modes are encoded as follows:\n\n[[rm]]\n.Rounding mode encoding.\n[%autowidth,float=\"center\",align=\"center\",cols=\"^,^,<\",options=\"header\"]\n!===\n!Rounding Mode |Mnemonic |Meaning\n!000 !RNE !Round to Nearest, ties to Even\n!001 !RTZ !Round towards Zero\n!010 !RDN !Round Down (towards latexmath:[$- type: RW-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_a344c30d", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/F/fcsr.yaml", + "section": "fcsr.NV", + "text": "CSR fcsr field NV (bits=4) *Invalid Operation*\n\nCumulative error flag for floating point operations.\n\nSet by hardware when a floating point operation is invalid and stays set until explicitly\ncleared by software. type: RW-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_c8fa6aab", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/F/fcsr.yaml", + "section": "fcsr.DZ", + "text": "CSR fcsr field DZ (bits=3) *Divide by zero*\n\nCumulative error flag for floating point operations.\n\nSet by hardware when a floating point divide attempts to divide by zero and stays set until explicitly\ncleared by software. type: RW-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_89b9cd70", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/F/fcsr.yaml", + "section": "fcsr.OF", + "text": "CSR fcsr field OF (bits=2) *Overflow*\n\nCumulative error flag for floating point operations.\n\nSet by hardware when a floating point operation overflows and stays set until explicitly\ncleared by software. type: RW-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_821ddca0", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/F/fcsr.yaml", + "section": "fcsr.UF", + "text": "CSR fcsr field UF (bits=1) *Underflow*\n\nCumulative error flag for floating point operations.\n\nSet by hardware when a floating point operation underflows and stays set until explicitly\ncleared by software. type: RW-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_491816b2", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/F/fcsr.yaml", + "section": "fcsr.NX", + "text": "CSR fcsr field NX (bits=rv32=? rv64=?) *Inexact*\n\nCumulative error flag for floating point operations.\n\nSet by hardware when a floating point operation is inexact and stays set until explicitly\ncleared by software. type: RW-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_143df80a", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/F/fflags.yaml", + "section": "fflags", + "text": "CSR fflags (address=1, priv=U): The accrued exception flags indicate the exception conditions that have arisen on any floating-point arithmetic\ninstruction since the field was last reset by software.\n\nThe base RISC-V ISA does not support generating a trap on the setting of a floating-point exception flag.\n\nAs allowed by the standa", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "F" + }, + { + "chunk_id": "chunk_e8f0f507", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/F/fflags.yaml", + "section": "fflags.NV", + "text": "CSR fflags field NV (bits=4) Set by hardware when a floating point operation is invalid and stays set until explicitly\ncleared by software. type: RW-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_873b3654", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/F/fflags.yaml", + "section": "fflags.DZ", + "text": "CSR fflags field DZ (bits=3) Set by hardware when a floating point divide attempts to divide by zero and stays set until explicitly\ncleared by software. type: RW-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_921b3d07", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/F/fflags.yaml", + "section": "fflags.OF", + "text": "CSR fflags field OF (bits=2) Set by hardware when a floating point operation overflows and stays set until explicitly\ncleared by software. type: RW-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_39aad221", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/F/fflags.yaml", + "section": "fflags.UF", + "text": "CSR fflags field UF (bits=1) Set by hardware when a floating point operation underflows and stays set until explicitly\ncleared by software. type: RW-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_8500dada", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/F/fflags.yaml", + "section": "fflags.NX", + "text": "CSR fflags field NX (bits=rv32=? rv64=?) Set by hardware when a floating point operation is inexact and stays set until explicitly\ncleared by software. type: RW-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_3525dec2", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/F/frm.yaml", + "section": "frm", + "text": "CSR frm (address=2, priv=U): Rounding modes are encoded as follows:\n\n[[rm]]\n.Rounding mode encoding.\n[%autowidth,float=\"center\",align=\"center\",cols=\"^,^,<\",options=\"header\"]\n!===\n!Rounding Mode |Mnemonic |Meaning\n!000 !RNE !Round to Nearest, ties to Even\n!001 !RTZ !Round towards Zero\n!010 !RDN !Round Down (towards latexmath:[$-", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "F" + }, + { + "chunk_id": "chunk_003a15e6", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/F/frm.yaml", + "section": "frm.ROUNDINGMODE", + "text": "CSR frm field ROUNDINGMODE (bits=2-0) Rounding mode data. type: RW-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_57a33031", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/hcounteren.yaml", + "section": "hcounteren", + "text": "CSR hcounteren (address=1542, priv=S): Together with `scounteren`, delegates control of the hardware performance-monitoring counters\nto VS/VU-mode\n\nSee `cycle` for a table describing how exceptions occur.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "H" + }, + { + "chunk_id": "chunk_c23ebe61", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/hcounteren.yaml", + "section": "hcounteren.CY", + "text": "CSR hcounteren field CY (bits=rv32=? rv64=?) When all of `scounteren.CY`, `mcounteren.CY`, and `hcounteren.CY` are set,\nthe `cycle` CSR (an alias of `mcycle`) is accessible to VU-mode.\n\nWhen `mcounteren.CY` and `hcounteren.CY` are set,\nthe `cycle` CSR (an alias of `mcycle`) is accessible to VS-mode.\n\nWhen `hcounteren.CY` is clear and `mcounter type: if (HCOUNTENABLE_EN[0]) { reset: if (HCOUNTENABLE_EN[0]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d7cae602", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/hcounteren.yaml", + "section": "hcounteren.TM", + "text": "CSR hcounteren field TM (bits=1) When all of `scounteren.TM`, `mcounteren.TM`, and `hcounteren.TM` are set,\nthe `time` CSR (an alias of `mtime` memory-mapped CSR) is accessible to VU-mode.\n\nWhen `mcounteren.TM` and `hcounteren.TM` are set,\nthe `time` CSR (an alias of `mtime`) is accessible to VS-mode.\n\nWhen `hcounteren.TM` is clear type: if (HCOUNTENABLE_EN[1]) { reset: if (HCOUNTENABLE_EN[1]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_2dd4f3a8", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/hcounteren.yaml", + "section": "hcounteren.IR", + "text": "CSR hcounteren field IR (bits=2) When all of `scounteren.IR`, `mcounteren.IR`, and `hcounteren.IR` are set,\nthe `instret` CSR (an alias of `minstret`) is accessible to VU-mode.\n\nWhen `mcounteren.IR` and `hcounteren.IR` are set,\nthe `instret` CSR (an alias of `minstret`) is accessible to VS-mode.\n\nWhen `hcounteren.IR` is clear and ` type: if (HCOUNTENABLE_EN[2]) { reset: if (HCOUNTENABLE_EN[2]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_09dd496e", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/hcounteren.yaml", + "section": "hcounteren.HPM3", + "text": "CSR hcounteren field HPM3 (bits=3) When all of `scounteren.HPM3`, `mcounteren.HPM3`, and `hcounteren.HPM3` are set,\nthe `hpmcounter3` CSR (an alias of `mhpmcounter3`) is accessible to VU-mode.\n\nWhen `mcounteren.HPM3` and `hcounteren.HPM3` are set,\nthe `hpmcounter3` CSR (an alias of `mhpmcounter3`) is accessible to VS-mode.\n\nWhen `hco type: if (HCOUNTENABLE_EN[3]) { reset: if (HCOUNTENABLE_EN[3]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_c175db0c", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/hcounteren.yaml", + "section": "hcounteren.HPM4", + "text": "CSR hcounteren field HPM4 (bits=4) When all of `scounteren.HPM4`, `mcounteren.HPM4`, and `hcounteren.HPM4` are set,\nthe `hpmcounter4` CSR (an alias of `mhpmcounter4`) is accessible to VU-mode.\n\nWhen `mcounteren.HPM4` and `hcounteren.HPM4` are set,\nthe `hpmcounter4` CSR (an alias of `mhpmcounter4`) is accessible to VS-mode.\n\nWhen `hco type: if (HCOUNTENABLE_EN[4]) { reset: if (HCOUNTENABLE_EN[4]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_88ee6a39", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/hcounteren.yaml", + "section": "hcounteren.HPM5", + "text": "CSR hcounteren field HPM5 (bits=5) When all of `scounteren.HPM5`, `mcounteren.HPM5`, and `hcounteren.HPM5` are set,\nthe `hpmcounter5` CSR (an alias of `mhpmcounter5`) is accessible to VU-mode.\n\nWhen `mcounteren.HPM5` and `hcounteren.HPM5` are set,\nthe `hpmcounter5` CSR (an alias of `mhpmcounter5`) is accessible to VS-mode.\n\nWhen `hco type: if (HCOUNTENABLE_EN[5]) { reset: if (HCOUNTENABLE_EN[5]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_e15c1ef0", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/hcounteren.yaml", + "section": "hcounteren.HPM6", + "text": "CSR hcounteren field HPM6 (bits=6) When all of `scounteren.HPM6`, `mcounteren.HPM6`, and `hcounteren.HPM6` are set,\nthe `hpmcounter6` CSR (an alias of `mhpmcounter6`) is accessible to VU-mode.\n\nWhen `mcounteren.HPM6` and `hcounteren.HPM6` are set,\nthe `hpmcounter6` CSR (an alias of `mhpmcounter6`) is accessible to VS-mode.\n\nWhen `hco type: if (HCOUNTENABLE_EN[6]) { reset: if (HCOUNTENABLE_EN[6]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_2d05a7c8", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/hcounteren.yaml", + "section": "hcounteren.HPM7", + "text": "CSR hcounteren field HPM7 (bits=7) When all of `scounteren.HPM7`, `mcounteren.HPM7`, and `hcounteren.HPM7` are set,\nthe `hpmcounter7` CSR (an alias of `mhpmcounter7`) is accessible to VU-mode.\n\nWhen `mcounteren.HPM7` and `hcounteren.HPM7` are set,\nthe `hpmcounter7` CSR (an alias of `mhpmcounter7`) is accessible to VS-mode.\n\nWhen `hco type: if (HCOUNTENABLE_EN[7]) { reset: if (HCOUNTENABLE_EN[7]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_1ca7be9a", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/hcounteren.yaml", + "section": "hcounteren.HPM8", + "text": "CSR hcounteren field HPM8 (bits=8) When all of `scounteren.HPM8`, `mcounteren.HPM8`, and `hcounteren.HPM8` are set,\nthe `hpmcounter8` CSR (an alias of `mhpmcounter8`) is accessible to VU-mode.\n\nWhen `mcounteren.HPM8` and `hcounteren.HPM8` are set,\nthe `hpmcounter8` CSR (an alias of `mhpmcounter8`) is accessible to VS-mode.\n\nWhen `hco type: if (HCOUNTENABLE_EN[8]) { reset: if (HCOUNTENABLE_EN[8]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_1a874e58", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/hcounteren.yaml", + "section": "hcounteren.HPM9", + "text": "CSR hcounteren field HPM9 (bits=9) When all of `scounteren.HPM9`, `mcounteren.HPM9`, and `hcounteren.HPM9` are set,\nthe `hpmcounter9` CSR (an alias of `mhpmcounter9`) is accessible to VU-mode.\n\nWhen `mcounteren.HPM9` and `hcounteren.HPM9` are set,\nthe `hpmcounter9` CSR (an alias of `mhpmcounter9`) is accessible to VS-mode.\n\nWhen `hco type: if (HCOUNTENABLE_EN[9]) { reset: if (HCOUNTENABLE_EN[9]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_71039533", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/hcounteren.yaml", + "section": "hcounteren.HPM10", + "text": "CSR hcounteren field HPM10 (bits=10) When all of `scounteren.HPM10`, `mcounteren.HPM10`, and `hcounteren.HPM10` are set,\nthe `hpmcounter10` CSR (an alias of `mhpmcounter10`) is accessible to VU-mode.\n\nWhen `mcounteren.HPM10` and `hcounteren.HPM10` are set,\nthe `hpmcounter10` CSR (an alias of `mhpmcounter10`) is accessible to VS-mode.\n\n type: if (HCOUNTENABLE_EN[10]) { reset: if (HCOUNTENABLE_EN[10]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_7de90bb4", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/hcounteren.yaml", + "section": "hcounteren.HPM11", + "text": "CSR hcounteren field HPM11 (bits=11) When all of `scounteren.HPM11`, `mcounteren.HPM11`, and `hcounteren.HPM11` are set,\nthe `hpmcounter11` CSR (an alias of `mhpmcounter11`) is accessible to VU-mode.\n\nWhen `mcounteren.HPM11` and `hcounteren.HPM11` are set,\nthe `hpmcounter11` CSR (an alias of `mhpmcounter11`) is accessible to VS-mode.\n\n type: if (HCOUNTENABLE_EN[11]) { reset: if (HCOUNTENABLE_EN[11]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ddd73184", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/hcounteren.yaml", + "section": "hcounteren.HPM12", + "text": "CSR hcounteren field HPM12 (bits=12) When all of `scounteren.HPM12`, `mcounteren.HPM12`, and `hcounteren.HPM12` are set,\nthe `hpmcounter12` CSR (an alias of `mhpmcounter12`) is accessible to VU-mode.\n\nWhen `mcounteren.HPM12` and `hcounteren.HPM12` are set,\nthe `hpmcounter12` CSR (an alias of `mhpmcounter12`) is accessible to VS-mode.\n\n type: if (HCOUNTENABLE_EN[12]) { reset: if (HCOUNTENABLE_EN[12]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_8bce95b2", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/hcounteren.yaml", + "section": "hcounteren.HPM13", + "text": "CSR hcounteren field HPM13 (bits=13) When all of `scounteren.HPM13`, `mcounteren.HPM13`, and `hcounteren.HPM13` are set,\nthe `hpmcounter13` CSR (an alias of `mhpmcounter13`) is accessible to VU-mode.\n\nWhen `mcounteren.HPM13` and `hcounteren.HPM13` are set,\nthe `hpmcounter13` CSR (an alias of `mhpmcounter13`) is accessible to VS-mode.\n\n type: if (HCOUNTENABLE_EN[13]) { reset: if (HCOUNTENABLE_EN[13]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_b22a7590", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/hcounteren.yaml", + "section": "hcounteren.HPM14", + "text": "CSR hcounteren field HPM14 (bits=14) When all of `scounteren.HPM14`, `mcounteren.HPM14`, and `hcounteren.HPM14` are set,\nthe `hpmcounter14` CSR (an alias of `mhpmcounter14`) is accessible to VU-mode.\n\nWhen `mcounteren.HPM14` and `hcounteren.HPM14` are set,\nthe `hpmcounter14` CSR (an alias of `mhpmcounter14`) is accessible to VS-mode.\n\n type: if (HCOUNTENABLE_EN[14]) { reset: if (HCOUNTENABLE_EN[14]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_6fc766a6", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/hcounteren.yaml", + "section": "hcounteren.HPM15", + "text": "CSR hcounteren field HPM15 (bits=15) When all of `scounteren.HPM15`, `mcounteren.HPM15`, and `hcounteren.HPM15` are set,\nthe `hpmcounter15` CSR (an alias of `mhpmcounter15`) is accessible to VU-mode.\n\nWhen `mcounteren.HPM15` and `hcounteren.HPM15` are set,\nthe `hpmcounter15` CSR (an alias of `mhpmcounter15`) is accessible to VS-mode.\n\n type: if (HCOUNTENABLE_EN[15]) { reset: if (HCOUNTENABLE_EN[15]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_b09393b5", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/hcounteren.yaml", + "section": "hcounteren.HPM16", + "text": "CSR hcounteren field HPM16 (bits=16) When all of `scounteren.HPM16`, `mcounteren.HPM16`, and `hcounteren.HPM16` are set,\nthe `hpmcounter16` CSR (an alias of `mhpmcounter16`) is accessible to VU-mode.\n\nWhen `mcounteren.HPM16` and `hcounteren.HPM16` are set,\nthe `hpmcounter16` CSR (an alias of `mhpmcounter16`) is accessible to VS-mode.\n\n type: if (HCOUNTENABLE_EN[16]) { reset: if (HCOUNTENABLE_EN[16]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_394ffd49", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/hcounteren.yaml", + "section": "hcounteren.HPM17", + "text": "CSR hcounteren field HPM17 (bits=17) When all of `scounteren.HPM17`, `mcounteren.HPM17`, and `hcounteren.HPM17` are set,\nthe `hpmcounter17` CSR (an alias of `mhpmcounter17`) is accessible to VU-mode.\n\nWhen `mcounteren.HPM17` and `hcounteren.HPM17` are set,\nthe `hpmcounter17` CSR (an alias of `mhpmcounter17`) is accessible to VS-mode.\n\n type: if (HCOUNTENABLE_EN[17]) { reset: if (HCOUNTENABLE_EN[17]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_b3b28f41", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/hcounteren.yaml", + "section": "hcounteren.HPM18", + "text": "CSR hcounteren field HPM18 (bits=18) When all of `scounteren.HPM18`, `mcounteren.HPM18`, and `hcounteren.HPM18` are set,\nthe `hpmcounter18` CSR (an alias of `mhpmcounter18`) is accessible to VU-mode.\n\nWhen `mcounteren.HPM18` and `hcounteren.HPM18` are set,\nthe `hpmcounter18` CSR (an alias of `mhpmcounter18`) is accessible to VS-mode.\n\n type: if (HCOUNTENABLE_EN[18]) { reset: if (HCOUNTENABLE_EN[18]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_0f147a24", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/hcounteren.yaml", + "section": "hcounteren.HPM19", + "text": "CSR hcounteren field HPM19 (bits=19) When all of `scounteren.HPM19`, `mcounteren.HPM19`, and `hcounteren.HPM19` are set,\nthe `hpmcounter19` CSR (an alias of `mhpmcounter19`) is accessible to VU-mode.\n\nWhen `mcounteren.HPM19` and `hcounteren.HPM19` are set,\nthe `hpmcounter19` CSR (an alias of `mhpmcounter19`) is accessible to VS-mode.\n\n type: if (HCOUNTENABLE_EN[19]) { reset: if (HCOUNTENABLE_EN[19]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_e158afa8", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/hcounteren.yaml", + "section": "hcounteren.HPM20", + "text": "CSR hcounteren field HPM20 (bits=20) When all of `scounteren.HPM20`, `mcounteren.HPM20`, and `hcounteren.HPM20` are set,\nthe `hpmcounter20` CSR (an alias of `mhpmcounter20`) is accessible to VU-mode.\n\nWhen `mcounteren.HPM20` and `hcounteren.HPM20` are set,\nthe `hpmcounter20` CSR (an alias of `mhpmcounter20`) is accessible to VS-mode.\n\n type: if (HCOUNTENABLE_EN[20]) { reset: if (HCOUNTENABLE_EN[20]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_5b2022d6", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/hcounteren.yaml", + "section": "hcounteren.HPM21", + "text": "CSR hcounteren field HPM21 (bits=21) When all of `scounteren.HPM21`, `mcounteren.HPM21`, and `hcounteren.HPM21` are set,\nthe `hpmcounter21` CSR (an alias of `mhpmcounter21`) is accessible to VU-mode.\n\nWhen `mcounteren.HPM21` and `hcounteren.HPM21` are set,\nthe `hpmcounter21` CSR (an alias of `mhpmcounter21`) is accessible to VS-mode.\n\n type: if (HCOUNTENABLE_EN[21]) { reset: if (HCOUNTENABLE_EN[21]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_7c2bd177", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/hcounteren.yaml", + "section": "hcounteren.HPM22", + "text": "CSR hcounteren field HPM22 (bits=22) When all of `scounteren.HPM22`, `mcounteren.HPM22`, and `hcounteren.HPM22` are set,\nthe `hpmcounter22` CSR (an alias of `mhpmcounter22`) is accessible to VU-mode.\n\nWhen `mcounteren.HPM22` and `hcounteren.HPM22` are set,\nthe `hpmcounter22` CSR (an alias of `mhpmcounter22`) is accessible to VS-mode.\n\n type: if (HCOUNTENABLE_EN[22]) { reset: if (HCOUNTENABLE_EN[22]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_5956bf5d", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/hcounteren.yaml", + "section": "hcounteren.HPM23", + "text": "CSR hcounteren field HPM23 (bits=23) When all of `scounteren.HPM23`, `mcounteren.HPM23`, and `hcounteren.HPM23` are set,\nthe `hpmcounter23` CSR (an alias of `mhpmcounter23`) is accessible to VU-mode.\n\nWhen `mcounteren.HPM23` and `hcounteren.HPM23` are set,\nthe `hpmcounter23` CSR (an alias of `mhpmcounter23`) is accessible to VS-mode.\n\n type: if (HCOUNTENABLE_EN[23]) { reset: if (HCOUNTENABLE_EN[23]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_6667e0ad", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/hcounteren.yaml", + "section": "hcounteren.HPM24", + "text": "CSR hcounteren field HPM24 (bits=24) When all of `scounteren.HPM24`, `mcounteren.HPM24`, and `hcounteren.HPM24` are set,\nthe `hpmcounter24` CSR (an alias of `mhpmcounter24`) is accessible to VU-mode.\n\nWhen `mcounteren.HPM24` and `hcounteren.HPM24` are set,\nthe `hpmcounter24` CSR (an alias of `mhpmcounter24`) is accessible to VS-mode.\n\n type: if (HCOUNTENABLE_EN[24]) { reset: if (HCOUNTENABLE_EN[24]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_729e8177", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/hcounteren.yaml", + "section": "hcounteren.HPM25", + "text": "CSR hcounteren field HPM25 (bits=25) When all of `scounteren.HPM25`, `mcounteren.HPM25`, and `hcounteren.HPM25` are set,\nthe `hpmcounter25` CSR (an alias of `mhpmcounter25`) is accessible to VU-mode.\n\nWhen `mcounteren.HPM25` and `hcounteren.HPM25` are set,\nthe `hpmcounter25` CSR (an alias of `mhpmcounter25`) is accessible to VS-mode.\n\n type: if (HCOUNTENABLE_EN[25]) { reset: if (HCOUNTENABLE_EN[25]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_f63c0de8", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/hcounteren.yaml", + "section": "hcounteren.HPM26", + "text": "CSR hcounteren field HPM26 (bits=26) When all of `scounteren.HPM26`, `mcounteren.HPM26`, and `hcounteren.HPM26` are set,\nthe `hpmcounter26` CSR (an alias of `mhpmcounter26`) is accessible to VU-mode.\n\nWhen `mcounteren.HPM26` and `hcounteren.HPM26` are set,\nthe `hpmcounter26` CSR (an alias of `mhpmcounter26`) is accessible to VS-mode.\n\n type: if (HCOUNTENABLE_EN[26]) { reset: if (HCOUNTENABLE_EN[26]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_5eb42e3c", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/hcounteren.yaml", + "section": "hcounteren.HPM27", + "text": "CSR hcounteren field HPM27 (bits=27) When all of `scounteren.HPM27`, `mcounteren.HPM27`, and `hcounteren.HPM27` are set,\nthe `hpmcounter27` CSR (an alias of `mhpmcounter27`) is accessible to VU-mode.\n\nWhen `mcounteren.HPM27` and `hcounteren.HPM27` are set,\nthe `hpmcounter27` CSR (an alias of `mhpmcounter27`) is accessible to VS-mode.\n\n type: if (HCOUNTENABLE_EN[27]) { reset: if (HCOUNTENABLE_EN[27]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_cac8ad1a", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/hcounteren.yaml", + "section": "hcounteren.HPM28", + "text": "CSR hcounteren field HPM28 (bits=28) When all of `scounteren.HPM28`, `mcounteren.HPM28`, and `hcounteren.HPM28` are set,\nthe `hpmcounter28` CSR (an alias of `mhpmcounter28`) is accessible to VU-mode.\n\nWhen `mcounteren.HPM28` and `hcounteren.HPM28` are set,\nthe `hpmcounter28` CSR (an alias of `mhpmcounter28`) is accessible to VS-mode.\n\n type: if (HCOUNTENABLE_EN[28]) { reset: if (HCOUNTENABLE_EN[28]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_954fb67a", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/hcounteren.yaml", + "section": "hcounteren.HPM29", + "text": "CSR hcounteren field HPM29 (bits=29) When all of `scounteren.HPM29`, `mcounteren.HPM29`, and `hcounteren.HPM29` are set,\nthe `hpmcounter29` CSR (an alias of `mhpmcounter29`) is accessible to VU-mode.\n\nWhen `mcounteren.HPM29` and `hcounteren.HPM29` are set,\nthe `hpmcounter29` CSR (an alias of `mhpmcounter29`) is accessible to VS-mode.\n\n type: if (HCOUNTENABLE_EN[29]) { reset: if (HCOUNTENABLE_EN[29]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_043e53cf", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/hcounteren.yaml", + "section": "hcounteren.HPM30", + "text": "CSR hcounteren field HPM30 (bits=30) When all of `scounteren.HPM30`, `mcounteren.HPM30`, and `hcounteren.HPM30` are set,\nthe `hpmcounter30` CSR (an alias of `mhpmcounter30`) is accessible to VU-mode.\n\nWhen `mcounteren.HPM30` and `hcounteren.HPM30` are set,\nthe `hpmcounter30` CSR (an alias of `mhpmcounter30`) is accessible to VS-mode.\n\n type: if (HCOUNTENABLE_EN[30]) { reset: if (HCOUNTENABLE_EN[30]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_2b373c4c", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/hcounteren.yaml", + "section": "hcounteren.HPM31", + "text": "CSR hcounteren field HPM31 (bits=31) When all of `scounteren.HPM31`, `mcounteren.HPM31`, and `hcounteren.HPM31` are set,\nthe `hpmcounter31` CSR (an alias of `mhpmcounter31`) is accessible to VU-mode.\n\nWhen `mcounteren.HPM31` and `hcounteren.HPM31` are set,\nthe `hpmcounter31` CSR (an alias of `mhpmcounter31`) is accessible to VS-mode.\n\n type: if (HCOUNTENABLE_EN[31]) { reset: if (HCOUNTENABLE_EN[31]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_122eb70e", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/henvcfg.yaml", + "section": "henvcfg", + "text": "CSR henvcfg (address=1546, priv=S): The henvcfg CSR is a 64-bit read/write register that controls certain characteristics of the\nexecution environment when virtualization mode V=1.\n\nIf bit `henvcfg.FIOM` (Fence of I/O implies Memory) is set to one in henvcfg, `fence`\ninstructions executed when V=1 are modified so the requirement to or", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_fb184338", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/henvcfg.yaml", + "section": "henvcfg.STCE", + "text": "CSR henvcfg field STCE (bits=63) *STimecmp Enable*\n\nWhen set, `stimecmp` is operational in VS-mode if `menvcfg.STCE` is also set.\n\nWhen `menvcfg.STCE` is zero:\n * `henvcfg.STCE` reads-as-zero\n * `vstimecmp` access raises an `IllegalInstruction` exception.\n * `hip.VSTIP` reverts to its defined behavior as if Sstc is not implemented. type: return (implemented?(ExtensionName::Sstc)) ? CsrFieldType::RO : CsrFieldType::RW; reset: return (implemented?(ExtensionName::Sstc)) ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_2c12f58f", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/henvcfg.yaml", + "section": "henvcfg.PBMTE", + "text": "CSR henvcfg field PBMTE (bits=62) *Page Based Memory Type Enable*\n\nThe PBMTE bit controls whether the `Svpbmt` extension is available for use in VS-stage\naddress translation.\n\nWhen PBMTE=1, Svpbmt is available for VS-stage address translation.\n\nWhen PBMTE=0, the implementation behaves as though `Svpbmt` were not implemented for\nVS-s type: return (implemented?(ExtensionName::Svpbmt)) ? CsrFieldType::RO : CsrFieldType::RW; reset: return (implemented?(ExtensionName::Svpbmt)) ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_160e0b81", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/henvcfg.yaml", + "section": "henvcfg.ADUE", + "text": "CSR henvcfg field ADUE (bits=61) If the `Svadu` extension is implemented, the ADUE bit controls whether hardware updating of\nPTE A/D bits is enabled for VS-stage address translation.\n\nWhen ADUE=1, hardware updating of PTE A/D bits is enabled during VS-stage address\ntranslation, and the implementation behaves as though the Svade ext type: return (implemented?(ExtensionName::Svadu)) ? CsrFieldType::RW : CsrFieldType::RO; reset: return (implemented?(ExtensionName::Svadu)) ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_e38965eb", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/henvcfg.yaml", + "section": "henvcfg.CBZE", + "text": "CSR henvcfg field CBZE (bits=7) *Cache Block Zero instruction Enable*\n\nEnables the execution of the cache block zero instruction, `CBO.ZERO`,\n<% if ext?(:S) %>\nin S-mode\n<% elsif ext?(:U) %>\nin U-mode\n<% end %>.\n\n * `0`: The instruction raises an illegal instruction or virtual instruction exception\n * `1`: The instruction is exe type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_f0b5ac7a", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/henvcfg.yaml", + "section": "henvcfg.CBCFE", + "text": "CSR henvcfg field CBCFE (bits=6) *Cache Block Clean and Flush instruction Enable*\n\nEnables the execution of the cache block clean instruction, `CBO.CLEAN`, and the\ncache block flush instruction, `CBO.FLUSH`,\n<% if ext?(:S) %>\nin S-mode\n<% elsif ext?(:U) %>\nin U-mode\n<% end %>.\n\n * `0`: The instruction raises an illegal instruction type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_6a137885", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/henvcfg.yaml", + "section": "henvcfg.CBIE", + "text": "CSR henvcfg field CBIE (bits=5-4) *Cache Block Invalidate instruction Enable*\n\nEnables the execution of the cache block invalidate instruction, `CBO.INVAL`,\n<% if ext?(:S) %>\nin S-mode\n<% elsif ext?(:U) %>\nin U-mode\n<% end %>.\n\n * `00`: The instruction raises an illegal instruction or virtual instruction exception\n * `01`: The ins type: RW-R reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_7da16434", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/henvcfg.yaml", + "section": "henvcfg.SSE", + "text": "CSR henvcfg field SSE (bits=3) *Shadow Stack Enable*\n\nIf the SSE field is set to 1, the Zicfiss extension is activated in VS-mode. When the SSE\nfield is 0, the Zicfiss extension remains inactive in VS-mode, and the following rules apply\nwhen V=1 :\n\n - 32-bit Zicfiss instructions will revert to their behavior as defined by Zimop. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_17d013c5", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/henvcfg.yaml", + "section": "henvcfg.FIOM", + "text": "CSR henvcfg field FIOM (bits=rv32=? rv64=?) *Fence of I/O implies Memory*\n\nWhen `menvcfg.FIOM` is set,\nFENCE instructions ordering I/O regions also implicitly order memory regions when executed\nin any mode less privileged than M-mode.\n\n[separator=\"!\",%autowidth,float=\"center\",align=\"center\",cols=\"^,<\",options=\"header\"]\n!===\n!Instruction bit ! type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_fe577802", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/henvcfgh.yaml", + "section": "henvcfgh", + "text": "CSR henvcfgh (address=1562, priv=S): The henvcfgh CSR is a 32-bit read/write register for the most-significant 32 bits of `henvcfg`.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_f67902ef", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/henvcfgh.yaml", + "section": "henvcfgh.STCE", + "text": "CSR henvcfgh field STCE (bits=31) *STimecmp Enable*\n\nWhen set, `stimecmp` is operational in VS-mode if `menvcfg.STCE` is also set.\n\nWhen `menvcfg.STCE` is zero:\n * `henvcfg.STCE` reads-as-zero\n * `vstimecmp` access raises an `IllegalInstruction` exception.\n * `hip.VSTIP` reverts to its defined behavior as if Sstc is not implemented. type: return (implemented?(ExtensionName::Sstc)) ? CsrFieldType::RO : CsrFieldType::RW; reset: return (implemented?(ExtensionName::Sstc)) ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_94bb5467", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/henvcfgh.yaml", + "section": "henvcfgh.PBMTE", + "text": "CSR henvcfgh field PBMTE (bits=30) *Page Based Memory Type Enable*\n\nThe PBMTE bit controls whether the `Svpbmt` extension is available for use in VS-stage\naddress translation.\n\nWhen PBMTE=1, Svpbmt is available for VS-stage address translation.\n\nWhen PBMTE=0, the implementation behaves as though `Svpbmt` were not implemented for\nVS-s type: return (implemented?(ExtensionName::Svpbmt)) ? CsrFieldType::RO : CsrFieldType::RW; reset: return (implemented?(ExtensionName::Svpbmt)) ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ead1797b", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/henvcfgh.yaml", + "section": "henvcfgh.ADUE", + "text": "CSR henvcfgh field ADUE (bits=29) If the `Svadu` extension is implemented, the ADUE bit controls whether hardware updating of\nPTE A/D bits is enabled for VS-stage address translation.\n\nWhen ADUE=1, hardware updating of PTE A/D bits is enabled during VS-stage address\ntranslation, and the implementation behaves as though the Svade ext type: return (implemented?(ExtensionName::Svadu)) ? CsrFieldType::RW : CsrFieldType::RO; reset: return (implemented?(ExtensionName::Svadu)) ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_e139eb09", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/hgatp.yaml", + "section": "hgatp", + "text": "CSR hgatp (address=1664, priv=S): The hgatp register is an HSXLEN-bit read/write register\nwhich controls G-stage address translation and protection, the second stage of two-stage\ntranslation for guest virtual addresses.\nSimilar to CSR `satp`, this register holds the physical page number (PPN) of the\nguest-physical root page table;\na", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "H" + }, + { + "chunk_id": "chunk_06088d66", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/hgatp.yaml", + "section": "hgatp.MODE", + "text": "CSR hgatp field MODE (bits=rv32=31 rv64=63-60) When MODE=Bare, guest physical addresses are equal to supervisor physical addresses,\nand there is no further memory protection for a guest virtual machine beyond the\nphysical memory protection scheme.\nIn this case, the remaining fields in hgatp must be set to zeros.\n\nWhen HSXLEN=32, the only other v type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_160b1c11", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/hgatp.yaml", + "section": "hgatp.VMID", + "text": "CSR hgatp field VMID (bits=rv32=28-22 rv64=57-44) Virtual machine ID.\n\nThe number of VMID bits is determined by parameter VMID_WIDTH.\nVMID_WIDTH may be determined by software by writing one to every bit position in\nthe VMID field, then reading back the value in hgatp to see which bit\npositions in the VMID field hold a one.\nThe least-significant bit type: if (VMID_WIDTH == 0) { reset: if (VMID_WIDTH == 0) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ef47ea57", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/hgatp.yaml", + "section": "hgatp.PPN", + "text": "CSR hgatp field PPN (bits=rv32=21-0 rv64=43-0) The physical page number (PPN) of the guest-physical root page table. type: if (!SV32X4_TRANSLATION && !SV39X4_TRANSLATION && !SV48X4_TRANSLATION && !SV57X4_TRANSLATION) { reset: if (!SV32X4_TRANSLATION && !SV39X4_TRANSLATION && !SV48X4_TRANSLATION && !SV57X4", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_0970157e", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/htimedelta.yaml", + "section": "htimedelta", + "text": "CSR htimedelta (address=1541, priv=S): The `htimedelta` CSR is a 64-bit read/write register that contains the delta\nbetween the value of the `time` CSR and the value returned in VS-mode or VU-mode.\nThat is, reading the `time` CSR in VS or VU mode returns the sum of the contents\nof `htimedelta` and the actual value of `time`.\n\n[NOTE]\nBeca", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "H" + }, + { + "chunk_id": "chunk_990cbb25", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/htimedelta.yaml", + "section": "htimedelta.DELTA", + "text": "CSR htimedelta field DELTA (bits=63-0) Signed delta type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_6ea224fe", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/htimedeltah.yaml", + "section": "htimedeltah", + "text": "CSR htimedeltah (address=1557, priv=S): Upper half of the `htimedelta` CSR.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_47c1cb0b", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/htimedeltah.yaml", + "section": "htimedeltah.DELTA", + "text": "CSR htimedeltah field DELTA (bits=31-0) Signed delta type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_bd3b0531", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/htinst.yaml", + "section": "htinst", + "text": "CSR htinst (address=1610, priv=S): When a trap is taken into HS-mode, mtinst is written with a value that, if nonzero,\nprovides information about the instruction that trapped, to assist software in handling the trap.\nThe values that may be written to mtinst on a trap are documented in TODO.\n\nhtinst is a WARL register that need only b", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "H" + }, + { + "chunk_id": "chunk_78561cf0", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/htinst.yaml", + "section": "htinst.VALUE", + "text": "CSR htinst field VALUE (bits=rv32=31-0 rv64=63-0) Exception-specific information for a trap into HS-mode. type: if ( (TINST_VALUE_ON_FINAL_LOAD_GUEST_PAGE_FAULT != \"always zero\") reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ae44177f", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/htval.yaml", + "section": "htval", + "text": "CSR htval (address=1603, priv=M): When a trap is taken into HS-mode, htval is written with additional exception-specific information, alongside stval, to assist software in handling the trap.\n\nWhen a guest-page-fault trap is taken into HS-mode, htval is written with either zero or the guest physical address that faulted, shifted rig", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "H" + }, + { + "chunk_id": "chunk_8426442b", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/htval.yaml", + "section": "htval.VALUE", + "text": "CSR htval field VALUE (bits=rv32=31-0 rv64=63-0) Exception-specific information for a trap into M-mode. type: if (REPORT_GPA_IN_TVAL_ON_LOAD_GUEST_PAGE_FAULT reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_f14aea28", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/mtinst.yaml", + "section": "mtinst", + "text": "CSR mtinst (address=842, priv=M): When a trap is taken into M-mode, mtinst is written with a value that, if nonzero,\nprovides information about the instruction that trapped, to assist software in handling the trap.\nThe values that may be written to mtinst on a trap are documented in TODO.\n\nmtinst is a WARL register that need only be", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "H" + }, + { + "chunk_id": "chunk_5f1cc800", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/mtinst.yaml", + "section": "mtinst.VALUE", + "text": "CSR mtinst field VALUE (bits=rv32=31-0 rv64=63-0) Exception-specific information for a trap into M-mode. type: if ( (TINST_VALUE_ON_FINAL_LOAD_GUEST_PAGE_FAULT != \"always zero\") reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_54382b1e", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/mtval2.yaml", + "section": "mtval2", + "text": "CSR mtval2 (address=843, priv=M): When a trap is taken into M-mode from a virtual mode, mtval2 is written with additional exception-specific information,\nalongside mtval, to assist software in handling the trap.\n\nWhen a guest-page-fault trap is taken into M-mode, mtval2 is written with either zero or the guest physical address that ", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "H" + }, + { + "chunk_id": "chunk_cecbda23", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/mtval2.yaml", + "section": "mtval2.VALUE", + "text": "CSR mtval2 field VALUE (bits=rv32=31-0 rv64=63-0) Exception-specific information for a trap into M-mode. type: if (REPORT_GPA_IN_TVAL_ON_LOAD_GUEST_PAGE_FAULT reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_5948ceeb", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/vsatp.yaml", + "section": "vsatp", + "text": "CSR vsatp (address=640, priv=VS): The `vsatp` register is a VSXLEN-bit read/write register that is VS-mode's version of supervisor\nregister `satp`.\nWhen V=1, `vsatp` substitutes for the usual `satp`, so instructions that normally read or modify\n`satp` actually access `vsatp` instead.\n`vsatp` controls VS-stage address translation, th", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "H" + }, + { + "chunk_id": "chunk_93becdad", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/vsatp.yaml", + "section": "vsatp.MODE", + "text": "CSR vsatp field MODE (bits=rv32=31 rv64=63-60) *Translation Mode*\n\nControls the current translation mode in VS-mode according to the table below.\n\n[separator=\"!\",%autowidth]\n!===\n! Value ! Name ! Description\n\n! 0 ! Bare a! No translation -> virtual address == physical address\n<%- if ext?(:Sv39) -%>\n! 8 ! Sv39 ! 39-bit virtual address translation type: RW-R reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_c5caae07", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/vsatp.yaml", + "section": "vsatp.ASID", + "text": "CSR vsatp field ASID (bits=rv32=30-22 rv64=59-44) *Address Space ID* type: RW-R reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_08fc45b4", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/H/vsatp.yaml", + "section": "vsatp.PPN", + "text": "CSR vsatp field PPN (bits=rv32=21-0 rv64=43-0) *Physical Page Number*\n\nThe physical address of the active root page table is PPN << 12.\n\nCan only hold values that correspond to a valid page table base, which\nwill be implementation-dependent. type: RW-R reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_6b4bfa92", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/mcounteren.yaml", + "section": "mcounteren", + "text": "CSR mcounteren (address=774, priv=M): The counter-enable `mcounteren` register is a 32-bit register that controls the availability\nof the hardware performance-monitoring counters to\n<%- if ext?(:S) -%>\nS-mode\n<%- elsif ext?(:U) -%>\nU-mode\n<%- else -%>\nthe next-lower privileged mode\n<%- end -%>\n.\n\nThe settings in this register only contr", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "U" + }, + { + "chunk_id": "chunk_00397484", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/mcounteren.yaml", + "section": "mcounteren.CY", + "text": "CSR mcounteren field CY (bits=rv32=? rv64=?) When set, the `cycle` CSR (an alias of `mcycle`) is accessible to\n<%- if ext?(:S) -%>\nS-mode.\n<%- else -%>\nU-mode.\n<%- end -%>\n\n<%- if ext?(:S) -%>\nWhen `scounteren.CY` is also set, `cycle` is further accessible to U-mode.\n<%- end -%>\n\n<%- if ext?(:H) -%>\nWhen `hcounteren.CY` is also set, `cycle` is type: if (MCOUNTENABLE_EN[0]) { reset: if (MCOUNTENABLE_EN[0]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_2c7465d4", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/mcounteren.yaml", + "section": "mcounteren.TM", + "text": "CSR mcounteren field TM (bits=1) Placeholder for delegating `time` to less-privileged modes; however, since `time`\nis memory-mapped rather than a CSR, this field is always read-only zero. type: RO", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_584cad2f", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/mcounteren.yaml", + "section": "mcounteren.IR", + "text": "CSR mcounteren field IR (bits=2) When set, the `instret` CSR (an alias of `minstret`) is accessible to\n<%- if ext?(:S) -%>\nS-mode.\n<%- else -%>\nU-mode.\n<%- end -%>\n\n<%- if ext?(:S) -%>\nWhen `scounteren.IR` is also set, `instret` is further accessible to U-mode.\n<%- end -%>\n\n<%- if ext?(:H) -%>\nWhen `hcounteren.IR` is also set, `ins type: if (MCOUNTENABLE_EN[2]) { reset: if (MCOUNTENABLE_EN[2]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_658091f6", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/mcounteren.yaml", + "section": "mcounteren.HPM3", + "text": "CSR mcounteren field HPM3 (bits=3) When set, the `hpmcounter3` CSR (an alias of `mhpmcounter3`) is accessible to\n<%- if ext?(:S) -%>\nS-mode.\n<%- else -%>\nU-mode.\n<%- end -%>\n\n<%- if ext?(:S) -%>\nWhen `scounteren.HPM3` is also set, `hpmcounter3` is further accessible to U-mode.\n<%- end -%>\n\n<%- if ext?(:H) -%>\nWhen `hcounteren.HPM3` i type: if (MCOUNTENABLE_EN[3]) { reset: if (MCOUNTENABLE_EN[3]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_9f010140", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/mcounteren.yaml", + "section": "mcounteren.HPM4", + "text": "CSR mcounteren field HPM4 (bits=4) When set, the `hpmcounter4` CSR (an alias of `mhpmcounter4`) is accessible to\n<%- if ext?(:S) -%>\nS-mode.\n<%- else -%>\nU-mode.\n<%- end -%>\n\n<%- if ext?(:S) -%>\nWhen `scounteren.HPM4` is also set, `hpmcounter4` is further accessible to U-mode.\n<%- end -%>\n\n<%- if ext?(:H) -%>\nWhen `hcounteren.HPM4` i type: if (MCOUNTENABLE_EN[4]) { reset: if (MCOUNTENABLE_EN[4]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ab20959a", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/mcounteren.yaml", + "section": "mcounteren.HPM5", + "text": "CSR mcounteren field HPM5 (bits=5) When set, the `hpmcounter5` CSR (an alias of `mhpmcounter5`) is accessible to\n<%- if ext?(:S) -%>\nS-mode.\n<%- else -%>\nU-mode.\n<%- end -%>\n\n<%- if ext?(:S) -%>\nWhen `scounteren.HPM5` is also set, `hpmcounter5` is further accessible to U-mode.\n<%- end -%>\n\n<%- if ext?(:H) -%>\nWhen `hcounteren.HPM5` i type: if (MCOUNTENABLE_EN[5]) { reset: if (MCOUNTENABLE_EN[5]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_2867555c", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/mcounteren.yaml", + "section": "mcounteren.HPM6", + "text": "CSR mcounteren field HPM6 (bits=6) When set, the `hpmcounter6` CSR (an alias of `mhpmcounter6`) is accessible to\n<%- if ext?(:S) -%>\nS-mode.\n<%- else -%>\nU-mode.\n<%- end -%>\n\n<%- if ext?(:S) -%>\nWhen `scounteren.HPM6` is also set, `hpmcounter6` is further accessible to U-mode.\n<%- end -%>\n\n<%- if ext?(:H) -%>\nWhen `hcounteren.HPM6` i type: if (MCOUNTENABLE_EN[6]) { reset: if (MCOUNTENABLE_EN[6]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_9107a4fe", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/mcounteren.yaml", + "section": "mcounteren.HPM7", + "text": "CSR mcounteren field HPM7 (bits=7) When set, the `hpmcounter7` CSR (an alias of `mhpmcounter7`) is accessible to\n<%- if ext?(:S) -%>\nS-mode.\n<%- else -%>\nU-mode.\n<%- end -%>\n\n<%- if ext?(:S) -%>\nWhen `scounteren.HPM7` is also set, `hpmcounter7` is further accessible to U-mode.\n<%- end -%>\n\n<%- if ext?(:H) -%>\nWhen `hcounteren.HPM7` i type: if (MCOUNTENABLE_EN[7]) { reset: if (MCOUNTENABLE_EN[7]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_7587f528", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/mcounteren.yaml", + "section": "mcounteren.HPM8", + "text": "CSR mcounteren field HPM8 (bits=8) When set, the `hpmcounter8` CSR (an alias of `mhpmcounter8`) is accessible to\n<%- if ext?(:S) -%>\nS-mode.\n<%- else -%>\nU-mode.\n<%- end -%>\n\n<%- if ext?(:S) -%>\nWhen `scounteren.HPM8` is also set, `hpmcounter8` is further accessible to U-mode.\n<%- end -%>\n\n<%- if ext?(:H) -%>\nWhen `hcounteren.HPM8` i type: if (MCOUNTENABLE_EN[8]) { reset: if (MCOUNTENABLE_EN[8]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_f9baf771", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/mcounteren.yaml", + "section": "mcounteren.HPM9", + "text": "CSR mcounteren field HPM9 (bits=9) When set, the `hpmcounter9` CSR (an alias of `mhpmcounter9`) is accessible to\n<%- if ext?(:S) -%>\nS-mode.\n<%- else -%>\nU-mode.\n<%- end -%>\n\n<%- if ext?(:S) -%>\nWhen `scounteren.HPM9` is also set, `hpmcounter9` is further accessible to U-mode.\n<%- end -%>\n\n<%- if ext?(:H) -%>\nWhen `hcounteren.HPM9` i type: if (MCOUNTENABLE_EN[9]) { reset: if (MCOUNTENABLE_EN[9]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_10bcc106", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/mcounteren.yaml", + "section": "mcounteren.HPM10", + "text": "CSR mcounteren field HPM10 (bits=10) When set, the `hpmcounter10` CSR (an alias of `mhpmcounter10`) is accessible to\n<%- if ext?(:S) -%>\nS-mode.\n<%- else -%>\nU-mode.\n<%- end -%>\n\n<%- if ext?(:S) -%>\nWhen `scounteren.HPM10` is also set, `hpmcounter10` is further accessible to U-mode.\n<%- end -%>\n\n<%- if ext?(:H) -%>\nWhen `hcounteren.HPM type: if (MCOUNTENABLE_EN[10]) { reset: if (MCOUNTENABLE_EN[10]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_b2e8af14", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/mcounteren.yaml", + "section": "mcounteren.HPM11", + "text": "CSR mcounteren field HPM11 (bits=11) When set, the `hpmcounter11` CSR (an alias of `mhpmcounter11`) is accessible to\n<%- if ext?(:S) -%>\nS-mode.\n<%- else -%>\nU-mode.\n<%- end -%>\n\n<%- if ext?(:S) -%>\nWhen `scounteren.HPM11` is also set, `hpmcounter11` is further accessible to U-mode.\n<%- end -%>\n\n<%- if ext?(:H) -%>\nWhen `hcounteren.HPM type: if (MCOUNTENABLE_EN[11]) { reset: if (MCOUNTENABLE_EN[11]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_670ae682", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/mcounteren.yaml", + "section": "mcounteren.HPM12", + "text": "CSR mcounteren field HPM12 (bits=12) When set, the `hpmcounter12` CSR (an alias of `mhpmcounter12`) is accessible to\n<%- if ext?(:S) -%>\nS-mode.\n<%- else -%>\nU-mode.\n<%- end -%>\n\n<%- if ext?(:S) -%>\nWhen `scounteren.HPM12` is also set, `hpmcounter12` is further accessible to U-mode.\n<%- end -%>\n\n<%- if ext?(:H) -%>\nWhen `hcounteren.HPM type: if (MCOUNTENABLE_EN[12]) { reset: if (MCOUNTENABLE_EN[12]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_49331397", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/mcounteren.yaml", + "section": "mcounteren.HPM13", + "text": "CSR mcounteren field HPM13 (bits=13) When set, the `hpmcounter13` CSR (an alias of `mhpmcounter13`) is accessible to\n<%- if ext?(:S) -%>\nS-mode.\n<%- else -%>\nU-mode.\n<%- end -%>\n\n<%- if ext?(:S) -%>\nWhen `scounteren.HPM13` is also set, `hpmcounter13` is further accessible to U-mode.\n<%- end -%>\n\n<%- if ext?(:H) -%>\nWhen `hcounteren.HPM type: if (MCOUNTENABLE_EN[13]) { reset: if (MCOUNTENABLE_EN[13]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_de886841", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/mcounteren.yaml", + "section": "mcounteren.HPM14", + "text": "CSR mcounteren field HPM14 (bits=14) When set, the `hpmcounter14` CSR (an alias of `mhpmcounter14`) is accessible to\n<%- if ext?(:S) -%>\nS-mode.\n<%- else -%>\nU-mode.\n<%- end -%>\n\n<%- if ext?(:S) -%>\nWhen `scounteren.HPM14` is also set, `hpmcounter14` is further accessible to U-mode.\n<%- end -%>\n\n<%- if ext?(:H) -%>\nWhen `hcounteren.HPM type: if (MCOUNTENABLE_EN[14]) { reset: if (MCOUNTENABLE_EN[14]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_c03227fc", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/mcounteren.yaml", + "section": "mcounteren.HPM15", + "text": "CSR mcounteren field HPM15 (bits=15) When set, the `hpmcounter15` CSR (an alias of `mhpmcounter15`) is accessible to\n<%- if ext?(:S) -%>\nS-mode.\n<%- else -%>\nU-mode.\n<%- end -%>\n\n<%- if ext?(:S) -%>\nWhen `scounteren.HPM15` is also set, `hpmcounter15` is further accessible to U-mode.\n<%- end -%>\n\n<%- if ext?(:H) -%>\nWhen `hcounteren.HPM type: if (MCOUNTENABLE_EN[15]) { reset: if (MCOUNTENABLE_EN[15]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_f6f76822", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/mcounteren.yaml", + "section": "mcounteren.HPM16", + "text": "CSR mcounteren field HPM16 (bits=16) When set, the `hpmcounter16` CSR (an alias of `mhpmcounter16`) is accessible to\n<%- if ext?(:S) -%>\nS-mode.\n<%- else -%>\nU-mode.\n<%- end -%>\n\n<%- if ext?(:S) -%>\nWhen `scounteren.HPM16` is also set, `hpmcounter16` is further accessible to U-mode.\n<%- end -%>\n\n<%- if ext?(:H) -%>\nWhen `hcounteren.HPM type: if (MCOUNTENABLE_EN[16]) { reset: if (MCOUNTENABLE_EN[16]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_f1f6c806", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/mcounteren.yaml", + "section": "mcounteren.HPM17", + "text": "CSR mcounteren field HPM17 (bits=17) When set, the `hpmcounter17` CSR (an alias of `mhpmcounter17`) is accessible to\n<%- if ext?(:S) -%>\nS-mode.\n<%- else -%>\nU-mode.\n<%- end -%>\n\n<%- if ext?(:S) -%>\nWhen `scounteren.HPM17` is also set, `hpmcounter17` is further accessible to U-mode.\n<%- end -%>\n\n<%- if ext?(:H) -%>\nWhen `hcounteren.HPM type: if (MCOUNTENABLE_EN[17]) { reset: if (MCOUNTENABLE_EN[17]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ae2513b7", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/mcounteren.yaml", + "section": "mcounteren.HPM18", + "text": "CSR mcounteren field HPM18 (bits=18) When set, the `hpmcounter18` CSR (an alias of `mhpmcounter18`) is accessible to\n<%- if ext?(:S) -%>\nS-mode.\n<%- else -%>\nU-mode.\n<%- end -%>\n\n<%- if ext?(:S) -%>\nWhen `scounteren.HPM18` is also set, `hpmcounter18` is further accessible to U-mode.\n<%- end -%>\n\n<%- if ext?(:H) -%>\nWhen `hcounteren.HPM type: if (MCOUNTENABLE_EN[18]) { reset: if (MCOUNTENABLE_EN[18]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_dd5933a2", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/mcounteren.yaml", + "section": "mcounteren.HPM19", + "text": "CSR mcounteren field HPM19 (bits=19) When set, the `hpmcounter19` CSR (an alias of `mhpmcounter19`) is accessible to\n<%- if ext?(:S) -%>\nS-mode.\n<%- else -%>\nU-mode.\n<%- end -%>\n\n<%- if ext?(:S) -%>\nWhen `scounteren.HPM19` is also set, `hpmcounter19` is further accessible to U-mode.\n<%- end -%>\n\n<%- if ext?(:H) -%>\nWhen `hcounteren.HPM type: if (MCOUNTENABLE_EN[19]) { reset: if (MCOUNTENABLE_EN[19]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_887e61bd", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/mcounteren.yaml", + "section": "mcounteren.HPM20", + "text": "CSR mcounteren field HPM20 (bits=20) When set, the `hpmcounter20` CSR (an alias of `mhpmcounter20`) is accessible to\n<%- if ext?(:S) -%>\nS-mode.\n<%- else -%>\nU-mode.\n<%- end -%>\n\n<%- if ext?(:S) -%>\nWhen `scounteren.HPM20` is also set, `hpmcounter20` is further accessible to U-mode.\n<%- end -%>\n\n<%- if ext?(:H) -%>\nWhen `hcounteren.HPM type: if (MCOUNTENABLE_EN[20]) { reset: if (MCOUNTENABLE_EN[20]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_f5298d12", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/mcounteren.yaml", + "section": "mcounteren.HPM21", + "text": "CSR mcounteren field HPM21 (bits=21) When set, the `hpmcounter21` CSR (an alias of `mhpmcounter21`) is accessible to\n<%- if ext?(:S) -%>\nS-mode.\n<%- else -%>\nU-mode.\n<%- end -%>\n\n<%- if ext?(:S) -%>\nWhen `scounteren.HPM21` is also set, `hpmcounter21` is further accessible to U-mode.\n<%- end -%>\n\n<%- if ext?(:H) -%>\nWhen `hcounteren.HPM type: if (MCOUNTENABLE_EN[21]) { reset: if (MCOUNTENABLE_EN[21]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_e676adc7", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/mcounteren.yaml", + "section": "mcounteren.HPM22", + "text": "CSR mcounteren field HPM22 (bits=22) When set, the `hpmcounter22` CSR (an alias of `mhpmcounter22`) is accessible to\n<%- if ext?(:S) -%>\nS-mode.\n<%- else -%>\nU-mode.\n<%- end -%>\n\n<%- if ext?(:S) -%>\nWhen `scounteren.HPM22` is also set, `hpmcounter22` is further accessible to U-mode.\n<%- end -%>\n\n<%- if ext?(:H) -%>\nWhen `hcounteren.HPM type: if (MCOUNTENABLE_EN[22]) { reset: if (MCOUNTENABLE_EN[22]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_1bfebd46", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/mcounteren.yaml", + "section": "mcounteren.HPM23", + "text": "CSR mcounteren field HPM23 (bits=23) When set, the `hpmcounter23` CSR (an alias of `mhpmcounter23`) is accessible to\n<%- if ext?(:S) -%>\nS-mode.\n<%- else -%>\nU-mode.\n<%- end -%>\n\n<%- if ext?(:S) -%>\nWhen `scounteren.HPM23` is also set, `hpmcounter23` is further accessible to U-mode.\n<%- end -%>\n\n<%- if ext?(:H) -%>\nWhen `hcounteren.HPM type: if (MCOUNTENABLE_EN[23]) { reset: if (MCOUNTENABLE_EN[23]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_0546ed5e", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/mcounteren.yaml", + "section": "mcounteren.HPM24", + "text": "CSR mcounteren field HPM24 (bits=24) When set, the `hpmcounter24` CSR (an alias of `mhpmcounter24`) is accessible to\n<%- if ext?(:S) -%>\nS-mode.\n<%- else -%>\nU-mode.\n<%- end -%>\n\n<%- if ext?(:S) -%>\nWhen `scounteren.HPM24` is also set, `hpmcounter24` is further accessible to U-mode.\n<%- end -%>\n\n<%- if ext?(:H) -%>\nWhen `hcounteren.HPM type: if (MCOUNTENABLE_EN[24]) { reset: if (MCOUNTENABLE_EN[24]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ecfe8d27", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/mcounteren.yaml", + "section": "mcounteren.HPM25", + "text": "CSR mcounteren field HPM25 (bits=25) When set, the `hpmcounter25` CSR (an alias of `mhpmcounter25`) is accessible to\n<%- if ext?(:S) -%>\nS-mode.\n<%- else -%>\nU-mode.\n<%- end -%>\n\n<%- if ext?(:S) -%>\nWhen `scounteren.HPM25` is also set, `hpmcounter25` is further accessible to U-mode.\n<%- end -%>\n\n<%- if ext?(:H) -%>\nWhen `hcounteren.HPM type: if (MCOUNTENABLE_EN[25]) { reset: if (MCOUNTENABLE_EN[25]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_343b4726", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/mcounteren.yaml", + "section": "mcounteren.HPM26", + "text": "CSR mcounteren field HPM26 (bits=26) When set, the `hpmcounter26` CSR (an alias of `mhpmcounter26`) is accessible to\n<%- if ext?(:S) -%>\nS-mode.\n<%- else -%>\nU-mode.\n<%- end -%>\n\n<%- if ext?(:S) -%>\nWhen `scounteren.HPM26` is also set, `hpmcounter26` is further accessible to U-mode.\n<%- end -%>\n\n<%- if ext?(:H) -%>\nWhen `hcounteren.HPM type: if (MCOUNTENABLE_EN[26]) { reset: if (MCOUNTENABLE_EN[26]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ef96676a", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/mcounteren.yaml", + "section": "mcounteren.HPM27", + "text": "CSR mcounteren field HPM27 (bits=27) When set, the `hpmcounter27` CSR (an alias of `mhpmcounter27`) is accessible to\n<%- if ext?(:S) -%>\nS-mode.\n<%- else -%>\nU-mode.\n<%- end -%>\n\n<%- if ext?(:S) -%>\nWhen `scounteren.HPM27` is also set, `hpmcounter27` is further accessible to U-mode.\n<%- end -%>\n\n<%- if ext?(:H) -%>\nWhen `hcounteren.HPM type: if (MCOUNTENABLE_EN[27]) { reset: if (MCOUNTENABLE_EN[27]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_aea9494d", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/mcounteren.yaml", + "section": "mcounteren.HPM28", + "text": "CSR mcounteren field HPM28 (bits=28) When set, the `hpmcounter28` CSR (an alias of `mhpmcounter28`) is accessible to\n<%- if ext?(:S) -%>\nS-mode.\n<%- else -%>\nU-mode.\n<%- end -%>\n\n<%- if ext?(:S) -%>\nWhen `scounteren.HPM28` is also set, `hpmcounter28` is further accessible to U-mode.\n<%- end -%>\n\n<%- if ext?(:H) -%>\nWhen `hcounteren.HPM type: if (MCOUNTENABLE_EN[28]) { reset: if (MCOUNTENABLE_EN[28]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_1614ffb3", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/mcounteren.yaml", + "section": "mcounteren.HPM29", + "text": "CSR mcounteren field HPM29 (bits=29) When set, the `hpmcounter29` CSR (an alias of `mhpmcounter29`) is accessible to\n<%- if ext?(:S) -%>\nS-mode.\n<%- else -%>\nU-mode.\n<%- end -%>\n\n<%- if ext?(:S) -%>\nWhen `scounteren.HPM29` is also set, `hpmcounter29` is further accessible to U-mode.\n<%- end -%>\n\n<%- if ext?(:H) -%>\nWhen `hcounteren.HPM type: if (MCOUNTENABLE_EN[29]) { reset: if (MCOUNTENABLE_EN[29]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_00ed4b37", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/mcounteren.yaml", + "section": "mcounteren.HPM30", + "text": "CSR mcounteren field HPM30 (bits=30) When set, the `hpmcounter30` CSR (an alias of `mhpmcounter30`) is accessible to\n<%- if ext?(:S) -%>\nS-mode.\n<%- else -%>\nU-mode.\n<%- end -%>\n\n<%- if ext?(:S) -%>\nWhen `scounteren.HPM30` is also set, `hpmcounter30` is further accessible to U-mode.\n<%- end -%>\n\n<%- if ext?(:H) -%>\nWhen `hcounteren.HPM type: if (MCOUNTENABLE_EN[30]) { reset: if (MCOUNTENABLE_EN[30]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_66a842cb", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/mcounteren.yaml", + "section": "mcounteren.HPM31", + "text": "CSR mcounteren field HPM31 (bits=31) When set, the `hpmcounter31` CSR (an alias of `mhpmcounter31`) is accessible to\n<%- if ext?(:S) -%>\nS-mode.\n<%- else -%>\nU-mode.\n<%- end -%>\n\n<%- if ext?(:S) -%>\nWhen `scounteren.HPM31` is also set, `hpmcounter31` is further accessible to U-mode.\n<%- end -%>\n\n<%- if ext?(:H) -%>\nWhen `hcounteren.HPM type: if (MCOUNTENABLE_EN[31]) { reset: if (MCOUNTENABLE_EN[31]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_6bfd78e9", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr0.yaml", + "section": "pmpaddr0", + "text": "CSR pmpaddr0 (address=944, priv=M): PMP entry address", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_a55e2e77", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr0.yaml", + "section": "pmpaddr0.ADDR", + "text": "CSR pmpaddr0 field ADDR (bits=rv32=31-0 rv64=63-0) Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 0\n(or, if `pmp1cfg.A` == TOR, for PMP entry 1). type: if (NUM_PMP_ENTRIES > 0) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_192e8ea1", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr1.yaml", + "section": "pmpaddr1", + "text": "CSR pmpaddr1 (address=945, priv=M): PMP entry address", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_28b9894b", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr1.yaml", + "section": "pmpaddr1.ADDR", + "text": "CSR pmpaddr1 field ADDR (bits=rv32=31-0 rv64=63-0) Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 1\n(or, if `pmp2cfg.A` == TOR, for PMP entry 2). type: if (NUM_PMP_ENTRIES > 1) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_3e5e47db", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr10.yaml", + "section": "pmpaddr10", + "text": "CSR pmpaddr10 (address=954, priv=M): PMP entry address", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_99d4f57c", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr10.yaml", + "section": "pmpaddr10.ADDR", + "text": "CSR pmpaddr10 field ADDR (bits=rv32=31-0 rv64=63-0) Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 10\n(or, if `pmp11cfg.A` == TOR, for PMP entry 11). type: if (NUM_PMP_ENTRIES > 10) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_e7326185", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr11.yaml", + "section": "pmpaddr11", + "text": "CSR pmpaddr11 (address=955, priv=M): PMP entry address", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d4f883ae", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr11.yaml", + "section": "pmpaddr11.ADDR", + "text": "CSR pmpaddr11 field ADDR (bits=rv32=31-0 rv64=63-0) Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 11\n(or, if `pmp12cfg.A` == TOR, for PMP entry 12). type: if (NUM_PMP_ENTRIES > 11) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_21dddea2", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr12.yaml", + "section": "pmpaddr12", + "text": "CSR pmpaddr12 (address=956, priv=M): PMP entry address", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_3d9ca09a", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr12.yaml", + "section": "pmpaddr12.ADDR", + "text": "CSR pmpaddr12 field ADDR (bits=rv32=31-0 rv64=63-0) Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 12\n(or, if `pmp13cfg.A` == TOR, for PMP entry 13). type: if (NUM_PMP_ENTRIES > 12) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_acbf13ae", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr13.yaml", + "section": "pmpaddr13", + "text": "CSR pmpaddr13 (address=957, priv=M): PMP entry address", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_48af2dd3", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr13.yaml", + "section": "pmpaddr13.ADDR", + "text": "CSR pmpaddr13 field ADDR (bits=rv32=31-0 rv64=63-0) Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 13\n(or, if `pmp14cfg.A` == TOR, for PMP entry 14). type: if (NUM_PMP_ENTRIES > 13) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_c2f98e85", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr14.yaml", + "section": "pmpaddr14", + "text": "CSR pmpaddr14 (address=958, priv=M): PMP entry address", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_972f82b3", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr14.yaml", + "section": "pmpaddr14.ADDR", + "text": "CSR pmpaddr14 field ADDR (bits=rv32=31-0 rv64=63-0) Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 14\n(or, if `pmp15cfg.A` == TOR, for PMP entry 15). type: if (NUM_PMP_ENTRIES > 14) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_bf1a2604", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr15.yaml", + "section": "pmpaddr15", + "text": "CSR pmpaddr15 (address=959, priv=M): PMP entry address", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_1f891bdb", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr15.yaml", + "section": "pmpaddr15.ADDR", + "text": "CSR pmpaddr15 field ADDR (bits=rv32=31-0 rv64=63-0) Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 15\n(or, if `pmp16cfg.A` == TOR, for PMP entry 16). type: if (NUM_PMP_ENTRIES > 15) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_cdd18324", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr16.yaml", + "section": "pmpaddr16", + "text": "CSR pmpaddr16 (address=960, priv=M): PMP entry address", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ae1eb088", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr16.yaml", + "section": "pmpaddr16.ADDR", + "text": "CSR pmpaddr16 field ADDR (bits=rv32=31-0 rv64=63-0) Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 16\n(or, if `pmp17cfg.A` == TOR, for PMP entry 17). type: if (NUM_PMP_ENTRIES > 16) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ab174011", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr17.yaml", + "section": "pmpaddr17", + "text": "CSR pmpaddr17 (address=961, priv=M): PMP entry address", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_0ecbf375", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr17.yaml", + "section": "pmpaddr17.ADDR", + "text": "CSR pmpaddr17 field ADDR (bits=rv32=31-0 rv64=63-0) Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 17\n(or, if `pmp18cfg.A` == TOR, for PMP entry 18). type: if (NUM_PMP_ENTRIES > 17) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_e96b1de7", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr18.yaml", + "section": "pmpaddr18", + "text": "CSR pmpaddr18 (address=962, priv=M): PMP entry address", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_800ec466", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr18.yaml", + "section": "pmpaddr18.ADDR", + "text": "CSR pmpaddr18 field ADDR (bits=rv32=31-0 rv64=63-0) Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 18\n(or, if `pmp19cfg.A` == TOR, for PMP entry 19). type: if (NUM_PMP_ENTRIES > 18) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_a4ea62bc", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr19.yaml", + "section": "pmpaddr19", + "text": "CSR pmpaddr19 (address=963, priv=M): PMP entry address", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_295e31f5", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr19.yaml", + "section": "pmpaddr19.ADDR", + "text": "CSR pmpaddr19 field ADDR (bits=rv32=31-0 rv64=63-0) Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 19\n(or, if `pmp20cfg.A` == TOR, for PMP entry 20). type: if (NUM_PMP_ENTRIES > 19) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_fbd6a41f", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr2.yaml", + "section": "pmpaddr2", + "text": "CSR pmpaddr2 (address=946, priv=M): PMP entry address", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d640e21c", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr2.yaml", + "section": "pmpaddr2.ADDR", + "text": "CSR pmpaddr2 field ADDR (bits=rv32=31-0 rv64=63-0) Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 2\n(or, if `pmp3cfg.A` == TOR, for PMP entry 3). type: if (NUM_PMP_ENTRIES > 2) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_4e3dae02", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr20.yaml", + "section": "pmpaddr20", + "text": "CSR pmpaddr20 (address=964, priv=M): PMP entry address", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_7bd97cb0", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr20.yaml", + "section": "pmpaddr20.ADDR", + "text": "CSR pmpaddr20 field ADDR (bits=rv32=31-0 rv64=63-0) Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 20\n(or, if `pmp21cfg.A` == TOR, for PMP entry 21). type: if (NUM_PMP_ENTRIES > 20) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d3fc5e46", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr21.yaml", + "section": "pmpaddr21", + "text": "CSR pmpaddr21 (address=965, priv=M): PMP entry address", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_686e5b4e", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr21.yaml", + "section": "pmpaddr21.ADDR", + "text": "CSR pmpaddr21 field ADDR (bits=rv32=31-0 rv64=63-0) Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 21\n(or, if `pmp22cfg.A` == TOR, for PMP entry 22). type: if (NUM_PMP_ENTRIES > 21) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_fb31783e", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr22.yaml", + "section": "pmpaddr22", + "text": "CSR pmpaddr22 (address=966, priv=M): PMP entry address", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ff8df806", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr22.yaml", + "section": "pmpaddr22.ADDR", + "text": "CSR pmpaddr22 field ADDR (bits=rv32=31-0 rv64=63-0) Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 22\n(or, if `pmp23cfg.A` == TOR, for PMP entry 23). type: if (NUM_PMP_ENTRIES > 22) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_7218fc40", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr23.yaml", + "section": "pmpaddr23", + "text": "CSR pmpaddr23 (address=967, priv=M): PMP entry address", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_9738a35d", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr23.yaml", + "section": "pmpaddr23.ADDR", + "text": "CSR pmpaddr23 field ADDR (bits=rv32=31-0 rv64=63-0) Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 23\n(or, if `pmp24cfg.A` == TOR, for PMP entry 24). type: if (NUM_PMP_ENTRIES > 23) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d8054287", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr24.yaml", + "section": "pmpaddr24", + "text": "CSR pmpaddr24 (address=968, priv=M): PMP entry address", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_41dbfec5", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr24.yaml", + "section": "pmpaddr24.ADDR", + "text": "CSR pmpaddr24 field ADDR (bits=rv32=31-0 rv64=63-0) Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 24\n(or, if `pmp25cfg.A` == TOR, for PMP entry 25). type: if (NUM_PMP_ENTRIES > 24) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_178b96bd", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr25.yaml", + "section": "pmpaddr25", + "text": "CSR pmpaddr25 (address=969, priv=M): PMP entry address", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_f3d49aae", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr25.yaml", + "section": "pmpaddr25.ADDR", + "text": "CSR pmpaddr25 field ADDR (bits=rv32=31-0 rv64=63-0) Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 25\n(or, if `pmp26cfg.A` == TOR, for PMP entry 26). type: if (NUM_PMP_ENTRIES > 25) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_507e10a0", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr26.yaml", + "section": "pmpaddr26", + "text": "CSR pmpaddr26 (address=970, priv=M): PMP entry address", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_fc33a49c", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr26.yaml", + "section": "pmpaddr26.ADDR", + "text": "CSR pmpaddr26 field ADDR (bits=rv32=31-0 rv64=63-0) Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 26\n(or, if `pmp27cfg.A` == TOR, for PMP entry 27). type: if (NUM_PMP_ENTRIES > 26) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_0702fffe", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr27.yaml", + "section": "pmpaddr27", + "text": "CSR pmpaddr27 (address=971, priv=M): PMP entry address", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_caa3f379", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr27.yaml", + "section": "pmpaddr27.ADDR", + "text": "CSR pmpaddr27 field ADDR (bits=rv32=31-0 rv64=63-0) Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 27\n(or, if `pmp28cfg.A` == TOR, for PMP entry 28). type: if (NUM_PMP_ENTRIES > 27) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_2bfe1a9e", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr28.yaml", + "section": "pmpaddr28", + "text": "CSR pmpaddr28 (address=972, priv=M): PMP entry address", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_78a1f2fc", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr28.yaml", + "section": "pmpaddr28.ADDR", + "text": "CSR pmpaddr28 field ADDR (bits=rv32=31-0 rv64=63-0) Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 28\n(or, if `pmp29cfg.A` == TOR, for PMP entry 29). type: if (NUM_PMP_ENTRIES > 28) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_2e8f7a91", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr29.yaml", + "section": "pmpaddr29", + "text": "CSR pmpaddr29 (address=973, priv=M): PMP entry address", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_8958b304", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr29.yaml", + "section": "pmpaddr29.ADDR", + "text": "CSR pmpaddr29 field ADDR (bits=rv32=31-0 rv64=63-0) Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 29\n(or, if `pmp30cfg.A` == TOR, for PMP entry 30). type: if (NUM_PMP_ENTRIES > 29) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_c52c8e3b", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr3.yaml", + "section": "pmpaddr3", + "text": "CSR pmpaddr3 (address=947, priv=M): PMP entry address", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_abb9ac3e", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr3.yaml", + "section": "pmpaddr3.ADDR", + "text": "CSR pmpaddr3 field ADDR (bits=rv32=31-0 rv64=63-0) Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 3\n(or, if `pmp4cfg.A` == TOR, for PMP entry 4). type: if (NUM_PMP_ENTRIES > 3) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ceba154a", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr30.yaml", + "section": "pmpaddr30", + "text": "CSR pmpaddr30 (address=974, priv=M): PMP entry address", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_92194911", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr30.yaml", + "section": "pmpaddr30.ADDR", + "text": "CSR pmpaddr30 field ADDR (bits=rv32=31-0 rv64=63-0) Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 30\n(or, if `pmp31cfg.A` == TOR, for PMP entry 31). type: if (NUM_PMP_ENTRIES > 30) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_755bb6c8", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr31.yaml", + "section": "pmpaddr31", + "text": "CSR pmpaddr31 (address=975, priv=M): PMP entry address", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d43febf7", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr31.yaml", + "section": "pmpaddr31.ADDR", + "text": "CSR pmpaddr31 field ADDR (bits=rv32=31-0 rv64=63-0) Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 31\n(or, if `pmp32cfg.A` == TOR, for PMP entry 32). type: if (NUM_PMP_ENTRIES > 31) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_a42ba89a", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr32.yaml", + "section": "pmpaddr32", + "text": "CSR pmpaddr32 (address=976, priv=M): PMP entry address", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_a8644963", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr32.yaml", + "section": "pmpaddr32.ADDR", + "text": "CSR pmpaddr32 field ADDR (bits=rv32=31-0 rv64=63-0) Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 32\n(or, if `pmp33cfg.A` == TOR, for PMP entry 33). type: if (NUM_PMP_ENTRIES > 32) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_9e428242", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr33.yaml", + "section": "pmpaddr33", + "text": "CSR pmpaddr33 (address=977, priv=M): PMP entry address", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_2487df82", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr33.yaml", + "section": "pmpaddr33.ADDR", + "text": "CSR pmpaddr33 field ADDR (bits=rv32=31-0 rv64=63-0) Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 33\n(or, if `pmp34cfg.A` == TOR, for PMP entry 34). type: if (NUM_PMP_ENTRIES > 33) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_78126fea", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr34.yaml", + "section": "pmpaddr34", + "text": "CSR pmpaddr34 (address=978, priv=M): PMP entry address", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_4d9092b3", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr34.yaml", + "section": "pmpaddr34.ADDR", + "text": "CSR pmpaddr34 field ADDR (bits=rv32=31-0 rv64=63-0) Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 34\n(or, if `pmp35cfg.A` == TOR, for PMP entry 35). type: if (NUM_PMP_ENTRIES > 34) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ddec6eea", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr35.yaml", + "section": "pmpaddr35", + "text": "CSR pmpaddr35 (address=979, priv=M): PMP entry address", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_e848dccf", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr35.yaml", + "section": "pmpaddr35.ADDR", + "text": "CSR pmpaddr35 field ADDR (bits=rv32=31-0 rv64=63-0) Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 35\n(or, if `pmp36cfg.A` == TOR, for PMP entry 36). type: if (NUM_PMP_ENTRIES > 35) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_c7cb2c15", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr36.yaml", + "section": "pmpaddr36", + "text": "CSR pmpaddr36 (address=980, priv=M): PMP entry address", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_981491b5", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr36.yaml", + "section": "pmpaddr36.ADDR", + "text": "CSR pmpaddr36 field ADDR (bits=rv32=31-0 rv64=63-0) Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 36\n(or, if `pmp37cfg.A` == TOR, for PMP entry 37). type: if (NUM_PMP_ENTRIES > 36) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d38a978c", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr37.yaml", + "section": "pmpaddr37", + "text": "CSR pmpaddr37 (address=981, priv=M): PMP entry address", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_01cd11b7", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr37.yaml", + "section": "pmpaddr37.ADDR", + "text": "CSR pmpaddr37 field ADDR (bits=rv32=31-0 rv64=63-0) Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 37\n(or, if `pmp38cfg.A` == TOR, for PMP entry 38). type: if (NUM_PMP_ENTRIES > 37) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_e1959faa", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr38.yaml", + "section": "pmpaddr38", + "text": "CSR pmpaddr38 (address=982, priv=M): PMP entry address", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_4194e9ed", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr38.yaml", + "section": "pmpaddr38.ADDR", + "text": "CSR pmpaddr38 field ADDR (bits=rv32=31-0 rv64=63-0) Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 38\n(or, if `pmp39cfg.A` == TOR, for PMP entry 39). type: if (NUM_PMP_ENTRIES > 38) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_b5502a47", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr39.yaml", + "section": "pmpaddr39", + "text": "CSR pmpaddr39 (address=983, priv=M): PMP entry address", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_280e5f8c", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr39.yaml", + "section": "pmpaddr39.ADDR", + "text": "CSR pmpaddr39 field ADDR (bits=rv32=31-0 rv64=63-0) Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 39\n(or, if `pmp40cfg.A` == TOR, for PMP entry 40). type: if (NUM_PMP_ENTRIES > 39) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_c5c987cc", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr4.yaml", + "section": "pmpaddr4", + "text": "CSR pmpaddr4 (address=948, priv=M): PMP entry address", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_5c8d6cba", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr4.yaml", + "section": "pmpaddr4.ADDR", + "text": "CSR pmpaddr4 field ADDR (bits=rv32=31-0 rv64=63-0) Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 4\n(or, if `pmp5cfg.A` == TOR, for PMP entry 5). type: if (NUM_PMP_ENTRIES > 4) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_b82f28d9", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr40.yaml", + "section": "pmpaddr40", + "text": "CSR pmpaddr40 (address=984, priv=M): PMP entry address", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_e9185cc3", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr40.yaml", + "section": "pmpaddr40.ADDR", + "text": "CSR pmpaddr40 field ADDR (bits=rv32=31-0 rv64=63-0) Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 40\n(or, if `pmp41cfg.A` == TOR, for PMP entry 41). type: if (NUM_PMP_ENTRIES > 40) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_4d317c75", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr41.yaml", + "section": "pmpaddr41", + "text": "CSR pmpaddr41 (address=985, priv=M): PMP entry address", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_43b9ea3f", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr41.yaml", + "section": "pmpaddr41.ADDR", + "text": "CSR pmpaddr41 field ADDR (bits=rv32=31-0 rv64=63-0) Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 41\n(or, if `pmp42cfg.A` == TOR, for PMP entry 42). type: if (NUM_PMP_ENTRIES > 41) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_19588cb2", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr42.yaml", + "section": "pmpaddr42", + "text": "CSR pmpaddr42 (address=986, priv=M): PMP entry address", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_dc19c3b7", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr42.yaml", + "section": "pmpaddr42.ADDR", + "text": "CSR pmpaddr42 field ADDR (bits=rv32=31-0 rv64=63-0) Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 42\n(or, if `pmp43cfg.A` == TOR, for PMP entry 43). type: if (NUM_PMP_ENTRIES > 42) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_98e32792", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr43.yaml", + "section": "pmpaddr43", + "text": "CSR pmpaddr43 (address=987, priv=M): PMP entry address", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_c401217a", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr43.yaml", + "section": "pmpaddr43.ADDR", + "text": "CSR pmpaddr43 field ADDR (bits=rv32=31-0 rv64=63-0) Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 43\n(or, if `pmp44cfg.A` == TOR, for PMP entry 44). type: if (NUM_PMP_ENTRIES > 43) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_dff9ad17", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr44.yaml", + "section": "pmpaddr44", + "text": "CSR pmpaddr44 (address=988, priv=M): PMP entry address", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_fafbdae1", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr44.yaml", + "section": "pmpaddr44.ADDR", + "text": "CSR pmpaddr44 field ADDR (bits=rv32=31-0 rv64=63-0) Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 44\n(or, if `pmp45cfg.A` == TOR, for PMP entry 45). type: if (NUM_PMP_ENTRIES > 44) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_582b2c47", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr45.yaml", + "section": "pmpaddr45", + "text": "CSR pmpaddr45 (address=989, priv=M): PMP entry address", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ed2718fc", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr45.yaml", + "section": "pmpaddr45.ADDR", + "text": "CSR pmpaddr45 field ADDR (bits=rv32=31-0 rv64=63-0) Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 45\n(or, if `pmp46cfg.A` == TOR, for PMP entry 46). type: if (NUM_PMP_ENTRIES > 45) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_22d25560", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr46.yaml", + "section": "pmpaddr46", + "text": "CSR pmpaddr46 (address=990, priv=M): PMP entry address", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_91db839b", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr46.yaml", + "section": "pmpaddr46.ADDR", + "text": "CSR pmpaddr46 field ADDR (bits=rv32=31-0 rv64=63-0) Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 46\n(or, if `pmp47cfg.A` == TOR, for PMP entry 47). type: if (NUM_PMP_ENTRIES > 46) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_054e13f8", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr47.yaml", + "section": "pmpaddr47", + "text": "CSR pmpaddr47 (address=991, priv=M): PMP entry address", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_fbcff00c", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr47.yaml", + "section": "pmpaddr47.ADDR", + "text": "CSR pmpaddr47 field ADDR (bits=rv32=31-0 rv64=63-0) Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 47\n(or, if `pmp48cfg.A` == TOR, for PMP entry 48). type: if (NUM_PMP_ENTRIES > 47) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ec43cb8f", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr48.yaml", + "section": "pmpaddr48", + "text": "CSR pmpaddr48 (address=992, priv=M): PMP entry address", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_26c25ef0", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr48.yaml", + "section": "pmpaddr48.ADDR", + "text": "CSR pmpaddr48 field ADDR (bits=rv32=31-0 rv64=63-0) Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 48\n(or, if `pmp49cfg.A` == TOR, for PMP entry 49). type: if (NUM_PMP_ENTRIES > 48) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_697d4779", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr49.yaml", + "section": "pmpaddr49", + "text": "CSR pmpaddr49 (address=993, priv=M): PMP entry address", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_3f223c45", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr49.yaml", + "section": "pmpaddr49.ADDR", + "text": "CSR pmpaddr49 field ADDR (bits=rv32=31-0 rv64=63-0) Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 49\n(or, if `pmp50cfg.A` == TOR, for PMP entry 50). type: if (NUM_PMP_ENTRIES > 49) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_57a0ef04", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr5.yaml", + "section": "pmpaddr5", + "text": "CSR pmpaddr5 (address=949, priv=M): PMP entry address", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d321d7d1", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr5.yaml", + "section": "pmpaddr5.ADDR", + "text": "CSR pmpaddr5 field ADDR (bits=rv32=31-0 rv64=63-0) Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 5\n(or, if `pmp6cfg.A` == TOR, for PMP entry 6). type: if (NUM_PMP_ENTRIES > 5) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_90dc9691", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr50.yaml", + "section": "pmpaddr50", + "text": "CSR pmpaddr50 (address=994, priv=M): PMP entry address", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_27703a98", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr50.yaml", + "section": "pmpaddr50.ADDR", + "text": "CSR pmpaddr50 field ADDR (bits=rv32=31-0 rv64=63-0) Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 50\n(or, if `pmp51cfg.A` == TOR, for PMP entry 51). type: if (NUM_PMP_ENTRIES > 50) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_c68bf878", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr51.yaml", + "section": "pmpaddr51", + "text": "CSR pmpaddr51 (address=995, priv=M): PMP entry address", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_bc6afcc5", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr51.yaml", + "section": "pmpaddr51.ADDR", + "text": "CSR pmpaddr51 field ADDR (bits=rv32=31-0 rv64=63-0) Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 51\n(or, if `pmp52cfg.A` == TOR, for PMP entry 52). type: if (NUM_PMP_ENTRIES > 51) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_07ca9299", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr52.yaml", + "section": "pmpaddr52", + "text": "CSR pmpaddr52 (address=996, priv=M): PMP entry address", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_c7b1c709", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr52.yaml", + "section": "pmpaddr52.ADDR", + "text": "CSR pmpaddr52 field ADDR (bits=rv32=31-0 rv64=63-0) Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 52\n(or, if `pmp53cfg.A` == TOR, for PMP entry 53). type: if (NUM_PMP_ENTRIES > 52) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_f37553d5", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr53.yaml", + "section": "pmpaddr53", + "text": "CSR pmpaddr53 (address=997, priv=M): PMP entry address", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_43c68d15", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr53.yaml", + "section": "pmpaddr53.ADDR", + "text": "CSR pmpaddr53 field ADDR (bits=rv32=31-0 rv64=63-0) Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 53\n(or, if `pmp54cfg.A` == TOR, for PMP entry 54). type: if (NUM_PMP_ENTRIES > 53) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_29e26afc", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr54.yaml", + "section": "pmpaddr54", + "text": "CSR pmpaddr54 (address=998, priv=M): PMP entry address", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_5f0d7cba", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr54.yaml", + "section": "pmpaddr54.ADDR", + "text": "CSR pmpaddr54 field ADDR (bits=rv32=31-0 rv64=63-0) Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 54\n(or, if `pmp55cfg.A` == TOR, for PMP entry 55). type: if (NUM_PMP_ENTRIES > 54) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_b959810a", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr55.yaml", + "section": "pmpaddr55", + "text": "CSR pmpaddr55 (address=999, priv=M): PMP entry address", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_2bcdcf58", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr55.yaml", + "section": "pmpaddr55.ADDR", + "text": "CSR pmpaddr55 field ADDR (bits=rv32=31-0 rv64=63-0) Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 55\n(or, if `pmp56cfg.A` == TOR, for PMP entry 56). type: if (NUM_PMP_ENTRIES > 55) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_326a383f", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr56.yaml", + "section": "pmpaddr56", + "text": "CSR pmpaddr56 (address=1000, priv=M): PMP entry address", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_4fa95e4d", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr56.yaml", + "section": "pmpaddr56.ADDR", + "text": "CSR pmpaddr56 field ADDR (bits=rv32=31-0 rv64=63-0) Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 56\n(or, if `pmp57cfg.A` == TOR, for PMP entry 57). type: if (NUM_PMP_ENTRIES > 56) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_aa186519", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr57.yaml", + "section": "pmpaddr57", + "text": "CSR pmpaddr57 (address=1001, priv=M): PMP entry address", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_558f4ef3", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr57.yaml", + "section": "pmpaddr57.ADDR", + "text": "CSR pmpaddr57 field ADDR (bits=rv32=31-0 rv64=63-0) Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 57\n(or, if `pmp58cfg.A` == TOR, for PMP entry 58). type: if (NUM_PMP_ENTRIES > 57) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_65fe0a26", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr58.yaml", + "section": "pmpaddr58", + "text": "CSR pmpaddr58 (address=1002, priv=M): PMP entry address", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_fe0ce490", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr58.yaml", + "section": "pmpaddr58.ADDR", + "text": "CSR pmpaddr58 field ADDR (bits=rv32=31-0 rv64=63-0) Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 58\n(or, if `pmp59cfg.A` == TOR, for PMP entry 59). type: if (NUM_PMP_ENTRIES > 58) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_b9489e49", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr59.yaml", + "section": "pmpaddr59", + "text": "CSR pmpaddr59 (address=1003, priv=M): PMP entry address", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_10851a96", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr59.yaml", + "section": "pmpaddr59.ADDR", + "text": "CSR pmpaddr59 field ADDR (bits=rv32=31-0 rv64=63-0) Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 59\n(or, if `pmp60cfg.A` == TOR, for PMP entry 60). type: if (NUM_PMP_ENTRIES > 59) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ed2343a1", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr6.yaml", + "section": "pmpaddr6", + "text": "CSR pmpaddr6 (address=950, priv=M): PMP entry address", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_903f2551", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr6.yaml", + "section": "pmpaddr6.ADDR", + "text": "CSR pmpaddr6 field ADDR (bits=rv32=31-0 rv64=63-0) Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 6\n(or, if `pmp7cfg.A` == TOR, for PMP entry 7). type: if (NUM_PMP_ENTRIES > 6) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d443982f", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr60.yaml", + "section": "pmpaddr60", + "text": "CSR pmpaddr60 (address=1004, priv=M): PMP entry address", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_16e854e1", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr60.yaml", + "section": "pmpaddr60.ADDR", + "text": "CSR pmpaddr60 field ADDR (bits=rv32=31-0 rv64=63-0) Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 60\n(or, if `pmp61cfg.A` == TOR, for PMP entry 61). type: if (NUM_PMP_ENTRIES > 60) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d1a72c56", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr61.yaml", + "section": "pmpaddr61", + "text": "CSR pmpaddr61 (address=1005, priv=M): PMP entry address", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_11c04fd5", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr61.yaml", + "section": "pmpaddr61.ADDR", + "text": "CSR pmpaddr61 field ADDR (bits=rv32=31-0 rv64=63-0) Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 61\n(or, if `pmp62cfg.A` == TOR, for PMP entry 62). type: if (NUM_PMP_ENTRIES > 61) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_295180eb", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr62.yaml", + "section": "pmpaddr62", + "text": "CSR pmpaddr62 (address=1006, priv=M): PMP entry address", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_9e1bd4a0", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr62.yaml", + "section": "pmpaddr62.ADDR", + "text": "CSR pmpaddr62 field ADDR (bits=rv32=31-0 rv64=63-0) Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 62\n(or, if `pmp63cfg.A` == TOR, for PMP entry 63). type: if (NUM_PMP_ENTRIES > 62) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_f25bb026", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr63.yaml", + "section": "pmpaddr63", + "text": "CSR pmpaddr63 (address=1007, priv=M): PMP entry address", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_30de2f16", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr63.yaml", + "section": "pmpaddr63.ADDR", + "text": "CSR pmpaddr63 field ADDR (bits=rv32=31-0 rv64=63-0) Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 63\n(or, if `pmp64cfg.A` == TOR, for PMP entry 64). type: if (NUM_PMP_ENTRIES > 63) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_fd831146", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr7.yaml", + "section": "pmpaddr7", + "text": "CSR pmpaddr7 (address=951, priv=M): PMP entry address", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_7af2ebd2", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr7.yaml", + "section": "pmpaddr7.ADDR", + "text": "CSR pmpaddr7 field ADDR (bits=rv32=31-0 rv64=63-0) Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 7\n(or, if `pmp8cfg.A` == TOR, for PMP entry 8). type: if (NUM_PMP_ENTRIES > 7) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_b512da1e", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr8.yaml", + "section": "pmpaddr8", + "text": "CSR pmpaddr8 (address=952, priv=M): PMP entry address", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_fa3d16d7", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr8.yaml", + "section": "pmpaddr8.ADDR", + "text": "CSR pmpaddr8 field ADDR (bits=rv32=31-0 rv64=63-0) Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 8\n(or, if `pmp9cfg.A` == TOR, for PMP entry 9). type: if (NUM_PMP_ENTRIES > 8) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_38028e42", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr9.yaml", + "section": "pmpaddr9", + "text": "CSR pmpaddr9 (address=953, priv=M): PMP entry address", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_e5c0e21e", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpaddr9.yaml", + "section": "pmpaddr9.ADDR", + "text": "CSR pmpaddr9 field ADDR (bits=rv32=31-0 rv64=63-0) Bits PHYS_ADDR_WIDTH-1:2 of the address specifier for PMP entry 9\n(or, if `pmp10cfg.A` == TOR, for PMP entry 10). type: if (NUM_PMP_ENTRIES > 9) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_3bcde4ea", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg0.yaml", + "section": "pmpcfg0", + "text": "CSR pmpcfg0 (address=928, priv=M): PMP entry configuration", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_9e323892", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg0.yaml", + "section": "pmpcfg0.pmp0cfg", + "text": "CSR pmpcfg0 field pmp0cfg (bits=7-0) *PMP configuration for entry 0*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 6:5 ! _Reserved_ Writes shall be ignored.\n type: if (NUM_PMP_ENTRIES > 0) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_68af9db5", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg0.yaml", + "section": "pmpcfg0.pmp1cfg", + "text": "CSR pmpcfg0 field pmp1cfg (bits=15-8) *PMP configuration for entry 1*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 14:13 ! _Reserved_ Writes shall be ignore type: if (NUM_PMP_ENTRIES > 1) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_b16a99ab", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg0.yaml", + "section": "pmpcfg0.pmp2cfg", + "text": "CSR pmpcfg0 field pmp2cfg (bits=23-16) *PMP configuration for entry 2*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 22:21 ! _Reserved_ Writes shall be ignore type: if (NUM_PMP_ENTRIES > 2) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_f6814c67", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg0.yaml", + "section": "pmpcfg0.pmp3cfg", + "text": "CSR pmpcfg0 field pmp3cfg (bits=31-24) *PMP configuration for entry 3*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 30:29 ! _Reserved_ Writes shall be ignore type: if (NUM_PMP_ENTRIES > 3) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_c86efaf8", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg0.yaml", + "section": "pmpcfg0.pmp4cfg", + "text": "CSR pmpcfg0 field pmp4cfg (bits=39-32) *PMP configuration for entry 4*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 39 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 38:37 ! _Reserved_ Writes shall be ignore type: if (NUM_PMP_ENTRIES > 4) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_7abefc80", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg0.yaml", + "section": "pmpcfg0.pmp5cfg", + "text": "CSR pmpcfg0 field pmp5cfg (bits=47-40) *PMP configuration for entry 5*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 47 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 46:45 ! _Reserved_ Writes shall be ignore type: if (NUM_PMP_ENTRIES > 5) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_31e1f100", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg0.yaml", + "section": "pmpcfg0.pmp6cfg", + "text": "CSR pmpcfg0 field pmp6cfg (bits=55-48) *PMP configuration for entry 6*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 55 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 54:53 ! _Reserved_ Writes shall be ignore type: if (NUM_PMP_ENTRIES > 6) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_17e36631", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg0.yaml", + "section": "pmpcfg0.pmp7cfg", + "text": "CSR pmpcfg0 field pmp7cfg (bits=63-56) *PMP configuration for entry 7*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 63 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 62:61 ! _Reserved_ Writes shall be ignore type: if (NUM_PMP_ENTRIES > 7) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_108d0540", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg1.yaml", + "section": "pmpcfg1", + "text": "CSR pmpcfg1 (address=929, priv=M): PMP entry configuration", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_e29bc80a", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg1.yaml", + "section": "pmpcfg1.pmp4cfg", + "text": "CSR pmpcfg1 field pmp4cfg (bits=7-0) *PMP configuration for entry 4*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 6:5 ! _Reserved_ Writes shall be ignored.\n type: if (NUM_PMP_ENTRIES > 4) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_8dab2379", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg1.yaml", + "section": "pmpcfg1.pmp5cfg", + "text": "CSR pmpcfg1 field pmp5cfg (bits=15-8) *PMP configuration for entry 5*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 14:13 ! _Reserved_ Writes shall be ignore type: if (NUM_PMP_ENTRIES > 5) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_7b235d68", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg1.yaml", + "section": "pmpcfg1.pmp6cfg", + "text": "CSR pmpcfg1 field pmp6cfg (bits=23-16) *PMP configuration for entry 6*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 22:21 ! _Reserved_ Writes shall be ignore type: if (NUM_PMP_ENTRIES > 6) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_e952634b", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg1.yaml", + "section": "pmpcfg1.pmp7cfg", + "text": "CSR pmpcfg1 field pmp7cfg (bits=31-24) *PMP configuration for entry 7*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 30:29 ! _Reserved_ Writes shall be ignore type: if (NUM_PMP_ENTRIES > 7) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_6d11c00c", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg10.yaml", + "section": "pmpcfg10", + "text": "CSR pmpcfg10 (address=938, priv=M): PMP entry configuration", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_060b91e5", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg10.yaml", + "section": "pmpcfg10.pmp40cfg", + "text": "CSR pmpcfg10 field pmp40cfg (bits=7-0) *PMP configuration for entry 40*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 6:5 ! _Reserved_ Writes shall be ignored. type: if (NUM_PMP_ENTRIES > 40) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_638a0da0", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg10.yaml", + "section": "pmpcfg10.pmp41cfg", + "text": "CSR pmpcfg10 field pmp41cfg (bits=15-8) *PMP configuration for entry 41*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 14:13 ! _Reserved_ Writes shall be ignor type: if (NUM_PMP_ENTRIES > 41) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ca615884", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg10.yaml", + "section": "pmpcfg10.pmp42cfg", + "text": "CSR pmpcfg10 field pmp42cfg (bits=23-16) *PMP configuration for entry 42*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 22:21 ! _Reserved_ Writes shall be ignor type: if (NUM_PMP_ENTRIES > 42) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_b7507f6d", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg10.yaml", + "section": "pmpcfg10.pmp43cfg", + "text": "CSR pmpcfg10 field pmp43cfg (bits=31-24) *PMP configuration for entry 43*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 30:29 ! _Reserved_ Writes shall be ignor type: if (NUM_PMP_ENTRIES > 43) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_70a08083", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg10.yaml", + "section": "pmpcfg10.pmp44cfg", + "text": "CSR pmpcfg10 field pmp44cfg (bits=39-32) *PMP configuration for entry 44*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 39 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 38:37 ! _Reserved_ Writes shall be ignor type: if (NUM_PMP_ENTRIES > 44) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_4a4654c3", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg10.yaml", + "section": "pmpcfg10.pmp45cfg", + "text": "CSR pmpcfg10 field pmp45cfg (bits=47-40) *PMP configuration for entry 45*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 47 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 46:45 ! _Reserved_ Writes shall be ignor type: if (NUM_PMP_ENTRIES > 45) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_86842601", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg10.yaml", + "section": "pmpcfg10.pmp46cfg", + "text": "CSR pmpcfg10 field pmp46cfg (bits=55-48) *PMP configuration for entry 46*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 55 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 54:53 ! _Reserved_ Writes shall be ignor type: if (NUM_PMP_ENTRIES > 46) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_329d17d0", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg10.yaml", + "section": "pmpcfg10.pmp47cfg", + "text": "CSR pmpcfg10 field pmp47cfg (bits=63-56) *PMP configuration for entry 47*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 63 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 62:61 ! _Reserved_ Writes shall be ignor type: if (NUM_PMP_ENTRIES > 47) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_e16c7c2d", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg11.yaml", + "section": "pmpcfg11", + "text": "CSR pmpcfg11 (address=939, priv=M): PMP entry configuration", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_56c1cd50", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg11.yaml", + "section": "pmpcfg11.pmp44cfg", + "text": "CSR pmpcfg11 field pmp44cfg (bits=7-0) *PMP configuration for entry 44*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 6:5 ! _Reserved_ Writes shall be ignored. type: if (NUM_PMP_ENTRIES > 44) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_2bc12b46", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg11.yaml", + "section": "pmpcfg11.pmp45cfg", + "text": "CSR pmpcfg11 field pmp45cfg (bits=15-8) *PMP configuration for entry 45*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 14:13 ! _Reserved_ Writes shall be ignor type: if (NUM_PMP_ENTRIES > 45) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_53a2f632", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg11.yaml", + "section": "pmpcfg11.pmp46cfg", + "text": "CSR pmpcfg11 field pmp46cfg (bits=23-16) *PMP configuration for entry 46*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 22:21 ! _Reserved_ Writes shall be ignor type: if (NUM_PMP_ENTRIES > 46) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_b58e6216", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg11.yaml", + "section": "pmpcfg11.pmp47cfg", + "text": "CSR pmpcfg11 field pmp47cfg (bits=31-24) *PMP configuration for entry 47*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 30:29 ! _Reserved_ Writes shall be ignor type: if (NUM_PMP_ENTRIES > 47) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_996ed13c", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg12.yaml", + "section": "pmpcfg12", + "text": "CSR pmpcfg12 (address=940, priv=M): PMP entry configuration", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_1a74ab1b", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg12.yaml", + "section": "pmpcfg12.pmp48cfg", + "text": "CSR pmpcfg12 field pmp48cfg (bits=7-0) *PMP configuration for entry 48*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 6:5 ! _Reserved_ Writes shall be ignored. type: if (NUM_PMP_ENTRIES > 48) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_1b53a7ad", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg12.yaml", + "section": "pmpcfg12.pmp49cfg", + "text": "CSR pmpcfg12 field pmp49cfg (bits=15-8) *PMP configuration for entry 49*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 14:13 ! _Reserved_ Writes shall be ignor type: if (NUM_PMP_ENTRIES > 49) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_bd3a603f", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg12.yaml", + "section": "pmpcfg12.pmp50cfg", + "text": "CSR pmpcfg12 field pmp50cfg (bits=23-16) *PMP configuration for entry 50*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 22:21 ! _Reserved_ Writes shall be ignor type: if (NUM_PMP_ENTRIES > 50) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_62b99027", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg12.yaml", + "section": "pmpcfg12.pmp51cfg", + "text": "CSR pmpcfg12 field pmp51cfg (bits=31-24) *PMP configuration for entry 51*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 30:29 ! _Reserved_ Writes shall be ignor type: if (NUM_PMP_ENTRIES > 51) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_4d71c589", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg12.yaml", + "section": "pmpcfg12.pmp52cfg", + "text": "CSR pmpcfg12 field pmp52cfg (bits=39-32) *PMP configuration for entry 52*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 39 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 38:37 ! _Reserved_ Writes shall be ignor type: if (NUM_PMP_ENTRIES > 52) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_55ff8eed", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg12.yaml", + "section": "pmpcfg12.pmp53cfg", + "text": "CSR pmpcfg12 field pmp53cfg (bits=47-40) *PMP configuration for entry 53*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 47 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 46:45 ! _Reserved_ Writes shall be ignor type: if (NUM_PMP_ENTRIES > 53) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_718cd1a2", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg12.yaml", + "section": "pmpcfg12.pmp54cfg", + "text": "CSR pmpcfg12 field pmp54cfg (bits=55-48) *PMP configuration for entry 54*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 55 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 54:53 ! _Reserved_ Writes shall be ignor type: if (NUM_PMP_ENTRIES > 54) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_8672a065", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg12.yaml", + "section": "pmpcfg12.pmp55cfg", + "text": "CSR pmpcfg12 field pmp55cfg (bits=63-56) *PMP configuration for entry 55*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 63 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 62:61 ! _Reserved_ Writes shall be ignor type: if (NUM_PMP_ENTRIES > 55) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_5b8ee07c", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg13.yaml", + "section": "pmpcfg13", + "text": "CSR pmpcfg13 (address=941, priv=M): PMP entry configuration", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_7c104a92", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg13.yaml", + "section": "pmpcfg13.pmp52cfg", + "text": "CSR pmpcfg13 field pmp52cfg (bits=7-0) *PMP configuration for entry 52*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 6:5 ! _Reserved_ Writes shall be ignored. type: if (NUM_PMP_ENTRIES > 52) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_7d9a0c47", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg13.yaml", + "section": "pmpcfg13.pmp53cfg", + "text": "CSR pmpcfg13 field pmp53cfg (bits=15-8) *PMP configuration for entry 53*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 14:13 ! _Reserved_ Writes shall be ignor type: if (NUM_PMP_ENTRIES > 53) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_e8c0eb08", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg13.yaml", + "section": "pmpcfg13.pmp54cfg", + "text": "CSR pmpcfg13 field pmp54cfg (bits=23-16) *PMP configuration for entry 54*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 22:21 ! _Reserved_ Writes shall be ignor type: if (NUM_PMP_ENTRIES > 54) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_a94df04f", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg13.yaml", + "section": "pmpcfg13.pmp55cfg", + "text": "CSR pmpcfg13 field pmp55cfg (bits=31-24) *PMP configuration for entry 55*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 30:29 ! _Reserved_ Writes shall be ignor type: if (NUM_PMP_ENTRIES > 55) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_c5def1b6", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg14.yaml", + "section": "pmpcfg14", + "text": "CSR pmpcfg14 (address=942, priv=M): PMP entry configuration", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d1b087d0", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg14.yaml", + "section": "pmpcfg14.pmp56cfg", + "text": "CSR pmpcfg14 field pmp56cfg (bits=7-0) *PMP configuration for entry 56*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 6:5 ! _Reserved_ Writes shall be ignored. type: if (NUM_PMP_ENTRIES > 56) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_810f01dd", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg14.yaml", + "section": "pmpcfg14.pmp57cfg", + "text": "CSR pmpcfg14 field pmp57cfg (bits=15-8) *PMP configuration for entry 57*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 14:13 ! _Reserved_ Writes shall be ignor type: if (NUM_PMP_ENTRIES > 57) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_4573f46f", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg14.yaml", + "section": "pmpcfg14.pmp58cfg", + "text": "CSR pmpcfg14 field pmp58cfg (bits=23-16) *PMP configuration for entry 58*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 22:21 ! _Reserved_ Writes shall be ignor type: if (NUM_PMP_ENTRIES > 58) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_e70f9e1c", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg14.yaml", + "section": "pmpcfg14.pmp59cfg", + "text": "CSR pmpcfg14 field pmp59cfg (bits=31-24) *PMP configuration for entry 59*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 30:29 ! _Reserved_ Writes shall be ignor type: if (NUM_PMP_ENTRIES > 59) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_98075829", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg14.yaml", + "section": "pmpcfg14.pmp60cfg", + "text": "CSR pmpcfg14 field pmp60cfg (bits=39-32) *PMP configuration for entry 60*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 39 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 38:37 ! _Reserved_ Writes shall be ignor type: if (NUM_PMP_ENTRIES > 60) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_7d954d2d", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg14.yaml", + "section": "pmpcfg14.pmp61cfg", + "text": "CSR pmpcfg14 field pmp61cfg (bits=47-40) *PMP configuration for entry 61*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 47 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 46:45 ! _Reserved_ Writes shall be ignor type: if (NUM_PMP_ENTRIES > 61) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_05be68ad", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg14.yaml", + "section": "pmpcfg14.pmp62cfg", + "text": "CSR pmpcfg14 field pmp62cfg (bits=55-48) *PMP configuration for entry 62*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 55 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 54:53 ! _Reserved_ Writes shall be ignor type: if (NUM_PMP_ENTRIES > 62) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_a36f6b83", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg14.yaml", + "section": "pmpcfg14.pmp63cfg", + "text": "CSR pmpcfg14 field pmp63cfg (bits=63-56) *PMP configuration for entry 63*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 63 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 62:61 ! _Reserved_ Writes shall be ignor type: if (NUM_PMP_ENTRIES > 63) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_71ea279b", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg15.yaml", + "section": "pmpcfg15", + "text": "CSR pmpcfg15 (address=943, priv=M): PMP entry configuration", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_11e291c6", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg15.yaml", + "section": "pmpcfg15.pmp60cfg", + "text": "CSR pmpcfg15 field pmp60cfg (bits=7-0) *PMP configuration for entry 60*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 6:5 ! _Reserved_ Writes shall be ignored. type: if (NUM_PMP_ENTRIES > 60) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d4788138", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg15.yaml", + "section": "pmpcfg15.pmp61cfg", + "text": "CSR pmpcfg15 field pmp61cfg (bits=15-8) *PMP configuration for entry 61*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 14:13 ! _Reserved_ Writes shall be ignor type: if (NUM_PMP_ENTRIES > 61) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_b69c3499", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg15.yaml", + "section": "pmpcfg15.pmp62cfg", + "text": "CSR pmpcfg15 field pmp62cfg (bits=23-16) *PMP configuration for entry 62*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 22:21 ! _Reserved_ Writes shall be ignor type: if (NUM_PMP_ENTRIES > 62) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_fac3a06d", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg15.yaml", + "section": "pmpcfg15.pmp63cfg", + "text": "CSR pmpcfg15 field pmp63cfg (bits=31-24) *PMP configuration for entry 63*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 30:29 ! _Reserved_ Writes shall be ignor type: if (NUM_PMP_ENTRIES > 63) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_a5f09965", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg2.yaml", + "section": "pmpcfg2", + "text": "CSR pmpcfg2 (address=930, priv=M): PMP entry configuration", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_7b4ae72b", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg2.yaml", + "section": "pmpcfg2.pmp8cfg", + "text": "CSR pmpcfg2 field pmp8cfg (bits=7-0) *PMP configuration for entry 8*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 6:5 ! _Reserved_ Writes shall be ignored.\n type: if (NUM_PMP_ENTRIES > 8) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_13577c1d", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg2.yaml", + "section": "pmpcfg2.pmp9cfg", + "text": "CSR pmpcfg2 field pmp9cfg (bits=15-8) *PMP configuration for entry 9*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 14:13 ! _Reserved_ Writes shall be ignore type: if (NUM_PMP_ENTRIES > 9) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_05312841", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg2.yaml", + "section": "pmpcfg2.pmp10cfg", + "text": "CSR pmpcfg2 field pmp10cfg (bits=23-16) *PMP configuration for entry 10*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 22:21 ! _Reserved_ Writes shall be ignor type: if (NUM_PMP_ENTRIES > 10) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_92850703", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg2.yaml", + "section": "pmpcfg2.pmp11cfg", + "text": "CSR pmpcfg2 field pmp11cfg (bits=31-24) *PMP configuration for entry 11*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 30:29 ! _Reserved_ Writes shall be ignor type: if (NUM_PMP_ENTRIES > 11) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_bf556e3c", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg2.yaml", + "section": "pmpcfg2.pmp12cfg", + "text": "CSR pmpcfg2 field pmp12cfg (bits=39-32) *PMP configuration for entry 12*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 39 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 38:37 ! _Reserved_ Writes shall be ignor type: if (NUM_PMP_ENTRIES > 12) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_a46d50b3", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg2.yaml", + "section": "pmpcfg2.pmp13cfg", + "text": "CSR pmpcfg2 field pmp13cfg (bits=47-40) *PMP configuration for entry 13*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 47 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 46:45 ! _Reserved_ Writes shall be ignor type: if (NUM_PMP_ENTRIES > 13) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_c2d5fa3b", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg2.yaml", + "section": "pmpcfg2.pmp14cfg", + "text": "CSR pmpcfg2 field pmp14cfg (bits=55-48) *PMP configuration for entry 14*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 55 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 54:53 ! _Reserved_ Writes shall be ignor type: if (NUM_PMP_ENTRIES > 14) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d0eb1626", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg2.yaml", + "section": "pmpcfg2.pmp15cfg", + "text": "CSR pmpcfg2 field pmp15cfg (bits=63-56) *PMP configuration for entry 15*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 63 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 62:61 ! _Reserved_ Writes shall be ignor type: if (NUM_PMP_ENTRIES > 15) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_db6e7372", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg3.yaml", + "section": "pmpcfg3", + "text": "CSR pmpcfg3 (address=931, priv=M): PMP entry configuration", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_36b45f5a", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg3.yaml", + "section": "pmpcfg3.pmp12cfg", + "text": "CSR pmpcfg3 field pmp12cfg (bits=7-0) *PMP configuration for entry 12*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 6:5 ! _Reserved_ Writes shall be ignored. type: if (NUM_PMP_ENTRIES > 12) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_37b9f217", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg3.yaml", + "section": "pmpcfg3.pmp13cfg", + "text": "CSR pmpcfg3 field pmp13cfg (bits=15-8) *PMP configuration for entry 13*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 14:13 ! _Reserved_ Writes shall be ignor type: if (NUM_PMP_ENTRIES > 13) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_81b80eb0", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg3.yaml", + "section": "pmpcfg3.pmp14cfg", + "text": "CSR pmpcfg3 field pmp14cfg (bits=23-16) *PMP configuration for entry 14*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 22:21 ! _Reserved_ Writes shall be ignor type: if (NUM_PMP_ENTRIES > 14) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_06bec199", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg3.yaml", + "section": "pmpcfg3.pmp15cfg", + "text": "CSR pmpcfg3 field pmp15cfg (bits=31-24) *PMP configuration for entry 15*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 30:29 ! _Reserved_ Writes shall be ignor type: if (NUM_PMP_ENTRIES > 15) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_72ae4ce0", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg4.yaml", + "section": "pmpcfg4", + "text": "CSR pmpcfg4 (address=932, priv=M): PMP entry configuration", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_b3e1d94c", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg4.yaml", + "section": "pmpcfg4.pmp16cfg", + "text": "CSR pmpcfg4 field pmp16cfg (bits=7-0) *PMP configuration for entry 16*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 6:5 ! _Reserved_ Writes shall be ignored. type: if (NUM_PMP_ENTRIES > 16) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_413ceddd", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg4.yaml", + "section": "pmpcfg4.pmp17cfg", + "text": "CSR pmpcfg4 field pmp17cfg (bits=15-8) *PMP configuration for entry 17*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 14:13 ! _Reserved_ Writes shall be ignor type: if (NUM_PMP_ENTRIES > 17) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_c13ab077", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg4.yaml", + "section": "pmpcfg4.pmp18cfg", + "text": "CSR pmpcfg4 field pmp18cfg (bits=23-16) *PMP configuration for entry 18*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 22:21 ! _Reserved_ Writes shall be ignor type: if (NUM_PMP_ENTRIES > 18) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_579784c5", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg4.yaml", + "section": "pmpcfg4.pmp19cfg", + "text": "CSR pmpcfg4 field pmp19cfg (bits=31-24) *PMP configuration for entry 19*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 30:29 ! _Reserved_ Writes shall be ignor type: if (NUM_PMP_ENTRIES > 19) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_3bd37be0", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg4.yaml", + "section": "pmpcfg4.pmp20cfg", + "text": "CSR pmpcfg4 field pmp20cfg (bits=39-32) *PMP configuration for entry 20*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 39 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 38:37 ! _Reserved_ Writes shall be ignor type: if (NUM_PMP_ENTRIES > 20) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_2304ab61", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg4.yaml", + "section": "pmpcfg4.pmp21cfg", + "text": "CSR pmpcfg4 field pmp21cfg (bits=47-40) *PMP configuration for entry 21*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 47 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 46:45 ! _Reserved_ Writes shall be ignor type: if (NUM_PMP_ENTRIES > 21) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d4d8e59d", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg4.yaml", + "section": "pmpcfg4.pmp22cfg", + "text": "CSR pmpcfg4 field pmp22cfg (bits=55-48) *PMP configuration for entry 22*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 55 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 54:53 ! _Reserved_ Writes shall be ignor type: if (NUM_PMP_ENTRIES > 22) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_3b3b663a", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg4.yaml", + "section": "pmpcfg4.pmp23cfg", + "text": "CSR pmpcfg4 field pmp23cfg (bits=63-56) *PMP configuration for entry 23*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 63 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 62:61 ! _Reserved_ Writes shall be ignor type: if (NUM_PMP_ENTRIES > 23) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_620a5216", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg5.yaml", + "section": "pmpcfg5", + "text": "CSR pmpcfg5 (address=933, priv=M): PMP entry configuration", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_af96e078", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg5.yaml", + "section": "pmpcfg5.pmp20cfg", + "text": "CSR pmpcfg5 field pmp20cfg (bits=7-0) *PMP configuration for entry 20*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 6:5 ! _Reserved_ Writes shall be ignored. type: if (NUM_PMP_ENTRIES > 20) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_4124cb40", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg5.yaml", + "section": "pmpcfg5.pmp21cfg", + "text": "CSR pmpcfg5 field pmp21cfg (bits=15-8) *PMP configuration for entry 21*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 14:13 ! _Reserved_ Writes shall be ignor type: if (NUM_PMP_ENTRIES > 21) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_dfa61e61", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg5.yaml", + "section": "pmpcfg5.pmp22cfg", + "text": "CSR pmpcfg5 field pmp22cfg (bits=23-16) *PMP configuration for entry 22*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 22:21 ! _Reserved_ Writes shall be ignor type: if (NUM_PMP_ENTRIES > 22) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_b3cdefc9", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg5.yaml", + "section": "pmpcfg5.pmp23cfg", + "text": "CSR pmpcfg5 field pmp23cfg (bits=31-24) *PMP configuration for entry 23*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 30:29 ! _Reserved_ Writes shall be ignor type: if (NUM_PMP_ENTRIES > 23) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_2a1ec362", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg6.yaml", + "section": "pmpcfg6", + "text": "CSR pmpcfg6 (address=934, priv=M): PMP entry configuration", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_195ec384", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg6.yaml", + "section": "pmpcfg6.pmp24cfg", + "text": "CSR pmpcfg6 field pmp24cfg (bits=7-0) *PMP configuration for entry 24*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 6:5 ! _Reserved_ Writes shall be ignored. type: if (NUM_PMP_ENTRIES > 24) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_c80e7a9c", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg6.yaml", + "section": "pmpcfg6.pmp25cfg", + "text": "CSR pmpcfg6 field pmp25cfg (bits=15-8) *PMP configuration for entry 25*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 14:13 ! _Reserved_ Writes shall be ignor type: if (NUM_PMP_ENTRIES > 25) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ecf1c37e", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg6.yaml", + "section": "pmpcfg6.pmp26cfg", + "text": "CSR pmpcfg6 field pmp26cfg (bits=23-16) *PMP configuration for entry 26*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 22:21 ! _Reserved_ Writes shall be ignor type: if (NUM_PMP_ENTRIES > 26) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_7d9883d8", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg6.yaml", + "section": "pmpcfg6.pmp27cfg", + "text": "CSR pmpcfg6 field pmp27cfg (bits=31-24) *PMP configuration for entry 27*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 30:29 ! _Reserved_ Writes shall be ignor type: if (NUM_PMP_ENTRIES > 27) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_a0077e12", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg6.yaml", + "section": "pmpcfg6.pmp28cfg", + "text": "CSR pmpcfg6 field pmp28cfg (bits=39-32) *PMP configuration for entry 28*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 39 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 38:37 ! _Reserved_ Writes shall be ignor type: if (NUM_PMP_ENTRIES > 28) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_7e4e16cb", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg6.yaml", + "section": "pmpcfg6.pmp29cfg", + "text": "CSR pmpcfg6 field pmp29cfg (bits=47-40) *PMP configuration for entry 29*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 47 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 46:45 ! _Reserved_ Writes shall be ignor type: if (NUM_PMP_ENTRIES > 29) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_01141cf9", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg6.yaml", + "section": "pmpcfg6.pmp30cfg", + "text": "CSR pmpcfg6 field pmp30cfg (bits=55-48) *PMP configuration for entry 30*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 55 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 54:53 ! _Reserved_ Writes shall be ignor type: if (NUM_PMP_ENTRIES > 30) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_9a3f5127", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg6.yaml", + "section": "pmpcfg6.pmp31cfg", + "text": "CSR pmpcfg6 field pmp31cfg (bits=63-56) *PMP configuration for entry 31*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 63 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 62:61 ! _Reserved_ Writes shall be ignor type: if (NUM_PMP_ENTRIES > 31) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_a27e60c5", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg7.yaml", + "section": "pmpcfg7", + "text": "CSR pmpcfg7 (address=935, priv=M): PMP entry configuration", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_1a0ec60a", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg7.yaml", + "section": "pmpcfg7.pmp28cfg", + "text": "CSR pmpcfg7 field pmp28cfg (bits=7-0) *PMP configuration for entry 28*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 6:5 ! _Reserved_ Writes shall be ignored. type: if (NUM_PMP_ENTRIES > 28) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_e7728778", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg7.yaml", + "section": "pmpcfg7.pmp29cfg", + "text": "CSR pmpcfg7 field pmp29cfg (bits=15-8) *PMP configuration for entry 29*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 14:13 ! _Reserved_ Writes shall be ignor type: if (NUM_PMP_ENTRIES > 29) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_efa35d98", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg7.yaml", + "section": "pmpcfg7.pmp30cfg", + "text": "CSR pmpcfg7 field pmp30cfg (bits=23-16) *PMP configuration for entry 30*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 22:21 ! _Reserved_ Writes shall be ignor type: if (NUM_PMP_ENTRIES > 30) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_69a2ae11", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg7.yaml", + "section": "pmpcfg7.pmp31cfg", + "text": "CSR pmpcfg7 field pmp31cfg (bits=31-24) *PMP configuration for entry 31*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 30:29 ! _Reserved_ Writes shall be ignor type: if (NUM_PMP_ENTRIES > 31) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_4848d3ba", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg8.yaml", + "section": "pmpcfg8", + "text": "CSR pmpcfg8 (address=936, priv=M): PMP entry configuration", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_bd478d15", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg8.yaml", + "section": "pmpcfg8.pmp32cfg", + "text": "CSR pmpcfg8 field pmp32cfg (bits=7-0) *PMP configuration for entry 32*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 6:5 ! _Reserved_ Writes shall be ignored. type: if (NUM_PMP_ENTRIES > 32) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_3e7295f4", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg8.yaml", + "section": "pmpcfg8.pmp33cfg", + "text": "CSR pmpcfg8 field pmp33cfg (bits=15-8) *PMP configuration for entry 33*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 14:13 ! _Reserved_ Writes shall be ignor type: if (NUM_PMP_ENTRIES > 33) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_5c5a3106", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg8.yaml", + "section": "pmpcfg8.pmp34cfg", + "text": "CSR pmpcfg8 field pmp34cfg (bits=23-16) *PMP configuration for entry 34*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 22:21 ! _Reserved_ Writes shall be ignor type: if (NUM_PMP_ENTRIES > 34) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ea338bd4", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg8.yaml", + "section": "pmpcfg8.pmp35cfg", + "text": "CSR pmpcfg8 field pmp35cfg (bits=31-24) *PMP configuration for entry 35*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 30:29 ! _Reserved_ Writes shall be ignor type: if (NUM_PMP_ENTRIES > 35) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ff3eaadc", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg8.yaml", + "section": "pmpcfg8.pmp36cfg", + "text": "CSR pmpcfg8 field pmp36cfg (bits=39-32) *PMP configuration for entry 36*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 39 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 38:37 ! _Reserved_ Writes shall be ignor type: if (NUM_PMP_ENTRIES > 36) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_5bf0599d", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg8.yaml", + "section": "pmpcfg8.pmp37cfg", + "text": "CSR pmpcfg8 field pmp37cfg (bits=47-40) *PMP configuration for entry 37*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 47 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 46:45 ! _Reserved_ Writes shall be ignor type: if (NUM_PMP_ENTRIES > 37) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_176969d9", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg8.yaml", + "section": "pmpcfg8.pmp38cfg", + "text": "CSR pmpcfg8 field pmp38cfg (bits=55-48) *PMP configuration for entry 38*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 55 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 54:53 ! _Reserved_ Writes shall be ignor type: if (NUM_PMP_ENTRIES > 38) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ed9582f7", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg8.yaml", + "section": "pmpcfg8.pmp39cfg", + "text": "CSR pmpcfg8 field pmp39cfg (bits=63-56) *PMP configuration for entry 39*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 63 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 62:61 ! _Reserved_ Writes shall be ignor type: if (NUM_PMP_ENTRIES > 39) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_8840fae0", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg9.yaml", + "section": "pmpcfg9", + "text": "CSR pmpcfg9 (address=937, priv=M): PMP entry configuration", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_84c41168", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg9.yaml", + "section": "pmpcfg9.pmp36cfg", + "text": "CSR pmpcfg9 field pmp36cfg (bits=7-0) *PMP configuration for entry 36*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 7 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 6:5 ! _Reserved_ Writes shall be ignored. type: if (NUM_PMP_ENTRIES > 36) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ffecbef6", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg9.yaml", + "section": "pmpcfg9.pmp37cfg", + "text": "CSR pmpcfg9 field pmp37cfg (bits=15-8) *PMP configuration for entry 37*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 15 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 14:13 ! _Reserved_ Writes shall be ignor type: if (NUM_PMP_ENTRIES > 37) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_e6fe3731", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg9.yaml", + "section": "pmpcfg9.pmp38cfg", + "text": "CSR pmpcfg9 field pmp38cfg (bits=23-16) *PMP configuration for entry 38*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 23 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 22:21 ! _Reserved_ Writes shall be ignor type: if (NUM_PMP_ENTRIES > 38) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_f44638ab", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/I/pmpcfg9.yaml", + "section": "pmpcfg9.pmp39cfg", + "text": "CSR pmpcfg9 field pmp39cfg (bits=31-24) *PMP configuration for entry 39*\n\nThe bits are as follows:\n\n[separator=\"!\",%autowidth]\n!===\n! Name ! Location ! Description\n\nh! L ! 31 ! Locks the entry from further modification. Additionally, when set, PMP checks also apply to M-mode for the entry.\nh! - ! 30:29 ! _Reserved_ Writes shall be ignor type: if (NUM_PMP_ENTRIES > 39) { reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_8d5ad061", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/S/scounteren.yaml", + "section": "scounteren", + "text": "CSR scounteren (address=262, priv=S): Delegates control of the hardware performance-monitoring counters\nto U-mode", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "S" + }, + { + "chunk_id": "chunk_e080dc35", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/S/scounteren.yaml", + "section": "scounteren.CY", + "text": "CSR scounteren field CY (bits=rv32=? rv64=?) When both `scounteren.CY` and `mcounteren.CY` are set, the `cycle` CSR (an alias of `mcycle`) is accessible to U-mode\n<% if ext?(:H) %>(delegation to VS/VU mode is further handled by `hcounteren.CY`)<% end %>. type: if (SCOUNTENABLE_EN[0]) { reset: if (SCOUNTENABLE_EN[0]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_4eba99d0", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/S/scounteren.yaml", + "section": "scounteren.TM", + "text": "CSR scounteren field TM (bits=1) When both `scounteren.TM` and `mcounteren.TM` are set, the `time` CSR (an alias of `mtime` memory-mapped CSR) is accessible to U-mode\n<% if ext?(:H) %>(delegation to VS/VU mode is further handled by `hcounteren.TM`)<% end %>. type: if (SCOUNTENABLE_EN[1]) { reset: if (SCOUNTENABLE_EN[1]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_2ee84cdb", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/S/scounteren.yaml", + "section": "scounteren.IR", + "text": "CSR scounteren field IR (bits=2) When both `scounteren.IR` and `mcounteren.IR` are set, the `instret` CSR (an alias of memory-mapped `minstret`) is accessible to U-mode\n<% if ext?(:H) %>(delegation to VS/VU mode is further handled by `hcounteren.IR`)<% end %>. type: if (SCOUNTENABLE_EN[2]) { reset: if (SCOUNTENABLE_EN[2]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_00bd5b17", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/S/scounteren.yaml", + "section": "scounteren.HPM3", + "text": "CSR scounteren field HPM3 (bits=3) When both `scounteren.HPM3` and `mcounteren.HPM3` are set, the `hpmcounter3` CSR (an alias of `mhpmcounter3`)\nis accessible to U-mode\n<% if ext?(:H) %>(delegation to VS/VU mode is further handled by `hcounteren.HPM3`)<% end %>. type: if (SCOUNTENABLE_EN[3]) { reset: if (SCOUNTENABLE_EN[3]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_6c2b790d", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/S/scounteren.yaml", + "section": "scounteren.HPM4", + "text": "CSR scounteren field HPM4 (bits=4) When both `scounteren.HPM4` and `mcounteren.HPM4` are set, the `hpmcounter4` CSR (an alias of `mhpmcounter4`)\nis accessible to U-mode\n<% if ext?(:H) %>(delegation to VS/VU mode is further handled by `hcounteren.HPM4`)<% end %>. type: if (SCOUNTENABLE_EN[4]) { reset: if (SCOUNTENABLE_EN[4]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_b43a905d", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/S/scounteren.yaml", + "section": "scounteren.HPM5", + "text": "CSR scounteren field HPM5 (bits=5) When both `scounteren.HPM5` and `mcounteren.HPM5` are set, the `hpmcounter5` CSR (an alias of `mhpmcounter5`)\nis accessible to U-mode\n<% if ext?(:H) %>(delegation to VS/VU mode is further handled by `hcounteren.HPM5`)<% end %>. type: if (SCOUNTENABLE_EN[5]) { reset: if (SCOUNTENABLE_EN[5]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_0f3ee534", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/S/scounteren.yaml", + "section": "scounteren.HPM6", + "text": "CSR scounteren field HPM6 (bits=6) When both `scounteren.HPM6` and `mcounteren.HPM6` are set, the `hpmcounter6` CSR (an alias of `mhpmcounter6`)\nis accessible to U-mode\n<% if ext?(:H) %>(delegation to VS/VU mode is further handled by `hcounteren.HPM6`)<% end %>. type: if (SCOUNTENABLE_EN[6]) { reset: if (SCOUNTENABLE_EN[6]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_6bc00208", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/S/scounteren.yaml", + "section": "scounteren.HPM7", + "text": "CSR scounteren field HPM7 (bits=7) When both `scounteren.HPM7` and `mcounteren.HPM7` are set, the `hpmcounter7` CSR (an alias of `mhpmcounter7`)\nis accessible to U-mode\n<% if ext?(:H) %>(delegation to VS/VU mode is further handled by `hcounteren.HPM7`)<% end %>. type: if (SCOUNTENABLE_EN[7]) { reset: if (SCOUNTENABLE_EN[7]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_0e71245b", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/S/scounteren.yaml", + "section": "scounteren.HPM8", + "text": "CSR scounteren field HPM8 (bits=8) When both `scounteren.HPM8` and `mcounteren.HPM8` are set, the `hpmcounter8` CSR (an alias of `mhpmcounter8`)\nis accessible to U-mode\n<% if ext?(:H) %>(delegation to VS/VU mode is further handled by `hcounteren.HPM8`)<% end %>. type: if (SCOUNTENABLE_EN[8]) { reset: if (SCOUNTENABLE_EN[8]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_622dd256", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/S/scounteren.yaml", + "section": "scounteren.HPM9", + "text": "CSR scounteren field HPM9 (bits=9) When both `scounteren.HPM9` and `mcounteren.HPM9` are set, the `hpmcounter9` CSR (an alias of `mhpmcounter9`)\nis accessible to U-mode\n<% if ext?(:H) %>(delegation to VS/VU mode is further handled by `hcounteren.HPM9`)<% end %>. type: if (SCOUNTENABLE_EN[9]) { reset: if (SCOUNTENABLE_EN[9]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_14715618", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/S/scounteren.yaml", + "section": "scounteren.HPM10", + "text": "CSR scounteren field HPM10 (bits=10) When both `scounteren.HPM10` and `mcounteren.HPM10` are set, the `hpmcounter10` CSR (an alias of `mhpmcounter10`)\nis accessible to U-mode\n<% if ext?(:H) %>(delegation to VS/VU mode is further handled by `hcounteren.HPM10`)<% end %>. type: if (SCOUNTENABLE_EN[10]) { reset: if (SCOUNTENABLE_EN[10]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_f7e387a4", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/S/scounteren.yaml", + "section": "scounteren.HPM11", + "text": "CSR scounteren field HPM11 (bits=11) When both `scounteren.HPM11` and `mcounteren.HPM11` are set, the `hpmcounter11` CSR (an alias of `mhpmcounter11`)\nis accessible to U-mode\n<% if ext?(:H) %>(delegation to VS/VU mode is further handled by `hcounteren.HPM11`)<% end %>. type: if (SCOUNTENABLE_EN[11]) { reset: if (SCOUNTENABLE_EN[11]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_e2090e04", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/S/scounteren.yaml", + "section": "scounteren.HPM12", + "text": "CSR scounteren field HPM12 (bits=12) When both `scounteren.HPM12` and `mcounteren.HPM12` are set, the `hpmcounter12` CSR (an alias of `mhpmcounter12`)\nis accessible to U-mode\n<% if ext?(:H) %>(delegation to VS/VU mode is further handled by `hcounteren.HPM12`)<% end %>. type: if (SCOUNTENABLE_EN[12]) { reset: if (SCOUNTENABLE_EN[12]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_e0134f9e", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/S/scounteren.yaml", + "section": "scounteren.HPM13", + "text": "CSR scounteren field HPM13 (bits=13) When both `scounteren.HPM13` and `mcounteren.HPM13` are set, the `hpmcounter13` CSR (an alias of `mhpmcounter13`)\nis accessible to U-mode\n<% if ext?(:H) %>(delegation to VS/VU mode is further handled by `hcounteren.HPM13`)<% end %>. type: if (SCOUNTENABLE_EN[13]) { reset: if (SCOUNTENABLE_EN[13]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_f6f96b29", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/S/scounteren.yaml", + "section": "scounteren.HPM14", + "text": "CSR scounteren field HPM14 (bits=14) When both `scounteren.HPM14` and `mcounteren.HPM14` are set, the `hpmcounter14` CSR (an alias of `mhpmcounter14`)\nis accessible to U-mode\n<% if ext?(:H) %>(delegation to VS/VU mode is further handled by `hcounteren.HPM14`)<% end %>. type: if (SCOUNTENABLE_EN[14]) { reset: if (SCOUNTENABLE_EN[14]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_1fc78dd1", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/S/scounteren.yaml", + "section": "scounteren.HPM15", + "text": "CSR scounteren field HPM15 (bits=15) When both `scounteren.HPM15` and `mcounteren.HPM15` are set, the `hpmcounter15` CSR (an alias of `mhpmcounter15`)\nis accessible to U-mode\n<% if ext?(:H) %>(delegation to VS/VU mode is further handled by `hcounteren.HPM15`)<% end %>. type: if (SCOUNTENABLE_EN[15]) { reset: if (SCOUNTENABLE_EN[15]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_837eaabf", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/S/scounteren.yaml", + "section": "scounteren.HPM16", + "text": "CSR scounteren field HPM16 (bits=16) When both `scounteren.HPM16` and `mcounteren.HPM16` are set, the `hpmcounter16` CSR (an alias of `mhpmcounter16`)\nis accessible to U-mode\n<% if ext?(:H) %>(delegation to VS/VU mode is further handled by `hcounteren.HPM16`)<% end %>. type: if (SCOUNTENABLE_EN[16]) { reset: if (SCOUNTENABLE_EN[16]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d16d7fa2", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/S/scounteren.yaml", + "section": "scounteren.HPM17", + "text": "CSR scounteren field HPM17 (bits=17) When both `scounteren.HPM17` and `mcounteren.HPM17` are set, the `hpmcounter17` CSR (an alias of `mhpmcounter17`)\nis accessible to U-mode\n<% if ext?(:H) %>(delegation to VS/VU mode is further handled by `hcounteren.HPM17`)<% end %>. type: if (SCOUNTENABLE_EN[17]) { reset: if (SCOUNTENABLE_EN[17]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_31b2bf52", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/S/scounteren.yaml", + "section": "scounteren.HPM18", + "text": "CSR scounteren field HPM18 (bits=18) When both `scounteren.HPM18` and `mcounteren.HPM18` are set, the `hpmcounter18` CSR (an alias of `mhpmcounter18`)\nis accessible to U-mode\n<% if ext?(:H) %>(delegation to VS/VU mode is further handled by `hcounteren.HPM18`)<% end %>. type: if (SCOUNTENABLE_EN[18]) { reset: if (SCOUNTENABLE_EN[18]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_8c343bca", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/S/scounteren.yaml", + "section": "scounteren.HPM19", + "text": "CSR scounteren field HPM19 (bits=19) When both `scounteren.HPM19` and `mcounteren.HPM19` are set, the `hpmcounter19` CSR (an alias of `mhpmcounter19`)\nis accessible to U-mode\n<% if ext?(:H) %>(delegation to VS/VU mode is further handled by `hcounteren.HPM19`)<% end %>. type: if (SCOUNTENABLE_EN[19]) { reset: if (SCOUNTENABLE_EN[19]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_c855f9cb", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/S/scounteren.yaml", + "section": "scounteren.HPM20", + "text": "CSR scounteren field HPM20 (bits=20) When both `scounteren.HPM20` and `mcounteren.HPM20` are set, the `hpmcounter20` CSR (an alias of `mhpmcounter20`)\nis accessible to U-mode\n<% if ext?(:H) %>(delegation to VS/VU mode is further handled by `hcounteren.HPM20`)<% end %>. type: if (SCOUNTENABLE_EN[20]) { reset: if (SCOUNTENABLE_EN[20]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_b432e254", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/S/scounteren.yaml", + "section": "scounteren.HPM21", + "text": "CSR scounteren field HPM21 (bits=21) When both `scounteren.HPM21` and `mcounteren.HPM21` are set, the `hpmcounter21` CSR (an alias of `mhpmcounter21`)\nis accessible to U-mode\n<% if ext?(:H) %>(delegation to VS/VU mode is further handled by `hcounteren.HPM21`)<% end %>. type: if (SCOUNTENABLE_EN[21]) { reset: if (SCOUNTENABLE_EN[21]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_91bae51e", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/S/scounteren.yaml", + "section": "scounteren.HPM22", + "text": "CSR scounteren field HPM22 (bits=22) When both `scounteren.HPM22` and `mcounteren.HPM22` are set, the `hpmcounter22` CSR (an alias of `mhpmcounter22`)\nis accessible to U-mode\n<% if ext?(:H) %>(delegation to VS/VU mode is further handled by `hcounteren.HPM22`)<% end %>. type: if (SCOUNTENABLE_EN[22]) { reset: if (SCOUNTENABLE_EN[22]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ddad6c0c", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/S/scounteren.yaml", + "section": "scounteren.HPM23", + "text": "CSR scounteren field HPM23 (bits=23) When both `scounteren.HPM23` and `mcounteren.HPM23` are set, the `hpmcounter23` CSR (an alias of `mhpmcounter23`)\nis accessible to U-mode\n<% if ext?(:H) %>(delegation to VS/VU mode is further handled by `hcounteren.HPM23`)<% end %>. type: if (SCOUNTENABLE_EN[23]) { reset: if (SCOUNTENABLE_EN[23]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_b3c2c2bb", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/S/scounteren.yaml", + "section": "scounteren.HPM24", + "text": "CSR scounteren field HPM24 (bits=24) When both `scounteren.HPM24` and `mcounteren.HPM24` are set, the `hpmcounter24` CSR (an alias of `mhpmcounter24`)\nis accessible to U-mode\n<% if ext?(:H) %>(delegation to VS/VU mode is further handled by `hcounteren.HPM24`)<% end %>. type: if (SCOUNTENABLE_EN[24]) { reset: if (SCOUNTENABLE_EN[24]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d62d34d8", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/S/scounteren.yaml", + "section": "scounteren.HPM25", + "text": "CSR scounteren field HPM25 (bits=25) When both `scounteren.HPM25` and `mcounteren.HPM25` are set, the `hpmcounter25` CSR (an alias of `mhpmcounter25`)\nis accessible to U-mode\n<% if ext?(:H) %>(delegation to VS/VU mode is further handled by `hcounteren.HPM25`)<% end %>. type: if (SCOUNTENABLE_EN[25]) { reset: if (SCOUNTENABLE_EN[25]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_9640c665", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/S/scounteren.yaml", + "section": "scounteren.HPM26", + "text": "CSR scounteren field HPM26 (bits=26) When both `scounteren.HPM26` and `mcounteren.HPM26` are set, the `hpmcounter26` CSR (an alias of `mhpmcounter26`)\nis accessible to U-mode\n<% if ext?(:H) %>(delegation to VS/VU mode is further handled by `hcounteren.HPM26`)<% end %>. type: if (SCOUNTENABLE_EN[26]) { reset: if (SCOUNTENABLE_EN[26]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d652f5a5", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/S/scounteren.yaml", + "section": "scounteren.HPM27", + "text": "CSR scounteren field HPM27 (bits=27) When both `scounteren.HPM27` and `mcounteren.HPM27` are set, the `hpmcounter27` CSR (an alias of `mhpmcounter27`)\nis accessible to U-mode\n<% if ext?(:H) %>(delegation to VS/VU mode is further handled by `hcounteren.HPM27`)<% end %>. type: if (SCOUNTENABLE_EN[27]) { reset: if (SCOUNTENABLE_EN[27]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_c3f8207a", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/S/scounteren.yaml", + "section": "scounteren.HPM28", + "text": "CSR scounteren field HPM28 (bits=28) When both `scounteren.HPM28` and `mcounteren.HPM28` are set, the `hpmcounter28` CSR (an alias of `mhpmcounter28`)\nis accessible to U-mode\n<% if ext?(:H) %>(delegation to VS/VU mode is further handled by `hcounteren.HPM28`)<% end %>. type: if (SCOUNTENABLE_EN[28]) { reset: if (SCOUNTENABLE_EN[28]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_0a9fbdb9", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/S/scounteren.yaml", + "section": "scounteren.HPM29", + "text": "CSR scounteren field HPM29 (bits=29) When both `scounteren.HPM29` and `mcounteren.HPM29` are set, the `hpmcounter29` CSR (an alias of `mhpmcounter29`)\nis accessible to U-mode\n<% if ext?(:H) %>(delegation to VS/VU mode is further handled by `hcounteren.HPM29`)<% end %>. type: if (SCOUNTENABLE_EN[29]) { reset: if (SCOUNTENABLE_EN[29]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_3689e6ac", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/S/scounteren.yaml", + "section": "scounteren.HPM30", + "text": "CSR scounteren field HPM30 (bits=30) When both `scounteren.HPM30` and `mcounteren.HPM30` are set, the `hpmcounter30` CSR (an alias of `mhpmcounter30`)\nis accessible to U-mode\n<% if ext?(:H) %>(delegation to VS/VU mode is further handled by `hcounteren.HPM30`)<% end %>. type: if (SCOUNTENABLE_EN[30]) { reset: if (SCOUNTENABLE_EN[30]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_93dd6752", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/S/scounteren.yaml", + "section": "scounteren.HPM31", + "text": "CSR scounteren field HPM31 (bits=31) When both `scounteren.HPM31` and `mcounteren.HPM31` are set, the `hpmcounter31` CSR (an alias of `mhpmcounter31`)\nis accessible to U-mode\n<% if ext?(:H) %>(delegation to VS/VU mode is further handled by `hcounteren.HPM31`)<% end %>. type: if (SCOUNTENABLE_EN[31]) { reset: if (SCOUNTENABLE_EN[31]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_eec660fc", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcntrpmf/mcyclecfg.yaml", + "section": "mcyclecfg", + "text": "CSR mcyclecfg (address=801, priv=M): The `mcyclecfg` CSR is a 64-bit machine-level register that configures privilege\nmode filtering for the cycle counter. Each inhibit bit (xINH) suppresses\ncounting of events in the corresponding privilege mode when set.\n\n| Field | Description |\n|---------", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Smcntrpmf" + }, + { + "chunk_id": "chunk_b5df1b60", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcntrpmf/mcyclecfg.yaml", + "section": "mcyclecfg.MINH", + "text": "CSR mcyclecfg field MINH (bits=62) If set, then counting of events in M-mode is inhibited. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_9bb7e31f", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcntrpmf/mcyclecfg.yaml", + "section": "mcyclecfg.SINH", + "text": "CSR mcyclecfg field SINH (bits=61) If set, then counting of events in S/HS-mode is inhibited. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_b7e9f1a1", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcntrpmf/mcyclecfg.yaml", + "section": "mcyclecfg.UINH", + "text": "CSR mcyclecfg field UINH (bits=60) If set, then counting of events in U-mode is inhibited. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d1219fb1", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcntrpmf/mcyclecfg.yaml", + "section": "mcyclecfg.VSINH", + "text": "CSR mcyclecfg field VSINH (bits=59) If set, then counting of events in VS-mode is inhibited. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ea73e916", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcntrpmf/mcyclecfg.yaml", + "section": "mcyclecfg.VUINH", + "text": "CSR mcyclecfg field VUINH (bits=58) If set, then counting of events in VU-mode is inhibited. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_8ff9c17d", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcntrpmf/mcyclecfgh.yaml", + "section": "mcyclecfgh", + "text": "CSR mcyclecfgh (address=1825, priv=M): Upper 32 bits of the 64-bit `mcyclecfg` CSR, used for RV32 systems to access\nthe privilege mode filtering inhibit bits.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Smcntrpmf" + }, + { + "chunk_id": "chunk_34e58150", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcntrpmf/mcyclecfgh.yaml", + "section": "mcyclecfgh.MINH", + "text": "CSR mcyclecfgh field MINH (bits=30) If set, then counting of events in M-mode is inhibited. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_13bf32e4", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcntrpmf/mcyclecfgh.yaml", + "section": "mcyclecfgh.SINH", + "text": "CSR mcyclecfgh field SINH (bits=29) If set, then counting of events in S/HS-mode is inhibited. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_420a1ab1", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcntrpmf/mcyclecfgh.yaml", + "section": "mcyclecfgh.UINH", + "text": "CSR mcyclecfgh field UINH (bits=28) If set, then counting of events in U-mode is inhibited. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_e40814ef", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcntrpmf/mcyclecfgh.yaml", + "section": "mcyclecfgh.VSINH", + "text": "CSR mcyclecfgh field VSINH (bits=27) If set, then counting of events in VS-mode is inhibited. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_95d25558", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcntrpmf/mcyclecfgh.yaml", + "section": "mcyclecfgh.VUINH", + "text": "CSR mcyclecfgh field VUINH (bits=26) If set, then counting of events in VU-mode is inhibited. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_2701c3ee", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcntrpmf/minstretcfg.yaml", + "section": "minstretcfg", + "text": "CSR minstretcfg (address=802, priv=M): The `minstretcfg` CSR is a 64-bit machine-level register that configures privilege\nmode filtering for the `minstret` (Machine Instructions-Retired Counter). Each inhibit bit (xINH)\ndisables counting of retired instructions in the associated privilege mode.\n\n| Field | Description ", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Smcntrpmf" + }, + { + "chunk_id": "chunk_4c55bbdf", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcntrpmf/minstretcfg.yaml", + "section": "minstretcfg.MINH", + "text": "CSR minstretcfg field MINH (bits=62) If set, then counting of events in M-mode is inhibited. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_0ec7608b", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcntrpmf/minstretcfg.yaml", + "section": "minstretcfg.SINH", + "text": "CSR minstretcfg field SINH (bits=61) If set, then counting of events in S/HS-mode is inhibited. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_db8c53d7", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcntrpmf/minstretcfg.yaml", + "section": "minstretcfg.UINH", + "text": "CSR minstretcfg field UINH (bits=60) If set, then counting of events in U-mode is inhibited. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_28d88a9f", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcntrpmf/minstretcfg.yaml", + "section": "minstretcfg.VSINH", + "text": "CSR minstretcfg field VSINH (bits=59) If set, then counting of events in VS-mode is inhibited. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_1973992f", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcntrpmf/minstretcfg.yaml", + "section": "minstretcfg.VUINH", + "text": "CSR minstretcfg field VUINH (bits=58) If set, then counting of events in VU-mode is inhibited. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_928a7c8f", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcntrpmf/minstretcfgh.yaml", + "section": "minstretcfgh", + "text": "CSR minstretcfgh (address=1826, priv=M): Upper 32 bits of the 64-bit `minstretcfg` CSR, used on RV32 systems to access\nprivilege mode filtering inhibit bits for instruction retirement.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Smcntrpmf" + }, + { + "chunk_id": "chunk_70d0b628", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcntrpmf/minstretcfgh.yaml", + "section": "minstretcfgh.MINH", + "text": "CSR minstretcfgh field MINH (bits=30) If set, then counting of events in M-mode is inhibited. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ee2bb39d", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcntrpmf/minstretcfgh.yaml", + "section": "minstretcfgh.SINH", + "text": "CSR minstretcfgh field SINH (bits=29) If set, then counting of events in S/HS-mode is inhibited. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_5428759f", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcntrpmf/minstretcfgh.yaml", + "section": "minstretcfgh.UINH", + "text": "CSR minstretcfgh field UINH (bits=28) If set, then counting of events in U-mode is inhibited. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_2f567892", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcntrpmf/minstretcfgh.yaml", + "section": "minstretcfgh.VSINH", + "text": "CSR minstretcfgh field VSINH (bits=27) If set, then counting of events in VS-mode is inhibited. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_c30a8cac", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcntrpmf/minstretcfgh.yaml", + "section": "minstretcfgh.VUINH", + "text": "CSR minstretcfgh field VUINH (bits=26) If set, then counting of events in VU-mode is inhibited. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_90ee938a", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcsrind/mireg.yaml", + "section": "mireg", + "text": "CSR mireg (address=849, priv=M): The mireg machine indirect alias CSR is used to access another CSR's state\nindirectly upon a read or write, as determined by the value of miselect.\n\nThe behavior upon accessing mireg from M-mode, while miselect holds a value\nthat is not implemented, is UNSPECIFIED.\n\nIt is expected that implementatio", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Smcsrind" + }, + { + "chunk_id": "chunk_385e176a", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcsrind/mireg.yaml", + "section": "mireg.VALUE", + "text": "CSR mireg field VALUE (bits=rv32=31-0 rv64=63-0) Register state of the CSR selected by the current `miselect` value type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_03eb7bfe", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcsrind/mireg2.yaml", + "section": "mireg2", + "text": "CSR mireg2 (address=850, priv=M): The `mireg2` machine indirect alias CSR is used to access register state indirectly\nupon a read or write, as determined by the value of `miselect`.\n\nThe behavior upon accessing `mireg2` from M-mode, while `miselect` holds a value\nthat is not implemented, is UNSPECIFIED.\n\nIt is expected that implemen", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Smcsrind" + }, + { + "chunk_id": "chunk_c2ec4668", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcsrind/mireg2.yaml", + "section": "mireg2.VALUE", + "text": "CSR mireg2 field VALUE (bits=rv32=31-0 rv64=63-0) Register state of the CSR selected by the current `miselect` value type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_f0dc6f2e", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcsrind/mireg3.yaml", + "section": "mireg3", + "text": "CSR mireg3 (address=851, priv=M): The `mireg3` machine indirect alias CSR is used to access register state indirectly\nupon a read or write, as determined by the value of `miselect`.\n\nThe behavior upon accessing `mireg3` from M-mode, while `miselect` holds a value\nthat is not implemented, is UNSPECIFIED.\n\nIt is expected that implemen", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Smcsrind" + }, + { + "chunk_id": "chunk_49921fd7", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcsrind/mireg3.yaml", + "section": "mireg3.VALUE", + "text": "CSR mireg3 field VALUE (bits=rv32=31-0 rv64=63-0) Register state of the CSR selected by the current `miselect` value type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_a5981028", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcsrind/mireg4.yaml", + "section": "mireg4", + "text": "CSR mireg4 (address=853, priv=M): The `mireg4` machine indirect alias CSR is used to access register state indirectly\nupon a read or write, as determined by the value of `miselect`.\n\nThe behavior upon accessing `mireg4` from M-mode, while `miselect` holds a value\nthat is not implemented, is UNSPECIFIED.\n\nIt is expected that implemen", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Smcsrind" + }, + { + "chunk_id": "chunk_020d8c3d", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcsrind/mireg4.yaml", + "section": "mireg4.VALUE", + "text": "CSR mireg4 field VALUE (bits=rv32=31-0 rv64=63-0) Register state of the CSR selected by the current `miselect` value type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_f5e3c415", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcsrind/mireg5.yaml", + "section": "mireg5", + "text": "CSR mireg5 (address=854, priv=M): The `mireg5` machine indirect alias CSR is used to access register state indirectly\nupon a read or write, as determined by the value of `miselect`.\n\nThe behavior upon accessing `mireg5` from M-mode, while `miselect` holds a value\nthat is not implemented, is UNSPECIFIED.\n\nIt is expected that implemen", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Smcsrind" + }, + { + "chunk_id": "chunk_84a3e9ba", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcsrind/mireg5.yaml", + "section": "mireg5.VALUE", + "text": "CSR mireg5 field VALUE (bits=rv32=31-0 rv64=63-0) Register state of the CSR selected by the current `miselect` value type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_90cc3f48", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcsrind/mireg6.yaml", + "section": "mireg6", + "text": "CSR mireg6 (address=855, priv=M): The `mireg6` machine indirect alias CSR is used to access register state indirectly\nupon a read or write, as determined by the value of `miselect`.\n\nThe behavior upon accessing `mireg6` from M-mode, while `miselect` holds a value\nthat is not implemented, is UNSPECIFIED.\n\nIt is expected that implemen", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Smcsrind" + }, + { + "chunk_id": "chunk_04e48420", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcsrind/mireg6.yaml", + "section": "mireg6.VALUE", + "text": "CSR mireg6 field VALUE (bits=rv32=31-0 rv64=63-0) Register state of the CSR selected by the current `miselect` value type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ab71855d", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcsrind/miselect.yaml", + "section": "miselect", + "text": "CSR miselect (address=848, priv=M): The CSRs listed in the table above provide a window for accessing register state indirectly.\nThe value of `miselect` determines which register is accessed upon read or write of each of\nthe machine indirect alias CSRs (`mireg*`). `miselect` value ranges are allocated to dependent\nextensions, which sp", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Smcsrind" + }, + { + "chunk_id": "chunk_f48463cd", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcsrind/miselect.yaml", + "section": "miselect.VALUE", + "text": "CSR miselect field VALUE (bits=rv32=31-0 rv64=63-0) Selects which indirect register is accessed via `mireg*`. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_24d6a6a5", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcsrind/sireg.yaml", + "section": "sireg", + "text": "CSR sireg (address=337, priv=S): Access to `sireg` from M-mode or S-mode while `siselect` holds a number in a\nstandard-defined and implemented range results in specific behavior that, for each combination of\n`siselect` and `sireg`, is defined by the extension to which the `siselect` value is allocated.\n\nOrdinarily, `sireg` will acc", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Sscsrind" + }, + { + "chunk_id": "chunk_b2a53bff", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcsrind/sireg.yaml", + "section": "sireg.VALUE", + "text": "CSR sireg field VALUE (bits=rv32=31-0 rv64=63-0) The data read from or written to the register selected by the current `siselect` value. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_a04fde23", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcsrind/sireg2.yaml", + "section": "sireg2", + "text": "CSR sireg2 (address=338, priv=S): Access to `sireg2` from M-mode or S-mode while `siselect` holds a number in a\nstandard-defined and implemented range results in specific behavior that, for each combination of\n`siselect` and `sireg2`, is defined by the extension to which the `siselect` value is allocated.\n\nOrdinarily, `sireg2` will ", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Sscsrind" + }, + { + "chunk_id": "chunk_a5187a25", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcsrind/sireg2.yaml", + "section": "sireg2.VALUE", + "text": "CSR sireg2 field VALUE (bits=rv32=31-0 rv64=63-0) The data read from or written to the register selected by the current `siselect` value. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_582c4a99", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcsrind/sireg3.yaml", + "section": "sireg3", + "text": "CSR sireg3 (address=339, priv=S): Access to `sireg3` from M-mode or S-mode while `siselect` holds a number in a\nstandard-defined and implemented range results in specific behavior that, for each combination of\n`siselect` and `sireg3`, is defined by the extension to which the `siselect` value is allocated.\n\nOrdinarily, `sireg3` will ", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Sscsrind" + }, + { + "chunk_id": "chunk_1beb4231", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcsrind/sireg3.yaml", + "section": "sireg3.VALUE", + "text": "CSR sireg3 field VALUE (bits=rv32=31-0 rv64=63-0) The data read from or written to the register selected by the current `siselect` value. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_471bde8c", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcsrind/sireg4.yaml", + "section": "sireg4", + "text": "CSR sireg4 (address=341, priv=S): Access to `sireg4` from M-mode or S-mode while `siselect` holds a number in a\nstandard-defined and implemented range results in specific behavior that, for each combination of\n`siselect` and `sireg4`, is defined by the extension to which the `siselect` value is allocated.\n\nOrdinarily, `sireg4` will ", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Sscsrind" + }, + { + "chunk_id": "chunk_29d1c6d2", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcsrind/sireg4.yaml", + "section": "sireg4.VALUE", + "text": "CSR sireg4 field VALUE (bits=rv32=31-0 rv64=63-0) The data read from or written to the register selected by the current `siselect` value. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_126f1557", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcsrind/sireg5.yaml", + "section": "sireg5", + "text": "CSR sireg5 (address=342, priv=S): Access to `sireg5` from M-mode or S-mode while `siselect` holds a number in a\nstandard-defined and implemented range results in specific behavior that, for each combination of\n`siselect` and `sireg5`, is defined by the extension to which the `siselect` value is allocated.\n\nOrdinarily, `sireg5` will ", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Sscsrind" + }, + { + "chunk_id": "chunk_8daa56ec", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcsrind/sireg5.yaml", + "section": "sireg5.VALUE", + "text": "CSR sireg5 field VALUE (bits=rv32=31-0 rv64=63-0) The data read from or written to the register selected by the current `siselect` value. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_a04c74ff", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcsrind/sireg6.yaml", + "section": "sireg6", + "text": "CSR sireg6 (address=343, priv=S): Access to `sireg6` from M-mode or S-mode while `siselect` holds a number in a\nstandard-defined and implemented range results in specific behavior that, for each combination of\n`siselect` and `sireg6`, is defined by the extension to which the `siselect` value is allocated.\n\nOrdinarily, `sireg6` will ", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Sscsrind" + }, + { + "chunk_id": "chunk_05c4bde3", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcsrind/sireg6.yaml", + "section": "sireg6.VALUE", + "text": "CSR sireg6 field VALUE (bits=rv32=31-0 rv64=63-0) The data read from or written to the register selected by the current `siselect` value. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_75eb0884", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcsrind/siselect.yaml", + "section": "siselect", + "text": "CSR siselect (address=336, priv=S): The `siselect` register will support the value range 0..0xFFF at a minimum. A future extension may\ndefine a value range outside of this minimum range. Only if such an extension is implemented will\n`siselect` be required to support larger values.\n\nRequiring a range of 0-0xFFF for `siselect`, even tho", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Sscsrind" + }, + { + "chunk_id": "chunk_d7cd35fe", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcsrind/siselect.yaml", + "section": "siselect.VALUE", + "text": "CSR siselect field VALUE (bits=rv32=31-0 rv64=63-0) Value ranges are allocated to dependent extensions, which specify the\nregister state accessible via each `sireg*` register, for each `siselect` value. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_c3066e84", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcsrind/vsireg.yaml", + "section": "vsireg", + "text": "CSR vsireg (address=593, priv=VS): The `vsireg` CSR is one of several alias registers used to indirectly access\nvirtual supervisor-level CSRs in VS-mode or VU-mode.\n\nThe register addressed by `vsireg` is selected by the current value of the `vsiselect` CSR.\n\nThe alias mechanism allows indirect CSR access, which helps in virtualizatio", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Smcsrind" + }, + { + "chunk_id": "chunk_c304a0e8", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcsrind/vsireg.yaml", + "section": "vsireg.VALUE", + "text": "CSR vsireg field VALUE (bits=rv32=31-0 rv64=63-0) The data read from or written to the register selected by the current\nvalue of the `vsiselect` CSR. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_047bb5bc", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcsrind/vsireg2.yaml", + "section": "vsireg2", + "text": "CSR vsireg2 (address=594, priv=VS): The `vsireg2` CSR is one of several alias registers used to indirectly access\nvirtual supervisor-level CSRs in VS-mode or VU-mode.\n\nThe register addressed by `vsireg2` is selected by the current value of the `vsiselect` CSR.\n\nThe alias mechanism allows indirect CSR access, which helps in virtualizat", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Smcsrind" + }, + { + "chunk_id": "chunk_5dc8ca83", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcsrind/vsireg2.yaml", + "section": "vsireg2.VALUE", + "text": "CSR vsireg2 field VALUE (bits=rv32=31-0 rv64=63-0) Data read or written based on the currently selected `vsiselect` value. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_27fc5471", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcsrind/vsireg3.yaml", + "section": "vsireg3", + "text": "CSR vsireg3 (address=595, priv=VS): The `vsireg3` CSR is one of several alias registers used to indirectly access\nvirtual supervisor-level CSRs in VS-mode or VU-mode.\n\nThe register addressed by `vsireg3` is selected by the current value of the `vsiselect` CSR.\n\nThe alias mechanism allows indirect CSR access, which helps in virtualizat", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Smcsrind" + }, + { + "chunk_id": "chunk_5ff136e8", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcsrind/vsireg3.yaml", + "section": "vsireg3.VALUE", + "text": "CSR vsireg3 field VALUE (bits=rv32=31-0 rv64=63-0) The data read or written based on the currently selected `vsiselect` value. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_07e10822", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcsrind/vsireg4.yaml", + "section": "vsireg4", + "text": "CSR vsireg4 (address=597, priv=VS): The `vsireg4` CSR is one of several alias registers used to indirectly access\nvirtual supervisor-level CSRs in VS-mode or VU-mode.\n\nThe register addressed by `vsireg4` is selected by the current value of the `vsiselect` CSR.\n\nThe alias mechanism allows indirect CSR access, which helps in virtualizat", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Smcsrind" + }, + { + "chunk_id": "chunk_8f93dea9", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcsrind/vsireg4.yaml", + "section": "vsireg4.VALUE", + "text": "CSR vsireg4 field VALUE (bits=rv32=31-0 rv64=63-0) The data read or written based on the currently selected `vsiselect` value. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_77cd00f3", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcsrind/vsireg5.yaml", + "section": "vsireg5", + "text": "CSR vsireg5 (address=598, priv=VS): The `vsireg5` CSR is one of several alias registers used to indirectly access\nvirtual supervisor-level CSRs in VS-mode or VU-mode.\n\nThe register addressed by `vsireg5` is selected by the current value of the `vsiselect` CSR.\n\nThe alias mechanism allows indirect CSR access, which helps in virtualizat", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Smcsrind" + }, + { + "chunk_id": "chunk_3e456312", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcsrind/vsireg5.yaml", + "section": "vsireg5.VALUE", + "text": "CSR vsireg5 field VALUE (bits=rv32=31-0 rv64=63-0) The data read or written from the register selected by the value in `vsiselect`. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_9ec525a6", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcsrind/vsireg6.yaml", + "section": "vsireg6", + "text": "CSR vsireg6 (address=599, priv=VS): The `vsireg6` CSR is one of several alias registers used to indirectly access\nvirtual supervisor-level CSRs in VS-mode or VU-mode.\n\nThe register addressed by `vsireg6` is selected by the current value of the `vsiselect` CSR.\n\nThe alias mechanism allows indirect CSR access, which helps in virtualizat", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Smcsrind" + }, + { + "chunk_id": "chunk_2fff33aa", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcsrind/vsireg6.yaml", + "section": "vsireg6.VALUE", + "text": "CSR vsireg6 field VALUE (bits=rv32=31-0 rv64=63-0) The data read or written from the register selected by the current value of `vsiselect`. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_0cdae335", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcsrind/vsiselect.yaml", + "section": "vsiselect", + "text": "CSR vsiselect (address=592, priv=VS): The `vsiselect` register will support the value range 0..0xFFF at a minimum.\nA future extension may define a value range outside of this minimum range.\nOnly if such an extension is implemented will `vsiselect` be required to support larger values.\n\nRequiring a range of 0-0xFFF for `vsiselect`, even ", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Smcsrind" + }, + { + "chunk_id": "chunk_b6e78903", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smcsrind/vsiselect.yaml", + "section": "vsiselect.VALUE", + "text": "CSR vsiselect field VALUE (bits=rv32=31-0 rv64=63-0) The index value selecting the register accessed through the `vsireg*` alias registers. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_5d70fac2", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smctr/mctrctl.yaml", + "section": "mctrctl", + "text": "CSR mctrctl (address=846, priv=M): The `mctrctl` register enables and configures the Control Transfer Records capability in M mode.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Smctr" + }, + { + "chunk_id": "chunk_4a3b0e09", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smctr/mctrctl.yaml", + "section": "mctrctl.U", + "text": "CSR mctrctl field U (bits=rv32=? rv64=?) Enable transfer recording in the User mode. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_6b15e23c", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smctr/mctrctl.yaml", + "section": "mctrctl.S", + "text": "CSR mctrctl field S (bits=1) Enable transfer recording in the Supervisor mode. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_8a586a5c", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smctr/mctrctl.yaml", + "section": "mctrctl.M", + "text": "CSR mctrctl field M (bits=2) Enable transfer recording in the Machine mode. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ccf09f50", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smctr/mctrctl.yaml", + "section": "mctrctl.RASEMU", + "text": "CSR mctrctl field RASEMU (bits=7) When set, it enables RAS (Return Address Stack) Emulation Mode. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_e83d7c4e", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smctr/mctrctl.yaml", + "section": "mctrctl.STE", + "text": "CSR mctrctl field STE (bits=8) Enables recording of traps to S-mode when S=0. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_76ddc7ea", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smctr/mctrctl.yaml", + "section": "mctrctl.MTE", + "text": "CSR mctrctl field MTE (bits=9) Enables recording of traps to M-mode when M=0. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_7a2e3194", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smctr/mctrctl.yaml", + "section": "mctrctl.BPFRZ", + "text": "CSR mctrctl field BPFRZ (bits=11) Set `sctrstatus.FROZEN` on a breakpoint exception that traps to M or S mode. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_19dc9950", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smctr/mctrctl.yaml", + "section": "mctrctl.LCOFIFRZ", + "text": "CSR mctrctl field LCOFIFRZ (bits=12) Set `sctrstatus.FROZEN` on local-counter-overflow interrupt (LCOFI) that traps\nto M or S mode. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_84ac5a5a", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smctr/mctrctl.yaml", + "section": "mctrctl.EXCINH", + "text": "CSR mctrctl field EXCINH (bits=33) When set, it inhibits recording of exceptions. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_2cbb998e", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smctr/mctrctl.yaml", + "section": "mctrctl.INTRINH", + "text": "CSR mctrctl field INTRINH (bits=34) When set, it inhibits recording of interrupts. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_7e168c2c", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smctr/mctrctl.yaml", + "section": "mctrctl.TRETINH", + "text": "CSR mctrctl field TRETINH (bits=35) When set, it inhibits recording of trap returns. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_76ec3b95", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smctr/mctrctl.yaml", + "section": "mctrctl.NTBREN", + "text": "CSR mctrctl field NTBREN (bits=36) When set, it enables recording of not-taken branches. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ef3308b0", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smctr/mctrctl.yaml", + "section": "mctrctl.TKBRINH", + "text": "CSR mctrctl field TKBRINH (bits=37) When set, it inhibits recording of taken branches. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_102ad72f", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smctr/mctrctl.yaml", + "section": "mctrctl.INDCALLINH", + "text": "CSR mctrctl field INDCALLINH (bits=40) When set, it inhibits recording of indirect calls. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_763bf7d8", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smctr/mctrctl.yaml", + "section": "mctrctl.DIRCALLINH", + "text": "CSR mctrctl field DIRCALLINH (bits=41) When set, it inhibits recording of direct calls. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_e4e3e04d", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smctr/mctrctl.yaml", + "section": "mctrctl.INDJMPINH", + "text": "CSR mctrctl field INDJMPINH (bits=42) When set, it inhibits recording of indirect jumps (without linkage). type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_4bc5dbed", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smctr/mctrctl.yaml", + "section": "mctrctl.DIRJMPINH", + "text": "CSR mctrctl field DIRJMPINH (bits=43) When set, it inhibits recording of direct jumps (without linkage). type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_93363780", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smctr/mctrctl.yaml", + "section": "mctrctl.CORSWAPINH", + "text": "CSR mctrctl field CORSWAPINH (bits=44) When set, it inhibits recording of co-routine swaps. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_7fe2610d", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smctr/mctrctl.yaml", + "section": "mctrctl.RETINH", + "text": "CSR mctrctl field RETINH (bits=45) When set, it inhibits recording of function returns. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_a351368c", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smctr/mctrctl.yaml", + "section": "mctrctl.INDLJMPINH", + "text": "CSR mctrctl field INDLJMPINH (bits=46) When set, it inhibits recording of other indirect jumps (with linkage). type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_c6ccf5ce", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smctr/mctrctl.yaml", + "section": "mctrctl.DIRLJMPINH", + "text": "CSR mctrctl field DIRLJMPINH (bits=47) When set, it inhibits recording of other direct jumps (with linkage). type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_b16e2473", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smctr/mctrctl.yaml", + "section": "mctrctl.CUSTOM", + "text": "CSR mctrctl field CUSTOM (bits=63-60) WARL bits designated for custom use. The value 0 must correspond to standard behavior. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_3cd2265d", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smctr/sctrctl.yaml", + "section": "sctrctl", + "text": "CSR sctrctl (address=334, priv=S): The `sctrctl` register enables and configures the Control Transfer Records capability in S mode.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Smctr" + }, + { + "chunk_id": "chunk_6e91c487", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smctr/sctrctl.yaml", + "section": "sctrctl.U", + "text": "CSR sctrctl field U (bits=rv32=? rv64=?) Enable transfer recording in the User mode. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_51d44952", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smctr/sctrctl.yaml", + "section": "sctrctl.S", + "text": "CSR sctrctl field S (bits=1) Enable transfer recording in the Supervisor mode. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_22e04cec", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smctr/sctrctl.yaml", + "section": "sctrctl.RASEMU", + "text": "CSR sctrctl field RASEMU (bits=7) When set, it enables RAS (Return Address Stack) Emulation Mode. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_8eb49f55", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smctr/sctrctl.yaml", + "section": "sctrctl.STE", + "text": "CSR sctrctl field STE (bits=8) Enables recording of traps to S-mode when S=0. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_cf905773", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smctr/sctrctl.yaml", + "section": "sctrctl.BPFRZ", + "text": "CSR sctrctl field BPFRZ (bits=11) Set `sctrstatus.FROZEN` on a breakpoint exception that traps to M or S mode. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_9b34a7e3", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smctr/sctrctl.yaml", + "section": "sctrctl.LCOFIFRZ", + "text": "CSR sctrctl field LCOFIFRZ (bits=12) Set `sctrstatus.FROZEN` on local-counter-overflow interrupt (LCOFI) that traps\nto M or S mode. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d96f4888", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smctr/sctrctl.yaml", + "section": "sctrctl.EXCINH", + "text": "CSR sctrctl field EXCINH (bits=33) When set, it inhibits recording of exceptions. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_1fea4273", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smctr/sctrctl.yaml", + "section": "sctrctl.INTRINH", + "text": "CSR sctrctl field INTRINH (bits=34) When set, it inhibits recording of interrupts. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_9c56ddda", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smctr/sctrctl.yaml", + "section": "sctrctl.TRETINH", + "text": "CSR sctrctl field TRETINH (bits=35) When set, it inhibits recording of trap returns. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ca105ebf", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smctr/sctrctl.yaml", + "section": "sctrctl.NTBREN", + "text": "CSR sctrctl field NTBREN (bits=36) When set, it enables recording of not-taken branches. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_940d7836", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smctr/sctrctl.yaml", + "section": "sctrctl.TKBRINH", + "text": "CSR sctrctl field TKBRINH (bits=37) When set, it inhibits recording of taken branches. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_add05b81", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smctr/sctrctl.yaml", + "section": "sctrctl.INDCALLINH", + "text": "CSR sctrctl field INDCALLINH (bits=40) When set, it inhibits recording of indirect calls. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_8340692e", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smctr/sctrctl.yaml", + "section": "sctrctl.DIRCALLINH", + "text": "CSR sctrctl field DIRCALLINH (bits=41) When set, it inhibits recording of direct calls. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_7da3efd9", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smctr/sctrctl.yaml", + "section": "sctrctl.INDJMPINH", + "text": "CSR sctrctl field INDJMPINH (bits=42) When set, it inhibits recording of indirect jumps (without linkage). type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_b7e7162d", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smctr/sctrctl.yaml", + "section": "sctrctl.DIRJMPINH", + "text": "CSR sctrctl field DIRJMPINH (bits=43) When set, it inhibits recording of direct jumps (without linkage). type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_fa0c87e8", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smctr/sctrctl.yaml", + "section": "sctrctl.CORSWAPINH", + "text": "CSR sctrctl field CORSWAPINH (bits=44) When set, it inhibits recording of co-routine swaps. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_59b16547", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smctr/sctrctl.yaml", + "section": "sctrctl.RETINH", + "text": "CSR sctrctl field RETINH (bits=45) When set, it inhibits recording of function returns. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_57f64bba", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smctr/sctrctl.yaml", + "section": "sctrctl.INDLJMPINH", + "text": "CSR sctrctl field INDLJMPINH (bits=46) When set, it inhibits recording of other indirect jumps (with linkage). type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_189385d2", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smctr/sctrctl.yaml", + "section": "sctrctl.DIRLJMPINH", + "text": "CSR sctrctl field DIRLJMPINH (bits=47) When set, it inhibits recording of other direct jumps (with linkage). type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_c304ee7d", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smctr/sctrctl.yaml", + "section": "sctrctl.CUSTOM", + "text": "CSR sctrctl field CUSTOM (bits=63-60) WARL bits designated for custom use. The value 0 must correspond to standard behavior. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_bb1c7a36", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smctr/vsctrctl.yaml", + "section": "vsctrctl", + "text": "CSR vsctrctl (address=590, priv=VS): The `vsctrctl` register is a VS-mode's version of supervisor register `sctrctl` that\nconfigures the Control Transfer Records capability. When `V=1`, vsctrctl substitutes\nfor the usual `sctrctl`, so instructions that normally read or modify `sctrctl` actually\naccess `vsctrctl` instead.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Smctr" + }, + { + "chunk_id": "chunk_42f41500", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smctr/vsctrctl.yaml", + "section": "vsctrctl.U", + "text": "CSR vsctrctl field U (bits=rv32=? rv64=?) Enable transfer recording in the VU mode. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_b75bcd09", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smctr/vsctrctl.yaml", + "section": "vsctrctl.S", + "text": "CSR vsctrctl field S (bits=1) Enable transfer recording in the VS mode. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_2eab72b9", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smctr/vsctrctl.yaml", + "section": "vsctrctl.RASEMU", + "text": "CSR vsctrctl field RASEMU (bits=7) When set, it enables RAS (Return Address Stack) Emulation Mode. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_6bf74489", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smctr/vsctrctl.yaml", + "section": "vsctrctl.STE", + "text": "CSR vsctrctl field STE (bits=8) Enables recording of traps to VS-mode when S=0. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d010ea1e", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smctr/vsctrctl.yaml", + "section": "vsctrctl.BPFRZ", + "text": "CSR vsctrctl field BPFRZ (bits=11) Set `sctrstatus.FROZEN` on a breakpoint exception that traps to VS mode. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_693f6762", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smctr/vsctrctl.yaml", + "section": "vsctrctl.LCOFIFRZ", + "text": "CSR vsctrctl field LCOFIFRZ (bits=12) Set `sctrstatus.FROZEN` on local-counter-overflow interrupt (LCOFI) that traps to VS mode. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_79e12057", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smctr/vsctrctl.yaml", + "section": "vsctrctl.EXCINH", + "text": "CSR vsctrctl field EXCINH (bits=33) When set, it inhibits recording of exceptions. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_c046f719", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smctr/vsctrctl.yaml", + "section": "vsctrctl.INTRINH", + "text": "CSR vsctrctl field INTRINH (bits=34) When set, it inhibits recording of interrupts. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_fef71ab0", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smctr/vsctrctl.yaml", + "section": "vsctrctl.TRETINH", + "text": "CSR vsctrctl field TRETINH (bits=35) When set, it inhibits recording of trap returns. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_458bf558", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smctr/vsctrctl.yaml", + "section": "vsctrctl.NTBREN", + "text": "CSR vsctrctl field NTBREN (bits=36) When set, it enables recording of not-taken branches. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d05c3eb1", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smctr/vsctrctl.yaml", + "section": "vsctrctl.TKBRINH", + "text": "CSR vsctrctl field TKBRINH (bits=37) When set, it inhibits recording of taken branches. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_0486fe37", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smctr/vsctrctl.yaml", + "section": "vsctrctl.INDCALLINH", + "text": "CSR vsctrctl field INDCALLINH (bits=40) When set, it inhibits recording of indirect calls. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_277a1b3e", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smctr/vsctrctl.yaml", + "section": "vsctrctl.DIRCALLINH", + "text": "CSR vsctrctl field DIRCALLINH (bits=41) When set, it inhibits recording of direct calls. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ab3dc8ba", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smctr/vsctrctl.yaml", + "section": "vsctrctl.INDJMPINH", + "text": "CSR vsctrctl field INDJMPINH (bits=42) When set, it inhibits recording of indirect jumps (without linkage). type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_e8706b6d", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smctr/vsctrctl.yaml", + "section": "vsctrctl.DIRJMPINH", + "text": "CSR vsctrctl field DIRJMPINH (bits=43) When set, it inhibits recording of direct jumps (without linkage). type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_8fb87e1d", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smctr/vsctrctl.yaml", + "section": "vsctrctl.CORSWAPINH", + "text": "CSR vsctrctl field CORSWAPINH (bits=44) When set, it inhibits recording of co-routine swaps. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_9e7ee0f6", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smctr/vsctrctl.yaml", + "section": "vsctrctl.RETINH", + "text": "CSR vsctrctl field RETINH (bits=45) When set, it inhibits recording of function returns. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_264a3e2b", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smctr/vsctrctl.yaml", + "section": "vsctrctl.INDLJMPINH", + "text": "CSR vsctrctl field INDLJMPINH (bits=46) When set, it inhibits recording of other indirect jumps (with linkage). type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_6b28fd4b", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smctr/vsctrctl.yaml", + "section": "vsctrctl.DIRLJMPINH", + "text": "CSR vsctrctl field DIRLJMPINH (bits=47) When set, it inhibits recording of other direct jumps (with linkage). type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_3bbb8352", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smctr/vsctrctl.yaml", + "section": "vsctrctl.CUSTOM", + "text": "CSR vsctrctl field CUSTOM (bits=63-60) WARL bits designated for custom use. The value 0 must correspond to standard behavior. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_332e1a70", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smrnmi/mncause.yaml", + "section": "mncause", + "text": "CSR mncause (address=1858, priv=M): The mncause CSR holds the reason for the NMI.\nIf the reason is an interrupt, bit MXLEN-1 is set to 1, and the NMI cause is encoded in\nthe least-significant bits.\nIf the reason is an interrupt and NMI causes are not supported,\nbit MXLEN-1 is set to 1, and zero is written to the least-significant bits", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Smrnmi" + }, + { + "chunk_id": "chunk_b6b98a02", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smrnmi/mncause.yaml", + "section": "mncause.INT", + "text": "CSR mncause field INT (bits=rv32=31 rv64=63) Written by hardware when a resumable NMI is taken into M-mode.\n\nWhen set, the last non-maskable exception was caused by an asynchronous Interrupt.\n\n[when,\"TRAP_ON_ILLEGAL_WLRL == true\"]\nIf `mcause` is written with an undefined cause (combination of `mcause.INT` and `mcause.CODE`), an `Illegal Instru type: RW-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_917f430c", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smrnmi/mncause.yaml", + "section": "mncause.CODE", + "text": "CSR mncause field CODE (bits=rv32=30-0 rv64=62-0) TODO type: RW-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_f381afdb", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smrnmi/mnepc.yaml", + "section": "mnepc", + "text": "CSR mnepc (address=1857, priv=M): Written with the PC of an instruction on an exception or interrupt taken in M-mode.\n\nAlso controls where the hart jumps on an exception return from M-mode.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Smrnmi" + }, + { + "chunk_id": "chunk_bc149065", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smrnmi/mnepc.yaml", + "section": "mnepc.PC", + "text": "CSR mnepc field PC (bits=rv32=31-0 rv64=63-0) When a NMI / double trap is taken into M-mode, `mnepc.PC` is written with the virtual address of the\ninstruction that was interrupted or that encountered the exception.\nOtherwise, `mnepc.PC` is never written by the implementation, though it may be explicitly written\nby software.\n\nOn an exception ret type: RW-RH reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_b247fd16", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smrnmi/mnscratch.yaml", + "section": "mnscratch", + "text": "CSR mnscratch (address=1856, priv=M): Scratch register for software use in NMI / double trap. Bits are not\ninterpreted by hardware.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Smrnmi" + }, + { + "chunk_id": "chunk_7529dc95", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smrnmi/mnscratch.yaml", + "section": "mnscratch.SCRATCH", + "text": "CSR mnscratch field SCRATCH (bits=rv32=31-0 rv64=63-0) Scratch value type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_3da75a61", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smrnmi/mnstatus.yaml", + "section": "mnstatus", + "text": "CSR mnstatus (address=1860, priv=M): The mnstatus register tracks and controls the hart's current NMI operating state.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Smrnmi" + }, + { + "chunk_id": "chunk_bb0ec485", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smrnmi/mnstatus.yaml", + "section": "mnstatus.MNPP", + "text": "CSR mnstatus field MNPP (bits=12-11) M-mode NMI Previous Privilege.\n\nWritten by hardware in two cases:\n\n* Written with the prior nominal privilege level when entering M-mode NMI from an exception/interrupt.\n* Written with 0 when executing an `mnret` instruction to return from a double exception / NMI in M-mode.\n\nCan also be written by type: RW-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_53d1fb2d", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smrnmi/mnstatus.yaml", + "section": "mnstatus.MNPELP", + "text": "CSR mnstatus field MNPELP (bits=9) M-mode NMI Previous Expected Landing Pad state.\n\nDefined by the Zicfilp extension. Holds the previous\nExpected Landing Pad (ELP) state when entering M-mode NMI. type: RW-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_95073feb", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smrnmi/mnstatus.yaml", + "section": "mnstatus.MNPV", + "text": "CSR mnstatus field MNPV (bits=7) *Machine Previous NMI Virtualization mode*\n\nWritten with the prior virtualization mode when entering M-mode from an exception/interrupt.\nWhen returning via an MRET instruction, the virtualization mode becomes the value of MPV unless MPP=3, in which case the virtualization mode is always 0.\nCan also type: RW-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_e56cc4b3", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Smrnmi/mnstatus.yaml", + "section": "mnstatus.NMIE", + "text": "CSR mnstatus field NMIE (bits=3) *M-mode NMI Enable*\n\nWritten by hardware in two cases:\n\n* Written with the value 0 when entering M-mode NMI.\n* Written with the value 0 when entering M-mode double trap.\n\nWritten by software in one case only:\n\n* The NMIE is 0 on reset for boot code to initialize system to service NMIs. Once SW write type: RW-H", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ff462cd8", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Sscofpmf/scountovf.yaml", + "section": "scountovf", + "text": "CSR scountovf (address=3488, priv=S): A 32-bit read-only register that contains shadow copies of the OF bits in the 29 `mhpmevent` CSRs\n(`mhpmevent3` - `mhpmevent31`) — where `scountovf` bit X corresponds to `mhpmeventX`.\n\nThis register enables supervisor-level overflow interrupt handler\nsoftware to quickly and easily determine which co", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Sscofpmf" + }, + { + "chunk_id": "chunk_a202d3a2", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Sscofpmf/scountovf.yaml", + "section": "scountovf.OF3", + "text": "CSR scountovf field OF3 (bits=3) [when=\"HPM_COUNTER_EN[3] == true\"]\nShadow copy of mhpmevent3 overflow (OF) bit.\n\n[when=\"HPM_COUNTER_EN[3] == false\"]\nThis field is read-only zero because the counter is not enabled. type: return HPM_COUNTER_EN[3] ? CsrFieldType::RO : CsrFieldType::ROH; reset: return HPM_COUNTER_EN[3] ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_790549ba", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Sscofpmf/scountovf.yaml", + "section": "scountovf.OF4", + "text": "CSR scountovf field OF4 (bits=4) [when=\"HPM_COUNTER_EN[4] == true\"]\nShadow copy of mhpmevent4 overflow (OF) bit.\n\n[when=\"HPM_COUNTER_EN[4] == false\"]\nThis field is read-only zero because the counter is not enabled. type: return HPM_COUNTER_EN[4] ? CsrFieldType::RO : CsrFieldType::ROH; reset: return HPM_COUNTER_EN[4] ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_4779dd2a", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Sscofpmf/scountovf.yaml", + "section": "scountovf.OF5", + "text": "CSR scountovf field OF5 (bits=5) [when=\"HPM_COUNTER_EN[5] == true\"]\nShadow copy of mhpmevent5 overflow (OF) bit.\n\n[when=\"HPM_COUNTER_EN[5] == false\"]\nThis field is read-only zero because the counter is not enabled. type: return HPM_COUNTER_EN[5] ? CsrFieldType::RO : CsrFieldType::ROH; reset: return HPM_COUNTER_EN[5] ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_26de26e1", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Sscofpmf/scountovf.yaml", + "section": "scountovf.OF6", + "text": "CSR scountovf field OF6 (bits=6) [when=\"HPM_COUNTER_EN[6] == true\"]\nShadow copy of mhpmevent6 overflow (OF) bit.\n\n[when=\"HPM_COUNTER_EN[6] == false\"]\nThis field is read-only zero because the counter is not enabled. type: return HPM_COUNTER_EN[6] ? CsrFieldType::RO : CsrFieldType::ROH; reset: return HPM_COUNTER_EN[6] ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_3f91c805", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Sscofpmf/scountovf.yaml", + "section": "scountovf.OF7", + "text": "CSR scountovf field OF7 (bits=7) [when=\"HPM_COUNTER_EN[7] == true\"]\nShadow copy of mhpmevent7 overflow (OF) bit.\n\n[when=\"HPM_COUNTER_EN[7] == false\"]\nThis field is read-only zero because the counter is not enabled. type: return HPM_COUNTER_EN[7] ? CsrFieldType::RO : CsrFieldType::ROH; reset: return HPM_COUNTER_EN[7] ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_384db2ab", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Sscofpmf/scountovf.yaml", + "section": "scountovf.OF8", + "text": "CSR scountovf field OF8 (bits=8) [when=\"HPM_COUNTER_EN[8] == true\"]\nShadow copy of mhpmevent8 overflow (OF) bit.\n\n[when=\"HPM_COUNTER_EN[8] == false\"]\nThis field is read-only zero because the counter is not enabled. type: return HPM_COUNTER_EN[8] ? CsrFieldType::RO : CsrFieldType::ROH; reset: return HPM_COUNTER_EN[8] ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_76668680", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Sscofpmf/scountovf.yaml", + "section": "scountovf.OF9", + "text": "CSR scountovf field OF9 (bits=9) [when=\"HPM_COUNTER_EN[9] == true\"]\nShadow copy of mhpmevent9 overflow (OF) bit.\n\n[when=\"HPM_COUNTER_EN[9] == false\"]\nThis field is read-only zero because the counter is not enabled. type: return HPM_COUNTER_EN[9] ? CsrFieldType::RO : CsrFieldType::ROH; reset: return HPM_COUNTER_EN[9] ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_35c911f4", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Sscofpmf/scountovf.yaml", + "section": "scountovf.OF10", + "text": "CSR scountovf field OF10 (bits=10) [when=\"HPM_COUNTER_EN[10] == true\"]\nShadow copy of mhpmevent10 overflow (OF) bit.\n\n[when=\"HPM_COUNTER_EN[10] == false\"]\nThis field is read-only zero because the counter is not enabled. type: return HPM_COUNTER_EN[10] ? CsrFieldType::RO : CsrFieldType::ROH; reset: return HPM_COUNTER_EN[10] ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_17ef4621", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Sscofpmf/scountovf.yaml", + "section": "scountovf.OF11", + "text": "CSR scountovf field OF11 (bits=11) [when=\"HPM_COUNTER_EN[11] == true\"]\nShadow copy of mhpmevent11 overflow (OF) bit.\n\n[when=\"HPM_COUNTER_EN[11] == false\"]\nThis field is read-only zero because the counter is not enabled. type: return HPM_COUNTER_EN[11] ? CsrFieldType::RO : CsrFieldType::ROH; reset: return HPM_COUNTER_EN[11] ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_7df42e3e", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Sscofpmf/scountovf.yaml", + "section": "scountovf.OF12", + "text": "CSR scountovf field OF12 (bits=12) [when=\"HPM_COUNTER_EN[12] == true\"]\nShadow copy of mhpmevent12 overflow (OF) bit.\n\n[when=\"HPM_COUNTER_EN[12] == false\"]\nThis field is read-only zero because the counter is not enabled. type: return HPM_COUNTER_EN[12] ? CsrFieldType::RO : CsrFieldType::ROH; reset: return HPM_COUNTER_EN[12] ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_c3a03d1a", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Sscofpmf/scountovf.yaml", + "section": "scountovf.OF13", + "text": "CSR scountovf field OF13 (bits=13) [when=\"HPM_COUNTER_EN[13] == true\"]\nShadow copy of mhpmevent13 overflow (OF) bit.\n\n[when=\"HPM_COUNTER_EN[13] == false\"]\nThis field is read-only zero because the counter is not enabled. type: return HPM_COUNTER_EN[13] ? CsrFieldType::RO : CsrFieldType::ROH; reset: return HPM_COUNTER_EN[13] ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_8fea2a05", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Sscofpmf/scountovf.yaml", + "section": "scountovf.OF14", + "text": "CSR scountovf field OF14 (bits=14) [when=\"HPM_COUNTER_EN[14] == true\"]\nShadow copy of mhpmevent14 overflow (OF) bit.\n\n[when=\"HPM_COUNTER_EN[14] == false\"]\nThis field is read-only zero because the counter is not enabled. type: return HPM_COUNTER_EN[14] ? CsrFieldType::RO : CsrFieldType::ROH; reset: return HPM_COUNTER_EN[14] ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_446e28ac", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Sscofpmf/scountovf.yaml", + "section": "scountovf.OF15", + "text": "CSR scountovf field OF15 (bits=15) [when=\"HPM_COUNTER_EN[15] == true\"]\nShadow copy of mhpmevent15 overflow (OF) bit.\n\n[when=\"HPM_COUNTER_EN[15] == false\"]\nThis field is read-only zero because the counter is not enabled. type: return HPM_COUNTER_EN[15] ? CsrFieldType::RO : CsrFieldType::ROH; reset: return HPM_COUNTER_EN[15] ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_57e86ddf", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Sscofpmf/scountovf.yaml", + "section": "scountovf.OF16", + "text": "CSR scountovf field OF16 (bits=16) [when=\"HPM_COUNTER_EN[16] == true\"]\nShadow copy of mhpmevent16 overflow (OF) bit.\n\n[when=\"HPM_COUNTER_EN[16] == false\"]\nThis field is read-only zero because the counter is not enabled. type: return HPM_COUNTER_EN[16] ? CsrFieldType::RO : CsrFieldType::ROH; reset: return HPM_COUNTER_EN[16] ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_15adc949", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Sscofpmf/scountovf.yaml", + "section": "scountovf.OF17", + "text": "CSR scountovf field OF17 (bits=17) [when=\"HPM_COUNTER_EN[17] == true\"]\nShadow copy of mhpmevent17 overflow (OF) bit.\n\n[when=\"HPM_COUNTER_EN[17] == false\"]\nThis field is read-only zero because the counter is not enabled. type: return HPM_COUNTER_EN[17] ? CsrFieldType::RO : CsrFieldType::ROH; reset: return HPM_COUNTER_EN[17] ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_c170a6b2", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Sscofpmf/scountovf.yaml", + "section": "scountovf.OF18", + "text": "CSR scountovf field OF18 (bits=18) [when=\"HPM_COUNTER_EN[18] == true\"]\nShadow copy of mhpmevent18 overflow (OF) bit.\n\n[when=\"HPM_COUNTER_EN[18] == false\"]\nThis field is read-only zero because the counter is not enabled. type: return HPM_COUNTER_EN[18] ? CsrFieldType::RO : CsrFieldType::ROH; reset: return HPM_COUNTER_EN[18] ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_210bd4ae", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Sscofpmf/scountovf.yaml", + "section": "scountovf.OF19", + "text": "CSR scountovf field OF19 (bits=19) [when=\"HPM_COUNTER_EN[19] == true\"]\nShadow copy of mhpmevent19 overflow (OF) bit.\n\n[when=\"HPM_COUNTER_EN[19] == false\"]\nThis field is read-only zero because the counter is not enabled. type: return HPM_COUNTER_EN[19] ? CsrFieldType::RO : CsrFieldType::ROH; reset: return HPM_COUNTER_EN[19] ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_a050d4b1", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Sscofpmf/scountovf.yaml", + "section": "scountovf.OF20", + "text": "CSR scountovf field OF20 (bits=20) [when=\"HPM_COUNTER_EN[20] == true\"]\nShadow copy of mhpmevent20 overflow (OF) bit.\n\n[when=\"HPM_COUNTER_EN[20] == false\"]\nThis field is read-only zero because the counter is not enabled. type: return HPM_COUNTER_EN[20] ? CsrFieldType::RO : CsrFieldType::ROH; reset: return HPM_COUNTER_EN[20] ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_1e38021f", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Sscofpmf/scountovf.yaml", + "section": "scountovf.OF21", + "text": "CSR scountovf field OF21 (bits=21) [when=\"HPM_COUNTER_EN[21] == true\"]\nShadow copy of mhpmevent21 overflow (OF) bit.\n\n[when=\"HPM_COUNTER_EN[21] == false\"]\nThis field is read-only zero because the counter is not enabled. type: return HPM_COUNTER_EN[21] ? CsrFieldType::RO : CsrFieldType::ROH; reset: return HPM_COUNTER_EN[21] ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_c223aa3d", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Sscofpmf/scountovf.yaml", + "section": "scountovf.OF22", + "text": "CSR scountovf field OF22 (bits=22) [when=\"HPM_COUNTER_EN[22] == true\"]\nShadow copy of mhpmevent22 overflow (OF) bit.\n\n[when=\"HPM_COUNTER_EN[22] == false\"]\nThis field is read-only zero because the counter is not enabled. type: return HPM_COUNTER_EN[22] ? CsrFieldType::RO : CsrFieldType::ROH; reset: return HPM_COUNTER_EN[22] ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_36dcca71", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Sscofpmf/scountovf.yaml", + "section": "scountovf.OF23", + "text": "CSR scountovf field OF23 (bits=23) [when=\"HPM_COUNTER_EN[23] == true\"]\nShadow copy of mhpmevent23 overflow (OF) bit.\n\n[when=\"HPM_COUNTER_EN[23] == false\"]\nThis field is read-only zero because the counter is not enabled. type: return HPM_COUNTER_EN[23] ? CsrFieldType::RO : CsrFieldType::ROH; reset: return HPM_COUNTER_EN[23] ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_bf8aa6b6", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Sscofpmf/scountovf.yaml", + "section": "scountovf.OF24", + "text": "CSR scountovf field OF24 (bits=24) [when=\"HPM_COUNTER_EN[24] == true\"]\nShadow copy of mhpmevent24 overflow (OF) bit.\n\n[when=\"HPM_COUNTER_EN[24] == false\"]\nThis field is read-only zero because the counter is not enabled. type: return HPM_COUNTER_EN[24] ? CsrFieldType::RO : CsrFieldType::ROH; reset: return HPM_COUNTER_EN[24] ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_586ac962", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Sscofpmf/scountovf.yaml", + "section": "scountovf.OF25", + "text": "CSR scountovf field OF25 (bits=25) [when=\"HPM_COUNTER_EN[25] == true\"]\nShadow copy of mhpmevent25 overflow (OF) bit.\n\n[when=\"HPM_COUNTER_EN[25] == false\"]\nThis field is read-only zero because the counter is not enabled. type: return HPM_COUNTER_EN[25] ? CsrFieldType::RO : CsrFieldType::ROH; reset: return HPM_COUNTER_EN[25] ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_14992942", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Sscofpmf/scountovf.yaml", + "section": "scountovf.OF26", + "text": "CSR scountovf field OF26 (bits=26) [when=\"HPM_COUNTER_EN[26] == true\"]\nShadow copy of mhpmevent26 overflow (OF) bit.\n\n[when=\"HPM_COUNTER_EN[26] == false\"]\nThis field is read-only zero because the counter is not enabled. type: return HPM_COUNTER_EN[26] ? CsrFieldType::RO : CsrFieldType::ROH; reset: return HPM_COUNTER_EN[26] ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_21e564f1", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Sscofpmf/scountovf.yaml", + "section": "scountovf.OF27", + "text": "CSR scountovf field OF27 (bits=27) [when=\"HPM_COUNTER_EN[27] == true\"]\nShadow copy of mhpmevent27 overflow (OF) bit.\n\n[when=\"HPM_COUNTER_EN[27] == false\"]\nThis field is read-only zero because the counter is not enabled. type: return HPM_COUNTER_EN[27] ? CsrFieldType::RO : CsrFieldType::ROH; reset: return HPM_COUNTER_EN[27] ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_354626c6", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Sscofpmf/scountovf.yaml", + "section": "scountovf.OF28", + "text": "CSR scountovf field OF28 (bits=28) [when=\"HPM_COUNTER_EN[28] == true\"]\nShadow copy of mhpmevent28 overflow (OF) bit.\n\n[when=\"HPM_COUNTER_EN[28] == false\"]\nThis field is read-only zero because the counter is not enabled. type: return HPM_COUNTER_EN[28] ? CsrFieldType::RO : CsrFieldType::ROH; reset: return HPM_COUNTER_EN[28] ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_77110020", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Sscofpmf/scountovf.yaml", + "section": "scountovf.OF29", + "text": "CSR scountovf field OF29 (bits=29) [when=\"HPM_COUNTER_EN[29] == true\"]\nShadow copy of mhpmevent29 overflow (OF) bit.\n\n[when=\"HPM_COUNTER_EN[29] == false\"]\nThis field is read-only zero because the counter is not enabled. type: return HPM_COUNTER_EN[29] ? CsrFieldType::RO : CsrFieldType::ROH; reset: return HPM_COUNTER_EN[29] ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_8326a4b0", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Sscofpmf/scountovf.yaml", + "section": "scountovf.OF30", + "text": "CSR scountovf field OF30 (bits=30) [when=\"HPM_COUNTER_EN[30] == true\"]\nShadow copy of mhpmevent30 overflow (OF) bit.\n\n[when=\"HPM_COUNTER_EN[30] == false\"]\nThis field is read-only zero because the counter is not enabled. type: return HPM_COUNTER_EN[30] ? CsrFieldType::RO : CsrFieldType::ROH; reset: return HPM_COUNTER_EN[30] ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_76ec40bb", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Sscofpmf/scountovf.yaml", + "section": "scountovf.OF31", + "text": "CSR scountovf field OF31 (bits=31) [when=\"HPM_COUNTER_EN[31] == true\"]\nShadow copy of mhpmevent31 overflow (OF) bit.\n\n[when=\"HPM_COUNTER_EN[31] == false\"]\nThis field is read-only zero because the counter is not enabled. type: return HPM_COUNTER_EN[31] ? CsrFieldType::RO : CsrFieldType::ROH; reset: return HPM_COUNTER_EN[31] ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_294803c3", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Ssqosid/srmcfg.yaml", + "section": "srmcfg", + "text": "CSR srmcfg (address=385, priv=S): The `srmcfg` register is used to configure a Resource Control ID (`RCID`) and a Monitoring Counter ID (`MCID`).\nBoth `RCID` and `MCID` are WARL fields.\n\nThe `RCID` and `MCID` accompany each request made by the hart to shared resource controllers.\nThe `RCID` is used to determine the resource allocati", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Ssqosid" + }, + { + "chunk_id": "chunk_abbc63e2", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Ssqosid/srmcfg.yaml", + "section": "srmcfg.RCID", + "text": "CSR srmcfg field RCID (bits=11-0) The `RCID` is used to determine the resource allocations (e.g., cache occupancy limits,\nmemory bandwidth limits, etc.) to enforce. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_597591a9", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Ssqosid/srmcfg.yaml", + "section": "srmcfg.MCID", + "text": "CSR srmcfg field MCID (bits=27-16) The `MCID` is used to identify a counter to monitor resource usage. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_aea00992", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/V/vcsr.yaml", + "section": "vcsr", + "text": "CSR vcsr (address=15, priv=U): Contains aliases to vxrm and vxsat CSRs", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Zvl32b" + }, + { + "chunk_id": "chunk_4fd99be6", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/V/vcsr.yaml", + "section": "vcsr.VXRM", + "text": "CSR vcsr field VXRM (bits=2-1) See vxrm. type: RW-RH reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_8b19b0c8", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/V/vcsr.yaml", + "section": "vcsr.VXSAT", + "text": "CSR vcsr field VXSAT (bits=rv32=? rv64=?) See vxsat. type: RW-RH reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_f28d9a24", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/V/vl.yaml", + "section": "vl", + "text": "CSR vl (address=3104, priv=U): Holds an unsigned integer specifying number of elements to be updated with results from a vector instruction.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Zvl32b" + }, + { + "chunk_id": "chunk_41388ada", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/V/vl.yaml", + "section": "vl.VALUE", + "text": "CSR vl field VALUE (bits=rv32=31-0 rv64=63-0) The vl register holds an unsigned integer specifying the number of elements to be updated with\nresults from a vector instruction, as further detailed in Section Section 31.5.4.\n\n[NOTE]\nThe number of bits implemented in vl depends on the implementation's maximum vector\nlength of the smallest supporte type: RO-H reset: return (FOLLOW_VTYPE_RESET_RECOMMENDATION)? 0 : UNDEFINED_LEGAL;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_c98d9b6b", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/V/vlenb.yaml", + "section": "vlenb", + "text": "CSR vlenb (address=3106, priv=U): Holds the value VLEN/8, the vector register length in bytes.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Zvl32b" + }, + { + "chunk_id": "chunk_6164b0a8", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/V/vlenb.yaml", + "section": "vlenb.VALUE", + "text": "CSR vlenb field VALUE (bits=rv32=31-0 rv64=63-0) The value in vlenb is a design-time constant in any implementation.\nWithout this CSR, several instructions are needed to calculate VLEN in bytes, and the code\nhas to disturb current vl and vtype settings which require them to be saved and restored. type: RO reset: return VLEN / 8;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_1a0cb0a8", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/V/vstart.yaml", + "section": "vstart", + "text": "CSR vstart (address=8, priv=U): Specifies the index of the first element to be executed by a vector instruction.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Zvl32b" + }, + { + "chunk_id": "chunk_c2eaaf0d", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/V/vstart.yaml", + "section": "vstart.VALUE", + "text": "CSR vstart field VALUE (bits=rv32=31-0 rv64=63-0) Normally, vstart is only written by hardware on a trap on a vector instruction, with the vstart value\nrepresenting the element on which the trap was taken (either a synchronous exception or an\nasynchronous interrupt), and at which execution should resume after a resumable trap is handled.\nAll vector type: RW-RH reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_3728fa73", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/V/vtype.yaml", + "section": "vtype", + "text": "CSR vtype (address=3105, priv=U): Provides the default type used to interpret the contents of the vector register file.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Zvl32b" + }, + { + "chunk_id": "chunk_1a00826f", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/V/vtype.yaml", + "section": "vtype.VILL", + "text": "CSR vtype field VILL (bits=rv32=31 rv64=63) The vill bit is used to encode that a previous vset{i}vl{i} instruction attempted to write an\nunsupported value to vtype.\n\n[NOTE]\nThe vill bit is held in bit XLEN-1 of the CSR to support checking for illegal values with a\nbranch on the sign bit.\n\nIf the vill bit is set, then any attempt to execute a type: RO-H reset: return (FOLLOW_VTYPE_RESET_RECOMMENDATION)? 1 : UNDEFINED_LEGAL;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_f4e0ac6d", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/V/vtype.yaml", + "section": "vtype.VMA", + "text": "CSR vtype field VMA (bits=7) Vector mask agnostic bit. Modifies the behavior of destination inactive masked-off elements during the\nexecution of vector instructions.\n\nA value of 0 means inactive elements are undisturbed, meaning the corresponding set of destination elements\nin a vector register group retain the value they previ type: RO-H reset: return (FOLLOW_VTYPE_RESET_RECOMMENDATION)? 0 : UNDEFINED_LEGAL;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d029e4dd", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/V/vtype.yaml", + "section": "vtype.VTA", + "text": "CSR vtype field VTA (bits=6) Vector tail agnostic bit. Modifies the bahavior of destination tail elements during the execution of vector\ninstructions.\n\nA value of 0 means tail elements are undisturbed, meaning the corresponding set of destination elements\nin a vector register group retain the value they previously held.\n\nA valu type: RO-H reset: return (FOLLOW_VTYPE_RESET_RECOMMENDATION)? 0 : UNDEFINED_LEGAL;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ccd5a638", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/V/vtype.yaml", + "section": "vtype.VSEW", + "text": "CSR vtype field VSEW (bits=5-3) The value in vsew sets the dynamic selected element width (SEW).\n\n[separator=\"!\"]\n!===\n! vsew[2:0] ! SEW ! Elements per vector register\n! 000 ! 8 ! 16\n! 001 ! 16 ! 8\n! 010 ! 32 ! 4\n! 011 ! 64 ! 2\n! 1XX ! Reserved ! Reserved\n!===\n\nIt is recommended that at reset, vill is set, and the remaining bits i type: RO-H reset: return (FOLLOW_VTYPE_RESET_RECOMMENDATION)? 0 : UNDEFINED_LEGAL;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_a6fcf14b", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/V/vtype.yaml", + "section": "vtype.VLMUL", + "text": "CSR vtype field VLMUL (bits=2-0) Vector register group multiplier.\n\nMultiple vector registers can be grouped together, so that a single vector instruction can operate on\nmultiple vector registers. The term vector register group is used herein to refer to one or more vector\nregisters used as a single operand to a vector instruction. type: RO-H reset: return (FOLLOW_VTYPE_RESET_RECOMMENDATION)? 0 : UNDEFINED_LEGAL;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_13724bbf", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/V/vxrm.yaml", + "section": "vxrm", + "text": "CSR vxrm (address=10, priv=U): Holds a 2-bit read-write rounding-mode field in the least-significant bits", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Zvl32b" + }, + { + "chunk_id": "chunk_3e1af2c3", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/V/vxrm.yaml", + "section": "vxrm.VALUE", + "text": "CSR vxrm field VALUE (bits=rv32=31-0 rv64=63-0) The vector fixed-point rounding-mode register holds a two-bit read-write rounding-mode field in the\nleast-significant bits (vxrm[1:0]). The upper bits, vxrm[XLEN-1:2], should be written as zeros.\nThe vector fixed-point rounding-mode is given a separate CSR address to allow independent access,\nbut is type: RW-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_20e3f095", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/V/vxsat.yaml", + "section": "vxsat", + "text": "CSR vxsat (address=9, priv=U): Indicates if a fixed-point instruction has had to saturate an output value to fit into a destination format", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Zvl32b" + }, + { + "chunk_id": "chunk_5547e72a", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/V/vxsat.yaml", + "section": "vxsat.VALUE", + "text": "CSR vxsat field VALUE (bits=rv32=31-0 rv64=63-0) The vxsat CSR has a single read-write least-significant bit (vxsat[0]) that indicates if a fixed-point\ninstruction has had to saturate an output value to fit into a destination format. Bits vxsat[XLEN-1:1]\nshould be written as zeros.\n\nThe vxsat bit is mirrored in vcsr. type: RW-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ee449a26", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zicntr/mcountinhibit.yaml", + "section": "mcountinhibit", + "text": "CSR mcountinhibit (address=800, priv=M): Bits to inhibit (stops counting) performance counters.\n\nThe counter-inhibit register `mcountinhibit` is a *WARL* register that\ncontrols which of the hardware performance-monitoring counters\nincrement. The settings in this register only control whether the\ncounters increment; their accessibility is n", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Sm" + }, + { + "chunk_id": "chunk_20f8a0db", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zicntr/mcountinhibit.yaml", + "section": "mcountinhibit.CY", + "text": "CSR mcountinhibit field CY (bits=rv32=? rv64=?) When set, `mcycle.COUNT` stops counting in all privilege modes. type: return COUNTINHIBIT_EN[0] ? CsrFieldType::RW : CsrFieldType::RO; reset: return COUNTINHIBIT_EN[0] ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ae1e6210", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zicntr/mcountinhibit.yaml", + "section": "mcountinhibit.IR", + "text": "CSR mcountinhibit field IR (bits=2) When set, `minstret.COUNT` stops counting in all privilege modes. type: return COUNTINHIBIT_EN[2] ? CsrFieldType::RW : CsrFieldType::RO; reset: return COUNTINHIBIT_EN[2] ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_3b30f4c4", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zicntr/mcountinhibit.yaml", + "section": "mcountinhibit.HPM3", + "text": "CSR mcountinhibit field HPM3 (bits=3) [when=\"COUNTINHIBIT_EN[3] == true\"]\nWhen set, `hpmcounter3.COUNT` stops counting in all privilege modes.\n\n[when=\"COUNTINHIBIT_EN[3] == false\"]\nSince hpmcounter3 is not implemented, this field is read-only zero. type: return COUNTINHIBIT_EN[3] ? CsrFieldType::RW : CsrFieldType::RO; reset: return COUNTINHIBIT_EN[3] ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_31f529d9", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zicntr/mcountinhibit.yaml", + "section": "mcountinhibit.HPM4", + "text": "CSR mcountinhibit field HPM4 (bits=4) [when=\"COUNTINHIBIT_EN[4] == true\"]\nWhen set, `hpmcounter4.COUNT` stops counting in all privilege modes.\n\n[when=\"COUNTINHIBIT_EN[4] == false\"]\nSince hpmcounter4 is not implemented, this field is read-only zero. type: return COUNTINHIBIT_EN[4] ? CsrFieldType::RW : CsrFieldType::RO; reset: return COUNTINHIBIT_EN[4] ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_c13a529c", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zicntr/mcountinhibit.yaml", + "section": "mcountinhibit.HPM5", + "text": "CSR mcountinhibit field HPM5 (bits=5) [when=\"COUNTINHIBIT_EN[5] == true\"]\nWhen set, `hpmcounter5.COUNT` stops counting in all privilege modes.\n\n[when=\"COUNTINHIBIT_EN[5] == false\"]\nSince hpmcounter5 is not implemented, this field is read-only zero. type: return COUNTINHIBIT_EN[5] ? CsrFieldType::RW : CsrFieldType::RO; reset: return COUNTINHIBIT_EN[5] ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_c1e04720", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zicntr/mcountinhibit.yaml", + "section": "mcountinhibit.HPM6", + "text": "CSR mcountinhibit field HPM6 (bits=6) [when=\"COUNTINHIBIT_EN[6] == true\"]\nWhen set, `hpmcounter6.COUNT` stops counting in all privilege modes.\n\n[when=\"COUNTINHIBIT_EN[6] == false\"]\nSince hpmcounter6 is not implemented, this field is read-only zero. type: return COUNTINHIBIT_EN[6] ? CsrFieldType::RW : CsrFieldType::RO; reset: return COUNTINHIBIT_EN[6] ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_acddd113", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zicntr/mcountinhibit.yaml", + "section": "mcountinhibit.HPM7", + "text": "CSR mcountinhibit field HPM7 (bits=7) [when=\"COUNTINHIBIT_EN[7] == true\"]\nWhen set, `hpmcounter7.COUNT` stops counting in all privilege modes.\n\n[when=\"COUNTINHIBIT_EN[7] == false\"]\nSince hpmcounter7 is not implemented, this field is read-only zero. type: return COUNTINHIBIT_EN[7] ? CsrFieldType::RW : CsrFieldType::RO; reset: return COUNTINHIBIT_EN[7] ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_8474532a", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zicntr/mcountinhibit.yaml", + "section": "mcountinhibit.HPM8", + "text": "CSR mcountinhibit field HPM8 (bits=8) [when=\"COUNTINHIBIT_EN[8] == true\"]\nWhen set, `hpmcounter8.COUNT` stops counting in all privilege modes.\n\n[when=\"COUNTINHIBIT_EN[8] == false\"]\nSince hpmcounter8 is not implemented, this field is read-only zero. type: return COUNTINHIBIT_EN[8] ? CsrFieldType::RW : CsrFieldType::RO; reset: return COUNTINHIBIT_EN[8] ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_5ad38f5f", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zicntr/mcountinhibit.yaml", + "section": "mcountinhibit.HPM9", + "text": "CSR mcountinhibit field HPM9 (bits=9) [when=\"COUNTINHIBIT_EN[9] == true\"]\nWhen set, `hpmcounter9.COUNT` stops counting in all privilege modes.\n\n[when=\"COUNTINHIBIT_EN[9] == false\"]\nSince hpmcounter9 is not implemented, this field is read-only zero. type: return COUNTINHIBIT_EN[9] ? CsrFieldType::RW : CsrFieldType::RO; reset: return COUNTINHIBIT_EN[9] ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_8fd26d38", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zicntr/mcountinhibit.yaml", + "section": "mcountinhibit.HPM10", + "text": "CSR mcountinhibit field HPM10 (bits=10) [when=\"COUNTINHIBIT_EN[10] == true\"]\nWhen set, `hpmcounter10.COUNT` stops counting in all privilege modes.\n\n[when=\"COUNTINHIBIT_EN[10] == false\"]\nSince hpmcounter10 is not implemented, this field is read-only zero. type: return COUNTINHIBIT_EN[10] ? CsrFieldType::RW : CsrFieldType::RO; reset: return COUNTINHIBIT_EN[10] ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_b0d534de", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zicntr/mcountinhibit.yaml", + "section": "mcountinhibit.HPM11", + "text": "CSR mcountinhibit field HPM11 (bits=11) [when=\"COUNTINHIBIT_EN[11] == true\"]\nWhen set, `hpmcounter11.COUNT` stops counting in all privilege modes.\n\n[when=\"COUNTINHIBIT_EN[11] == false\"]\nSince hpmcounter11 is not implemented, this field is read-only zero. type: return COUNTINHIBIT_EN[11] ? CsrFieldType::RW : CsrFieldType::RO; reset: return COUNTINHIBIT_EN[11] ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_7bca7cc6", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zicntr/mcountinhibit.yaml", + "section": "mcountinhibit.HPM12", + "text": "CSR mcountinhibit field HPM12 (bits=12) [when=\"COUNTINHIBIT_EN[12] == true\"]\nWhen set, `hpmcounter12.COUNT` stops counting in all privilege modes.\n\n[when=\"COUNTINHIBIT_EN[12] == false\"]\nSince hpmcounter12 is not implemented, this field is read-only zero. type: return COUNTINHIBIT_EN[12] ? CsrFieldType::RW : CsrFieldType::RO; reset: return COUNTINHIBIT_EN[12] ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_2c62aa9c", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zicntr/mcountinhibit.yaml", + "section": "mcountinhibit.HPM13", + "text": "CSR mcountinhibit field HPM13 (bits=13) [when=\"COUNTINHIBIT_EN[13] == true\"]\nWhen set, `hpmcounter13.COUNT` stops counting in all privilege modes.\n\n[when=\"COUNTINHIBIT_EN[13] == false\"]\nSince hpmcounter13 is not implemented, this field is read-only zero. type: return COUNTINHIBIT_EN[13] ? CsrFieldType::RW : CsrFieldType::RO; reset: return COUNTINHIBIT_EN[13] ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_78c68302", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zicntr/mcountinhibit.yaml", + "section": "mcountinhibit.HPM14", + "text": "CSR mcountinhibit field HPM14 (bits=14) [when=\"COUNTINHIBIT_EN[14] == true\"]\nWhen set, `hpmcounter14.COUNT` stops counting in all privilege modes.\n\n[when=\"COUNTINHIBIT_EN[14] == false\"]\nSince hpmcounter14 is not implemented, this field is read-only zero. type: return COUNTINHIBIT_EN[14] ? CsrFieldType::RW : CsrFieldType::RO; reset: return COUNTINHIBIT_EN[14] ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_f5ecc5fc", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zicntr/mcountinhibit.yaml", + "section": "mcountinhibit.HPM15", + "text": "CSR mcountinhibit field HPM15 (bits=15) [when=\"COUNTINHIBIT_EN[15] == true\"]\nWhen set, `hpmcounter15.COUNT` stops counting in all privilege modes.\n\n[when=\"COUNTINHIBIT_EN[15] == false\"]\nSince hpmcounter15 is not implemented, this field is read-only zero. type: return COUNTINHIBIT_EN[15] ? CsrFieldType::RW : CsrFieldType::RO; reset: return COUNTINHIBIT_EN[15] ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_98a7c82b", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zicntr/mcountinhibit.yaml", + "section": "mcountinhibit.HPM16", + "text": "CSR mcountinhibit field HPM16 (bits=16) [when=\"COUNTINHIBIT_EN[16] == true\"]\nWhen set, `hpmcounter16.COUNT` stops counting in all privilege modes.\n\n[when=\"COUNTINHIBIT_EN[16] == false\"]\nSince hpmcounter16 is not implemented, this field is read-only zero. type: return COUNTINHIBIT_EN[16] ? CsrFieldType::RW : CsrFieldType::RO; reset: return COUNTINHIBIT_EN[16] ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_f11bbf5b", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zicntr/mcountinhibit.yaml", + "section": "mcountinhibit.HPM17", + "text": "CSR mcountinhibit field HPM17 (bits=17) [when=\"COUNTINHIBIT_EN[17] == true\"]\nWhen set, `hpmcounter17.COUNT` stops counting in all privilege modes.\n\n[when=\"COUNTINHIBIT_EN[17] == false\"]\nSince hpmcounter17 is not implemented, this field is read-only zero. type: return COUNTINHIBIT_EN[17] ? CsrFieldType::RW : CsrFieldType::RO; reset: return COUNTINHIBIT_EN[17] ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_7ca5a550", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zicntr/mcountinhibit.yaml", + "section": "mcountinhibit.HPM18", + "text": "CSR mcountinhibit field HPM18 (bits=18) [when=\"COUNTINHIBIT_EN[18] == true\"]\nWhen set, `hpmcounter18.COUNT` stops counting in all privilege modes.\n\n[when=\"COUNTINHIBIT_EN[18] == false\"]\nSince hpmcounter18 is not implemented, this field is read-only zero. type: return COUNTINHIBIT_EN[18] ? CsrFieldType::RW : CsrFieldType::RO; reset: return COUNTINHIBIT_EN[18] ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d93b0a2c", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zicntr/mcountinhibit.yaml", + "section": "mcountinhibit.HPM19", + "text": "CSR mcountinhibit field HPM19 (bits=19) [when=\"COUNTINHIBIT_EN[19] == true\"]\nWhen set, `hpmcounter19.COUNT` stops counting in all privilege modes.\n\n[when=\"COUNTINHIBIT_EN[19] == false\"]\nSince hpmcounter19 is not implemented, this field is read-only zero. type: return COUNTINHIBIT_EN[19] ? CsrFieldType::RW : CsrFieldType::RO; reset: return COUNTINHIBIT_EN[19] ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d9ad0a8c", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zicntr/mcountinhibit.yaml", + "section": "mcountinhibit.HPM20", + "text": "CSR mcountinhibit field HPM20 (bits=20) [when=\"COUNTINHIBIT_EN[20] == true\"]\nWhen set, `hpmcounter20.COUNT` stops counting in all privilege modes.\n\n[when=\"COUNTINHIBIT_EN[20] == false\"]\nSince hpmcounter20 is not implemented, this field is read-only zero. type: return COUNTINHIBIT_EN[20] ? CsrFieldType::RW : CsrFieldType::RO; reset: return COUNTINHIBIT_EN[20] ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_561ae305", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zicntr/mcountinhibit.yaml", + "section": "mcountinhibit.HPM21", + "text": "CSR mcountinhibit field HPM21 (bits=21) [when=\"COUNTINHIBIT_EN[21] == true\"]\nWhen set, `hpmcounter21.COUNT` stops counting in all privilege modes.\n\n[when=\"COUNTINHIBIT_EN[21] == false\"]\nSince hpmcounter21 is not implemented, this field is read-only zero. type: return COUNTINHIBIT_EN[21] ? CsrFieldType::RW : CsrFieldType::RO; reset: return COUNTINHIBIT_EN[21] ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_886f89dc", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zicntr/mcountinhibit.yaml", + "section": "mcountinhibit.HPM22", + "text": "CSR mcountinhibit field HPM22 (bits=22) [when=\"COUNTINHIBIT_EN[22] == true\"]\nWhen set, `hpmcounter22.COUNT` stops counting in all privilege modes.\n\n[when=\"COUNTINHIBIT_EN[22] == false\"]\nSince hpmcounter22 is not implemented, this field is read-only zero. type: return COUNTINHIBIT_EN[22] ? CsrFieldType::RW : CsrFieldType::RO; reset: return COUNTINHIBIT_EN[22] ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_e04bf860", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zicntr/mcountinhibit.yaml", + "section": "mcountinhibit.HPM23", + "text": "CSR mcountinhibit field HPM23 (bits=23) [when=\"COUNTINHIBIT_EN[23] == true\"]\nWhen set, `hpmcounter23.COUNT` stops counting in all privilege modes.\n\n[when=\"COUNTINHIBIT_EN[23] == false\"]\nSince hpmcounter23 is not implemented, this field is read-only zero. type: return COUNTINHIBIT_EN[23] ? CsrFieldType::RW : CsrFieldType::RO; reset: return COUNTINHIBIT_EN[23] ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_874d92b4", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zicntr/mcountinhibit.yaml", + "section": "mcountinhibit.HPM24", + "text": "CSR mcountinhibit field HPM24 (bits=24) [when=\"COUNTINHIBIT_EN[24] == true\"]\nWhen set, `hpmcounter24.COUNT` stops counting in all privilege modes.\n\n[when=\"COUNTINHIBIT_EN[24] == false\"]\nSince hpmcounter24 is not implemented, this field is read-only zero. type: return COUNTINHIBIT_EN[24] ? CsrFieldType::RW : CsrFieldType::RO; reset: return COUNTINHIBIT_EN[24] ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_97decd63", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zicntr/mcountinhibit.yaml", + "section": "mcountinhibit.HPM25", + "text": "CSR mcountinhibit field HPM25 (bits=25) [when=\"COUNTINHIBIT_EN[25] == true\"]\nWhen set, `hpmcounter25.COUNT` stops counting in all privilege modes.\n\n[when=\"COUNTINHIBIT_EN[25] == false\"]\nSince hpmcounter25 is not implemented, this field is read-only zero. type: return COUNTINHIBIT_EN[25] ? CsrFieldType::RW : CsrFieldType::RO; reset: return COUNTINHIBIT_EN[25] ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_321ad253", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zicntr/mcountinhibit.yaml", + "section": "mcountinhibit.HPM26", + "text": "CSR mcountinhibit field HPM26 (bits=26) [when=\"COUNTINHIBIT_EN[26] == true\"]\nWhen set, `hpmcounter26.COUNT` stops counting in all privilege modes.\n\n[when=\"COUNTINHIBIT_EN[26] == false\"]\nSince hpmcounter26 is not implemented, this field is read-only zero. type: return COUNTINHIBIT_EN[26] ? CsrFieldType::RW : CsrFieldType::RO; reset: return COUNTINHIBIT_EN[26] ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_55947744", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zicntr/mcountinhibit.yaml", + "section": "mcountinhibit.HPM27", + "text": "CSR mcountinhibit field HPM27 (bits=27) [when=\"COUNTINHIBIT_EN[27] == true\"]\nWhen set, `hpmcounter27.COUNT` stops counting in all privilege modes.\n\n[when=\"COUNTINHIBIT_EN[27] == false\"]\nSince hpmcounter27 is not implemented, this field is read-only zero. type: return COUNTINHIBIT_EN[27] ? CsrFieldType::RW : CsrFieldType::RO; reset: return COUNTINHIBIT_EN[27] ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_a9b130d0", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zicntr/mcountinhibit.yaml", + "section": "mcountinhibit.HPM28", + "text": "CSR mcountinhibit field HPM28 (bits=28) [when=\"COUNTINHIBIT_EN[28] == true\"]\nWhen set, `hpmcounter28.COUNT` stops counting in all privilege modes.\n\n[when=\"COUNTINHIBIT_EN[28] == false\"]\nSince hpmcounter28 is not implemented, this field is read-only zero. type: return COUNTINHIBIT_EN[28] ? CsrFieldType::RW : CsrFieldType::RO; reset: return COUNTINHIBIT_EN[28] ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ae92e284", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zicntr/mcountinhibit.yaml", + "section": "mcountinhibit.HPM29", + "text": "CSR mcountinhibit field HPM29 (bits=29) [when=\"COUNTINHIBIT_EN[29] == true\"]\nWhen set, `hpmcounter29.COUNT` stops counting in all privilege modes.\n\n[when=\"COUNTINHIBIT_EN[29] == false\"]\nSince hpmcounter29 is not implemented, this field is read-only zero. type: return COUNTINHIBIT_EN[29] ? CsrFieldType::RW : CsrFieldType::RO; reset: return COUNTINHIBIT_EN[29] ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_2d1ff5d2", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zicntr/mcountinhibit.yaml", + "section": "mcountinhibit.HPM30", + "text": "CSR mcountinhibit field HPM30 (bits=30) [when=\"COUNTINHIBIT_EN[30] == true\"]\nWhen set, `hpmcounter30.COUNT` stops counting in all privilege modes.\n\n[when=\"COUNTINHIBIT_EN[30] == false\"]\nSince hpmcounter30 is not implemented, this field is read-only zero. type: return COUNTINHIBIT_EN[30] ? CsrFieldType::RW : CsrFieldType::RO; reset: return COUNTINHIBIT_EN[30] ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_3bc1f3ad", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zicntr/mcountinhibit.yaml", + "section": "mcountinhibit.HPM31", + "text": "CSR mcountinhibit field HPM31 (bits=31) [when=\"COUNTINHIBIT_EN[31] == true\"]\nWhen set, `hpmcounter31.COUNT` stops counting in all privilege modes.\n\n[when=\"COUNTINHIBIT_EN[31] == false\"]\nSince hpmcounter31 is not implemented, this field is read-only zero. type: return COUNTINHIBIT_EN[31] ? CsrFieldType::RW : CsrFieldType::RO; reset: return COUNTINHIBIT_EN[31] ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_f7aa5a4c", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter10.yaml", + "section": "hpmcounter10", + "text": "CSR hpmcounter10 (address=3082, priv=U): Alias for M-mode CSR `mhpmcounter10`.\n\nSee `mhpmcounter10` for information on privilege mode access control.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Zihpm" + }, + { + "chunk_id": "chunk_a2cabc16", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter10.yaml", + "section": "hpmcounter10.COUNT", + "text": "CSR hpmcounter10 field COUNT (bits=63-0) Alias of `mhpmcounter10.COUNT`. type: RO-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_652f6ad9", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter10h.yaml", + "section": "hpmcounter10h", + "text": "CSR hpmcounter10h (address=3210, priv=U): Alias for M-mode CSR `mhpmcounter10h`.\n\nSee `mhpmcounter10h` for information on privilege mode access control.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_f1df7906", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter10h.yaml", + "section": "hpmcounter10h.COUNT", + "text": "CSR hpmcounter10h field COUNT (bits=31-0) Alias of `mhpmcounter10h.COUNT`. type: RO-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_13a339ed", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter11.yaml", + "section": "hpmcounter11", + "text": "CSR hpmcounter11 (address=3083, priv=U): Alias for M-mode CSR `mhpmcounter11`.\n\nSee `mhpmcounter11` for information on privilege mode access control.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Zihpm" + }, + { + "chunk_id": "chunk_eafc994c", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter11.yaml", + "section": "hpmcounter11.COUNT", + "text": "CSR hpmcounter11 field COUNT (bits=63-0) Alias of `mhpmcounter11.COUNT`. type: RO-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_e56a7fe9", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter11h.yaml", + "section": "hpmcounter11h", + "text": "CSR hpmcounter11h (address=3211, priv=U): Alias for M-mode CSR `mhpmcounter11h`.\n\nSee `mhpmcounter11h` for information on privilege mode access control.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_69fbd93f", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter11h.yaml", + "section": "hpmcounter11h.COUNT", + "text": "CSR hpmcounter11h field COUNT (bits=31-0) Alias of `mhpmcounter11h.COUNT`. type: RO-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_1cff7bf1", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter12.yaml", + "section": "hpmcounter12", + "text": "CSR hpmcounter12 (address=3084, priv=U): Alias for M-mode CSR `mhpmcounter12`.\n\nSee `mhpmcounter12` for information on privilege mode access control.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Zihpm" + }, + { + "chunk_id": "chunk_c82af480", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter12.yaml", + "section": "hpmcounter12.COUNT", + "text": "CSR hpmcounter12 field COUNT (bits=63-0) Alias of `mhpmcounter12.COUNT`. type: RO-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d90a34d5", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter12h.yaml", + "section": "hpmcounter12h", + "text": "CSR hpmcounter12h (address=3212, priv=U): Alias for M-mode CSR `mhpmcounter12h`.\n\nSee `mhpmcounter12h` for information on privilege mode access control.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_495acaa9", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter12h.yaml", + "section": "hpmcounter12h.COUNT", + "text": "CSR hpmcounter12h field COUNT (bits=31-0) Alias of `mhpmcounter12h.COUNT`. type: RO-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_4f7c0979", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter13.yaml", + "section": "hpmcounter13", + "text": "CSR hpmcounter13 (address=3085, priv=U): Alias for M-mode CSR `mhpmcounter13`.\n\nSee `mhpmcounter13` for information on privilege mode access control.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Zihpm" + }, + { + "chunk_id": "chunk_94e94d91", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter13.yaml", + "section": "hpmcounter13.COUNT", + "text": "CSR hpmcounter13 field COUNT (bits=63-0) Alias of `mhpmcounter13.COUNT`. type: RO-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_f496e27b", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter13h.yaml", + "section": "hpmcounter13h", + "text": "CSR hpmcounter13h (address=3213, priv=U): Alias for M-mode CSR `mhpmcounter13h`.\n\nSee `mhpmcounter13h` for information on privilege mode access control.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_4adffd83", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter13h.yaml", + "section": "hpmcounter13h.COUNT", + "text": "CSR hpmcounter13h field COUNT (bits=31-0) Alias of `mhpmcounter13h.COUNT`. type: RO-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_0911136d", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter14.yaml", + "section": "hpmcounter14", + "text": "CSR hpmcounter14 (address=3086, priv=U): Alias for M-mode CSR `mhpmcounter14`.\n\nSee `mhpmcounter14` for information on privilege mode access control.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Zihpm" + }, + { + "chunk_id": "chunk_1449b2c0", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter14.yaml", + "section": "hpmcounter14.COUNT", + "text": "CSR hpmcounter14 field COUNT (bits=63-0) Alias of `mhpmcounter14.COUNT`. type: RO-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_5b194109", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter14h.yaml", + "section": "hpmcounter14h", + "text": "CSR hpmcounter14h (address=3214, priv=U): Alias for M-mode CSR `mhpmcounter14h`.\n\nSee `mhpmcounter14h` for information on privilege mode access control.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_da4b915a", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter14h.yaml", + "section": "hpmcounter14h.COUNT", + "text": "CSR hpmcounter14h field COUNT (bits=31-0) Alias of `mhpmcounter14h.COUNT`. type: RO-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_f330f80b", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter15.yaml", + "section": "hpmcounter15", + "text": "CSR hpmcounter15 (address=3087, priv=U): Alias for M-mode CSR `mhpmcounter15`.\n\nSee `mhpmcounter15` for information on privilege mode access control.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Zihpm" + }, + { + "chunk_id": "chunk_8c29d620", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter15.yaml", + "section": "hpmcounter15.COUNT", + "text": "CSR hpmcounter15 field COUNT (bits=63-0) Alias of `mhpmcounter15.COUNT`. type: RO-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_04565071", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter15h.yaml", + "section": "hpmcounter15h", + "text": "CSR hpmcounter15h (address=3215, priv=U): Alias for M-mode CSR `mhpmcounter15h`.\n\nSee `mhpmcounter15h` for information on privilege mode access control.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_412448bc", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter15h.yaml", + "section": "hpmcounter15h.COUNT", + "text": "CSR hpmcounter15h field COUNT (bits=31-0) Alias of `mhpmcounter15h.COUNT`. type: RO-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_8baf5be2", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter16.yaml", + "section": "hpmcounter16", + "text": "CSR hpmcounter16 (address=3088, priv=U): Alias for M-mode CSR `mhpmcounter16`.\n\nSee `mhpmcounter16` for information on privilege mode access control.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Zihpm" + }, + { + "chunk_id": "chunk_f437302d", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter16.yaml", + "section": "hpmcounter16.COUNT", + "text": "CSR hpmcounter16 field COUNT (bits=63-0) Alias of `mhpmcounter16.COUNT`. type: RO-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_3be17032", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter16h.yaml", + "section": "hpmcounter16h", + "text": "CSR hpmcounter16h (address=3216, priv=U): Alias for M-mode CSR `mhpmcounter16h`.\n\nSee `mhpmcounter16h` for information on privilege mode access control.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_f8b01298", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter16h.yaml", + "section": "hpmcounter16h.COUNT", + "text": "CSR hpmcounter16h field COUNT (bits=31-0) Alias of `mhpmcounter16h.COUNT`. type: RO-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_7818d61c", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter17.yaml", + "section": "hpmcounter17", + "text": "CSR hpmcounter17 (address=3089, priv=U): Alias for M-mode CSR `mhpmcounter17`.\n\nSee `mhpmcounter17` for information on privilege mode access control.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Zihpm" + }, + { + "chunk_id": "chunk_e14a1b37", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter17.yaml", + "section": "hpmcounter17.COUNT", + "text": "CSR hpmcounter17 field COUNT (bits=63-0) Alias of `mhpmcounter17.COUNT`. type: RO-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_5d7bc3e8", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter17h.yaml", + "section": "hpmcounter17h", + "text": "CSR hpmcounter17h (address=3217, priv=U): Alias for M-mode CSR `mhpmcounter17h`.\n\nSee `mhpmcounter17h` for information on privilege mode access control.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_6837f2a3", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter17h.yaml", + "section": "hpmcounter17h.COUNT", + "text": "CSR hpmcounter17h field COUNT (bits=31-0) Alias of `mhpmcounter17h.COUNT`. type: RO-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_1261b39f", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter18.yaml", + "section": "hpmcounter18", + "text": "CSR hpmcounter18 (address=3090, priv=U): Alias for M-mode CSR `mhpmcounter18`.\n\nSee `mhpmcounter18` for information on privilege mode access control.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Zihpm" + }, + { + "chunk_id": "chunk_a48ca5c6", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter18.yaml", + "section": "hpmcounter18.COUNT", + "text": "CSR hpmcounter18 field COUNT (bits=63-0) Alias of `mhpmcounter18.COUNT`. type: RO-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_74733cd6", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter18h.yaml", + "section": "hpmcounter18h", + "text": "CSR hpmcounter18h (address=3218, priv=U): Alias for M-mode CSR `mhpmcounter18h`.\n\nSee `mhpmcounter18h` for information on privilege mode access control.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_da037818", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter18h.yaml", + "section": "hpmcounter18h.COUNT", + "text": "CSR hpmcounter18h field COUNT (bits=31-0) Alias of `mhpmcounter18h.COUNT`. type: RO-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ec0646ba", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter19.yaml", + "section": "hpmcounter19", + "text": "CSR hpmcounter19 (address=3091, priv=U): Alias for M-mode CSR `mhpmcounter19`.\n\nSee `mhpmcounter19` for information on privilege mode access control.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Zihpm" + }, + { + "chunk_id": "chunk_ab72b688", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter19.yaml", + "section": "hpmcounter19.COUNT", + "text": "CSR hpmcounter19 field COUNT (bits=63-0) Alias of `mhpmcounter19.COUNT`. type: RO-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_c7d21a74", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter19h.yaml", + "section": "hpmcounter19h", + "text": "CSR hpmcounter19h (address=3219, priv=U): Alias for M-mode CSR `mhpmcounter19h`.\n\nSee `mhpmcounter19h` for information on privilege mode access control.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_3acbe8ed", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter19h.yaml", + "section": "hpmcounter19h.COUNT", + "text": "CSR hpmcounter19h field COUNT (bits=31-0) Alias of `mhpmcounter19h.COUNT`. type: RO-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_c50543d6", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter20.yaml", + "section": "hpmcounter20", + "text": "CSR hpmcounter20 (address=3092, priv=U): Alias for M-mode CSR `mhpmcounter20`.\n\nSee `mhpmcounter20` for information on privilege mode access control.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Zihpm" + }, + { + "chunk_id": "chunk_0c6df65e", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter20.yaml", + "section": "hpmcounter20.COUNT", + "text": "CSR hpmcounter20 field COUNT (bits=63-0) Alias of `mhpmcounter20.COUNT`. type: RO-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_21abfc2d", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter20h.yaml", + "section": "hpmcounter20h", + "text": "CSR hpmcounter20h (address=3220, priv=U): Alias for M-mode CSR `mhpmcounter20h`.\n\nSee `mhpmcounter20h` for information on privilege mode access control.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_562e42d4", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter20h.yaml", + "section": "hpmcounter20h.COUNT", + "text": "CSR hpmcounter20h field COUNT (bits=31-0) Alias of `mhpmcounter20h.COUNT`. type: RO-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ce88de85", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter21.yaml", + "section": "hpmcounter21", + "text": "CSR hpmcounter21 (address=3093, priv=U): Alias for M-mode CSR `mhpmcounter21`.\n\nSee `mhpmcounter21` for information on privilege mode access control.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Zihpm" + }, + { + "chunk_id": "chunk_7633708a", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter21.yaml", + "section": "hpmcounter21.COUNT", + "text": "CSR hpmcounter21 field COUNT (bits=63-0) Alias of `mhpmcounter21.COUNT`. type: RO-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_3349cac3", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter21h.yaml", + "section": "hpmcounter21h", + "text": "CSR hpmcounter21h (address=3221, priv=U): Alias for M-mode CSR `mhpmcounter21h`.\n\nSee `mhpmcounter21h` for information on privilege mode access control.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_2f196fe9", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter21h.yaml", + "section": "hpmcounter21h.COUNT", + "text": "CSR hpmcounter21h field COUNT (bits=31-0) Alias of `mhpmcounter21h.COUNT`. type: RO-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_1c14eb63", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter22.yaml", + "section": "hpmcounter22", + "text": "CSR hpmcounter22 (address=3094, priv=U): Alias for M-mode CSR `mhpmcounter22`.\n\nSee `mhpmcounter22` for information on privilege mode access control.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Zihpm" + }, + { + "chunk_id": "chunk_63704dfc", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter22.yaml", + "section": "hpmcounter22.COUNT", + "text": "CSR hpmcounter22 field COUNT (bits=63-0) Alias of `mhpmcounter22.COUNT`. type: RO-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ddf1dbfa", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter22h.yaml", + "section": "hpmcounter22h", + "text": "CSR hpmcounter22h (address=3222, priv=U): Alias for M-mode CSR `mhpmcounter22h`.\n\nSee `mhpmcounter22h` for information on privilege mode access control.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_49d5296a", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter22h.yaml", + "section": "hpmcounter22h.COUNT", + "text": "CSR hpmcounter22h field COUNT (bits=31-0) Alias of `mhpmcounter22h.COUNT`. type: RO-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_aac319a2", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter23.yaml", + "section": "hpmcounter23", + "text": "CSR hpmcounter23 (address=3095, priv=U): Alias for M-mode CSR `mhpmcounter23`.\n\nSee `mhpmcounter23` for information on privilege mode access control.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Zihpm" + }, + { + "chunk_id": "chunk_d528dcb2", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter23.yaml", + "section": "hpmcounter23.COUNT", + "text": "CSR hpmcounter23 field COUNT (bits=63-0) Alias of `mhpmcounter23.COUNT`. type: RO-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_96119a3f", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter23h.yaml", + "section": "hpmcounter23h", + "text": "CSR hpmcounter23h (address=3223, priv=U): Alias for M-mode CSR `mhpmcounter23h`.\n\nSee `mhpmcounter23h` for information on privilege mode access control.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_57f3eb8f", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter23h.yaml", + "section": "hpmcounter23h.COUNT", + "text": "CSR hpmcounter23h field COUNT (bits=31-0) Alias of `mhpmcounter23h.COUNT`. type: RO-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_c034b2f7", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter24.yaml", + "section": "hpmcounter24", + "text": "CSR hpmcounter24 (address=3096, priv=U): Alias for M-mode CSR `mhpmcounter24`.\n\nSee `mhpmcounter24` for information on privilege mode access control.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Zihpm" + }, + { + "chunk_id": "chunk_e02bfc3a", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter24.yaml", + "section": "hpmcounter24.COUNT", + "text": "CSR hpmcounter24 field COUNT (bits=63-0) Alias of `mhpmcounter24.COUNT`. type: RO-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_269bd234", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter24h.yaml", + "section": "hpmcounter24h", + "text": "CSR hpmcounter24h (address=3224, priv=U): Alias for M-mode CSR `mhpmcounter24h`.\n\nSee `mhpmcounter24h` for information on privilege mode access control.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_b560d5d7", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter24h.yaml", + "section": "hpmcounter24h.COUNT", + "text": "CSR hpmcounter24h field COUNT (bits=31-0) Alias of `mhpmcounter24h.COUNT`. type: RO-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_2160d2f7", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter25.yaml", + "section": "hpmcounter25", + "text": "CSR hpmcounter25 (address=3097, priv=U): Alias for M-mode CSR `mhpmcounter25`.\n\nSee `mhpmcounter25` for information on privilege mode access control.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Zihpm" + }, + { + "chunk_id": "chunk_01321e1e", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter25.yaml", + "section": "hpmcounter25.COUNT", + "text": "CSR hpmcounter25 field COUNT (bits=63-0) Alias of `mhpmcounter25.COUNT`. type: RO-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_00b5b8c2", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter25h.yaml", + "section": "hpmcounter25h", + "text": "CSR hpmcounter25h (address=3225, priv=U): Alias for M-mode CSR `mhpmcounter25h`.\n\nSee `mhpmcounter25h` for information on privilege mode access control.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_082477a5", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter25h.yaml", + "section": "hpmcounter25h.COUNT", + "text": "CSR hpmcounter25h field COUNT (bits=31-0) Alias of `mhpmcounter25h.COUNT`. type: RO-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_7d1b7aa1", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter26.yaml", + "section": "hpmcounter26", + "text": "CSR hpmcounter26 (address=3098, priv=U): Alias for M-mode CSR `mhpmcounter26`.\n\nSee `mhpmcounter26` for information on privilege mode access control.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Zihpm" + }, + { + "chunk_id": "chunk_89c5ad69", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter26.yaml", + "section": "hpmcounter26.COUNT", + "text": "CSR hpmcounter26 field COUNT (bits=63-0) Alias of `mhpmcounter26.COUNT`. type: RO-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_7d8c30c1", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter26h.yaml", + "section": "hpmcounter26h", + "text": "CSR hpmcounter26h (address=3226, priv=U): Alias for M-mode CSR `mhpmcounter26h`.\n\nSee `mhpmcounter26h` for information on privilege mode access control.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_21ad3216", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter26h.yaml", + "section": "hpmcounter26h.COUNT", + "text": "CSR hpmcounter26h field COUNT (bits=31-0) Alias of `mhpmcounter26h.COUNT`. type: RO-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d4dd5342", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter27.yaml", + "section": "hpmcounter27", + "text": "CSR hpmcounter27 (address=3099, priv=U): Alias for M-mode CSR `mhpmcounter27`.\n\nSee `mhpmcounter27` for information on privilege mode access control.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Zihpm" + }, + { + "chunk_id": "chunk_d21f404c", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter27.yaml", + "section": "hpmcounter27.COUNT", + "text": "CSR hpmcounter27 field COUNT (bits=63-0) Alias of `mhpmcounter27.COUNT`. type: RO-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_71b2bebf", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter27h.yaml", + "section": "hpmcounter27h", + "text": "CSR hpmcounter27h (address=3227, priv=U): Alias for M-mode CSR `mhpmcounter27h`.\n\nSee `mhpmcounter27h` for information on privilege mode access control.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_f38f5299", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter27h.yaml", + "section": "hpmcounter27h.COUNT", + "text": "CSR hpmcounter27h field COUNT (bits=31-0) Alias of `mhpmcounter27h.COUNT`. type: RO-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_6b75543f", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter28.yaml", + "section": "hpmcounter28", + "text": "CSR hpmcounter28 (address=3100, priv=U): Alias for M-mode CSR `mhpmcounter28`.\n\nSee `mhpmcounter28` for information on privilege mode access control.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Zihpm" + }, + { + "chunk_id": "chunk_eb4e4dcf", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter28.yaml", + "section": "hpmcounter28.COUNT", + "text": "CSR hpmcounter28 field COUNT (bits=63-0) Alias of `mhpmcounter28.COUNT`. type: RO-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_5e2e193c", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter28h.yaml", + "section": "hpmcounter28h", + "text": "CSR hpmcounter28h (address=3228, priv=U): Alias for M-mode CSR `mhpmcounter28h`.\n\nSee `mhpmcounter28h` for information on privilege mode access control.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_4542929f", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter28h.yaml", + "section": "hpmcounter28h.COUNT", + "text": "CSR hpmcounter28h field COUNT (bits=31-0) Alias of `mhpmcounter28h.COUNT`. type: RO-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_0138101e", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter29.yaml", + "section": "hpmcounter29", + "text": "CSR hpmcounter29 (address=3101, priv=U): Alias for M-mode CSR `mhpmcounter29`.\n\nSee `mhpmcounter29` for information on privilege mode access control.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Zihpm" + }, + { + "chunk_id": "chunk_ec509e0f", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter29.yaml", + "section": "hpmcounter29.COUNT", + "text": "CSR hpmcounter29 field COUNT (bits=63-0) Alias of `mhpmcounter29.COUNT`. type: RO-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_919ce9ee", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter29h.yaml", + "section": "hpmcounter29h", + "text": "CSR hpmcounter29h (address=3229, priv=U): Alias for M-mode CSR `mhpmcounter29h`.\n\nSee `mhpmcounter29h` for information on privilege mode access control.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_b185eb65", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter29h.yaml", + "section": "hpmcounter29h.COUNT", + "text": "CSR hpmcounter29h field COUNT (bits=31-0) Alias of `mhpmcounter29h.COUNT`. type: RO-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_c95e4d8a", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter3.yaml", + "section": "hpmcounter3", + "text": "CSR hpmcounter3 (address=3075, priv=U): Alias for M-mode CSR `mhpmcounter3`.\n\nSee `mhpmcounter3` for information on privilege mode access control.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Zihpm" + }, + { + "chunk_id": "chunk_a9bcae87", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter3.yaml", + "section": "hpmcounter3.COUNT", + "text": "CSR hpmcounter3 field COUNT (bits=63-0) Alias of `mhpmcounter3.COUNT`. type: RO-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_087dd5db", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter30.yaml", + "section": "hpmcounter30", + "text": "CSR hpmcounter30 (address=3102, priv=U): Alias for M-mode CSR `mhpmcounter30`.\n\nSee `mhpmcounter30` for information on privilege mode access control.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Zihpm" + }, + { + "chunk_id": "chunk_3c19d5a5", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter30.yaml", + "section": "hpmcounter30.COUNT", + "text": "CSR hpmcounter30 field COUNT (bits=63-0) Alias of `mhpmcounter30.COUNT`. type: RO-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_fac1ae32", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter30h.yaml", + "section": "hpmcounter30h", + "text": "CSR hpmcounter30h (address=3230, priv=U): Alias for M-mode CSR `mhpmcounter30h`.\n\nSee `mhpmcounter30h` for information on privilege mode access control.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_cf78ced8", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter30h.yaml", + "section": "hpmcounter30h.COUNT", + "text": "CSR hpmcounter30h field COUNT (bits=31-0) Alias of `mhpmcounter30h.COUNT`. type: RO-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_a7c72480", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter31.yaml", + "section": "hpmcounter31", + "text": "CSR hpmcounter31 (address=3103, priv=U): Alias for M-mode CSR `mhpmcounter31`.\n\nSee `mhpmcounter31` for information on privilege mode access control.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Zihpm" + }, + { + "chunk_id": "chunk_42af7664", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter31.yaml", + "section": "hpmcounter31.COUNT", + "text": "CSR hpmcounter31 field COUNT (bits=63-0) Alias of `mhpmcounter31.COUNT`. type: RO-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_b6c8aec4", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter31h.yaml", + "section": "hpmcounter31h", + "text": "CSR hpmcounter31h (address=3231, priv=U): Alias for M-mode CSR `mhpmcounter31h`.\n\nSee `mhpmcounter31h` for information on privilege mode access control.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_097892ab", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter31h.yaml", + "section": "hpmcounter31h.COUNT", + "text": "CSR hpmcounter31h field COUNT (bits=31-0) Alias of `mhpmcounter31h.COUNT`. type: RO-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_e3034124", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter3h.yaml", + "section": "hpmcounter3h", + "text": "CSR hpmcounter3h (address=3203, priv=U): Alias for M-mode CSR `mhpmcounter3h`.\n\nSee `mhpmcounter3h` for information on privilege mode access control.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d6e69470", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter3h.yaml", + "section": "hpmcounter3h.COUNT", + "text": "CSR hpmcounter3h field COUNT (bits=31-0) Alias of `mhpmcounter3h.COUNT`. type: RO-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_99bf627d", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter4.yaml", + "section": "hpmcounter4", + "text": "CSR hpmcounter4 (address=3076, priv=U): Alias for M-mode CSR `mhpmcounter4`.\n\nSee `mhpmcounter4` for information on privilege mode access control.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Zihpm" + }, + { + "chunk_id": "chunk_20a8c595", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter4.yaml", + "section": "hpmcounter4.COUNT", + "text": "CSR hpmcounter4 field COUNT (bits=63-0) Alias of `mhpmcounter4.COUNT`. type: RO-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_305b8989", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter4h.yaml", + "section": "hpmcounter4h", + "text": "CSR hpmcounter4h (address=3204, priv=U): Alias for M-mode CSR `mhpmcounter4h`.\n\nSee `mhpmcounter4h` for information on privilege mode access control.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_77221cd6", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter4h.yaml", + "section": "hpmcounter4h.COUNT", + "text": "CSR hpmcounter4h field COUNT (bits=31-0) Alias of `mhpmcounter4h.COUNT`. type: RO-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_16de8378", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter5.yaml", + "section": "hpmcounter5", + "text": "CSR hpmcounter5 (address=3077, priv=U): Alias for M-mode CSR `mhpmcounter5`.\n\nSee `mhpmcounter5` for information on privilege mode access control.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Zihpm" + }, + { + "chunk_id": "chunk_af2a3f1d", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter5.yaml", + "section": "hpmcounter5.COUNT", + "text": "CSR hpmcounter5 field COUNT (bits=63-0) Alias of `mhpmcounter5.COUNT`. type: RO-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_5f16d299", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter5h.yaml", + "section": "hpmcounter5h", + "text": "CSR hpmcounter5h (address=3205, priv=U): Alias for M-mode CSR `mhpmcounter5h`.\n\nSee `mhpmcounter5h` for information on privilege mode access control.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_7a98b6c8", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter5h.yaml", + "section": "hpmcounter5h.COUNT", + "text": "CSR hpmcounter5h field COUNT (bits=31-0) Alias of `mhpmcounter5h.COUNT`. type: RO-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_96a52166", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter6.yaml", + "section": "hpmcounter6", + "text": "CSR hpmcounter6 (address=3078, priv=U): Alias for M-mode CSR `mhpmcounter6`.\n\nSee `mhpmcounter6` for information on privilege mode access control.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Zihpm" + }, + { + "chunk_id": "chunk_93e9ba5b", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter6.yaml", + "section": "hpmcounter6.COUNT", + "text": "CSR hpmcounter6 field COUNT (bits=63-0) Alias of `mhpmcounter6.COUNT`. type: RO-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_7245542f", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter6h.yaml", + "section": "hpmcounter6h", + "text": "CSR hpmcounter6h (address=3206, priv=U): Alias for M-mode CSR `mhpmcounter6h`.\n\nSee `mhpmcounter6h` for information on privilege mode access control.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d2b34fd7", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter6h.yaml", + "section": "hpmcounter6h.COUNT", + "text": "CSR hpmcounter6h field COUNT (bits=31-0) Alias of `mhpmcounter6h.COUNT`. type: RO-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ae8f3c57", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter7.yaml", + "section": "hpmcounter7", + "text": "CSR hpmcounter7 (address=3079, priv=U): Alias for M-mode CSR `mhpmcounter7`.\n\nSee `mhpmcounter7` for information on privilege mode access control.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Zihpm" + }, + { + "chunk_id": "chunk_35e7b799", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter7.yaml", + "section": "hpmcounter7.COUNT", + "text": "CSR hpmcounter7 field COUNT (bits=63-0) Alias of `mhpmcounter7.COUNT`. type: RO-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_184a3346", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter7h.yaml", + "section": "hpmcounter7h", + "text": "CSR hpmcounter7h (address=3207, priv=U): Alias for M-mode CSR `mhpmcounter7h`.\n\nSee `mhpmcounter7h` for information on privilege mode access control.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_868ca496", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter7h.yaml", + "section": "hpmcounter7h.COUNT", + "text": "CSR hpmcounter7h field COUNT (bits=31-0) Alias of `mhpmcounter7h.COUNT`. type: RO-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_35ecf92c", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter8.yaml", + "section": "hpmcounter8", + "text": "CSR hpmcounter8 (address=3080, priv=U): Alias for M-mode CSR `mhpmcounter8`.\n\nSee `mhpmcounter8` for information on privilege mode access control.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Zihpm" + }, + { + "chunk_id": "chunk_7eb67d6b", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter8.yaml", + "section": "hpmcounter8.COUNT", + "text": "CSR hpmcounter8 field COUNT (bits=63-0) Alias of `mhpmcounter8.COUNT`. type: RO-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_40703b86", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter8h.yaml", + "section": "hpmcounter8h", + "text": "CSR hpmcounter8h (address=3208, priv=U): Alias for M-mode CSR `mhpmcounter8h`.\n\nSee `mhpmcounter8h` for information on privilege mode access control.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_e0a3e7fc", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter8h.yaml", + "section": "hpmcounter8h.COUNT", + "text": "CSR hpmcounter8h field COUNT (bits=31-0) Alias of `mhpmcounter8h.COUNT`. type: RO-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_c4462c6f", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter9.yaml", + "section": "hpmcounter9", + "text": "CSR hpmcounter9 (address=3081, priv=U): Alias for M-mode CSR `mhpmcounter9`.\n\nSee `mhpmcounter9` for information on privilege mode access control.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Zihpm" + }, + { + "chunk_id": "chunk_352c1551", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter9.yaml", + "section": "hpmcounter9.COUNT", + "text": "CSR hpmcounter9 field COUNT (bits=63-0) Alias of `mhpmcounter9.COUNT`. type: RO-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_4cecaa2a", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter9h.yaml", + "section": "hpmcounter9h", + "text": "CSR hpmcounter9h (address=3209, priv=U): Alias for M-mode CSR `mhpmcounter9h`.\n\nSee `mhpmcounter9h` for information on privilege mode access control.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_de37699b", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/hpmcounter9h.yaml", + "section": "hpmcounter9h.COUNT", + "text": "CSR hpmcounter9h field COUNT (bits=31-0) Alias of `mhpmcounter9h.COUNT`. type: RO-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_51d20d4a", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter10.yaml", + "section": "mhpmcounter10", + "text": "CSR mhpmcounter10 (address=2826, priv=M): Programmable hardware performance counter.\n\nThe `hpmcounter10` CSR is a read-only shadow of this CSR. Access to `hpmcounter10`\nis controlled with `mcounteren.HPM10`\n<%- if ext?(:S) -%>\n, `scounteren.HPM10`\n<%- if ext?(:H) -%>\n, and `hcounteren.HPM10`\n<%- end -%>\n<%- end -%>\nas follows:\n\n<%- if ext?(", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_fcca48ba", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter10.yaml", + "section": "mhpmcounter10.COUNT", + "text": "CSR mhpmcounter10 field COUNT (bits=63-0) [when=\"HPM_COUNTER_EN[10] == true\"]\n--\nPerformance counter for event selected in `mhpmevent10.EVENT`.\n\nIncrements every time event occurs unless:\n\n * `mcountinhibit.HPM10` <%- if ext?(:Smcdeleg) -%>or its alias `scountinhibit.HPM10`<%- end -%> is set\n <%- if ext?(:Sscofpmf) -%>\n * `mhpmevent10.MI type: return (HPM_COUNTER_EN[10]) ? CsrFieldType::RWH : CsrFieldType::RO; reset: return (HPM_COUNTER_EN[10]) ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_8550b2d0", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter10h.yaml", + "section": "mhpmcounter10h", + "text": "CSR mhpmcounter10h (address=2954, priv=M): Upper half of mhpmcounter10.\n\nThe `hpmcounter10h` CSR is a read-only shadow of this CSR. Access to `hpmcounter10h`\nis controlled with `mcounteren.HPM10`\n<%- if ext?(:S) -%>\n, `scounteren.HPM10`\n<%- if ext?(:H) -%>\n, and `hcounteren.HPM10`\n<%- end -%>\n<%- end -%>\nas follows:\n\n<%- if ext?(:H) -%>\n[%au", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_2534a244", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter10h.yaml", + "section": "mhpmcounter10h.COUNT", + "text": "CSR mhpmcounter10h field COUNT (bits=31-0) Upper bits of counter. type: return (HPM_COUNTER_EN[10]) ? CsrFieldType::RWH : CsrFieldType::RO; reset: return (HPM_COUNTER_EN[10]) ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ccb9f254", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter11.yaml", + "section": "mhpmcounter11", + "text": "CSR mhpmcounter11 (address=2827, priv=M): Programmable hardware performance counter.\n\nThe `hpmcounter11` CSR is a read-only shadow of this CSR. Access to `hpmcounter11`\nis controlled with `mcounteren.HPM11`\n<%- if ext?(:S) -%>\n, `scounteren.HPM11`\n<%- if ext?(:H) -%>\n, and `hcounteren.HPM11`\n<%- end -%>\n<%- end -%>\nas follows:\n\n<%- if ext?(", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_93cacffb", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter11.yaml", + "section": "mhpmcounter11.COUNT", + "text": "CSR mhpmcounter11 field COUNT (bits=63-0) [when=\"HPM_COUNTER_EN[11] == true\"]\n--\nPerformance counter for event selected in `mhpmevent11.EVENT`.\n\nIncrements every time event occurs unless:\n\n * `mcountinhibit.HPM11` <%- if ext?(:Smcdeleg) -%>or its alias `scountinhibit.HPM11`<%- end -%> is set\n <%- if ext?(:Sscofpmf) -%>\n * `mhpmevent11.MI type: return (HPM_COUNTER_EN[11]) ? CsrFieldType::RWH : CsrFieldType::RO; reset: return (HPM_COUNTER_EN[11]) ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_03c5183d", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter11h.yaml", + "section": "mhpmcounter11h", + "text": "CSR mhpmcounter11h (address=2955, priv=M): Upper half of mhpmcounter11.\n\nThe `hpmcounter11h` CSR is a read-only shadow of this CSR. Access to `hpmcounter11h`\nis controlled with `mcounteren.HPM11`\n<%- if ext?(:S) -%>\n, `scounteren.HPM11`\n<%- if ext?(:H) -%>\n, and `hcounteren.HPM11`\n<%- end -%>\n<%- end -%>\nas follows:\n\n<%- if ext?(:H) -%>\n[%au", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ac8ba9db", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter11h.yaml", + "section": "mhpmcounter11h.COUNT", + "text": "CSR mhpmcounter11h field COUNT (bits=31-0) Upper bits of counter. type: return (HPM_COUNTER_EN[11]) ? CsrFieldType::RWH : CsrFieldType::RO; reset: return (HPM_COUNTER_EN[11]) ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_4a1f9711", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter12.yaml", + "section": "mhpmcounter12", + "text": "CSR mhpmcounter12 (address=2828, priv=M): Programmable hardware performance counter.\n\nThe `hpmcounter12` CSR is a read-only shadow of this CSR. Access to `hpmcounter12`\nis controlled with `mcounteren.HPM12`\n<%- if ext?(:S) -%>\n, `scounteren.HPM12`\n<%- if ext?(:H) -%>\n, and `hcounteren.HPM12`\n<%- end -%>\n<%- end -%>\nas follows:\n\n<%- if ext?(", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_2c2f0f52", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter12.yaml", + "section": "mhpmcounter12.COUNT", + "text": "CSR mhpmcounter12 field COUNT (bits=63-0) [when=\"HPM_COUNTER_EN[12] == true\"]\n--\nPerformance counter for event selected in `mhpmevent12.EVENT`.\n\nIncrements every time event occurs unless:\n\n * `mcountinhibit.HPM12` <%- if ext?(:Smcdeleg) -%>or its alias `scountinhibit.HPM12`<%- end -%> is set\n <%- if ext?(:Sscofpmf) -%>\n * `mhpmevent12.MI type: return (HPM_COUNTER_EN[12]) ? CsrFieldType::RWH : CsrFieldType::RO; reset: return (HPM_COUNTER_EN[12]) ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_03ff0dd1", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter12h.yaml", + "section": "mhpmcounter12h", + "text": "CSR mhpmcounter12h (address=2956, priv=M): Upper half of mhpmcounter12.\n\nThe `hpmcounter12h` CSR is a read-only shadow of this CSR. Access to `hpmcounter12h`\nis controlled with `mcounteren.HPM12`\n<%- if ext?(:S) -%>\n, `scounteren.HPM12`\n<%- if ext?(:H) -%>\n, and `hcounteren.HPM12`\n<%- end -%>\n<%- end -%>\nas follows:\n\n<%- if ext?(:H) -%>\n[%au", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_3b4d3e74", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter12h.yaml", + "section": "mhpmcounter12h.COUNT", + "text": "CSR mhpmcounter12h field COUNT (bits=31-0) Upper bits of counter. type: return (HPM_COUNTER_EN[12]) ? CsrFieldType::RWH : CsrFieldType::RO; reset: return (HPM_COUNTER_EN[12]) ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_4ac5dfde", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter13.yaml", + "section": "mhpmcounter13", + "text": "CSR mhpmcounter13 (address=2829, priv=M): Programmable hardware performance counter.\n\nThe `hpmcounter13` CSR is a read-only shadow of this CSR. Access to `hpmcounter13`\nis controlled with `mcounteren.HPM13`\n<%- if ext?(:S) -%>\n, `scounteren.HPM13`\n<%- if ext?(:H) -%>\n, and `hcounteren.HPM13`\n<%- end -%>\n<%- end -%>\nas follows:\n\n<%- if ext?(", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_c690817a", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter13.yaml", + "section": "mhpmcounter13.COUNT", + "text": "CSR mhpmcounter13 field COUNT (bits=63-0) [when=\"HPM_COUNTER_EN[13] == true\"]\n--\nPerformance counter for event selected in `mhpmevent13.EVENT`.\n\nIncrements every time event occurs unless:\n\n * `mcountinhibit.HPM13` <%- if ext?(:Smcdeleg) -%>or its alias `scountinhibit.HPM13`<%- end -%> is set\n <%- if ext?(:Sscofpmf) -%>\n * `mhpmevent13.MI type: return (HPM_COUNTER_EN[13]) ? CsrFieldType::RWH : CsrFieldType::RO; reset: return (HPM_COUNTER_EN[13]) ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_c2b460dd", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter13h.yaml", + "section": "mhpmcounter13h", + "text": "CSR mhpmcounter13h (address=2957, priv=M): Upper half of mhpmcounter13.\n\nThe `hpmcounter13h` CSR is a read-only shadow of this CSR. Access to `hpmcounter13h`\nis controlled with `mcounteren.HPM13`\n<%- if ext?(:S) -%>\n, `scounteren.HPM13`\n<%- if ext?(:H) -%>\n, and `hcounteren.HPM13`\n<%- end -%>\n<%- end -%>\nas follows:\n\n<%- if ext?(:H) -%>\n[%au", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_aeac13a4", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter13h.yaml", + "section": "mhpmcounter13h.COUNT", + "text": "CSR mhpmcounter13h field COUNT (bits=31-0) Upper bits of counter. type: return (HPM_COUNTER_EN[13]) ? CsrFieldType::RWH : CsrFieldType::RO; reset: return (HPM_COUNTER_EN[13]) ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_470c2f40", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter14.yaml", + "section": "mhpmcounter14", + "text": "CSR mhpmcounter14 (address=2830, priv=M): Programmable hardware performance counter.\n\nThe `hpmcounter14` CSR is a read-only shadow of this CSR. Access to `hpmcounter14`\nis controlled with `mcounteren.HPM14`\n<%- if ext?(:S) -%>\n, `scounteren.HPM14`\n<%- if ext?(:H) -%>\n, and `hcounteren.HPM14`\n<%- end -%>\n<%- end -%>\nas follows:\n\n<%- if ext?(", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d5aa0384", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter14.yaml", + "section": "mhpmcounter14.COUNT", + "text": "CSR mhpmcounter14 field COUNT (bits=63-0) [when=\"HPM_COUNTER_EN[14] == true\"]\n--\nPerformance counter for event selected in `mhpmevent14.EVENT`.\n\nIncrements every time event occurs unless:\n\n * `mcountinhibit.HPM14` <%- if ext?(:Smcdeleg) -%>or its alias `scountinhibit.HPM14`<%- end -%> is set\n <%- if ext?(:Sscofpmf) -%>\n * `mhpmevent14.MI type: return (HPM_COUNTER_EN[14]) ? CsrFieldType::RWH : CsrFieldType::RO; reset: return (HPM_COUNTER_EN[14]) ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_dcbcd330", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter14h.yaml", + "section": "mhpmcounter14h", + "text": "CSR mhpmcounter14h (address=2958, priv=M): Upper half of mhpmcounter14.\n\nThe `hpmcounter14h` CSR is a read-only shadow of this CSR. Access to `hpmcounter14h`\nis controlled with `mcounteren.HPM14`\n<%- if ext?(:S) -%>\n, `scounteren.HPM14`\n<%- if ext?(:H) -%>\n, and `hcounteren.HPM14`\n<%- end -%>\n<%- end -%>\nas follows:\n\n<%- if ext?(:H) -%>\n[%au", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_6bd2bd95", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter14h.yaml", + "section": "mhpmcounter14h.COUNT", + "text": "CSR mhpmcounter14h field COUNT (bits=31-0) Upper bits of counter. type: return (HPM_COUNTER_EN[14]) ? CsrFieldType::RWH : CsrFieldType::RO; reset: return (HPM_COUNTER_EN[14]) ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_72187109", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter15.yaml", + "section": "mhpmcounter15", + "text": "CSR mhpmcounter15 (address=2831, priv=M): Programmable hardware performance counter.\n\nThe `hpmcounter15` CSR is a read-only shadow of this CSR. Access to `hpmcounter15`\nis controlled with `mcounteren.HPM15`\n<%- if ext?(:S) -%>\n, `scounteren.HPM15`\n<%- if ext?(:H) -%>\n, and `hcounteren.HPM15`\n<%- end -%>\n<%- end -%>\nas follows:\n\n<%- if ext?(", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_470d4c57", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter15.yaml", + "section": "mhpmcounter15.COUNT", + "text": "CSR mhpmcounter15 field COUNT (bits=63-0) [when=\"HPM_COUNTER_EN[15] == true\"]\n--\nPerformance counter for event selected in `mhpmevent15.EVENT`.\n\nIncrements every time event occurs unless:\n\n * `mcountinhibit.HPM15` <%- if ext?(:Smcdeleg) -%>or its alias `scountinhibit.HPM15`<%- end -%> is set\n <%- if ext?(:Sscofpmf) -%>\n * `mhpmevent15.MI type: return (HPM_COUNTER_EN[15]) ? CsrFieldType::RWH : CsrFieldType::RO; reset: return (HPM_COUNTER_EN[15]) ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_5975528a", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter15h.yaml", + "section": "mhpmcounter15h", + "text": "CSR mhpmcounter15h (address=2959, priv=M): Upper half of mhpmcounter15.\n\nThe `hpmcounter15h` CSR is a read-only shadow of this CSR. Access to `hpmcounter15h`\nis controlled with `mcounteren.HPM15`\n<%- if ext?(:S) -%>\n, `scounteren.HPM15`\n<%- if ext?(:H) -%>\n, and `hcounteren.HPM15`\n<%- end -%>\n<%- end -%>\nas follows:\n\n<%- if ext?(:H) -%>\n[%au", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_550d7842", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter15h.yaml", + "section": "mhpmcounter15h.COUNT", + "text": "CSR mhpmcounter15h field COUNT (bits=31-0) Upper bits of counter. type: return (HPM_COUNTER_EN[15]) ? CsrFieldType::RWH : CsrFieldType::RO; reset: return (HPM_COUNTER_EN[15]) ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_30710e4c", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter16.yaml", + "section": "mhpmcounter16", + "text": "CSR mhpmcounter16 (address=2832, priv=M): Programmable hardware performance counter.\n\nThe `hpmcounter16` CSR is a read-only shadow of this CSR. Access to `hpmcounter16`\nis controlled with `mcounteren.HPM16`\n<%- if ext?(:S) -%>\n, `scounteren.HPM16`\n<%- if ext?(:H) -%>\n, and `hcounteren.HPM16`\n<%- end -%>\n<%- end -%>\nas follows:\n\n<%- if ext?(", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_2cc94a40", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter16.yaml", + "section": "mhpmcounter16.COUNT", + "text": "CSR mhpmcounter16 field COUNT (bits=63-0) [when=\"HPM_COUNTER_EN[16] == true\"]\n--\nPerformance counter for event selected in `mhpmevent16.EVENT`.\n\nIncrements every time event occurs unless:\n\n * `mcountinhibit.HPM16` <%- if ext?(:Smcdeleg) -%>or its alias `scountinhibit.HPM16`<%- end -%> is set\n <%- if ext?(:Sscofpmf) -%>\n * `mhpmevent16.MI type: return (HPM_COUNTER_EN[16]) ? CsrFieldType::RWH : CsrFieldType::RO; reset: return (HPM_COUNTER_EN[16]) ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_2b6ca88a", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter16h.yaml", + "section": "mhpmcounter16h", + "text": "CSR mhpmcounter16h (address=2960, priv=M): Upper half of mhpmcounter16.\n\nThe `hpmcounter16h` CSR is a read-only shadow of this CSR. Access to `hpmcounter16h`\nis controlled with `mcounteren.HPM16`\n<%- if ext?(:S) -%>\n, `scounteren.HPM16`\n<%- if ext?(:H) -%>\n, and `hcounteren.HPM16`\n<%- end -%>\n<%- end -%>\nas follows:\n\n<%- if ext?(:H) -%>\n[%au", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_427eaf30", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter16h.yaml", + "section": "mhpmcounter16h.COUNT", + "text": "CSR mhpmcounter16h field COUNT (bits=31-0) Upper bits of counter. type: return (HPM_COUNTER_EN[16]) ? CsrFieldType::RWH : CsrFieldType::RO; reset: return (HPM_COUNTER_EN[16]) ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ee4db137", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter17.yaml", + "section": "mhpmcounter17", + "text": "CSR mhpmcounter17 (address=2833, priv=M): Programmable hardware performance counter.\n\nThe `hpmcounter17` CSR is a read-only shadow of this CSR. Access to `hpmcounter17`\nis controlled with `mcounteren.HPM17`\n<%- if ext?(:S) -%>\n, `scounteren.HPM17`\n<%- if ext?(:H) -%>\n, and `hcounteren.HPM17`\n<%- end -%>\n<%- end -%>\nas follows:\n\n<%- if ext?(", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d32d3c51", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter17.yaml", + "section": "mhpmcounter17.COUNT", + "text": "CSR mhpmcounter17 field COUNT (bits=63-0) [when=\"HPM_COUNTER_EN[17] == true\"]\n--\nPerformance counter for event selected in `mhpmevent17.EVENT`.\n\nIncrements every time event occurs unless:\n\n * `mcountinhibit.HPM17` <%- if ext?(:Smcdeleg) -%>or its alias `scountinhibit.HPM17`<%- end -%> is set\n <%- if ext?(:Sscofpmf) -%>\n * `mhpmevent17.MI type: return (HPM_COUNTER_EN[17]) ? CsrFieldType::RWH : CsrFieldType::RO; reset: return (HPM_COUNTER_EN[17]) ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_dfd3326e", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter17h.yaml", + "section": "mhpmcounter17h", + "text": "CSR mhpmcounter17h (address=2961, priv=M): Upper half of mhpmcounter17.\n\nThe `hpmcounter17h` CSR is a read-only shadow of this CSR. Access to `hpmcounter17h`\nis controlled with `mcounteren.HPM17`\n<%- if ext?(:S) -%>\n, `scounteren.HPM17`\n<%- if ext?(:H) -%>\n, and `hcounteren.HPM17`\n<%- end -%>\n<%- end -%>\nas follows:\n\n<%- if ext?(:H) -%>\n[%au", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_e6777c15", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter17h.yaml", + "section": "mhpmcounter17h.COUNT", + "text": "CSR mhpmcounter17h field COUNT (bits=31-0) Upper bits of counter. type: return (HPM_COUNTER_EN[17]) ? CsrFieldType::RWH : CsrFieldType::RO; reset: return (HPM_COUNTER_EN[17]) ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_b03fc217", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter18.yaml", + "section": "mhpmcounter18", + "text": "CSR mhpmcounter18 (address=2834, priv=M): Programmable hardware performance counter.\n\nThe `hpmcounter18` CSR is a read-only shadow of this CSR. Access to `hpmcounter18`\nis controlled with `mcounteren.HPM18`\n<%- if ext?(:S) -%>\n, `scounteren.HPM18`\n<%- if ext?(:H) -%>\n, and `hcounteren.HPM18`\n<%- end -%>\n<%- end -%>\nas follows:\n\n<%- if ext?(", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_f0425fdd", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter18.yaml", + "section": "mhpmcounter18.COUNT", + "text": "CSR mhpmcounter18 field COUNT (bits=63-0) [when=\"HPM_COUNTER_EN[18] == true\"]\n--\nPerformance counter for event selected in `mhpmevent18.EVENT`.\n\nIncrements every time event occurs unless:\n\n * `mcountinhibit.HPM18` <%- if ext?(:Smcdeleg) -%>or its alias `scountinhibit.HPM18`<%- end -%> is set\n <%- if ext?(:Sscofpmf) -%>\n * `mhpmevent18.MI type: return (HPM_COUNTER_EN[18]) ? CsrFieldType::RWH : CsrFieldType::RO; reset: return (HPM_COUNTER_EN[18]) ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_68bf032c", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter18h.yaml", + "section": "mhpmcounter18h", + "text": "CSR mhpmcounter18h (address=2962, priv=M): Upper half of mhpmcounter18.\n\nThe `hpmcounter18h` CSR is a read-only shadow of this CSR. Access to `hpmcounter18h`\nis controlled with `mcounteren.HPM18`\n<%- if ext?(:S) -%>\n, `scounteren.HPM18`\n<%- if ext?(:H) -%>\n, and `hcounteren.HPM18`\n<%- end -%>\n<%- end -%>\nas follows:\n\n<%- if ext?(:H) -%>\n[%au", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_5aff248c", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter18h.yaml", + "section": "mhpmcounter18h.COUNT", + "text": "CSR mhpmcounter18h field COUNT (bits=31-0) Upper bits of counter. type: return (HPM_COUNTER_EN[18]) ? CsrFieldType::RWH : CsrFieldType::RO; reset: return (HPM_COUNTER_EN[18]) ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_7198dfe4", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter19.yaml", + "section": "mhpmcounter19", + "text": "CSR mhpmcounter19 (address=2835, priv=M): Programmable hardware performance counter.\n\nThe `hpmcounter19` CSR is a read-only shadow of this CSR. Access to `hpmcounter19`\nis controlled with `mcounteren.HPM19`\n<%- if ext?(:S) -%>\n, `scounteren.HPM19`\n<%- if ext?(:H) -%>\n, and `hcounteren.HPM19`\n<%- end -%>\n<%- end -%>\nas follows:\n\n<%- if ext?(", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ef0e36a9", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter19.yaml", + "section": "mhpmcounter19.COUNT", + "text": "CSR mhpmcounter19 field COUNT (bits=63-0) [when=\"HPM_COUNTER_EN[19] == true\"]\n--\nPerformance counter for event selected in `mhpmevent19.EVENT`.\n\nIncrements every time event occurs unless:\n\n * `mcountinhibit.HPM19` <%- if ext?(:Smcdeleg) -%>or its alias `scountinhibit.HPM19`<%- end -%> is set\n <%- if ext?(:Sscofpmf) -%>\n * `mhpmevent19.MI type: return (HPM_COUNTER_EN[19]) ? CsrFieldType::RWH : CsrFieldType::RO; reset: return (HPM_COUNTER_EN[19]) ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ec255b17", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter19h.yaml", + "section": "mhpmcounter19h", + "text": "CSR mhpmcounter19h (address=2963, priv=M): Upper half of mhpmcounter19.\n\nThe `hpmcounter19h` CSR is a read-only shadow of this CSR. Access to `hpmcounter19h`\nis controlled with `mcounteren.HPM19`\n<%- if ext?(:S) -%>\n, `scounteren.HPM19`\n<%- if ext?(:H) -%>\n, and `hcounteren.HPM19`\n<%- end -%>\n<%- end -%>\nas follows:\n\n<%- if ext?(:H) -%>\n[%au", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_bc6f63be", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter19h.yaml", + "section": "mhpmcounter19h.COUNT", + "text": "CSR mhpmcounter19h field COUNT (bits=31-0) Upper bits of counter. type: return (HPM_COUNTER_EN[19]) ? CsrFieldType::RWH : CsrFieldType::RO; reset: return (HPM_COUNTER_EN[19]) ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_99cec3cf", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter20.yaml", + "section": "mhpmcounter20", + "text": "CSR mhpmcounter20 (address=2836, priv=M): Programmable hardware performance counter.\n\nThe `hpmcounter20` CSR is a read-only shadow of this CSR. Access to `hpmcounter20`\nis controlled with `mcounteren.HPM20`\n<%- if ext?(:S) -%>\n, `scounteren.HPM20`\n<%- if ext?(:H) -%>\n, and `hcounteren.HPM20`\n<%- end -%>\n<%- end -%>\nas follows:\n\n<%- if ext?(", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_f4d849b0", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter20.yaml", + "section": "mhpmcounter20.COUNT", + "text": "CSR mhpmcounter20 field COUNT (bits=63-0) [when=\"HPM_COUNTER_EN[20] == true\"]\n--\nPerformance counter for event selected in `mhpmevent20.EVENT`.\n\nIncrements every time event occurs unless:\n\n * `mcountinhibit.HPM20` <%- if ext?(:Smcdeleg) -%>or its alias `scountinhibit.HPM20`<%- end -%> is set\n <%- if ext?(:Sscofpmf) -%>\n * `mhpmevent20.MI type: return (HPM_COUNTER_EN[20]) ? CsrFieldType::RWH : CsrFieldType::RO; reset: return (HPM_COUNTER_EN[20]) ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_39fe1c40", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter20h.yaml", + "section": "mhpmcounter20h", + "text": "CSR mhpmcounter20h (address=2964, priv=M): Upper half of mhpmcounter20.\n\nThe `hpmcounter20h` CSR is a read-only shadow of this CSR. Access to `hpmcounter20h`\nis controlled with `mcounteren.HPM20`\n<%- if ext?(:S) -%>\n, `scounteren.HPM20`\n<%- if ext?(:H) -%>\n, and `hcounteren.HPM20`\n<%- end -%>\n<%- end -%>\nas follows:\n\n<%- if ext?(:H) -%>\n[%au", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_b81911ea", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter20h.yaml", + "section": "mhpmcounter20h.COUNT", + "text": "CSR mhpmcounter20h field COUNT (bits=31-0) Upper bits of counter. type: return (HPM_COUNTER_EN[20]) ? CsrFieldType::RWH : CsrFieldType::RO; reset: return (HPM_COUNTER_EN[20]) ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_e07e5c5c", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter21.yaml", + "section": "mhpmcounter21", + "text": "CSR mhpmcounter21 (address=2837, priv=M): Programmable hardware performance counter.\n\nThe `hpmcounter21` CSR is a read-only shadow of this CSR. Access to `hpmcounter21`\nis controlled with `mcounteren.HPM21`\n<%- if ext?(:S) -%>\n, `scounteren.HPM21`\n<%- if ext?(:H) -%>\n, and `hcounteren.HPM21`\n<%- end -%>\n<%- end -%>\nas follows:\n\n<%- if ext?(", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d8a2ac0e", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter21.yaml", + "section": "mhpmcounter21.COUNT", + "text": "CSR mhpmcounter21 field COUNT (bits=63-0) [when=\"HPM_COUNTER_EN[21] == true\"]\n--\nPerformance counter for event selected in `mhpmevent21.EVENT`.\n\nIncrements every time event occurs unless:\n\n * `mcountinhibit.HPM21` <%- if ext?(:Smcdeleg) -%>or its alias `scountinhibit.HPM21`<%- end -%> is set\n <%- if ext?(:Sscofpmf) -%>\n * `mhpmevent21.MI type: return (HPM_COUNTER_EN[21]) ? CsrFieldType::RWH : CsrFieldType::RO; reset: return (HPM_COUNTER_EN[21]) ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_e67cf134", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter21h.yaml", + "section": "mhpmcounter21h", + "text": "CSR mhpmcounter21h (address=2965, priv=M): Upper half of mhpmcounter21.\n\nThe `hpmcounter21h` CSR is a read-only shadow of this CSR. Access to `hpmcounter21h`\nis controlled with `mcounteren.HPM21`\n<%- if ext?(:S) -%>\n, `scounteren.HPM21`\n<%- if ext?(:H) -%>\n, and `hcounteren.HPM21`\n<%- end -%>\n<%- end -%>\nas follows:\n\n<%- if ext?(:H) -%>\n[%au", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_80bcb50a", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter21h.yaml", + "section": "mhpmcounter21h.COUNT", + "text": "CSR mhpmcounter21h field COUNT (bits=31-0) Upper bits of counter. type: return (HPM_COUNTER_EN[21]) ? CsrFieldType::RWH : CsrFieldType::RO; reset: return (HPM_COUNTER_EN[21]) ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d341070a", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter22.yaml", + "section": "mhpmcounter22", + "text": "CSR mhpmcounter22 (address=2838, priv=M): Programmable hardware performance counter.\n\nThe `hpmcounter22` CSR is a read-only shadow of this CSR. Access to `hpmcounter22`\nis controlled with `mcounteren.HPM22`\n<%- if ext?(:S) -%>\n, `scounteren.HPM22`\n<%- if ext?(:H) -%>\n, and `hcounteren.HPM22`\n<%- end -%>\n<%- end -%>\nas follows:\n\n<%- if ext?(", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_267ed084", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter22.yaml", + "section": "mhpmcounter22.COUNT", + "text": "CSR mhpmcounter22 field COUNT (bits=63-0) [when=\"HPM_COUNTER_EN[22] == true\"]\n--\nPerformance counter for event selected in `mhpmevent22.EVENT`.\n\nIncrements every time event occurs unless:\n\n * `mcountinhibit.HPM22` <%- if ext?(:Smcdeleg) -%>or its alias `scountinhibit.HPM22`<%- end -%> is set\n <%- if ext?(:Sscofpmf) -%>\n * `mhpmevent22.MI type: return (HPM_COUNTER_EN[22]) ? CsrFieldType::RWH : CsrFieldType::RO; reset: return (HPM_COUNTER_EN[22]) ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_23365c30", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter22h.yaml", + "section": "mhpmcounter22h", + "text": "CSR mhpmcounter22h (address=2966, priv=M): Upper half of mhpmcounter22.\n\nThe `hpmcounter22h` CSR is a read-only shadow of this CSR. Access to `hpmcounter22h`\nis controlled with `mcounteren.HPM22`\n<%- if ext?(:S) -%>\n, `scounteren.HPM22`\n<%- if ext?(:H) -%>\n, and `hcounteren.HPM22`\n<%- end -%>\n<%- end -%>\nas follows:\n\n<%- if ext?(:H) -%>\n[%au", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ea8e3bf8", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter22h.yaml", + "section": "mhpmcounter22h.COUNT", + "text": "CSR mhpmcounter22h field COUNT (bits=31-0) Upper bits of counter. type: return (HPM_COUNTER_EN[22]) ? CsrFieldType::RWH : CsrFieldType::RO; reset: return (HPM_COUNTER_EN[22]) ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_1affb4d6", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter23.yaml", + "section": "mhpmcounter23", + "text": "CSR mhpmcounter23 (address=2839, priv=M): Programmable hardware performance counter.\n\nThe `hpmcounter23` CSR is a read-only shadow of this CSR. Access to `hpmcounter23`\nis controlled with `mcounteren.HPM23`\n<%- if ext?(:S) -%>\n, `scounteren.HPM23`\n<%- if ext?(:H) -%>\n, and `hcounteren.HPM23`\n<%- end -%>\n<%- end -%>\nas follows:\n\n<%- if ext?(", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_abe0535b", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter23.yaml", + "section": "mhpmcounter23.COUNT", + "text": "CSR mhpmcounter23 field COUNT (bits=63-0) [when=\"HPM_COUNTER_EN[23] == true\"]\n--\nPerformance counter for event selected in `mhpmevent23.EVENT`.\n\nIncrements every time event occurs unless:\n\n * `mcountinhibit.HPM23` <%- if ext?(:Smcdeleg) -%>or its alias `scountinhibit.HPM23`<%- end -%> is set\n <%- if ext?(:Sscofpmf) -%>\n * `mhpmevent23.MI type: return (HPM_COUNTER_EN[23]) ? CsrFieldType::RWH : CsrFieldType::RO; reset: return (HPM_COUNTER_EN[23]) ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_fe4c06f9", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter23h.yaml", + "section": "mhpmcounter23h", + "text": "CSR mhpmcounter23h (address=2967, priv=M): Upper half of mhpmcounter23.\n\nThe `hpmcounter23h` CSR is a read-only shadow of this CSR. Access to `hpmcounter23h`\nis controlled with `mcounteren.HPM23`\n<%- if ext?(:S) -%>\n, `scounteren.HPM23`\n<%- if ext?(:H) -%>\n, and `hcounteren.HPM23`\n<%- end -%>\n<%- end -%>\nas follows:\n\n<%- if ext?(:H) -%>\n[%au", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_c2a0355f", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter23h.yaml", + "section": "mhpmcounter23h.COUNT", + "text": "CSR mhpmcounter23h field COUNT (bits=31-0) Upper bits of counter. type: return (HPM_COUNTER_EN[23]) ? CsrFieldType::RWH : CsrFieldType::RO; reset: return (HPM_COUNTER_EN[23]) ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_1534a04f", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter24.yaml", + "section": "mhpmcounter24", + "text": "CSR mhpmcounter24 (address=2840, priv=M): Programmable hardware performance counter.\n\nThe `hpmcounter24` CSR is a read-only shadow of this CSR. Access to `hpmcounter24`\nis controlled with `mcounteren.HPM24`\n<%- if ext?(:S) -%>\n, `scounteren.HPM24`\n<%- if ext?(:H) -%>\n, and `hcounteren.HPM24`\n<%- end -%>\n<%- end -%>\nas follows:\n\n<%- if ext?(", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_4140d42e", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter24.yaml", + "section": "mhpmcounter24.COUNT", + "text": "CSR mhpmcounter24 field COUNT (bits=63-0) [when=\"HPM_COUNTER_EN[24] == true\"]\n--\nPerformance counter for event selected in `mhpmevent24.EVENT`.\n\nIncrements every time event occurs unless:\n\n * `mcountinhibit.HPM24` <%- if ext?(:Smcdeleg) -%>or its alias `scountinhibit.HPM24`<%- end -%> is set\n <%- if ext?(:Sscofpmf) -%>\n * `mhpmevent24.MI type: return (HPM_COUNTER_EN[24]) ? CsrFieldType::RWH : CsrFieldType::RO; reset: return (HPM_COUNTER_EN[24]) ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_575a1df4", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter24h.yaml", + "section": "mhpmcounter24h", + "text": "CSR mhpmcounter24h (address=2968, priv=M): Upper half of mhpmcounter24.\n\nThe `hpmcounter24h` CSR is a read-only shadow of this CSR. Access to `hpmcounter24h`\nis controlled with `mcounteren.HPM24`\n<%- if ext?(:S) -%>\n, `scounteren.HPM24`\n<%- if ext?(:H) -%>\n, and `hcounteren.HPM24`\n<%- end -%>\n<%- end -%>\nas follows:\n\n<%- if ext?(:H) -%>\n[%au", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_9bbe13e5", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter24h.yaml", + "section": "mhpmcounter24h.COUNT", + "text": "CSR mhpmcounter24h field COUNT (bits=31-0) Upper bits of counter. type: return (HPM_COUNTER_EN[24]) ? CsrFieldType::RWH : CsrFieldType::RO; reset: return (HPM_COUNTER_EN[24]) ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_eda01b19", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter25.yaml", + "section": "mhpmcounter25", + "text": "CSR mhpmcounter25 (address=2841, priv=M): Programmable hardware performance counter.\n\nThe `hpmcounter25` CSR is a read-only shadow of this CSR. Access to `hpmcounter25`\nis controlled with `mcounteren.HPM25`\n<%- if ext?(:S) -%>\n, `scounteren.HPM25`\n<%- if ext?(:H) -%>\n, and `hcounteren.HPM25`\n<%- end -%>\n<%- end -%>\nas follows:\n\n<%- if ext?(", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_e62ce0fd", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter25.yaml", + "section": "mhpmcounter25.COUNT", + "text": "CSR mhpmcounter25 field COUNT (bits=63-0) [when=\"HPM_COUNTER_EN[25] == true\"]\n--\nPerformance counter for event selected in `mhpmevent25.EVENT`.\n\nIncrements every time event occurs unless:\n\n * `mcountinhibit.HPM25` <%- if ext?(:Smcdeleg) -%>or its alias `scountinhibit.HPM25`<%- end -%> is set\n <%- if ext?(:Sscofpmf) -%>\n * `mhpmevent25.MI type: return (HPM_COUNTER_EN[25]) ? CsrFieldType::RWH : CsrFieldType::RO; reset: return (HPM_COUNTER_EN[25]) ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_c4be1145", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter25h.yaml", + "section": "mhpmcounter25h", + "text": "CSR mhpmcounter25h (address=2969, priv=M): Upper half of mhpmcounter25.\n\nThe `hpmcounter25h` CSR is a read-only shadow of this CSR. Access to `hpmcounter25h`\nis controlled with `mcounteren.HPM25`\n<%- if ext?(:S) -%>\n, `scounteren.HPM25`\n<%- if ext?(:H) -%>\n, and `hcounteren.HPM25`\n<%- end -%>\n<%- end -%>\nas follows:\n\n<%- if ext?(:H) -%>\n[%au", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d7cc8a72", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter25h.yaml", + "section": "mhpmcounter25h.COUNT", + "text": "CSR mhpmcounter25h field COUNT (bits=31-0) Upper bits of counter. type: return (HPM_COUNTER_EN[25]) ? CsrFieldType::RWH : CsrFieldType::RO; reset: return (HPM_COUNTER_EN[25]) ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_fc624b18", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter26.yaml", + "section": "mhpmcounter26", + "text": "CSR mhpmcounter26 (address=2842, priv=M): Programmable hardware performance counter.\n\nThe `hpmcounter26` CSR is a read-only shadow of this CSR. Access to `hpmcounter26`\nis controlled with `mcounteren.HPM26`\n<%- if ext?(:S) -%>\n, `scounteren.HPM26`\n<%- if ext?(:H) -%>\n, and `hcounteren.HPM26`\n<%- end -%>\n<%- end -%>\nas follows:\n\n<%- if ext?(", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_f70d9285", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter26.yaml", + "section": "mhpmcounter26.COUNT", + "text": "CSR mhpmcounter26 field COUNT (bits=63-0) [when=\"HPM_COUNTER_EN[26] == true\"]\n--\nPerformance counter for event selected in `mhpmevent26.EVENT`.\n\nIncrements every time event occurs unless:\n\n * `mcountinhibit.HPM26` <%- if ext?(:Smcdeleg) -%>or its alias `scountinhibit.HPM26`<%- end -%> is set\n <%- if ext?(:Sscofpmf) -%>\n * `mhpmevent26.MI type: return (HPM_COUNTER_EN[26]) ? CsrFieldType::RWH : CsrFieldType::RO; reset: return (HPM_COUNTER_EN[26]) ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_3a7e73b5", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter26h.yaml", + "section": "mhpmcounter26h", + "text": "CSR mhpmcounter26h (address=2970, priv=M): Upper half of mhpmcounter26.\n\nThe `hpmcounter26h` CSR is a read-only shadow of this CSR. Access to `hpmcounter26h`\nis controlled with `mcounteren.HPM26`\n<%- if ext?(:S) -%>\n, `scounteren.HPM26`\n<%- if ext?(:H) -%>\n, and `hcounteren.HPM26`\n<%- end -%>\n<%- end -%>\nas follows:\n\n<%- if ext?(:H) -%>\n[%au", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_8f84d481", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter26h.yaml", + "section": "mhpmcounter26h.COUNT", + "text": "CSR mhpmcounter26h field COUNT (bits=31-0) Upper bits of counter. type: return (HPM_COUNTER_EN[26]) ? CsrFieldType::RWH : CsrFieldType::RO; reset: return (HPM_COUNTER_EN[26]) ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_87308345", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter27.yaml", + "section": "mhpmcounter27", + "text": "CSR mhpmcounter27 (address=2843, priv=M): Programmable hardware performance counter.\n\nThe `hpmcounter27` CSR is a read-only shadow of this CSR. Access to `hpmcounter27`\nis controlled with `mcounteren.HPM27`\n<%- if ext?(:S) -%>\n, `scounteren.HPM27`\n<%- if ext?(:H) -%>\n, and `hcounteren.HPM27`\n<%- end -%>\n<%- end -%>\nas follows:\n\n<%- if ext?(", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_0bd515c4", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter27.yaml", + "section": "mhpmcounter27.COUNT", + "text": "CSR mhpmcounter27 field COUNT (bits=63-0) [when=\"HPM_COUNTER_EN[27] == true\"]\n--\nPerformance counter for event selected in `mhpmevent27.EVENT`.\n\nIncrements every time event occurs unless:\n\n * `mcountinhibit.HPM27` <%- if ext?(:Smcdeleg) -%>or its alias `scountinhibit.HPM27`<%- end -%> is set\n <%- if ext?(:Sscofpmf) -%>\n * `mhpmevent27.MI type: return (HPM_COUNTER_EN[27]) ? CsrFieldType::RWH : CsrFieldType::RO; reset: return (HPM_COUNTER_EN[27]) ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_fccefebf", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter27h.yaml", + "section": "mhpmcounter27h", + "text": "CSR mhpmcounter27h (address=2971, priv=M): Upper half of mhpmcounter27.\n\nThe `hpmcounter27h` CSR is a read-only shadow of this CSR. Access to `hpmcounter27h`\nis controlled with `mcounteren.HPM27`\n<%- if ext?(:S) -%>\n, `scounteren.HPM27`\n<%- if ext?(:H) -%>\n, and `hcounteren.HPM27`\n<%- end -%>\n<%- end -%>\nas follows:\n\n<%- if ext?(:H) -%>\n[%au", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_afaff117", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter27h.yaml", + "section": "mhpmcounter27h.COUNT", + "text": "CSR mhpmcounter27h field COUNT (bits=31-0) Upper bits of counter. type: return (HPM_COUNTER_EN[27]) ? CsrFieldType::RWH : CsrFieldType::RO; reset: return (HPM_COUNTER_EN[27]) ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_3a60908d", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter28.yaml", + "section": "mhpmcounter28", + "text": "CSR mhpmcounter28 (address=2844, priv=M): Programmable hardware performance counter.\n\nThe `hpmcounter28` CSR is a read-only shadow of this CSR. Access to `hpmcounter28`\nis controlled with `mcounteren.HPM28`\n<%- if ext?(:S) -%>\n, `scounteren.HPM28`\n<%- if ext?(:H) -%>\n, and `hcounteren.HPM28`\n<%- end -%>\n<%- end -%>\nas follows:\n\n<%- if ext?(", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_93a5e639", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter28.yaml", + "section": "mhpmcounter28.COUNT", + "text": "CSR mhpmcounter28 field COUNT (bits=63-0) [when=\"HPM_COUNTER_EN[28] == true\"]\n--\nPerformance counter for event selected in `mhpmevent28.EVENT`.\n\nIncrements every time event occurs unless:\n\n * `mcountinhibit.HPM28` <%- if ext?(:Smcdeleg) -%>or its alias `scountinhibit.HPM28`<%- end -%> is set\n <%- if ext?(:Sscofpmf) -%>\n * `mhpmevent28.MI type: return (HPM_COUNTER_EN[28]) ? CsrFieldType::RWH : CsrFieldType::RO; reset: return (HPM_COUNTER_EN[28]) ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_31c8ea87", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter28h.yaml", + "section": "mhpmcounter28h", + "text": "CSR mhpmcounter28h (address=2972, priv=M): Upper half of mhpmcounter28.\n\nThe `hpmcounter28h` CSR is a read-only shadow of this CSR. Access to `hpmcounter28h`\nis controlled with `mcounteren.HPM28`\n<%- if ext?(:S) -%>\n, `scounteren.HPM28`\n<%- if ext?(:H) -%>\n, and `hcounteren.HPM28`\n<%- end -%>\n<%- end -%>\nas follows:\n\n<%- if ext?(:H) -%>\n[%au", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_94ea2b8c", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter28h.yaml", + "section": "mhpmcounter28h.COUNT", + "text": "CSR mhpmcounter28h field COUNT (bits=31-0) Upper bits of counter. type: return (HPM_COUNTER_EN[28]) ? CsrFieldType::RWH : CsrFieldType::RO; reset: return (HPM_COUNTER_EN[28]) ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d9019fd5", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter29.yaml", + "section": "mhpmcounter29", + "text": "CSR mhpmcounter29 (address=2845, priv=M): Programmable hardware performance counter.\n\nThe `hpmcounter29` CSR is a read-only shadow of this CSR. Access to `hpmcounter29`\nis controlled with `mcounteren.HPM29`\n<%- if ext?(:S) -%>\n, `scounteren.HPM29`\n<%- if ext?(:H) -%>\n, and `hcounteren.HPM29`\n<%- end -%>\n<%- end -%>\nas follows:\n\n<%- if ext?(", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_b9c5568d", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter29.yaml", + "section": "mhpmcounter29.COUNT", + "text": "CSR mhpmcounter29 field COUNT (bits=63-0) [when=\"HPM_COUNTER_EN[29] == true\"]\n--\nPerformance counter for event selected in `mhpmevent29.EVENT`.\n\nIncrements every time event occurs unless:\n\n * `mcountinhibit.HPM29` <%- if ext?(:Smcdeleg) -%>or its alias `scountinhibit.HPM29`<%- end -%> is set\n <%- if ext?(:Sscofpmf) -%>\n * `mhpmevent29.MI type: return (HPM_COUNTER_EN[29]) ? CsrFieldType::RWH : CsrFieldType::RO; reset: return (HPM_COUNTER_EN[29]) ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_dd4b2e53", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter29h.yaml", + "section": "mhpmcounter29h", + "text": "CSR mhpmcounter29h (address=2973, priv=M): Upper half of mhpmcounter29.\n\nThe `hpmcounter29h` CSR is a read-only shadow of this CSR. Access to `hpmcounter29h`\nis controlled with `mcounteren.HPM29`\n<%- if ext?(:S) -%>\n, `scounteren.HPM29`\n<%- if ext?(:H) -%>\n, and `hcounteren.HPM29`\n<%- end -%>\n<%- end -%>\nas follows:\n\n<%- if ext?(:H) -%>\n[%au", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_075efb63", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter29h.yaml", + "section": "mhpmcounter29h.COUNT", + "text": "CSR mhpmcounter29h field COUNT (bits=31-0) Upper bits of counter. type: return (HPM_COUNTER_EN[29]) ? CsrFieldType::RWH : CsrFieldType::RO; reset: return (HPM_COUNTER_EN[29]) ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_47078db1", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter3.yaml", + "section": "mhpmcounter3", + "text": "CSR mhpmcounter3 (address=2819, priv=M): Programmable hardware performance counter.\n\nThe `hpmcounter3` CSR is a read-only shadow of this CSR. Access to `hpmcounter3`\nis controlled with `mcounteren.HPM3`\n<%- if ext?(:S) -%>\n, `scounteren.HPM3`\n<%- if ext?(:H) -%>\n, and `hcounteren.HPM3`\n<%- end -%>\n<%- end -%>\nas follows:\n\n<%- if ext?(:H) -", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_230efdec", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter3.yaml", + "section": "mhpmcounter3.COUNT", + "text": "CSR mhpmcounter3 field COUNT (bits=63-0) [when=\"HPM_COUNTER_EN[3] == true\"]\n--\nPerformance counter for event selected in `mhpmevent3.EVENT`.\n\nIncrements every time event occurs unless:\n\n * `mcountinhibit.HPM3` <%- if ext?(:Smcdeleg) -%>or its alias `scountinhibit.HPM3`<%- end -%> is set\n <%- if ext?(:Sscofpmf) -%>\n * `mhpmevent3.MINH` i type: return (HPM_COUNTER_EN[3]) ? CsrFieldType::RWH : CsrFieldType::RO; reset: return (HPM_COUNTER_EN[3]) ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ab721381", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter30.yaml", + "section": "mhpmcounter30", + "text": "CSR mhpmcounter30 (address=2846, priv=M): Programmable hardware performance counter.\n\nThe `hpmcounter30` CSR is a read-only shadow of this CSR. Access to `hpmcounter30`\nis controlled with `mcounteren.HPM30`\n<%- if ext?(:S) -%>\n, `scounteren.HPM30`\n<%- if ext?(:H) -%>\n, and `hcounteren.HPM30`\n<%- end -%>\n<%- end -%>\nas follows:\n\n<%- if ext?(", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_8183feb9", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter30.yaml", + "section": "mhpmcounter30.COUNT", + "text": "CSR mhpmcounter30 field COUNT (bits=63-0) [when=\"HPM_COUNTER_EN[30] == true\"]\n--\nPerformance counter for event selected in `mhpmevent30.EVENT`.\n\nIncrements every time event occurs unless:\n\n * `mcountinhibit.HPM30` <%- if ext?(:Smcdeleg) -%>or its alias `scountinhibit.HPM30`<%- end -%> is set\n <%- if ext?(:Sscofpmf) -%>\n * `mhpmevent30.MI type: return (HPM_COUNTER_EN[30]) ? CsrFieldType::RWH : CsrFieldType::RO; reset: return (HPM_COUNTER_EN[30]) ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_e72faed2", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter30h.yaml", + "section": "mhpmcounter30h", + "text": "CSR mhpmcounter30h (address=2974, priv=M): Upper half of mhpmcounter30.\n\nThe `hpmcounter30h` CSR is a read-only shadow of this CSR. Access to `hpmcounter30h`\nis controlled with `mcounteren.HPM30`\n<%- if ext?(:S) -%>\n, `scounteren.HPM30`\n<%- if ext?(:H) -%>\n, and `hcounteren.HPM30`\n<%- end -%>\n<%- end -%>\nas follows:\n\n<%- if ext?(:H) -%>\n[%au", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_fe25fae7", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter30h.yaml", + "section": "mhpmcounter30h.COUNT", + "text": "CSR mhpmcounter30h field COUNT (bits=31-0) Upper bits of counter. type: return (HPM_COUNTER_EN[30]) ? CsrFieldType::RWH : CsrFieldType::RO; reset: return (HPM_COUNTER_EN[30]) ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_cfe1a70e", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter31.yaml", + "section": "mhpmcounter31", + "text": "CSR mhpmcounter31 (address=2847, priv=M): Programmable hardware performance counter.\n\nThe `hpmcounter31` CSR is a read-only shadow of this CSR. Access to `hpmcounter31`\nis controlled with `mcounteren.HPM31`\n<%- if ext?(:S) -%>\n, `scounteren.HPM31`\n<%- if ext?(:H) -%>\n, and `hcounteren.HPM31`\n<%- end -%>\n<%- end -%>\nas follows:\n\n<%- if ext?(", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_192f0e6f", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter31.yaml", + "section": "mhpmcounter31.COUNT", + "text": "CSR mhpmcounter31 field COUNT (bits=63-0) [when=\"HPM_COUNTER_EN[31] == true\"]\n--\nPerformance counter for event selected in `mhpmevent31.EVENT`.\n\nIncrements every time event occurs unless:\n\n * `mcountinhibit.HPM31` <%- if ext?(:Smcdeleg) -%>or its alias `scountinhibit.HPM31`<%- end -%> is set\n <%- if ext?(:Sscofpmf) -%>\n * `mhpmevent31.MI type: return (HPM_COUNTER_EN[31]) ? CsrFieldType::RWH : CsrFieldType::RO; reset: return (HPM_COUNTER_EN[31]) ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_90e6e275", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter31h.yaml", + "section": "mhpmcounter31h", + "text": "CSR mhpmcounter31h (address=2975, priv=M): Upper half of mhpmcounter31.\n\nThe `hpmcounter31h` CSR is a read-only shadow of this CSR. Access to `hpmcounter31h`\nis controlled with `mcounteren.HPM31`\n<%- if ext?(:S) -%>\n, `scounteren.HPM31`\n<%- if ext?(:H) -%>\n, and `hcounteren.HPM31`\n<%- end -%>\n<%- end -%>\nas follows:\n\n<%- if ext?(:H) -%>\n[%au", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_0e4d86f4", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter31h.yaml", + "section": "mhpmcounter31h.COUNT", + "text": "CSR mhpmcounter31h field COUNT (bits=31-0) Upper bits of counter. type: return (HPM_COUNTER_EN[31]) ? CsrFieldType::RWH : CsrFieldType::RO; reset: return (HPM_COUNTER_EN[31]) ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_3282f649", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter3h.yaml", + "section": "mhpmcounter3h", + "text": "CSR mhpmcounter3h (address=2947, priv=M): Upper half of mhpmcounter3.\n\nThe `hpmcounter3h` CSR is a read-only shadow of this CSR. Access to `hpmcounter3h`\nis controlled with `mcounteren.HPM3`\n<%- if ext?(:S) -%>\n, `scounteren.HPM3`\n<%- if ext?(:H) -%>\n, and `hcounteren.HPM3`\n<%- end -%>\n<%- end -%>\nas follows:\n\n<%- if ext?(:H) -%>\n[%autowidt", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_5e18aafd", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter3h.yaml", + "section": "mhpmcounter3h.COUNT", + "text": "CSR mhpmcounter3h field COUNT (bits=31-0) Upper bits of counter. type: return (HPM_COUNTER_EN[3]) ? CsrFieldType::RWH : CsrFieldType::RO; reset: return (HPM_COUNTER_EN[3]) ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_473d28e8", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter4.yaml", + "section": "mhpmcounter4", + "text": "CSR mhpmcounter4 (address=2820, priv=M): Programmable hardware performance counter.\n\nThe `hpmcounter4` CSR is a read-only shadow of this CSR. Access to `hpmcounter4`\nis controlled with `mcounteren.HPM4`\n<%- if ext?(:S) -%>\n, `scounteren.HPM4`\n<%- if ext?(:H) -%>\n, and `hcounteren.HPM4`\n<%- end -%>\n<%- end -%>\nas follows:\n\n<%- if ext?(:H) -", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_dd06abea", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter4.yaml", + "section": "mhpmcounter4.COUNT", + "text": "CSR mhpmcounter4 field COUNT (bits=63-0) [when=\"HPM_COUNTER_EN[4] == true\"]\n--\nPerformance counter for event selected in `mhpmevent4.EVENT`.\n\nIncrements every time event occurs unless:\n\n * `mcountinhibit.HPM4` <%- if ext?(:Smcdeleg) -%>or its alias `scountinhibit.HPM4`<%- end -%> is set\n <%- if ext?(:Sscofpmf) -%>\n * `mhpmevent4.MINH` i type: return (HPM_COUNTER_EN[4]) ? CsrFieldType::RWH : CsrFieldType::RO; reset: return (HPM_COUNTER_EN[4]) ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_cbabff7b", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter4h.yaml", + "section": "mhpmcounter4h", + "text": "CSR mhpmcounter4h (address=2948, priv=M): Upper half of mhpmcounter4.\n\nThe `hpmcounter4h` CSR is a read-only shadow of this CSR. Access to `hpmcounter4h`\nis controlled with `mcounteren.HPM4`\n<%- if ext?(:S) -%>\n, `scounteren.HPM4`\n<%- if ext?(:H) -%>\n, and `hcounteren.HPM4`\n<%- end -%>\n<%- end -%>\nas follows:\n\n<%- if ext?(:H) -%>\n[%autowidt", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_acb39984", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter4h.yaml", + "section": "mhpmcounter4h.COUNT", + "text": "CSR mhpmcounter4h field COUNT (bits=31-0) Upper bits of counter. type: return (HPM_COUNTER_EN[4]) ? CsrFieldType::RWH : CsrFieldType::RO; reset: return (HPM_COUNTER_EN[4]) ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_c332b573", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter5.yaml", + "section": "mhpmcounter5", + "text": "CSR mhpmcounter5 (address=2821, priv=M): Programmable hardware performance counter.\n\nThe `hpmcounter5` CSR is a read-only shadow of this CSR. Access to `hpmcounter5`\nis controlled with `mcounteren.HPM5`\n<%- if ext?(:S) -%>\n, `scounteren.HPM5`\n<%- if ext?(:H) -%>\n, and `hcounteren.HPM5`\n<%- end -%>\n<%- end -%>\nas follows:\n\n<%- if ext?(:H) -", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_dacd49a3", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter5.yaml", + "section": "mhpmcounter5.COUNT", + "text": "CSR mhpmcounter5 field COUNT (bits=63-0) [when=\"HPM_COUNTER_EN[5] == true\"]\n--\nPerformance counter for event selected in `mhpmevent5.EVENT`.\n\nIncrements every time event occurs unless:\n\n * `mcountinhibit.HPM5` <%- if ext?(:Smcdeleg) -%>or its alias `scountinhibit.HPM5`<%- end -%> is set\n <%- if ext?(:Sscofpmf) -%>\n * `mhpmevent5.MINH` i type: return (HPM_COUNTER_EN[5]) ? CsrFieldType::RWH : CsrFieldType::RO; reset: return (HPM_COUNTER_EN[5]) ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_793b96e2", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter5h.yaml", + "section": "mhpmcounter5h", + "text": "CSR mhpmcounter5h (address=2949, priv=M): Upper half of mhpmcounter5.\n\nThe `hpmcounter5h` CSR is a read-only shadow of this CSR. Access to `hpmcounter5h`\nis controlled with `mcounteren.HPM5`\n<%- if ext?(:S) -%>\n, `scounteren.HPM5`\n<%- if ext?(:H) -%>\n, and `hcounteren.HPM5`\n<%- end -%>\n<%- end -%>\nas follows:\n\n<%- if ext?(:H) -%>\n[%autowidt", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_fbda6d15", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter5h.yaml", + "section": "mhpmcounter5h.COUNT", + "text": "CSR mhpmcounter5h field COUNT (bits=31-0) Upper bits of counter. type: return (HPM_COUNTER_EN[5]) ? CsrFieldType::RWH : CsrFieldType::RO; reset: return (HPM_COUNTER_EN[5]) ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_f2449ea8", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter6.yaml", + "section": "mhpmcounter6", + "text": "CSR mhpmcounter6 (address=2822, priv=M): Programmable hardware performance counter.\n\nThe `hpmcounter6` CSR is a read-only shadow of this CSR. Access to `hpmcounter6`\nis controlled with `mcounteren.HPM6`\n<%- if ext?(:S) -%>\n, `scounteren.HPM6`\n<%- if ext?(:H) -%>\n, and `hcounteren.HPM6`\n<%- end -%>\n<%- end -%>\nas follows:\n\n<%- if ext?(:H) -", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ae3d069c", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter6.yaml", + "section": "mhpmcounter6.COUNT", + "text": "CSR mhpmcounter6 field COUNT (bits=63-0) [when=\"HPM_COUNTER_EN[6] == true\"]\n--\nPerformance counter for event selected in `mhpmevent6.EVENT`.\n\nIncrements every time event occurs unless:\n\n * `mcountinhibit.HPM6` <%- if ext?(:Smcdeleg) -%>or its alias `scountinhibit.HPM6`<%- end -%> is set\n <%- if ext?(:Sscofpmf) -%>\n * `mhpmevent6.MINH` i type: return (HPM_COUNTER_EN[6]) ? CsrFieldType::RWH : CsrFieldType::RO; reset: return (HPM_COUNTER_EN[6]) ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_5b772378", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter6h.yaml", + "section": "mhpmcounter6h", + "text": "CSR mhpmcounter6h (address=2950, priv=M): Upper half of mhpmcounter6.\n\nThe `hpmcounter6h` CSR is a read-only shadow of this CSR. Access to `hpmcounter6h`\nis controlled with `mcounteren.HPM6`\n<%- if ext?(:S) -%>\n, `scounteren.HPM6`\n<%- if ext?(:H) -%>\n, and `hcounteren.HPM6`\n<%- end -%>\n<%- end -%>\nas follows:\n\n<%- if ext?(:H) -%>\n[%autowidt", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ac191460", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter6h.yaml", + "section": "mhpmcounter6h.COUNT", + "text": "CSR mhpmcounter6h field COUNT (bits=31-0) Upper bits of counter. type: return (HPM_COUNTER_EN[6]) ? CsrFieldType::RWH : CsrFieldType::RO; reset: return (HPM_COUNTER_EN[6]) ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_0e5977ea", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter7.yaml", + "section": "mhpmcounter7", + "text": "CSR mhpmcounter7 (address=2823, priv=M): Programmable hardware performance counter.\n\nThe `hpmcounter7` CSR is a read-only shadow of this CSR. Access to `hpmcounter7`\nis controlled with `mcounteren.HPM7`\n<%- if ext?(:S) -%>\n, `scounteren.HPM7`\n<%- if ext?(:H) -%>\n, and `hcounteren.HPM7`\n<%- end -%>\n<%- end -%>\nas follows:\n\n<%- if ext?(:H) -", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_9fb47fa0", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter7.yaml", + "section": "mhpmcounter7.COUNT", + "text": "CSR mhpmcounter7 field COUNT (bits=63-0) [when=\"HPM_COUNTER_EN[7] == true\"]\n--\nPerformance counter for event selected in `mhpmevent7.EVENT`.\n\nIncrements every time event occurs unless:\n\n * `mcountinhibit.HPM7` <%- if ext?(:Smcdeleg) -%>or its alias `scountinhibit.HPM7`<%- end -%> is set\n <%- if ext?(:Sscofpmf) -%>\n * `mhpmevent7.MINH` i type: return (HPM_COUNTER_EN[7]) ? CsrFieldType::RWH : CsrFieldType::RO; reset: return (HPM_COUNTER_EN[7]) ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_5d864663", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter7h.yaml", + "section": "mhpmcounter7h", + "text": "CSR mhpmcounter7h (address=2951, priv=M): Upper half of mhpmcounter7.\n\nThe `hpmcounter7h` CSR is a read-only shadow of this CSR. Access to `hpmcounter7h`\nis controlled with `mcounteren.HPM7`\n<%- if ext?(:S) -%>\n, `scounteren.HPM7`\n<%- if ext?(:H) -%>\n, and `hcounteren.HPM7`\n<%- end -%>\n<%- end -%>\nas follows:\n\n<%- if ext?(:H) -%>\n[%autowidt", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_4161cdb8", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter7h.yaml", + "section": "mhpmcounter7h.COUNT", + "text": "CSR mhpmcounter7h field COUNT (bits=31-0) Upper bits of counter. type: return (HPM_COUNTER_EN[7]) ? CsrFieldType::RWH : CsrFieldType::RO; reset: return (HPM_COUNTER_EN[7]) ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_8446a4b8", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter8.yaml", + "section": "mhpmcounter8", + "text": "CSR mhpmcounter8 (address=2824, priv=M): Programmable hardware performance counter.\n\nThe `hpmcounter8` CSR is a read-only shadow of this CSR. Access to `hpmcounter8`\nis controlled with `mcounteren.HPM8`\n<%- if ext?(:S) -%>\n, `scounteren.HPM8`\n<%- if ext?(:H) -%>\n, and `hcounteren.HPM8`\n<%- end -%>\n<%- end -%>\nas follows:\n\n<%- if ext?(:H) -", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_f003f61e", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter8.yaml", + "section": "mhpmcounter8.COUNT", + "text": "CSR mhpmcounter8 field COUNT (bits=63-0) [when=\"HPM_COUNTER_EN[8] == true\"]\n--\nPerformance counter for event selected in `mhpmevent8.EVENT`.\n\nIncrements every time event occurs unless:\n\n * `mcountinhibit.HPM8` <%- if ext?(:Smcdeleg) -%>or its alias `scountinhibit.HPM8`<%- end -%> is set\n <%- if ext?(:Sscofpmf) -%>\n * `mhpmevent8.MINH` i type: return (HPM_COUNTER_EN[8]) ? CsrFieldType::RWH : CsrFieldType::RO; reset: return (HPM_COUNTER_EN[8]) ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_79eab35f", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter8h.yaml", + "section": "mhpmcounter8h", + "text": "CSR mhpmcounter8h (address=2952, priv=M): Upper half of mhpmcounter8.\n\nThe `hpmcounter8h` CSR is a read-only shadow of this CSR. Access to `hpmcounter8h`\nis controlled with `mcounteren.HPM8`\n<%- if ext?(:S) -%>\n, `scounteren.HPM8`\n<%- if ext?(:H) -%>\n, and `hcounteren.HPM8`\n<%- end -%>\n<%- end -%>\nas follows:\n\n<%- if ext?(:H) -%>\n[%autowidt", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_1f98b610", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter8h.yaml", + "section": "mhpmcounter8h.COUNT", + "text": "CSR mhpmcounter8h field COUNT (bits=31-0) Upper bits of counter. type: return (HPM_COUNTER_EN[8]) ? CsrFieldType::RWH : CsrFieldType::RO; reset: return (HPM_COUNTER_EN[8]) ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ad84653a", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter9.yaml", + "section": "mhpmcounter9", + "text": "CSR mhpmcounter9 (address=2825, priv=M): Programmable hardware performance counter.\n\nThe `hpmcounter9` CSR is a read-only shadow of this CSR. Access to `hpmcounter9`\nis controlled with `mcounteren.HPM9`\n<%- if ext?(:S) -%>\n, `scounteren.HPM9`\n<%- if ext?(:H) -%>\n, and `hcounteren.HPM9`\n<%- end -%>\n<%- end -%>\nas follows:\n\n<%- if ext?(:H) -", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_b35b865c", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter9.yaml", + "section": "mhpmcounter9.COUNT", + "text": "CSR mhpmcounter9 field COUNT (bits=63-0) [when=\"HPM_COUNTER_EN[9] == true\"]\n--\nPerformance counter for event selected in `mhpmevent9.EVENT`.\n\nIncrements every time event occurs unless:\n\n * `mcountinhibit.HPM9` <%- if ext?(:Smcdeleg) -%>or its alias `scountinhibit.HPM9`<%- end -%> is set\n <%- if ext?(:Sscofpmf) -%>\n * `mhpmevent9.MINH` i type: return (HPM_COUNTER_EN[9]) ? CsrFieldType::RWH : CsrFieldType::RO; reset: return (HPM_COUNTER_EN[9]) ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_bf292e0d", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter9h.yaml", + "section": "mhpmcounter9h", + "text": "CSR mhpmcounter9h (address=2953, priv=M): Upper half of mhpmcounter9.\n\nThe `hpmcounter9h` CSR is a read-only shadow of this CSR. Access to `hpmcounter9h`\nis controlled with `mcounteren.HPM9`\n<%- if ext?(:S) -%>\n, `scounteren.HPM9`\n<%- if ext?(:H) -%>\n, and `hcounteren.HPM9`\n<%- end -%>\n<%- end -%>\nas follows:\n\n<%- if ext?(:H) -%>\n[%autowidt", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_6ddcee30", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmcounter9h.yaml", + "section": "mhpmcounter9h.COUNT", + "text": "CSR mhpmcounter9h field COUNT (bits=31-0) Upper bits of counter. type: return (HPM_COUNTER_EN[9]) ? CsrFieldType::RWH : CsrFieldType::RO; reset: return (HPM_COUNTER_EN[9]) ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_a81dc203", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent10.yaml", + "section": "mhpmevent10", + "text": "CSR mhpmevent10 (address=810, priv=M): Programmable hardware performance counter event selector\n<% if ext?(:Sscofpmf) %> and overflow/filtering control<% end %>", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_f80d6041", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent10.yaml", + "section": "mhpmevent10.OF", + "text": "CSR mhpmevent10 field OF (bits=63) Overflow status and interrupt disable.\n\nThe OF bit is set when the corresponding hpmcounter overflows, and remains set until written by\nsoftware. Since hpmcounter values are unsigned values, overflow is defined as unsigned\noverflow of the implemented counter bits.\n\nThe OF bit is sticky; it stays set type: if (HPM_COUNTER_EN[10]) { reset: if (HPM_COUNTER_EN[10]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_16265ad0", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent10.yaml", + "section": "mhpmevent10.MINH", + "text": "CSR mhpmevent10 field MINH (bits=62) When set, mhpmcounter10 does not increment while the hart in operating in M-mode. type: if (HPM_COUNTER_EN[10]) { reset: if (HPM_COUNTER_EN[10]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_2019a82e", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent10.yaml", + "section": "mhpmevent10.SINH", + "text": "CSR mhpmevent10 field SINH (bits=61) When set, mhpmcounter10 does not increment while the hart in operating in (H)S-mode. type: if (HPM_COUNTER_EN[10] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { reset: if (HPM_COUNTER_EN[10] && implemented?(ExtensionName::S)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_a17ec3a9", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent10.yaml", + "section": "mhpmevent10.UINH", + "text": "CSR mhpmevent10 field UINH (bits=60) When set, mhpmcounter10 does not increment while the hart in operating in U-mode. type: if (HPM_COUNTER_EN[10] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { reset: if (HPM_COUNTER_EN[10] && implemented?(ExtensionName::U)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_9b267572", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent10.yaml", + "section": "mhpmevent10.VSINH", + "text": "CSR mhpmevent10 field VSINH (bits=59) When set, mhpmcounter10 does not increment while the hart in operating in VS-mode. type: if ((HPM_COUNTER_EN[10]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if (HPM_COUNTER_EN[10] && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_7e7b7f66", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent10.yaml", + "section": "mhpmevent10.VUINH", + "text": "CSR mhpmevent10 field VUINH (bits=58) When set, mhpmcounter10 does not increment while the hart in operating in VU-mode. type: if (HPM_COUNTER_EN[10] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[10]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_49ecd6d7", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent10.yaml", + "section": "mhpmevent10.EVENT", + "text": "CSR mhpmevent10 field EVENT (bits=57-0) Event selector for performance counter `mhpmcounter10`. type: if (HPM_COUNTER_EN[10]) { reset: if (HPM_COUNTER_EN[10]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_7ebc40df", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent10h.yaml", + "section": "mhpmevent10h", + "text": "CSR mhpmevent10h (address=1834, priv=M): Alias of `mhpmevent10`[63:32].\n\nIntroduced with the `Sscofpmf` extension. Prior to that, there was no way to access the upper\n32-bits of `mhpmevent#{hpm_num}`.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_e393686a", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent10h.yaml", + "section": "mhpmevent10h.OF", + "text": "CSR mhpmevent10h field OF (bits=31) Alias of mhpmevent10.OF. type: if (HPM_COUNTER_EN[10]) { reset: if (HPM_COUNTER_EN[10]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_22f9f7db", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent10h.yaml", + "section": "mhpmevent10h.MINH", + "text": "CSR mhpmevent10h field MINH (bits=30) Alias of mhpmevent10.MINH. type: if (HPM_COUNTER_EN[10]) { reset: if (HPM_COUNTER_EN[10]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_18b15605", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent10h.yaml", + "section": "mhpmevent10h.SINH", + "text": "CSR mhpmevent10h field SINH (bits=29) Alias of mhpmevent10.SINH. type: if ((HPM_COUNTER_EN[10]) && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { reset: if ((HPM_COUNTER_EN[10]) && implemented?(ExtensionName::S)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_bbfbe304", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent10h.yaml", + "section": "mhpmevent10h.UINH", + "text": "CSR mhpmevent10h field UINH (bits=28) Alias of mhpmevent10.UINH. type: if ((HPM_COUNTER_EN[10]) && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { reset: if ((HPM_COUNTER_EN[10]) && implemented?(ExtensionName::U)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_88ece637", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent10h.yaml", + "section": "mhpmevent10h.VSINH", + "text": "CSR mhpmevent10h field VSINH (bits=27) Alias of mhpmevent10.VSINH. type: if ((HPM_COUNTER_EN[10]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[10]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_c383465a", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent10h.yaml", + "section": "mhpmevent10h.VUINH", + "text": "CSR mhpmevent10h field VUINH (bits=26) Alias of mhpmevent10.VUINH. type: if ((HPM_COUNTER_EN[10]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[10]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d894316e", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent10h.yaml", + "section": "mhpmevent10h.EVENT", + "text": "CSR mhpmevent10h field EVENT (bits=25-0) High part of event selector for performance counter `mhpmcounter10`. type: if (HPM_COUNTER_EN[10]) { reset: if (HPM_COUNTER_EN[10]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_dbe7154c", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent11.yaml", + "section": "mhpmevent11", + "text": "CSR mhpmevent11 (address=811, priv=M): Programmable hardware performance counter event selector\n<% if ext?(:Sscofpmf) %> and overflow/filtering control<% end %>", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_7e1f81a9", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent11.yaml", + "section": "mhpmevent11.OF", + "text": "CSR mhpmevent11 field OF (bits=63) Overflow status and interrupt disable.\n\nThe OF bit is set when the corresponding hpmcounter overflows, and remains set until written by\nsoftware. Since hpmcounter values are unsigned values, overflow is defined as unsigned\noverflow of the implemented counter bits.\n\nThe OF bit is sticky; it stays set type: if (HPM_COUNTER_EN[11]) { reset: if (HPM_COUNTER_EN[11]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_bd4bb42c", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent11.yaml", + "section": "mhpmevent11.MINH", + "text": "CSR mhpmevent11 field MINH (bits=62) When set, mhpmcounter11 does not increment while the hart in operating in M-mode. type: if (HPM_COUNTER_EN[11]) { reset: if (HPM_COUNTER_EN[11]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d0f8c168", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent11.yaml", + "section": "mhpmevent11.SINH", + "text": "CSR mhpmevent11 field SINH (bits=61) When set, mhpmcounter11 does not increment while the hart in operating in (H)S-mode. type: if (HPM_COUNTER_EN[11] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { reset: if (HPM_COUNTER_EN[11] && implemented?(ExtensionName::S)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_743631b1", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent11.yaml", + "section": "mhpmevent11.UINH", + "text": "CSR mhpmevent11 field UINH (bits=60) When set, mhpmcounter11 does not increment while the hart in operating in U-mode. type: if (HPM_COUNTER_EN[11] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { reset: if (HPM_COUNTER_EN[11] && implemented?(ExtensionName::U)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_a694b806", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent11.yaml", + "section": "mhpmevent11.VSINH", + "text": "CSR mhpmevent11 field VSINH (bits=59) When set, mhpmcounter11 does not increment while the hart in operating in VS-mode. type: if ((HPM_COUNTER_EN[11]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if (HPM_COUNTER_EN[11] && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_fc7c686f", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent11.yaml", + "section": "mhpmevent11.VUINH", + "text": "CSR mhpmevent11 field VUINH (bits=58) When set, mhpmcounter11 does not increment while the hart in operating in VU-mode. type: if (HPM_COUNTER_EN[11] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[11]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_891a545c", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent11.yaml", + "section": "mhpmevent11.EVENT", + "text": "CSR mhpmevent11 field EVENT (bits=57-0) Event selector for performance counter `mhpmcounter11`. type: if (HPM_COUNTER_EN[11]) { reset: if (HPM_COUNTER_EN[11]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_c95e9a0c", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent11h.yaml", + "section": "mhpmevent11h", + "text": "CSR mhpmevent11h (address=1835, priv=M): Alias of `mhpmevent11`[63:32].\n\nIntroduced with the `Sscofpmf` extension. Prior to that, there was no way to access the upper\n32-bits of `mhpmevent#{hpm_num}`.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_64500b00", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent11h.yaml", + "section": "mhpmevent11h.OF", + "text": "CSR mhpmevent11h field OF (bits=31) Alias of mhpmevent11.OF. type: if (HPM_COUNTER_EN[11]) { reset: if (HPM_COUNTER_EN[11]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_9cf07491", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent11h.yaml", + "section": "mhpmevent11h.MINH", + "text": "CSR mhpmevent11h field MINH (bits=30) Alias of mhpmevent11.MINH. type: if (HPM_COUNTER_EN[11]) { reset: if (HPM_COUNTER_EN[11]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_fd1d1cb3", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent11h.yaml", + "section": "mhpmevent11h.SINH", + "text": "CSR mhpmevent11h field SINH (bits=29) Alias of mhpmevent11.SINH. type: if ((HPM_COUNTER_EN[11]) && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { reset: if ((HPM_COUNTER_EN[11]) && implemented?(ExtensionName::S)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_73277cd0", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent11h.yaml", + "section": "mhpmevent11h.UINH", + "text": "CSR mhpmevent11h field UINH (bits=28) Alias of mhpmevent11.UINH. type: if ((HPM_COUNTER_EN[11]) && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { reset: if ((HPM_COUNTER_EN[11]) && implemented?(ExtensionName::U)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_7a6f046c", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent11h.yaml", + "section": "mhpmevent11h.VSINH", + "text": "CSR mhpmevent11h field VSINH (bits=27) Alias of mhpmevent11.VSINH. type: if ((HPM_COUNTER_EN[11]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[11]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_6094c198", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent11h.yaml", + "section": "mhpmevent11h.VUINH", + "text": "CSR mhpmevent11h field VUINH (bits=26) Alias of mhpmevent11.VUINH. type: if ((HPM_COUNTER_EN[11]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[11]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_4b19a5d9", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent11h.yaml", + "section": "mhpmevent11h.EVENT", + "text": "CSR mhpmevent11h field EVENT (bits=25-0) High part of event selector for performance counter `mhpmcounter11`. type: if (HPM_COUNTER_EN[11]) { reset: if (HPM_COUNTER_EN[11]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_dc5d4f07", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent12.yaml", + "section": "mhpmevent12", + "text": "CSR mhpmevent12 (address=812, priv=M): Programmable hardware performance counter event selector\n<% if ext?(:Sscofpmf) %> and overflow/filtering control<% end %>", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_9844d98d", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent12.yaml", + "section": "mhpmevent12.OF", + "text": "CSR mhpmevent12 field OF (bits=63) Overflow status and interrupt disable.\n\nThe OF bit is set when the corresponding hpmcounter overflows, and remains set until written by\nsoftware. Since hpmcounter values are unsigned values, overflow is defined as unsigned\noverflow of the implemented counter bits.\n\nThe OF bit is sticky; it stays set type: if (HPM_COUNTER_EN[12]) { reset: if (HPM_COUNTER_EN[12]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_8bdecb93", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent12.yaml", + "section": "mhpmevent12.MINH", + "text": "CSR mhpmevent12 field MINH (bits=62) When set, mhpmcounter12 does not increment while the hart in operating in M-mode. type: if (HPM_COUNTER_EN[12]) { reset: if (HPM_COUNTER_EN[12]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_786a6c21", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent12.yaml", + "section": "mhpmevent12.SINH", + "text": "CSR mhpmevent12 field SINH (bits=61) When set, mhpmcounter12 does not increment while the hart in operating in (H)S-mode. type: if (HPM_COUNTER_EN[12] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { reset: if (HPM_COUNTER_EN[12] && implemented?(ExtensionName::S)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_68652ae3", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent12.yaml", + "section": "mhpmevent12.UINH", + "text": "CSR mhpmevent12 field UINH (bits=60) When set, mhpmcounter12 does not increment while the hart in operating in U-mode. type: if (HPM_COUNTER_EN[12] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { reset: if (HPM_COUNTER_EN[12] && implemented?(ExtensionName::U)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_f8611d0a", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent12.yaml", + "section": "mhpmevent12.VSINH", + "text": "CSR mhpmevent12 field VSINH (bits=59) When set, mhpmcounter12 does not increment while the hart in operating in VS-mode. type: if ((HPM_COUNTER_EN[12]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if (HPM_COUNTER_EN[12] && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_c8857fd3", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent12.yaml", + "section": "mhpmevent12.VUINH", + "text": "CSR mhpmevent12 field VUINH (bits=58) When set, mhpmcounter12 does not increment while the hart in operating in VU-mode. type: if (HPM_COUNTER_EN[12] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[12]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_c568c247", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent12.yaml", + "section": "mhpmevent12.EVENT", + "text": "CSR mhpmevent12 field EVENT (bits=57-0) Event selector for performance counter `mhpmcounter12`. type: if (HPM_COUNTER_EN[12]) { reset: if (HPM_COUNTER_EN[12]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_e97780ce", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent12h.yaml", + "section": "mhpmevent12h", + "text": "CSR mhpmevent12h (address=1836, priv=M): Alias of `mhpmevent12`[63:32].\n\nIntroduced with the `Sscofpmf` extension. Prior to that, there was no way to access the upper\n32-bits of `mhpmevent#{hpm_num}`.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_b167000d", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent12h.yaml", + "section": "mhpmevent12h.OF", + "text": "CSR mhpmevent12h field OF (bits=31) Alias of mhpmevent12.OF. type: if (HPM_COUNTER_EN[12]) { reset: if (HPM_COUNTER_EN[12]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_71339497", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent12h.yaml", + "section": "mhpmevent12h.MINH", + "text": "CSR mhpmevent12h field MINH (bits=30) Alias of mhpmevent12.MINH. type: if (HPM_COUNTER_EN[12]) { reset: if (HPM_COUNTER_EN[12]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_cab4ff46", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent12h.yaml", + "section": "mhpmevent12h.SINH", + "text": "CSR mhpmevent12h field SINH (bits=29) Alias of mhpmevent12.SINH. type: if ((HPM_COUNTER_EN[12]) && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { reset: if ((HPM_COUNTER_EN[12]) && implemented?(ExtensionName::S)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_2f67f504", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent12h.yaml", + "section": "mhpmevent12h.UINH", + "text": "CSR mhpmevent12h field UINH (bits=28) Alias of mhpmevent12.UINH. type: if ((HPM_COUNTER_EN[12]) && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { reset: if ((HPM_COUNTER_EN[12]) && implemented?(ExtensionName::U)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_855517c3", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent12h.yaml", + "section": "mhpmevent12h.VSINH", + "text": "CSR mhpmevent12h field VSINH (bits=27) Alias of mhpmevent12.VSINH. type: if ((HPM_COUNTER_EN[12]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[12]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ef15a281", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent12h.yaml", + "section": "mhpmevent12h.VUINH", + "text": "CSR mhpmevent12h field VUINH (bits=26) Alias of mhpmevent12.VUINH. type: if ((HPM_COUNTER_EN[12]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[12]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_4ed2c19c", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent12h.yaml", + "section": "mhpmevent12h.EVENT", + "text": "CSR mhpmevent12h field EVENT (bits=25-0) High part of event selector for performance counter `mhpmcounter12`. type: if (HPM_COUNTER_EN[12]) { reset: if (HPM_COUNTER_EN[12]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_81107ea8", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent13.yaml", + "section": "mhpmevent13", + "text": "CSR mhpmevent13 (address=813, priv=M): Programmable hardware performance counter event selector\n<% if ext?(:Sscofpmf) %> and overflow/filtering control<% end %>", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d711eaff", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent13.yaml", + "section": "mhpmevent13.OF", + "text": "CSR mhpmevent13 field OF (bits=63) Overflow status and interrupt disable.\n\nThe OF bit is set when the corresponding hpmcounter overflows, and remains set until written by\nsoftware. Since hpmcounter values are unsigned values, overflow is defined as unsigned\noverflow of the implemented counter bits.\n\nThe OF bit is sticky; it stays set type: if (HPM_COUNTER_EN[13]) { reset: if (HPM_COUNTER_EN[13]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_396518cf", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent13.yaml", + "section": "mhpmevent13.MINH", + "text": "CSR mhpmevent13 field MINH (bits=62) When set, mhpmcounter13 does not increment while the hart in operating in M-mode. type: if (HPM_COUNTER_EN[13]) { reset: if (HPM_COUNTER_EN[13]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d2490c4f", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent13.yaml", + "section": "mhpmevent13.SINH", + "text": "CSR mhpmevent13 field SINH (bits=61) When set, mhpmcounter13 does not increment while the hart in operating in (H)S-mode. type: if (HPM_COUNTER_EN[13] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { reset: if (HPM_COUNTER_EN[13] && implemented?(ExtensionName::S)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_b8211518", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent13.yaml", + "section": "mhpmevent13.UINH", + "text": "CSR mhpmevent13 field UINH (bits=60) When set, mhpmcounter13 does not increment while the hart in operating in U-mode. type: if (HPM_COUNTER_EN[13] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { reset: if (HPM_COUNTER_EN[13] && implemented?(ExtensionName::U)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_90e7474c", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent13.yaml", + "section": "mhpmevent13.VSINH", + "text": "CSR mhpmevent13 field VSINH (bits=59) When set, mhpmcounter13 does not increment while the hart in operating in VS-mode. type: if ((HPM_COUNTER_EN[13]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if (HPM_COUNTER_EN[13] && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_25d8febc", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent13.yaml", + "section": "mhpmevent13.VUINH", + "text": "CSR mhpmevent13 field VUINH (bits=58) When set, mhpmcounter13 does not increment while the hart in operating in VU-mode. type: if (HPM_COUNTER_EN[13] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[13]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_a763b16c", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent13.yaml", + "section": "mhpmevent13.EVENT", + "text": "CSR mhpmevent13 field EVENT (bits=57-0) Event selector for performance counter `mhpmcounter13`. type: if (HPM_COUNTER_EN[13]) { reset: if (HPM_COUNTER_EN[13]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_1f817764", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent13h.yaml", + "section": "mhpmevent13h", + "text": "CSR mhpmevent13h (address=1837, priv=M): Alias of `mhpmevent13`[63:32].\n\nIntroduced with the `Sscofpmf` extension. Prior to that, there was no way to access the upper\n32-bits of `mhpmevent#{hpm_num}`.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_c04beb69", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent13h.yaml", + "section": "mhpmevent13h.OF", + "text": "CSR mhpmevent13h field OF (bits=31) Alias of mhpmevent13.OF. type: if (HPM_COUNTER_EN[13]) { reset: if (HPM_COUNTER_EN[13]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_be3307cf", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent13h.yaml", + "section": "mhpmevent13h.MINH", + "text": "CSR mhpmevent13h field MINH (bits=30) Alias of mhpmevent13.MINH. type: if (HPM_COUNTER_EN[13]) { reset: if (HPM_COUNTER_EN[13]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_cf0967ca", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent13h.yaml", + "section": "mhpmevent13h.SINH", + "text": "CSR mhpmevent13h field SINH (bits=29) Alias of mhpmevent13.SINH. type: if ((HPM_COUNTER_EN[13]) && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { reset: if ((HPM_COUNTER_EN[13]) && implemented?(ExtensionName::S)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_e9adc185", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent13h.yaml", + "section": "mhpmevent13h.UINH", + "text": "CSR mhpmevent13h field UINH (bits=28) Alias of mhpmevent13.UINH. type: if ((HPM_COUNTER_EN[13]) && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { reset: if ((HPM_COUNTER_EN[13]) && implemented?(ExtensionName::U)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_6db42992", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent13h.yaml", + "section": "mhpmevent13h.VSINH", + "text": "CSR mhpmevent13h field VSINH (bits=27) Alias of mhpmevent13.VSINH. type: if ((HPM_COUNTER_EN[13]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[13]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_5dbb08dc", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent13h.yaml", + "section": "mhpmevent13h.VUINH", + "text": "CSR mhpmevent13h field VUINH (bits=26) Alias of mhpmevent13.VUINH. type: if ((HPM_COUNTER_EN[13]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[13]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d674772f", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent13h.yaml", + "section": "mhpmevent13h.EVENT", + "text": "CSR mhpmevent13h field EVENT (bits=25-0) High part of event selector for performance counter `mhpmcounter13`. type: if (HPM_COUNTER_EN[13]) { reset: if (HPM_COUNTER_EN[13]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_c46064b5", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent14.yaml", + "section": "mhpmevent14", + "text": "CSR mhpmevent14 (address=814, priv=M): Programmable hardware performance counter event selector\n<% if ext?(:Sscofpmf) %> and overflow/filtering control<% end %>", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_b77a15c1", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent14.yaml", + "section": "mhpmevent14.OF", + "text": "CSR mhpmevent14 field OF (bits=63) Overflow status and interrupt disable.\n\nThe OF bit is set when the corresponding hpmcounter overflows, and remains set until written by\nsoftware. Since hpmcounter values are unsigned values, overflow is defined as unsigned\noverflow of the implemented counter bits.\n\nThe OF bit is sticky; it stays set type: if (HPM_COUNTER_EN[14]) { reset: if (HPM_COUNTER_EN[14]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_99d61c59", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent14.yaml", + "section": "mhpmevent14.MINH", + "text": "CSR mhpmevent14 field MINH (bits=62) When set, mhpmcounter14 does not increment while the hart in operating in M-mode. type: if (HPM_COUNTER_EN[14]) { reset: if (HPM_COUNTER_EN[14]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_8d72a852", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent14.yaml", + "section": "mhpmevent14.SINH", + "text": "CSR mhpmevent14 field SINH (bits=61) When set, mhpmcounter14 does not increment while the hart in operating in (H)S-mode. type: if (HPM_COUNTER_EN[14] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { reset: if (HPM_COUNTER_EN[14] && implemented?(ExtensionName::S)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_4216553d", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent14.yaml", + "section": "mhpmevent14.UINH", + "text": "CSR mhpmevent14 field UINH (bits=60) When set, mhpmcounter14 does not increment while the hart in operating in U-mode. type: if (HPM_COUNTER_EN[14] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { reset: if (HPM_COUNTER_EN[14] && implemented?(ExtensionName::U)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_968103a5", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent14.yaml", + "section": "mhpmevent14.VSINH", + "text": "CSR mhpmevent14 field VSINH (bits=59) When set, mhpmcounter14 does not increment while the hart in operating in VS-mode. type: if ((HPM_COUNTER_EN[14]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if (HPM_COUNTER_EN[14] && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_af1fe43e", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent14.yaml", + "section": "mhpmevent14.VUINH", + "text": "CSR mhpmevent14 field VUINH (bits=58) When set, mhpmcounter14 does not increment while the hart in operating in VU-mode. type: if (HPM_COUNTER_EN[14] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[14]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_045b9395", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent14.yaml", + "section": "mhpmevent14.EVENT", + "text": "CSR mhpmevent14 field EVENT (bits=57-0) Event selector for performance counter `mhpmcounter14`. type: if (HPM_COUNTER_EN[14]) { reset: if (HPM_COUNTER_EN[14]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_9855a512", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent14h.yaml", + "section": "mhpmevent14h", + "text": "CSR mhpmevent14h (address=1838, priv=M): Alias of `mhpmevent14`[63:32].\n\nIntroduced with the `Sscofpmf` extension. Prior to that, there was no way to access the upper\n32-bits of `mhpmevent#{hpm_num}`.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ba5b95b5", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent14h.yaml", + "section": "mhpmevent14h.OF", + "text": "CSR mhpmevent14h field OF (bits=31) Alias of mhpmevent14.OF. type: if (HPM_COUNTER_EN[14]) { reset: if (HPM_COUNTER_EN[14]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_cd7d3713", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent14h.yaml", + "section": "mhpmevent14h.MINH", + "text": "CSR mhpmevent14h field MINH (bits=30) Alias of mhpmevent14.MINH. type: if (HPM_COUNTER_EN[14]) { reset: if (HPM_COUNTER_EN[14]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_124aab76", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent14h.yaml", + "section": "mhpmevent14h.SINH", + "text": "CSR mhpmevent14h field SINH (bits=29) Alias of mhpmevent14.SINH. type: if ((HPM_COUNTER_EN[14]) && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { reset: if ((HPM_COUNTER_EN[14]) && implemented?(ExtensionName::S)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_6e7f3c4e", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent14h.yaml", + "section": "mhpmevent14h.UINH", + "text": "CSR mhpmevent14h field UINH (bits=28) Alias of mhpmevent14.UINH. type: if ((HPM_COUNTER_EN[14]) && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { reset: if ((HPM_COUNTER_EN[14]) && implemented?(ExtensionName::U)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_8bc47871", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent14h.yaml", + "section": "mhpmevent14h.VSINH", + "text": "CSR mhpmevent14h field VSINH (bits=27) Alias of mhpmevent14.VSINH. type: if ((HPM_COUNTER_EN[14]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[14]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_63404cc5", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent14h.yaml", + "section": "mhpmevent14h.VUINH", + "text": "CSR mhpmevent14h field VUINH (bits=26) Alias of mhpmevent14.VUINH. type: if ((HPM_COUNTER_EN[14]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[14]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_2541e189", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent14h.yaml", + "section": "mhpmevent14h.EVENT", + "text": "CSR mhpmevent14h field EVENT (bits=25-0) High part of event selector for performance counter `mhpmcounter14`. type: if (HPM_COUNTER_EN[14]) { reset: if (HPM_COUNTER_EN[14]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_9d1f6bb7", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent15.yaml", + "section": "mhpmevent15", + "text": "CSR mhpmevent15 (address=815, priv=M): Programmable hardware performance counter event selector\n<% if ext?(:Sscofpmf) %> and overflow/filtering control<% end %>", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_b518b493", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent15.yaml", + "section": "mhpmevent15.OF", + "text": "CSR mhpmevent15 field OF (bits=63) Overflow status and interrupt disable.\n\nThe OF bit is set when the corresponding hpmcounter overflows, and remains set until written by\nsoftware. Since hpmcounter values are unsigned values, overflow is defined as unsigned\noverflow of the implemented counter bits.\n\nThe OF bit is sticky; it stays set type: if (HPM_COUNTER_EN[15]) { reset: if (HPM_COUNTER_EN[15]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d93e722d", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent15.yaml", + "section": "mhpmevent15.MINH", + "text": "CSR mhpmevent15 field MINH (bits=62) When set, mhpmcounter15 does not increment while the hart in operating in M-mode. type: if (HPM_COUNTER_EN[15]) { reset: if (HPM_COUNTER_EN[15]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_32143eea", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent15.yaml", + "section": "mhpmevent15.SINH", + "text": "CSR mhpmevent15 field SINH (bits=61) When set, mhpmcounter15 does not increment while the hart in operating in (H)S-mode. type: if (HPM_COUNTER_EN[15] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { reset: if (HPM_COUNTER_EN[15] && implemented?(ExtensionName::S)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_f3401f3b", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent15.yaml", + "section": "mhpmevent15.UINH", + "text": "CSR mhpmevent15 field UINH (bits=60) When set, mhpmcounter15 does not increment while the hart in operating in U-mode. type: if (HPM_COUNTER_EN[15] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { reset: if (HPM_COUNTER_EN[15] && implemented?(ExtensionName::U)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_359741ab", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent15.yaml", + "section": "mhpmevent15.VSINH", + "text": "CSR mhpmevent15 field VSINH (bits=59) When set, mhpmcounter15 does not increment while the hart in operating in VS-mode. type: if ((HPM_COUNTER_EN[15]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if (HPM_COUNTER_EN[15] && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_c7f82cfd", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent15.yaml", + "section": "mhpmevent15.VUINH", + "text": "CSR mhpmevent15 field VUINH (bits=58) When set, mhpmcounter15 does not increment while the hart in operating in VU-mode. type: if (HPM_COUNTER_EN[15] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[15]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_1b6385e0", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent15.yaml", + "section": "mhpmevent15.EVENT", + "text": "CSR mhpmevent15 field EVENT (bits=57-0) Event selector for performance counter `mhpmcounter15`. type: if (HPM_COUNTER_EN[15]) { reset: if (HPM_COUNTER_EN[15]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_619c2a68", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent15h.yaml", + "section": "mhpmevent15h", + "text": "CSR mhpmevent15h (address=1839, priv=M): Alias of `mhpmevent15`[63:32].\n\nIntroduced with the `Sscofpmf` extension. Prior to that, there was no way to access the upper\n32-bits of `mhpmevent#{hpm_num}`.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_271c00b7", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent15h.yaml", + "section": "mhpmevent15h.OF", + "text": "CSR mhpmevent15h field OF (bits=31) Alias of mhpmevent15.OF. type: if (HPM_COUNTER_EN[15]) { reset: if (HPM_COUNTER_EN[15]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_4673dddd", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent15h.yaml", + "section": "mhpmevent15h.MINH", + "text": "CSR mhpmevent15h field MINH (bits=30) Alias of mhpmevent15.MINH. type: if (HPM_COUNTER_EN[15]) { reset: if (HPM_COUNTER_EN[15]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d2927bb9", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent15h.yaml", + "section": "mhpmevent15h.SINH", + "text": "CSR mhpmevent15h field SINH (bits=29) Alias of mhpmevent15.SINH. type: if ((HPM_COUNTER_EN[15]) && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { reset: if ((HPM_COUNTER_EN[15]) && implemented?(ExtensionName::S)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_acc52a55", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent15h.yaml", + "section": "mhpmevent15h.UINH", + "text": "CSR mhpmevent15h field UINH (bits=28) Alias of mhpmevent15.UINH. type: if ((HPM_COUNTER_EN[15]) && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { reset: if ((HPM_COUNTER_EN[15]) && implemented?(ExtensionName::U)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ae02ba83", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent15h.yaml", + "section": "mhpmevent15h.VSINH", + "text": "CSR mhpmevent15h field VSINH (bits=27) Alias of mhpmevent15.VSINH. type: if ((HPM_COUNTER_EN[15]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[15]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_b9d726f8", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent15h.yaml", + "section": "mhpmevent15h.VUINH", + "text": "CSR mhpmevent15h field VUINH (bits=26) Alias of mhpmevent15.VUINH. type: if ((HPM_COUNTER_EN[15]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[15]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_07295ef3", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent15h.yaml", + "section": "mhpmevent15h.EVENT", + "text": "CSR mhpmevent15h field EVENT (bits=25-0) High part of event selector for performance counter `mhpmcounter15`. type: if (HPM_COUNTER_EN[15]) { reset: if (HPM_COUNTER_EN[15]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_6686dfab", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent16.yaml", + "section": "mhpmevent16", + "text": "CSR mhpmevent16 (address=816, priv=M): Programmable hardware performance counter event selector\n<% if ext?(:Sscofpmf) %> and overflow/filtering control<% end %>", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_e49fa24b", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent16.yaml", + "section": "mhpmevent16.OF", + "text": "CSR mhpmevent16 field OF (bits=63) Overflow status and interrupt disable.\n\nThe OF bit is set when the corresponding hpmcounter overflows, and remains set until written by\nsoftware. Since hpmcounter values are unsigned values, overflow is defined as unsigned\noverflow of the implemented counter bits.\n\nThe OF bit is sticky; it stays set type: if (HPM_COUNTER_EN[16]) { reset: if (HPM_COUNTER_EN[16]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_3b05fe75", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent16.yaml", + "section": "mhpmevent16.MINH", + "text": "CSR mhpmevent16 field MINH (bits=62) When set, mhpmcounter16 does not increment while the hart in operating in M-mode. type: if (HPM_COUNTER_EN[16]) { reset: if (HPM_COUNTER_EN[16]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_19e9dc49", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent16.yaml", + "section": "mhpmevent16.SINH", + "text": "CSR mhpmevent16 field SINH (bits=61) When set, mhpmcounter16 does not increment while the hart in operating in (H)S-mode. type: if (HPM_COUNTER_EN[16] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { reset: if (HPM_COUNTER_EN[16] && implemented?(ExtensionName::S)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_0369adc0", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent16.yaml", + "section": "mhpmevent16.UINH", + "text": "CSR mhpmevent16 field UINH (bits=60) When set, mhpmcounter16 does not increment while the hart in operating in U-mode. type: if (HPM_COUNTER_EN[16] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { reset: if (HPM_COUNTER_EN[16] && implemented?(ExtensionName::U)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_69299c30", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent16.yaml", + "section": "mhpmevent16.VSINH", + "text": "CSR mhpmevent16 field VSINH (bits=59) When set, mhpmcounter16 does not increment while the hart in operating in VS-mode. type: if ((HPM_COUNTER_EN[16]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if (HPM_COUNTER_EN[16] && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_a75af62b", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent16.yaml", + "section": "mhpmevent16.VUINH", + "text": "CSR mhpmevent16 field VUINH (bits=58) When set, mhpmcounter16 does not increment while the hart in operating in VU-mode. type: if (HPM_COUNTER_EN[16] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[16]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_bf1c92ff", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent16.yaml", + "section": "mhpmevent16.EVENT", + "text": "CSR mhpmevent16 field EVENT (bits=57-0) Event selector for performance counter `mhpmcounter16`. type: if (HPM_COUNTER_EN[16]) { reset: if (HPM_COUNTER_EN[16]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_870150c5", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent16h.yaml", + "section": "mhpmevent16h", + "text": "CSR mhpmevent16h (address=1840, priv=M): Alias of `mhpmevent16`[63:32].\n\nIntroduced with the `Sscofpmf` extension. Prior to that, there was no way to access the upper\n32-bits of `mhpmevent#{hpm_num}`.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_1d811234", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent16h.yaml", + "section": "mhpmevent16h.OF", + "text": "CSR mhpmevent16h field OF (bits=31) Alias of mhpmevent16.OF. type: if (HPM_COUNTER_EN[16]) { reset: if (HPM_COUNTER_EN[16]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_c73dbd38", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent16h.yaml", + "section": "mhpmevent16h.MINH", + "text": "CSR mhpmevent16h field MINH (bits=30) Alias of mhpmevent16.MINH. type: if (HPM_COUNTER_EN[16]) { reset: if (HPM_COUNTER_EN[16]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_616ceea6", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent16h.yaml", + "section": "mhpmevent16h.SINH", + "text": "CSR mhpmevent16h field SINH (bits=29) Alias of mhpmevent16.SINH. type: if ((HPM_COUNTER_EN[16]) && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { reset: if ((HPM_COUNTER_EN[16]) && implemented?(ExtensionName::S)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_e7a0b6f2", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent16h.yaml", + "section": "mhpmevent16h.UINH", + "text": "CSR mhpmevent16h field UINH (bits=28) Alias of mhpmevent16.UINH. type: if ((HPM_COUNTER_EN[16]) && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { reset: if ((HPM_COUNTER_EN[16]) && implemented?(ExtensionName::U)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_41a3bf2d", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent16h.yaml", + "section": "mhpmevent16h.VSINH", + "text": "CSR mhpmevent16h field VSINH (bits=27) Alias of mhpmevent16.VSINH. type: if ((HPM_COUNTER_EN[16]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[16]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_2c7cb9f1", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent16h.yaml", + "section": "mhpmevent16h.VUINH", + "text": "CSR mhpmevent16h field VUINH (bits=26) Alias of mhpmevent16.VUINH. type: if ((HPM_COUNTER_EN[16]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[16]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d6e77042", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent16h.yaml", + "section": "mhpmevent16h.EVENT", + "text": "CSR mhpmevent16h field EVENT (bits=25-0) High part of event selector for performance counter `mhpmcounter16`. type: if (HPM_COUNTER_EN[16]) { reset: if (HPM_COUNTER_EN[16]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_799ca96d", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent17.yaml", + "section": "mhpmevent17", + "text": "CSR mhpmevent17 (address=817, priv=M): Programmable hardware performance counter event selector\n<% if ext?(:Sscofpmf) %> and overflow/filtering control<% end %>", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_8eb12807", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent17.yaml", + "section": "mhpmevent17.OF", + "text": "CSR mhpmevent17 field OF (bits=63) Overflow status and interrupt disable.\n\nThe OF bit is set when the corresponding hpmcounter overflows, and remains set until written by\nsoftware. Since hpmcounter values are unsigned values, overflow is defined as unsigned\noverflow of the implemented counter bits.\n\nThe OF bit is sticky; it stays set type: if (HPM_COUNTER_EN[17]) { reset: if (HPM_COUNTER_EN[17]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_8e15ba1c", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent17.yaml", + "section": "mhpmevent17.MINH", + "text": "CSR mhpmevent17 field MINH (bits=62) When set, mhpmcounter17 does not increment while the hart in operating in M-mode. type: if (HPM_COUNTER_EN[17]) { reset: if (HPM_COUNTER_EN[17]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_6477de58", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent17.yaml", + "section": "mhpmevent17.SINH", + "text": "CSR mhpmevent17 field SINH (bits=61) When set, mhpmcounter17 does not increment while the hart in operating in (H)S-mode. type: if (HPM_COUNTER_EN[17] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { reset: if (HPM_COUNTER_EN[17] && implemented?(ExtensionName::S)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_5ce6de3b", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent17.yaml", + "section": "mhpmevent17.UINH", + "text": "CSR mhpmevent17 field UINH (bits=60) When set, mhpmcounter17 does not increment while the hart in operating in U-mode. type: if (HPM_COUNTER_EN[17] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { reset: if (HPM_COUNTER_EN[17] && implemented?(ExtensionName::U)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_7c87928c", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent17.yaml", + "section": "mhpmevent17.VSINH", + "text": "CSR mhpmevent17 field VSINH (bits=59) When set, mhpmcounter17 does not increment while the hart in operating in VS-mode. type: if ((HPM_COUNTER_EN[17]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if (HPM_COUNTER_EN[17] && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_685a7ba9", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent17.yaml", + "section": "mhpmevent17.VUINH", + "text": "CSR mhpmevent17 field VUINH (bits=58) When set, mhpmcounter17 does not increment while the hart in operating in VU-mode. type: if (HPM_COUNTER_EN[17] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[17]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_db34c87f", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent17.yaml", + "section": "mhpmevent17.EVENT", + "text": "CSR mhpmevent17 field EVENT (bits=57-0) Event selector for performance counter `mhpmcounter17`. type: if (HPM_COUNTER_EN[17]) { reset: if (HPM_COUNTER_EN[17]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_f5996e1e", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent17h.yaml", + "section": "mhpmevent17h", + "text": "CSR mhpmevent17h (address=1841, priv=M): Alias of `mhpmevent17`[63:32].\n\nIntroduced with the `Sscofpmf` extension. Prior to that, there was no way to access the upper\n32-bits of `mhpmevent#{hpm_num}`.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_cce2c1e9", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent17h.yaml", + "section": "mhpmevent17h.OF", + "text": "CSR mhpmevent17h field OF (bits=31) Alias of mhpmevent17.OF. type: if (HPM_COUNTER_EN[17]) { reset: if (HPM_COUNTER_EN[17]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_21c342e4", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent17h.yaml", + "section": "mhpmevent17h.MINH", + "text": "CSR mhpmevent17h field MINH (bits=30) Alias of mhpmevent17.MINH. type: if (HPM_COUNTER_EN[17]) { reset: if (HPM_COUNTER_EN[17]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_8f1f34f8", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent17h.yaml", + "section": "mhpmevent17h.SINH", + "text": "CSR mhpmevent17h field SINH (bits=29) Alias of mhpmevent17.SINH. type: if ((HPM_COUNTER_EN[17]) && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { reset: if ((HPM_COUNTER_EN[17]) && implemented?(ExtensionName::S)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_7f31e358", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent17h.yaml", + "section": "mhpmevent17h.UINH", + "text": "CSR mhpmevent17h field UINH (bits=28) Alias of mhpmevent17.UINH. type: if ((HPM_COUNTER_EN[17]) && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { reset: if ((HPM_COUNTER_EN[17]) && implemented?(ExtensionName::U)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_8513a0df", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent17h.yaml", + "section": "mhpmevent17h.VSINH", + "text": "CSR mhpmevent17h field VSINH (bits=27) Alias of mhpmevent17.VSINH. type: if ((HPM_COUNTER_EN[17]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[17]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_8559d640", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent17h.yaml", + "section": "mhpmevent17h.VUINH", + "text": "CSR mhpmevent17h field VUINH (bits=26) Alias of mhpmevent17.VUINH. type: if ((HPM_COUNTER_EN[17]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[17]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_94684c75", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent17h.yaml", + "section": "mhpmevent17h.EVENT", + "text": "CSR mhpmevent17h field EVENT (bits=25-0) High part of event selector for performance counter `mhpmcounter17`. type: if (HPM_COUNTER_EN[17]) { reset: if (HPM_COUNTER_EN[17]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_8bddaebc", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent18.yaml", + "section": "mhpmevent18", + "text": "CSR mhpmevent18 (address=818, priv=M): Programmable hardware performance counter event selector\n<% if ext?(:Sscofpmf) %> and overflow/filtering control<% end %>", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ca1f9921", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent18.yaml", + "section": "mhpmevent18.OF", + "text": "CSR mhpmevent18 field OF (bits=63) Overflow status and interrupt disable.\n\nThe OF bit is set when the corresponding hpmcounter overflows, and remains set until written by\nsoftware. Since hpmcounter values are unsigned values, overflow is defined as unsigned\noverflow of the implemented counter bits.\n\nThe OF bit is sticky; it stays set type: if (HPM_COUNTER_EN[18]) { reset: if (HPM_COUNTER_EN[18]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_c6d93b74", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent18.yaml", + "section": "mhpmevent18.MINH", + "text": "CSR mhpmevent18 field MINH (bits=62) When set, mhpmcounter18 does not increment while the hart in operating in M-mode. type: if (HPM_COUNTER_EN[18]) { reset: if (HPM_COUNTER_EN[18]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d6afaf14", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent18.yaml", + "section": "mhpmevent18.SINH", + "text": "CSR mhpmevent18 field SINH (bits=61) When set, mhpmcounter18 does not increment while the hart in operating in (H)S-mode. type: if (HPM_COUNTER_EN[18] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { reset: if (HPM_COUNTER_EN[18] && implemented?(ExtensionName::S)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_9c8d71d5", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent18.yaml", + "section": "mhpmevent18.UINH", + "text": "CSR mhpmevent18 field UINH (bits=60) When set, mhpmcounter18 does not increment while the hart in operating in U-mode. type: if (HPM_COUNTER_EN[18] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { reset: if (HPM_COUNTER_EN[18] && implemented?(ExtensionName::U)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_a7b9ee79", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent18.yaml", + "section": "mhpmevent18.VSINH", + "text": "CSR mhpmevent18 field VSINH (bits=59) When set, mhpmcounter18 does not increment while the hart in operating in VS-mode. type: if ((HPM_COUNTER_EN[18]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if (HPM_COUNTER_EN[18] && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_f0d357f9", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent18.yaml", + "section": "mhpmevent18.VUINH", + "text": "CSR mhpmevent18 field VUINH (bits=58) When set, mhpmcounter18 does not increment while the hart in operating in VU-mode. type: if (HPM_COUNTER_EN[18] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[18]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_714812e0", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent18.yaml", + "section": "mhpmevent18.EVENT", + "text": "CSR mhpmevent18 field EVENT (bits=57-0) Event selector for performance counter `mhpmcounter18`. type: if (HPM_COUNTER_EN[18]) { reset: if (HPM_COUNTER_EN[18]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_27fdd455", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent18h.yaml", + "section": "mhpmevent18h", + "text": "CSR mhpmevent18h (address=1842, priv=M): Alias of `mhpmevent18`[63:32].\n\nIntroduced with the `Sscofpmf` extension. Prior to that, there was no way to access the upper\n32-bits of `mhpmevent#{hpm_num}`.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_94000797", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent18h.yaml", + "section": "mhpmevent18h.OF", + "text": "CSR mhpmevent18h field OF (bits=31) Alias of mhpmevent18.OF. type: if (HPM_COUNTER_EN[18]) { reset: if (HPM_COUNTER_EN[18]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_0a9a6eaf", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent18h.yaml", + "section": "mhpmevent18h.MINH", + "text": "CSR mhpmevent18h field MINH (bits=30) Alias of mhpmevent18.MINH. type: if (HPM_COUNTER_EN[18]) { reset: if (HPM_COUNTER_EN[18]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_05c7f001", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent18h.yaml", + "section": "mhpmevent18h.SINH", + "text": "CSR mhpmevent18h field SINH (bits=29) Alias of mhpmevent18.SINH. type: if ((HPM_COUNTER_EN[18]) && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { reset: if ((HPM_COUNTER_EN[18]) && implemented?(ExtensionName::S)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_188e133b", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent18h.yaml", + "section": "mhpmevent18h.UINH", + "text": "CSR mhpmevent18h field UINH (bits=28) Alias of mhpmevent18.UINH. type: if ((HPM_COUNTER_EN[18]) && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { reset: if ((HPM_COUNTER_EN[18]) && implemented?(ExtensionName::U)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_c7579547", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent18h.yaml", + "section": "mhpmevent18h.VSINH", + "text": "CSR mhpmevent18h field VSINH (bits=27) Alias of mhpmevent18.VSINH. type: if ((HPM_COUNTER_EN[18]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[18]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_68ffe9cf", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent18h.yaml", + "section": "mhpmevent18h.VUINH", + "text": "CSR mhpmevent18h field VUINH (bits=26) Alias of mhpmevent18.VUINH. type: if ((HPM_COUNTER_EN[18]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[18]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_b88c61ae", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent18h.yaml", + "section": "mhpmevent18h.EVENT", + "text": "CSR mhpmevent18h field EVENT (bits=25-0) High part of event selector for performance counter `mhpmcounter18`. type: if (HPM_COUNTER_EN[18]) { reset: if (HPM_COUNTER_EN[18]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_f4669a91", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent19.yaml", + "section": "mhpmevent19", + "text": "CSR mhpmevent19 (address=819, priv=M): Programmable hardware performance counter event selector\n<% if ext?(:Sscofpmf) %> and overflow/filtering control<% end %>", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_214315be", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent19.yaml", + "section": "mhpmevent19.OF", + "text": "CSR mhpmevent19 field OF (bits=63) Overflow status and interrupt disable.\n\nThe OF bit is set when the corresponding hpmcounter overflows, and remains set until written by\nsoftware. Since hpmcounter values are unsigned values, overflow is defined as unsigned\noverflow of the implemented counter bits.\n\nThe OF bit is sticky; it stays set type: if (HPM_COUNTER_EN[19]) { reset: if (HPM_COUNTER_EN[19]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_2bc57c9c", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent19.yaml", + "section": "mhpmevent19.MINH", + "text": "CSR mhpmevent19 field MINH (bits=62) When set, mhpmcounter19 does not increment while the hart in operating in M-mode. type: if (HPM_COUNTER_EN[19]) { reset: if (HPM_COUNTER_EN[19]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_1dce7af3", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent19.yaml", + "section": "mhpmevent19.SINH", + "text": "CSR mhpmevent19 field SINH (bits=61) When set, mhpmcounter19 does not increment while the hart in operating in (H)S-mode. type: if (HPM_COUNTER_EN[19] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { reset: if (HPM_COUNTER_EN[19] && implemented?(ExtensionName::S)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_0103c08b", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent19.yaml", + "section": "mhpmevent19.UINH", + "text": "CSR mhpmevent19 field UINH (bits=60) When set, mhpmcounter19 does not increment while the hart in operating in U-mode. type: if (HPM_COUNTER_EN[19] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { reset: if (HPM_COUNTER_EN[19] && implemented?(ExtensionName::U)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_3db4d560", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent19.yaml", + "section": "mhpmevent19.VSINH", + "text": "CSR mhpmevent19 field VSINH (bits=59) When set, mhpmcounter19 does not increment while the hart in operating in VS-mode. type: if ((HPM_COUNTER_EN[19]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if (HPM_COUNTER_EN[19] && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_f12fc876", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent19.yaml", + "section": "mhpmevent19.VUINH", + "text": "CSR mhpmevent19 field VUINH (bits=58) When set, mhpmcounter19 does not increment while the hart in operating in VU-mode. type: if (HPM_COUNTER_EN[19] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[19]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_7a831dc0", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent19.yaml", + "section": "mhpmevent19.EVENT", + "text": "CSR mhpmevent19 field EVENT (bits=57-0) Event selector for performance counter `mhpmcounter19`. type: if (HPM_COUNTER_EN[19]) { reset: if (HPM_COUNTER_EN[19]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_5c13eca3", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent19h.yaml", + "section": "mhpmevent19h", + "text": "CSR mhpmevent19h (address=1843, priv=M): Alias of `mhpmevent19`[63:32].\n\nIntroduced with the `Sscofpmf` extension. Prior to that, there was no way to access the upper\n32-bits of `mhpmevent#{hpm_num}`.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_41b2166b", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent19h.yaml", + "section": "mhpmevent19h.OF", + "text": "CSR mhpmevent19h field OF (bits=31) Alias of mhpmevent19.OF. type: if (HPM_COUNTER_EN[19]) { reset: if (HPM_COUNTER_EN[19]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ce42f55f", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent19h.yaml", + "section": "mhpmevent19h.MINH", + "text": "CSR mhpmevent19h field MINH (bits=30) Alias of mhpmevent19.MINH. type: if (HPM_COUNTER_EN[19]) { reset: if (HPM_COUNTER_EN[19]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_7fa11ef8", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent19h.yaml", + "section": "mhpmevent19h.SINH", + "text": "CSR mhpmevent19h field SINH (bits=29) Alias of mhpmevent19.SINH. type: if ((HPM_COUNTER_EN[19]) && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { reset: if ((HPM_COUNTER_EN[19]) && implemented?(ExtensionName::S)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_e91558d2", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent19h.yaml", + "section": "mhpmevent19h.UINH", + "text": "CSR mhpmevent19h field UINH (bits=28) Alias of mhpmevent19.UINH. type: if ((HPM_COUNTER_EN[19]) && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { reset: if ((HPM_COUNTER_EN[19]) && implemented?(ExtensionName::U)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_9ad2f9ea", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent19h.yaml", + "section": "mhpmevent19h.VSINH", + "text": "CSR mhpmevent19h field VSINH (bits=27) Alias of mhpmevent19.VSINH. type: if ((HPM_COUNTER_EN[19]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[19]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_bbad7565", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent19h.yaml", + "section": "mhpmevent19h.VUINH", + "text": "CSR mhpmevent19h field VUINH (bits=26) Alias of mhpmevent19.VUINH. type: if ((HPM_COUNTER_EN[19]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[19]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_675139fc", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent19h.yaml", + "section": "mhpmevent19h.EVENT", + "text": "CSR mhpmevent19h field EVENT (bits=25-0) High part of event selector for performance counter `mhpmcounter19`. type: if (HPM_COUNTER_EN[19]) { reset: if (HPM_COUNTER_EN[19]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_7fed16b9", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent20.yaml", + "section": "mhpmevent20", + "text": "CSR mhpmevent20 (address=820, priv=M): Programmable hardware performance counter event selector\n<% if ext?(:Sscofpmf) %> and overflow/filtering control<% end %>", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_7d42b8a1", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent20.yaml", + "section": "mhpmevent20.OF", + "text": "CSR mhpmevent20 field OF (bits=63) Overflow status and interrupt disable.\n\nThe OF bit is set when the corresponding hpmcounter overflows, and remains set until written by\nsoftware. Since hpmcounter values are unsigned values, overflow is defined as unsigned\noverflow of the implemented counter bits.\n\nThe OF bit is sticky; it stays set type: if (HPM_COUNTER_EN[20]) { reset: if (HPM_COUNTER_EN[20]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_1bd32ac8", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent20.yaml", + "section": "mhpmevent20.MINH", + "text": "CSR mhpmevent20 field MINH (bits=62) When set, mhpmcounter20 does not increment while the hart in operating in M-mode. type: if (HPM_COUNTER_EN[20]) { reset: if (HPM_COUNTER_EN[20]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d2ec2738", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent20.yaml", + "section": "mhpmevent20.SINH", + "text": "CSR mhpmevent20 field SINH (bits=61) When set, mhpmcounter20 does not increment while the hart in operating in (H)S-mode. type: if (HPM_COUNTER_EN[20] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { reset: if (HPM_COUNTER_EN[20] && implemented?(ExtensionName::S)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_65438a59", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent20.yaml", + "section": "mhpmevent20.UINH", + "text": "CSR mhpmevent20 field UINH (bits=60) When set, mhpmcounter20 does not increment while the hart in operating in U-mode. type: if (HPM_COUNTER_EN[20] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { reset: if (HPM_COUNTER_EN[20] && implemented?(ExtensionName::U)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d1afd57d", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent20.yaml", + "section": "mhpmevent20.VSINH", + "text": "CSR mhpmevent20 field VSINH (bits=59) When set, mhpmcounter20 does not increment while the hart in operating in VS-mode. type: if ((HPM_COUNTER_EN[20]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if (HPM_COUNTER_EN[20] && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_c006fde8", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent20.yaml", + "section": "mhpmevent20.VUINH", + "text": "CSR mhpmevent20 field VUINH (bits=58) When set, mhpmcounter20 does not increment while the hart in operating in VU-mode. type: if (HPM_COUNTER_EN[20] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[20]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_3415385f", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent20.yaml", + "section": "mhpmevent20.EVENT", + "text": "CSR mhpmevent20 field EVENT (bits=57-0) Event selector for performance counter `mhpmcounter20`. type: if (HPM_COUNTER_EN[20]) { reset: if (HPM_COUNTER_EN[20]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d67379ac", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent20h.yaml", + "section": "mhpmevent20h", + "text": "CSR mhpmevent20h (address=1844, priv=M): Alias of `mhpmevent20`[63:32].\n\nIntroduced with the `Sscofpmf` extension. Prior to that, there was no way to access the upper\n32-bits of `mhpmevent#{hpm_num}`.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_934cd3fa", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent20h.yaml", + "section": "mhpmevent20h.OF", + "text": "CSR mhpmevent20h field OF (bits=31) Alias of mhpmevent20.OF. type: if (HPM_COUNTER_EN[20]) { reset: if (HPM_COUNTER_EN[20]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_9f038c9c", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent20h.yaml", + "section": "mhpmevent20h.MINH", + "text": "CSR mhpmevent20h field MINH (bits=30) Alias of mhpmevent20.MINH. type: if (HPM_COUNTER_EN[20]) { reset: if (HPM_COUNTER_EN[20]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ccb544ed", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent20h.yaml", + "section": "mhpmevent20h.SINH", + "text": "CSR mhpmevent20h field SINH (bits=29) Alias of mhpmevent20.SINH. type: if ((HPM_COUNTER_EN[20]) && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { reset: if ((HPM_COUNTER_EN[20]) && implemented?(ExtensionName::S)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_08c48a2f", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent20h.yaml", + "section": "mhpmevent20h.UINH", + "text": "CSR mhpmevent20h field UINH (bits=28) Alias of mhpmevent20.UINH. type: if ((HPM_COUNTER_EN[20]) && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { reset: if ((HPM_COUNTER_EN[20]) && implemented?(ExtensionName::U)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_39965a49", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent20h.yaml", + "section": "mhpmevent20h.VSINH", + "text": "CSR mhpmevent20h field VSINH (bits=27) Alias of mhpmevent20.VSINH. type: if ((HPM_COUNTER_EN[20]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[20]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_de02e6a0", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent20h.yaml", + "section": "mhpmevent20h.VUINH", + "text": "CSR mhpmevent20h field VUINH (bits=26) Alias of mhpmevent20.VUINH. type: if ((HPM_COUNTER_EN[20]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[20]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_7c837314", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent20h.yaml", + "section": "mhpmevent20h.EVENT", + "text": "CSR mhpmevent20h field EVENT (bits=25-0) High part of event selector for performance counter `mhpmcounter20`. type: if (HPM_COUNTER_EN[20]) { reset: if (HPM_COUNTER_EN[20]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_0462d639", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent21.yaml", + "section": "mhpmevent21", + "text": "CSR mhpmevent21 (address=821, priv=M): Programmable hardware performance counter event selector\n<% if ext?(:Sscofpmf) %> and overflow/filtering control<% end %>", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_838c4b62", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent21.yaml", + "section": "mhpmevent21.OF", + "text": "CSR mhpmevent21 field OF (bits=63) Overflow status and interrupt disable.\n\nThe OF bit is set when the corresponding hpmcounter overflows, and remains set until written by\nsoftware. Since hpmcounter values are unsigned values, overflow is defined as unsigned\noverflow of the implemented counter bits.\n\nThe OF bit is sticky; it stays set type: if (HPM_COUNTER_EN[21]) { reset: if (HPM_COUNTER_EN[21]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_886b527c", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent21.yaml", + "section": "mhpmevent21.MINH", + "text": "CSR mhpmevent21 field MINH (bits=62) When set, mhpmcounter21 does not increment while the hart in operating in M-mode. type: if (HPM_COUNTER_EN[21]) { reset: if (HPM_COUNTER_EN[21]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_fd4c0d19", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent21.yaml", + "section": "mhpmevent21.SINH", + "text": "CSR mhpmevent21 field SINH (bits=61) When set, mhpmcounter21 does not increment while the hart in operating in (H)S-mode. type: if (HPM_COUNTER_EN[21] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { reset: if (HPM_COUNTER_EN[21] && implemented?(ExtensionName::S)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_f6ff544c", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent21.yaml", + "section": "mhpmevent21.UINH", + "text": "CSR mhpmevent21 field UINH (bits=60) When set, mhpmcounter21 does not increment while the hart in operating in U-mode. type: if (HPM_COUNTER_EN[21] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { reset: if (HPM_COUNTER_EN[21] && implemented?(ExtensionName::U)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_7c5e7dae", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent21.yaml", + "section": "mhpmevent21.VSINH", + "text": "CSR mhpmevent21 field VSINH (bits=59) When set, mhpmcounter21 does not increment while the hart in operating in VS-mode. type: if ((HPM_COUNTER_EN[21]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if (HPM_COUNTER_EN[21] && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_2f476442", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent21.yaml", + "section": "mhpmevent21.VUINH", + "text": "CSR mhpmevent21 field VUINH (bits=58) When set, mhpmcounter21 does not increment while the hart in operating in VU-mode. type: if (HPM_COUNTER_EN[21] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[21]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_5516d8d7", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent21.yaml", + "section": "mhpmevent21.EVENT", + "text": "CSR mhpmevent21 field EVENT (bits=57-0) Event selector for performance counter `mhpmcounter21`. type: if (HPM_COUNTER_EN[21]) { reset: if (HPM_COUNTER_EN[21]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_c20a923c", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent21h.yaml", + "section": "mhpmevent21h", + "text": "CSR mhpmevent21h (address=1845, priv=M): Alias of `mhpmevent21`[63:32].\n\nIntroduced with the `Sscofpmf` extension. Prior to that, there was no way to access the upper\n32-bits of `mhpmevent#{hpm_num}`.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_a2fcac27", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent21h.yaml", + "section": "mhpmevent21h.OF", + "text": "CSR mhpmevent21h field OF (bits=31) Alias of mhpmevent21.OF. type: if (HPM_COUNTER_EN[21]) { reset: if (HPM_COUNTER_EN[21]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_c888863a", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent21h.yaml", + "section": "mhpmevent21h.MINH", + "text": "CSR mhpmevent21h field MINH (bits=30) Alias of mhpmevent21.MINH. type: if (HPM_COUNTER_EN[21]) { reset: if (HPM_COUNTER_EN[21]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_8158ac90", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent21h.yaml", + "section": "mhpmevent21h.SINH", + "text": "CSR mhpmevent21h field SINH (bits=29) Alias of mhpmevent21.SINH. type: if ((HPM_COUNTER_EN[21]) && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { reset: if ((HPM_COUNTER_EN[21]) && implemented?(ExtensionName::S)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_0fa01e18", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent21h.yaml", + "section": "mhpmevent21h.UINH", + "text": "CSR mhpmevent21h field UINH (bits=28) Alias of mhpmevent21.UINH. type: if ((HPM_COUNTER_EN[21]) && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { reset: if ((HPM_COUNTER_EN[21]) && implemented?(ExtensionName::U)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_71226eac", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent21h.yaml", + "section": "mhpmevent21h.VSINH", + "text": "CSR mhpmevent21h field VSINH (bits=27) Alias of mhpmevent21.VSINH. type: if ((HPM_COUNTER_EN[21]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[21]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_306d721a", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent21h.yaml", + "section": "mhpmevent21h.VUINH", + "text": "CSR mhpmevent21h field VUINH (bits=26) Alias of mhpmevent21.VUINH. type: if ((HPM_COUNTER_EN[21]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[21]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_8b1c7d0c", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent21h.yaml", + "section": "mhpmevent21h.EVENT", + "text": "CSR mhpmevent21h field EVENT (bits=25-0) High part of event selector for performance counter `mhpmcounter21`. type: if (HPM_COUNTER_EN[21]) { reset: if (HPM_COUNTER_EN[21]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_2a8b9a69", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent22.yaml", + "section": "mhpmevent22", + "text": "CSR mhpmevent22 (address=822, priv=M): Programmable hardware performance counter event selector\n<% if ext?(:Sscofpmf) %> and overflow/filtering control<% end %>", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_21fda497", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent22.yaml", + "section": "mhpmevent22.OF", + "text": "CSR mhpmevent22 field OF (bits=63) Overflow status and interrupt disable.\n\nThe OF bit is set when the corresponding hpmcounter overflows, and remains set until written by\nsoftware. Since hpmcounter values are unsigned values, overflow is defined as unsigned\noverflow of the implemented counter bits.\n\nThe OF bit is sticky; it stays set type: if (HPM_COUNTER_EN[22]) { reset: if (HPM_COUNTER_EN[22]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_86debc2a", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent22.yaml", + "section": "mhpmevent22.MINH", + "text": "CSR mhpmevent22 field MINH (bits=62) When set, mhpmcounter22 does not increment while the hart in operating in M-mode. type: if (HPM_COUNTER_EN[22]) { reset: if (HPM_COUNTER_EN[22]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_7e588583", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent22.yaml", + "section": "mhpmevent22.SINH", + "text": "CSR mhpmevent22 field SINH (bits=61) When set, mhpmcounter22 does not increment while the hart in operating in (H)S-mode. type: if (HPM_COUNTER_EN[22] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { reset: if (HPM_COUNTER_EN[22] && implemented?(ExtensionName::S)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_09bebb8e", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent22.yaml", + "section": "mhpmevent22.UINH", + "text": "CSR mhpmevent22 field UINH (bits=60) When set, mhpmcounter22 does not increment while the hart in operating in U-mode. type: if (HPM_COUNTER_EN[22] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { reset: if (HPM_COUNTER_EN[22] && implemented?(ExtensionName::U)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_2bb28f24", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent22.yaml", + "section": "mhpmevent22.VSINH", + "text": "CSR mhpmevent22 field VSINH (bits=59) When set, mhpmcounter22 does not increment while the hart in operating in VS-mode. type: if ((HPM_COUNTER_EN[22]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if (HPM_COUNTER_EN[22] && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_861d56a2", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent22.yaml", + "section": "mhpmevent22.VUINH", + "text": "CSR mhpmevent22 field VUINH (bits=58) When set, mhpmcounter22 does not increment while the hart in operating in VU-mode. type: if (HPM_COUNTER_EN[22] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[22]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_4d9c9778", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent22.yaml", + "section": "mhpmevent22.EVENT", + "text": "CSR mhpmevent22 field EVENT (bits=57-0) Event selector for performance counter `mhpmcounter22`. type: if (HPM_COUNTER_EN[22]) { reset: if (HPM_COUNTER_EN[22]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_89eb2d76", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent22h.yaml", + "section": "mhpmevent22h", + "text": "CSR mhpmevent22h (address=1846, priv=M): Alias of `mhpmevent22`[63:32].\n\nIntroduced with the `Sscofpmf` extension. Prior to that, there was no way to access the upper\n32-bits of `mhpmevent#{hpm_num}`.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_9cd30355", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent22h.yaml", + "section": "mhpmevent22h.OF", + "text": "CSR mhpmevent22h field OF (bits=31) Alias of mhpmevent22.OF. type: if (HPM_COUNTER_EN[22]) { reset: if (HPM_COUNTER_EN[22]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_a5884daa", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent22h.yaml", + "section": "mhpmevent22h.MINH", + "text": "CSR mhpmevent22h field MINH (bits=30) Alias of mhpmevent22.MINH. type: if (HPM_COUNTER_EN[22]) { reset: if (HPM_COUNTER_EN[22]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_1748b17e", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent22h.yaml", + "section": "mhpmevent22h.SINH", + "text": "CSR mhpmevent22h field SINH (bits=29) Alias of mhpmevent22.SINH. type: if ((HPM_COUNTER_EN[22]) && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { reset: if ((HPM_COUNTER_EN[22]) && implemented?(ExtensionName::S)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_18cb5f67", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent22h.yaml", + "section": "mhpmevent22h.UINH", + "text": "CSR mhpmevent22h field UINH (bits=28) Alias of mhpmevent22.UINH. type: if ((HPM_COUNTER_EN[22]) && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { reset: if ((HPM_COUNTER_EN[22]) && implemented?(ExtensionName::U)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_760241b3", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent22h.yaml", + "section": "mhpmevent22h.VSINH", + "text": "CSR mhpmevent22h field VSINH (bits=27) Alias of mhpmevent22.VSINH. type: if ((HPM_COUNTER_EN[22]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[22]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_1971141d", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent22h.yaml", + "section": "mhpmevent22h.VUINH", + "text": "CSR mhpmevent22h field VUINH (bits=26) Alias of mhpmevent22.VUINH. type: if ((HPM_COUNTER_EN[22]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[22]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_5adab207", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent22h.yaml", + "section": "mhpmevent22h.EVENT", + "text": "CSR mhpmevent22h field EVENT (bits=25-0) High part of event selector for performance counter `mhpmcounter22`. type: if (HPM_COUNTER_EN[22]) { reset: if (HPM_COUNTER_EN[22]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_a8c38f41", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent23.yaml", + "section": "mhpmevent23", + "text": "CSR mhpmevent23 (address=823, priv=M): Programmable hardware performance counter event selector\n<% if ext?(:Sscofpmf) %> and overflow/filtering control<% end %>", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d4e56a3f", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent23.yaml", + "section": "mhpmevent23.OF", + "text": "CSR mhpmevent23 field OF (bits=63) Overflow status and interrupt disable.\n\nThe OF bit is set when the corresponding hpmcounter overflows, and remains set until written by\nsoftware. Since hpmcounter values are unsigned values, overflow is defined as unsigned\noverflow of the implemented counter bits.\n\nThe OF bit is sticky; it stays set type: if (HPM_COUNTER_EN[23]) { reset: if (HPM_COUNTER_EN[23]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_0f149168", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent23.yaml", + "section": "mhpmevent23.MINH", + "text": "CSR mhpmevent23 field MINH (bits=62) When set, mhpmcounter23 does not increment while the hart in operating in M-mode. type: if (HPM_COUNTER_EN[23]) { reset: if (HPM_COUNTER_EN[23]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_42762131", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent23.yaml", + "section": "mhpmevent23.SINH", + "text": "CSR mhpmevent23 field SINH (bits=61) When set, mhpmcounter23 does not increment while the hart in operating in (H)S-mode. type: if (HPM_COUNTER_EN[23] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { reset: if (HPM_COUNTER_EN[23] && implemented?(ExtensionName::S)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_e1f691af", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent23.yaml", + "section": "mhpmevent23.UINH", + "text": "CSR mhpmevent23 field UINH (bits=60) When set, mhpmcounter23 does not increment while the hart in operating in U-mode. type: if (HPM_COUNTER_EN[23] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { reset: if (HPM_COUNTER_EN[23] && implemented?(ExtensionName::U)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_28c51a22", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent23.yaml", + "section": "mhpmevent23.VSINH", + "text": "CSR mhpmevent23 field VSINH (bits=59) When set, mhpmcounter23 does not increment while the hart in operating in VS-mode. type: if ((HPM_COUNTER_EN[23]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if (HPM_COUNTER_EN[23] && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_bddcaf8a", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent23.yaml", + "section": "mhpmevent23.VUINH", + "text": "CSR mhpmevent23 field VUINH (bits=58) When set, mhpmcounter23 does not increment while the hart in operating in VU-mode. type: if (HPM_COUNTER_EN[23] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[23]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_382909ae", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent23.yaml", + "section": "mhpmevent23.EVENT", + "text": "CSR mhpmevent23 field EVENT (bits=57-0) Event selector for performance counter `mhpmcounter23`. type: if (HPM_COUNTER_EN[23]) { reset: if (HPM_COUNTER_EN[23]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_90f3fbd0", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent23h.yaml", + "section": "mhpmevent23h", + "text": "CSR mhpmevent23h (address=1847, priv=M): Alias of `mhpmevent23`[63:32].\n\nIntroduced with the `Sscofpmf` extension. Prior to that, there was no way to access the upper\n32-bits of `mhpmevent#{hpm_num}`.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ebe8fe33", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent23h.yaml", + "section": "mhpmevent23h.OF", + "text": "CSR mhpmevent23h field OF (bits=31) Alias of mhpmevent23.OF. type: if (HPM_COUNTER_EN[23]) { reset: if (HPM_COUNTER_EN[23]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_647e2403", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent23h.yaml", + "section": "mhpmevent23h.MINH", + "text": "CSR mhpmevent23h field MINH (bits=30) Alias of mhpmevent23.MINH. type: if (HPM_COUNTER_EN[23]) { reset: if (HPM_COUNTER_EN[23]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_a2a18a89", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent23h.yaml", + "section": "mhpmevent23h.SINH", + "text": "CSR mhpmevent23h field SINH (bits=29) Alias of mhpmevent23.SINH. type: if ((HPM_COUNTER_EN[23]) && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { reset: if ((HPM_COUNTER_EN[23]) && implemented?(ExtensionName::S)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_89b47394", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent23h.yaml", + "section": "mhpmevent23h.UINH", + "text": "CSR mhpmevent23h field UINH (bits=28) Alias of mhpmevent23.UINH. type: if ((HPM_COUNTER_EN[23]) && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { reset: if ((HPM_COUNTER_EN[23]) && implemented?(ExtensionName::U)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_e46fcb29", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent23h.yaml", + "section": "mhpmevent23h.VSINH", + "text": "CSR mhpmevent23h field VSINH (bits=27) Alias of mhpmevent23.VSINH. type: if ((HPM_COUNTER_EN[23]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[23]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_de8754ce", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent23h.yaml", + "section": "mhpmevent23h.VUINH", + "text": "CSR mhpmevent23h field VUINH (bits=26) Alias of mhpmevent23.VUINH. type: if ((HPM_COUNTER_EN[23]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[23]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_c54abd8f", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent23h.yaml", + "section": "mhpmevent23h.EVENT", + "text": "CSR mhpmevent23h field EVENT (bits=25-0) High part of event selector for performance counter `mhpmcounter23`. type: if (HPM_COUNTER_EN[23]) { reset: if (HPM_COUNTER_EN[23]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_b844a39f", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent24.yaml", + "section": "mhpmevent24", + "text": "CSR mhpmevent24 (address=824, priv=M): Programmable hardware performance counter event selector\n<% if ext?(:Sscofpmf) %> and overflow/filtering control<% end %>", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_b64f67ea", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent24.yaml", + "section": "mhpmevent24.OF", + "text": "CSR mhpmevent24 field OF (bits=63) Overflow status and interrupt disable.\n\nThe OF bit is set when the corresponding hpmcounter overflows, and remains set until written by\nsoftware. Since hpmcounter values are unsigned values, overflow is defined as unsigned\noverflow of the implemented counter bits.\n\nThe OF bit is sticky; it stays set type: if (HPM_COUNTER_EN[24]) { reset: if (HPM_COUNTER_EN[24]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_dbd4ddd7", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent24.yaml", + "section": "mhpmevent24.MINH", + "text": "CSR mhpmevent24 field MINH (bits=62) When set, mhpmcounter24 does not increment while the hart in operating in M-mode. type: if (HPM_COUNTER_EN[24]) { reset: if (HPM_COUNTER_EN[24]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_1bb55c3a", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent24.yaml", + "section": "mhpmevent24.SINH", + "text": "CSR mhpmevent24 field SINH (bits=61) When set, mhpmcounter24 does not increment while the hart in operating in (H)S-mode. type: if (HPM_COUNTER_EN[24] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { reset: if (HPM_COUNTER_EN[24] && implemented?(ExtensionName::S)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_2b0081e5", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent24.yaml", + "section": "mhpmevent24.UINH", + "text": "CSR mhpmevent24 field UINH (bits=60) When set, mhpmcounter24 does not increment while the hart in operating in U-mode. type: if (HPM_COUNTER_EN[24] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { reset: if (HPM_COUNTER_EN[24] && implemented?(ExtensionName::U)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_4ee14606", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent24.yaml", + "section": "mhpmevent24.VSINH", + "text": "CSR mhpmevent24 field VSINH (bits=59) When set, mhpmcounter24 does not increment while the hart in operating in VS-mode. type: if ((HPM_COUNTER_EN[24]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if (HPM_COUNTER_EN[24] && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_445e72be", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent24.yaml", + "section": "mhpmevent24.VUINH", + "text": "CSR mhpmevent24 field VUINH (bits=58) When set, mhpmcounter24 does not increment while the hart in operating in VU-mode. type: if (HPM_COUNTER_EN[24] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[24]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_6db65992", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent24.yaml", + "section": "mhpmevent24.EVENT", + "text": "CSR mhpmevent24 field EVENT (bits=57-0) Event selector for performance counter `mhpmcounter24`. type: if (HPM_COUNTER_EN[24]) { reset: if (HPM_COUNTER_EN[24]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_2971290a", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent24h.yaml", + "section": "mhpmevent24h", + "text": "CSR mhpmevent24h (address=1848, priv=M): Alias of `mhpmevent24`[63:32].\n\nIntroduced with the `Sscofpmf` extension. Prior to that, there was no way to access the upper\n32-bits of `mhpmevent#{hpm_num}`.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_80325352", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent24h.yaml", + "section": "mhpmevent24h.OF", + "text": "CSR mhpmevent24h field OF (bits=31) Alias of mhpmevent24.OF. type: if (HPM_COUNTER_EN[24]) { reset: if (HPM_COUNTER_EN[24]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_597b8eb4", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent24h.yaml", + "section": "mhpmevent24h.MINH", + "text": "CSR mhpmevent24h field MINH (bits=30) Alias of mhpmevent24.MINH. type: if (HPM_COUNTER_EN[24]) { reset: if (HPM_COUNTER_EN[24]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_a3e96433", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent24h.yaml", + "section": "mhpmevent24h.SINH", + "text": "CSR mhpmevent24h field SINH (bits=29) Alias of mhpmevent24.SINH. type: if ((HPM_COUNTER_EN[24]) && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { reset: if ((HPM_COUNTER_EN[24]) && implemented?(ExtensionName::S)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_eea53dcd", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent24h.yaml", + "section": "mhpmevent24h.UINH", + "text": "CSR mhpmevent24h field UINH (bits=28) Alias of mhpmevent24.UINH. type: if ((HPM_COUNTER_EN[24]) && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { reset: if ((HPM_COUNTER_EN[24]) && implemented?(ExtensionName::U)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_223cc728", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent24h.yaml", + "section": "mhpmevent24h.VSINH", + "text": "CSR mhpmevent24h field VSINH (bits=27) Alias of mhpmevent24.VSINH. type: if ((HPM_COUNTER_EN[24]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[24]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_8882664a", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent24h.yaml", + "section": "mhpmevent24h.VUINH", + "text": "CSR mhpmevent24h field VUINH (bits=26) Alias of mhpmevent24.VUINH. type: if ((HPM_COUNTER_EN[24]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[24]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_e73185e8", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent24h.yaml", + "section": "mhpmevent24h.EVENT", + "text": "CSR mhpmevent24h field EVENT (bits=25-0) High part of event selector for performance counter `mhpmcounter24`. type: if (HPM_COUNTER_EN[24]) { reset: if (HPM_COUNTER_EN[24]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_03311804", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent25.yaml", + "section": "mhpmevent25", + "text": "CSR mhpmevent25 (address=825, priv=M): Programmable hardware performance counter event selector\n<% if ext?(:Sscofpmf) %> and overflow/filtering control<% end %>", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d60bdb69", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent25.yaml", + "section": "mhpmevent25.OF", + "text": "CSR mhpmevent25 field OF (bits=63) Overflow status and interrupt disable.\n\nThe OF bit is set when the corresponding hpmcounter overflows, and remains set until written by\nsoftware. Since hpmcounter values are unsigned values, overflow is defined as unsigned\noverflow of the implemented counter bits.\n\nThe OF bit is sticky; it stays set type: if (HPM_COUNTER_EN[25]) { reset: if (HPM_COUNTER_EN[25]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_01d5f7b5", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent25.yaml", + "section": "mhpmevent25.MINH", + "text": "CSR mhpmevent25 field MINH (bits=62) When set, mhpmcounter25 does not increment while the hart in operating in M-mode. type: if (HPM_COUNTER_EN[25]) { reset: if (HPM_COUNTER_EN[25]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_44a5d498", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent25.yaml", + "section": "mhpmevent25.SINH", + "text": "CSR mhpmevent25 field SINH (bits=61) When set, mhpmcounter25 does not increment while the hart in operating in (H)S-mode. type: if (HPM_COUNTER_EN[25] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { reset: if (HPM_COUNTER_EN[25] && implemented?(ExtensionName::S)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_825ccaa8", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent25.yaml", + "section": "mhpmevent25.UINH", + "text": "CSR mhpmevent25 field UINH (bits=60) When set, mhpmcounter25 does not increment while the hart in operating in U-mode. type: if (HPM_COUNTER_EN[25] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { reset: if (HPM_COUNTER_EN[25] && implemented?(ExtensionName::U)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_5bd91775", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent25.yaml", + "section": "mhpmevent25.VSINH", + "text": "CSR mhpmevent25 field VSINH (bits=59) When set, mhpmcounter25 does not increment while the hart in operating in VS-mode. type: if ((HPM_COUNTER_EN[25]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if (HPM_COUNTER_EN[25] && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_f8445be3", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent25.yaml", + "section": "mhpmevent25.VUINH", + "text": "CSR mhpmevent25 field VUINH (bits=58) When set, mhpmcounter25 does not increment while the hart in operating in VU-mode. type: if (HPM_COUNTER_EN[25] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[25]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_fe8d977c", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent25.yaml", + "section": "mhpmevent25.EVENT", + "text": "CSR mhpmevent25 field EVENT (bits=57-0) Event selector for performance counter `mhpmcounter25`. type: if (HPM_COUNTER_EN[25]) { reset: if (HPM_COUNTER_EN[25]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_1774e3ce", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent25h.yaml", + "section": "mhpmevent25h", + "text": "CSR mhpmevent25h (address=1849, priv=M): Alias of `mhpmevent25`[63:32].\n\nIntroduced with the `Sscofpmf` extension. Prior to that, there was no way to access the upper\n32-bits of `mhpmevent#{hpm_num}`.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_121ae739", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent25h.yaml", + "section": "mhpmevent25h.OF", + "text": "CSR mhpmevent25h field OF (bits=31) Alias of mhpmevent25.OF. type: if (HPM_COUNTER_EN[25]) { reset: if (HPM_COUNTER_EN[25]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_4f87b3da", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent25h.yaml", + "section": "mhpmevent25h.MINH", + "text": "CSR mhpmevent25h field MINH (bits=30) Alias of mhpmevent25.MINH. type: if (HPM_COUNTER_EN[25]) { reset: if (HPM_COUNTER_EN[25]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_5d2b2dd7", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent25h.yaml", + "section": "mhpmevent25h.SINH", + "text": "CSR mhpmevent25h field SINH (bits=29) Alias of mhpmevent25.SINH. type: if ((HPM_COUNTER_EN[25]) && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { reset: if ((HPM_COUNTER_EN[25]) && implemented?(ExtensionName::S)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_bd4b1e3d", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent25h.yaml", + "section": "mhpmevent25h.UINH", + "text": "CSR mhpmevent25h field UINH (bits=28) Alias of mhpmevent25.UINH. type: if ((HPM_COUNTER_EN[25]) && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { reset: if ((HPM_COUNTER_EN[25]) && implemented?(ExtensionName::U)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_61272744", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent25h.yaml", + "section": "mhpmevent25h.VSINH", + "text": "CSR mhpmevent25h field VSINH (bits=27) Alias of mhpmevent25.VSINH. type: if ((HPM_COUNTER_EN[25]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[25]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_fcd886e4", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent25h.yaml", + "section": "mhpmevent25h.VUINH", + "text": "CSR mhpmevent25h field VUINH (bits=26) Alias of mhpmevent25.VUINH. type: if ((HPM_COUNTER_EN[25]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[25]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_f3d05f11", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent25h.yaml", + "section": "mhpmevent25h.EVENT", + "text": "CSR mhpmevent25h field EVENT (bits=25-0) High part of event selector for performance counter `mhpmcounter25`. type: if (HPM_COUNTER_EN[25]) { reset: if (HPM_COUNTER_EN[25]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_89eb9a4e", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent26.yaml", + "section": "mhpmevent26", + "text": "CSR mhpmevent26 (address=826, priv=M): Programmable hardware performance counter event selector\n<% if ext?(:Sscofpmf) %> and overflow/filtering control<% end %>", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_e402a0d7", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent26.yaml", + "section": "mhpmevent26.OF", + "text": "CSR mhpmevent26 field OF (bits=63) Overflow status and interrupt disable.\n\nThe OF bit is set when the corresponding hpmcounter overflows, and remains set until written by\nsoftware. Since hpmcounter values are unsigned values, overflow is defined as unsigned\noverflow of the implemented counter bits.\n\nThe OF bit is sticky; it stays set type: if (HPM_COUNTER_EN[26]) { reset: if (HPM_COUNTER_EN[26]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_94ba8d5c", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent26.yaml", + "section": "mhpmevent26.MINH", + "text": "CSR mhpmevent26 field MINH (bits=62) When set, mhpmcounter26 does not increment while the hart in operating in M-mode. type: if (HPM_COUNTER_EN[26]) { reset: if (HPM_COUNTER_EN[26]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_60446403", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent26.yaml", + "section": "mhpmevent26.SINH", + "text": "CSR mhpmevent26 field SINH (bits=61) When set, mhpmcounter26 does not increment while the hart in operating in (H)S-mode. type: if (HPM_COUNTER_EN[26] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { reset: if (HPM_COUNTER_EN[26] && implemented?(ExtensionName::S)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_9b960006", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent26.yaml", + "section": "mhpmevent26.UINH", + "text": "CSR mhpmevent26 field UINH (bits=60) When set, mhpmcounter26 does not increment while the hart in operating in U-mode. type: if (HPM_COUNTER_EN[26] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { reset: if (HPM_COUNTER_EN[26] && implemented?(ExtensionName::U)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_068cd059", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent26.yaml", + "section": "mhpmevent26.VSINH", + "text": "CSR mhpmevent26 field VSINH (bits=59) When set, mhpmcounter26 does not increment while the hart in operating in VS-mode. type: if ((HPM_COUNTER_EN[26]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if (HPM_COUNTER_EN[26] && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_742521a8", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent26.yaml", + "section": "mhpmevent26.VUINH", + "text": "CSR mhpmevent26 field VUINH (bits=58) When set, mhpmcounter26 does not increment while the hart in operating in VU-mode. type: if (HPM_COUNTER_EN[26] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[26]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_c245890d", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent26.yaml", + "section": "mhpmevent26.EVENT", + "text": "CSR mhpmevent26 field EVENT (bits=57-0) Event selector for performance counter `mhpmcounter26`. type: if (HPM_COUNTER_EN[26]) { reset: if (HPM_COUNTER_EN[26]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d61869db", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent26h.yaml", + "section": "mhpmevent26h", + "text": "CSR mhpmevent26h (address=1850, priv=M): Alias of `mhpmevent26`[63:32].\n\nIntroduced with the `Sscofpmf` extension. Prior to that, there was no way to access the upper\n32-bits of `mhpmevent#{hpm_num}`.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_9d29fee3", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent26h.yaml", + "section": "mhpmevent26h.OF", + "text": "CSR mhpmevent26h field OF (bits=31) Alias of mhpmevent26.OF. type: if (HPM_COUNTER_EN[26]) { reset: if (HPM_COUNTER_EN[26]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_80786f8f", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent26h.yaml", + "section": "mhpmevent26h.MINH", + "text": "CSR mhpmevent26h field MINH (bits=30) Alias of mhpmevent26.MINH. type: if (HPM_COUNTER_EN[26]) { reset: if (HPM_COUNTER_EN[26]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_f263966b", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent26h.yaml", + "section": "mhpmevent26h.SINH", + "text": "CSR mhpmevent26h field SINH (bits=29) Alias of mhpmevent26.SINH. type: if ((HPM_COUNTER_EN[26]) && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { reset: if ((HPM_COUNTER_EN[26]) && implemented?(ExtensionName::S)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_17d82bb3", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent26h.yaml", + "section": "mhpmevent26h.UINH", + "text": "CSR mhpmevent26h field UINH (bits=28) Alias of mhpmevent26.UINH. type: if ((HPM_COUNTER_EN[26]) && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { reset: if ((HPM_COUNTER_EN[26]) && implemented?(ExtensionName::U)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_869355af", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent26h.yaml", + "section": "mhpmevent26h.VSINH", + "text": "CSR mhpmevent26h field VSINH (bits=27) Alias of mhpmevent26.VSINH. type: if ((HPM_COUNTER_EN[26]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[26]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_80d38c47", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent26h.yaml", + "section": "mhpmevent26h.VUINH", + "text": "CSR mhpmevent26h field VUINH (bits=26) Alias of mhpmevent26.VUINH. type: if ((HPM_COUNTER_EN[26]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[26]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_71023336", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent26h.yaml", + "section": "mhpmevent26h.EVENT", + "text": "CSR mhpmevent26h field EVENT (bits=25-0) High part of event selector for performance counter `mhpmcounter26`. type: if (HPM_COUNTER_EN[26]) { reset: if (HPM_COUNTER_EN[26]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_91f86007", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent27.yaml", + "section": "mhpmevent27", + "text": "CSR mhpmevent27 (address=827, priv=M): Programmable hardware performance counter event selector\n<% if ext?(:Sscofpmf) %> and overflow/filtering control<% end %>", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_540867c1", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent27.yaml", + "section": "mhpmevent27.OF", + "text": "CSR mhpmevent27 field OF (bits=63) Overflow status and interrupt disable.\n\nThe OF bit is set when the corresponding hpmcounter overflows, and remains set until written by\nsoftware. Since hpmcounter values are unsigned values, overflow is defined as unsigned\noverflow of the implemented counter bits.\n\nThe OF bit is sticky; it stays set type: if (HPM_COUNTER_EN[27]) { reset: if (HPM_COUNTER_EN[27]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_3a31e670", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent27.yaml", + "section": "mhpmevent27.MINH", + "text": "CSR mhpmevent27 field MINH (bits=62) When set, mhpmcounter27 does not increment while the hart in operating in M-mode. type: if (HPM_COUNTER_EN[27]) { reset: if (HPM_COUNTER_EN[27]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_e6a02cb6", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent27.yaml", + "section": "mhpmevent27.SINH", + "text": "CSR mhpmevent27 field SINH (bits=61) When set, mhpmcounter27 does not increment while the hart in operating in (H)S-mode. type: if (HPM_COUNTER_EN[27] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { reset: if (HPM_COUNTER_EN[27] && implemented?(ExtensionName::S)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_9521930a", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent27.yaml", + "section": "mhpmevent27.UINH", + "text": "CSR mhpmevent27 field UINH (bits=60) When set, mhpmcounter27 does not increment while the hart in operating in U-mode. type: if (HPM_COUNTER_EN[27] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { reset: if (HPM_COUNTER_EN[27] && implemented?(ExtensionName::U)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_e2acd91d", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent27.yaml", + "section": "mhpmevent27.VSINH", + "text": "CSR mhpmevent27 field VSINH (bits=59) When set, mhpmcounter27 does not increment while the hart in operating in VS-mode. type: if ((HPM_COUNTER_EN[27]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if (HPM_COUNTER_EN[27] && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_2e36def1", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent27.yaml", + "section": "mhpmevent27.VUINH", + "text": "CSR mhpmevent27 field VUINH (bits=58) When set, mhpmcounter27 does not increment while the hart in operating in VU-mode. type: if (HPM_COUNTER_EN[27] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[27]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_9475532d", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent27.yaml", + "section": "mhpmevent27.EVENT", + "text": "CSR mhpmevent27 field EVENT (bits=57-0) Event selector for performance counter `mhpmcounter27`. type: if (HPM_COUNTER_EN[27]) { reset: if (HPM_COUNTER_EN[27]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_a6d52a47", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent27h.yaml", + "section": "mhpmevent27h", + "text": "CSR mhpmevent27h (address=1851, priv=M): Alias of `mhpmevent27`[63:32].\n\nIntroduced with the `Sscofpmf` extension. Prior to that, there was no way to access the upper\n32-bits of `mhpmevent#{hpm_num}`.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_9566a424", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent27h.yaml", + "section": "mhpmevent27h.OF", + "text": "CSR mhpmevent27h field OF (bits=31) Alias of mhpmevent27.OF. type: if (HPM_COUNTER_EN[27]) { reset: if (HPM_COUNTER_EN[27]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_9293314e", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent27h.yaml", + "section": "mhpmevent27h.MINH", + "text": "CSR mhpmevent27h field MINH (bits=30) Alias of mhpmevent27.MINH. type: if (HPM_COUNTER_EN[27]) { reset: if (HPM_COUNTER_EN[27]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_f8d8242c", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent27h.yaml", + "section": "mhpmevent27h.SINH", + "text": "CSR mhpmevent27h field SINH (bits=29) Alias of mhpmevent27.SINH. type: if ((HPM_COUNTER_EN[27]) && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { reset: if ((HPM_COUNTER_EN[27]) && implemented?(ExtensionName::S)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_53f691ec", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent27h.yaml", + "section": "mhpmevent27h.UINH", + "text": "CSR mhpmevent27h field UINH (bits=28) Alias of mhpmevent27.UINH. type: if ((HPM_COUNTER_EN[27]) && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { reset: if ((HPM_COUNTER_EN[27]) && implemented?(ExtensionName::U)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_42631fde", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent27h.yaml", + "section": "mhpmevent27h.VSINH", + "text": "CSR mhpmevent27h field VSINH (bits=27) Alias of mhpmevent27.VSINH. type: if ((HPM_COUNTER_EN[27]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[27]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_00a5bb7a", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent27h.yaml", + "section": "mhpmevent27h.VUINH", + "text": "CSR mhpmevent27h field VUINH (bits=26) Alias of mhpmevent27.VUINH. type: if ((HPM_COUNTER_EN[27]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[27]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_69f0351e", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent27h.yaml", + "section": "mhpmevent27h.EVENT", + "text": "CSR mhpmevent27h field EVENT (bits=25-0) High part of event selector for performance counter `mhpmcounter27`. type: if (HPM_COUNTER_EN[27]) { reset: if (HPM_COUNTER_EN[27]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_e5016740", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent28.yaml", + "section": "mhpmevent28", + "text": "CSR mhpmevent28 (address=828, priv=M): Programmable hardware performance counter event selector\n<% if ext?(:Sscofpmf) %> and overflow/filtering control<% end %>", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_a484f933", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent28.yaml", + "section": "mhpmevent28.OF", + "text": "CSR mhpmevent28 field OF (bits=63) Overflow status and interrupt disable.\n\nThe OF bit is set when the corresponding hpmcounter overflows, and remains set until written by\nsoftware. Since hpmcounter values are unsigned values, overflow is defined as unsigned\noverflow of the implemented counter bits.\n\nThe OF bit is sticky; it stays set type: if (HPM_COUNTER_EN[28]) { reset: if (HPM_COUNTER_EN[28]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_df3d37f2", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent28.yaml", + "section": "mhpmevent28.MINH", + "text": "CSR mhpmevent28 field MINH (bits=62) When set, mhpmcounter28 does not increment while the hart in operating in M-mode. type: if (HPM_COUNTER_EN[28]) { reset: if (HPM_COUNTER_EN[28]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_514b5d62", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent28.yaml", + "section": "mhpmevent28.SINH", + "text": "CSR mhpmevent28 field SINH (bits=61) When set, mhpmcounter28 does not increment while the hart in operating in (H)S-mode. type: if (HPM_COUNTER_EN[28] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { reset: if (HPM_COUNTER_EN[28] && implemented?(ExtensionName::S)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_2bb31615", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent28.yaml", + "section": "mhpmevent28.UINH", + "text": "CSR mhpmevent28 field UINH (bits=60) When set, mhpmcounter28 does not increment while the hart in operating in U-mode. type: if (HPM_COUNTER_EN[28] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { reset: if (HPM_COUNTER_EN[28] && implemented?(ExtensionName::U)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_23d6da6a", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent28.yaml", + "section": "mhpmevent28.VSINH", + "text": "CSR mhpmevent28 field VSINH (bits=59) When set, mhpmcounter28 does not increment while the hart in operating in VS-mode. type: if ((HPM_COUNTER_EN[28]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if (HPM_COUNTER_EN[28] && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_4a965dec", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent28.yaml", + "section": "mhpmevent28.VUINH", + "text": "CSR mhpmevent28 field VUINH (bits=58) When set, mhpmcounter28 does not increment while the hart in operating in VU-mode. type: if (HPM_COUNTER_EN[28] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[28]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_7f99c0f1", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent28.yaml", + "section": "mhpmevent28.EVENT", + "text": "CSR mhpmevent28 field EVENT (bits=57-0) Event selector for performance counter `mhpmcounter28`. type: if (HPM_COUNTER_EN[28]) { reset: if (HPM_COUNTER_EN[28]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_b93c811e", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent28h.yaml", + "section": "mhpmevent28h", + "text": "CSR mhpmevent28h (address=1852, priv=M): Alias of `mhpmevent28`[63:32].\n\nIntroduced with the `Sscofpmf` extension. Prior to that, there was no way to access the upper\n32-bits of `mhpmevent#{hpm_num}`.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_3473ef2b", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent28h.yaml", + "section": "mhpmevent28h.OF", + "text": "CSR mhpmevent28h field OF (bits=31) Alias of mhpmevent28.OF. type: if (HPM_COUNTER_EN[28]) { reset: if (HPM_COUNTER_EN[28]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d8354941", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent28h.yaml", + "section": "mhpmevent28h.MINH", + "text": "CSR mhpmevent28h field MINH (bits=30) Alias of mhpmevent28.MINH. type: if (HPM_COUNTER_EN[28]) { reset: if (HPM_COUNTER_EN[28]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_f21d3dd5", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent28h.yaml", + "section": "mhpmevent28h.SINH", + "text": "CSR mhpmevent28h field SINH (bits=29) Alias of mhpmevent28.SINH. type: if ((HPM_COUNTER_EN[28]) && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { reset: if ((HPM_COUNTER_EN[28]) && implemented?(ExtensionName::S)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_84bbdef8", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent28h.yaml", + "section": "mhpmevent28h.UINH", + "text": "CSR mhpmevent28h field UINH (bits=28) Alias of mhpmevent28.UINH. type: if ((HPM_COUNTER_EN[28]) && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { reset: if ((HPM_COUNTER_EN[28]) && implemented?(ExtensionName::U)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_186989ef", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent28h.yaml", + "section": "mhpmevent28h.VSINH", + "text": "CSR mhpmevent28h field VSINH (bits=27) Alias of mhpmevent28.VSINH. type: if ((HPM_COUNTER_EN[28]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[28]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_3a76ae09", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent28h.yaml", + "section": "mhpmevent28h.VUINH", + "text": "CSR mhpmevent28h field VUINH (bits=26) Alias of mhpmevent28.VUINH. type: if ((HPM_COUNTER_EN[28]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[28]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_dc441981", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent28h.yaml", + "section": "mhpmevent28h.EVENT", + "text": "CSR mhpmevent28h field EVENT (bits=25-0) High part of event selector for performance counter `mhpmcounter28`. type: if (HPM_COUNTER_EN[28]) { reset: if (HPM_COUNTER_EN[28]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_b4b491a1", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent29.yaml", + "section": "mhpmevent29", + "text": "CSR mhpmevent29 (address=829, priv=M): Programmable hardware performance counter event selector\n<% if ext?(:Sscofpmf) %> and overflow/filtering control<% end %>", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_5b10ee83", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent29.yaml", + "section": "mhpmevent29.OF", + "text": "CSR mhpmevent29 field OF (bits=63) Overflow status and interrupt disable.\n\nThe OF bit is set when the corresponding hpmcounter overflows, and remains set until written by\nsoftware. Since hpmcounter values are unsigned values, overflow is defined as unsigned\noverflow of the implemented counter bits.\n\nThe OF bit is sticky; it stays set type: if (HPM_COUNTER_EN[29]) { reset: if (HPM_COUNTER_EN[29]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_1f595ad5", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent29.yaml", + "section": "mhpmevent29.MINH", + "text": "CSR mhpmevent29 field MINH (bits=62) When set, mhpmcounter29 does not increment while the hart in operating in M-mode. type: if (HPM_COUNTER_EN[29]) { reset: if (HPM_COUNTER_EN[29]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_fe79c2a4", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent29.yaml", + "section": "mhpmevent29.SINH", + "text": "CSR mhpmevent29 field SINH (bits=61) When set, mhpmcounter29 does not increment while the hart in operating in (H)S-mode. type: if (HPM_COUNTER_EN[29] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { reset: if (HPM_COUNTER_EN[29] && implemented?(ExtensionName::S)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_b397314d", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent29.yaml", + "section": "mhpmevent29.UINH", + "text": "CSR mhpmevent29 field UINH (bits=60) When set, mhpmcounter29 does not increment while the hart in operating in U-mode. type: if (HPM_COUNTER_EN[29] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { reset: if (HPM_COUNTER_EN[29] && implemented?(ExtensionName::U)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_3bf70d0c", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent29.yaml", + "section": "mhpmevent29.VSINH", + "text": "CSR mhpmevent29 field VSINH (bits=59) When set, mhpmcounter29 does not increment while the hart in operating in VS-mode. type: if ((HPM_COUNTER_EN[29]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if (HPM_COUNTER_EN[29] && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_182f4b7a", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent29.yaml", + "section": "mhpmevent29.VUINH", + "text": "CSR mhpmevent29 field VUINH (bits=58) When set, mhpmcounter29 does not increment while the hart in operating in VU-mode. type: if (HPM_COUNTER_EN[29] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[29]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_b2c76e9e", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent29.yaml", + "section": "mhpmevent29.EVENT", + "text": "CSR mhpmevent29 field EVENT (bits=57-0) Event selector for performance counter `mhpmcounter29`. type: if (HPM_COUNTER_EN[29]) { reset: if (HPM_COUNTER_EN[29]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_fac369f4", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent29h.yaml", + "section": "mhpmevent29h", + "text": "CSR mhpmevent29h (address=1853, priv=M): Alias of `mhpmevent29`[63:32].\n\nIntroduced with the `Sscofpmf` extension. Prior to that, there was no way to access the upper\n32-bits of `mhpmevent#{hpm_num}`.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_8ba38c7a", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent29h.yaml", + "section": "mhpmevent29h.OF", + "text": "CSR mhpmevent29h field OF (bits=31) Alias of mhpmevent29.OF. type: if (HPM_COUNTER_EN[29]) { reset: if (HPM_COUNTER_EN[29]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_77461d0b", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent29h.yaml", + "section": "mhpmevent29h.MINH", + "text": "CSR mhpmevent29h field MINH (bits=30) Alias of mhpmevent29.MINH. type: if (HPM_COUNTER_EN[29]) { reset: if (HPM_COUNTER_EN[29]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_709e0114", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent29h.yaml", + "section": "mhpmevent29h.SINH", + "text": "CSR mhpmevent29h field SINH (bits=29) Alias of mhpmevent29.SINH. type: if ((HPM_COUNTER_EN[29]) && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { reset: if ((HPM_COUNTER_EN[29]) && implemented?(ExtensionName::S)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_be0b2ca7", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent29h.yaml", + "section": "mhpmevent29h.UINH", + "text": "CSR mhpmevent29h field UINH (bits=28) Alias of mhpmevent29.UINH. type: if ((HPM_COUNTER_EN[29]) && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { reset: if ((HPM_COUNTER_EN[29]) && implemented?(ExtensionName::U)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_6f52c348", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent29h.yaml", + "section": "mhpmevent29h.VSINH", + "text": "CSR mhpmevent29h field VSINH (bits=27) Alias of mhpmevent29.VSINH. type: if ((HPM_COUNTER_EN[29]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[29]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_b3aaf175", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent29h.yaml", + "section": "mhpmevent29h.VUINH", + "text": "CSR mhpmevent29h field VUINH (bits=26) Alias of mhpmevent29.VUINH. type: if ((HPM_COUNTER_EN[29]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[29]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_a7d72c17", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent29h.yaml", + "section": "mhpmevent29h.EVENT", + "text": "CSR mhpmevent29h field EVENT (bits=25-0) High part of event selector for performance counter `mhpmcounter29`. type: if (HPM_COUNTER_EN[29]) { reset: if (HPM_COUNTER_EN[29]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_14046a1e", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent3.yaml", + "section": "mhpmevent3", + "text": "CSR mhpmevent3 (address=803, priv=M): Programmable hardware performance counter event selector\n<% if ext?(:Sscofpmf) %> and overflow/filtering control<% end %>", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_0b4d67a2", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent3.yaml", + "section": "mhpmevent3.OF", + "text": "CSR mhpmevent3 field OF (bits=63) Overflow status and interrupt disable.\n\nThe OF bit is set when the corresponding hpmcounter overflows, and remains set until written by\nsoftware. Since hpmcounter values are unsigned values, overflow is defined as unsigned\noverflow of the implemented counter bits.\n\nThe OF bit is sticky; it stays set type: if (HPM_COUNTER_EN[3]) { reset: if (HPM_COUNTER_EN[3]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_72421fea", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent3.yaml", + "section": "mhpmevent3.MINH", + "text": "CSR mhpmevent3 field MINH (bits=62) When set, mhpmcounter3 does not increment while the hart in operating in M-mode. type: if (HPM_COUNTER_EN[3]) { reset: if (HPM_COUNTER_EN[3]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_79a3c0cb", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent3.yaml", + "section": "mhpmevent3.SINH", + "text": "CSR mhpmevent3 field SINH (bits=61) When set, mhpmcounter3 does not increment while the hart in operating in (H)S-mode. type: if (HPM_COUNTER_EN[3] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { reset: if (HPM_COUNTER_EN[3] && implemented?(ExtensionName::S)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_5c2e87ae", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent3.yaml", + "section": "mhpmevent3.UINH", + "text": "CSR mhpmevent3 field UINH (bits=60) When set, mhpmcounter3 does not increment while the hart in operating in U-mode. type: if (HPM_COUNTER_EN[3] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { reset: if (HPM_COUNTER_EN[3] && implemented?(ExtensionName::U)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_66aff88c", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent3.yaml", + "section": "mhpmevent3.VSINH", + "text": "CSR mhpmevent3 field VSINH (bits=59) When set, mhpmcounter3 does not increment while the hart in operating in VS-mode. type: if ((HPM_COUNTER_EN[3]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if (HPM_COUNTER_EN[3] && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_4e77c40b", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent3.yaml", + "section": "mhpmevent3.VUINH", + "text": "CSR mhpmevent3 field VUINH (bits=58) When set, mhpmcounter3 does not increment while the hart in operating in VU-mode. type: if (HPM_COUNTER_EN[3] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[3]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_791dbc78", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent3.yaml", + "section": "mhpmevent3.EVENT", + "text": "CSR mhpmevent3 field EVENT (bits=57-0) Event selector for performance counter `mhpmcounter3`. type: if (HPM_COUNTER_EN[3]) { reset: if (HPM_COUNTER_EN[3]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_0f15c64f", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent30.yaml", + "section": "mhpmevent30", + "text": "CSR mhpmevent30 (address=830, priv=M): Programmable hardware performance counter event selector\n<% if ext?(:Sscofpmf) %> and overflow/filtering control<% end %>", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_c144b5c0", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent30.yaml", + "section": "mhpmevent30.OF", + "text": "CSR mhpmevent30 field OF (bits=63) Overflow status and interrupt disable.\n\nThe OF bit is set when the corresponding hpmcounter overflows, and remains set until written by\nsoftware. Since hpmcounter values are unsigned values, overflow is defined as unsigned\noverflow of the implemented counter bits.\n\nThe OF bit is sticky; it stays set type: if (HPM_COUNTER_EN[30]) { reset: if (HPM_COUNTER_EN[30]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_a41b3377", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent30.yaml", + "section": "mhpmevent30.MINH", + "text": "CSR mhpmevent30 field MINH (bits=62) When set, mhpmcounter30 does not increment while the hart in operating in M-mode. type: if (HPM_COUNTER_EN[30]) { reset: if (HPM_COUNTER_EN[30]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_38538c2d", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent30.yaml", + "section": "mhpmevent30.SINH", + "text": "CSR mhpmevent30 field SINH (bits=61) When set, mhpmcounter30 does not increment while the hart in operating in (H)S-mode. type: if (HPM_COUNTER_EN[30] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { reset: if (HPM_COUNTER_EN[30] && implemented?(ExtensionName::S)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_542bca35", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent30.yaml", + "section": "mhpmevent30.UINH", + "text": "CSR mhpmevent30 field UINH (bits=60) When set, mhpmcounter30 does not increment while the hart in operating in U-mode. type: if (HPM_COUNTER_EN[30] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { reset: if (HPM_COUNTER_EN[30] && implemented?(ExtensionName::U)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ad477253", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent30.yaml", + "section": "mhpmevent30.VSINH", + "text": "CSR mhpmevent30 field VSINH (bits=59) When set, mhpmcounter30 does not increment while the hart in operating in VS-mode. type: if ((HPM_COUNTER_EN[30]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if (HPM_COUNTER_EN[30] && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_7f649c05", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent30.yaml", + "section": "mhpmevent30.VUINH", + "text": "CSR mhpmevent30 field VUINH (bits=58) When set, mhpmcounter30 does not increment while the hart in operating in VU-mode. type: if (HPM_COUNTER_EN[30] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[30]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_64f46f23", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent30.yaml", + "section": "mhpmevent30.EVENT", + "text": "CSR mhpmevent30 field EVENT (bits=57-0) Event selector for performance counter `mhpmcounter30`. type: if (HPM_COUNTER_EN[30]) { reset: if (HPM_COUNTER_EN[30]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_907866d0", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent30h.yaml", + "section": "mhpmevent30h", + "text": "CSR mhpmevent30h (address=1854, priv=M): Alias of `mhpmevent30`[63:32].\n\nIntroduced with the `Sscofpmf` extension. Prior to that, there was no way to access the upper\n32-bits of `mhpmevent#{hpm_num}`.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_b6636819", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent30h.yaml", + "section": "mhpmevent30h.OF", + "text": "CSR mhpmevent30h field OF (bits=31) Alias of mhpmevent30.OF. type: if (HPM_COUNTER_EN[30]) { reset: if (HPM_COUNTER_EN[30]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_cb1e320d", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent30h.yaml", + "section": "mhpmevent30h.MINH", + "text": "CSR mhpmevent30h field MINH (bits=30) Alias of mhpmevent30.MINH. type: if (HPM_COUNTER_EN[30]) { reset: if (HPM_COUNTER_EN[30]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_2e1f84f0", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent30h.yaml", + "section": "mhpmevent30h.SINH", + "text": "CSR mhpmevent30h field SINH (bits=29) Alias of mhpmevent30.SINH. type: if ((HPM_COUNTER_EN[30]) && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { reset: if ((HPM_COUNTER_EN[30]) && implemented?(ExtensionName::S)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_474fe41b", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent30h.yaml", + "section": "mhpmevent30h.UINH", + "text": "CSR mhpmevent30h field UINH (bits=28) Alias of mhpmevent30.UINH. type: if ((HPM_COUNTER_EN[30]) && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { reset: if ((HPM_COUNTER_EN[30]) && implemented?(ExtensionName::U)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_754deb6b", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent30h.yaml", + "section": "mhpmevent30h.VSINH", + "text": "CSR mhpmevent30h field VSINH (bits=27) Alias of mhpmevent30.VSINH. type: if ((HPM_COUNTER_EN[30]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[30]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_f0af4870", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent30h.yaml", + "section": "mhpmevent30h.VUINH", + "text": "CSR mhpmevent30h field VUINH (bits=26) Alias of mhpmevent30.VUINH. type: if ((HPM_COUNTER_EN[30]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[30]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_4a8cc94f", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent30h.yaml", + "section": "mhpmevent30h.EVENT", + "text": "CSR mhpmevent30h field EVENT (bits=25-0) High part of event selector for performance counter `mhpmcounter30`. type: if (HPM_COUNTER_EN[30]) { reset: if (HPM_COUNTER_EN[30]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_0202abae", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent31.yaml", + "section": "mhpmevent31", + "text": "CSR mhpmevent31 (address=831, priv=M): Programmable hardware performance counter event selector\n<% if ext?(:Sscofpmf) %> and overflow/filtering control<% end %>", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_f50f6fbf", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent31.yaml", + "section": "mhpmevent31.OF", + "text": "CSR mhpmevent31 field OF (bits=63) Overflow status and interrupt disable.\n\nThe OF bit is set when the corresponding hpmcounter overflows, and remains set until written by\nsoftware. Since hpmcounter values are unsigned values, overflow is defined as unsigned\noverflow of the implemented counter bits.\n\nThe OF bit is sticky; it stays set type: if (HPM_COUNTER_EN[31]) { reset: if (HPM_COUNTER_EN[31]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d5c5ba7b", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent31.yaml", + "section": "mhpmevent31.MINH", + "text": "CSR mhpmevent31 field MINH (bits=62) When set, mhpmcounter31 does not increment while the hart in operating in M-mode. type: if (HPM_COUNTER_EN[31]) { reset: if (HPM_COUNTER_EN[31]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_5424afc2", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent31.yaml", + "section": "mhpmevent31.SINH", + "text": "CSR mhpmevent31 field SINH (bits=61) When set, mhpmcounter31 does not increment while the hart in operating in (H)S-mode. type: if (HPM_COUNTER_EN[31] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { reset: if (HPM_COUNTER_EN[31] && implemented?(ExtensionName::S)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_25dd3c73", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent31.yaml", + "section": "mhpmevent31.UINH", + "text": "CSR mhpmevent31 field UINH (bits=60) When set, mhpmcounter31 does not increment while the hart in operating in U-mode. type: if (HPM_COUNTER_EN[31] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { reset: if (HPM_COUNTER_EN[31] && implemented?(ExtensionName::U)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_df9e0752", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent31.yaml", + "section": "mhpmevent31.VSINH", + "text": "CSR mhpmevent31 field VSINH (bits=59) When set, mhpmcounter31 does not increment while the hart in operating in VS-mode. type: if ((HPM_COUNTER_EN[31]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if (HPM_COUNTER_EN[31] && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_7984d019", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent31.yaml", + "section": "mhpmevent31.VUINH", + "text": "CSR mhpmevent31 field VUINH (bits=58) When set, mhpmcounter31 does not increment while the hart in operating in VU-mode. type: if (HPM_COUNTER_EN[31] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[31]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_b036c48f", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent31.yaml", + "section": "mhpmevent31.EVENT", + "text": "CSR mhpmevent31 field EVENT (bits=57-0) Event selector for performance counter `mhpmcounter31`. type: if (HPM_COUNTER_EN[31]) { reset: if (HPM_COUNTER_EN[31]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_e6163bf0", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent31h.yaml", + "section": "mhpmevent31h", + "text": "CSR mhpmevent31h (address=1855, priv=M): Alias of `mhpmevent31`[63:32].\n\nIntroduced with the `Sscofpmf` extension. Prior to that, there was no way to access the upper\n32-bits of `mhpmevent#{hpm_num}`.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_3d8ba78b", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent31h.yaml", + "section": "mhpmevent31h.OF", + "text": "CSR mhpmevent31h field OF (bits=31) Alias of mhpmevent31.OF. type: if (HPM_COUNTER_EN[31]) { reset: if (HPM_COUNTER_EN[31]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_67055b00", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent31h.yaml", + "section": "mhpmevent31h.MINH", + "text": "CSR mhpmevent31h field MINH (bits=30) Alias of mhpmevent31.MINH. type: if (HPM_COUNTER_EN[31]) { reset: if (HPM_COUNTER_EN[31]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_e72c05fa", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent31h.yaml", + "section": "mhpmevent31h.SINH", + "text": "CSR mhpmevent31h field SINH (bits=29) Alias of mhpmevent31.SINH. type: if ((HPM_COUNTER_EN[31]) && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { reset: if ((HPM_COUNTER_EN[31]) && implemented?(ExtensionName::S)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_f6d1019c", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent31h.yaml", + "section": "mhpmevent31h.UINH", + "text": "CSR mhpmevent31h field UINH (bits=28) Alias of mhpmevent31.UINH. type: if ((HPM_COUNTER_EN[31]) && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { reset: if ((HPM_COUNTER_EN[31]) && implemented?(ExtensionName::U)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_3196eb4f", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent31h.yaml", + "section": "mhpmevent31h.VSINH", + "text": "CSR mhpmevent31h field VSINH (bits=27) Alias of mhpmevent31.VSINH. type: if ((HPM_COUNTER_EN[31]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[31]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_e32e0b10", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent31h.yaml", + "section": "mhpmevent31h.VUINH", + "text": "CSR mhpmevent31h field VUINH (bits=26) Alias of mhpmevent31.VUINH. type: if ((HPM_COUNTER_EN[31]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[31]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_19e134e7", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent31h.yaml", + "section": "mhpmevent31h.EVENT", + "text": "CSR mhpmevent31h field EVENT (bits=25-0) High part of event selector for performance counter `mhpmcounter31`. type: if (HPM_COUNTER_EN[31]) { reset: if (HPM_COUNTER_EN[31]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_5fe17ff5", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent3h.yaml", + "section": "mhpmevent3h", + "text": "CSR mhpmevent3h (address=1827, priv=M): Alias of `mhpmevent3`[63:32].\n\nIntroduced with the `Sscofpmf` extension. Prior to that, there was no way to access the upper\n32-bits of `mhpmevent#{hpm_num}`.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_88bf8e0f", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent3h.yaml", + "section": "mhpmevent3h.OF", + "text": "CSR mhpmevent3h field OF (bits=31) Alias of mhpmevent3.OF. type: if (HPM_COUNTER_EN[3]) { reset: if (HPM_COUNTER_EN[3]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ac4905c4", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent3h.yaml", + "section": "mhpmevent3h.MINH", + "text": "CSR mhpmevent3h field MINH (bits=30) Alias of mhpmevent3.MINH. type: if (HPM_COUNTER_EN[3]) { reset: if (HPM_COUNTER_EN[3]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_12f78043", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent3h.yaml", + "section": "mhpmevent3h.SINH", + "text": "CSR mhpmevent3h field SINH (bits=29) Alias of mhpmevent3.SINH. type: if ((HPM_COUNTER_EN[3]) && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { reset: if ((HPM_COUNTER_EN[3]) && implemented?(ExtensionName::S)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_7b2bb0f7", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent3h.yaml", + "section": "mhpmevent3h.UINH", + "text": "CSR mhpmevent3h field UINH (bits=28) Alias of mhpmevent3.UINH. type: if ((HPM_COUNTER_EN[3]) && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { reset: if ((HPM_COUNTER_EN[3]) && implemented?(ExtensionName::U)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_7fc53547", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent3h.yaml", + "section": "mhpmevent3h.VSINH", + "text": "CSR mhpmevent3h field VSINH (bits=27) Alias of mhpmevent3.VSINH. type: if ((HPM_COUNTER_EN[3]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[3]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_46b1298b", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent3h.yaml", + "section": "mhpmevent3h.VUINH", + "text": "CSR mhpmevent3h field VUINH (bits=26) Alias of mhpmevent3.VUINH. type: if ((HPM_COUNTER_EN[3]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[3]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_3e7b8b49", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent3h.yaml", + "section": "mhpmevent3h.EVENT", + "text": "CSR mhpmevent3h field EVENT (bits=25-0) High part of event selector for performance counter `mhpmcounter3`. type: if (HPM_COUNTER_EN[3]) { reset: if (HPM_COUNTER_EN[3]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_bbf47db6", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent4.yaml", + "section": "mhpmevent4", + "text": "CSR mhpmevent4 (address=804, priv=M): Programmable hardware performance counter event selector\n<% if ext?(:Sscofpmf) %> and overflow/filtering control<% end %>", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_14008658", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent4.yaml", + "section": "mhpmevent4.OF", + "text": "CSR mhpmevent4 field OF (bits=63) Overflow status and interrupt disable.\n\nThe OF bit is set when the corresponding hpmcounter overflows, and remains set until written by\nsoftware. Since hpmcounter values are unsigned values, overflow is defined as unsigned\noverflow of the implemented counter bits.\n\nThe OF bit is sticky; it stays set type: if (HPM_COUNTER_EN[4]) { reset: if (HPM_COUNTER_EN[4]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_04e30e0a", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent4.yaml", + "section": "mhpmevent4.MINH", + "text": "CSR mhpmevent4 field MINH (bits=62) When set, mhpmcounter4 does not increment while the hart in operating in M-mode. type: if (HPM_COUNTER_EN[4]) { reset: if (HPM_COUNTER_EN[4]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_90dd69fb", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent4.yaml", + "section": "mhpmevent4.SINH", + "text": "CSR mhpmevent4 field SINH (bits=61) When set, mhpmcounter4 does not increment while the hart in operating in (H)S-mode. type: if (HPM_COUNTER_EN[4] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { reset: if (HPM_COUNTER_EN[4] && implemented?(ExtensionName::S)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_3efaf7f2", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent4.yaml", + "section": "mhpmevent4.UINH", + "text": "CSR mhpmevent4 field UINH (bits=60) When set, mhpmcounter4 does not increment while the hart in operating in U-mode. type: if (HPM_COUNTER_EN[4] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { reset: if (HPM_COUNTER_EN[4] && implemented?(ExtensionName::U)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d5033f84", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent4.yaml", + "section": "mhpmevent4.VSINH", + "text": "CSR mhpmevent4 field VSINH (bits=59) When set, mhpmcounter4 does not increment while the hart in operating in VS-mode. type: if ((HPM_COUNTER_EN[4]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if (HPM_COUNTER_EN[4] && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_e4fb9305", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent4.yaml", + "section": "mhpmevent4.VUINH", + "text": "CSR mhpmevent4 field VUINH (bits=58) When set, mhpmcounter4 does not increment while the hart in operating in VU-mode. type: if (HPM_COUNTER_EN[4] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[4]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_c10faba2", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent4.yaml", + "section": "mhpmevent4.EVENT", + "text": "CSR mhpmevent4 field EVENT (bits=57-0) Event selector for performance counter `mhpmcounter4`. type: if (HPM_COUNTER_EN[4]) { reset: if (HPM_COUNTER_EN[4]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_31cc510c", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent4h.yaml", + "section": "mhpmevent4h", + "text": "CSR mhpmevent4h (address=1828, priv=M): Alias of `mhpmevent4`[63:32].\n\nIntroduced with the `Sscofpmf` extension. Prior to that, there was no way to access the upper\n32-bits of `mhpmevent#{hpm_num}`.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d172c581", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent4h.yaml", + "section": "mhpmevent4h.OF", + "text": "CSR mhpmevent4h field OF (bits=31) Alias of mhpmevent4.OF. type: if (HPM_COUNTER_EN[4]) { reset: if (HPM_COUNTER_EN[4]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_40cffddb", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent4h.yaml", + "section": "mhpmevent4h.MINH", + "text": "CSR mhpmevent4h field MINH (bits=30) Alias of mhpmevent4.MINH. type: if (HPM_COUNTER_EN[4]) { reset: if (HPM_COUNTER_EN[4]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_b754595f", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent4h.yaml", + "section": "mhpmevent4h.SINH", + "text": "CSR mhpmevent4h field SINH (bits=29) Alias of mhpmevent4.SINH. type: if ((HPM_COUNTER_EN[4]) && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { reset: if ((HPM_COUNTER_EN[4]) && implemented?(ExtensionName::S)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_83aa73fa", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent4h.yaml", + "section": "mhpmevent4h.UINH", + "text": "CSR mhpmevent4h field UINH (bits=28) Alias of mhpmevent4.UINH. type: if ((HPM_COUNTER_EN[4]) && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { reset: if ((HPM_COUNTER_EN[4]) && implemented?(ExtensionName::U)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_861c17c7", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent4h.yaml", + "section": "mhpmevent4h.VSINH", + "text": "CSR mhpmevent4h field VSINH (bits=27) Alias of mhpmevent4.VSINH. type: if ((HPM_COUNTER_EN[4]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[4]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_85cc405c", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent4h.yaml", + "section": "mhpmevent4h.VUINH", + "text": "CSR mhpmevent4h field VUINH (bits=26) Alias of mhpmevent4.VUINH. type: if ((HPM_COUNTER_EN[4]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[4]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_57f4fda2", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent4h.yaml", + "section": "mhpmevent4h.EVENT", + "text": "CSR mhpmevent4h field EVENT (bits=25-0) High part of event selector for performance counter `mhpmcounter4`. type: if (HPM_COUNTER_EN[4]) { reset: if (HPM_COUNTER_EN[4]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_67236f2e", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent5.yaml", + "section": "mhpmevent5", + "text": "CSR mhpmevent5 (address=805, priv=M): Programmable hardware performance counter event selector\n<% if ext?(:Sscofpmf) %> and overflow/filtering control<% end %>", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_8c221073", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent5.yaml", + "section": "mhpmevent5.OF", + "text": "CSR mhpmevent5 field OF (bits=63) Overflow status and interrupt disable.\n\nThe OF bit is set when the corresponding hpmcounter overflows, and remains set until written by\nsoftware. Since hpmcounter values are unsigned values, overflow is defined as unsigned\noverflow of the implemented counter bits.\n\nThe OF bit is sticky; it stays set type: if (HPM_COUNTER_EN[5]) { reset: if (HPM_COUNTER_EN[5]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_b5811851", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent5.yaml", + "section": "mhpmevent5.MINH", + "text": "CSR mhpmevent5 field MINH (bits=62) When set, mhpmcounter5 does not increment while the hart in operating in M-mode. type: if (HPM_COUNTER_EN[5]) { reset: if (HPM_COUNTER_EN[5]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_037fb605", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent5.yaml", + "section": "mhpmevent5.SINH", + "text": "CSR mhpmevent5 field SINH (bits=61) When set, mhpmcounter5 does not increment while the hart in operating in (H)S-mode. type: if (HPM_COUNTER_EN[5] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { reset: if (HPM_COUNTER_EN[5] && implemented?(ExtensionName::S)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_7e55cd50", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent5.yaml", + "section": "mhpmevent5.UINH", + "text": "CSR mhpmevent5 field UINH (bits=60) When set, mhpmcounter5 does not increment while the hart in operating in U-mode. type: if (HPM_COUNTER_EN[5] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { reset: if (HPM_COUNTER_EN[5] && implemented?(ExtensionName::U)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d57909e1", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent5.yaml", + "section": "mhpmevent5.VSINH", + "text": "CSR mhpmevent5 field VSINH (bits=59) When set, mhpmcounter5 does not increment while the hart in operating in VS-mode. type: if ((HPM_COUNTER_EN[5]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if (HPM_COUNTER_EN[5] && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_6e42d54a", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent5.yaml", + "section": "mhpmevent5.VUINH", + "text": "CSR mhpmevent5 field VUINH (bits=58) When set, mhpmcounter5 does not increment while the hart in operating in VU-mode. type: if (HPM_COUNTER_EN[5] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[5]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_22724b70", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent5.yaml", + "section": "mhpmevent5.EVENT", + "text": "CSR mhpmevent5 field EVENT (bits=57-0) Event selector for performance counter `mhpmcounter5`. type: if (HPM_COUNTER_EN[5]) { reset: if (HPM_COUNTER_EN[5]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_3345ead7", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent5h.yaml", + "section": "mhpmevent5h", + "text": "CSR mhpmevent5h (address=1829, priv=M): Alias of `mhpmevent5`[63:32].\n\nIntroduced with the `Sscofpmf` extension. Prior to that, there was no way to access the upper\n32-bits of `mhpmevent#{hpm_num}`.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d6c97b21", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent5h.yaml", + "section": "mhpmevent5h.OF", + "text": "CSR mhpmevent5h field OF (bits=31) Alias of mhpmevent5.OF. type: if (HPM_COUNTER_EN[5]) { reset: if (HPM_COUNTER_EN[5]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_356fa33b", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent5h.yaml", + "section": "mhpmevent5h.MINH", + "text": "CSR mhpmevent5h field MINH (bits=30) Alias of mhpmevent5.MINH. type: if (HPM_COUNTER_EN[5]) { reset: if (HPM_COUNTER_EN[5]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_4c220e71", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent5h.yaml", + "section": "mhpmevent5h.SINH", + "text": "CSR mhpmevent5h field SINH (bits=29) Alias of mhpmevent5.SINH. type: if ((HPM_COUNTER_EN[5]) && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { reset: if ((HPM_COUNTER_EN[5]) && implemented?(ExtensionName::S)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_f6850480", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent5h.yaml", + "section": "mhpmevent5h.UINH", + "text": "CSR mhpmevent5h field UINH (bits=28) Alias of mhpmevent5.UINH. type: if ((HPM_COUNTER_EN[5]) && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { reset: if ((HPM_COUNTER_EN[5]) && implemented?(ExtensionName::U)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_bd4537ed", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent5h.yaml", + "section": "mhpmevent5h.VSINH", + "text": "CSR mhpmevent5h field VSINH (bits=27) Alias of mhpmevent5.VSINH. type: if ((HPM_COUNTER_EN[5]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[5]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_995f43e8", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent5h.yaml", + "section": "mhpmevent5h.VUINH", + "text": "CSR mhpmevent5h field VUINH (bits=26) Alias of mhpmevent5.VUINH. type: if ((HPM_COUNTER_EN[5]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[5]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_dd3d2e85", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent5h.yaml", + "section": "mhpmevent5h.EVENT", + "text": "CSR mhpmevent5h field EVENT (bits=25-0) High part of event selector for performance counter `mhpmcounter5`. type: if (HPM_COUNTER_EN[5]) { reset: if (HPM_COUNTER_EN[5]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_cef45478", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent6.yaml", + "section": "mhpmevent6", + "text": "CSR mhpmevent6 (address=806, priv=M): Programmable hardware performance counter event selector\n<% if ext?(:Sscofpmf) %> and overflow/filtering control<% end %>", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_1fd552de", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent6.yaml", + "section": "mhpmevent6.OF", + "text": "CSR mhpmevent6 field OF (bits=63) Overflow status and interrupt disable.\n\nThe OF bit is set when the corresponding hpmcounter overflows, and remains set until written by\nsoftware. Since hpmcounter values are unsigned values, overflow is defined as unsigned\noverflow of the implemented counter bits.\n\nThe OF bit is sticky; it stays set type: if (HPM_COUNTER_EN[6]) { reset: if (HPM_COUNTER_EN[6]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_5c9d28a7", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent6.yaml", + "section": "mhpmevent6.MINH", + "text": "CSR mhpmevent6 field MINH (bits=62) When set, mhpmcounter6 does not increment while the hart in operating in M-mode. type: if (HPM_COUNTER_EN[6]) { reset: if (HPM_COUNTER_EN[6]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_9f7a2e0e", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent6.yaml", + "section": "mhpmevent6.SINH", + "text": "CSR mhpmevent6 field SINH (bits=61) When set, mhpmcounter6 does not increment while the hart in operating in (H)S-mode. type: if (HPM_COUNTER_EN[6] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { reset: if (HPM_COUNTER_EN[6] && implemented?(ExtensionName::S)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d161ad52", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent6.yaml", + "section": "mhpmevent6.UINH", + "text": "CSR mhpmevent6 field UINH (bits=60) When set, mhpmcounter6 does not increment while the hart in operating in U-mode. type: if (HPM_COUNTER_EN[6] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { reset: if (HPM_COUNTER_EN[6] && implemented?(ExtensionName::U)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_201041ad", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent6.yaml", + "section": "mhpmevent6.VSINH", + "text": "CSR mhpmevent6 field VSINH (bits=59) When set, mhpmcounter6 does not increment while the hart in operating in VS-mode. type: if ((HPM_COUNTER_EN[6]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if (HPM_COUNTER_EN[6] && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_0f75f166", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent6.yaml", + "section": "mhpmevent6.VUINH", + "text": "CSR mhpmevent6 field VUINH (bits=58) When set, mhpmcounter6 does not increment while the hart in operating in VU-mode. type: if (HPM_COUNTER_EN[6] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[6]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_1e97aa19", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent6.yaml", + "section": "mhpmevent6.EVENT", + "text": "CSR mhpmevent6 field EVENT (bits=57-0) Event selector for performance counter `mhpmcounter6`. type: if (HPM_COUNTER_EN[6]) { reset: if (HPM_COUNTER_EN[6]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_078bec00", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent6h.yaml", + "section": "mhpmevent6h", + "text": "CSR mhpmevent6h (address=1830, priv=M): Alias of `mhpmevent6`[63:32].\n\nIntroduced with the `Sscofpmf` extension. Prior to that, there was no way to access the upper\n32-bits of `mhpmevent#{hpm_num}`.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_b0680cec", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent6h.yaml", + "section": "mhpmevent6h.OF", + "text": "CSR mhpmevent6h field OF (bits=31) Alias of mhpmevent6.OF. type: if (HPM_COUNTER_EN[6]) { reset: if (HPM_COUNTER_EN[6]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_72ad26c6", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent6h.yaml", + "section": "mhpmevent6h.MINH", + "text": "CSR mhpmevent6h field MINH (bits=30) Alias of mhpmevent6.MINH. type: if (HPM_COUNTER_EN[6]) { reset: if (HPM_COUNTER_EN[6]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_83f612bf", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent6h.yaml", + "section": "mhpmevent6h.SINH", + "text": "CSR mhpmevent6h field SINH (bits=29) Alias of mhpmevent6.SINH. type: if ((HPM_COUNTER_EN[6]) && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { reset: if ((HPM_COUNTER_EN[6]) && implemented?(ExtensionName::S)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_51b466e4", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent6h.yaml", + "section": "mhpmevent6h.UINH", + "text": "CSR mhpmevent6h field UINH (bits=28) Alias of mhpmevent6.UINH. type: if ((HPM_COUNTER_EN[6]) && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { reset: if ((HPM_COUNTER_EN[6]) && implemented?(ExtensionName::U)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ea0a5182", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent6h.yaml", + "section": "mhpmevent6h.VSINH", + "text": "CSR mhpmevent6h field VSINH (bits=27) Alias of mhpmevent6.VSINH. type: if ((HPM_COUNTER_EN[6]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[6]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ee29d1ff", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent6h.yaml", + "section": "mhpmevent6h.VUINH", + "text": "CSR mhpmevent6h field VUINH (bits=26) Alias of mhpmevent6.VUINH. type: if ((HPM_COUNTER_EN[6]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[6]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_df69bf38", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent6h.yaml", + "section": "mhpmevent6h.EVENT", + "text": "CSR mhpmevent6h field EVENT (bits=25-0) High part of event selector for performance counter `mhpmcounter6`. type: if (HPM_COUNTER_EN[6]) { reset: if (HPM_COUNTER_EN[6]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_307eda3a", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent7.yaml", + "section": "mhpmevent7", + "text": "CSR mhpmevent7 (address=807, priv=M): Programmable hardware performance counter event selector\n<% if ext?(:Sscofpmf) %> and overflow/filtering control<% end %>", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_eb5a01a4", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent7.yaml", + "section": "mhpmevent7.OF", + "text": "CSR mhpmevent7 field OF (bits=63) Overflow status and interrupt disable.\n\nThe OF bit is set when the corresponding hpmcounter overflows, and remains set until written by\nsoftware. Since hpmcounter values are unsigned values, overflow is defined as unsigned\noverflow of the implemented counter bits.\n\nThe OF bit is sticky; it stays set type: if (HPM_COUNTER_EN[7]) { reset: if (HPM_COUNTER_EN[7]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_a91038e0", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent7.yaml", + "section": "mhpmevent7.MINH", + "text": "CSR mhpmevent7 field MINH (bits=62) When set, mhpmcounter7 does not increment while the hart in operating in M-mode. type: if (HPM_COUNTER_EN[7]) { reset: if (HPM_COUNTER_EN[7]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_429e97f0", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent7.yaml", + "section": "mhpmevent7.SINH", + "text": "CSR mhpmevent7 field SINH (bits=61) When set, mhpmcounter7 does not increment while the hart in operating in (H)S-mode. type: if (HPM_COUNTER_EN[7] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { reset: if (HPM_COUNTER_EN[7] && implemented?(ExtensionName::S)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_7bb8e98a", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent7.yaml", + "section": "mhpmevent7.UINH", + "text": "CSR mhpmevent7 field UINH (bits=60) When set, mhpmcounter7 does not increment while the hart in operating in U-mode. type: if (HPM_COUNTER_EN[7] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { reset: if (HPM_COUNTER_EN[7] && implemented?(ExtensionName::U)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d7f16aed", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent7.yaml", + "section": "mhpmevent7.VSINH", + "text": "CSR mhpmevent7 field VSINH (bits=59) When set, mhpmcounter7 does not increment while the hart in operating in VS-mode. type: if ((HPM_COUNTER_EN[7]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if (HPM_COUNTER_EN[7] && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d0de560a", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent7.yaml", + "section": "mhpmevent7.VUINH", + "text": "CSR mhpmevent7 field VUINH (bits=58) When set, mhpmcounter7 does not increment while the hart in operating in VU-mode. type: if (HPM_COUNTER_EN[7] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[7]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_2b4811c6", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent7.yaml", + "section": "mhpmevent7.EVENT", + "text": "CSR mhpmevent7 field EVENT (bits=57-0) Event selector for performance counter `mhpmcounter7`. type: if (HPM_COUNTER_EN[7]) { reset: if (HPM_COUNTER_EN[7]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d78b2757", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent7h.yaml", + "section": "mhpmevent7h", + "text": "CSR mhpmevent7h (address=1831, priv=M): Alias of `mhpmevent7`[63:32].\n\nIntroduced with the `Sscofpmf` extension. Prior to that, there was no way to access the upper\n32-bits of `mhpmevent#{hpm_num}`.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_5c9c08e6", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent7h.yaml", + "section": "mhpmevent7h.OF", + "text": "CSR mhpmevent7h field OF (bits=31) Alias of mhpmevent7.OF. type: if (HPM_COUNTER_EN[7]) { reset: if (HPM_COUNTER_EN[7]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_b2f2a1ab", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent7h.yaml", + "section": "mhpmevent7h.MINH", + "text": "CSR mhpmevent7h field MINH (bits=30) Alias of mhpmevent7.MINH. type: if (HPM_COUNTER_EN[7]) { reset: if (HPM_COUNTER_EN[7]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ce4dd454", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent7h.yaml", + "section": "mhpmevent7h.SINH", + "text": "CSR mhpmevent7h field SINH (bits=29) Alias of mhpmevent7.SINH. type: if ((HPM_COUNTER_EN[7]) && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { reset: if ((HPM_COUNTER_EN[7]) && implemented?(ExtensionName::S)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_f8abc163", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent7h.yaml", + "section": "mhpmevent7h.UINH", + "text": "CSR mhpmevent7h field UINH (bits=28) Alias of mhpmevent7.UINH. type: if ((HPM_COUNTER_EN[7]) && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { reset: if ((HPM_COUNTER_EN[7]) && implemented?(ExtensionName::U)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_deecf18c", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent7h.yaml", + "section": "mhpmevent7h.VSINH", + "text": "CSR mhpmevent7h field VSINH (bits=27) Alias of mhpmevent7.VSINH. type: if ((HPM_COUNTER_EN[7]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[7]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_4f1ba956", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent7h.yaml", + "section": "mhpmevent7h.VUINH", + "text": "CSR mhpmevent7h field VUINH (bits=26) Alias of mhpmevent7.VUINH. type: if ((HPM_COUNTER_EN[7]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[7]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_7a191bce", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent7h.yaml", + "section": "mhpmevent7h.EVENT", + "text": "CSR mhpmevent7h field EVENT (bits=25-0) High part of event selector for performance counter `mhpmcounter7`. type: if (HPM_COUNTER_EN[7]) { reset: if (HPM_COUNTER_EN[7]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_9fa4f4f4", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent8.yaml", + "section": "mhpmevent8", + "text": "CSR mhpmevent8 (address=808, priv=M): Programmable hardware performance counter event selector\n<% if ext?(:Sscofpmf) %> and overflow/filtering control<% end %>", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ede29c00", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent8.yaml", + "section": "mhpmevent8.OF", + "text": "CSR mhpmevent8 field OF (bits=63) Overflow status and interrupt disable.\n\nThe OF bit is set when the corresponding hpmcounter overflows, and remains set until written by\nsoftware. Since hpmcounter values are unsigned values, overflow is defined as unsigned\noverflow of the implemented counter bits.\n\nThe OF bit is sticky; it stays set type: if (HPM_COUNTER_EN[8]) { reset: if (HPM_COUNTER_EN[8]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_81c3d2f5", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent8.yaml", + "section": "mhpmevent8.MINH", + "text": "CSR mhpmevent8 field MINH (bits=62) When set, mhpmcounter8 does not increment while the hart in operating in M-mode. type: if (HPM_COUNTER_EN[8]) { reset: if (HPM_COUNTER_EN[8]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_58684cd9", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent8.yaml", + "section": "mhpmevent8.SINH", + "text": "CSR mhpmevent8 field SINH (bits=61) When set, mhpmcounter8 does not increment while the hart in operating in (H)S-mode. type: if (HPM_COUNTER_EN[8] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { reset: if (HPM_COUNTER_EN[8] && implemented?(ExtensionName::S)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_b9c70385", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent8.yaml", + "section": "mhpmevent8.UINH", + "text": "CSR mhpmevent8 field UINH (bits=60) When set, mhpmcounter8 does not increment while the hart in operating in U-mode. type: if (HPM_COUNTER_EN[8] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { reset: if (HPM_COUNTER_EN[8] && implemented?(ExtensionName::U)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_98fa5f21", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent8.yaml", + "section": "mhpmevent8.VSINH", + "text": "CSR mhpmevent8 field VSINH (bits=59) When set, mhpmcounter8 does not increment while the hart in operating in VS-mode. type: if ((HPM_COUNTER_EN[8]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if (HPM_COUNTER_EN[8] && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_47041ee2", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent8.yaml", + "section": "mhpmevent8.VUINH", + "text": "CSR mhpmevent8 field VUINH (bits=58) When set, mhpmcounter8 does not increment while the hart in operating in VU-mode. type: if (HPM_COUNTER_EN[8] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[8]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_3180917c", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent8.yaml", + "section": "mhpmevent8.EVENT", + "text": "CSR mhpmevent8 field EVENT (bits=57-0) Event selector for performance counter `mhpmcounter8`. type: if (HPM_COUNTER_EN[8]) { reset: if (HPM_COUNTER_EN[8]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_146b6dd4", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent8h.yaml", + "section": "mhpmevent8h", + "text": "CSR mhpmevent8h (address=1832, priv=M): Alias of `mhpmevent8`[63:32].\n\nIntroduced with the `Sscofpmf` extension. Prior to that, there was no way to access the upper\n32-bits of `mhpmevent#{hpm_num}`.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_293546c4", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent8h.yaml", + "section": "mhpmevent8h.OF", + "text": "CSR mhpmevent8h field OF (bits=31) Alias of mhpmevent8.OF. type: if (HPM_COUNTER_EN[8]) { reset: if (HPM_COUNTER_EN[8]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_b0062349", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent8h.yaml", + "section": "mhpmevent8h.MINH", + "text": "CSR mhpmevent8h field MINH (bits=30) Alias of mhpmevent8.MINH. type: if (HPM_COUNTER_EN[8]) { reset: if (HPM_COUNTER_EN[8]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_7c35f702", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent8h.yaml", + "section": "mhpmevent8h.SINH", + "text": "CSR mhpmevent8h field SINH (bits=29) Alias of mhpmevent8.SINH. type: if ((HPM_COUNTER_EN[8]) && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { reset: if ((HPM_COUNTER_EN[8]) && implemented?(ExtensionName::S)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_5a21175a", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent8h.yaml", + "section": "mhpmevent8h.UINH", + "text": "CSR mhpmevent8h field UINH (bits=28) Alias of mhpmevent8.UINH. type: if ((HPM_COUNTER_EN[8]) && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { reset: if ((HPM_COUNTER_EN[8]) && implemented?(ExtensionName::U)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_881c7529", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent8h.yaml", + "section": "mhpmevent8h.VSINH", + "text": "CSR mhpmevent8h field VSINH (bits=27) Alias of mhpmevent8.VSINH. type: if ((HPM_COUNTER_EN[8]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[8]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_61a4ecfc", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent8h.yaml", + "section": "mhpmevent8h.VUINH", + "text": "CSR mhpmevent8h field VUINH (bits=26) Alias of mhpmevent8.VUINH. type: if ((HPM_COUNTER_EN[8]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[8]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ed92b5e7", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent8h.yaml", + "section": "mhpmevent8h.EVENT", + "text": "CSR mhpmevent8h field EVENT (bits=25-0) High part of event selector for performance counter `mhpmcounter8`. type: if (HPM_COUNTER_EN[8]) { reset: if (HPM_COUNTER_EN[8]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_3b8f1916", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent9.yaml", + "section": "mhpmevent9", + "text": "CSR mhpmevent9 (address=809, priv=M): Programmable hardware performance counter event selector\n<% if ext?(:Sscofpmf) %> and overflow/filtering control<% end %>", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_7ac23141", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent9.yaml", + "section": "mhpmevent9.OF", + "text": "CSR mhpmevent9 field OF (bits=63) Overflow status and interrupt disable.\n\nThe OF bit is set when the corresponding hpmcounter overflows, and remains set until written by\nsoftware. Since hpmcounter values are unsigned values, overflow is defined as unsigned\noverflow of the implemented counter bits.\n\nThe OF bit is sticky; it stays set type: if (HPM_COUNTER_EN[9]) { reset: if (HPM_COUNTER_EN[9]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ee425050", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent9.yaml", + "section": "mhpmevent9.MINH", + "text": "CSR mhpmevent9 field MINH (bits=62) When set, mhpmcounter9 does not increment while the hart in operating in M-mode. type: if (HPM_COUNTER_EN[9]) { reset: if (HPM_COUNTER_EN[9]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_aef565b5", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent9.yaml", + "section": "mhpmevent9.SINH", + "text": "CSR mhpmevent9 field SINH (bits=61) When set, mhpmcounter9 does not increment while the hart in operating in (H)S-mode. type: if (HPM_COUNTER_EN[9] && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { reset: if (HPM_COUNTER_EN[9] && implemented?(ExtensionName::S)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_31ded4d3", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent9.yaml", + "section": "mhpmevent9.UINH", + "text": "CSR mhpmevent9 field UINH (bits=60) When set, mhpmcounter9 does not increment while the hart in operating in U-mode. type: if (HPM_COUNTER_EN[9] && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { reset: if (HPM_COUNTER_EN[9] && implemented?(ExtensionName::U)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_fb97eead", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent9.yaml", + "section": "mhpmevent9.VSINH", + "text": "CSR mhpmevent9 field VSINH (bits=59) When set, mhpmcounter9 does not increment while the hart in operating in VS-mode. type: if ((HPM_COUNTER_EN[9]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if (HPM_COUNTER_EN[9] && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ea26d7b5", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent9.yaml", + "section": "mhpmevent9.VUINH", + "text": "CSR mhpmevent9 field VUINH (bits=58) When set, mhpmcounter9 does not increment while the hart in operating in VU-mode. type: if (HPM_COUNTER_EN[9] && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[9]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_7127e305", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent9.yaml", + "section": "mhpmevent9.EVENT", + "text": "CSR mhpmevent9 field EVENT (bits=57-0) Event selector for performance counter `mhpmcounter9`. type: if (HPM_COUNTER_EN[9]) { reset: if (HPM_COUNTER_EN[9]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d44377c9", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent9h.yaml", + "section": "mhpmevent9h", + "text": "CSR mhpmevent9h (address=1833, priv=M): Alias of `mhpmevent9`[63:32].\n\nIntroduced with the `Sscofpmf` extension. Prior to that, there was no way to access the upper\n32-bits of `mhpmevent#{hpm_num}`.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_9a89285e", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent9h.yaml", + "section": "mhpmevent9h.OF", + "text": "CSR mhpmevent9h field OF (bits=31) Alias of mhpmevent9.OF. type: if (HPM_COUNTER_EN[9]) { reset: if (HPM_COUNTER_EN[9]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_785a170d", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent9h.yaml", + "section": "mhpmevent9h.MINH", + "text": "CSR mhpmevent9h field MINH (bits=30) Alias of mhpmevent9.MINH. type: if (HPM_COUNTER_EN[9]) { reset: if (HPM_COUNTER_EN[9]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_9022e1c2", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent9h.yaml", + "section": "mhpmevent9h.SINH", + "text": "CSR mhpmevent9h field SINH (bits=29) Alias of mhpmevent9.SINH. type: if ((HPM_COUNTER_EN[9]) && implemented?(ExtensionName::S) && (CSR[misa].S == 1'b1)) { reset: if ((HPM_COUNTER_EN[9]) && implemented?(ExtensionName::S)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_24c3285b", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent9h.yaml", + "section": "mhpmevent9h.UINH", + "text": "CSR mhpmevent9h field UINH (bits=28) Alias of mhpmevent9.UINH. type: if ((HPM_COUNTER_EN[9]) && implemented?(ExtensionName::U) && (CSR[misa].U == 1'b1)) { reset: if ((HPM_COUNTER_EN[9]) && implemented?(ExtensionName::U)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_a6f3dac4", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent9h.yaml", + "section": "mhpmevent9h.VSINH", + "text": "CSR mhpmevent9h field VSINH (bits=27) Alias of mhpmevent9.VSINH. type: if ((HPM_COUNTER_EN[9]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[9]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_3b6a3efe", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent9h.yaml", + "section": "mhpmevent9h.VUINH", + "text": "CSR mhpmevent9h field VUINH (bits=26) Alias of mhpmevent9.VUINH. type: if ((HPM_COUNTER_EN[9]) && implemented?(ExtensionName::H) && (CSR[misa].H == 1'b1)) { reset: if ((HPM_COUNTER_EN[9]) && implemented?(ExtensionName::H)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_f9bedfa3", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/Zihpm/mhpmevent9h.yaml", + "section": "mhpmevent9h.EVENT", + "text": "CSR mhpmevent9h field EVENT (bits=25-0) High part of event selector for performance counter `mhpmcounter9`. type: if (HPM_COUNTER_EN[9]) { reset: if (HPM_COUNTER_EN[9]) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d25dc43d", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/cycle.yaml", + "section": "cycle", + "text": "CSR cycle (address=3072, priv=U): Alias for M-mode CSR `mcycle`.\n\nPrivilege mode access is controlled with `mcounteren.CY`, `scounteren.CY`, and `hcounteren.CY` as follows:\n\n[%autowidth,cols=\"1,1,1,1,1,1,1\",separator=\"!\"]\n!===\n.2+h![.rotate]#`mcounteren.CY`# .2+h! [.rotate]#`scounteren.CY`# .2+h! [.rotate]#`hcounteren.CY`#\n4+^.>h! `", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Zicntr" + }, + { + "chunk_id": "chunk_a89b6a06", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/cycle.yaml", + "section": "cycle.COUNT", + "text": "CSR cycle field COUNT (bits=63-0) Alias of `mcycle.COUNT`. type: RO-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_c9d66953", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/cycleh.yaml", + "section": "cycleh", + "text": "CSR cycleh (address=3200, priv=U): Alias for M-mode CSR `mcycleh`.\n\nPrivilege mode access is controlled with `mcounteren.CY`, `scounteren.CY`, and `hcounteren.CY` as follows:\n\n[%autowidth,cols=\"1,1,1,1,1,1,1\",separator=\"!\"]\n!===\n.2+h![.rotate]#`mcounteren.CY`# .2+h! [.rotate]#`scounteren.CY`# .2+h! [.rotate]#`hcounteren.CY`#\n4+^.>h! ", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_82e64364", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/cycleh.yaml", + "section": "cycleh.COUNT", + "text": "CSR cycleh field COUNT (bits=31-0) Alias of `mcycleh.COUNT`. type: RO-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_f9e8635f", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/dcsr.yaml", + "section": "dcsr", + "text": "CSR dcsr (address=1968, priv=D): Upon entry into Debug Mode, v and prv are updated with the privilege level the hart was previously in,\nand cause is updated with the reason for Debug Mode entry. Other than these fields and nmip, the\nother fields of dcsr are only writable by the external debugger.\n\nPriority of reasons for entering D", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Sdext" + }, + { + "chunk_id": "chunk_95b65109", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/dcsr.yaml", + "section": "dcsr.DEBUGVER", + "text": "CSR dcsr field DEBUGVER (bits=31-28) 0 (none):: There is no debug support.\n4 (1.0):: Debug support exists as it is described in this document.\n15 (custom):: There is debug support, but it does not conform to any available version of this spec. type: RO reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_2b38810c", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/dcsr.yaml", + "section": "dcsr.EXTCAUSE", + "text": "CSR dcsr field EXTCAUSE (bits=26-24) When cause is 7, this optional field contains the value of a more specific halt reason than \"other.\"\nOtherwise it contains 0.\n\n0 (critical error):: The hart entered a critical error state, as defined in the Smdbltrp extension.\n\nAll other values are reserved for future versions of this spec, or for u type: RO", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_3828e25f", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/dcsr.yaml", + "section": "dcsr.CETRIG", + "text": "CSR dcsr field CETRIG (bits=19) This bit is part of Smdbltrp and only exists when that extension is implemented.\n0 (disabled):: A hart in a critical error state does not enter\nDebug Mode but instead asserts the critical-error signal to\nthe platform.\n1 (enabled):: A hart in a critical error state enters Debug\nMode instead of assert type: RW", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_8228f7c1", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/dcsr.yaml", + "section": "dcsr.PELP", + "text": "CSR dcsr field PELP (bits=18) This bit is part of Zicfilp and only exists when that extension is implemented.\n0 (NO_LP_EXPECTED):: No landing pad instruction expected.\n1 (LP_EXPECTED):: A landing pad instruction is expected. type: RW", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_1f808ece", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/dcsr.yaml", + "section": "dcsr.EBREAKVS", + "text": "CSR dcsr field EBREAKVS (bits=17) 0 (exception):: ebreak instructions in VS-mode behave as described in the Privileged Spec.\n1 (debug mode):: ebreak instructions in VS-mode enter Debug Mode.\nThis bit is hardwired to 0 if the hart does not support virtualization mode. type: RW", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_09ccbd27", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/dcsr.yaml", + "section": "dcsr.EBREAKVU", + "text": "CSR dcsr field EBREAKVU (bits=16) 0 (exception):: ebreak instructions in VU-mode behave as described in the Privileged Spec.\n1 (debug mode):: ebreak instructions in VU-mode enter Debug Mode.\nThis bit is hardwired to 0 if the hart does not support virtualization mode. type: RW", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_64b990f4", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/dcsr.yaml", + "section": "dcsr.EBREAKM", + "text": "CSR dcsr field EBREAKM (bits=15) 0 (exception):: ebreak instructions in M-mode behave as described in the Privileged Spec.\n1 (debug mode):: ebreak instructions in M-mode enter Debug Mode. type: RW", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_2639ba12", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/dcsr.yaml", + "section": "dcsr.EBREAKS", + "text": "CSR dcsr field EBREAKS (bits=13) 0 (exception):: ebreak instructions in S-mode behave as described in the Privileged Spec.\n1 (debug mode):: ebreak instructions in S-mode enter Debug Mode.\nThis bit is hardwired to 0 if the hart does not support S-mode. type: RW", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_51b5320d", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/dcsr.yaml", + "section": "dcsr.EBREAKU", + "text": "CSR dcsr field EBREAKU (bits=12) 0 (exception):: ebreak instructions in U-mode behave as described in the Privileged Spec.\n1 (debug mode):: ebreak instructions in U-mode enter Debug Mode.\nThis bit is hardwired to 0 if the hart does not support U-mode. type: RW", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_cc5102ff", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/dcsr.yaml", + "section": "dcsr.STEPIE", + "text": "CSR dcsr field STEPIE (bits=11) 0 (interrupts disabled):: Interrupts (including NMI) are disabled during single stepping with step set.\nThis value should be supported.\n1 (interrupts enabled):: Interrupts (including NMI) are enabled during single stepping with step set.\nImplementations may hard wire this bit to 0. In that case inte type: if (DCSR_STEPIE_TYPE == \"read-only-0\" || DCSR_STEPIE_TYPE == \"read-only-1\") { reset: if (DCSR_STEPIE_TYPE == \"read-only-0\") {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_4528195e", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/dcsr.yaml", + "section": "dcsr.STOPCOUNT", + "text": "CSR dcsr field STOPCOUNT (bits=10) 0 (normal):: Increment counters as usual.\n1 (freeze):: Don’t increment any hart-local counters while in Debug Mode or on ebreak instructions\nthat cause entry into Debug Mode. These counters include the instret CSR. On single-hart cores cycle\nshould be stopped, but on multi-hart cores it must keep in type: if (DCSR_STOPCOUNT_TYPE == \"read-only-0\" || DCSR_STOPCOUNT_TYPE == \"read-only-1\") { reset: if (DCSR_STOPCOUNT_TYPE == \"read-only-0\") {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_42d42569", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/dcsr.yaml", + "section": "dcsr.STOPTIME", + "text": "CSR dcsr field STOPTIME (bits=9) 0 (normal):: time continues to reflect mtime.\n1 (freeze):: time is frozen at the time that Debug Mode was entered. When leaving Debug Mode,\ntime will reflect the latest value of mtime again.\nWhile all harts have stoptime=1 and are in Debug Mode, mtime is allowed to stop incrementing.\nAn implementati type: if (DCSR_STOPTIME_TYPE == \"read-only-0\" || DCSR_STOPTIME_TYPE == \"read-only-1\") { reset: if (DCSR_STOPTIME_TYPE == \"read-only-0\") {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_76719914", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/dcsr.yaml", + "section": "dcsr.CAUSE", + "text": "CSR dcsr field CAUSE (bits=8-6) Explains why Debug Mode was entered.\nWhen there are multiple reasons to enter Debug Mode in a\nsingle cycle, hardware should set cause to the cause with\nthe highest priority.\n1 (ebreak):: An ebreak instruction was executed.\n2 (trigger):: A Trigger Module trigger fired with action=1.\n3 (haltreq):: The type: RO", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_2fc3f046", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/dcsr.yaml", + "section": "dcsr.V", + "text": "CSR dcsr field V (bits=5) Extends the prv field with the virtualization mode the hart was operating in\nwhen Debug Mode was entered. A debugger can change this value to change the\nhart’s virtualization mode when exiting Debug Mode. This bit is hardwired to 0 on harts\nthat do not support virtualization mode. type: RW", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_1bdfc6f3", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/dcsr.yaml", + "section": "dcsr.MPRVEN", + "text": "CSR dcsr field MPRVEN (bits=4) 0 (disabled):: mprv in mstatus is ignored in Debug Mode.\n1 (enabled):: mprv in mstatus takes effect in Debug Mode.\nImplementing this bit is optional. It may be tied to either 0 or 1. type: if (DCSR_MPRVEN_TYPE == \"read-only-0\" || DCSR_MPRVEN_TYPE == \"read-only-1\") { reset: if (DCSR_MPRVEN_TYPE == \"read-only-0\") {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_90dcd7bc", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/dcsr.yaml", + "section": "dcsr.NMIP", + "text": "CSR dcsr field NMIP (bits=3) When set, there is a Non-Maskable-Interrupt (NMI) pending for the hart.\nSince an NMI can indicate a hardware error condition, reliable debugging\nmay no longer be possible once this bit becomes set. This is implementation-dependent. type: RO", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_9eebe014", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/dcsr.yaml", + "section": "dcsr.STEP", + "text": "CSR dcsr field STEP (bits=2) When set and not in Debug Mode, the hart will only execute a single instruction\nand then enter Debug Mode.\nThe debugger must not change the value of this bit while the hart is running. type: RW", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_7b028ea5", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/dcsr.yaml", + "section": "dcsr.PRV", + "text": "CSR dcsr field PRV (bits=1-0) Contains the privilege mode the hart was operating in when Debug Mode was entered.\nA debugger can change this value to change the hart’s privilege mode when exiting\nDebug Mode.\n\nNot all privilege modes are supported on all harts. If the encoding written is not\nsupported or the debugger is not allowe type: RW reset: 3", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_f61b2ba3", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/dpc.yaml", + "section": "dpc", + "text": "CSR dpc (address=1969, priv=D): Upon entry to debug mode, dpc is updated with the virtual address of the next instruction to be executed.\n\nExecuting the Program Buffer may cause the value of dpc to become UNSPECIFIED. If that is the case,\nit must be possible to read/write dpc using an abstract command with postexec not set. The de", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Sdext" + }, + { + "chunk_id": "chunk_42b0948f", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/dpc.yaml", + "section": "dpc.DPC", + "text": "CSR dpc field DPC (bits=rv32=31-0 rv64=63-0) Debug PC Value type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_89fd3e2d", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/dscratch0.yaml", + "section": "dscratch0", + "text": "CSR dscratch0 (address=1970, priv=D): Optional scratch register that can be used by implementations that need it. A debugger must\nnot write to this register unless hartinfo explicitly mentions it (the Debug Module may use this\nregister internally).", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Sdext" + }, + { + "chunk_id": "chunk_52afd85a", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/dscratch0.yaml", + "section": "dscratch0.VALUE", + "text": "CSR dscratch0 field VALUE (bits=rv32=31-0 rv64=63-0) Scratch field to hold a value used by debug routines. type: RW-H", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_a90b2a09", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/dscratch1.yaml", + "section": "dscratch1", + "text": "CSR dscratch1 (address=1971, priv=D): Optional scratch register that can be used by implementations that need it. A debugger must\nnot write to this register unless hartinfo explicitly mentions it (the Debug Module may use this\nregister internally).", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Sdext" + }, + { + "chunk_id": "chunk_7d4f6507", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/dscratch1.yaml", + "section": "dscratch1.VALUE", + "text": "CSR dscratch1 field VALUE (bits=rv32=31-0 rv64=63-0) Scratch field to hold a value used by debug routines. type: RW-H", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ada30bd5", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hcontext.yaml", + "section": "hcontext", + "text": "CSR hcontext (address=1704, priv=S): This optional register may be implemented only if the H extension is implemented.\nIf it is implemented, `mcontext` must also be implemented.\n\nThis register is only accessible in HS-Mode, M-mode and Debug Mode. If Smstateen is implemented,\nthen accessibility of in HS-Mode is controlled by `mstateen0[", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_9c91e098", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hcontext.yaml", + "section": "hcontext.HCONTEXT", + "text": "CSR hcontext field HCONTEXT (bits=13-0) Alias of `mcontext.HCONTEXT`. type: RW", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_0cb5990f", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hedeleg.yaml", + "section": "hedeleg", + "text": "CSR hedeleg (address=1538, priv=S): Controls exception delegation from HS-mode to VS-mode.\n\nBy default, all traps at any privilege level are handled in M-mode, though M-mode usually uses\nthe `medeleg` and `mideleg` CSRs to delegate some traps to HS-mode. The `hedeleg` and `hideleg`\nCSRs allow these traps to be further delegated to a V", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "H" + }, + { + "chunk_id": "chunk_a51eb528", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hedeleg.yaml", + "section": "hedeleg.IAM", + "text": "CSR hedeleg field IAM (bits=rv32=? rv64=?) *Instruction Address Misaligned*\n\nControls delegation of Instruction Address Misaligned exceptions to VS-mode.\n\nSee `medeleg.IAM` for details. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_9a21601d", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hedeleg.yaml", + "section": "hedeleg.IAF", + "text": "CSR hedeleg field IAF (bits=1) *Instruction Access Fault*\n\nControls delegation of Instruction Access Fault exceptions to VS-mode.\n\nSee `medeleg.IAF` for details. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_b50045f7", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hedeleg.yaml", + "section": "hedeleg.II", + "text": "CSR hedeleg field II (bits=2) *Illegal Instruction*\n\nControls delegation of Illegal Instruction exceptions to VS-mode.\n\nSee `medeleg.II` for details. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_444d77d3", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hedeleg.yaml", + "section": "hedeleg.B", + "text": "CSR hedeleg field B (bits=3) *Breakpoint*\n\nControls delegation of Breakpoint exceptions to VS-mode.\n\nSee `medeleg.B` for details. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_f0148c21", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hedeleg.yaml", + "section": "hedeleg.LAM", + "text": "CSR hedeleg field LAM (bits=4) *Load Address Misaligned*\n\nControls delegation of Load Address Misaligned exceptions to VS-mode.\n\nSee `medeleg.LAM` for details. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ebaf1f57", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hedeleg.yaml", + "section": "hedeleg.LAF", + "text": "CSR hedeleg field LAF (bits=5) *Load Access Fault*\n\nControls delegation of Load Access Fault exceptions to VS-mode.\n\nSee `medeleg.LAF` for details. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_947d214f", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hedeleg.yaml", + "section": "hedeleg.SAM", + "text": "CSR hedeleg field SAM (bits=6) *Store/AMO Address Misaligned*\n\nControls delegation of Store/AMO Address Misaligned exceptions to VS-mode.\n\nSee `medeleg.SAM` for details. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ac9a8126", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hedeleg.yaml", + "section": "hedeleg.SAF", + "text": "CSR hedeleg field SAF (bits=7) *Store/AMO Access Fault*\n\nControls delegation of Store/AMO Access Fault exceptions to VS-mode.\n\nSee `medeleg.SAF` for details. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_10961092", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hedeleg.yaml", + "section": "hedeleg.EU", + "text": "CSR hedeleg field EU (bits=8) *Environment Call from VU-mode*\n\nControls delegation of Environment Call from VU-mode exceptions to VS-mode.\n\nSee `medeleg.EU` for details. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d78cfd7c", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hedeleg.yaml", + "section": "hedeleg.ES", + "text": "CSR hedeleg field ES (bits=9) *Environment Call from HS-mode*\n\nEnvironment Call from HS-mode exceptions _cannot be delegated to VS-mode_,\nso this field is read-only 0.\n\nSee `medeleg.ES` for details. type: RO", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_0656758b", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hedeleg.yaml", + "section": "hedeleg.EVS", + "text": "CSR hedeleg field EVS (bits=10) *Environment Call from VS-mode*\n\nEnvironment Call from VS-mode exceptions _cannot be delegated to VS-mode_,\nso this field is read-only 0.\n\nSee `medeleg.EVS` for details. type: RO", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_99a75d50", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hedeleg.yaml", + "section": "hedeleg.EM", + "text": "CSR hedeleg field EM (bits=11) *Environment Call from M-mode*\n\nEnvironment Call from M-mode exceptions _cannot be delegated to VS-mode_,\nso this field is read-only 0.\n\nSee `medeleg.EM` for details. type: RO", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ec95c0ce", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hedeleg.yaml", + "section": "hedeleg.IPF", + "text": "CSR hedeleg field IPF (bits=12) *Instruction Page Fault*\n\nControls delegation of Instruction Page Fault exceptions to VS-mode.\n\nSee `medeleg.IPF` for details. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_3e5ac55a", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hedeleg.yaml", + "section": "hedeleg.LPF", + "text": "CSR hedeleg field LPF (bits=13) *Load Page Fault*\n\nControls delegation of Load Page Fault exceptions to VS-mode.\n\nSee `medeleg.LPF` for details. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_488384ce", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hedeleg.yaml", + "section": "hedeleg.SPF", + "text": "CSR hedeleg field SPF (bits=15) *Store/AMO Page Fault*\n\nControls delegation of Store/AMO Page Fault exceptions to VS-mode.\n\nSee `medeleg.SPF` for details. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_962617fa", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hedeleg.yaml", + "section": "hedeleg.IGPF", + "text": "CSR hedeleg field IGPF (bits=20) *Instruction Guest Page Fault*\n\nInstruction Guest Page Fault exceptions _cannot be delegated to VS-mode_,\nso this field is read-only 0.\n\nSee `medeleg.IGPF` for details. type: RO", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_625e3ab6", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hedeleg.yaml", + "section": "hedeleg.LGPF", + "text": "CSR hedeleg field LGPF (bits=21) *Load Guest Page Fault*\n\nLoad Guest Page Fault exceptions _cannot be delegated to VS-mode_,\nso this field is read-only 0.\n\nSee `medeleg.LGPF` for details. type: RO", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d918cc49", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hedeleg.yaml", + "section": "hedeleg.VI", + "text": "CSR hedeleg field VI (bits=22) *Virtual Instruction*\n\nVirtual Instruction exceptions _cannot be delegated to VS-mode_,\nso this field is read-only 0.\n\nSee `medeleg.VI` for details. type: RO", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_20ed9210", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hedeleg.yaml", + "section": "hedeleg.SGPF", + "text": "CSR hedeleg field SGPF (bits=23) *Store/AMO Guest Page Fault*\n\nStore/AMO Guest Page Fault exceptions _cannot be delegated to VS-mode_,\nso this field is read-only 0.\n\nSee `medeleg.SGPF` for details. type: RO", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_3160f3f2", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hedelegh.yaml", + "section": "hedelegh", + "text": "CSR hedelegh (address=1554, priv=S): Controls exception delegation from HS-mode to VS-mode.\n\nAlias of upper bits of `hedeleg`[63:32].", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_71dac743", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hstateen0.yaml", + "section": "hstateen0", + "text": "CSR hstateen0 (address=1548, priv=S): Each bit of a `stateen` CSR controls less-privileged access to an extension’s state,\nfor an extension that was not deemed \"worthy\" of a full XS field in `sstatus` like the\nFS and VS fields for the F and V extensions.\n\nThe number of registers provided at each level is four because it is believed that", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_a894856a", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hstateen0.yaml", + "section": "hstateen0.SE0", + "text": "CSR hstateen0 field SE0 (bits=63) The SE0 bit in `hstateen0` controls access to the `sstateen0` CSR. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_bd11a2fd", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hstateen0.yaml", + "section": "hstateen0.ENVCFG", + "text": "CSR hstateen0 field ENVCFG (bits=62) The ENVCFG bit in `hstateen0` controls access to the `senvcfg` CSRs. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_de5db4fd", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hstateen0.yaml", + "section": "hstateen0.CSRIND", + "text": "CSR hstateen0 field CSRIND (bits=60) The CSRIND bit in `hstateen0` controls access to the `siselect` and the\n`sireg*`, (really `vsiselect` and `vsireg*`) CSRs provided by the Sscsrind\nextensions. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d193c611", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hstateen0.yaml", + "section": "hstateen0.AIA", + "text": "CSR hstateen0 field AIA (bits=59) The AIA bit in `hstateen0` controls access to all state introduced by\nthe Ssaia extension and is not controlled by either the CSRIND or the\nIMSIC bits of `hstateen0`. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_3d96d878", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hstateen0.yaml", + "section": "hstateen0.IMSIC", + "text": "CSR hstateen0 field IMSIC (bits=58) The IMSIC bit in `hstateen0` controls access to the guest IMSIC state,\nincluding CSRs `stopei` (really `vstopei`), provided by the Ssaia extension.\n\nSetting the IMSIC bit in `hstateen0` to zero prevents a virtual machine\nfrom accessing the hart’s IMSIC the same as setting `hstatus.`VGEIN = 0. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_772e0063", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hstateen0.yaml", + "section": "hstateen0.CONTEXT", + "text": "CSR hstateen0 field CONTEXT (bits=57) The CONTEXT bit in `hstateen0` controls access to the `scontext` CSR provided\nby the Sdtrig extension. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_498cee0d", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hstateen0.yaml", + "section": "hstateen0.CTR", + "text": "CSR hstateen0 field CTR (bits=54) If the H extension is implemented and `mstateen0.CTR=1`, the `hstateen0.CTR` bit controls access to\nsupervisor CTR state when V=1. This state includes `sctrctl` (really `vsctrctl`), `sctrstatus`, and `sireg*`\n(really `vsireg*`) when `siselect` (really `vsiselect`) is in 0x200..0x2FF. `hstateen0.CTR` type: RW", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d69e6e4b", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hstateen0.yaml", + "section": "hstateen0.JVT", + "text": "CSR hstateen0 field JVT (bits=2) The JVT bit controls access to the `jvt` CSR provided by the Zcmt extension. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_964f82ee", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hstateen0.yaml", + "section": "hstateen0.FCSR", + "text": "CSR hstateen0 field FCSR (bits=1) The FCSR bit controls access to `fcsr` for the case when floating-point instructions\noperate on `x` registers instead of `f` registers as specified by the Zfinx and related\nextensions (Zdinx, etc.). Whenever `misa.F` = 1, FCSR bit of `mstateen0` is read-only\nzero (and hence read-only zero in `hstate type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_93c5e5e9", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hstateen0.yaml", + "section": "hstateen0.C", + "text": "CSR hstateen0 field C (bits=rv32=? rv64=?) The C bit controls access to any and all custom state. The C bit of these registers is\nnot custom state itself; it is a standard field of a standard CSR, either `mstateen0`,\n`hstateen0`, or `sstateen0`. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ff420c03", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hstateen0h.yaml", + "section": "hstateen0h", + "text": "CSR hstateen0h (address=1564, priv=S): For RV64 harts, the Smstateen/Ssstateen extension adds four new 64-bit CSRs at machine level: `mstateen0` (Machine State Enable 0),\n`mstateen1`, `mstateen2`, and `mstateen3`. If supervisor mode is implemented, another four CSRs are defined at\nsupervisor level: `sstateen0`, `sstateen1`, `sstateen2`, ", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_7bd75a1e", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hstateen0h.yaml", + "section": "hstateen0h.SE0", + "text": "CSR hstateen0h field SE0 (bits=31) The SE0 bit in `hstateen0h` controls access to the `sstateen0` CSR. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_84939eea", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hstateen0h.yaml", + "section": "hstateen0h.ENVCFG", + "text": "CSR hstateen0h field ENVCFG (bits=30) The ENVCFG bit in `hstateen0h` controls access to the `senvcfg` CSRs. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_db146a08", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hstateen0h.yaml", + "section": "hstateen0h.CSRIND", + "text": "CSR hstateen0h field CSRIND (bits=28) The CSRIND bit in `hstateen0h` controls access to the `siselect` and the\n`sireg*`, (really `vsiselect` and `vsireg*`) CSRs provided by the Sscsrind\nextensions. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_dc2736df", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hstateen0h.yaml", + "section": "hstateen0h.AIA", + "text": "CSR hstateen0h field AIA (bits=27) The AIA bit in `hstateen0h` controls access to all state introduced by\nthe Ssaia extension and is not controlled by either the CSRIND or the\nIMSIC bits of `hstateen0`. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_86084add", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hstateen0h.yaml", + "section": "hstateen0h.IMSIC", + "text": "CSR hstateen0h field IMSIC (bits=26) The IMSIC bit in `hstateen0h` controls access to the guest IMSIC state,\nincluding CSRs `stopei` (really `vstopei`), provided by the Ssaia extension.\n\nSetting the IMSIC bit in `hstateen0h` to zero prevents a virtual machine\nfrom accessing the hart’s IMSIC the same as setting `hstatus.`VGEIN = 0. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_bab70854", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hstateen0h.yaml", + "section": "hstateen0h.CONTEXT", + "text": "CSR hstateen0h field CONTEXT (bits=25) The CONTEXT bit in `hstateen0h` controls access to the `scontext` CSR provided\nby the Sdtrig extension. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_05590611", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hstateen0h.yaml", + "section": "hstateen0h.CTR", + "text": "CSR hstateen0h field CTR (bits=22) If the H extension is implemented and `mstateen0.CTR=1`, the `hstateen0.CTR` bit controls access to\nsupervisor CTR state when V=1. This state includes `sctrctl` (really `vsctrctl`), `sctrstatus`, and `sireg*`\n(really `vsireg*`) when `siselect` (really `vsiselect`) is in 0x200..0x2FF. `hstateen0.CTR` type: RW", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d288cfa1", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hstateen1.yaml", + "section": "hstateen1", + "text": "CSR hstateen1 (address=1549, priv=S): Each bit of a `stateen` CSR controls less-privileged access to an extension’s state,\nfor an extension that was not deemed \"worthy\" of a full XS field in `sstatus` like the\nFS and VS fields for the F and V extensions.\n\nThe number of registers provided at each level is four because it is believed that", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_cec70b14", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hstateen1.yaml", + "section": "hstateen1.SE0", + "text": "CSR hstateen1 field SE0 (bits=63) The SE0 bit in `hstateen1` controls access to the `sstateen1` CSR. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_b76dca49", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hstateen1h.yaml", + "section": "hstateen1h", + "text": "CSR hstateen1h (address=1565, priv=S): For RV64 harts, the Smstateen/Ssstateen extension adds four new 64-bit CSRs at machine level: `mstateen0` (Machine State Enable 0),\n`mstateen1`, `mstateen2`, and `mstateen3`. If supervisor mode is implemented, another four CSRs are defined at\nsupervisor level: `sstateen0`, `sstateen1`, `sstateen2`, ", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_60fcebdc", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hstateen1h.yaml", + "section": "hstateen1h.SE0", + "text": "CSR hstateen1h field SE0 (bits=31) The SE0 bit in `hstateen1h` controls access to the `sstateen1` CSR. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_f5caa2d9", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hstateen2.yaml", + "section": "hstateen2", + "text": "CSR hstateen2 (address=1550, priv=S): Each bit of a `stateen` CSR controls less-privileged access to an extension’s state,\nfor an extension that was not deemed \"worthy\" of a full XS field in `sstatus` like the\nFS and VS fields for the F and V extensions.\n\nThe number of registers provided at each level is four because it is believed that", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_40368502", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hstateen2.yaml", + "section": "hstateen2.SE0", + "text": "CSR hstateen2 field SE0 (bits=63) The SE0 bit in `hstateen2` controls access to the `sstateen2` CSR. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_14af4267", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hstateen2h.yaml", + "section": "hstateen2h", + "text": "CSR hstateen2h (address=1566, priv=S): For RV64 harts, the Smstateen/Ssstateen extension adds four new 64-bit CSRs at machine level: `mstateen0` (Machine State Enable 0),\n`mstateen1`, `mstateen2`, and `mstateen3`. If supervisor mode is implemented, another four CSRs are defined at\nsupervisor level: `sstateen0`, `sstateen1`, `sstateen2`, ", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_bc8aedd9", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hstateen2h.yaml", + "section": "hstateen2h.SE0", + "text": "CSR hstateen2h field SE0 (bits=31) The SE0 bit in `hstateen2h` controls access to the `sstateen2` CSR. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_6addbab0", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hstateen3.yaml", + "section": "hstateen3", + "text": "CSR hstateen3 (address=1551, priv=S): Each bit of a `stateen` CSR controls less-privileged access to an extension’s state,\nfor an extension that was not deemed \"worthy\" of a full XS field in `sstatus` like the\nFS and VS fields for the F and V extensions.\n\nThe number of registers provided at each level is four because it is believed that", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_9374e0b3", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hstateen3.yaml", + "section": "hstateen3.SE0", + "text": "CSR hstateen3 field SE0 (bits=63) The SE0 bit in `hstateen3` controls access to the `sstateen3` CSR. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_c0ca0334", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hstateen3h.yaml", + "section": "hstateen3h", + "text": "CSR hstateen3h (address=1567, priv=S): For RV64 harts, the Smstateen/Ssstateen extension adds four new 64-bit CSRs at machine level: `mstateen0` (Machine State Enable 0),\n`mstateen1`, `mstateen2`, and `mstateen3`. If supervisor mode is implemented, another four CSRs are defined at\nsupervisor level: `sstateen0`, `sstateen1`, `sstateen2`, ", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_f0a1bf7a", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hstateen3h.yaml", + "section": "hstateen3h.SE0", + "text": "CSR hstateen3h field SE0 (bits=31) The SE0 bit in `hstateen3h` controls access to the `sstateen3` CSR. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_0d0ebf7e", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hstatus.yaml", + "section": "hstatus", + "text": "CSR hstatus (address=1536, priv=S): The hstatus register tracks and controls a VS-mode guest.\n\nUnlike fields in `sstatus`, which are all aliases of fields `mstatus`,\nbits in `hstatus` are independent bits and do not have aliases.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "H" + }, + { + "chunk_id": "chunk_5b2b8977", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hstatus.yaml", + "section": "hstatus.VSXL", + "text": "CSR hstatus field VSXL (bits=33-32) Determines the effective XLEN in VS-mode. Valid values are:\n\n[separator=\"!\"]\n!===\n! Value ! VSXLEN\n\n! 0 ! 32\n! 1 ! 64\n!===\n Because the implementation only supports a single VSXLEN == 32, this field is read-only-0.\n Because the implementation only supports a single VSXLEN == 64, this field i type: if ($array_size(VSXLEN) == 1) { reset: if ($array_size(VSXLEN) == 1 && VSXLEN[0] == 32) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_50ac4129", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hstatus.yaml", + "section": "hstatus.VTSR", + "text": "CSR hstatus field VTSR (bits=22) When `hstatus.VTSR` is set, executing the `sret` instruction in VS-mode\nraises a `Virtual Instruction` exception.\n\nWhen `hstatus.VTSR` is clear, an `sret` instruction in VS-mode returns control\nto the mode stored in `vsstatus.SPP`. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_bd4b0d42", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hstatus.yaml", + "section": "hstatus.VTW", + "text": "CSR hstatus field VTW (bits=21) When `hstatus.VTW` is set, a `wfi` instruction executed in VS-mode raises\na `Virtual Instruction` exception after waiting an implementation-defined\namount of time (which can be 0).\n\nWhen both `hstatus.VTW` and `mstatus.TW` are clear, a `wfi` instruction\nexecutes in VS-mode without a timeout period.\n type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_0ed7a6fe", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hstatus.yaml", + "section": "hstatus.VTVM", + "text": "CSR hstatus field VTVM (bits=20) When set, a 'Virtual Instruction` trap occurs when executing an `sfence.vma`, `sinval.vma`,\nor an explicit CSR access of the `satp` (really `vsatp`) register when in VS-mode.\n\nWhen clear, the instructions execute as normal in VS-mode.\n\nNotably, `hstatus.VTVM` does *not* cause `hfence.vvma`, `sfence. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_07749281", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hstatus.yaml", + "section": "hstatus.VGEIN", + "text": "CSR hstatus field VGEIN (bits=17-12) Selects the guest external interrupt source for VS-level external interrupts.\n\nWhen `hstatus.VGEIN` == 0, no external interrupt source is selected.\n\nWhen `hstatus.VGEIN` != 0, it selects which bit of `hgeip` is currently active in VS-mode. type: # if NUM_EXTERNAL_GUEST_INTERRUPTS+1 is 63 (because indexing in `hgeip` starts at 1), reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_dd180582", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hstatus.yaml", + "section": "hstatus.HU", + "text": "CSR hstatus field HU (bits=9) When set, the hypervisor load/store instructions (`hlv`, `hlvx`, and `hsv`) can be\nexecuted in U-mode.\n\nWhen clear, the hypervisor load/store instructions cause an `Illegal Instruction` trap. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_76ba8adc", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hstatus.yaml", + "section": "hstatus.SPVP", + "text": "CSR hstatus field SPVP (bits=8) Written by hardware:\n\n* When taking a trap into HS-mode from VS-mode or VU-mode, `hstatus.SPVP` is written with the nominal privilege mode\n\nNotably, unlike its analog `mstatus.SPP`, `hstatus.SPVP` is *not* cleared when returning from a trap.\n\nCan also be written by software without immediate side-ef type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_c4759474", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hstatus.yaml", + "section": "hstatus.SPV", + "text": "CSR hstatus field SPV (bits=7) Written by hardware:\n\n* On a trap into HS-mode, hardware writes 1 when the prior mode was VS-mode or VU-mode, and 0 otherwise.\n\nCan also be written by software without immediate side-effect.\n\nAffects execution by:\n\n* When an `sret` instruction in executed in HS-mode or M-mode,\n control returns to V type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_fcd54250", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hstatus.yaml", + "section": "hstatus.GVA", + "text": "CSR hstatus field GVA (bits=6) Written by hardware whenever a trap is taken into HS-mode:\n\n* Writes 1 when a trap causes a guest virtual address to be written into `stval` (`Breakpoint`, `* Address Misaligned`, `* Access Fault`, `* Page Fault`, or `* Guest-Page Fault`).\n* Writes 0 otherwise\n\nDoes not affect execution. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_4e851233", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/hstatus.yaml", + "section": "hstatus.VSBE", + "text": "CSR hstatus field VSBE (bits=5) Controls the endianness of data VS-mode (0 = little, 1 = big).\nInstructions are always little endian, regardless of the data setting.\n Since the CPU does not support big endian in VS-mode, this is hardwired to 0.\n Since the CPU does not support little endian in VS-mode, this is hardwired to 1. type: if (VS_MODE_ENDIANNESS == \"dynamic\") { reset: if (VS_MODE_ENDIANNESS == \"little\") {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_19ce3e6a", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/instret.yaml", + "section": "instret", + "text": "CSR instret (address=3074, priv=U): Alias for M-mode CSR `minstret`.\n\nPrivilege mode access is controlled with `mcounteren.IR`, `scounteren.IR`, and `hcounteren.IR` as follows:\n\n[%autowidth,cols=\"1,1,1,1,1,1,1\",separator=\"!\"]\n!===\n.2+h![.rotate]#`mcounteren.IR`# .2+h! [.rotate]#`scounteren.IR`# .2+h! [.rotate]#`hcounteren.IR`#\n4+^.>h!", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Zicntr" + }, + { + "chunk_id": "chunk_545e469a", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/instret.yaml", + "section": "instret.COUNT", + "text": "CSR instret field COUNT (bits=63-0) Alias of `minstret.COUNT`. type: RO-H", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_62089dd6", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/instreth.yaml", + "section": "instreth", + "text": "CSR instreth (address=3202, priv=U): Alias for high bits of M-mode CSR `minstret`[63:32].\n\nPrivilege mode access is controlled with `mcounteren.IR`, `scounteren.IR`, and `hcounteren.IR` as follows:\n\n[%autowidth,cols=\"1,1,1,1,1,1,1\",separator=\"!\"]\n!===\n.2+h![.rotate]#`mcounteren.IR`# .2+h! [.rotate]#`scounteren.IR`# .2+h! [.rotate]#`hco", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_01fab47e", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/instreth.yaml", + "section": "instreth.COUNT", + "text": "CSR instreth field COUNT (bits=31-0) Alias of `minstret.COUNT`[63:32]. type: RO-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_6346436b", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/jvt.yaml", + "section": "jvt", + "text": "CSR jvt (address=23, priv=U): The `jvt` register is an XLEN-bit WARL read/write register that holds the jump table configuration,\nconsisting of the jump table base address (BASE) and the jump table mode (MODE).\n\n`jvt` CSR adds architectural state to the system software context (such as an OS process), therefore\nmust be saved/res", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Zcmt" + }, + { + "chunk_id": "chunk_2a5eb4b9", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/jvt.yaml", + "section": "jvt.BASE", + "text": "CSR jvt field BASE (bits=rv32=31-6 rv64=63-6) The value in the BASE field must always be aligned on a 64-byte boundary. Note that the CSR contains only\nbits XLEN-1 through 6 of the address base. When computing jump-table accesses, the lower six bits of base\nare filled with zeroes to obtain an XLEN-bit jump-table base address `jvt.base` that is type: if (JVT_READ_ONLY) { reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_b8587301", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/jvt.yaml", + "section": "jvt.MODE", + "text": "CSR jvt field MODE (bits=5-0) `jvt.mode` is a WARL field, so can only be programmed to modes which are implemented. Therefore the\ndiscovery mechanism is to attempt to program different modes and read back the values to see which\nare available. Jump table mode must be implemented. type: if (JVT_READ_ONLY) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_adf3d42f", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/marchid.yaml", + "section": "marchid", + "text": "CSR marchid (address=3858, priv=M): The `marchid` CSR is an MXLEN-bit read-only register encoding the base\nmicroarchitecture of the hart. This register must be readable in any\nimplementation, but a value of 0 can be returned to indicate the field\nis not implemented. The combination of `mvendorid` and `marchid` should\nuniquely identify", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Sm" + }, + { + "chunk_id": "chunk_b82f134f", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/marchid.yaml", + "section": "marchid.Architecture", + "text": "CSR marchid field Architecture (bits=rv32=31-0 rv64=63-0) Vendor-specific microarchitecture ID. type: RO reset: return ARCH_ID_VALUE;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_f92f41c9", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mcause.yaml", + "section": "mcause", + "text": "CSR mcause (address=834, priv=M): Reports the cause of the latest exception.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Sm" + }, + { + "chunk_id": "chunk_3deafb67", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mcause.yaml", + "section": "mcause.INT", + "text": "CSR mcause field INT (bits=rv32=31 rv64=63) Written by hardware when a trap is taken into M-mode.\n\nWhen set, the last exception was caused by an asynchronous Interrupt.\n\n`mcause.INT` is writable.\n\n[when,\"TRAP_ON_ILLEGAL_WLRL == true\"]\nIf `mcause` is written with an undefined cause (combination of `mcause.INT` and `mcause.CODE`), an `Illegal I type: RW-RH", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_fb179971", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mcause.yaml", + "section": "mcause.CODE", + "text": "CSR mcause field CODE (bits=rv32=30-0 rv64=62-0) Written by hardware when a trap is taken into M-mode.\n\nHolds the interrupt or exception code for the last taken trap.\n\n`mcause.CODE` is writable.\n\n[when,\"TRAP_ON_ILLEGAL_WLRL == true\"]\nIf `mcause` is written with an undefined cause (combination of `mcause.INT` and `mcause.CODE`), an `Illegal Instruc type: RW-RH", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_9888bd63", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mconfigptr.yaml", + "section": "mconfigptr", + "text": "CSR mconfigptr (address=3861, priv=M): Holds a physical address pointer to the unified discovery data structure in Memory.\n\nThe `mconfigptr` holds the physical\naddress of a configuration data structure. Software can traverse this\ndata structure to discover information about the harts, the platform,\nand their configuration.\n\nThe pointer a", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Sm" + }, + { + "chunk_id": "chunk_de4887a9", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mconfigptr.yaml", + "section": "mconfigptr.ADDRESS", + "text": "CSR mconfigptr field ADDRESS (bits=rv32=31-0 rv64=63-0) Pointer to physical address of the Unified Discovery configuration data structure. type: RO reset: return CONFIG_PTR_ADDRESS;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_f91e5478", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mcontext.yaml", + "section": "mcontext", + "text": "CSR mcontext (address=1960, priv=M): This register must be implemented if `hcontext` is implemented, and is optional otherwise.\nIt is only accessible in M-mode and Debug mode.\n\n`hcontext` is primarily useful to set triggers on hypervisor systems that only fire when a\ngiven VM is executing. It is also useful in systems where M-Mode impl", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Sdtrig" + }, + { + "chunk_id": "chunk_9f710f68", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mcontext.yaml", + "section": "mcontext.HCONTEXT", + "text": "CSR mcontext field HCONTEXT (bits=13-0) M-Mode or HS-Mode (using `hcontext`) software can write a\ncontext number to this register, which can be used to set\ntriggers that only fire in that specific context.\n\nAn implementation may tie any number of upper bits in\nthis field to 0. If the H extension is not implemented, it’s\nrecommended to imp type: RW", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_676732c5", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mcycle.yaml", + "section": "mcycle", + "text": "CSR mcycle (address=2816, priv=M): Counts the number of clock cycles executed by the processor core on which\nthe hart is running.\nThe counter has 64-bit precision on all RV32 and RV64 harts.\n\nThe `mcycle` CSR may be shared between harts on the same core, in which case\nwrites to `mcycle` will be visible to those harts. The platform sh", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Sm" + }, + { + "chunk_id": "chunk_fefe0a77", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mcycle.yaml", + "section": "mcycle.COUNT", + "text": "CSR mcycle field COUNT (bits=63-0) Cycle counter.\n\n<%- if ext?(:Zicntr) -%>\nAliased as `cycle.CYCLE`.\n<%- end -%>\n\nIncrements every cycle unless:\n\n * `mcountinhibit.CY` <%- if ext?(:Smcdeleg) -%>or its alias `scountinhibit.CY`<%- end -%> is set\n <%- if ext?(:Smcntrpmf) -%>\n * `mcyclecfg.MINH` is set and the current privilege level type: RW-RH reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_de9a53d3", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mcycleh.yaml", + "section": "mcycleh", + "text": "CSR mcycleh (address=2944, priv=M): High-half alias of `mcycle`.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_14648a80", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mcycleh.yaml", + "section": "mcycleh.COUNT", + "text": "CSR mcycleh field COUNT (bits=31-0) Alias of upper half of `mcycle.COUNT`. type: RW-RH reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_dd682f65", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/medeleg.yaml", + "section": "medeleg", + "text": "CSR medeleg (address=770, priv=M): Controls exception delegation from M-mode to (H)S-mode\n<%- if ext?(:H) -%>\nor, in conjunction with `hedeleg`, to VS-mode\n<%- end -%>\n.\n\nAn exception cause is delegated to (H)S-mode when all of the following hold:\n\n* The corresponding field in `medeleg` is set.\n* The current privilege level is not M-", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "S" + }, + { + "chunk_id": "chunk_30d26c68", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/medeleg.yaml", + "section": "medeleg.IAM", + "text": "CSR medeleg field IAM (bits=rv32=? rv64=?) *Instruction Address Misaligned*\n\nDelegates Instruction Address Misaligned exceptions to (H)S-mode.\n<%- if ext?(:H) -%>\nInstruction Address Misaligned exceptions may be further delegated to VS-mode if `hedeleg.IAM` is also set.\n<%- end -%>\n\nExceptions are never taken into a less-privileged mode, reg type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_8acd5e58", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/medeleg.yaml", + "section": "medeleg.IAF", + "text": "CSR medeleg field IAF (bits=1) *Instruction Access Fault*\n\nDelegates Instruction Access Fault exceptions to (H)S-mode.\n<%- if ext?(:H) -%>\nInstruction Access Fault exceptions may be further delegated to VS-mode if `hedeleg.IAM` is also set.\n<%- end -%>\n\nExceptions are never taken into a less-privileged mode, regardless of `medele type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_caf916ee", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/medeleg.yaml", + "section": "medeleg.II", + "text": "CSR medeleg field II (bits=2) *Illegal Instruction*\n\nDelegates Illegal Instruction exceptions to (H)S-mode.\n<%- if ext?(:H) -%>\nIllegal Instruction exceptions may be further delegated to VS-mode if `hedeleg.II` is also set.\n<%- end -%>\n\nExceptions are never taken into a less-privileged mode, regardless of `medeleg`.\n\nThe handlin type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_425a9b83", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/medeleg.yaml", + "section": "medeleg.B", + "text": "CSR medeleg field B (bits=3) *Breakpoint*\n\nDelegates Breakpoint exceptions to (H)S-mode.\n<%- if ext?(:H) -%>\nBreakpoint exceptions may be further delegated to VS-mode if `hedeleg.B` is also set.\n<%- end -%>\n\nExceptions are never taken into a less-privileged mode, regardless of `medeleg`.\n\nThe handling mode is determined as foll type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_aab3d20f", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/medeleg.yaml", + "section": "medeleg.LAM", + "text": "CSR medeleg field LAM (bits=4) *Load Address Misaligned*\n\nDelegates Load Address Misaligned exceptions to (H)S-mode.\n<%- if ext?(:H) -%>\nLoad Address Misaligned exceptions may be further delegated to VS-mode if `hedeleg.LAM` is also set.\n<%- end -%>\n\nExceptions are never taken into a less-privileged mode, regardless of `medeleg`. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_053a5682", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/medeleg.yaml", + "section": "medeleg.LAF", + "text": "CSR medeleg field LAF (bits=5) *Load Access Fault*\n\nDelegates Load Access Fault exceptions to (H)S-mode.\n<%- if ext?(:H) -%>\nLoad Access Fault exceptions may be further delegated to VS-mode if `hedeleg.LAF` is also set.\n<%- end -%>\n\nExceptions are never taken into a less-privileged mode, regardless of `medeleg`.\n\nThe handling mod type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_e8ae7428", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/medeleg.yaml", + "section": "medeleg.SAM", + "text": "CSR medeleg field SAM (bits=6) *Store/AMO Address Misaligned*\n\nDelegates Store/AMO Address Misaligned exceptions to (H)S-mode.\n<%- if ext?(:H) -%>\nStore/AMO Address Misaligned exceptions may be further delegated to VS-mode if `hedeleg.SAM` is also set.\n<%- end -%>\n\nExceptions are never taken into a less-privileged mode, regardles type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_2a98b34e", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/medeleg.yaml", + "section": "medeleg.SAF", + "text": "CSR medeleg field SAF (bits=7) *Store/AMO Access Fault*\n\nDelegates Store/AMO Access Fault exceptions to (H)S-mode.\n<%- if ext?(:H) -%>\nStore/AMO Access Fault exceptions may be further delegated to VS-mode if `hedeleg.SAM` is also set.\n<%- end -%>\n\nExceptions are never taken into a less-privileged mode, regardless of `medeleg`.\n\nT type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_3d7d155d", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/medeleg.yaml", + "section": "medeleg.EU", + "text": "CSR medeleg field EU (bits=8) *Environment Call from U-Mode*\n\nDelegates Environment Call from U-mode exceptions to (H)S-mode.\n<%- if ext?(:H) -%>\nEnvironment Call from U-mode exceptions may be further delegated to VS-mode if `hedeleg.EU` is also set.\n<%- end -%>\n\nExceptions are never taken into a less-privileged mode, regardless type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_43556ba7", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/medeleg.yaml", + "section": "medeleg.ES", + "text": "CSR medeleg field ES (bits=9) *Environment Call from S-Mode*\n\nDelegates Environment Call from S-mode exceptions to (H)S-mode.\n<%- if ext?(:H) -%>\nEnvironment Call from S-mode exceptions _cannot be delegated to VS-mode_.\n<%- end -%>\n\nExceptions are never taken into a less-privileged mode, regardless of `medeleg`.\n\nThe handling mo type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_783cfa1c", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/medeleg.yaml", + "section": "medeleg.EVS", + "text": "CSR medeleg field EVS (bits=10) *Environment Call from VS-Mode*\n\nDelegates Environment Call from VS-mode exceptions to (H)S-mode.\n<%- if ext?(:H) -%>\nEnvironment Call from S-mode exceptions _cannot be delegated to VS-mode_.\n<%- end -%>\n\nExceptions are never taken into a less-privileged mode, regardless of `medeleg`.\n\nThe handling type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_202ca332", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/medeleg.yaml", + "section": "medeleg.EM", + "text": "CSR medeleg field EM (bits=11) *Environment Call from M-Mode*\n\nAn Environment Call from M-mode cannot be delegated, so this is a read-only field.\n\nAll Environment Call from M-mode exceptions are taken by M-mode. type: RO", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_cbea60a1", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/medeleg.yaml", + "section": "medeleg.IPF", + "text": "CSR medeleg field IPF (bits=12) *Instruction Page Fault*\n\nDelegates Instruction Page Fault exceptions to (H)S-mode.\n<%- if ext?(:H) -%>\nInstruction Page Fault exceptions may be further delegated to VS-mode if `hedeleg.IPF` is also set.\n<%- end -%>\n\nExceptions are never taken into a less-privileged mode, regardless of `medeleg`.\n\nT type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_8ce8ab21", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/medeleg.yaml", + "section": "medeleg.LPF", + "text": "CSR medeleg field LPF (bits=13) *Load Page Fault*\n\nDelegates Load Page Fault exceptions to (H)S-mode.\n<%- if ext?(:H) -%>\nLoad Page Fault exceptions may be further delegated to VS-mode if `hedeleg.LPF` is also set.\n<%- end -%>\n\nExceptions are never taken into a less-privileged mode, regardless of `medeleg`.\n\nThe handling mode is d type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_b2590c6f", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/medeleg.yaml", + "section": "medeleg.SPF", + "text": "CSR medeleg field SPF (bits=15) *Store/AMO Page Fault*\n\nDelegates Store/AMO Page Fault exceptions to (H)S-mode.\n<%- if ext?(:H) -%>\nStore/AMO Page Fault exceptions may be further delegated to VS-mode if `hedeleg.SPF` is also set.\n<%- end -%>\n\nExceptions are never taken into a less-privileged mode, regardless of `medeleg`.\n\nThe han type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_6bffd5fe", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/medeleg.yaml", + "section": "medeleg.IGPF", + "text": "CSR medeleg field IGPF (bits=20) *Instruction Guest Page Fault*\n\nDelegates Instruction Guest Page Fault exceptions to (H)S-mode.\n<%- if ext?(:H) -%>\nInstruction Guest Page Fault exceptions _cannot be delegated to VS-mode_.\n<%- end -%>\n\nExceptions are never taken into a less-privileged mode, regardless of `medeleg`.\n\nThe handling mo type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_db7f777e", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/medeleg.yaml", + "section": "medeleg.LGPF", + "text": "CSR medeleg field LGPF (bits=21) *Load Guest Page Fault*\n\nDelegates Load Guest Page Fault exceptions to (H)S-mode.\n<%- if ext?(:H) -%>\nLoad Guest Page Fault exceptions _cannot be delegated to VS-mode_.\n<%- end -%>\n\nExceptions are never taken into a less-privileged mode, regardless of `medeleg`.\n\nThe handling mode is determined as f type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_8f2092ba", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/medeleg.yaml", + "section": "medeleg.VI", + "text": "CSR medeleg field VI (bits=22) *Virtual Instruction*\n\nDelegates Virtual Instruction exceptions to (H)S-mode.\n<%- if ext?(:H) -%>\nVirtual Instruction exceptions _cannot be delegated to VS-mode_.\n<%- end -%>\n\nExceptions are never taken into a less-privileged mode, regardless of `medeleg`.\n\nThe handling mode is determined as follows type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_a774ec6c", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/medeleg.yaml", + "section": "medeleg.SGPF", + "text": "CSR medeleg field SGPF (bits=23) *Store/AMO Guest Page Fault*\n\nDelegates Store/AMO Guest Page Fault exceptions to (H)S-mode.\n<%- if ext?(:H) -%>\nStore/AMO Guest Page Fault exceptions _cannot be delegated to VS-mode_.\n<%- end -%>\n\nExceptions are never taken into a less-privileged mode, regardless of `medeleg`.\n\nThe handling mode is type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ad7c3c69", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/medelegh.yaml", + "section": "medelegh", + "text": "CSR medelegh (address=786, priv=M): Alias of the upper 32 bits of `medeleg`.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_354472a1", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/menvcfg.yaml", + "section": "menvcfg", + "text": "CSR menvcfg (address=778, priv=M): Contains fields that control certain characteristics of the execution environment\nfor modes less privileged than M-mode.\n\nThe `menvcfg` CSR controls\ncertain characteristics of the execution environment for modes less\nprivileged than M.\n\nIf bit FIOM (Fence of I/O implies Memory) is set to one in `men", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d5e84b10", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/menvcfg.yaml", + "section": "menvcfg.STCE", + "text": "CSR menvcfg field STCE (bits=63) *STimecmp Enable*\n\nWhen set, `stimecmp` is operational.\n\nWhen clear, `stimecmp` access in a mode other than M-mode raises an `Illegal Instruction` trap.\nS-mode timer interrupts will not be generated when clear, and `mip` and `sip` revert to their prior behavior without `Sstc`. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_8540fbf9", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/menvcfg.yaml", + "section": "menvcfg.PBMTE", + "text": "CSR menvcfg field PBMTE (bits=62) *Page Based Memory Type Enable*\n\nThe PBMTE bit controls whether the Svpbmt extension is available for use in S-mode<% if ext?(:H) %>and G-stage<% end %>\naddress translation (i.e., for page tables pointed to by satp<% if ext?(:H) %> or hgatp<% end %>). When PBMTE=1, Svpbmt is\navailable for S-mode <% type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_b2dc113e", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/menvcfg.yaml", + "section": "menvcfg.ADUE", + "text": "CSR menvcfg field ADUE (bits=61) If the Svadu extension is implemented, the ADUE bit controls whether hardware updating of\nPTE A/D bits is enabled for S-mode and G-stage address translations. When ADUE=1, hardware\nupdating of PTE A/D bits is enabled during S-mode address translation, and the\nimplementation behaves as though the Sva type: return (implemented?(ExtensionName::Svadu)) ? CsrFieldType::RW : CsrFieldType::RO; reset: return (implemented?(ExtensionName::Svadu)) ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_a7455280", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/menvcfg.yaml", + "section": "menvcfg.CBZE", + "text": "CSR menvcfg field CBZE (bits=7) *Cache Block Zero instruction Enable*\n\nEnables the execution of the cache block zero instruction, `CBO.ZERO`,\n<% if ext?(:S) %>\nin S-mode\n<% elsif ext?(:U) %>\nin U-mode\n<% end %>.\n\n * `0`: The instruction raises an illegal instruction or virtual instruction exception\n * `1`: The instruction is exe type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d44f7874", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/menvcfg.yaml", + "section": "menvcfg.CBCFE", + "text": "CSR menvcfg field CBCFE (bits=6) *Cache Block Clean and Flush instruction Enable*\n\nEnables the execution of the cache block clean instruction, `CBO.CLEAN`, and the\ncache block flush instruction, `CBO.FLUSH`,\n<% if ext?(:S) %>\nin S-mode\n<% elsif ext?(:U) %>\nin U-mode\n<% end %>.\n\n * `0`: The instruction raises an illegal instruction type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_03688218", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/menvcfg.yaml", + "section": "menvcfg.CBIE", + "text": "CSR menvcfg field CBIE (bits=5-4) *Cache Block Invalidate instruction Enable*\n\nEnables the execution of the cache block invalidate instruction, `CBO.INVAL`,\n<% if ext?(:S) %>\nin S-mode\n<% elsif ext?(:U) %>\nin U-mode\n<% end %>.\n\n * `00`: The instruction raises an illegal instruction or virtual instruction exception\n * `01`: The ins type: RW-R reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_23d0b7c4", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/menvcfg.yaml", + "section": "menvcfg.SSE", + "text": "CSR menvcfg field SSE (bits=3) *Shadow Stack Enable*\n\nWhen the SSE field is set to 1 the Zicfiss extension isactivated in S-mode. When SSE\nfield is 0, the following rules apply to privilege modes that are less than M:\n\n - 32-bit Zicfiss instructions will revert to their behavior as defined by Zimop.\n\n - 16-bit Zicfiss instructi type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_2666c11b", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/menvcfg.yaml", + "section": "menvcfg.FIOM", + "text": "CSR menvcfg field FIOM (bits=rv32=? rv64=?) *Fence of I/O implies Memory*\n\nWhen `menvcfg.FIOM` is set,\nFENCE instructions ordering I/O regions also implicitly order memory regions when executed\nin any mode less privileged than M-mode.\n\n[separator=\"!\",%autowidth,float=\"center\",align=\"center\",cols=\"^,<\",options=\"header\"]\n!===\n!Instruction bit ! type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_658b27a9", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/menvcfgh.yaml", + "section": "menvcfgh", + "text": "CSR menvcfgh (address=794, priv=M): Contains bits to enable/disable extensions", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_fdf5eae5", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/menvcfgh.yaml", + "section": "menvcfgh.STCE", + "text": "CSR menvcfgh field STCE (bits=31) *STimecmp Enable*\n\nAlias of `menvcfg.STCE` type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_f8507b15", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/menvcfgh.yaml", + "section": "menvcfgh.PBMTE", + "text": "CSR menvcfgh field PBMTE (bits=30) *Page Based Memory Type Enable*\n\nAlias of `menvcfg.PBMTE` type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_3dd64f73", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/menvcfgh.yaml", + "section": "menvcfgh.ADUE", + "text": "CSR menvcfgh field ADUE (bits=29) Alias of `menvcfg.ADUE` type: return (implemented?(ExtensionName::Svadu)) ? CsrFieldType::RW : CsrFieldType::RO; reset: return (implemented?(ExtensionName::Svadu)) ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_4a442bc0", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mepc.yaml", + "section": "mepc", + "text": "CSR mepc (address=833, priv=M): Written with the PC of an instruction on an exception or interrupt taken in M-mode.\n\nAlso controls where the hart jumps on an exception return from M-mode.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Sm" + }, + { + "chunk_id": "chunk_725ae7b0", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mepc.yaml", + "section": "mepc.PC", + "text": "CSR mepc field PC (bits=rv32=31-0 rv64=63-0) When a trap is taken into M-mode, `mepc.PC` is written with the virtual address of the\ninstruction that was interrupted or that encountered the exception.\nOtherwise, `mepc.PC` is never written by the implementation, though it may be explicitly written\nby software.\n\nOn an exception return from M-mode type: RW-RH", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_7c56300e", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mhartid.yaml", + "section": "mhartid", + "text": "CSR mhartid (address=3860, priv=M): Reports the unique hart-specific ID in the system.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Sm" + }, + { + "chunk_id": "chunk_47401030", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mhartid.yaml", + "section": "mhartid.ID", + "text": "CSR mhartid field ID (bits=rv32=31-0 rv64=63-0) hart-specific ID. type: RO reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_0ce03dd0", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mideleg.yaml", + "section": "mideleg", + "text": "CSR mideleg (address=771, priv=M): Controls exception delegation from M-mode to HS/S-mode\n\nBy default, all traps at any privilege level are handled in machine\nmode, though a machine-mode handler can redirect traps back to the\nappropriate level with the `MRET` instruction. To increase performance,\nimplementations can provide individua", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_09865295", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mideleg.yaml", + "section": "mideleg.SSI", + "text": "CSR mideleg field SSI (bits=1) *Supervisor Software Interrupt delegation*\n\nWhen 1, Supervisor Software interrupts are delegated to HS/S-mode. type: RW", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_b968ac92", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mideleg.yaml", + "section": "mideleg.VSSI", + "text": "CSR mideleg field VSSI (bits=2) *Virtual Supervisor Software Interrupt delegation*\n\nWhen 1, Virtual Supervisor Software interrupts are delegated to HS-mode.\n\nVirtual Supervisor Software Interrupts are always delegated to HS-mode, so this field is read-only one. type: RO reset: 1", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_159f773f", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mideleg.yaml", + "section": "mideleg.MSI", + "text": "CSR mideleg field MSI (bits=3) *Machine Software interrupt delegation*\n\nSince M-mode interrupts cannot be delegated, this field is read-only zero. type: RO", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_bfa4ca62", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mideleg.yaml", + "section": "mideleg.STI", + "text": "CSR mideleg field STI (bits=5) *Supervisor Timer interrupt delegation*\n\nWhen 1, Supervisor Timer interrupts are delegated to HS/S-mode. type: RW", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_53f64ec4", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mideleg.yaml", + "section": "mideleg.VSTI", + "text": "CSR mideleg field VSTI (bits=6) *Virtual Supervisor Timer interrupt delegation*\n\nWhen 1, Virtual Supervisor Timer interrupts are delegated to HS-mode.\n\nVirtual Supervisor Time Interrupts are always delegated to HS-mode, so this field is read-only one. type: RO reset: 1", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_3200dea9", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mideleg.yaml", + "section": "mideleg.MTI", + "text": "CSR mideleg field MTI (bits=7) *Machine Timer interrupt delegation*\n\nSince M-mode interrupts cannot be delegated, this field is read-only zero. type: RO", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_b62da452", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mideleg.yaml", + "section": "mideleg.SEI", + "text": "CSR mideleg field SEI (bits=9) *Supervisor External interrupt delegation*\n\nWhen 1, Supervisor External interrupts are delegated to HS/S-mode. type: RW", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_0cf8b2d3", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mideleg.yaml", + "section": "mideleg.VSEI", + "text": "CSR mideleg field VSEI (bits=10) *Virtual Supervisor External interrupt delegation*\n\nVirtual Supervisor External Interrupts are always delegated to HS-mode, so this field is read-only one. type: RO reset: 1", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_78dd5b69", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mideleg.yaml", + "section": "mideleg.MEI", + "text": "CSR mideleg field MEI (bits=11) *Machine External interrupt delegation*\n\nSince M-mode interrupts cannot be delegated, this field is read-only zero. type: RO", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_3f651a4f", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mideleg.yaml", + "section": "mideleg.SGEI", + "text": "CSR mideleg field SGEI (bits=12) *Supervisor Guest External Interrupt delegation*\n\nSupervisor Guest External interrupts are always delegated to HS-mode, so this field is read-only one. type: RO reset: 1", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_a7d288bc", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mideleg.yaml", + "section": "mideleg.LCOFI", + "text": "CSR mideleg field LCOFI (bits=13) *Local Counter Overflow Interrupt delegation*\n\nWhen 1, local counter overflow interrupts are delegated to (H)S-mode. type: RW", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_df4857d6", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mie.yaml", + "section": "mie", + "text": "CSR mie (address=772, priv=M): mip.yaml#/description", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Sm" + }, + { + "chunk_id": "chunk_10b25ce2", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mie.yaml", + "section": "mie.SSIE", + "text": "CSR mie field SSIE (bits=1) Enables Supervisor Software Interrupts. type: RW", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_3a4f6706", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mie.yaml", + "section": "mie.VSSIE", + "text": "CSR mie field VSSIE (bits=2) Enables Virtual Supervisor Software Interrupts. type: RW", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_5460ed95", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mie.yaml", + "section": "mie.MSIE", + "text": "CSR mie field MSIE (bits=3) Enables Machine Software Interrupts. type: RW", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_7769b0b7", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mie.yaml", + "section": "mie.STIE", + "text": "CSR mie field STIE (bits=5) Enables Supervisor Timer Interrupts. type: RW", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ffee4a23", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mie.yaml", + "section": "mie.VSTIE", + "text": "CSR mie field VSTIE (bits=6) Enables Virtual Supervisor Timer Interrupts. type: RW", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_8baa24de", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mie.yaml", + "section": "mie.MTIE", + "text": "CSR mie field MTIE (bits=7) Enables Machine Timer Interrupts. type: RW", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_6b34e9cc", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mie.yaml", + "section": "mie.SEIE", + "text": "CSR mie field SEIE (bits=9) Enables Supervisor External Interrupts. type: RW", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_37314e91", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mie.yaml", + "section": "mie.VSEIE", + "text": "CSR mie field VSEIE (bits=10) Enables Virtual Supervisor External Interrupts. type: RW", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_e125066f", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mie.yaml", + "section": "mie.MEIE", + "text": "CSR mie field MEIE (bits=11) Enables Machine External Interrupts. type: RW", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_f86dd433", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mie.yaml", + "section": "mie.SGEIE", + "text": "CSR mie field SGEIE (bits=12) Enables Supervisor Guest External Interrupts type: RW", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_8e6ae7f3", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mie.yaml", + "section": "mie.LCOFIE", + "text": "CSR mie field LCOFIE (bits=13) Enables Local Counter Overflow Interrupts. type: RW", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_89208424", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mimpid.yaml", + "section": "mimpid", + "text": "CSR mimpid (address=3859, priv=M): Reports the vendor-specific implementation ID.\n\nThe `mimpid` CSR provides a unique encoding of the version of the\nprocessor implementation. This register must be readable in any\nimplementation, but a value of 0 can be returned to indicate that the\nfield is not implemented. The Implementation value s", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Sm" + }, + { + "chunk_id": "chunk_c148c448", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mimpid.yaml", + "section": "mimpid.Implementation", + "text": "CSR mimpid field Implementation (bits=rv32=31-0 rv64=63-0) Vendor-specific implementation ID. type: RO reset: return IMP_ID_VALUE;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_0f7a1bc8", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/minstret.yaml", + "section": "minstret", + "text": "CSR minstret (address=2818, priv=M): Counts the number of instructions retired by this hart from some arbitrary start point in the past.\n\n[NOTE]\nInstructions that cause synchronous exceptions, including `ecall` and `ebreak`, are not\nconsidered to retire and hence do not increment the `minstret` CSR.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Sm" + }, + { + "chunk_id": "chunk_0af111d1", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/minstret.yaml", + "section": "minstret.COUNT", + "text": "CSR minstret field COUNT (bits=63-0) Instructions retired counter.\n\n<%- if ext?(:Zicntr) -%>\nAliased as `instret.COUNT`.\n<%- end -%>\n\nIncrements every time an instruction retires unless:\n\n * `mcountinhibit.IR` <%- if ext?(:Smcdeleg) -%>or its alias `scountinhibit.IR`<%- end -%> is set\n <%- if ext?(:Smcntrpmf) -%>\n * `minstretcfg.MIN type: RW-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_b629f0fb", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/minstreth.yaml", + "section": "minstreth", + "text": "CSR minstreth (address=2946, priv=M): Upper half of 64-bit instructions retired counters.\n\nSee `minstret` for details.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_6cbeab4c", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/minstreth.yaml", + "section": "minstreth.COUNT", + "text": "CSR minstreth field COUNT (bits=31-0) *Instructions retired counter*\n\nUpper half of `minstret`. type: RW-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_26cd3e61", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mip.yaml", + "section": "mip", + "text": "CSR mip (address=836, priv=M): The `mie` and `mip` CSRs are MXLEN-bit read/write registers used when\nthe CLINT or PLIC interrupt controllers are present.\nNote that the CLINT refers to an interrupt controller\nused by some RISC-V implementations but isn't a ratified\nRISC-V International standard.\n\nThe `mip` CSR contains information", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Sm" + }, + { + "chunk_id": "chunk_02f719a1", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mip.yaml", + "section": "mip.SSIP", + "text": "CSR mip field SSIP (bits=1) *Supervisor Software Interrupt Pending*\n\nReports the current pending state of an (H)S-mode software interrupt, which is generated by writing to this field.\n\n<%- if ext?(:Smaia) -%>\nWhen using AIA/IMSIC, IPIs are expected to be delivered as external interrupts\nand SSIP is not backed by any hardware u type: RW", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_8233bc92", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mip.yaml", + "section": "mip.VSSIP", + "text": "CSR mip field VSSIP (bits=2) *Virtual Supervisor Software Interrupt Pending*\n\nReports the current pending state of a VS-mode software interrupt, which is generated by writing to this field.\n\n<%- if ext?(:Smaia) -%>\nWhen using AIA/IMSIC, IPIs are expected to be delivered as external interrupts and VSSIP is not backed by any hard type: RW", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_b5ffc25c", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mip.yaml", + "section": "mip.MSIP", + "text": "CSR mip field MSIP (bits=3) *Machine Software Interrupt Pending*\n\nUnused field.\n\n<%- if ext?(:Smaia) -%>\nWith AIA/IMSIC, IPIs are delivered as external interrupts. As a result, this bit is\nunused and hardwired to 0.\n<%- end -%> type: RO", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_9a16bba9", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mip.yaml", + "section": "mip.STIP", + "text": "CSR mip field STIP (bits=5) *Supervisor Timer Interrupt Pending*\n\nReports the current pending state of an (H)S-mode timer interrupt\n<%- if ext?(:Sstc) -%>\n, which is normally controlled by the `stimecmp` CSR.\n<%- else -%>\n, which is generated by software by writing to `mip.STIP`<% if ext?(:Smaia) %>or its alias `mvip.STIP`<% e type: RW", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_6a109228", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mip.yaml", + "section": "mip.VSTIP", + "text": "CSR mip field VSTIP (bits=6) *Virtual Supervisor Timer Interrupt Pending*\n\nReports the current pending state of a VS-mode timer interrupt\n<%- if ext?(:Sstc) -%>\n, which is normally controlled by the `vstimecmp` CSR, but can also be injected by the hypervisor through `hvip.VSTIP`.\n<%- else -%>\n, which is generated by M-mode and/ type: RO-H", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_6adfca25", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mip.yaml", + "section": "mip.MTIP", + "text": "CSR mip field MTIP (bits=7) *Machine Timer Interrupt Pending*\n\nReports the current pending state of an M-mode timer interrupt.\n\nBit is controlled by the timer device (using `mtimecmp`), and is not writable. type: RO-H", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_4278b008", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mip.yaml", + "section": "mip.SEIP", + "text": "CSR mip field SEIP (bits=9) *Supervisor External Interrupt Pending*\n\nReports the current pending state of an (H)S-mode external interrupt.\n\nThis field has two parts: a software-writable shadow value and a wire from the interrupt controller.\nThe value presented to software in the bit on a CSR read is the logical OR of the softw type: RW-H", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_eff92728", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mip.yaml", + "section": "mip.VSEIP", + "text": "CSR mip field VSEIP (bits=10) *Virtual Supervisor External Interrupt Pending*\n\nReports the current pending state of a VS-mode external interrupt.\n\nThis field is the logical OR of `hvip.VSEIP` and the wire coming from the interrupt controller.\n\nThe field is not writable by software\n<%- if ext?(:Smaia) -%>\n(_i.e._, unlike the beha type: RO-H", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_a6199315", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mip.yaml", + "section": "mip.MEIP", + "text": "CSR mip field MEIP (bits=11) *Machine External Interrupt Pending*\n\nReports the current pending state of an M-mode external interrupt.\n\nMEIP is controlled by the external interrupt controller <% if ext?(:Smaia) %>(AIA) <% end %>.\nIt is not writable by software. type: RO-H", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_a9677592", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mip.yaml", + "section": "mip.SGEIP", + "text": "CSR mip field SGEIP (bits=12) *Supervisor Guest External Interrupt Pending*\n\nRead-only summary of any pending Supervisor Guest External Interrupt Pending, i.e.:\nthe logical-OR reduction of the `hgeip` register.\n\n_Alias_:\n\n* `hip.SGEIP` type: RO-H", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_249a9316", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mip.yaml", + "section": "mip.LCOFIP", + "text": "CSR mip field LCOFIP (bits=13) *Local Counter Overflow Interrupt pending*\n\n<%- if ext?(:H) -%>\nWhen `hideleg.LCOFI` is set,\n`vsip.LCOFIP`, `sip.LCOFIP`, and `mip.LCOFIP` are all aliases.\n<%- end -%>\n\nWhen a counter overflow interrupt occurs, a hidden sticky bit is set.\n\nSoftware writes 0 to `mip.LCOFIP` to clear the pending inter type: RW-H", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_a93e1034", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/misa.yaml", + "section": "misa", + "text": "CSR misa (address=769, priv=M): Reports the XLEN and \"major\" extensions supported by the ISA.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Sm" + }, + { + "chunk_id": "chunk_6eadbce9", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/misa.yaml", + "section": "misa.MXL", + "text": "CSR misa field MXL (bits=rv32=31-30 rv64=63-62) XLEN in M-mode. type: RO reset: return (MXLEN == 32) ? 2'b01 : 2'b10;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_52c7315c", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/misa.yaml", + "section": "misa.A", + "text": "CSR misa field A (bits=rv32=? rv64=?) Indicates support for the `A` (atomic) extension.\n\n[when,\"MUTABLE_MISA_A == true\"]\nWriting 0 to this field will cause all atomic instructions to raise an `IllegalInstruction` exception. type: return (implemented?(ExtensionName::A) && MUTABLE_MISA_A) ? CsrFieldType::RW : CsrFieldType::RO; reset: return implemented?(ExtensionName::A) ? 1 : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_1068550d", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/misa.yaml", + "section": "misa.B", + "text": "CSR misa field B (bits=1) Indicates support for the `B` (bitmanip) extension.\n\n[when,\"MUTABLE_MISA_B == true\"]\nWriting 0 to this field will cause all bitmanip instructions to raise an `IllegalInstruction` exception. type: return (implemented?(ExtensionName::B) && MUTABLE_MISA_B) ? CsrFieldType::RW : CsrFieldType::RO; reset: return implemented?(ExtensionName::B) ? 1 : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_845e4d55", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/misa.yaml", + "section": "misa.C", + "text": "CSR misa field C (bits=2) Indicates support for the `C` (compressed) extension.\n\n[when,\"MUTABLE_MISA_C == true\"]\nWriting 0 to this field will cause all compressed instructions to raise an `IllegalInstruction` exception.\nAdditionally, IALIGN becomes 32. type: return (implemented?(ExtensionName::C) && MUTABLE_MISA_C) ? CsrFieldType::RW : CsrFieldType::RO; reset: return implemented?(ExtensionName::C) ? 1 : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_bea3e314", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/misa.yaml", + "section": "misa.D", + "text": "CSR misa field D (bits=3) Indicates support for the `D` (double precision float) extension.\n\n[when,\"MUTABLE_MISA_D == true\"]\n--\nWriting 0 to this field will cause all double-precision floating point instructions to raise an `IllegalInstruction` exception.\n\nAdditionally, the upper 32-bits of the f registers will read as zero. type: return (implemented?(ExtensionName::D) && MUTABLE_MISA_D) ? CsrFieldType::RW : CsrFieldType::RO; reset: return implemented?(ExtensionName::D) ? 1 : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_10bdf2c4", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/misa.yaml", + "section": "misa.F", + "text": "CSR misa field F (bits=5) Indicates support for the `F` (single precision float) extension.\n\n[when,\"MUTABLE_MISA_F == true\"]\n--\nWriting 0 to this field will cause all floating point (single and double precision) instructions to raise an `IllegalInstruction` exception.\n\nWriting 0 to this field with `misa.D` set will result in type: return (implemented?(ExtensionName::F) && MUTABLE_MISA_F) ? CsrFieldType::RW : CsrFieldType::RO; reset: return implemented?(ExtensionName::F) ? 1 : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_2f16b5fa", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/misa.yaml", + "section": "misa.G", + "text": "CSR misa field G (bits=6) Indicates support for all of the following extensions: `I`, `A`, `M`, `F`, `D`. type: if ((implemented?(ExtensionName::A) && MUTABLE_MISA_A) || reset: return (", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_a1fc7e4e", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/misa.yaml", + "section": "misa.H", + "text": "CSR misa field H (bits=7) Indicates support for the `H` (hypervisor) extension.\n\n[when,\"MUTABLE_MISA_H == true\"]\nWriting 0 to this field will cause all attempts to enter VS- or VU- mode, execute a hypervisor instruction, or access a hypervisor CSR to raise an `IllegalInstruction` fault. type: return (implemented?(ExtensionName::H) && MUTABLE_MISA_H) ? CsrFieldType::RW : CsrFieldType::RO; reset: return implemented?(ExtensionName::H) ? 1 : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_06bf3ba7", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/misa.yaml", + "section": "misa.I", + "text": "CSR misa field I (bits=8) Indicates support for the `I` (base) extension. type: RO reset: 1", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_77aaa00e", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/misa.yaml", + "section": "misa.M", + "text": "CSR misa field M (bits=12) Indicates support for the `M` (integer multiply/divide) extension.\n\n[when,\"MUTABLE_MISA_M == true\"]\nWriting 0 to this field will cause all attempts to execute an integer multiply or divide instruction to raise an `IllegalInstruction` exception. type: return (implemented?(ExtensionName::M) && MUTABLE_MISA_M) ? CsrFieldType::RW : CsrFieldType::RO; reset: return implemented?(ExtensionName::M) ? 1 : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_001d6310", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/misa.yaml", + "section": "misa.Q", + "text": "CSR misa field Q (bits=16) Indicates support for the `Q` (quad precision float) extension.\n\n[when,\"MUTABLE_MISA_Q == true\"]\n--\nWriting 0 to this field will cause all quad-precision floating point instructions to raise an `IllegalInstruction` exception.\n-- type: return MUTABLE_MISA_Q ? CsrFieldType::RW : CsrFieldType::RO; reset: 1", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_9c572809", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/misa.yaml", + "section": "misa.S", + "text": "CSR misa field S (bits=18) Indicates support for the `S` (supervisor mode) extension.\n\n[when,\"MUTABLE_MISA_S == true\"]\nWriting 0 to this field will cause all attempts to enter S-mode or access S-mode state to raise an exception. type: return (implemented?(ExtensionName::S) && MUTABLE_MISA_S) ? CsrFieldType::RW : CsrFieldType::RO; reset: return implemented?(ExtensionName::S) ? 1 : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_dfaba129", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/misa.yaml", + "section": "misa.U", + "text": "CSR misa field U (bits=20) Indicates support for the `U` (user mode) extension.\n\n[when,\"MUTABLE_MISA_U == true\"]\nWriting 0 to this field will cause all attempts to enter U-mode to raise an exception. type: return (implemented?(ExtensionName::U) && MUTABLE_MISA_U) ? CsrFieldType::RW : CsrFieldType::RO; reset: return implemented?(ExtensionName::U) ? 1 : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_a7796efb", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/misa.yaml", + "section": "misa.V", + "text": "CSR misa field V (bits=21) Indicates support for the `V` (vector) extension.\n\n[when,\"MUTABLE_MISA_V == true\"]\nWriting 0 to this field will cause all attempts to execute a vector instruction to raise an `IllegalInstruction` trap. type: return (implemented?(ExtensionName::V) && MUTABLE_MISA_V) ? CsrFieldType::RW : CsrFieldType::RO; reset: return implemented?(ExtensionName::V) ? 1 : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_c4aa8cbc", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mscontext.yaml", + "section": "mscontext", + "text": "CSR mscontext (address=1962, priv=S): This optional register is an alias for `scontext`. It is only\naccessible in S/HS-mode, M-mode and Debug Mode. It is included\nfor backward compatibility with version 0.13.\n\nThe encoding of this CSR does not conform to the CSR Address\nMapping Convention in the Privileged Spec. It is expected that\nnew ", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_4fbee3f3", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mscontext.yaml", + "section": "mscontext.DATA", + "text": "CSR mscontext field DATA (bits=rv32=31-0 rv64=63-0) Supervisor mode software can write a context number to\nthis register, which can be used to set triggers that only fire\nin that specific context.\n\nAn implementation may tie any number of high bits in\nthis field to 0. It’s recommended to implement 16 bits on\nRV32 and 32 bits on RV64. type: RW", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_92647e0f", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mscratch.yaml", + "section": "mscratch", + "text": "CSR mscratch (address=832, priv=M): Scratch register for software use. Bits are not interpreted by hardware.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Sm" + }, + { + "chunk_id": "chunk_1a52d45f", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mscratch.yaml", + "section": "mscratch.SCRATCH", + "text": "CSR mscratch field SCRATCH (bits=rv32=31-0 rv64=63-0) Scratch value type: RW", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_0616446b", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mseccfg.yaml", + "section": "mseccfg", + "text": "CSR mseccfg (address=1863, priv=M): Machine Security Configuration", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ae482ba9", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mseccfgh.yaml", + "section": "mseccfgh", + "text": "CSR mseccfgh (address=1879, priv=M): Machine Security Configuration", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_10325265", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstateen0.yaml", + "section": "mstateen0", + "text": "CSR mstateen0 (address=780, priv=M): Each bit of a `stateen` CSR controls less-privileged access to an extension’s state,\nor an extension that was not deemed \"worthy\" of a full XS field in `sstatus` like the\nFS and VS fields for the F and V extensions.\n\nThe number of registers provided at each level is four because it is believed that\n", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Smstateen" + }, + { + "chunk_id": "chunk_4d33c2da", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstateen0.yaml", + "section": "mstateen0.SE0", + "text": "CSR mstateen0 field SE0 (bits=63) The SE0 bit in `mstateen0` controls access to the `hstateen0`, `hstateen0h`, and the `sstateen0` CSRs. type: RW", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_cc69bf79", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstateen0.yaml", + "section": "mstateen0.ENVCFG", + "text": "CSR mstateen0 field ENVCFG (bits=62) The ENVCFG bit in `mstateen0` controls access to the `henvcfg`, `henvcfgh`, and the `senvcfg` CSRs. type: RW", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_6b677087", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstateen0.yaml", + "section": "mstateen0.CSRIND", + "text": "CSR mstateen0 field CSRIND (bits=60) The CSRIND bit in `mstateen0` controls access to the `siselect`, `sireg*`, `vsiselect`, and the `vsireg*`\nCSRs provided by the Sscsrind extensions. type: RW", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_8374e629", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstateen0.yaml", + "section": "mstateen0.AIA", + "text": "CSR mstateen0 field AIA (bits=59) The AIA bit in `mstateen0` controls access to all state introduced by the Ssaia extension and is not\ncontrolled by either the CSRIND or the IMSIC bits. type: RW", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_2223ac05", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstateen0.yaml", + "section": "mstateen0.IMSIC", + "text": "CSR mstateen0 field IMSIC (bits=58) The IMSIC bit in `mstateen0` controls access to the IMSIC state, including CSRs `stopei` and `vstopei`,\nprovided by the Ssaia extension. type: RW", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_87cbe14e", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstateen0.yaml", + "section": "mstateen0.CONTEXT", + "text": "CSR mstateen0 field CONTEXT (bits=57) The CONTEXT bit in `mstateen0` controls access to the `scontext` and `hcontext` CSRs provided by the\nSdtrig extension. type: RW", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_9dfba7c2", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstateen0.yaml", + "section": "mstateen0.P1P13", + "text": "CSR mstateen0 field P1P13 (bits=56) The P1P13 bit in `mstateen0` controls access to the `hedelegh` introduced by Privileged Specification\nVersion 1.13. type: RW", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_b51df260", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstateen0.yaml", + "section": "mstateen0.SRMCFG", + "text": "CSR mstateen0 field SRMCFG (bits=55) The SRMCFG bit in `mstateen0` controls access to the `srmcfg`` CSR introduced by the Ssqosid Chapter 18\nextension. type: RW", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_3d28466f", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstateen0.yaml", + "section": "mstateen0.CTR", + "text": "CSR mstateen0 field CTR (bits=54) When Smstateen is implemented, the `mstateen0.CTR` bit controls access to CTR register state from\nprivilege modes less privileged than M-mode. type: RW", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_b4b8034c", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstateen0.yaml", + "section": "mstateen0.JVT", + "text": "CSR mstateen0 field JVT (bits=2) The JVT bit controls access to the `jvt` CSR provided by the Zcmt extension. type: RW", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_adc2c97b", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstateen0.yaml", + "section": "mstateen0.FCSR", + "text": "CSR mstateen0 field FCSR (bits=1) The FCSR bit controls access to `fcsr` for the case when floating-point instructions\noperate on `x` registers instead of `f` registers as specified by the Zfinx and related\nextensions (Zdinx, etc.). Whenever `misa.F` = 1, FCSR bit of `mstateen0` is read-only\nzero (and hence read-only zero in `hstate type: RW", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_9ab96f52", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstateen0.yaml", + "section": "mstateen0.C", + "text": "CSR mstateen0 field C (bits=rv32=? rv64=?) The C bit controls access to any and all custom state. The C bit of these registers is\nnot custom state itself; it is a standard field of a standard CSR, either `mstateen0`,\n`hstateen0`, or `sstateen0`. type: RW", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_19ef0492", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstateen0h.yaml", + "section": "mstateen0h", + "text": "CSR mstateen0h (address=796, priv=M): For RV64 harts, the Smstateen extension adds four new 64-bit CSRs at machine level: `mstateen0` (Machine State\nEnable 0), `mstateen1`, `mstateen2`, and `mstateen3`. For RV32, the registers listed above are 32-bit, and for the\nmachine-level CSRs there is a corresponding set of high-half CSRs for the ", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_b19566f5", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstateen0h.yaml", + "section": "mstateen0h.SE0", + "text": "CSR mstateen0h field SE0 (bits=31) The SE0 bit in `mstateen0h` controls access to the `hstateen0`, `hstateen0h`, and the `sstateen0` CSRs. type: RW", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_73da1e96", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstateen0h.yaml", + "section": "mstateen0h.ENVCFG", + "text": "CSR mstateen0h field ENVCFG (bits=30) The ENVCFG bit in `mstateen0h` controls access to the `henvcfg`, `henvcfgh`, and the `senvcfg` CSRs. type: RW", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_3b17d05a", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstateen0h.yaml", + "section": "mstateen0h.CSRIND", + "text": "CSR mstateen0h field CSRIND (bits=28) The CSRIND bit in `mstateen0h` controls access to the `siselect`, `sireg*`, `vsiselect`, and the `vsireg*`\nCSRs provided by the Sscsrind extensions. type: RW", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_35f404d0", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstateen0h.yaml", + "section": "mstateen0h.AIA", + "text": "CSR mstateen0h field AIA (bits=27) The AIA bit in `mstateen0h` controls access to all state introduced by the Ssaia extension and is not\ncontrolled by either the CSRIND or the IMSIC bits. type: RW", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_6ff84ab3", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstateen0h.yaml", + "section": "mstateen0h.IMSIC", + "text": "CSR mstateen0h field IMSIC (bits=26) The IMSIC bit in `mstateen0h` controls access to the IMSIC state, including CSRs `stopei` and `vstopei`,\nprovided by the Ssaia extension. type: RW", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_4848bbce", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstateen0h.yaml", + "section": "mstateen0h.CONTEXT", + "text": "CSR mstateen0h field CONTEXT (bits=25) The CONTEXT bit in `mstateen0h` controls access to the `scontext` and `hcontext` CSRs provided by the\nSdtrig extension. type: RW", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_a3aa0ab2", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstateen0h.yaml", + "section": "mstateen0h.P1P13", + "text": "CSR mstateen0h field P1P13 (bits=24) The P1P13 bit in `mstateen0h` controls access to the `hedelegh` introduced by Privileged Specification\nVersion 1.13. type: RW", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_e9b7df67", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstateen0h.yaml", + "section": "mstateen0h.SRMCFG", + "text": "CSR mstateen0h field SRMCFG (bits=23) The SRMCFG bit in `mstateen0h` controls access to the `srmcfg`` CSR introduced by the Ssqosid Chapter 18\nextension. type: RW", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ef1815a1", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstateen0h.yaml", + "section": "mstateen0h.CTR", + "text": "CSR mstateen0h field CTR (bits=22) When Smstateen is implemented, the `mstateen0.CTR` bit controls access to CTR register state from\nprivilege modes less privileged than M-mode. type: RW", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_81d062eb", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstateen1.yaml", + "section": "mstateen1", + "text": "CSR mstateen1 (address=781, priv=M): Each bit of a `stateen` CSR controls less-privileged access to an extension’s state,\nor an extension that was not deemed \"worthy\" of a full XS field in `sstatus` like the\nFS and VS fields for the F and V extensions.\n\nThe number of registers provided at each level is four because it is believed that\n", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Smstateen" + }, + { + "chunk_id": "chunk_efa4d23a", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstateen1.yaml", + "section": "mstateen1.SE0", + "text": "CSR mstateen1 field SE0 (bits=63) The SE0 bit in `mstateen1` controls access to the `hstateen1`, `hstateen1h`, and the `sstateen1` CSRs. type: RW", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ad91d0d2", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstateen1h.yaml", + "section": "mstateen1h", + "text": "CSR mstateen1h (address=797, priv=M): For RV64 harts, the Smstateen extension adds four new 64-bit CSRs at machine level: `mstateen0` (Machine State\nEnable 0), `mstateen1`, `mstateen2`, and `mstateen3`. For RV32, the registers listed above are 32-bit, and for the\nmachine-level CSRs there is a corresponding set of high-half CSRs for the ", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_b9494d0c", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstateen1h.yaml", + "section": "mstateen1h.SE0", + "text": "CSR mstateen1h field SE0 (bits=31) The SE0 bit in `mstateen1h` controls access to the `hstateen1`, `hstateen1h`, and the `sstateen1` CSRs. type: RW", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_503d1d71", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstateen2.yaml", + "section": "mstateen2", + "text": "CSR mstateen2 (address=782, priv=M): Each bit of a `stateen` CSR controls less-privileged access to an extension’s state,\nor an extension that was not deemed \"worthy\" of a full XS field in `sstatus` like the\nFS and VS fields for the F and V extensions.\n\nThe number of registers provided at each level is four because it is believed that\n", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Smstateen" + }, + { + "chunk_id": "chunk_81992392", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstateen2.yaml", + "section": "mstateen2.SE0", + "text": "CSR mstateen2 field SE0 (bits=63) The SE0 bit in `mstateen2` controls access to the `hstateen2`, `hstateen2h`, and the `sstateen2` CSRs. type: RW", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_3b06a8c1", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstateen2h.yaml", + "section": "mstateen2h", + "text": "CSR mstateen2h (address=798, priv=M): For RV64 harts, the Smstateen extension adds four new 64-bit CSRs at machine level: `mstateen0` (Machine State\nEnable 0), `mstateen1`, `mstateen2`, and `mstateen3`. For RV32, the registers listed above are 32-bit, and for the\nmachine-level CSRs there is a corresponding set of high-half CSRs for the ", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_2a605bc5", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstateen2h.yaml", + "section": "mstateen2h.SE0", + "text": "CSR mstateen2h field SE0 (bits=31) The SE0 bit in `mstateen2h` controls access to the `hstateen2`, `hstateen2h`, and the `sstateen2` CSRs. type: RW", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ecc3fd61", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstateen3.yaml", + "section": "mstateen3", + "text": "CSR mstateen3 (address=783, priv=M): Each bit of a `stateen` CSR controls less-privileged access to an extension’s state,\nor an extension that was not deemed \"worthy\" of a full XS field in `sstatus` like the\nFS and VS fields for the F and V extensions.\n\nThe number of registers provided at each level is four because it is believed that\n", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Smstateen" + }, + { + "chunk_id": "chunk_7a03194e", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstateen3.yaml", + "section": "mstateen3.SE0", + "text": "CSR mstateen3 field SE0 (bits=63) The SE0 bit in `mstateen3` controls access to the `hstateen3`, `hstateen3h`, and the `sstateen3` CSRs. type: RW", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ac79ac33", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstateen3h.yaml", + "section": "mstateen3h", + "text": "CSR mstateen3h (address=799, priv=M): For RV64 harts, the Smstateen extension adds four new 64-bit CSRs at machine level: `mstateen0` (Machine State\nEnable 0), `mstateen1`, `mstateen2`, and `mstateen3`. For RV32, the registers listed above are 32-bit, and for the\nmachine-level CSRs there is a corresponding set of high-half CSRs for the ", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_0d14e6b9", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstateen3h.yaml", + "section": "mstateen3h.SE0", + "text": "CSR mstateen3h field SE0 (bits=31) The SE0 bit in `mstateen3h` controls access to the `hstateen3`, `hstateen3h`, and the `sstateen3` CSRs. type: RW", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_5be967b2", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstatus.yaml", + "section": "mstatus", + "text": "CSR mstatus (address=768, priv=M): The mstatus register tracks and controls the hart's current operating state.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Sm" + }, + { + "chunk_id": "chunk_475539a4", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstatus.yaml", + "section": "mstatus.SD", + "text": "CSR mstatus field SD (bits=rv32=31 rv64=63) Read-only bit that summarizes whether either the FS, XS, or VS\nfields signal the presence of some dirty state. type: # this is read-only if FS and VS are both read-only reset: # the reset value is known if both FS and VS are legal", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_c3d769ad", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstatus.yaml", + "section": "mstatus.MDT", + "text": "CSR mstatus field MDT (bits=42) Written to 1 when entering M-mode from an exception/interrupt.\nWhen returning via an MRET instruction, the bit is written to 0.\nOn reset in set to 1, and software should write it to 0 when boot sequence is done.\nWhen mstatus.MDT=1, direct write by CSR instruction cannot set mstatus.MIE to 1, if not type: RW-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_641f1b89", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstatus.yaml", + "section": "mstatus.MPV", + "text": "CSR mstatus field MPV (bits=39) Written with the prior virtualization mode when entering M-mode from an exception/interrupt.\nWhen returning via an MRET instruction, the virtualization mode becomes the value of MPV unless MPP=3, in which case the virtualization mode is always 0.\nCan also be written by software. type: RW-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_593d2d21", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstatus.yaml", + "section": "mstatus.GVA", + "text": "CSR mstatus field GVA (bits=38) When a trap is taken and a guest virtual address is written into mtval, GVA is set.\nWhen a trap is taken and a guest virtual address is written into mtval, GVA is cleared. type: RW-H", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ff9597c6", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstatus.yaml", + "section": "mstatus.MBE", + "text": "CSR mstatus field MBE (bits=37) Controls the endianness of data M-mode (0 = little, 1 = big).\nInstructions are always little endian, regardless of the data setting.\n\n[when,\"M_MODE_ENDIANNESS == little\"]\nSince the CPU does not support big endian, this is hardwired to 0.\n\n[when,\"M_MODE_ENDIANNESS == big\"]\nSince the CPU does not supp type: return (M_MODE_ENDIANNESS == \"dynamic\") ? CsrFieldType::RW : CsrFieldType::RO; reset: return (M_MODE_ENDIANNESS == \"big\") ? 1 : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_61a23c75", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstatus.yaml", + "section": "mstatus.SBE", + "text": "CSR mstatus field SBE (bits=36) Controls the endianness of S-mode (0 = little, 1 = big).\nInstructions are always little endian, regardless of the data setting.\n\n[when,\"S_MODE_ENDIANNESS == little\"]\nSince the CPU does not support big endian, this is hardwired to 0.\n\n[when,\"S_MODE_ENDIANNESS == big\"]\nSince the CPU does not support l type: return (S_MODE_ENDIANNESS == \"dynamic\") ? CsrFieldType::RW : CsrFieldType::RO; reset: if (S_MODE_ENDIANNESS == \"little\") {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_f06e4aca", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstatus.yaml", + "section": "mstatus.SXL", + "text": "CSR mstatus field SXL (bits=35-34) Sets the effective XLEN for S-mode (0 = 32-bit, 1 = 64-bit, 2 = 128-bit [reserved]).\n\n[when,\"SXLEN==32\"]\nSince the CPU only supports SXLEN==32, this is hardwired to 1.\n\n[when,\"SXLEN==64\"]\nSince the CPU only supports SXLEN==64, this is hardwired to 2.\n\n[when,\"SXLEN=3264\"]\n--\nIt is not valid to have S type: return (implemented?(ExtensionName::S) && $array_size(SXLEN) > 1) ? CsrFieldType::RW : CsrFieldType::RO; reset: if ($array_size(SXLEN) == 1 && $array_includes?(SXLEN, 32)) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_fb300a9a", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstatus.yaml", + "section": "mstatus.UXL", + "text": "CSR mstatus field UXL (bits=33-32) U-mode XLEN.\n\nSets the effective XLEN for U-mode (1 = 32-bit, 2 = 64-bit, 3 = 128-bit [reserved]).\n\n[when,\"UXLEN == 32\"]\nSince the CPU only supports UXLEN==32, this is hardwired to 1.\n\n[when,\"UXLEN == 64\"]\nSince the CPU only supports UXLEN==64, this is hardwired to 2.\n\n\n[when,\"UXLEN == 3264\"]\n--\nIt type: return ($array_size(UXLEN) > 1) ? CsrFieldType::RW : CsrFieldType::RO; reset: if ($array_size(UXLEN) == 1 && UXLEN[0] == 32) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_cef9b0b7", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstatus.yaml", + "section": "mstatus.TSR", + "text": "CSR mstatus field TSR (bits=22) When 1, attempts to execute the `sret` instruction while executing in HS/S-mode\nwill raise an Illegal Instruction exception.\n\n[when,\"ext?(:H)\"]\nDoes not affect the behavior of `sret` in VS_mode (see `hstatus.VTSR`). type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_8d041f4e", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstatus.yaml", + "section": "mstatus.TW", + "text": "CSR mstatus field TW (bits=21) When 1, the WFI instruction will raise an Illegal Instruction trap after an\nimplementaion-defined wait period when executed in a mode other than M-mode.\n\nWhen 0, the `wfi` instruction is permitted to wait forever in (H)S-mode but must\ntrap after an implementation-defined wait period in U-mode. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_8dead226", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstatus.yaml", + "section": "mstatus.TVM", + "text": "CSR mstatus field TVM (bits=20) When 1, an `Illegal Instruction` trap occurs when\n\n* writing the `satp` CSR, executing an `sfence.vma`, or executing an `sinval.vma` while in (H)S-mode (but not VS-mode)\n* writing the `hgtap` CSR, executing an `hfence.gvma`, or executing an `hinval.gvma` while in HS-mode\n\nNotably, `mstatus.TVM` does type: if (CSR[misa].S == 1'b0) { reset: if (CSR[misa].S == 1'b0) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_7171ec2a", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstatus.yaml", + "section": "mstatus.MXR", + "text": "CSR mstatus field MXR (bits=19) When 1, loads from pages marked readable *or executable* are allowed.\nWhen 0, loads from pages marked executable raise a Page Fault exception. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_761da620", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstatus.yaml", + "section": "mstatus.SUM", + "text": "CSR mstatus field SUM (bits=18) When 0, an S-mode read or an M-mode read with mstatus.MPRV=1 and mstatus.MPP=01\nto a 'U' (user) page will cause an ILLEGAL INSTRUCTION exception. type: # only writable if there is some translation supported reset: if (has_virt_mem?()) {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_e5bb8e45", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstatus.yaml", + "section": "mstatus.MPRV", + "text": "CSR mstatus field MPRV (bits=17) When 1, loads and stores behave as if the current virtualization mode:privilege level was\n`mstatus.MPV`:`mstatus.MPP`.\n\n`mstatus.MPRV` is cleared on any exception return (`mret` or `sret` instruction, regardless of the trap handler privilege mode). type: return (CSR[misa].U == 1'b1) ? CsrFieldType::RWH : CsrFieldType::RO;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_8e0c86fb", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstatus.yaml", + "section": "mstatus.XS", + "text": "CSR mstatus field XS (bits=16-15) Summarizes the current state of any custom extension state.\nEither 0 - Off, 1 - Initial, 2 - Clean, 3 - Dirty.\nSince there are no custom extensions in the base spec, this field is read-only 0. type: RO", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_2eb61298", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstatus.yaml", + "section": "mstatus.FS", + "text": "CSR mstatus field FS (bits=14-13) When 0, floating point instructions (from F and D extensions) are disabled,\nand cause `ILLEGAL INSTRUCTION` exceptions.\nWhen a floating point register, or the fCSR register is written, FS obtains the value 3.\nValues 1 and 2 are valid write values for software, but are not interpreted by hardware\noth type: if (implemented?(ExtensionName::F) && (!MISA_CSR_IMPLEMENTED || CSR[misa].F == 1'b1)) { reset: return $array_size(MSTATUS_FS_LEGAL_VALUES) == 1 ? MSTATUS_FS_LEGAL_VALUES[0] : ", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_b6cb895b", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstatus.yaml", + "section": "mstatus.MPP", + "text": "CSR mstatus field MPP (bits=12-11) Written by hardware in two cases:\n\n* Written with the prior nominal privilege level when entering M-mode from an exception/interrupt.\n* Written with 0 when executing an `mret` instruction to return from an exception in M-mode.\n\nCan also be written by software without immediate side-effect.\n\nAffects type: RW-H reset: return 2'b11;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_705093ad", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstatus.yaml", + "section": "mstatus.VS", + "text": "CSR mstatus field VS (bits=10-9) When 0, vector instructions (from the V extension) are disabled, and cause ILLEGAL INSTRUCTION exceptions.\nWhen a vector register or vector CSR is written, VS obtains the value 3.\nValues 1 and 2 are valid write values for software, but are not interpreted by hardware\nother than to possibly enable a type: if (implemented?(ExtensionName::V) && (!MISA_CSR_IMPLEMENTED || CSR[misa].V == 1'b1)) { reset: if (CSR[misa].V == 1'b1){", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_2b3825d2", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstatus.yaml", + "section": "mstatus.SPP", + "text": "CSR mstatus field SPP (bits=8) Written by hardware in two cases:\n\n* Written with the prior nominal privilege level when entering (H)S-mode from an exception/interrupt.\n* Written with 0 when executing an `sret` instruction to return from an exception in (H)S-mode or (unlikely) M-mode.\n\nCan also be written by software without immed type: RW-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_52fc0879", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstatus.yaml", + "section": "mstatus.MPIE", + "text": "CSR mstatus field MPIE (bits=7) Written by hardware in two cases:\n\n* Written with prior value of `mstatus.MIE` when entering M-mode from an exception/interrupt.\n* Written with the value 1 when returning from an exception in M-mode (via the `mret` instruction).\n\nCan also be written by software without immediate side effect.\n\nOther type: RW-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_996ba725", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstatus.yaml", + "section": "mstatus.UBE", + "text": "CSR mstatus field UBE (bits=6) Controls the endianness of U-mode (0 = little, 1 = big).\nInstructions are always little endian, regardless of the data setting.\n\n[when,\"U_MODE_ENDIANNESS == 'little'\"]\nSince the CPU does not support big endian in U-mode, this is hardwired to 0.\n\n[when,\"U_MODE_ENDIANNESS == 'big'\"]\nSince the CPU does type: return (U_MODE_ENDIANNESS == \"dynamic\") ? CsrFieldType::RW : CsrFieldType::RO; reset: if (U_MODE_ENDIANNESS == \"little\") {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_afa60cd7", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstatus.yaml", + "section": "mstatus.SPIE", + "text": "CSR mstatus field SPIE (bits=5) Written by hardware in two cases:\n\n* Written with prior value of `mstatus.SIE` when entering (H)S-mode from an exception/interrupt.\n* Written with the value 1 when returning from an exception via the `sret` instruction in (H)S-mode or (unlikely) M-mode.\n\nCan also be written by software without immed type: return (CSR[misa].S == 1'b1) ? CsrFieldType::RWH : CsrFieldType::RO; reset: return (CSR[misa].S == 1'b1) ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_a16d85f4", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstatus.yaml", + "section": "mstatus.MIE", + "text": "CSR mstatus field MIE (bits=3) Written by hardware in two cases:\n\n* Written with the value 0 when entering M-mode from an exception/interrupt.\n* Written with the prior value of `mstatus.MPIE` when returning from an exception in M-mode (via `mret`).\n\nAffects execution by:\n\n* When 0, all interrupts are disabled when the current pri type: RW-H", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_c8615164", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstatus.yaml", + "section": "mstatus.SIE", + "text": "CSR mstatus field SIE (bits=1) Written by hardware in two cases:\n\n* Written with the value 0 when entering (H)S-mode from an exception/interrupt.\n* Written with the prior value of `mstatus.SPIE` when returning from an exception via `sret` in (H)S-mode or (unlikely) M-mode.\n\nAffects execution by:\n\n* When 0, all (H)S-mode interrupt type: return (CSR[misa].S == 1'b1) ? CsrFieldType::RWH : CsrFieldType::RO; reset: return (CSR[misa].S == 1'b1) ? UNDEFINED_LEGAL : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ecabb11b", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstatush.yaml", + "section": "mstatush", + "text": "CSR mstatush (address=784, priv=M): The mstatus register tracks and controls the hart's current operating state.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d4ab97f3", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstatush.yaml", + "section": "mstatush.MDT", + "text": "CSR mstatush field MDT (bits=10) *Machine Disable Trap*\n\nWritten to 1 when entering M-mode from an exception/interrupt.\nWhen returning via an MRET instruction, the bit is written to 0.\nOn reset in set to 1, and software should write it to 0 when boot sequence is done.\nWhen mstatush.MDT=1, direct write by CSR instruction cannot set type: RW-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_a52f0781", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstatush.yaml", + "section": "mstatush.MPV", + "text": "CSR mstatush field MPV (bits=7) *Machine Previous Virtualization mode*\n\nWritten with the prior virtualization mode when entering M-mode from an exception/interrupt.\nWhen returning via an MRET instruction, the virtualization mode becomes the value of MPV unless MPP=3, in which case the virtualization mode is always 0.\nCan also be w type: RW-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_37ccce29", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstatush.yaml", + "section": "mstatush.GVA", + "text": "CSR mstatush field GVA (bits=6) *Guest Virtual Address*\n\nWhen a trap is taken and a guest virtual address is written into mtval, GVA is set.\nWhen a trap is taken and a guest virtual address is written into mtval, GVA is cleared. type: RW-H", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_8b219605", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstatush.yaml", + "section": "mstatush.MBE", + "text": "CSR mstatush field MBE (bits=5) see `mstatus.MBE` type: return (M_MODE_ENDIANNESS == \"dynamic\") ? CsrFieldType::RW : CsrFieldType::RO; reset: return (M_MODE_ENDIANNESS == \"big\") ? 1 : 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_27ab6e29", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mstatush.yaml", + "section": "mstatush.SBE", + "text": "CSR mstatush field SBE (bits=4) see `mstatus.SBE` type: return (S_MODE_ENDIANNESS == \"dynamic\") ? CsrFieldType::RW : CsrFieldType::RO; reset: if (S_MODE_ENDIANNESS == \"little\") {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_4b1074a0", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mtval.yaml", + "section": "mtval", + "text": "CSR mtval (address=835, priv=M): Holds trap-specific information", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Sm" + }, + { + "chunk_id": "chunk_ae190273", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mtval.yaml", + "section": "mtval.VALUE", + "text": "CSR mtval field VALUE (bits=rv32=31-0 rv64=63-0) Written with trap-specific information when a trap is taken into M-mode.\n\nThe values are:\n\n[separator=\"!\"]\n!===\n! Exception type ! Value\n\n! [0] Instruction address misaligned ! The misaligned virtual PC (same as the value written to `mepc`).\n! [1] Instruction access fault ! The <% if ext?(:C) %> por type: RW-H", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ab0f85be", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mtvec.yaml", + "section": "mtvec", + "text": "CSR mtvec (address=773, priv=M): Controls where traps jump.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Sm" + }, + { + "chunk_id": "chunk_66a6fd6e", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mtvec.yaml", + "section": "mtvec.BASE", + "text": "CSR mtvec field BASE (bits=rv32=31-2 rv64=63-2) Bits [MXLEN-1:2] of the exception vector physical address for any trap taken in M-mode.\n\nThe implementation physical memory map may resitrict which values are legal in this field. type: return MTVEC_ACCESS == \"ro\" ? CsrFieldType::RO : CsrFieldType::RWR;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_bdddaad6", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mtvec.yaml", + "section": "mtvec.MODE", + "text": "CSR mtvec field MODE (bits=1-0) Vectoring mode for asynchronous interrupts.\n\n0 - Direct, 1 - Vectored\n\nWhen Direct, all synchronous exceptions and asynchronous interrupts jump to (`mtvec.BASE` << 2).\n\nWhen Vectored, asynchronous interrupts jump to (`mtvec.BASE` << 2 + `mcause.CAUSE`*4) while synchronous exceptions continue to jump type: if (MTVEC_ACCESS == \"ro\") { reset: return ($array_size(MTVEC_MODES) == 1) ? MTVEC_MODES[0] : UNDEFINED_LEGAL;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_65cee720", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mvendorid.yaml", + "section": "mvendorid", + "text": "CSR mvendorid (address=3857, priv=M): Reports the JEDEC manufacturer ID of the core.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Sm" + }, + { + "chunk_id": "chunk_b222db2c", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mvendorid.yaml", + "section": "mvendorid.Bank", + "text": "CSR mvendorid field Bank (bits=31-7) JEDEC manufacturer ID bank minus 1 type: RO reset: return VENDOR_ID_BANK;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ec0d07e7", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/mvendorid.yaml", + "section": "mvendorid.Offset", + "text": "CSR mvendorid field Offset (bits=6-0) JEDEC manufacturer ID offset type: RO reset: return VENDOR_ID_OFFSET;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_8036e727", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/satp.yaml", + "section": "satp", + "text": "CSR satp (address=384, priv=S): Controls the translation mode in (H)S-mode and U-mode, and holds the current ASID and page table base pointer.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "S" + }, + { + "chunk_id": "chunk_fa01b23b", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/satp.yaml", + "section": "satp.MODE", + "text": "CSR satp field MODE (bits=rv32=31 rv64=63-60) *Translation Mode*\n\nControls the current translation mode according to the table below.\n\n[separator=\"!\",%autowidth]\n!===\n! Value ! Name ! Description\n\n! 0 ! Bare a! No translation -> virtual address == physical address\n<%- if ext?(:Sv39) -%>\n! 8 ! Sv39 ! 39-bit virtual address translation\n<%- end -% type: RW-R reset: return 0;", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_6ac66552", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/satp.yaml", + "section": "satp.ASID", + "text": "CSR satp field ASID (bits=rv32=30-22 rv64=59-44) *Address Space ID* type: RW-R reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_59b62514", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/satp.yaml", + "section": "satp.PPN", + "text": "CSR satp field PPN (bits=rv32=21-0 rv64=43-0) *Physical Page Number*\n\nThe physical address of the active root page table is PPN << 12.\n\nCan only hold values that correspond to a valid page table base, which\nwill be implementation-dependent. type: RW-R reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_f5c66650", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/scause.yaml", + "section": "scause", + "text": "CSR scause (address=322, priv=S): Reports the cause of the latest exception.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "S" + }, + { + "chunk_id": "chunk_dd8033b9", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/scause.yaml", + "section": "scause.INT", + "text": "CSR scause field INT (bits=rv32=31 rv64=63) Written by hardware when a trap is taken into S-mode.\n\nWhen set, the last exception was caused by an asynchronous Interrupt.\n\n`scause.INT` is writable.\n\n[when,\"TRAP_ON_ILLEGAL_WLRL == true\"]\nIf `scause` is written with an undefined cause (combination of `scause.INT` and `scause.CODE`), an `Illegal I type: RW-RH reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_98781587", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/scause.yaml", + "section": "scause.CODE", + "text": "CSR scause field CODE (bits=rv32=30-0 rv64=62-0) Written by hardware when a trap is taken into S-mode.\n\nHolds the interrupt or exception code for the last taken trap.\n\n`scause.CODE` is writable.\n\n[when,\"TRAP_ON_ILLEGAL_WLRL == true\"]\nIf `scause` is written with an undefined cause (combination of `scause.INT` and `scause.CODE`), an `Illegal Instruc type: RW-RH reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ddf30d01", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/scontext.yaml", + "section": "scontext", + "text": "CSR scontext (address=1448, priv=S): This optional register is only accessible in S/HS-mode, VS-mode, M-mode and Debug Mode.\nAccessibility of this CSR is controlled by `mstateen0[57]` and `hstateen0[57]` in the\nSmstateen extension. Enabling `scontext` can be a security risk in a virtualized system\nwith a hypervisor that does not swap `", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_39838493", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/scontext.yaml", + "section": "scontext.DATA", + "text": "CSR scontext field DATA (bits=31-0) Supervisor mode software can write a context number to\nthis register, which can be used to set triggers that only fire\nin that specific context.\n\nAn implementation may tie any number of high bits in\nthis field to 0. It’s recommended to implement 16 bits on\nRV32 and 32 bits on RV64. type: RW", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_58412263", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/senvcfg.yaml", + "section": "senvcfg", + "text": "CSR senvcfg (address=266, priv=S): Contains fields that control certain characteristics of the U-mode execution environment.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d8c9f4d6", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/senvcfg.yaml", + "section": "senvcfg.CBZE", + "text": "CSR senvcfg field CBZE (bits=7) *Cache Block Zero instruction Enable*\n\nBit is read-only 0 when `menvcfg.CBZE` is clear.\n\nEnables the execution of the cache block zero instruction, `cbo.zero`,\nin U-mode<% if ext?(:H) %> and (in conjunction with `henvcfg.CBZE`) VU-mode<% end %>.\n\n * `0`: The instruction raises an illegal instructio type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_4c1a1dfa", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/senvcfg.yaml", + "section": "senvcfg.CBCFE", + "text": "CSR senvcfg field CBCFE (bits=6) *Cache Block Clean and Flush instruction Enable*\n\nEnables the execution of the cache block clean instruction, `cbo.clean`, and the\ncache block flush instruction, `cbo.flush`,\n<% if ext?(:S) %>\nin S-mode\n<% elsif ext?(:U) %>\nin U-mode\n<% end %>.\n\n * `0`: The instruction raises an illegal instruction type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_aa3254ac", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/senvcfg.yaml", + "section": "senvcfg.CBIE", + "text": "CSR senvcfg field CBIE (bits=5-4) *Cache Block Invalidate instruction Enable*\n\nThis field has restricted values based on the value of `menvcfg.CBIE`.\nWhen an invalid value is written, it is ignored and the field remains unchanged.\n\n[separator=\"!\",%autowidth,cols=\",.>\"]\n!===\n! [.rotate]#`menvcfg.CBIE`# ! Valid values of `senvcfg.CBIE type: RW-R reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_c632b9f0", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/senvcfg.yaml", + "section": "senvcfg.SSE", + "text": "CSR senvcfg field SSE (bits=3) *Shadow Stack Enable*\n\nWhen the SSE field is set to 1, the Zicfiss extension is\nactivated in VU/U-mode. When the SSE field is 0, the Zicfiss extension remains inactive\nin VU/U-mode, and the following rules apply:\n\n - 32-bit Zicfiss instructions will revert to their behavior as defined by Zimop.\n\n type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_2f70ff25", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/senvcfg.yaml", + "section": "senvcfg.FIOM", + "text": "CSR senvcfg field FIOM (bits=rv32=? rv64=?) *Fence of I/O implies Memory*\n\nWhen either `senvcfg.FIOM` or `menvcfg.FIOM` is set,\nFENCE instructions ordering I/O regions also implicitly order memory regions when executed\nin U-mode as follows:\n\n[separator=\"!\",%autowidth,float=\"center\",align=\"center\",cols=\"^,<\",options=\"header\"]\n!===\n!Instruction type: RW", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_1fc80719", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/sepc.yaml", + "section": "sepc", + "text": "CSR sepc (address=321, priv=S): Written with the PC of an instruction on an exception or interrupt taken in (H)S-mode.\n\nAlso controls where the hart jumps on an exception return from (H)S-mode.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "S" + }, + { + "chunk_id": "chunk_1e59db69", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/sepc.yaml", + "section": "sepc.PC", + "text": "CSR sepc field PC (bits=63-0) When a trap is taken into S-mode, `sepc.PC` is written with the virtual address of the\ninstruction that was interrupted or that encountered the exception.\nOtherwise, `sepc.PC` is never written by the implementation, though it may be explicitly written\nby software.\n\nOn an exception return from S-mode type: RW-RH reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_3d171eee", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/sie.yaml", + "section": "sie", + "text": "CSR sie (address=260, priv=S): Supervisor interrupt-enable register.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "S" + }, + { + "chunk_id": "chunk_9290bd31", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/sie.yaml", + "section": "sie.SSIE", + "text": "CSR sie field SSIE (bits=1) Supervisor Software Interrupt Enable type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_96e72ea7", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/sie.yaml", + "section": "sie.STIE", + "text": "CSR sie field STIE (bits=5) Supervisor Timer Interrupt Enable type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_610a1cdc", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/sie.yaml", + "section": "sie.SEIE", + "text": "CSR sie field SEIE (bits=9) Supervisor External Interrupt Enable type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_75c30bb1", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/sie.yaml", + "section": "sie.LCOFIE", + "text": "CSR sie field LCOFIE (bits=13) Local Counter Overflow Interrupt Enable type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_2a7926f9", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/sip.yaml", + "section": "sip", + "text": "CSR sip (address=324, priv=S): A restricted view of the interrupt pending bits in `mip`.\n\nHypervisor-related interrupts (VS-mode interrupts and Supervisor Guest interrupts) are not reflected\nin `sip` even though those interrupts can be taken in HS-mode. Instead, they are reported through `hip`.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "S" + }, + { + "chunk_id": "chunk_a3c5096e", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/sip.yaml", + "section": "sip.SSIP", + "text": "CSR sip field SSIP (bits=1) *Supervisor Software Interrupt Pending*\n\nReports the current pending state of an (H)S-mode software interrupt.\n\nWhen Supervisor Software Interrupts are not delegated to (H)S-mode (`mideleg.SSI` is clear), `sip.SSIP` is read-only 0.\n\nOtherwise, `sip.SSIP` is an alias of `mip.SSIP`.\n\n<%- if ext?(:Smai type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_823fdcd2", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/sip.yaml", + "section": "sip.STIP", + "text": "CSR sip field STIP (bits=5) *Supervisor Timer Interrupt Pending*\n\nReports the current pending state of an (H)S-mode timer interrupt.\n\nWhen Supervisor Timer Interrupts are not delegated to (H)S-mode (_i.e._, `mideleg.STI` is clear), `sip.STIP` is read-only 0.\n\nOtherwise, `sip.STIP` is a read-only view of `mip.STIP`.\n\n<% if ext? type: RO-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d11d930c", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/sip.yaml", + "section": "sip.SEIP", + "text": "CSR sip field SEIP (bits=9) *Supervisor External Interrupt Pending*\n\nReports the current pending state of an (H)S-mode external interrupt.\n\nWhen Supervisor External Interrupts are not delegated to (H)S-mode (_i.e._, `mideleg.SEI` is clear), `sip.SEIP` is read-only 0.\n\nOtherwise, `sip.SEIP` is a read-only view of `mip.SEIP`.\n\nT type: RO-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_774f5243", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/sip.yaml", + "section": "sip.LCOFIP", + "text": "CSR sip field LCOFIP (bits=13) *Local Counter Overflow Interrupt pending*\n\nReports the current pending state of a Local Counter Overflow interrupt.\n\nWhen Local Counter Overflow interrupts are not delegated to (H)S-mode (_i.e._, `mideleg.LCOFI` is clear), `sip.LCOFIP` is read-only 0.\n\nOtherwise, `sip.LCOFIP` is an alias of `mip.LC type: RW-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_975801bf", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/sscratch.yaml", + "section": "sscratch", + "text": "CSR sscratch (address=320, priv=S): Scratch register for software use. Bits are not interpreted by hardware.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "S" + }, + { + "chunk_id": "chunk_2c05079e", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/sscratch.yaml", + "section": "sscratch.SCRATCH", + "text": "CSR sscratch field SCRATCH (bits=63-0) Scratch value type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_6fc7b495", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/ssp.yaml", + "section": "ssp", + "text": "CSR ssp (address=17, priv=U): The `ssp` CSR is an unprivileged read-write (URW) CSR that reads and writes\nXLEN low order bits of the shadow stack pointer. The `ssp` is always as wide\nas the XLEN of the current privilege mode. The bits 1:0 of ssp are read-only\nzero. If the UXLEN or SXLEN may never be 32, then the bit 2 is also re", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Zicfiss" + }, + { + "chunk_id": "chunk_307c473d", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/ssp.yaml", + "section": "ssp.VALUE", + "text": "CSR ssp field VALUE (bits=rv32=31-2 rv64=63-3) The value in ssp points to the top of the shadow stack, which is the address\nof the last element stored on the shadow stack. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_23c1d3e8", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/sstateen0.yaml", + "section": "sstateen0", + "text": "CSR sstateen0 (address=268, priv=S): Each bit of a `stateen` CSR controls less-privileged access to an extension’s state,\nfor an extension that was not deemed \"worthy\" of a full XS field in `sstatus` like the\nFS and VS fields for the F and V extensions.\n\nThe number of registers provided at each level is four because it is believed that", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_429b90c1", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/sstateen0.yaml", + "section": "sstateen0.JVT", + "text": "CSR sstateen0 field JVT (bits=2) The JVT bit controls access to the `jvt` CSR provided by the Zcmt extension. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d292a435", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/sstateen0.yaml", + "section": "sstateen0.FCSR", + "text": "CSR sstateen0 field FCSR (bits=1) The FCSR bit controls access to `fcsr` for the case when floating-point instructions\noperate on `x` registers instead of `f` registers as specified by the Zfinx and related\nextensions (Zdinx, etc.). Whenever `misa.F` = 1, FCSR bit of `mstateen0` is read-only\nzero (and hence read-only zero in `hstate type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d1efaaf0", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/sstateen0.yaml", + "section": "sstateen0.C", + "text": "CSR sstateen0 field C (bits=rv32=? rv64=?) The C bit controls access to any and all custom state. The C bit of these registers is\nnot custom state itself; it is a standard field of a standard CSR, either `mstateen0`,\n`hstateen0`, or `sstateen0`. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_69f9b4f0", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/sstateen1.yaml", + "section": "sstateen1", + "text": "CSR sstateen1 (address=269, priv=S): Each bit of a `stateen` CSR controls less-privileged access to an extension’s state,\nfor an extension that was not deemed \"worthy\" of a full XS field in `sstatus` like the\nFS and VS fields for the F and V extensions.\n\nThe number of registers provided at each level is four because it is believed that", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_b5c31b5f", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/sstateen1.yaml", + "section": "sstateen1.DATA", + "text": "CSR sstateen1 field DATA (bits=rv32=31-0 rv64=63-0) Data value type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_6e4968c7", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/sstateen2.yaml", + "section": "sstateen2", + "text": "CSR sstateen2 (address=270, priv=S): Each bit of a `stateen` CSR controls less-privileged access to an extension’s state,\nfor an extension that was not deemed \"worthy\" of a full XS field in `sstatus` like the\nFS and VS fields for the F and V extensions.\n\nThe number of registers provided at each level is four because it is believed that", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_6ca72e74", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/sstateen2.yaml", + "section": "sstateen2.DATA", + "text": "CSR sstateen2 field DATA (bits=rv32=31-0 rv64=63-0) Data value type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_1d59d801", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/sstateen3.yaml", + "section": "sstateen3", + "text": "CSR sstateen3 (address=271, priv=S): Each bit of a `stateen` CSR controls less-privileged access to an extension’s state,\nfor an extension that was not deemed \"worthy\" of a full XS field in `sstatus` like the\nFS and VS fields for the F and V extensions.\n\nThe number of registers provided at each level is four because it is believed that", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_019dcfeb", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/sstateen3.yaml", + "section": "sstateen3.DATA", + "text": "CSR sstateen3 field DATA (bits=rv32=31-0 rv64=63-0) Data value type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ad7a589d", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/sstatus.yaml", + "section": "sstatus", + "text": "CSR sstatus (address=256, priv=S): The sstatus register tracks and controls the hart's current operating state.\n\nAll fields in sstatus are aliases of the same field in mstatus.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "S" + }, + { + "chunk_id": "chunk_4594749c", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/sstatus.yaml", + "section": "sstatus.SD", + "text": "CSR sstatus field SD (bits=rv32=31 rv64=63) *State Dirty*\n\nAlias of `mstatus.SD`. type: RO-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_c3c102e7", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/sstatus.yaml", + "section": "sstatus.UXL", + "text": "CSR sstatus field UXL (bits=33-32) *U-mode XLEN*\n\nAlias of `mstatus.UXL`. type: RO reset: 2", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_c70a2fec", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/sstatus.yaml", + "section": "sstatus.MXR", + "text": "CSR sstatus field MXR (bits=19) *Make eXecutable Readable*\n\nAlias of `mstatus.MXR`. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_f4c53f69", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/sstatus.yaml", + "section": "sstatus.SUM", + "text": "CSR sstatus field SUM (bits=18) *permit Supervisor Memory Access*\n\nAlias of `mstatus.SUM`. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_da4bd727", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/sstatus.yaml", + "section": "sstatus.XS", + "text": "CSR sstatus field XS (bits=16-15) Custom (X) extension context Status.\n\nAlias of `mstatus.XS`. type: RO reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ad5659a6", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/sstatus.yaml", + "section": "sstatus.FS", + "text": "CSR sstatus field FS (bits=14-13) Floating point context status.\n\nAlias of `mstatus.FS`. type: RW-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d276a675", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/sstatus.yaml", + "section": "sstatus.VS", + "text": "CSR sstatus field VS (bits=10-9) Vector context status.\n\nAlias of `mstatus.VS`. type: RW-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_4a74901b", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/sstatus.yaml", + "section": "sstatus.SPP", + "text": "CSR sstatus field SPP (bits=8) *S-mode Previous Privilege*\n\nAlias of `mstatus.SPP`. type: RW-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_30ee0563", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/sstatus.yaml", + "section": "sstatus.UBE", + "text": "CSR sstatus field UBE (bits=6) *U-mode Big Endian*\n\nAlias of `mstatus.UBE`. type: RO reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_affeb2c5", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/sstatus.yaml", + "section": "sstatus.SPIE", + "text": "CSR sstatus field SPIE (bits=5) *S-mode Previous Interrupt Enable*\n\nAlias of `mstatus.SPIE`. type: RW-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_3fa3dd0d", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/sstatus.yaml", + "section": "sstatus.SIE", + "text": "CSR sstatus field SIE (bits=1) *S-mode Interrupt Enable*\n\nAlias of `mstatus.SIE`. type: RW-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_6e0f4553", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/stval.yaml", + "section": "stval", + "text": "CSR stval (address=323, priv=S): Holds trap-specific information", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "S" + }, + { + "chunk_id": "chunk_2d0f51ae", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/stval.yaml", + "section": "stval.VALUE", + "text": "CSR stval field VALUE (bits=63-0) Written with trap-specific information when a trap is taken into S-mode.\n\nThe values are:\n\n[separator=\"!\"]\n!===\n! Exception type ! Value\n\n! [0] Instruction address misaligned ! The misaligned virtual PC (same as the value written to `mepc`).\n! [1] Instruction access fault ! The <% if ext?(:C) %> por type: RW-H", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_90f30047", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/stvec.yaml", + "section": "stvec", + "text": "CSR stvec (address=261, priv=S): Controls where traps jump.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "S" + }, + { + "chunk_id": "chunk_d9de21fc", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/stvec.yaml", + "section": "stvec.BASE", + "text": "CSR stvec field BASE (bits=63-2) <%- va_size = ext?(:Sv57) ? 57 : (ext?(:Sv48) ? 49 :39) -%>\nBit 63:0 of the virtual address of the exception vector for any trap taken into S-mode.\n\nIf the base address is written with a non-cannonical address (_i.e._, bits 63:<%= va_size %> do not match bit <%= va_size-1 %>),\nthe write should be ig type: RW-R reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_43051c43", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/stvec.yaml", + "section": "stvec.MODE", + "text": "CSR stvec field MODE (bits=1-0) Vectoring mode for asynchronous interrupts.\n\n0 - Direct, 1 - Vectored\n\nWhen Direct, all synchronous exceptions and asynchronous interrupts jump to (`stvec.BASE` << 2).\n\nWhen Vectored, asynchronous interrupts jump to (`stvec.BASE` << 2 + `scause.CAUSE`*4) while synchronous exceptions continue to jump type: RW-R", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_8bac9d1a", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/tdata1.yaml", + "section": "tdata1", + "text": "CSR tdata1 (address=1953, priv=M): This register provides access to the trigger selected by `tselect`.\nThe reset values listed here apply to every underlying trigger.\n\nThis register is optional if no triggers are implemented.\nWriting 0 to this register must result in a trigger that is disabled.\nIf this trigger supports multiple types", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Sdtrig" + }, + { + "chunk_id": "chunk_f12a97c3", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/tdata1.yaml", + "section": "tdata1.TYPE", + "text": "CSR tdata1 field TYPE (bits=rv32=31-28 rv64=63-60) 0 (none):: There is no trigger at this `tselect`.\n1 (legacy):: The trigger is a legacy SiFive address match trigger. These should not be implemented and aren’t further documented here.\n2 (mcontrol):: The trigger is an address/data match trigger. The remaining bits in this register act as described i type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_b23ab28d", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/tdata1.yaml", + "section": "tdata1.DMODE", + "text": "CSR tdata1 field DMODE (bits=rv32=27 rv64=59) If type is 0, then this bit is hard-wired to 0.\n\n0 (both): Both Debug and M-mode can write the `tdata` registers at the selected `tselect`.\n1 (dmode): Only Debug Mode can write the `tdata` registers at the selected `tselect`. Writes from other modes are ignored.\n\nThis bit is only writable from Debug type: RW", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_0898f47a", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/tdata1.yaml", + "section": "tdata1.DATA", + "text": "CSR tdata1 field DATA (bits=rv32=26-0 rv64=58-0) If type is 0, then this field is hard-wired to 0.\nTrigger-specific data. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_564e15ed", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/tdata2.yaml", + "section": "tdata2", + "text": "CSR tdata2 (address=1954, priv=M): This register provides access to the trigger selected by `tselect`.\nThe reset values listed here apply to every underlying trigger.\n\nTrigger-specific data. It is optional if no implemented triggers use it.\nIf the trigger is disabled, then this register can be written with any value\nsupported by any ", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Sdtrig" + }, + { + "chunk_id": "chunk_f123657a", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/tdata2.yaml", + "section": "tdata2.DATA", + "text": "CSR tdata2 field DATA (bits=rv32=31-0 rv64=63-0) Data value type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_f13dcdda", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/tdata3.yaml", + "section": "tdata3", + "text": "CSR tdata3 (address=1955, priv=M): This register provides access to the trigger selected by `tselect`.\nThe reset values listed here apply to every underlying trigger.\n\nTrigger-specific data. It is optional if no implemented triggers use it.\nIf the trigger is disabled, then this register can be written with any value\nsupported by any ", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Sdtrig" + }, + { + "chunk_id": "chunk_66d22b93", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/tdata3.yaml", + "section": "tdata3.DATA", + "text": "CSR tdata3 field DATA (bits=rv32=31-0 rv64=63-0) Data value type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_89f016bb", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/time.yaml", + "section": "time", + "text": "CSR time (address=3073, priv=U): [when,\"TIME_CSR_IMPLEMENTED == false\"]\nThis CSR does not exist, and access will cause an IllegalInstruction exception.\n\n[when,\"TIME_CSR_IMPLEMENTED == true\"]\n--\nShadow of the memory-mapped M-mode CSR `mtime`.\n\nPrivilege mode access is controlled with `mcounteren.TM`, `scounteren.TM`, and `hcounteren", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Zicntr" + }, + { + "chunk_id": "chunk_b398cc0c", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/time.yaml", + "section": "time.COUNT", + "text": "CSR time field COUNT (bits=63-0) Reports the current wall-clock time from the timer device.\n\nAlias of the `mtime` memory-mapped CSR. type: RO-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_3a9d470d", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/timeh.yaml", + "section": "timeh", + "text": "CSR timeh (address=3201, priv=U): [when,\"TIME_CSR_IMPLEMENTED == false\"]\nThis CSR does not exist, and access will cause an IllegalInstruction exception.\n\n[when,\"TIME_CSR_IMPLEMENTED == true\"]\n--\nShadow of the memory-mapped M-mode CSR `mtimeh`.\n\nPrivilege mode access is controlled with `mcounteren.TM`, `scounteren.TM`, and `hcountere", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_8583257d", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/timeh.yaml", + "section": "timeh.COUNT", + "text": "CSR timeh field COUNT (bits=31-0) Reports the most significant 32 bits of the current wall-clock time from the timer device. type: RO-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_5b9a9331", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/tselect.yaml", + "section": "tselect", + "text": "CSR tselect (address=1952, priv=M): This register determines which trigger is accessible through the other Trigger Module registers.\n\nIt is optional if no triggers are implemented. The set of accessible triggers must start at 0,\nand be contiguous. This register is WARL. Writes of values greater than or equal to the number of\nsupported", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "Sdtrig" + }, + { + "chunk_id": "chunk_87a13353", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/tselect.yaml", + "section": "tselect.INDEX", + "text": "CSR tselect field INDEX (bits=rv32=31-0 rv64=63-0) Index value type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_69cfa6d5", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/vscause.yaml", + "section": "vscause", + "text": "CSR vscause (address=578, priv=VS): Reports the cause of the latest exception taken in VS-mode.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "H" + }, + { + "chunk_id": "chunk_1a1eb61d", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/vscause.yaml", + "section": "vscause.INT", + "text": "CSR vscause field INT (bits=rv32=31 rv64=63) Written by hardware when a trap is taken into VS-mode.\n\nWhen set, the last exception was caused by an asynchronous Interrupt.\n\n`vscause.INT` is writable.\n\n[when,\"TRAP_ON_ILLEGAL_WLRL == true\"]\nIf `vscause` is written with an undefined cause (combination of `vscause.INT` and `vscause.CODE`), an `Ille type: RW-RH reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_c9313241", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/vscause.yaml", + "section": "vscause.CODE", + "text": "CSR vscause field CODE (bits=rv32=30-0 rv64=62-0) Written by hardware when a trap is taken into VS-mode.\n\nHolds the interrupt or exception code for the last taken trap.\n\n`vscause.CODE` is writable.\n\n[when,\"TRAP_ON_ILLEGAL_WLRL == true\"]\nIf `vscause` is written with an undefined cause (combination of `vscause.INT` and `vscause.CODE`), an `Illegal In type: RW-RH reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_195d5a2b", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/vsepc.yaml", + "section": "vsepc", + "text": "CSR vsepc (address=577, priv=VS): Written with the PC of an instruction on an exception or interrupt taken in VS-mode.\n\nAlso controls where the hart jumps on an exception return from VS-mode.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "H" + }, + { + "chunk_id": "chunk_0ebd4310", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/vsepc.yaml", + "section": "vsepc.PC", + "text": "CSR vsepc field PC (bits=63-0) When a trap is taken into VS-mode, `vsepc.PC` is written with the virtual address of the\ninstruction that was interrupted or that encountered the exception.\nOtherwise, `vsepc.PC` is never written by the implementation, though it may be explicitly written\nby software.\n\nOn an exception return from VS- type: RW-RH reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_2689ca30", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/vsstatus.yaml", + "section": "vsstatus", + "text": "CSR vsstatus (address=512, priv=VS): The vsstatus register tracks and controls the hart's current operating state.\n\nIt is VS-mode's version of `sstatus`, and substitutes for it when in VS-mode\n(_i.e._, in VS-mode CSR address 0x100 is `vsstatus`, not `sstatus`).\n\nUnlike the relationship between `sstatus` and `mstatus`, none of the bits ", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "H" + }, + { + "chunk_id": "chunk_b579ea12", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/vsstatus.yaml", + "section": "vsstatus.SD", + "text": "CSR vsstatus field SD (bits=rv32=31 rv64=63) *State Dirty*\n\nRead-only bit that summarizes whether any of the\n`vsstatus.FS`, <% if ext?(:V) %> `vsstatus.VS`, <% end %> or `vsstatus.XS`\nfields signal the presence of some dirty state\n(_i.e._, any of them hold the value `11`).\n\nThis bit is _not_ an alias of `mstatus.SD` since\nit only reflects the type: RO-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_ad16dbd3", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/vsstatus.yaml", + "section": "vsstatus.UXL", + "text": "CSR vsstatus field UXL (bits=33-32) *VU-mode XLEN*\n\nSets the effective XLEN for VU-mode (0 = 32-bit, 1 = 64-bit, 2 = 128-bit).\n\n[when,\"VUXLEN == 32\"]\nSince the hart only supports VUXLEN==32, this is hardwired to 0.\n\n[when,\"VUXLEN == 64\"]\nSince the hart only supports VUXLEN==64, this is hardwired to 1. type: return ($array_size(VUXLEN) > 1) ? CsrFieldType::RW : CsrFieldType::RO; reset: return ($array_size(VUXLEN) > 1) ? UNDEFINED_LEGAL : VUXLEN[0];", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_2034bf91", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/vsstatus.yaml", + "section": "vsstatus.MXR", + "text": "CSR vsstatus field MXR (bits=19) *Make eXecutable Readable*\n\nMakes it possible to read executable pages when loading from effective VU-mode or VS-mode\n(normally, executable pages are not readable).\n\n* When 1, load in effective VU-mode or VS-mode from pages marked readable *or executable*\n are allowed as long as the page is marked type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_d0e093b8", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/vsstatus.yaml", + "section": "vsstatus.SUM", + "text": "CSR vsstatus field SUM (bits=18) *permit Supervisor Memory Access*\n\nAllows VS-mode to read user pages.\n\nApplies to the following loads and stores:\n\n* All loads and stores in VS-mode.\n* All loads and stores in M-mode when `mstatus.MPRV` == 1, `mstatus.MPP` == 1, and `mstatus.MPV` == 1\n* Loads and stores generated by one of the `hlv. type: RW reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_589d5766", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/vsstatus.yaml", + "section": "vsstatus.XS", + "text": "CSR vsstatus field XS (bits=16-15) *Custom (X) extension context Status*\n\nSummarizes the current state of any custom extension state.\nEither 0 - Off, 1 - Initial, 2 - Clean, 3 - Dirty.\nSince there are no custom extensions, this field is read-only 0. type: RO", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_695657c3", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/vsstatus.yaml", + "section": "vsstatus.FS", + "text": "CSR vsstatus field FS (bits=14-13) *Floating point context status*\n\nWhen 0, floating point instructions (from F and D extensions) in VS-mode or VU-mode are disabled,\nand cause ILLEGAL INSTRUCTION exceptions.\nFloating point instructions in all modes, including VS-mode and VU-mode,\nare similarly disabled when `mstatus.FS` is clear.\n\nWh type: RW-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_e3ce5055", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/vsstatus.yaml", + "section": "vsstatus.VS", + "text": "CSR vsstatus field VS (bits=10-9) *Vector context status*\n\nWhen 0, vector instructions (from the V extension) are disabled, and cause ILLEGAL INSTRUCTION exceptions.\nWhen a vector register or vector CSR is written, VS obtains the value 3.\nValues 1 and 2 are valid write values for software, but are not interpreted by hardware\nother t type: RW-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_db5d4b4e", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/vsstatus.yaml", + "section": "vsstatus.SPP", + "text": "CSR vsstatus field SPP (bits=8) *VS-mode Previous Privilege*\n\nWritten with the prior nominal privilege level (_i.e._, 0 for VU-mode and 1 for VS-mode)\nwhen entering VS-mode from an exception/interrupt.\nCan also be written by software without immediate side-effect.\n\nOn a return from an exception from VS-mode, the machine will enter type: RW-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_63724b52", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/vsstatus.yaml", + "section": "vsstatus.UBE", + "text": "CSR vsstatus field UBE (bits=6) *VU-mode Big Endian*\n\nControls the endianness of VU-mode (0 = little, 1 = big).\n\n[when,\"VU_MODE_ENDIANNESS == 'little'\"]\nSince the CPU does not support big endian, this is hardwired to 0.\n\n[when,\"VU_MODE_ENDIANNESS == 'big'\"]\nSince the CPU does not support big endian, this is hardwired to 1. type: return (VU_MODE_ENDIANNESS == \"dynamic\") ? CsrFieldType::RW : CsrFieldType::RO; reset: if (VU_MODE_ENDIANNESS == \"little\") {", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_e958af66", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/vsstatus.yaml", + "section": "vsstatus.SPIE", + "text": "CSR vsstatus field SPIE (bits=5) *VS-mode Previous Interrupt Enable*\n\nWritten by hardware in two cases:\n\n* Written with prior value of `vsstatus.SIE` when entering VS-mode from an exception/interrupt.\n* Written with the value 1 when returning from an exception in VS-mode (via the `sret` instruction).\n\nCan also be written by softwar type: RW-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_9ac43316", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/vsstatus.yaml", + "section": "vsstatus.SIE", + "text": "CSR vsstatus field SIE (bits=1) *VS-mode Interrupt Enable*\n\nWritten by hardware in two cases:\n\n* Written with the value 0 when entering VS-mode from an exception/interrupt.\n* Written with the prior value of `vsstatus.SPIE` when returning from an exception in VS-mode (via `sret`).\n\nAffects execution by:\n\n* When 0, all VS-mode inter type: RW-H reset: UNDEFINED_LEGAL", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_4c45f241", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/vstval.yaml", + "section": "vstval", + "text": "CSR vstval (address=579, priv=S): Holds trap-specific information", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "H" + }, + { + "chunk_id": "chunk_a5d62ba6", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/vstval.yaml", + "section": "vstval.VALUE", + "text": "CSR vstval field VALUE (bits=rv32=31-0 rv64=63-0) Written with trap-specific information when a trap is taken into VS-mode.\n\nThe values are:\n\n[separator=\"!\"]\n!===\n! Exception type ! Value\n\n! [0] Instruction address misaligned ! The misaligned virtual PC (same as the value written to `mepc`).\n! [1] Instruction access fault ! The <% if ext?(:C) %> po type: RW-H", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_e1c254e9", + "source": "udb_csr", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/vstvec.yaml", + "section": "vstvec", + "text": "CSR vstvec (address=517, priv=S): Controls where traps jump.", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": "H" + }, + { + "chunk_id": "chunk_6ae9b115", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/vstvec.yaml", + "section": "vstvec.BASE", + "text": "CSR vstvec field BASE (bits=63-2) <%- va_size = ext?(:Sv57) ? 57 : (ext?(:Sv48) ? 49 :39) -%>\nBit 63:0 of the virtual address of the exception vector for any trap taken into VS-mode.\n\nIf the base address is written with a non-cannonical address (_i.e._, bits 63:<%= va_size %> do not match bit <%= va_size-1 %>),\nthe write should be i type: RW-R", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_75de66a8", + "source": "udb_csr_field", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/csr/vstvec.yaml", + "section": "vstvec.MODE", + "text": "CSR vstvec field MODE (bits=1-0) Vectoring mode for asynchronous interrupts taken into VS-mode.\n\n0 - Direct, 1 - Vectored\n\nWhen Direct, all synchronous exceptions and asynchronous interrupts jump to (`vstvec.BASE` << 2).\n\nWhen Vectored, asynchronous interrupts jump to (`vstvec.BASE` << 2 + `vscause.CAUSE`*4) while synchronous excep type: RW-R", + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "" + }, + { + "chunk_id": "chunk_775c4841", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/A.yaml", + "section": "A", + "text": "Extension A (Atomic instructions) [ratified] The atomic-instruction extension, named `A`, contains\ninstructions that atomically read-modify-write memory to support\nsynchronization between multiple RISC-V harts running in the same memory\nspace. The two forms of atomic instruction provided are\nload-reserved/store-conditional instructions and atomic fetch-and-op\nmemory instructions. Both types of atomic instruction support various\nmemory consis", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "A" + }, + { + "chunk_id": "chunk_0e04af9f", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/B.yaml", + "section": "B", + "text": "Extension B (Bit Manipulation) [ratified] The B standard extension comprises instructions provided by the `Zba`, `Zbb`, and `Zbs` extensions.\n\nBit 1 of the `misa` register encodes the presence of the B standard extension. When `misa.B` is 1,\nthe implementation supports the instructions provided by the `Zba`, `Zbb`, and `Zbs` extensions.\nWhen `misa.B` is 0, it indicates that the implementation may not support one or more of the\n`Zba`, `Zbb", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "B" + }, + { + "chunk_id": "chunk_3d18c798", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/C.yaml", + "section": "C", + "text": "Extension C (Compressed instructions) [ratified] The `C` extension reduces static and dynamic code size by\nadding short 16-bit instruction encodings for common operations. The C\nextension can be added to any of the base ISAs (RV32, RV64, RV128), and\nwe use the generic term \"RVC\" to cover any of these. Typically,\n50%-60% of the RISC-V instructions in a program can be replaced with RVC\ninstructions, resulting in a 25%-30% code-size reduction.\n\n= O", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "C" + }, + { + "chunk_id": "chunk_e99e3b92", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/D.yaml", + "section": "D", + "text": "Extension D (Double-precision floating-point) [ratified] The `D` extension adds\ndouble-precision floating-point computational instructions compliant\nwith the https://ieeexplore.ieee.org/document/4610935[IEEE 754-2008] arithmetic standard. The D extension depends on\nthe base single-precision instruction subset `F`.\n(((double-precision, floating point)))\n(((floating point, double precision)))\n\n= D Register State\n\nThe D extension widens the 32 floating-poi", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "D" + }, + { + "chunk_id": "chunk_6ab0892b", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/F.yaml", + "section": "F", + "text": "Extension F (Single-precision floating-point) [ratified] This chapter describes the standard instruction-set extension for\nsingle-precision floating-point, which is named \"F\" and adds\nsingle-precision floating-point computational instructions compliant\nwith the IEEE 754-2008 arithmetic standard cite:[ieee754-2008]. The F extension depends on the \"Zicsr\" extension for control and status register access.\n\n= F Register State\n\nThe F extension adds 32 floati", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "F" + }, + { + "chunk_id": "chunk_2ecac87a", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/H.yaml", + "section": "H", + "text": "Extension H (Hypervisor) [ratified] This chapter describes the RISC-V hypervisor extension, which\nvirtualizes the supervisor-level architecture to support the efficient\nhosting of guest operating systems atop a type-1 or type-2 hypervisor.\nThe hypervisor extension changes supervisor mode into\n_hypervisor-extended supervisor mode_ (HS-mode, or _hypervisor mode_ for\nshort), where a hypervisor or a hosting-capable operating system runs", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "H" + }, + { + "chunk_id": "chunk_289012fe", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/I.yaml", + "section": "I", + "text": "Extension I (Base integer ISA (RV32I or RV64I)) [ratified] Base integer instructions -- TODO", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "I" + }, + { + "chunk_id": "chunk_f16ef233", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/M.yaml", + "section": "M", + "text": "Extension M (Integer multiply and divide) [ratified] This chapter describes the standard integer multiplication and division\ninstruction extension, which is named `M` and contains instructions\nthat multiply or divide values held in two integer registers.\n\n[TIP]\n====\nWe separate integer multiply and divide out from the base to simplify\nlow-end implementations, or for applications where integer multiply and\ndivide operations are either infrequent or b", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "M" + }, + { + "chunk_id": "chunk_68054bed", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Q.yaml", + "section": "Q", + "text": "Extension Q (Quad-Precision Floating-Point) [ratified] 128-bit quad-precision binary floating-point instructions compliant with the IEEE 754-2008\narithmetic standard.\n`Q` depends on the double-precision floating-point extension `D`.\nWith `Q`, the floating-point registers are extended to hold either a single, double, or quad-precision\nfloating-point value (FLEN=128).\nThe NaN-boxing is extended recursively to allow a single-precision value to be NaN-box", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Q" + }, + { + "chunk_id": "chunk_b547dbc5", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/S.yaml", + "section": "S", + "text": "Extension S (Supervisor mode) [ratified] This chapter describes the RISC-V supervisor-level architecture, which\ncontains a common core that is used with various supervisor-level\naddress translation and protection schemes.\n\n[NOTE]\n====\nSupervisor mode is deliberately restricted in terms of interactions with\nunderlying physical hardware, such as physical memory and device\ninterrupts, to support clean virtualization. In this spirit, certain", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "S" + }, + { + "chunk_id": "chunk_2743fa42", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Sdext.yaml", + "section": "Sdext", + "text": "Extension Sdext (Debug) [ratified] Hart-visible portion of the debug spec.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Sdext" + }, + { + "chunk_id": "chunk_13987568", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Sdtrig.yaml", + "section": "Sdtrig", + "text": "Extension Sdtrig (Debug triggers) [ratified] Triggers can cause a breakpoint exception, entry into Debug Mode, or a\ntrace action without having to execute a special instruction. This makes\nthem invaluable when debugging code from ROM. They can trigger on\nexecution of instructions at a given memory address, or on the\naddress/data in loads/stores.\n\nIf Sdtrig is implemented, the Trigger Module must support at least one\ntrigger. Accessing trigge", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Sdtrig" + }, + { + "chunk_id": "chunk_b6b42fca", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Sha.yaml", + "section": "Sha", + "text": "Extension Sha (Augmented hypervisor) [ratified] *Sha* comprises the following extensions:\n\n** *H* The hypervisor extension.\n\n** *Ssstateen* Supervisor-mode view of the state-enable extension. The\n supervisor-mode (`sstateen0-3`) and hypervisor-mode (`hstateen0-3`)\n state-enable registers must be provided.\n\n** *Shcounterenw* For any `hpmcounter` that is not read-only zero, the corresponding bit in `hcounteren` must be writable.\n\n** *Shvstva", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Sha" + }, + { + "chunk_id": "chunk_1df9d8f1", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Shcounterenw.yaml", + "section": "Shcounterenw", + "text": "Extension Shcounterenw (Hypervisor counter enable) [ratified] For any hpmcounter that is not read-only zero, the corresponding bit in `hcounteren` must be writable.\n\n[NOTE]\nThis extension was ratified with the RVA22 profiles.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Shcounterenw" + }, + { + "chunk_id": "chunk_94989a19", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Shgatpa.yaml", + "section": "Shgatpa", + "text": "Extension Shgatpa (SvNNx4 mode supported for all modes supported by Supervisor Address Translation and Protection, as well as Bare) [ratified] For each supported virtual memory scheme SvNN supported in\n`satp`, the corresponding hgatp SvNNx4 mode must be supported. The\n`hgatp` mode Bare must also be supported.\n\n[NOTE]\nThis extension was ratified with the RVA22 profiles.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Shgatpa" + }, + { + "chunk_id": "chunk_8c03cc3c", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Shtvala.yaml", + "section": "Shtvala", + "text": "Extension Shtvala (Hypervisor Trap Value provides all needed values) [ratified] htval must be written with the faulting guest physical address in all circumstances permitted by\nthe ISA.\n\n[NOTE]\nThis extension was ratified with the RVA22 profiles.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Shtvala" + }, + { + "chunk_id": "chunk_780152bd", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Shvsatpa.yaml", + "section": "Shvsatpa", + "text": "Extension Shvsatpa (Virtual Supervisor Address Translation and Protection supports all modes supported by Supervisor Address Translation and Protection) [ratified] All translation modes supported in the `satp` CSR must be supported in the `vsatp` CSR.\n\n[NOTE]\nThis extension was ratified with the RVA22 profiles.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Shvsatpa" + }, + { + "chunk_id": "chunk_45af8c11", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Shvstvala.yaml", + "section": "Shvstvala", + "text": "Extension Shvstvala (Virtual Supervisor Trap Value provides all needed values) [ratified] vstval must be written with the faulting virtual address\nfor load, store, and instruction page-fault, access-fault, and\nmisaligned exceptions, and for breakpoint exceptions other than\nthose caused by execution of the `ebreak` or `c.ebreak` instructions.\nFor virtual-instruction and illegal-instruction exceptions, vstval must be written with the\nfaulting instruction.\n\n[NOTE]\nThis extension was ratif", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Shvstvala" + }, + { + "chunk_id": "chunk_b8805e9a", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Shvstvecd.yaml", + "section": "Shvstvecd", + "text": "Extension Shvstvecd (Virtual Supervisor Trap Vector Base Address supports Direct mode) [ratified] `vstvec.MODE` must be capable of holding the value 0 (Direct).\nWhen `vstvec.MODE`=Direct, `vstvec.BASE` must be capable of holding\nany valid four-byte-aligned address.\n\n[NOTE]\nThis extension was ratified with the RVA22 profiles.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Shvstvecd" + }, + { + "chunk_id": "chunk_d677067a", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Sm.yaml", + "section": "Sm", + "text": "Extension Sm (Machine mode) [ratified] This chapter describes the machine-level operations available in machine-mode (M-mode), which is\nthe highest privilege mode in a RISC-V hart. M-mode is used for low-level access to a hardware\nplatform and is the first mode entered at reset. M-mode can also be used to implement features that\nare too difficult or expensive to implement in hardware directly. The RISC-V machine-level ISA\ncontains a co", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Sm" + }, + { + "chunk_id": "chunk_50461ff0", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Smaia.yaml", + "section": "Smaia", + "text": "Extension Smaia (Advanced Interrupt Architecture, M-mode extension) [ratified] Advanced Interrupt Architecture, M-mode extension", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Smaia" + }, + { + "chunk_id": "chunk_8e21bbc6", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Smcdeleg.yaml", + "section": "Smcdeleg", + "text": "Extension Smcdeleg (Performance counter delegation) [ratified] Performance counter delegation", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Smcdeleg" + }, + { + "chunk_id": "chunk_e1bd2c24", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Smcntrpmf.yaml", + "section": "Smcntrpmf", + "text": "Extension Smcntrpmf (Cycle and Instret Privilege Mode Filtering) [ratified] Cycle and Instret Privilege Mode Filtering", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Smcntrpmf" + }, + { + "chunk_id": "chunk_3d4593eb", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Smcsrind.yaml", + "section": "Smcsrind", + "text": "Extension Smcsrind (Machine-mode Indirect CSR Access) [ratified] Smcsrind/Sscsrind is an ISA extension that extends the indirect CSR access mechanism originally defined as\npart of the Smaia/Ssaia extensions, in order to make it available for use by other extensions without creating\nan unnecessary dependence on Smaia/Ssaia.\n\nThis extension confers two benefits:\n\nIt provides a means to access an array of registers via CSRs without requiring allocation of large ch", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Smcsrind" + }, + { + "chunk_id": "chunk_da994234", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Smctr.yaml", + "section": "Smctr", + "text": "Extension Smctr (Control Transfer Records) [ratified] A method for recording control flow transfer history is valuable not only for performance\nprofiling but also for debugging.\nControl flow transfers refer to jump instructions (including function calls and returns), taken\nbranch instructions, traps, and trap returns.\nProfiling tools, such as Linux perf, collect control transfer history when sampling software\nexecution, thereby enabling tools, like A", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Smctr" + }, + { + "chunk_id": "chunk_4b998dab", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Smdbltrp.yaml", + "section": "Smdbltrp", + "text": "Extension Smdbltrp (Double trap in M-mode) [ratified] The `Smdbltrp` extension addresses a double trap in M-mode.\nWhen the `Smrnmi` extension is implemented, it enables invocation of the RNMI handler on a\ndouble trap in M-mode to handle the critical error.\nIf the `Smrnmi` extension is not implemented or if a double trap occurs during the RNMI\nhandler's execution, this extension helps transition the hart to a critical error state and\nenables signaling", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Smdbltrp" + }, + { + "chunk_id": "chunk_081dc0ba", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Smepmp.yaml", + "section": "Smepmp", + "text": "Extension Smepmp (PMP Enhancements for memory access and execution prevention on Machine mode) [ratified] The Smepmp extension enhances the Physical Memory Protection (PMP) mechanism\nto support M-mode memory access and execution prevention.\n\nSmepmp adds a new Machine Security Configuration register (`mseccfg`) with the\nfollowing key fields:\n\n* **MML (Machine Mode Lockdown)**: When set, changes the interpretation of\n PMP rules so that `pmpcfg.L` marks rules as M-mode-only rather than locked.\n This en", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Smepmp" + }, + { + "chunk_id": "chunk_7edf3776", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Smmpm.yaml", + "section": "Smmpm", + "text": "Extension Smmpm (Pointer masking for M-mode) [ratified] A machine-level extension that provides pointer masking for M-mode.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Smmpm" + }, + { + "chunk_id": "chunk_c7958e77", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Smnpm.yaml", + "section": "Smnpm", + "text": "Extension Smnpm (Pointer masking for next privilege level less than M-mode) [ratified] A machine-level extension that provides pointer masking for the next lower privilege mode\n(S/HS if S-mode is implemented, or U-mode otherwise).", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Smnpm" + }, + { + "chunk_id": "chunk_9c0c1f53", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Smrnmi.yaml", + "section": "Smrnmi", + "text": "Extension Smrnmi (Resumable Non-Maskable Interrupts) [ratified] The base machine-level architecture supports only unresumable non-maskable interrupts (UNMIs),\nwhere the NMI jumps to a handler in machine mode, overwriting the current `mepc` and `mcause`\nregister values.\nIf the hart had been executing machine-mode code in a trap handler, the previous values in `mepc`\nand `mcause` would not be recoverable and so execution is not generally resumable.\n\nThe `Smrnmi`", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Smrnmi" + }, + { + "chunk_id": "chunk_e6cfddbe", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Smstateen.yaml", + "section": "Smstateen", + "text": "Extension Smstateen (Machine-mode view of the state-enable extension) [ratified] Machine-mode view of the state-enable extension. The Smstateen\nextension specification comprises the `mstateen*`, `sstateen*`,\nand `hstateen*` CSRs and their functionality.\n\nNOTE: The Smstateen extension specification is an M-mode extension as\nit includes M-mode features, but the supervisor-mode visible\ncomponents of the extension are named as the Ssstateen extension. Only\nSsstateen is mandated i", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Smstateen" + }, + { + "chunk_id": "chunk_07ade54b", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Ssaia.yaml", + "section": "Ssaia", + "text": "Extension Ssaia (Advanced Interrupt Architecture, S-mode extension) [ratified] Advanced Interrupt Architecture, S-mode extension", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Ssaia" + }, + { + "chunk_id": "chunk_1c11ee31", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Ssccfg.yaml", + "section": "Ssccfg", + "text": "Extension Ssccfg (Supervisor-mode counter configuration) [ratified] Supervisor-mode counter configuration", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Ssccfg" + }, + { + "chunk_id": "chunk_7dedbe6d", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Ssccptr.yaml", + "section": "Ssccptr", + "text": "Extension Ssccptr (Cacheable and coherent main memory page table reads) [ratified] Main memory regions with both the cacheability and coherence PMAs must support hardware page-table reads.\n\n[NOTE]\nThis extension was ratified with the RVA20 profiles.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Ssccptr" + }, + { + "chunk_id": "chunk_d06888d3", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Sscofpmf.yaml", + "section": "Sscofpmf", + "text": "Extension Sscofpmf (Counter Overflow and Privilege Mode Filtering) [ratified] Counter Overflow and Privilege Mode Filtering", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Sscofpmf" + }, + { + "chunk_id": "chunk_9f047fe6", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Sscounterenw.yaml", + "section": "Sscounterenw", + "text": "Extension Sscounterenw (Support writeable enables for any supported counter) [ratified] For any hpmcounter that is not read-only zero, the corresponding bit in `scounteren` must be writable.\n\n[NOTE]\nThis extension was ratified with the RVA22 profiles.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Sscounterenw" + }, + { + "chunk_id": "chunk_bb8d79ae", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Sscsrind.yaml", + "section": "Sscsrind", + "text": "Extension Sscsrind (Supervisor-mode Indirect CSR Access) [ratified] Smcsrind/Sscsrind is an ISA extension that extends the indirect CSR access mechanism originally defined as\npart of the Smaia/Ssaia extensions, in order to make it available for use by other extensions without creating\nan unnecessary dependence on Smaia/Ssaia.\n\nThis extension confers two benefits:\n\nIt provides a means to access an array of registers via CSRs without requiring allocation of large ch", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Sscsrind" + }, + { + "chunk_id": "chunk_aed102ac", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Ssctr.yaml", + "section": "Ssctr", + "text": "Extension Ssctr (Control Transfer Records) [ratified] The supervisor view of `Smctr`.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Ssctr" + }, + { + "chunk_id": "chunk_f351fa2c", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Ssdbltrp.yaml", + "section": "Ssdbltrp", + "text": "Extension Ssdbltrp (Double trap for supervisor mode) [ratified] The Ssdbltrp extension addresses a double trap in privilege modes lower than M.\nIt enables HS-mode to invoke a critical error handler in a virtual machine on a double trap in VS-mode.\nIt also allows M-mode to invoke a critical error handler in the OS/Hypervisor on a double trap in S/HS-mode.\n\nThe Ssdbltrp extension adds the `menvcfg.DTE` and the `sstatus.SDT` fields.\nIf the hypervisor extension is", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Ssdbltrp" + }, + { + "chunk_id": "chunk_6c657dfc", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Ssnpm.yaml", + "section": "Ssnpm", + "text": "Extension Ssnpm (Pointer masking for next privilege level less than S-mode) [ratified] A supervisor-level extension that provides pointer masking for the next lower privilege mode (U-mode),\nand for VS-modes and VU-modes if the H extension is present.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Ssnpm" + }, + { + "chunk_id": "chunk_59fec707", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Sspm.yaml", + "section": "Sspm", + "text": "Extension Sspm (Pointer masking available in supervisor mode) [ratified] Indicates that there is pointer-masking support available in supervisor mode,\nwith some facility provided in the application execution environment to control pointer masking.\n\nThis extension describes an execution environment but has no bearing on hardware implementations.\nIt is intended to be used in profile specifications where a Supervisor profile\ncan only reference Supervisor level pointer mas", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Sspm" + }, + { + "chunk_id": "chunk_b0940ddb", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Ssqosid.yaml", + "section": "Ssqosid", + "text": "Extension Ssqosid (Quality-of-Service Identifiers) [ratified] Quality of Service (QoS) is defined as the minimal end-to-end performance guaranteed in advance by a service level agreement (SLA) to a workload.\nPerformance metrics might include measures such as instructions per cycle (IPC), latency of service, etc.\n\nWhen multiple workloads execute concurrently on modern processors—equipped with large core counts, multiple cache hierarchies, and multiple memory\n", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Ssqosid" + }, + { + "chunk_id": "chunk_7a1011be", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Ssstateen.yaml", + "section": "Ssstateen", + "text": "Extension Ssstateen (Supervisor-mode view of the state-enable extension) [ratified] Supervisor-mode view of the state-enable extension. The\nsupervisor-mode (`sstateen0-3`) and hypervisor-mode (`hstateen0-3`)\nstate-enable registers must be provided.\n\nNOTE: The Smstateen extension specification is an M-mode extension as\nit includes M-mode features, but the supervisor-mode visible\ncomponents of the extension are named as the Ssstateen extension. Only\nSsstateen is mandated in the R", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Ssstateen" + }, + { + "chunk_id": "chunk_e646c293", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Ssstrict.yaml", + "section": "Ssstrict", + "text": "Extension Ssstrict (Unimplemented reserved encodings trap and no non-conforming extensions) [ratified] No non-conforming extensions are present. Attempts to\nexecute unimplemented opcodes or access unimplemented CSRs in the\nstandard or reserved encoding spaces raises an illegal instruction\nexception that results in a contained trap to the supervisor-mode\ntrap handler.\n\n[NOTE]\nSsstrict does not prescribe behavior for the custom encoding\nspaces or CSRs.\n\n[NOTE]\nSsstrict definition applies to the exec", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Ssstrict" + }, + { + "chunk_id": "chunk_e0498dde", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Sstc.yaml", + "section": "Sstc", + "text": "Extension Sstc (Supervisor-mode timer interrupts) [ratified] Supervisor-mode timer interrupts", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Sstc" + }, + { + "chunk_id": "chunk_952a4338", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Sstvala.yaml", + "section": "Sstvala", + "text": "Extension Sstvala (Supervisor Trap Value provides all needed values) [ratified] `stval` must be written with the faulting virtual address for load, store,\nand instruction page-fault, access-fault, and misaligned exceptions,\nand for breakpoint exceptions other than those caused by execution of the\n`ebreak` or `c.ebreak instructions.\n\nFor virtual-instruction and illegal-instruction exceptions,\n`stval` must be written with the faulting instruction.\n\n[NOTE]\nThis extension was rat", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Sstvala" + }, + { + "chunk_id": "chunk_618a0b51", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Sstvecd.yaml", + "section": "Sstvecd", + "text": "Extension Sstvecd (Direct exception vectoring) [ratified] `stvec.MODE` must be capable of holding the value 0 (Direct).\nWhen `stvec.MODE`=Direct, `stvec.BASE` must be capable of holding any valid\nfour-byte-aligned address.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Sstvecd" + }, + { + "chunk_id": "chunk_b6c24c33", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Sstvecv.yaml", + "section": "Sstvecv", + "text": "Extension Sstvecv (Vectored exception handling) [ratified] `stvec.MODE` must be capable of holding the value 1 (Vectored).\nWhen `stvec.MODE`=Vectored, interrupts set `pc` to `stvec.BASE + 4 * cause`,\nallowing each interrupt source to have its own entry point.\nSynchronous exceptions still use the base address regardless of the mode.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Sstvecv" + }, + { + "chunk_id": "chunk_198d4e7e", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Ssu32xl.yaml", + "section": "Ssu32xl", + "text": "Extension Ssu32xl (32-bit UXLEN) [ratified] `sstatus.UXL` must be capable of holding the value 1 (i.e., UXLEN=32 must be supported).\n\nThis allows U-mode to run 32-bit code on a 64-bit machine by setting `sstatus.UXL` to 1.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Ssu32xl" + }, + { + "chunk_id": "chunk_b7082470", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Ssu64xl.yaml", + "section": "Ssu64xl", + "text": "Extension Ssu64xl (64-bit UXLEN) [ratified] `sstatus.UXL` must be capable of holding the value 2 (i.e., UXLEN=64 must be supported).\n\n[NOTE]\nThis extension is defined by RVA22.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Ssu64xl" + }, + { + "chunk_id": "chunk_bb0038a2", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Ssube.yaml", + "section": "Ssube", + "text": "Extension Ssube (Big-endian User Mode) [ratified] `sstatus.UBE` must be capable of holding the value 1 (i.e., big-endian user mode must be supported).\n\nWhen `sstatus.UBE` is set to 1, data accesses in U-mode use big-endian byte ordering.\nInstructions are always fetched as little-endian regardless of this setting.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Ssube" + }, + { + "chunk_id": "chunk_b51909fd", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Supm.yaml", + "section": "Supm", + "text": "Extension Supm (Pointer masking available in user mode) [ratified] Indicates that there is pointer-masking support available in user mode,\nwith some facility provided in the application execution environment to control pointer masking.\n\nThis extension describes an execution environment but has no bearing on hardware implementations.\nIt is intended to be used in profile specifications where a User profile\ncan only reference User level pointer masking functionality", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Supm" + }, + { + "chunk_id": "chunk_db63588b", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Sv32.yaml", + "section": "Sv32", + "text": "Extension Sv32 (32-bit virtual address translation (3 level)) [ratified] 32-bit virtual address translation (3 level)", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Sv32" + }, + { + "chunk_id": "chunk_64f86e27", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Sv39.yaml", + "section": "Sv39", + "text": "Extension Sv39 (39-bit virtual address translation (3 level)) [ratified] 39-bit virtual address translation (3 level)", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Sv39" + }, + { + "chunk_id": "chunk_ab69c7ac", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Sv48.yaml", + "section": "Sv48", + "text": "Extension Sv48 (48-bit virtual address translation (4 level)) [ratified] 48-bit virtual address translation (4 level)", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Sv48" + }, + { + "chunk_id": "chunk_94631fb6", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Sv57.yaml", + "section": "Sv57", + "text": "Extension Sv57 (57-bit virtual address translation (5 level)) [ratified] 57-bit virtual address translation (5 level)", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Sv57" + }, + { + "chunk_id": "chunk_c99f324c", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Svade.yaml", + "section": "Svade", + "text": "Extension Svade (Exception on PTE A/D Bits) [ratified] The Svade extension indicates that hardware does *not* update the A/D bits of a page table\nduring a page walk. Rather, encountering a PTE with the A bit clear or the D bit clear when\nan operation is a write will cause a Page Fault.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Svade" + }, + { + "chunk_id": "chunk_01695785", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Svadu.yaml", + "section": "Svadu", + "text": "Extension Svadu (Hardware Updating of PTE A/D Bits) [ratified] The Svadu extension adds support and CSR controls for hardware updating of PTE\nA/D bits. The A and D bits are managed by these extensions as follows:\n\n* When a virtual page is accessed and the A bit is clear, the PTE is updated to\n set the A bit. When the virtual page is written and the D bit is clear, the\n PTE is updated to set the D bit. When G-stage address translation is in use\n and is not", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Svadu" + }, + { + "chunk_id": "chunk_27972989", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Svbare.yaml", + "section": "Svbare", + "text": "Extension Svbare (Bare virtual addressing) [ratified] This extension mandates that the `satp` mode Bare must\nbe supported.\n\n[NOTE]\nThis extension was ratified as part of the RVA22 profile.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Svbare" + }, + { + "chunk_id": "chunk_7ffbbede", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Svinval.yaml", + "section": "Svinval", + "text": "Extension Svinval (Fine-grained address-translation cache invalidation) [ratified] The `Svinval` extension splits `sfence.vma`, `hfence.vma`, and `hfence.gvma` instructions into\nfiner-grained invalidation and ordering operations that can be more efficiently batched or\npipelined on certain classes of high-performance implementation.\n\nThe `sinval.vma` instruction invalidates any address-translation cache entries that an\n`sfence.vma` instruction with the same values of rs1 and rs2 ", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Svinval" + }, + { + "chunk_id": "chunk_04d23c6d", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Svnapot.yaml", + "section": "Svnapot", + "text": "Extension Svnapot (Naturally Aligned Power-of-Two Translation Contiguity) [ratified] In Sv39, Sv48, and Sv57, when a PTE has N=1, the PTE represents a\ntranslation that is part of a range of contiguous virtual-to-physical\ntranslations with the same values for PTE bits 5-0. Such ranges must be\nof a naturally aligned power-of-2 (NAPOT) granularity larger than the\nbase page size.\n\nThe Svnapot extension depends on Sv39.\n\n[[ptenapot]]\n.Page table entry encodings when __pte__.N=1\n[%autow", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Svnapot" + }, + { + "chunk_id": "chunk_245ae64f", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Svpbmt.yaml", + "section": "Svpbmt", + "text": "Extension Svpbmt (Page-based memory types) [ratified] This extension mandates that the `satp` mode Bare must\nbe supported.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Svpbmt" + }, + { + "chunk_id": "chunk_e7e842b2", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Svrsw60t59b.yaml", + "section": "Svrsw60t59b", + "text": "Extension Svrsw60t59b (PTE Reserved-for-Software Bits 60-59) [ratified] == \"Svrsw60t59b\" Extension for PTE Reserved-for-Software Bits 60-59, Version 1.0\n\nIf the Svrsw60t59b extension is implemented, then bits 60-59 of the page table\nentries (PTEs) are reserved for use by supervisor software and are ignored by\nthe implementation.\n\nIf the Hypervisor (H) extension is also implemented, then bits 60-59 of the\nG-stage PTEs are reserved for use by supervisor software and are", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Svrsw60t59b" + }, + { + "chunk_id": "chunk_5bb395f3", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Svvptc.yaml", + "section": "Svvptc", + "text": "Extension Svvptc (Guarantee visibility of PTE transitions from invalid to valid) [ratified] When the Svvptc extension is implemented, explicit stores by a hart that update\nthe Valid bit of leaf and/or non-leaf PTEs from 0 to 1 and are visible to a hart\nwill eventually become visible within a bounded timeframe to subsequent implicit\naccesses by that hart to such PTEs.\n\n[NOTE]\nSvvptc relieves an operating system from executing certain memory-management\ninstructions, such as `SFENCE.VMA` or", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Svvptc" + }, + { + "chunk_id": "chunk_553d40fd", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/U.yaml", + "section": "U", + "text": "Extension U (User-mode privilege level) [ratified] User-mode privilege level is supported by an implementation if the U extension is present.\nNote that the RISC-V ISA doesn't formally define a U extension and it is only discussed in the Privileged ISA manual.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "U" + }, + { + "chunk_id": "chunk_8cfadc41", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/V.yaml", + "section": "V", + "text": "Extension V (Vector Operations) [ratified] General support for data-parallel execution.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "V" + }, + { + "chunk_id": "chunk_2fb9c7e8", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Za128rs.yaml", + "section": "Za128rs", + "text": "Extension Za128rs (Reservation set size of at most 128 bytes) [ratified] Reservation sets must be contiguous, naturally aligned, and at most 128 bytes in size.\n\n[NOTE]\nThis extension was ratified as part of the RVA20 profile.\n\n[NOTE]\nThe minimum reservation set size is effectively determined by the size of atomic accesses in\nthe A extension.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Za128rs" + }, + { + "chunk_id": "chunk_bec838d4", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Za64rs.yaml", + "section": "Za64rs", + "text": "Extension Za64rs (Reservation set size of at most 64 bytes) [ratified] Reservation sets must be contiguous, naturally aligned, and at most 64 bytes in size.\n\n[NOTE]\nThis extension was ratified as part of the RVA22 profile.\n\n[NOTE]\nThe minimum reservation set size is effectively determined by the size of atomic accesses in\nthe A extension.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Za64rs" + }, + { + "chunk_id": "chunk_74d97c7e", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zaamo.yaml", + "section": "Zaamo", + "text": "Extension Zaamo (Load-acquire/Store-release atomic instructions) [ratified] The atomic memory operation (AMO) instructions perform read-modify-write\noperations for multiprocessor synchronization and are encoded with an\nR-type instruction format. These AMO instructions atomically load a data\nvalue from the address in _rs1_, place the value into register _rd_,\napply a binary operator to the loaded value and the original value in\n_rs2_, then store the result back to the orig", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zaamo" + }, + { + "chunk_id": "chunk_365aa84e", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zabha.yaml", + "section": "Zabha", + "text": "Extension Zabha (Byte and Halfword Atomic Memory Operations) [ratified] Adds byte and halfword atomic memory operations to the RISC-V Unprivileged ISA.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zabha" + }, + { + "chunk_id": "chunk_8d9c3c7f", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zacas.yaml", + "section": "Zacas", + "text": "Extension Zacas (Atomic Compare-and-Swap (CAS) Instructions) [ratified] Adds Word/Doubleword/Quadword compare-and-swap instructions.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zacas" + }, + { + "chunk_id": "chunk_bf3f2712", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zalasr.yaml", + "section": "Zalasr", + "text": "Extension Zalasr (Atomic Load-Acquire and Store-Release) [ratified] load-acquire and store-release instructions.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zalasr" + }, + { + "chunk_id": "chunk_baac236c", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zalrsc.yaml", + "section": "Zalrsc", + "text": "Extension Zalrsc (Load-Reserved/Store-Conditional Instructions) [ratified] Complex atomic memory operations on a single memory word or doubleword\nare performed with the load-reserved (LR) and store-conditional (SC)\ninstructions. `LR.W` loads a word from the address in _rs1_, places the\nsign-extended value in _rd_, and registers a _reservation set_--a set of\nbytes that subsumes the bytes in the addressed word. `SC.W` conditionally\nwrites a word in _rs2_ to the address in ", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zalrsc" + }, + { + "chunk_id": "chunk_5b963b7d", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zama16b.yaml", + "section": "Zama16b", + "text": "Extension Zama16b (Misaligned load/store/AMO within aligned 16-byte boundaries are atomic) [ratified] Misaligned loads, stores, and AMOs to main memory regions that do not cross a\nnaturally-aligned 16-byte boundary are atomic.\n\n[NOTE]\nZama16b is a new RVA23 profile-defined extension that represents\nthe presence of the new Misaligned Atomicity Granule feature added in\nSm1p13. The extension will be added to the PMA section of the\nprivileged architecture manual.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zama16b" + }, + { + "chunk_id": "chunk_a18bfd0e", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zawrs.yaml", + "section": "Zawrs", + "text": "Extension Zawrs (Wait-on-Reservation-Set Instructions) [ratified] The `Zawrs` extension defines a pair of instructions to be used in polling loops that allows a\ncore to enter a low-power state and wait on a store to a memory location.\nWaiting for a memory location to be updated is a common pattern in many use cases such as:\n\n* Contenders for a lock waiting for the lock variable to be updated.\n* Consumers waiting on the tail of an empty queue for the producer to ", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zawrs" + }, + { + "chunk_id": "chunk_82848918", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zba.yaml", + "section": "Zba", + "text": "Extension Zba (Address generation) [ratified] The Zba instructions can be used to accelerate the generation of addresses that index into\narrays of basic types (halfword, word, doubleword) using both unsigned word-sized and\nXLEN-sized indices: a shifted index is added to a base address.\n\nThe shift and add instructions do a left shift of 1, 2, or 3 because these are commonly found\nin real-world code and because they can be implemented with a mi", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zba" + }, + { + "chunk_id": "chunk_9d4e2644", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zbb.yaml", + "section": "Zbb", + "text": "Extension Zbb (Basic bit-manipulation) [ratified] Basic bit-manipulation", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zbb" + }, + { + "chunk_id": "chunk_aec5bec1", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zbc.yaml", + "section": "Zbc", + "text": "Extension Zbc (Carry-less multiplication) [ratified] Carry-less multiplication is the multiplication in the polynomial ring over GF(2).", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zbc" + }, + { + "chunk_id": "chunk_5bb1547e", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zbkb.yaml", + "section": "Zbkb", + "text": "Extension Zbkb (Bit-manipulation for Cryptography) [ratified] This extension contains instructions essential for implementing common operations in cryptographic workloads.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zbkb" + }, + { + "chunk_id": "chunk_889f6f84", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zbkc.yaml", + "section": "Zbkc", + "text": "Extension Zbkc (Carry-less multiplication for Cryptography) [ratified] Carry-less multiplication is the multiplication in the polynomial ring over GF(2).\nThis is a critical operation in some cryptographic workloads, particularly the AES-GCM\nauthenticated encryption scheme.\nThis extension provides only the instructions needed to efficiently implement the GHASH operation,\nwhich is part of this workload.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zbkc" + }, + { + "chunk_id": "chunk_48e283e1", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zbkx.yaml", + "section": "Zbkx", + "text": "Extension Zbkx (Crossbar permutations) [ratified] Adds instructions to implement a \"lookup table\" for 4 and 8 bit elements inside the general purpose\nregisters.\n\nThese instructions are useful for expressing N-bit to N-bit boolean operations, and implementing\ncryptographic code with secret dependent memory accesses (particularly SBoxes) such that the\nexecution latency does not depend on the (secret) data being operated on.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zbkx" + }, + { + "chunk_id": "chunk_04ee3c8c", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zbs.yaml", + "section": "Zbs", + "text": "Extension Zbs (Single-bit instructions) [ratified] The single-bit instructions provide a mechanism to set, clear, invert, or extract a single bit\nin a register. The bit is specified by its index", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zbs" + }, + { + "chunk_id": "chunk_18155642", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zca.yaml", + "section": "Zca", + "text": "Extension Zca (C instructions excluding floating-point loads/stores) [ratified] The Zca extension is added as way to refer to instructions in the `C` extension that do not\ninclude the floating-point loads and stores.\n\nTherefore it excludes all 16-bit floating point loads and stores:\n`c.flw`, `c.flwsp`, `c.fsw`, `c.fswsp`, `c.fld`, `c.fldsp`, `c.fsd`, `c.fsdsp`.\n\n[NOTE]\nThe 'C' extension only includes `F`/`D` instructions when `D` and `F` are also specified.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zca" + }, + { + "chunk_id": "chunk_419a6e3f", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zcb.yaml", + "section": "Zcb", + "text": "Extension Zcb (Simple code-size saving instructions) [ratified] Zcb has simple code-size saving instructions which are easy to implement on all CPUs.\nAll proposed encodings are currently reserved for all architectures, and have no conflicts with any existing extensions.\n\nThe Zcb extension depends on the Zca extension.\n\nAs shown on the individual instruction pages, many of the instructions in Zcb depend upon another extension being implemented.\nFor example, c.m", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zcb" + }, + { + "chunk_id": "chunk_4e655c27", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zcd.yaml", + "section": "Zcd", + "text": "Extension Zcd (Compressed double-precision floating-point loads/stores) [ratified] Zcd is the existing set of compressed double precision floating point loads and stores:\n`c.fld`, `c.fldsp`, `c.fsd`, `c.fsdsp`.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zcd" + }, + { + "chunk_id": "chunk_0542953d", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zce.yaml", + "section": "Zce", + "text": "Extension Zce (Compressed instructions for microcontrollers) [ratified] The Zce extension is intended to be used for microcontrollers, and includes all relevant Zc\nextensions.\n\n* Specifying `Zce` on RV32 without `F` includes `Zca`, `Zcb`, `Zcmp`, `Zcmt`\n* Specifying `Zce` on RV32 with `F` includes `Zca`, `Zcb`, `Zcmp`, `Zcmt` and `Zcf`\n* Specifying `Zce` on RV64 always includes `Zca`, `Zcb`, `Zcmp`, `Zcmt`\n* `Zcf` doesn't exist for RV64\n\nTherefore common ISA strings c", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zce" + }, + { + "chunk_id": "chunk_916e6ac4", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zcf.yaml", + "section": "Zcf", + "text": "Extension Zcf (Compressed single-precision floating-point loads/stores) [ratified] Zcf is the existing set of compressed single precision floating point loads and stores (RV32 only):\n`c.flw`, `c.flwsp`, `c.fsw`, `c.fswsp`.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zcf" + }, + { + "chunk_id": "chunk_a1a669c9", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zclsd.yaml", + "section": "Zclsd", + "text": "Extension Zclsd (Compressed Load/Store Pair for RV32) [ratified] This extension adds load and store instructions using register pairs. It does so by reusing existing instruction encodings which are RV64-only. The specification defines 16-bit encodings.\nLoad and store instructions will use the same definition of even-odd pairs as defined by the Zdinx extension.\nThe extension improves static code density, by replacing two separate load or store instructions with ", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zclsd" + }, + { + "chunk_id": "chunk_3e133842", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zcmop.yaml", + "section": "Zcmop", + "text": "Extension Zcmop (Compressed May-Be-Operations) [ratified] The \"Zcmop\" extension, which defines eight 16-bit MOP\ninstructions named C.MOP.__n__, where __n__ is an odd integer between 1 and\n15, inclusive. C.MOP.__n__ is encoded in the reserved encoding space\ncorresponding to C.LUI x__n__, 0, as shown in <>.\nUnlike the MOPs defined in the Zimop extension, the C.MOP.__n__ instructions\nare defined to _not_ write any register.\nTheir encoding allows", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zcmop" + }, + { + "chunk_id": "chunk_9858a870", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zcmp.yaml", + "section": "Zcmp", + "text": "Extension Zcmp (Complex PUSH/POP and Double Move) [ratified] The Zcmp extension is a set of instructions which may be executed as a series of existing 32-bit RISC-V instructions.\n\nThis extension reuses some encodings from _c.fsdsp_. Therefore it is _incompatible_ with <>,\n which is included when C and D extensions are both present.\n\nNOTE: Zcmp is primarily targeted at embedded class CPUs due to implementation complexity. Additionally, it is not compat", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zcmp" + }, + { + "chunk_id": "chunk_6be43eb1", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zcmt.yaml", + "section": "Zcmt", + "text": "Extension Zcmt (Table Jump) [ratified] Zcmt adds the table jump instructions and also adds the jvt CSR. The jvt CSR requires a\nstate enable if Smstateen is implemented. See <> for details.\n\nThis extension reuses some encodings from _c.fsdsp_. Therefore it is _incompatible_ with <>,\n which is included when C and D extensions are both present.\n\nNOTE: Zcmt is primarily targeted at embedded class CPUs due to implementation ", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zcmt" + }, + { + "chunk_id": "chunk_962ad533", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zdinx.yaml", + "section": "Zdinx", + "text": "Extension Zdinx (Double-precision floating-point instructions using integer registers) [ratified] The Zdinx extension provides analogous double-precision floating-point instructions.\n\nThe Zdinx extension adds all of the instructions that the D extension adds, except for the transfer\ninstructions FLD, FSD, FMV.D.X, FMV.X.D, C.FLD[SP], and C.FSD[SP].\n\nThe Zdinx variants of these D-extension instructions have the same semantics,\nexcept that whenever such an instruction would have accessed an f re", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zdinx" + }, + { + "chunk_id": "chunk_b16c642b", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zfa.yaml", + "section": "Zfa", + "text": "Extension Zfa (Additional Floating-Point Instructions) [ratified] `Zfa` adds instructions for immediate loads, IEEE 754-2019 minimum and maximum operations,\nround-to-integer operations, and quiet floating-point comparisons.\nFor RV32D, the `Zfa` extension also adds instructions to transfer double-precision floating-point\nvalues to and from integer registers, and for RV64Q, it adds analogous instructions for\nquad-precision floating-point values.\nThe `Zfa` extensio", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zfa" + }, + { + "chunk_id": "chunk_66fdc17a", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zfbfmin.yaml", + "section": "Zfbfmin", + "text": "Extension Zfbfmin (Scalar BF16 Converts) [ratified] The minimal set of instructions needed to enable scalar support of the BF16 format.\nIt enables BF16 as an interchange format as it provides conversion between BF16 values and\nFP32 values.\n\nThis extension depends upon the single-precision floating-point extension `F`,\nand the `flh`, `fsh`, `fmv.x.h`, and `fmv.h.x` instructions as defined in the `Zfh` extension.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zfbfmin" + }, + { + "chunk_id": "chunk_d68757f5", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zfh.yaml", + "section": "Zfh", + "text": "Extension Zfh (Half-precision floating point) [ratified] 16-bit half-precision binary floating-point instructions compliant with the IEEE 754-2008\narithmetic standard.\nThe `Zfh` extension depends on the single-precision floating-point extension, `F`.\nThe NaN-boxing scheme is extended to allow a half-precision value to be NaN-boxed inside a\nsingle-precision value (which may be recursively NaN-boxed inside a double- or quad-precision\nvalue when the D or Q", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zfh" + }, + { + "chunk_id": "chunk_13b4ea9e", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zfhmin.yaml", + "section": "Zfhmin", + "text": "Extension Zfhmin (Minimal half-precision floating-point) [ratified] `Zfhmin` provides\nminimal support for 16-bit half-precision binary floating-point\ninstructions. The Zfhmin extension is a subset of the `Zfh` extension,\nconsisting only of data transfer and conversion instructions. Like `Zfh`,\nthe `Zfhmin` extension depends on the single-precision floating-point\nextension, `F`. The expectation is that `Zfhmin` software primarily uses the\nhalf-precision format for ", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zfhmin" + }, + { + "chunk_id": "chunk_d3ec4beb", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zfinx.yaml", + "section": "Zfinx", + "text": "Extension Zfinx (Single-precision floating-point instructions using integer registers) [ratified] The \"Zfinx\" extension (pronounced \"z-f-in-x\") provides instructions similar to those in the\nstandard floating-point F extension for single-precision floating-point instructions but\nwhich operate on the x registers instead of the f registers.\n\n[NOTE]\n--\nThe F extension uses separate f registers for floating-point computation,\nto reduce register pressure and simplify the provision of register-file p", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zfinx" + }, + { + "chunk_id": "chunk_5a53bbaa", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zhinx.yaml", + "section": "Zhinx", + "text": "Extension Zhinx (Half-precision floating-point instructions using integer registers) [ratified] The Zhinx extension provides analogous half-precision floating-point instructions. The Zhinx extension\ndepends upon the Zfinx extension.\nThe Zhinx extension adds all of the instructions that the Zfh extension adds, except for the transfer\ninstructions FLH, FSH, FMV.H.X, and FMV.X.H.\nThe Zhinx variants of these Zfh-extension instructions have the same semantics, except that whenever\nsuch an instruc", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zhinx" + }, + { + "chunk_id": "chunk_2d9e331f", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zhinxmin.yaml", + "section": "Zhinxmin", + "text": "Extension Zhinxmin (Minimal support for half-precision floating-point instructions using integer registers) [ratified] The Zhinxmin extension provides minimal support for 16-bit half-precision floating-point\ninstructions that operate on the x registers.\nThe Zhinxmin extension depends upon the Zfinx extension.\n\nThe Zhinxmin extension includes the following instructions from the Zhinx extension:\nFCVT.S.H and FCVT.H.S. If the Zdinx extension is present, the FCVT.D.H and FCVT.H.D instructions\nare also included.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zhinxmin" + }, + { + "chunk_id": "chunk_c572dff4", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zic64b.yaml", + "section": "Zic64b", + "text": "Extension Zic64b (64-byte cache blocks) [ratified] Cache blocks must be 64 bytes in size, naturally aligned in the address space.\n\n[NOTE]\nThis extension was ratified with the RVA20 profiles.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zic64b" + }, + { + "chunk_id": "chunk_b271e1ba", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zicbom.yaml", + "section": "Zicbom", + "text": "Extension Zicbom (Cache-block management instructions) [ratified] Cache-block management instructions", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zicbom" + }, + { + "chunk_id": "chunk_d451494e", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zicbop.yaml", + "section": "Zicbop", + "text": "Extension Zicbop (Cache-block prefetch) [ratified] Cache-block prefetch instructions", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zicbop" + }, + { + "chunk_id": "chunk_8beb8227", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zicboz.yaml", + "section": "Zicboz", + "text": "Extension Zicboz (Cache-block zero instruction) [ratified] Cache-block zero instruction", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zicboz" + }, + { + "chunk_id": "chunk_b3de18b8", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Ziccamoa.yaml", + "section": "Ziccamoa", + "text": "Extension Ziccamoa (Main memory supports all atomics in A extension) [ratified] Main memory regions with both the cacheability and coherence PMAs must support AMOArithmetic.\n\n[NOTE]\nThis extension was ratified as part of the RVA20 profile.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Ziccamoa" + }, + { + "chunk_id": "chunk_2d21b9eb", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Ziccamoc.yaml", + "section": "Ziccamoc", + "text": "Extension Ziccamoc (Cacheable and coherent PMAs provide `AMOCASQ` level PMA support) [ratified] Main memory regions with both the cacheability and coherence PMAs\nmust provide `AMOCASQ` level PMA support.\n\n[NOTE]\nZiccamoc is a new RVA23 profile-defined extension that ensures\nCompare and Swap instructions are properly supported in main memory\nregions. The extension will be added to the PMA section of the\nprivileged architecture manual.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Ziccamoc" + }, + { + "chunk_id": "chunk_ff5d8e78", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Ziccif.yaml", + "section": "Ziccif", + "text": "Extension Ziccif (Main memory supports instruction fetch with atomicity requirement) [ratified] Main memory regions with both the cacheability and coherence PMAs must support instruction\nfetch, and any instruction fetches of naturally aligned power-of-2 sizes up to\nmin(ILEN,XLEN) (i.e., 32 bits for RVA22) are atomic.\n\n[NOTE]\nThis extension was ratified as part of the RVA20 profile.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Ziccif" + }, + { + "chunk_id": "chunk_de86fef5", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zicclsm.yaml", + "section": "Zicclsm", + "text": "Extension Zicclsm (Main memory supports misaligned loads/stores) [ratified] Misaligned loads and stores to main memory regions with both the cacheability and coherence\nPMAs must be supported.\n\n[NOTE]\nThis extension was ratified as part of the RVA20 profile.\n\n[NOTE]\nThis requires misaligned support for all regular load and store instructions (including\nscalar and vector) but not AMOs or other specialized forms of memory access.\nEven though mandated, misaligned loads and st", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zicclsm" + }, + { + "chunk_id": "chunk_b4c1b1b0", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Ziccrse.yaml", + "section": "Ziccrse", + "text": "Extension Ziccrse (Main memory supports forward progress on LR/SC sequences) [ratified] Main memory regions with both the cacheability and coherence PMAs must support RsrvEventual.\n\n[NOTE]\nThis extension was ratified as part of the RVA20 profile.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Ziccrse" + }, + { + "chunk_id": "chunk_f3538b37", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zicfilp.yaml", + "section": "Zicfilp", + "text": "Extension Zicfilp (Landing Pad) [ratified] TODO", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zicfilp" + }, + { + "chunk_id": "chunk_e5113782", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zicfiss.yaml", + "section": "Zicfiss", + "text": "Extension Zicfiss (Shadow Stack) [ratified] TODO", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zicfiss" + }, + { + "chunk_id": "chunk_cdb90189", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zicntr.yaml", + "section": "Zicntr", + "text": "Extension Zicntr (Base Counters and Timers) [ratified] The CYCLE, TIME, and INSTRET counters, which have dedicated functions\n(cycle count, real-time clock, and instructions retired, respectively).", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zicntr" + }, + { + "chunk_id": "chunk_94cee11d", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zicond.yaml", + "section": "Zicond", + "text": "Extension Zicond (Integer Conditional Operations) [ratified] The \"Conditional\" operations extension provides a simple solution that provides most of the\nbenefit and all of the flexibility one would desire to support conditional arithmetic and\nconditional-select/move operations, while remaining true to the RISC-V design philosophy.\nThe instructions follow the format for R-type instructions with 3 operands (_i.e._, 2 source\noperands and 1 destination operand)", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zicond" + }, + { + "chunk_id": "chunk_cd13f39d", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zicsr.yaml", + "section": "Zicsr", + "text": "Extension Zicsr (Control and status register instructions) [ratified] Control and status register instructions", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zicsr" + }, + { + "chunk_id": "chunk_5cef9998", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zifencei.yaml", + "section": "Zifencei", + "text": "Extension Zifencei (Instruction fence) [ratified] This chapter defines the \"Zifencei\" extension, which includes the\nFENCE.I instruction that provides explicit synchronization between\nwrites to instruction memory and instruction fetches on the same hart.\nCurrently, this instruction is the only standard mechanism to ensure\nthat stores visible to a hart will also be visible to its instruction\nfetches.\n(((store instruction word, not included)))\n\n[NOT", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zifencei" + }, + { + "chunk_id": "chunk_c1411b6b", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zihintntl.yaml", + "section": "Zihintntl", + "text": "Extension Zihintntl (Non-Temporal Locality Hints) [ratified] The NTL instructions are HINTs that indicate that the explicit memory\naccesses of the immediately subsequent instruction (henceforth \"target\ninstruction\") exhibit poor temporal locality of reference. The NTL\ninstructions do not change architectural state, nor do they alter the\narchitecturally visible effects of the target instruction. Four variants\nare provided:\n\nThe NTL.P1 instruction indicates t", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zihintntl" + }, + { + "chunk_id": "chunk_2a6f1cb4", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zihintpause.yaml", + "section": "Zihintpause", + "text": "Extension Zihintpause (Pause Hint) [ratified] The PAUSE instruction is a HINT that indicates the current hart's rate\nof instruction retirement should be temporarily reduced or paused. The\nduration of its effect must be bounded and may be zero.\n(((PAUSE, HINT)))\n(((HINT, PAUSE)))\n\n[NOTE]\n====\nSoftware can use the PAUSE instruction to reduce energy consumption\nwhile executing spin-wait code sequences. Multithreaded cores might\ntemporarily relin", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zihintpause" + }, + { + "chunk_id": "chunk_dd0b3c01", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zihpm.yaml", + "section": "Zihpm", + "text": "Extension Zihpm (Hardware Performance Counters) [ratified] Hardware performance counters", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zihpm" + }, + { + "chunk_id": "chunk_d64211e1", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zilsd.yaml", + "section": "Zilsd", + "text": "Extension Zilsd (Load/Store Pair for RV32) [ratified] This specification adds load and store instructions using register pairs. It does so by reusing existing instruction encodings which are RV64-only. The specification defines 32-bit encodings.\nLoad and store instructions will use the same definition of even-odd pairs as defined by the Zdinx extension.\nThe extension improves static code density, by replacing two separate load or store instructions w", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zilsd" + }, + { + "chunk_id": "chunk_27c66c64", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zimop.yaml", + "section": "Zimop", + "text": "Extension Zimop (May-Be-Operations) [ratified] The \"Zimop\" extension introduces the concept of\ninstructions that _may be operations_ (MOPs). MOPs are initially defined to\nsimply write zero to `x[rd]`, but are designed to be redefined by later\nextensions to perform some other action.\nThe Zimop extension defines an encoding space for 40 MOPs.\n\n[NOTE]\n====\nIt is sometimes desirable to define instruction-set extensions whose\ninstructions, rather ", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zimop" + }, + { + "chunk_id": "chunk_bfdd1dc3", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zk.yaml", + "section": "Zk", + "text": "Extension Zk (Standard Cryptography Extensions) [ratified] This extension is shorthand for the following set of other extensions:\n\n* `Zkn`\n* `Zkr`\n* `Zkt`", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zk" + }, + { + "chunk_id": "chunk_8760e334", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zkn.yaml", + "section": "Zkn", + "text": "Extension Zkn (NIST Algorithm Suite) [ratified] This extension is shorthand for the following set of other extensions:\n\n* `Zbkb`\n* `Zbkc`\n* `Zbkx`\n* `Zkne`\n* `Zknd`\n* `Zknh`", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zkn" + }, + { + "chunk_id": "chunk_87d23586", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zknd.yaml", + "section": "Zknd", + "text": "Extension Zknd (NIST Suite: AES Decryption) [ratified] Instructions for accelerating the decryption and key-schedule functions of the AES block cipher.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zknd" + }, + { + "chunk_id": "chunk_d6138655", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zkne.yaml", + "section": "Zkne", + "text": "Extension Zkne (NIST Suite: AES Encryption) [ratified] Instructions for accelerating the encryption and key-schedule functions of the AES block cipher.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zkne" + }, + { + "chunk_id": "chunk_9d51c1c0", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zknh.yaml", + "section": "Zknh", + "text": "Extension Zknh (NIST Suite: SHA2 Hashing) [ratified] Instructions for accelerating the SHA2 family of cryptographic hash functions.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zknh" + }, + { + "chunk_id": "chunk_fc38f485", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zkr.yaml", + "section": "Zkr", + "text": "Extension Zkr (Entropy Source) [ratified] Defines the `seed` CSR.\nThis CSR provides up to 16 physical entropy bits that can be used to seed cryptographic random bit generators.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zkr" + }, + { + "chunk_id": "chunk_3a88e9ab", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zks.yaml", + "section": "Zks", + "text": "Extension Zks (ShangMi Algorithm Suite) [ratified] This extension is shorthand for the following set of other extensions:\n\n* `Zbkb`\n* `Zbkc`\n* `Zbkx`\n* `Zksed`\n* `Zksh`", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zks" + }, + { + "chunk_id": "chunk_3b8d5d40", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zksed.yaml", + "section": "Zksed", + "text": "Extension Zksed (ShangMi Suite: SM4 Block Cipher Instructions) [ratified] Instructions for accelerating the SM4 Block Cipher. Note that unlike AES, this cipher uses the\nsame core operation for encryption and decryption, hence there is only one extension for it.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zksed" + }, + { + "chunk_id": "chunk_46ff19e2", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zksh.yaml", + "section": "Zksh", + "text": "Extension Zksh (ShangMi Suite: SM3 Hash Function Instructions) [ratified] Instructions for accelerating the SM3 hash function.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zksh" + }, + { + "chunk_id": "chunk_3e540453", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zkt.yaml", + "section": "Zkt", + "text": "Extension Zkt (Data-independent execution latency) [ratified] The Zkt extension attests that the machine has data-independent execution time for a safe\nsubset of instructions.\nThis property is commonly called \"constant-time\" although should not be taken with that literal\nmeaning.\n\nAll currently proposed cryptographic instructions (scalar `K` extension) are on this list,\ntogether with a set of relevant supporting instructions from `I`, `M`, `C`, and `B` exten", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zkt" + }, + { + "chunk_id": "chunk_c6baaba2", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zmmul.yaml", + "section": "Zmmul", + "text": "Extension Zmmul (Integer multiplication) [ratified] The `Zmmul` extension implements the multiplication subset of the `M` extension.\nIt adds `MUL`, `MULH`, `MULHU`, `MULHSU`, and (for RV64 only) `MULW`.\nThe encodings are identical to those of the corresponding M-extension instructions.\n`M` implies `Zmmul`.\n\n[NOTE]\nThe `Zmmul` extension enables low-cost implementations that require multiplication\noperations but not division. For many microcontroller", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zmmul" + }, + { + "chunk_id": "chunk_876ba3c0", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Ztso.yaml", + "section": "Ztso", + "text": "Extension Ztso (Total Store Ordering) [ratified] The Ztso extension provides Total Store Ordering (TSO) memory consistency semantics\nfor RISC-V systems. This is an optional extension that complements the baseline\nRISC-V Weak Memory Ordering (RVWMO) model by providing stricter memory ordering\nguarantees.\n\nWhen Ztso is implemented, all loads and stores behave as if they have implicit\nacquire and release semantics, respectively. This provides a fam", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Ztso" + }, + { + "chunk_id": "chunk_5ef38ffe", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zvbb.yaml", + "section": "Zvbb", + "text": "Extension Zvbb (Vector Basic Bit-manipulation) [ratified] Vector basic bit-manipulation instructions.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zvbb" + }, + { + "chunk_id": "chunk_f0728ea4", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zvbc.yaml", + "section": "Zvbc", + "text": "Extension Zvbc (Vector Carryless Multiplication) [ratified] General purpose carryless multiplication instructions which are commonly used in cryptography and\nhashing (e.g., Elliptic curve cryptography, GHASH, CRC).\n\nThese instructions are only defined for SEW=64.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zvbc" + }, + { + "chunk_id": "chunk_793d81f9", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zve32f.yaml", + "section": "Zve32f", + "text": "Extension Zve32f (Vector Extension for Minimal Single-Precision Embedded Floating-Point) [ratified] The Zve32f extension adds single-precision vector floating-point support to\nthe Zve32x base embedded vector extension. The maximum element width (ELEN)\nremains 32 bits.\n\nZve32f includes all functionality of Zve32x plus:\n\n* Single-precision vector floating-point instructions\n* Vector floating-point reductions\n* Vector floating-point compare and classify instructions\n\nZve32f requires the F (single-p", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zve32f" + }, + { + "chunk_id": "chunk_32a51716", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zve32x.yaml", + "section": "Zve32x", + "text": "Extension Zve32x (Vector Extension for Minimal Vector Register Length of 32 Bits) [ratified] The Zve32x extension provides support for vector integer operations with a\nmaximum element width (ELEN) of 32 bits. This is a base embedded vector\nextension that excludes floating-point vector operations.\n\nZve32x includes:\n\n* All vector load and store instructions\n* All vector integer instructions\n* All vector fixed-point arithmetic instructions\n* All vector mask instructions\n* All vector permutat", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zve32x" + }, + { + "chunk_id": "chunk_f9d7bf47", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zve64d.yaml", + "section": "Zve64d", + "text": "Extension Zve64d (Vector Extension for Minimal Double-Precision Embedded Floating-Point) [ratified] The Zve64d extension adds double-precision vector floating-point support to\nthe Zve64f embedded vector extension. The maximum element width (ELEN) is\n64 bits, supporting 64-bit integer and 64-bit double-precision floating-point\nelements.\n\nZve64d includes all functionality of Zve64f plus:\n\n* Double-precision vector floating-point instructions\n* Double-precision vector floating-point reductions\n* Ve", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zve64d" + }, + { + "chunk_id": "chunk_c942ae15", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zve64f.yaml", + "section": "Zve64f", + "text": "Extension Zve64f (Vector Extension for Minimal Single-Precision Embedded Floating-Point) [ratified] The Zve64f extension adds single-precision vector floating-point support to\nthe Zve64x base embedded vector extension. The maximum element width (ELEN)\nis 64 bits, supporting both 64-bit integer and 32-bit floating-point elements.\n\nZve64f includes all functionality of Zve64x and Zve32f plus:\n\n* Single-precision vector floating-point instructions with 64-bit integer support\n* Support for widening f", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zve64f" + }, + { + "chunk_id": "chunk_afe9810b", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zve64x.yaml", + "section": "Zve64x", + "text": "Extension Zve64x (Vector Extension for Minimal Vector Register Length of 64 Bits) [ratified] The Zve64x extension provides support for vector integer operations with a\nmaximum element width (ELEN) of 64 bits. This is a base embedded vector\nextension that excludes floating-point vector operations.\n\nZve64x includes all functionality of Zve32x plus:\n\n* Support for 64-bit integer vector elements (SEW=64)\n* 64-bit vector load and store instructions\n* All vector integer instructions operating o", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zve64x" + }, + { + "chunk_id": "chunk_5f154878", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zvfbfmin.yaml", + "section": "Zvfbfmin", + "text": "Extension Zvfbfmin (Vector BF16 Converts) [ratified] This extension provides the minimal set of instructions needed to enable vector support of the\nBF16 format.\nIt enables BF16 as an interchange format as it provides conversion between BF16 values and FP32 values.\n\nThis extension depends upon either the `V` extension or the `Zve32f` embedded vector extension.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zvfbfmin" + }, + { + "chunk_id": "chunk_e738a71e", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zvfbfwma.yaml", + "section": "Zvfbfwma", + "text": "Extension Zvfbfwma (Vector BF16 widening mul-add) [ratified] This extension provides a vector widening BF16 mul-add instruction that accumulates into FP32.\n\nThis extension depends upon the `Zvfbfmin` extension and the `Zfbfmin` extension.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zvfbfwma" + }, + { + "chunk_id": "chunk_b074ff7d", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zvfh.yaml", + "section": "Zvfh", + "text": "Extension Zvfh (Vector Extension for Half-Precision Floating-Point) [ratified] This extension provides support for vectors of IEEE 754-2008\nbinary16 values.\nWhen the Zvfh extension is implemented, all instructions in Sections\n<>, <>,\n<>, <>,\n<>, and <>\nbecome defined when SEW=16.\nThe EEW=16 floating-point operands of these instructions use the bi", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zvfh" + }, + { + "chunk_id": "chunk_00763651", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zvfhmin.yaml", + "section": "Zvfhmin", + "text": "Extension Zvfhmin (Vector Extension for Minimal Half-Precision Floating-Point) [ratified] This extension provides minimal support for vectors of IEEE 754-2008\nbinary16 values, adding conversions to and from binary32.\nWhen the Zvfhmin extension is implemented, the `vfwcvt.f.f.v` and\n`vfncvt.f.f.w` instructions become defined when SEW=16.\nThe EEW=16 floating-point operands of these instructions use the binary16\nformat.\n\nThis extension depends on the Zve32f extension.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zvfhmin" + }, + { + "chunk_id": "chunk_8a6eed3b", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zvkb.yaml", + "section": "Zvkb", + "text": "Extension Zvkb (Vector Cryptography Bit-manipulation) [ratified] Vector bit-manipulation instructions that are essential for implementing common cryptographic workloads securely & efficiently.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zvkb" + }, + { + "chunk_id": "chunk_1448f70f", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zvkg.yaml", + "section": "Zvkg", + "text": "Extension Zvkg (Vector GCM/GMAC) [ratified] Instructions to enable the efficient implementation of GHASHH which is used in Galois/Counter Mode\n(GCM) and Galois Message Authentication Code (GMAC).\n\nAll of these instructions work on 128-bit element groups comprised of four 32-bit elements.\n\nTo help avoid side-channel timing attacks, these instructions shall be implemented with data-independent timing.\n\nThe number of element groups to be proce", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zvkg" + }, + { + "chunk_id": "chunk_6a330870", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zvkn.yaml", + "section": "Zvkn", + "text": "Extension Zvkn (NIST Algorithm Suite) [ratified] This extension is shorthand for the following set of other extensions:\n\n* `Zvkned`\n* `Zvknhb`\n* `Zvkb`\n* `Zvkt`", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zvkn" + }, + { + "chunk_id": "chunk_900cdba4", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zvknc.yaml", + "section": "Zvknc", + "text": "Extension Zvknc (NIST Algorithm Suite with carryless multiply) [ratified] This extension is shorthand for the following set of other extensions:\n\n* `Zvkn`\n* `Zvbc`", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zvknc" + }, + { + "chunk_id": "chunk_7f061f5c", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zvkned.yaml", + "section": "Zvkned", + "text": "Extension Zvkned (NIST Suite: Vector AES Block Cipher) [ratified] Instructions for accelerating encryption, decryption and key-schedule functions of the AES block\ncipher as defined in Federal Information Processing Standards Publication 197.\n\nAll of these instructions work on 128-bit element groups comprised of four 32-bit elements.\n\nTo help avoid side-channel timing attacks, these instructions shall be implemented with data-independent timing.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zvkned" + }, + { + "chunk_id": "chunk_5dd272b0", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zvkng.yaml", + "section": "Zvkng", + "text": "Extension Zvkng (NIST Algorithm Suite with GCM) [ratified] This extension is shorthand for the following set of other extensions:\n\n* `Zvkn`\n* `Zvkg`", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zvkng" + }, + { + "chunk_id": "chunk_40714164", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zvknha.yaml", + "section": "Zvknha", + "text": "Extension Zvknha (NIST Suite: Vector SHA-2 Secure Hash (SHA-256)) [ratified] Instructions for accelerating 256-bit SHA-2 as defined in FIPS PUB 180-4 Secure Hash Standard (SHS)", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zvknha" + }, + { + "chunk_id": "chunk_75da99f8", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zvknhb.yaml", + "section": "Zvknhb", + "text": "Extension Zvknhb (NIST Suite: Vector SHA-2 Secure Hash (SHA-256 + SHA-512)) [ratified] Instructions for accelerating 256-bit/512-bit SHA-2 as defined in FIPS PUB 180-4 Secure Hash Standard (SHS)", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zvknhb" + }, + { + "chunk_id": "chunk_454b8ff8", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zvks.yaml", + "section": "Zvks", + "text": "Extension Zvks (ShangMi Algorithm Suite) [ratified] This extension is shorthand for the following set of other extensions:\n\n* `Zvksed`\n* `Zvksh`\n* `Zvkb`\n* `Zvkt`", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zvks" + }, + { + "chunk_id": "chunk_98b8f4c7", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zvksc.yaml", + "section": "Zvksc", + "text": "Extension Zvksc (ShangMi Algorithm Suite with carryless multiplication) [ratified] This extension is shorthand for the following set of other extensions:\n\n* `Zvks`\n* `Zvbc`", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zvksc" + }, + { + "chunk_id": "chunk_fdc71fa1", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zvksed.yaml", + "section": "Zvksed", + "text": "Extension Zvksed (ShangMi Suite: SM4 Block Cipher) [ratified] Instructions for accelerating encryption, decryption and key-schedule functions of the SM4 block cipher.\n\nThe SM4 block cipher is specified in 32907-2016: {SM4} Block Cipher Algorithm (GB/T 32907-2016: SM4 Block Cipher Algorithm, 2016)\n\nThere are other various sources available that describe the SM4 block cipher. While not the final version of the standard, RFC 8998 ShangMi (SM) Cipher Suites for ", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zvksed" + }, + { + "chunk_id": "chunk_1a095a6e", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zvksg.yaml", + "section": "Zvksg", + "text": "Extension Zvksg (ShangMi Algorithm Suite with GCM) [ratified] This extension is shorthand for the following set of other extensions:\n\n* `Zvks`\n* `Zvkg`", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zvksg" + }, + { + "chunk_id": "chunk_09677db3", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zvksh.yaml", + "section": "Zvksh", + "text": "Extension Zvksh (ShangMi Suite: SM3 Secure Hash) [ratified] Instructions for accelerating functions of the SM3 Hash Function.\n\nAll of these instructions work on 256-bit element groups comprised of eight 32-bit elements.\n\nTo help avoid side-channel timing attacks, these instructions shall be implemented with data-independent timing.", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zvksh" + }, + { + "chunk_id": "chunk_5eef5ffa", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zvkt.yaml", + "section": "Zvkt", + "text": "Extension Zvkt (Vector Data-Independent Execution Latency) [ratified] The Zvkt extension requires all implemented instructions from the following list to be executed\nwith data-independent execution latency.\n\nData-independent execution latency (DIEL) applies to all data operands of an instruction, even\nthose that are not a part of the body or that are inactive.\nHowever, DIEL does not apply to other values such as vl, vtype, and the mask (when used to control\nexecutio", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zvkt" + }, + { + "chunk_id": "chunk_a1b5782d", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zvl1024b.yaml", + "section": "Zvl1024b", + "text": "Extension Zvl1024b (Vector register length must be at least 1024 bits) [ratified] The Zvl1024b extension requires the implementation to have a vector register\nlength (VLEN) of at least 1024 bits.\n\nThe Zvl*b extensions are a family of extensions that specify minimum vector\nregister lengths. They allow software to determine the minimum VLEN supported\nby an implementation without needing to probe at runtime.\n\nWith VLEN=1024 and SEW=8 bits, VLMAX is 128 elements (with LMUL=1).", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zvl1024b" + }, + { + "chunk_id": "chunk_323f9d7c", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zvl128b.yaml", + "section": "Zvl128b", + "text": "Extension Zvl128b (Vector register length must be at least 128 bits) [ratified] The Zvl128b extension requires the implementation to have a vector register\nlength (VLEN) of at least 128 bits.\n\nThe Zvl*b extensions are a family of extensions that specify minimum vector\nregister lengths. They allow software to determine the minimum VLEN supported\nby an implementation without needing to probe at runtime.\n\nVLEN=128 is the minimum vector register length required by the full V\nexte", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zvl128b" + }, + { + "chunk_id": "chunk_52ff31ff", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zvl256b.yaml", + "section": "Zvl256b", + "text": "Extension Zvl256b (Vector register length must be at least 256 bits) [ratified] The Zvl256b extension requires the implementation to have a vector register\nlength (VLEN) of at least 256 bits.\n\nThe Zvl*b extensions are a family of extensions that specify minimum vector\nregister lengths. They allow software to determine the minimum VLEN supported\nby an implementation without needing to probe at runtime.\n\nWith VLEN=256 and SEW=8 bits, VLMAX is 32 elements (with LMUL=1).", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zvl256b" + }, + { + "chunk_id": "chunk_dae273b7", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zvl32b.yaml", + "section": "Zvl32b", + "text": "Extension Zvl32b (Vector register length must be at least 32 bits) [ratified] The Zvl32b extension requires the implementation to have a vector register\nlength (VLEN) of at least 32 bits.\n\nThe Zvl*b extensions are a family of extensions that specify minimum vector\nregister lengths. They allow software to determine the minimum VLEN supported\nby an implementation without needing to probe at runtime.\n\nWith VLEN=32 and the smallest supported SEW of 8 bits, the minimum VLMAX\nis ", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zvl32b" + }, + { + "chunk_id": "chunk_a5d42bbe", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zvl512b.yaml", + "section": "Zvl512b", + "text": "Extension Zvl512b (Vector register length must be at least 512 bits) [ratified] The Zvl512b extension requires the implementation to have a vector register\nlength (VLEN) of at least 512 bits.\n\nThe Zvl*b extensions are a family of extensions that specify minimum vector\nregister lengths. They allow software to determine the minimum VLEN supported\nby an implementation without needing to probe at runtime.\n\nWith VLEN=512 and SEW=8 bits, VLMAX is 64 elements (with LMUL=1).", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zvl512b" + }, + { + "chunk_id": "chunk_35574511", + "source": "udb_ext", + "source_file": "/Users/cybertron/MyProjects/LFX/riscv-unified-db/spec/std/isa/ext/Zvl64b.yaml", + "section": "Zvl64b", + "text": "Extension Zvl64b (Vector register length must be at least 64 bits) [ratified] The Zvl64b extension requires the implementation to have a vector register\nlength (VLEN) of at least 64 bits.\n\nThe Zvl*b extensions are a family of extensions that specify minimum vector\nregister lengths. They allow software to determine the minimum VLEN supported\nby an implementation without needing to probe at runtime.\n\nWith VLEN=64 and the smallest supported SEW of 8 bits, the minimum VLMAX\nis ", + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": "Zvl64b" + } +] \ No newline at end of file diff --git a/tools/llm-extraction/main.py b/tools/llm-extraction/main.py new file mode 100644 index 0000000000..7b84cd63af --- /dev/null +++ b/tools/llm-extraction/main.py @@ -0,0 +1,114 @@ +#!/usr/bin/env python3 +""" +Purpose: + CLI entry point for the RISC-V UDB LLM-extraction pipeline. + Parses subcommand and flags; delegates all logic to pipeline_runner.py. + +Pipeline Stage: + entry point (orchestrates all stages) + +Inputs: + - CLI arguments: subcommand, --mode, --dry-run + +Outputs: + - (delegates to pipeline_runner.run()) + +Core Responsibilities: + - Define and parse CLI arguments via argparse + - Import pipeline_runner with sys.path fallback for non-venv usage + - Forward subcommand + mode to pipeline_runner.run() + +Key Assumptions: + - Run from llm-extraction/ with the .venv activated + - pipeline_runner.py is in the same directory + +Failure Modes: + - parser.error() if pipeline_runner cannot be imported + - sys.exit(0) on --dry-run (not a failure) + +Notes: + - All real work is in pipeline_runner.py; this file stays thin by design + +Usage: + python main.py all + python main.py embed --mode analysis + python main.py process + python main.py ingest + python main.py export +""" + +import argparse +import sys + + +def _build_parser() -> argparse.ArgumentParser: + parser = argparse.ArgumentParser( + prog="main", + description="RISC-V UDB LLM Extraction Pipeline", + formatter_class=argparse.RawDescriptionHelpFormatter, + epilog=( + "Subcommands\n" + "-----------\n" + " ingest — Clone / update riscv-isa-manual (git shallow clone)\n" + " process — Parse AsciiDoc → filtered chunk JSON + CSV\n" + " embed — Build ChromaDB vector index from parameter YAML schemas\n" + " export — Write dependency graph, report, and analysis corpus\n" + " all — Run ingest → process → embed → export\n" + ), + ) + + parser.add_argument( + "subcommand", + choices=["ingest", "process", "embed", "export", "all"], + help="Pipeline stage to run.", + ) + parser.add_argument( + "--mode", + choices=["rag", "analysis"], + default="rag", + help=( + "Embedding mode for the 'embed' and 'all' subcommands.\n" + " rag = retrieval index only (default)\n" + " analysis = retrieval index + full analysis corpus JSON" + ), + ) + parser.add_argument( + "--dry-run", + action="store_true", + help="Print what would be executed without actually running anything.", + ) + + return parser + + +# --------------------------------------------------------------------------- + + +def main() -> None: + parser = _build_parser() + args = parser.parse_args() + + if args.dry_run: + print(f"[dry-run] Would execute subcommand: {args.subcommand!r} (mode={args.mode})") + sys.exit(0) + + # pipeline_runner is a sibling file; fall back to explicit path insert if needed. + try: + from pipeline_runner import run + except ModuleNotFoundError: + import os + sys.path.insert(0, os.path.join(os.path.dirname(__file__), "chunk")) + try: + from pipeline_runner import run + except ModuleNotFoundError as exc: + parser.error( + f"Could not import pipeline_runner: {exc}\n" + "Make sure you are running from the llm-extraction/ directory " + "or that the virtual environment is activated." + ) + + run(subcommand=args.subcommand, mode=args.mode) + + +if __name__ == "__main__": + main() diff --git a/tools/llm-extraction/pipeline/__init__.py b/tools/llm-extraction/pipeline/__init__.py new file mode 100644 index 0000000000..25905c2b84 --- /dev/null +++ b/tools/llm-extraction/pipeline/__init__.py @@ -0,0 +1 @@ +"""pipeline/ — RISC-V UDB extraction pipeline sub-packages.""" diff --git a/tools/llm-extraction/pipeline/export/__init__.py b/tools/llm-extraction/pipeline/export/__init__.py new file mode 100644 index 0000000000..e69de29bb2 diff --git a/tools/llm-extraction/pipeline/export/reporter.py b/tools/llm-extraction/pipeline/export/reporter.py new file mode 100644 index 0000000000..4bb522f119 --- /dev/null +++ b/tools/llm-extraction/pipeline/export/reporter.py @@ -0,0 +1,270 @@ +""" +Purpose: + Generate three isolated reports for the RISC-V UDB extraction pipeline: + 1. AsciiDoc Chunker Report (from detailed filter stats + raw chunks) + 2. UDB YAML Chunker Report (from the UDB chunks) + 3. Overall Summary Report (combines timing and high-level outcomes) + +Pipeline Stage: + export + +Inputs: + - data/output/adoc_report_data.json + - data/output/parameter_dataset.csv (via Pandas) + - data/output/udb_chunks.json (via Pandas) + - _TIMINGS + +Outputs: + - data/evaluation/report_adoc_chunker.md + - data/evaluation/report_udb_chunker.md + - data/evaluation/report_overall_summary.md +""" + +from __future__ import annotations + +import json +from datetime import datetime, timezone +from pathlib import Path +from typing import Any +import pandas as pd + +import sys +_EXPORT_DIR = Path(__file__).parent.resolve() +_TOOL_DIR = _EXPORT_DIR.parent.parent +if str(_TOOL_DIR) not in sys.path: + sys.path.insert(0, str(_TOOL_DIR)) + +from configs.config import OUTPUT_DIR, DATA_DIR, logger # noqa: E402 + +EVAL_DIR = DATA_DIR / "evaluation" + + +# --------------------------------------------------------------------------- +# Data Loading (Pandas) +# --------------------------------------------------------------------------- + +def _load_adoc_dataframe() -> pd.DataFrame: + """Loads the AsciiDoc parameter dataset CSV into Pandas.""" + csv_path = OUTPUT_DIR / "parameter_dataset.csv" + if not csv_path.exists(): + return pd.DataFrame() + try: + df = pd.read_csv(csv_path) + return df.fillna("") + except Exception as e: + logger.warning(f"Error loading {csv_path}: {e}") + return pd.DataFrame() + + +def _load_udb_dataframe() -> pd.DataFrame: + """Loads the UDB JSON chunks into Pandas.""" + json_path = OUTPUT_DIR / "udb_chunks.json" + if not json_path.exists(): + return pd.DataFrame() + try: + with open(json_path, encoding="utf-8") as f: + data = json.load(f) + df = pd.DataFrame(data) + return df.fillna("") + except Exception as e: + logger.warning(f"Error loading {json_path}: {e}") + return pd.DataFrame() + + +# --------------------------------------------------------------------------- +# Render Helpers +# --------------------------------------------------------------------------- + +def _render_parameter_list(df: pd.DataFrame, title: str) -> str: + """Renders a Pandas DataFrame of parameters into a Markdown table (sampled for brevity).""" + if df.empty: + return f"\n## {title}\n> No parameters found.\n" + + # Select columns if they exist + cols = [] + if "section" in df.columns: cols.append("section") + if "parameter_class" in df.columns: cols.append("parameter_class") + if "text" in df.columns: cols.append("text") + if "confidence" in df.columns: cols.append("confidence") + + sub_df = df[cols].copy() + + # ── Sample up to 10 items randomly per parameter_class ── + if "parameter_class" in sub_df.columns: + sampled_dfs = [] + for p_class, group in sub_df.groupby("parameter_class"): + sampled_dfs.append(group.sample(n=min(len(group), 10), random_state=42)) + if sampled_dfs: + sub_df = pd.concat(sampled_dfs, ignore_index=True) + else: + sub_df = sub_df.sample(n=min(len(sub_df), 10), random_state=42) + + # Text truncation to avoid breaking markdown limits per row + if "text" in sub_df.columns: + sub_df["text"] = sub_df["text"].str.replace("\n", " ").str.slice(0, 200) + "..." + if "section" in sub_df.columns: + sub_df["section"] = sub_df["section"].str.replace("\n", " ") + + lines = [f"\n## {title}\n"] + lines.append("> _Showing a randomized sample (up to 10 chunks per parameter class)._\n") + lines.append("| " + " | ".join(sub_df.columns).title() + " |") + lines.append("|" + "|".join(["---"] * len(sub_df.columns)) + "|") + + for _, row in sub_df.iterrows(): + row_strs = [str(col_val).replace('|', '\\|') for col_val in row] + lines.append("| " + " | ".join(row_strs) + " |") + + return "\n".join(lines) + "\n" + + +# --------------------------------------------------------------------------- +# 1. AsciiDoc Chunker Report +# --------------------------------------------------------------------------- + +def _write_adoc_report(report_data: dict, df: pd.DataFrame, out_path: Path) -> None: + if not report_data and df.empty: + out_path.write_text("> ⚠️ AsciiDoc report data not found.\n") + return + + lines = ["# AsciiDoc Spec Chunker Full Analysis Report\n"] + + g = report_data.get("global", {}) + lines.append("## Executive Summary") + lines.append(f"- Total Files: {g.get('total_files', 0)}") + lines.append(f"- Processed Files: {g.get('processed_files', 0)}") + lines.append(f"- Skipped Files: {g.get('skipped_files', 0)}") + lines.append(f"- Total Raw Chunks: {g.get('total_raw_chunks', 0)}") + lines.append(f"- Final Chunks (in dataset): {len(df) if not df.empty else g.get('total_final_chunks', 0)}") + lines.append(f"- Reduction: {g.get('reduction_percent', 0)}%\n") + + # Filter rules logic + filters = report_data.get("filters", {}) + lines.append("\n## Filter Breakdown (Why chunks were dropped)") + sorted_drops = sorted(filters.get("reasons", {}).items(), key=lambda i: i[1], reverse=True) + for k, v in sorted_drops: + lines.append(f"- {k}: {v}") + + # Use Pandas for distribution analysis + if not df.empty: + lines.append("\n## Confidence Distribution") + conf_counts = df["confidence"].value_counts() + for k, v in conf_counts.items(): + lines.append(f"- {k}: {v} ({(v/len(df)*100):.1f}%)") + + lines.append("\n## Parameter Classification Summary") + cls_counts = df["parameter_class"].value_counts() + for k, v in cls_counts.items(): + lines.append(f"- {k}: {v} ({(v/len(df)*100):.1f}%)") + + lines.append("\n## Parameter Type Summary") + type_counts = df["parameter_type"].value_counts() + for k, v in type_counts.items(): + lines.append(f"- {k}: {v} ({(v/len(df)*100):.1f}%)") + + lines.append("\n## Per-file Chunk Selection Analysis") + lines.append("| S.No | File | Raw Candidates | Selected Final Chunks | Dropped |") + lines.append("|---|---|---|---|---|") + files_info = report_data.get("files", {}) + sorted_files = sorted(files_info.items(), key=lambda i: i[1].get("dropped", 0), reverse=True) + for i, (f, d) in enumerate(sorted_files, 1): + lines.append(f"| {i} | `{f}` | {d.get('raw_chunks', 0)} | {d.get('final_chunks', 0)} | {d.get('dropped', 0)} |") + + lines.append(_render_parameter_list(df, "Complete Extracted Parameters List (AsciiDoc)")) + + out_path.write_text("\n".join(lines), encoding="utf-8") + + +# --------------------------------------------------------------------------- +# 2. UDB YAML Chunker Report +# --------------------------------------------------------------------------- + +def _write_udb_report(df: pd.DataFrame, out_path: Path) -> dict: + if df.empty: + out_path.write_text("> ⚠️ UDB chunks not found.\n") + return {"total": 0} + + lines = ["# UDB YAML Chunker Analysis Report\n"] + lines.append("## Executive Summary") + lines.append(f"- Total UDB Chunks Produced: {len(df)}") + + lines.append("\n## Source Breakdown") + for k, v in df["source"].value_counts().items(): + lines.append(f"- {k}: {v}") + + lines.append("\n## Parameter Class Summary") + for k, v in df["parameter_class"].value_counts().items(): + lines.append(f"- {k}: {v}") + + lines.append("\n## Parameter Type Summary") + for k, v in df["parameter_type"].value_counts().items(): + lines.append(f"- {k}: {v}") + + lines.append("\n## Per-file Chunk Generation Analysis") + lines.append("| S.No | Source File | Chunks Generated |") + lines.append("|---|---|---|") + if "source_file" in df.columns: + file_counts = df["source_file"].value_counts() + for i, (f, count) in enumerate(file_counts.items(), 1): + lines.append(f"| {i} | `{f}` | {count} |") + else: + lines.append("> _Source file information not found in dataset._\n") + + # Append full list of parameters + lines.append(_render_parameter_list(df, "Complete Extracted Parameters List (UDB)")) + + out_path.write_text("\n".join(lines), encoding="utf-8") + return {"total": len(df), "src_dist": df["source"].value_counts().to_dict()} + + +# --------------------------------------------------------------------------- +# 3. Overall Pipeline Report +# --------------------------------------------------------------------------- + +def _write_overall_report(timings: dict[str, float], adoc_data: dict, udb_stats: dict, out_path: Path) -> None: + lines = ["# Overall Pipeline Summary Report\n"] + ts = datetime.now(timezone.utc).strftime("%Y-%m-%d %H:%M:%S UTC") + lines.append(f"> Execution completed at {ts}\n") + + lines.append("## Phase Execution Timings") + if not timings: + lines.append("_No timing data available (likely run sequentially by the user)._") + else: + lines.append("| Phase | Duration |") + lines.append("|---|---|") + total = 0.0 + for phase, secs in timings.items(): + total += secs + lines.append(f"| `{phase}` | {secs:.1f}s |") + lines.append(f"| **Total** | **{total:.1f}s** |") + + out_path.write_text("\n".join(lines), encoding="utf-8") + + +# --------------------------------------------------------------------------- +# Main Entry Point +# --------------------------------------------------------------------------- + +def generate_markdown_report(timings: dict[str, float] | None = None) -> list[Path]: + EVAL_DIR.mkdir(parents=True, exist_ok=True) + + adoc_out = EVAL_DIR / "report_adoc_chunker.md" + udb_out = EVAL_DIR / "report_udb_chunker.md" + + # AsciiDoc legacy stats (for drops) + adoc_json = OUTPUT_DIR / "adoc_report_data.json" + adoc_data = {} + if adoc_json.exists(): + try: + adoc_data = json.loads(adoc_json.read_text(encoding="utf-8")) + except Exception: + pass + + # Load data via pandas + df_adoc = _load_adoc_dataframe() + df_udb = _load_udb_dataframe() + + # Generate + _write_adoc_report(adoc_data, df_adoc, adoc_out) + udb_stats = _write_udb_report(df_udb, udb_out) + + return [adoc_out, udb_out] diff --git a/tools/llm-extraction/pipeline/ingest/__init__.py b/tools/llm-extraction/pipeline/ingest/__init__.py new file mode 100644 index 0000000000..643551fb80 --- /dev/null +++ b/tools/llm-extraction/pipeline/ingest/__init__.py @@ -0,0 +1,8 @@ +""" +pipeline/ingest/ — Ingestion-stage chunkers. + +Exports +------- + chunker_adoc — AsciiDoc ISA-manual chunker (AsciiDocChunker) + chunker_udb — UDB YAML/JSON schema chunker (UDBChunker, stub) +""" diff --git a/tools/llm-extraction/pipeline/ingest/chunker_adoc.py b/tools/llm-extraction/pipeline/ingest/chunker_adoc.py new file mode 100644 index 0000000000..f1d8dc79ff --- /dev/null +++ b/tools/llm-extraction/pipeline/ingest/chunker_adoc.py @@ -0,0 +1,847 @@ +""" +Purpose: + Parses RISC-V ISA manual AsciiDoc source files and extracts normative + parameter-defining sentences as structured chunk records for downstream + classification and embedding. + +Pipeline Stage: + ingest + +Inputs: + - data/riscv-isa-manual/src/**/*.adoc (shallow-cloned ISA manual) + - configs/schema_rules.yaml (filter keyword lists, loaded at import) + - configs/taxonomy.yaml (file-classification rules, loaded at import) + +Outputs: + - data/output/raw_chunks/.json (pre-filter sentences, one JSON per .adoc) + - data/output/chunks_repo.json (post-filter combined chunks) + - data/output/parameter_dataset.csv (flat CSV for downstream annotation) + - data/output/filter_stats.md (per-file + global filter-statistics report) + +Core Responsibilities: + - Load keyword vocabulary from schema_rules.yaml (not hardcoded frozensets) + - Load file-classification rules from taxonomy.yaml + - Clean AsciiDoc markup and split text into atomic normative sentences + - Filter noise, narrative, computation descriptions, and soft rationale + - Score confidence and classify parameter class + type per chunk + - Persist raw (pre-filter) and final (post-filter) chunk outputs + +Key Assumptions: + - ISA manual is at ISA_MANUAL_DIR or will be cloned by _ensure_repo() + - All .adoc source files live under src/ inside the manual repository + - All keyword strings in schema_rules.yaml are already lowercased + +Failure Modes: + - Empty chunks_repo.json if ISA manual is missing or src/ layout changes + - KeyError / silent under-extraction if schema_rules.yaml keys are renamed + - Over-extraction if noise_patterns list in schema_rules.yaml is too short + +Notes: + - Filtering is ordered cheapest-first: structural validity → semantic checks + - flush_paragraphs() is a proper instance method (not a closure) for testability + - split_conditions() is public so conditional-splitting logic can be tested alone +""" + +from __future__ import annotations + +import csv +import json +import re +import subprocess +import sys +from pathlib import Path +from typing import Optional + +from tqdm import tqdm + +# ── sys.path bootstrap ────────────────────────────────────────────────────── +# Ensure llm-extraction/ and llm-extraction/chunk/ are importable when this +# module is used standalone (e.g. during testing or direct execution). + +_INGEST_DIR = Path(__file__).parent.resolve() # pipeline/ingest/ +_PIPELINE_DIR = _INGEST_DIR.parent # pipeline/ +_TOOL_DIR = _PIPELINE_DIR.parent # llm-extraction/ +_CHUNK_DIR = _TOOL_DIR / "chunk" + +for _p in (str(_TOOL_DIR), str(_CHUNK_DIR)): + if _p not in sys.path: + sys.path.insert(0, _p) + +_CONFIGS_DIR = _TOOL_DIR / "configs" +_SCHEMA_RULES_PATH = _CONFIGS_DIR / "schema_rules.yaml" +_TAXONOMY_PATH = _CONFIGS_DIR / "taxonomy.yaml" + +from configs.config import ( # noqa: E402 + ISA_MANUAL_DIR, + ISA_MANUAL_REPO_URL, + OUTPUT_DIR, + CHUNKS_REPO_PATH, + FILTER_STATS_PATH, + PARAMETER_DATASET_PATH, + RAW_CHUNKS_DIR, + logger, +) +from pipeline.utils import chunk_id, normalize_text # noqa: E402 + +from pipeline.process.classifier import ( + _RULES, + classify_confidence, + classify_parameter_class, + classify_parameter_type, + contains_any, + has_access_vocab, + has_any_modal, + has_condition_vocab, + has_csr_vocab, + has_explicit_bit_rule, + has_field_vocab, + has_numeric_constraint, + has_strong_modal, + is_narrative, + is_pure_description, + should_keep, +) + + + + + +def _load_taxonomy() -> dict: + """ + Read configs/taxonomy.yaml and return the file-classification look-ups + needed by classify_file(). + """ + import yaml as _yaml + + with open(_TAXONOMY_PATH, "r", encoding="utf-8") as fh: + data = _yaml.safe_load(fh) + + cats = data.get("ignore_file_categories", {}) + return { + "ignored_exact": frozenset(cats.get("ignored_exact", [])), + "formal_files": tuple(cats.get("formal_files", [])), + "profile_prefix": cats.get("profile_prefix", "profiles/"), + "doc_files": tuple(cats.get("doc_files", [])), + } + + +_TAXONOMY = _load_taxonomy() + +_IGNORED_FILES_EXACT: frozenset[str] = _TAXONOMY["ignored_exact"] +_FORMAL_FILES: tuple[str, ...] = _TAXONOMY["formal_files"] +_PROFILE_PREFIX: str = _TAXONOMY["profile_prefix"] +_DOC_FILES: tuple[str, ...] = _TAXONOMY["doc_files"] + + +# Regexes stay in Python for safety; patterns are documented in schema_rules.yaml. + +_RE_NOTE_BLOCK = re.compile(r'\[NOTE\]\s*\n====.*?====\s*\n', re.DOTALL) +_RE_EQUAL_RUNS = re.compile(r'={2,}') +_RE_ANCHOR = re.compile(r'\[\[.*?\]\]') +_RE_NORM_ATTR = re.compile(r'\[#?norm:[^\]]+\]#?') +_RE_INDEX_TERM = re.compile(r'\(\(\(.*?\)\)\)') +_RE_XREF = re.compile(r'<<[^>]+>>') +_RE_TABLE = re.compile(r'\|===.*?\|===', re.DOTALL) +_RE_PERCENT_ATTR = re.compile(r'\[%.*?\]') +_RE_BLOCK_COMMENT = re.compile(r'/\*.*?\*/', re.DOTALL) +_RE_LIST_BULLET = re.compile(r'^[\*\-]\s+', re.MULTILINE) +_RE_WHITESPACE = re.compile(r'\s+') +_RE_SECTION_HDR = re.compile(r'^(=+)\s+(.+)$') + +# Capital+lowercase lookahead prevents splitting on abbreviations like "e.g. Foo". +_RE_SPLIT_SENT = re.compile(r'(?<=[.;])\s+(?=[A-Z][a-z])') + +# 'The' and 'All' excluded: they inflated raw-chunk counts 2× in earlier runs. +_RE_SPLIT_COND = re.compile(r'(?=\b(?:If|When|Unless|Otherwise)\b)') + +_RE_TAG_PAIR = re.compile(r'<[^>]{1,80}>') + + + + +def classify_file(file_path: str) -> tuple[str, Optional[str]]: + """ + Determine how a source .adoc file should be processed. + + Returns + ------- + (mode, category) where *mode* is one of: + "ignore" — skip entirely + "process" — full normative extraction (main corpus) + "process_formal" — memory-model / formal sections (light mode) + "process_profile" — profile requirement sections + "process_docs" — naming / intro / preface sections + + *category* is the ignored-bucket key used in the filter report, or None + when the file is actively processed into the main corpus. + """ + for name in _IGNORED_FILES_EXACT: + if file_path.endswith(name): + return "ignore", "docs" + + if any(name in file_path for name in _FORMAL_FILES): + return "process_formal", "formal" + if _PROFILE_PREFIX in file_path: + return "process_profile", "profiles" + if any(name in file_path for name in _DOC_FILES): + return "process_docs", "docs" + + return "process", None + + +def _raw_chunk_filename(file_path: str) -> str: + """ + Convert a relative adoc path like ``src/priv/machine.adoc`` into a flat + filename ``src__priv__machine.json`` safe for any filesystem. + """ + return file_path.replace("/", "__").replace(".adoc", ".json") + + +def _split_on_conjunctions(text: str) -> list[str]: + """ + Split a compound constraint sentence on 'and' / 'or'. + + Only fires when *both* parts look like complete constraints (≥ 8 words, + ending with a period). Otherwise the original sentence is returned intact + so no content is silently discarded. + """ + parts = re.split(r'\b(?:and|or)\b', text) + candidates = [ + p.strip() for p in parts + if len(p.strip().split()) >= 8 and p.strip().endswith(".") + ] + return candidates if len(candidates) >= 2 else [text] + + + + +class AsciiDocChunker: + """ + Two-stage AsciiDoc chunker. + + Stage 1 — raw_chunks/ : per-file pre-filter sentences (for debugging/diffing). + Stage 2 — chunks_repo.json / parameter_dataset.csv : final filtered output. + """ + + # ----------------------------------------------------------------------- + # Initialisation + # ----------------------------------------------------------------------- + + def __init__(self, repo_dir: Path) -> None: + self.repo_dir = repo_dir + self.repo_results: list[dict] = [] + self._global_counter: int = 0 + + self.report: dict = { + "global": {}, + "files": {}, + "filters": {"reasons": {}, "rules": []}, + "file_classification": { + "processed": [], + "ignored": {"formal": [], "docs": [], "profiles": []}, + }, + "confidence_distribution": { + "very_high": 0, + "high": 0, + "medium": 0, + "low": 0, + }, + "classification": { + "class": {}, + "type": {}, + "unknown_samples": [], + }, + } + + # ----------------------------------------------------------------------- + # Repository management + # ----------------------------------------------------------------------- + + def _ensure_repo(self) -> None: + if not self.repo_dir.exists(): + logger.info(f"Cloning ISA manual into {self.repo_dir} …") + subprocess.run( + ["git", "clone", "--depth=1", ISA_MANUAL_REPO_URL, str(self.repo_dir)], + check=True, + ) + + def _repo_commit(self) -> str: + result = subprocess.run( + ["git", "rev-parse", "HEAD"], + cwd=self.repo_dir, + capture_output=True, + text=True, + ) + return result.stdout.strip() + + # ----------------------------------------------------------------------- + # Report helpers + # ----------------------------------------------------------------------- + + def _log_rule(self, name: str) -> None: + if name not in self.report["filters"]["rules"]: + self.report["filters"]["rules"].append(name) + + def _drop(self, reason: str) -> None: + self.report["filters"]["reasons"][reason] = ( + self.report["filters"]["reasons"].get(reason, 0) + 1 + ) + + def _record_drop(self, reason: str, file_path: str) -> None: + """Convenience: increment both the global and per-file drop counters.""" + self._drop(reason) + self.report["files"][file_path]["dropped"] += 1 + + # ----------------------------------------------------------------------- + # Text cleaning + # ----------------------------------------------------------------------- + + def _preprocess(self, raw_text: str) -> str: + """Remove AsciiDoc [NOTE] delimited blocks before line processing.""" + self._log_rule("clean_note_blocks: Remove AsciiDoc [NOTE] delimited blocks") + return _RE_NOTE_BLOCK.sub("", raw_text) + + def _clean_text(self, text: str) -> str: + """ + Strip AsciiDoc structural markup, leaving only prose content. + Block-level constructs are removed before inline markup. + """ + self._log_rule("clean_formatting: Strip AsciiDoc structural markup") + text = _RE_EQUAL_RUNS.sub("", text) + text = _RE_ANCHOR.sub("", text) + text = _RE_NORM_ATTR.sub("", text) + text = _RE_INDEX_TERM.sub("", text) + text = _RE_XREF.sub("", text) + text = _RE_TABLE.sub("", text) + text = _RE_PERCENT_ATTR.sub("", text) + text = _RE_BLOCK_COMMENT.sub("", text) + + self._log_rule("clean_artifacts: Strip list bullets and inline symbols") + text = _RE_LIST_BULLET.sub("", text) + text = text.replace("as defined in .", "") + text = text.replace("≠", "!=") + text = text.replace("#", "").replace("_", "") + + return _RE_WHITESPACE.sub(" ", text).strip() + + # ----------------------------------------------------------------------- + # Sentence splitting + # ----------------------------------------------------------------------- + + def split_conditions(self, text: str) -> list[str]: + """ + Sub-split a sentence on genuine logical openers (If / When / Unless / + Otherwise). + + 'The' and 'All' are deliberately absent — splitting on them caused + raw-chunk counts to jump from ~5 k to ~11 k in earlier runs. + """ + self._log_rule("split_logical: Sub-split on conditional openers") + return _RE_SPLIT_COND.split(text) + + def _split_into_atomic_rules(self, text: str) -> list[str]: + """ + Split a cleaned paragraph into atomic normative sentences. + + Strategy + -------- + 1. Split on sentence-ending punctuation (period or semicolon) + followed by whitespace and a Capital+lowercase pair. This + conservatively avoids splitting on abbreviations. + 2. Sub-split each part on genuine logical openers via + ``split_conditions()``. + 3. Attempt conjunction splitting (and/or) only on long sentences + where both halves look like complete constraints. + """ + self._log_rule("split_sentences: Split on sentence boundaries") + parts = _RE_SPLIT_SENT.split(text) + + refined: list[str] = [] + for part in parts: + sub_parts = self.split_conditions(part) + for sp in sub_parts: + sp = sp.strip() + if len(sp) > 25: + self._log_rule( + "split_conjunctions: Decouple and/or compound constraints" + ) + refined.extend(_split_on_conjunctions(sp)) + + return [s for s in refined if len(s.strip()) > 25] + + # ----------------------------------------------------------------------- + # Structural validity + # ----------------------------------------------------------------------- + + def _is_valid_chunk(self, text: str) -> tuple[bool, Optional[str]]: + """ + Hard structural checks — applied first, before any semantic work. + Returns ``(valid, drop_reason)``. + """ + t = text.strip() + + self._log_rule("validate_complete: Reject very short non-terminal fragments") + if not t.endswith(".") and len(t.split()) < 7: + return False, "truncated" + + self._log_rule("validate_bullets: Reject AsciiDoc list elements") + if t.startswith(".") or t.startswith("*"): + return False, "bullet" + if re.match(r'^\d+\.\s', t): + return False, "bullet" + + self._log_rule("validate_refs: Reject broken cross-reference artefacts") + if _RE_TAG_PAIR.search(t): + return False, "formal_reference_tag" + + tl = t.lower() + if tl.startswith("note"): + return False, "note" + if any(p in tl for p in ("see .", "as defined in .", "(see )")): + return False, "broken_reference" + if tl.startswith("synopsis::"): + return False, "synopsis_header" + + return True, None + + # ----------------------------------------------------------------------- + # Semantic filters + # ----------------------------------------------------------------------- + + def _is_diagram_noise(self, text: str) -> bool: + """Reject WaveDrom, table dumps, and design-rationale fragments.""" + t = text.lower() + if contains_any(t, _RULES["noise_patterns"]): + return True + if "+" in text and "register" in t and not has_any_modal(t): + return True + if "[" in text and "]" in text and "bits" in t and not has_any_modal(t): + return True + return False + + def _is_non_normative(self, text: str) -> bool: + """Reject clearly narrative / non-normative sentences.""" + t = text.lower() + if is_narrative(t) and not has_strong_modal(t): + return True + if is_pure_description(t): + return True + return False + + def _is_computation_description(self, text: str) -> bool: + """Reject computation-step descriptions when no modal is present.""" + t = text.lower() + return contains_any(t, _RULES["computation_patterns"]) and not has_any_modal(t) + + def _is_soft_rationale(self, text: str) -> bool: + """Reject design-rationale sentences when no strong modal is present.""" + t = text.lower() + return contains_any(t, _RULES["soft_rationale_patterns"]) and not has_strong_modal(t) + + # ----------------------------------------------------------------------- + # Intent checkers (mode-specific) + # ----------------------------------------------------------------------- + + def _has_normative_intent(self, text: str) -> bool: + """General intent check for the main 'process' mode.""" + t = text.lower() + return ( + has_any_modal(t) + or has_condition_vocab(t) + or has_csr_vocab(t) + or has_field_vocab(t) + or has_access_vocab(t) + or has_explicit_bit_rule(t) + or has_numeric_constraint(text) + or contains_any(t, _RULES["normative_intent_vocab"]) + ) + + def _has_formal_intent(self, text: str) -> bool: + """Memory-model / formal section intent.""" + return contains_any(text.lower(), _RULES["formal_intent"]) + + def _has_profile_intent(self, text: str) -> bool: + """Profile section intent.""" + return contains_any(text.lower(), _RULES["profile_intent"]) + + def _has_doc_intent(self, text: str) -> bool: + """Naming / intro / preface section intent.""" + return contains_any(text.lower(), _RULES["docs_intent"]) + + def _compute_intent(self, mode: str, text: str) -> bool: + dispatch = { + "process_formal": self._has_formal_intent, + "process_profile": self._has_profile_intent, + "process_docs": self._has_doc_intent, + } + return dispatch.get(mode, self._has_normative_intent)(text) + + # ----------------------------------------------------------------------- + # Mode-specific secondary filter + # ----------------------------------------------------------------------- + + def _passes_mode_filter( + self, mode: str, text: str + ) -> tuple[bool, Optional[str]]: + """ + Applied *after* the keep gate. Drops content that passed confidence + scoring but does not belong in the mode's output corpus. + """ + if mode == "process_formal": + if not (self._has_formal_intent(text) or has_any_modal(text.lower())): + return False, "formal_filtered" + + elif mode == "process_profile": + if not self._has_profile_intent(text): + return False, "profile_filtered" + + elif mode == "process_docs": + if not self._has_doc_intent(text): + return False, "doc_filtered" + + return True, None + + + + # ----------------------------------------------------------------------- + # Raw chunk persistence + # ----------------------------------------------------------------------- + + def _save_raw_chunks(self, file_path: str, raw_sentences: list[dict]) -> None: + """ + Write all cleaned sentences for one .adoc file to + ``data/output/raw_chunks/.json`` *before* any semantic + filter runs. Used for debugging, diffing, and offline analysis. + """ + out_path = RAW_CHUNKS_DIR / _raw_chunk_filename(file_path) + payload = { + "source_file": file_path, + "total": len(raw_sentences), + "sentences": raw_sentences, + } + with open(out_path, "w", encoding="utf-8") as fh: + json.dump(payload, fh, indent=2, ensure_ascii=False) + + # ----------------------------------------------------------------------- + # Paragraph flushing (promoted from nested closure in original code) + # ----------------------------------------------------------------------- + + def flush_paragraphs( + self, + paragraphs_buf: list[str], + section_hierarchy: list[str], + start_line: int, + mode: str, + file_path: str, + file_chunks: list[dict], + raw_sentences: list[dict], + ) -> None: + """ + Process all paragraphs accumulated since the last section header. + + Parameters + ---------- + paragraphs_buf : lines collected between the previous header and now + section_hierarchy : current breadcrumb stack, e.g. ["Intro", "CSRs"] + start_line : 1-based line number where this paragraph block starts + mode : processing mode string ("process", "process_formal", …) + file_path : relative path of the source .adoc file (for logging) + file_chunks : accumulator for accepted chunk dicts (mutated in-place) + raw_sentences : accumulator for pre-filter sentence dicts (mutated) + """ + text_block = "\n".join(paragraphs_buf).strip() + if not text_block: + return + + paragraphs = re.split(r"\n\s*\n", text_block) + line_offset = start_line + section_path = " > ".join(section_hierarchy) + + self._log_rule("warl_detection") + self._log_rule("csr_context_boost") + self._log_rule("confidence_classification") + + for para in paragraphs: + p_norm = normalize_text(para) + p_lines_count = para.count("\n") + 1 + + if ( + not p_norm + or p_norm.startswith("//") + or p_norm.startswith("include::") + ): + line_offset += p_lines_count + 1 + continue + + cleaned = self._clean_text(p_norm) + sentences = self._split_into_atomic_rules(cleaned) + + for sentence in sentences: + sentence = sentence.strip() + if not sentence: + continue + + # ── Stage 1: collect raw sentence ────────────────────────── + self.report["files"][file_path]["raw_chunks"] += 1 + raw_sentences.append({ + "text": sentence, + "section": section_path, + "line_range": [line_offset, line_offset + p_lines_count - 1], + }) + + # ── Stage 2: filtering pipeline ──────────────────────────── + + # 1. Hard structural validation + valid, drop_reason = self._is_valid_chunk(sentence) + if not valid: + self._record_drop(drop_reason, file_path) + continue + + tl = sentence.lower() + + # 2. Instruction-description header + if tl.startswith("description"): + self._record_drop("instruction_description", file_path) + continue + + # 3. Diagram / formatting noise + if self._is_diagram_noise(sentence): + self._record_drop("noise", file_path) + continue + + # 4. Non-normative narrative + if self._is_non_normative(sentence): + self._record_drop("non_normative", file_path) + continue + + # 5. Computation description + if self._is_computation_description(sentence): + self._record_drop("computation_description", file_path) + continue + + # 6. Soft rationale / design intent + if self._is_soft_rationale(sentence): + self._record_drop("soft_rationale", file_path) + continue + + # 7. Confidence + intent gate + intent = self._compute_intent(mode, sentence) + keep, confidence = should_keep(sentence, section_path, intent) + self.report["confidence_distribution"][confidence] += 1 + + if not keep: + self._record_drop("low_signal", file_path) + continue + + # 8. Mode-specific secondary filter + passes, drop_reason = self._passes_mode_filter(mode, sentence) + if not passes: + self._record_drop(drop_reason, file_path) + continue + + # ── Accept ────────────────────────────────────────────────── + self._global_counter += 1 + self.report["files"][file_path]["final_chunks"] += 1 + + param_class = classify_parameter_class(sentence) + param_type = classify_parameter_type(sentence) + + cls = self.report["classification"]["class"] + cls[param_class] = cls.get(param_class, 0) + 1 + + typ = self.report["classification"]["type"] + typ[param_type] = typ.get(param_type, 0) + 1 + + if ( + param_class == "unknown" + and len(self.report["classification"]["unknown_samples"]) < 10 + ): + self.report["classification"]["unknown_samples"].append(sentence) + + file_chunks.append({ + "chunk_id": chunk_id(file_path, section_path, self._global_counter), + "text": sentence, + "source_file": file_path, + "section": section_path, + "confidence": confidence, + "parameter_class": param_class, + "parameter_type": param_type, + "line_range": [line_offset, line_offset + p_lines_count - 1], + }) + + line_offset += p_lines_count + 1 + + # ----------------------------------------------------------------------- + # Per-file processing + # ----------------------------------------------------------------------- + + def process_file(self, file_path: str) -> None: + """Parse one .adoc file and append accepted chunks to repo_results.""" + status, ignored_cat = classify_file(file_path) + + if status == "ignore": + self.report["file_classification"]["ignored"][ignored_cat].append(file_path) + return + + mode = status + self.report["file_classification"]["processed"].append(file_path) + + abs_path = self.repo_dir / file_path + if not abs_path.exists(): + logger.warning(f"File not found in repo: {file_path}") + return + + raw_text = abs_path.read_text(encoding="utf-8") + clean_text = self._preprocess(raw_text) + lines = clean_text.split("\n") + + current_hierarchy: list[str] = ["Preamble"] + paragraphs_buf: list[str] = [] + start_line: int = 1 + file_chunks: list[dict] = [] + raw_sentences: list[dict] = [] + + self.report["files"][file_path] = { + "raw_chunks": 0, + "final_chunks": 0, + "dropped": 0, + } + + for _i, line in enumerate(lines, 1): + header_match = _RE_SECTION_HDR.match(line) + if header_match: + self.flush_paragraphs( + paragraphs_buf, current_hierarchy, start_line, + mode, file_path, file_chunks, raw_sentences, + ) + + level = len(header_match.group(1)) + title = header_match.group(2).strip() + + if level == 1 or not current_hierarchy: + current_hierarchy = [title] + else: + depth_idx = level - 1 + if depth_idx < len(current_hierarchy): + current_hierarchy = current_hierarchy[:depth_idx] + [title] + else: + current_hierarchy.append(title) + + paragraphs_buf = [] + start_line = _i + 1 + else: + paragraphs_buf.append(line) + + # Flush the final paragraph block. + self.flush_paragraphs( + paragraphs_buf, current_hierarchy, start_line, + mode, file_path, file_chunks, raw_sentences, + ) + + # Persist raw sentences (pre-filter) for offline inspection. + self._save_raw_chunks(file_path, raw_sentences) + + if file_chunks: + self.repo_results.append({"file": file_path, "chunks": file_chunks}) + + # ----------------------------------------------------------------------- + # Output writing + # ----------------------------------------------------------------------- + + def _write_outputs(self) -> None: + """Write chunks_repo.json, parameter_dataset.csv, and dump report data.""" + with open(CHUNKS_REPO_PATH, "w", encoding="utf-8") as fh: + json.dump(self.repo_results, fh, indent=2) + + # ── Dump report dict for pipeline/export/reporter.py ── + report_data_path = OUTPUT_DIR / "adoc_report_data.json" + with open(report_data_path, "w", encoding="utf-8") as fh: + json.dump(self.report, fh, indent=2) + + with open(PARAMETER_DATASET_PATH, "w", newline="", encoding="utf-8") as fh: + writer = csv.writer(fh) + writer.writerow([ + "chunk_id", "file", "line", + "section", "text", + "parameter_class", "parameter_type", + "confidence", "reviewed", "notes", + ]) + for file_data in self.repo_results: + for c in file_data["chunks"]: + writer.writerow([ + c["chunk_id"], + c["source_file"], + c["line_range"][0], + c["section"], + c["text"], + c["parameter_class"], + c["parameter_type"], + c["confidence"], + False, + "", + ]) + + # ----------------------------------------------------------------------- + # Orchestration + # ----------------------------------------------------------------------- + + def run(self) -> bool: + """ + Full pipeline run: + 1. Ensure the ISA manual repository is present (clone if needed). + 2. Discover all .adoc sources. + 3. Process each file through the filtering pipeline. + 4. Write all output artefacts. + + Returns ``True`` on success. + """ + OUTPUT_DIR.mkdir(parents=True, exist_ok=True) + RAW_CHUNKS_DIR.mkdir(parents=True, exist_ok=True) + + self._ensure_repo() + + src_dir = self.repo_dir / "src" + rel_files = sorted( + str(f.relative_to(self.repo_dir)) + for f in src_dir.rglob("*.adoc") + ) + + logger.info(f"Processing {len(rel_files)} AsciiDoc files …") + + for f in tqdm(rel_files, desc="Parsing"): + self.process_file(f) + + r_total = sum(d["raw_chunks"] for d in self.report["files"].values()) + k_total = sum(d["final_chunks"] for d in self.report["files"].values()) + + self.report["global"] = { + "total_files": len(rel_files), + "processed_files": len(self.report["file_classification"]["processed"]), + "skipped_files": sum( + len(v) for v in self.report["file_classification"]["ignored"].values() + ), + "total_raw_chunks": r_total, + "total_final_chunks": k_total, + "reduction_percent": round(100 - (k_total / max(1, r_total) * 100), 2), + "isa_manual_commit": self._repo_commit(), + } + # Report generation is suspended pending pipeline/export completion. + # self._write_report() + + self._write_outputs() + logger.info(f"Analysis exported → {FILTER_STATS_PATH}") + logger.info(f"Raw chunks saved → {RAW_CHUNKS_DIR}/ ({len(rel_files)} files)") + return True + + +# --------------------------------------------------------------------------- +# CLI entry point (for direct invocation / testing) +# --------------------------------------------------------------------------- + +def main() -> None: + chunker = AsciiDocChunker(ISA_MANUAL_DIR) + chunker.run() + + +if __name__ == "__main__": + main() diff --git a/tools/llm-extraction/pipeline/ingest/chunker_udb.py b/tools/llm-extraction/pipeline/ingest/chunker_udb.py new file mode 100644 index 0000000000..19e6b4f098 --- /dev/null +++ b/tools/llm-extraction/pipeline/ingest/chunker_udb.py @@ -0,0 +1,388 @@ +""" +Purpose: + Ingests UDB parameter, CSR, and extension YAML schemas and converts them + into structured chunk records matching the AsciiDocChunker output schema, + enabling a unified downstream embedding and retrieval pipeline. + +Pipeline Stage: + ingest + +Inputs: + - spec/std/isa/param/*.yaml (one YAML file = one parameter) + - spec/std/isa/csr/*.yaml (one YAML file = one CSR, with field definitions) + - spec/std/isa/ext/*.yaml (extension metadata and descriptions) + +Outputs: + - data/output/udb_chunks.json (chunk records; schema matches chunks_repo.json) + +Core Responsibilities: + - Discover and parse parameter / CSR / extension YAML files + - Normalize schema format (wrapper-style vs schema-as-root) + - Build human-readable summary sentence per parameter / CSR field + - Classify parameter_class and parameter_type using taxonomy.yaml labels + - Write chunk records compatible with AsciiDocChunker output + +Key Assumptions: + - One YAML file = one parameter or one CSR + - Schema may be at root level or nested under a "schema" key + - $id field is a valid fallback when "name" is absent + +Failure Modes: + - Empty udb_chunks.json if YAML structure changes and normalization fails + - Missing name/description fields reduce classification quality + - NotImplementedError raised on run() until TODO methods are implemented + +Notes: + - Uses rule-based classification (not ML) — consistent with chunker_adoc.py + - Output chunk schema must stay in sync with AsciiDocChunker chunk dict keys +""" + +from __future__ import annotations + +import json +import sys +from pathlib import Path + +# ── sys.path bootstrap ────────────────────────────────────────────────────── + +_INGEST_DIR = Path(__file__).parent.resolve() # pipeline/ingest/ +_TOOL_DIR = _INGEST_DIR.parent.parent # llm-extraction/ + +if str(_TOOL_DIR) not in sys.path: + sys.path.insert(0, str(_TOOL_DIR)) + + + +from configs.config import ( # noqa: E402 + PARAM_DIR, + CSR_DIR, + EXT_DIR, + OUTPUT_DIR, + logger, +) +from pipeline.utils import chunk_id, flatten_text # noqa: E402 + +# Output path for UDB-sourced chunks. +UDB_CHUNKS_PATH = OUTPUT_DIR / "udb_chunks.json" + + +# --------------------------------------------------------------------------- +# Module-level helpers +# --------------------------------------------------------------------------- + +def _extract_defined_by(node) -> str: + """ + Normalise the ``definedBy`` field from a UDB YAML into a plain string. + + UDB supports two forms: + - ``{extension: {name: S}}`` → ``"S"`` + - ``{anyOf: [{extension: {name: A}}, …]}`` → ``"A, B"`` + """ + if not node: + return "" + if isinstance(node, str): + return node + if isinstance(node, dict): + ext = node.get("extension") or {} + if isinstance(ext, dict): + return str(ext.get("name", "")) + any_of = node.get("anyOf") or [] + names = [] + for item in any_of: + if isinstance(item, dict): + e = item.get("extension") or {} + if isinstance(e, dict): + names.append(str(e.get("name", ""))) + return ", ".join(n for n in names if n) + return "" + + +def _schema_summary(schema: dict) -> str: + """ + Build a short human-readable constraint summary from a UDB ``schema`` node. + + Examples: + integer [0, 16] → type=integer, minimum=0, maximum=16 + string enum [A, B, C] → type=string, enum: A, B, C + """ + if not schema: + return "" + parts: list[str] = [] + typ = schema.get("type", "") + if typ: + parts.append(f"type={typ}") + minimum = schema.get("minimum") + maximum = schema.get("maximum") + if minimum is not None or maximum is not None: + parts.append(f"range=[{minimum}, {maximum}]") + enum = schema.get("enum") or schema.get("const") + if enum: + if isinstance(enum, list): + parts.append(f"enum: {', '.join(str(v) for v in enum[:8])}") + else: + parts.append(f"const: {enum}") + return ", ".join(parts) + + +# Maps JSON Schema primitive types → taxonomy.yaml parameter_type labels. +_SCHEMA_TYPE_MAP: dict[str, str] = { + "integer": "range", + "number": "range", + "boolean": "binary", + "string": "enum", # most string params are mode/encoding selectors + "array": "range", + "object": "unknown", +} + + +def _map_schema_type(schema: dict) -> str: + """ + Map a UDB ``schema`` node to a taxonomy.yaml ``parameter_type`` label. + + Rules (in priority order): + 1. If the schema has an ``enum`` or ``const`` key → ``"enum"`` + 2. If it has ``minimum`` or ``maximum`` → ``"range"`` + 3. Map the ``type`` string via ``_SCHEMA_TYPE_MAP`` + 4. Fall back to ``"unknown"`` + """ + if not schema: + return "unknown" + if schema.get("enum") or schema.get("const"): + return "enum" + if schema.get("minimum") is not None or schema.get("maximum") is not None: + return "range" + raw_type = schema.get("type", "") + return _SCHEMA_TYPE_MAP.get(str(raw_type).lower(), "unknown") + + +def _first_line(value) -> str: + """ + Return the first non-empty line of a (possibly multiline) IDL string. + + IDL ``type()`` and ``reset_value()`` functions are multi-line; + only the first line is useful in a chunk summary. + """ + text = str(value).strip() if value else "" + for line in text.splitlines(): + stripped = line.strip() + if stripped: + return stripped + return "" + + +class UDBChunker: + """Produce chunk dicts from UDB YAML schemas compatible with AsciiDocChunker output.""" + + def __init__( + self, + param_dir: Path = PARAM_DIR, + csr_dir: Path = CSR_DIR, + ext_dir: Path = EXT_DIR, + ) -> None: + self.param_dir = param_dir + self.csr_dir = csr_dir + self.ext_dir = ext_dir + self.chunks: list[dict] = [] + + def _ingest_params(self) -> None: + """ + Walk param_dir, parse each YAML file, and append a chunk dict per parameter. + + Each chunk captures the parameter name, description, type/range/enum + constraints from the nested ``schema`` key, and the ``definedBy`` extension. + Confidence is set to ``"high"`` because UDB parameters are normative. + """ + from configs.config import yaml # ruamel.yaml instance + + files = sorted(self.param_dir.glob("*.yaml")) + logger.info(f"_ingest_params: {len(files)} parameter files found in {self.param_dir}") + + for idx, path in enumerate(files): + try: + with open(path, encoding="utf-8") as fh: + data = yaml.load(fh) + except Exception as exc: + logger.warning(f"Skipping {path.name}: {exc}") + continue + + name = str(data.get("name") or path.stem) + description = flatten_text(data.get("description") or "") + schema_node = data.get("schema") or {} + defined_by = _extract_defined_by(data.get("definedBy")) + + # Build a concise, human-readable summary sentence. + constraints = _schema_summary(schema_node) + text_parts = [f"Parameter {name}"] + if description: + text_parts.append(description) + if constraints: + text_parts.append(f"Schema: {constraints}.") + if defined_by: + text_parts.append(f"Defined by: {defined_by}.") + text = " ".join(text_parts) + + self.chunks.append({ + "chunk_id": chunk_id("udb_param", str(path), idx), + "source": "udb_param", + "source_file": str(path.relative_to(self.param_dir.parent.parent.parent)), + "section": name, + "text": text, + "parameter_class": "non_CSR_parameter", + "parameter_type": _map_schema_type(schema_node), + "confidence": "high", + "defined_by": defined_by, + }) + + def _ingest_csrs(self) -> None: + """ + Walk csr_dir recursively (CSRs are grouped in sub-dirs by extension), + parse each YAML file, and emit one chunk per CSR plus one chunk per field. + + Field chunks capture: name, location, description, type() IDL, reset_value() IDL. + """ + from configs.config import yaml + + files = sorted(self.csr_dir.rglob("*.yaml")) + logger.info(f"_ingest_csrs: {len(files)} CSR files found under {self.csr_dir}") + + for idx, path in enumerate(files): + try: + with open(path, encoding="utf-8") as fh: + data = yaml.load(fh) + except Exception as exc: + logger.warning(f"Skipping {path.name}: {exc}") + continue + + if data.get("kind") != "csr": + continue + + csr_name = str(data.get("name") or path.stem) + csr_desc = flatten_text(data.get("description") or "") + address = data.get("address", "") + priv_mode = data.get("priv_mode", "") + + # ── Top-level CSR chunk ────────────────────────────────────────── + csr_text = f"CSR {csr_name} (address={address}, priv={priv_mode})" + if csr_desc: + csr_text += f": {csr_desc[:300]}" + + self.chunks.append({ + "chunk_id": chunk_id("udb_csr", str(path), idx), + "source": "udb_csr", + "source_file": str(path), + "section": csr_name, + "text": csr_text, + "parameter_class": "CSR_controlled", + "parameter_type": "csr_register", + "confidence": "high", + "defined_by": _extract_defined_by(data.get("definedBy")), + }) + + # ── Per-field chunks ───────────────────────────────────────────── + for field_name, field in (data.get("fields") or {}).items(): + if not isinstance(field, dict): + continue + f_desc = flatten_text(field.get("description") or "") + # type() is an IDL function string — take only the first line for readability. + f_type = _first_line(field.get("type()") or field.get("type") or "") + f_reset = _first_line(field.get("reset_value()") or field.get("reset_value") or "") + # location may be split by RV32/RV64 — prefer unified, fall back to both. + loc = ( + field.get("location") + or f"rv32={field.get('location_rv32', '?')} rv64={field.get('location_rv64', '?')}" + ) + + parts = [ + f"CSR {csr_name} field {field_name} (bits={loc})", + f_desc[:300] if f_desc else "", + f"type: {f_type}" if f_type else "", + f"reset: {f_reset[:80]}" if f_reset else "", + ] + field_text = " ".join(p for p in parts if p) + + self.chunks.append({ + "chunk_id": chunk_id("udb_csr_field", f"{path}::{field_name}", idx), + "source": "udb_csr_field", + "source_file": str(path), + "section": f"{csr_name}.{field_name}", + "text": field_text, + "parameter_class": "CSR_controlled", + "parameter_type": "csr_field", + "confidence": "high", + "defined_by": "", + }) + + def _ingest_extensions(self) -> None: + """ + Walk ext_dir, extract each extension's long_name, description, and + ratification status as a lightweight chunk. + """ + from configs.config import yaml + + files = sorted(self.ext_dir.glob("*.yaml")) + logger.info(f"_ingest_extensions: {len(files)} extension files found in {self.ext_dir}") + + for idx, path in enumerate(files): + try: + with open(path, encoding="utf-8") as fh: + data = yaml.load(fh) + except Exception as exc: + logger.warning(f"Skipping {path.name}: {exc}") + continue + + if data.get("kind") != "extension": + continue + + name = str(data.get("name") or path.stem) + long_name = str(data.get("long_name") or "") + desc = flatten_text(data.get("description") or "") + versions = data.get("versions") or [] + state = versions[0].get("state", "") if versions else "" + + parts = [f"Extension {name}"] + if long_name: + parts.append(f"({long_name})") + if state: + parts.append(f"[{state}]") + if desc: + parts.append(desc[:400]) + text = " ".join(parts) + + self.chunks.append({ + "chunk_id": chunk_id("udb_ext", str(path), idx), + "source": "udb_ext", + "source_file": str(path), + "section": name, + "text": text, + "parameter_class": "non_CSR_parameter", + "parameter_type": "extension", + "confidence": "high", + "defined_by": name, + }) + + def _write_outputs(self) -> None: + OUTPUT_DIR.mkdir(parents=True, exist_ok=True) + with open(UDB_CHUNKS_PATH, "w", encoding="utf-8") as fh: + json.dump(self.chunks, fh, indent=2, ensure_ascii=False) + logger.info(f"UDB chunks written → {UDB_CHUNKS_PATH} ({len(self.chunks)} chunks)") + + def run(self) -> bool: + """Run full ingestion. Raises NotImplementedError until TODOs are filled.""" + logger.info("UDBChunker.run() — ingesting parameter / CSR YAML schemas …") + self._ingest_params() + self._ingest_csrs() + self._ingest_extensions() + self._write_outputs() + logger.info(f"UDBChunker complete: {len(self.chunks)} chunks produced.") + return True + + + + +def main() -> None: + chunker = UDBChunker() + chunker.run() + + +if __name__ == "__main__": + main() diff --git a/tools/llm-extraction/pipeline/utils.py b/tools/llm-extraction/pipeline/utils.py new file mode 100644 index 0000000000..4e8b5b99fe --- /dev/null +++ b/tools/llm-extraction/pipeline/utils.py @@ -0,0 +1,28 @@ +""" +Purpose: + Shared text-handling and utility functions for the extraction pipeline. +""" + +import hashlib +from typing import Any + +def flatten_text(value: Any) -> str: + """Flatten a nested JSON/YAML list or dict into a single string.""" + if isinstance(value, str): + return value.strip() + if isinstance(value, list): + parts = [] + for item in value: + parts.append(str(item["text"]) if isinstance(item, dict) and "text" in item else str(item)) + return " ".join(p for p in parts if p).strip() + return str(value) if value is not None else "" + + +def normalize_text(text: str) -> str: + """Collapse excess whitespace and newlines.""" + return " ".join(text.split()).strip() + + +def chunk_id(source: str, path: str, index: int) -> str: + """Generate a deterministic short hash for chunk IDs.""" + return "chunk_" + hashlib.md5(f"{source}::{path}::{index}".encode()).hexdigest()[:8] diff --git a/tools/llm-extraction/pipeline_runner.py b/tools/llm-extraction/pipeline_runner.py new file mode 100644 index 0000000000..900389c8bf --- /dev/null +++ b/tools/llm-extraction/pipeline_runner.py @@ -0,0 +1,250 @@ +""" +Purpose: + Orchestration logic for the RISC-V UDB extraction pipeline. + Receives a subcommand from main.py and dispatches to the correct stage. + +Pipeline Stage: + all (orchestrates ingest → process → embed → export) + +Inputs: + - (delegates to per-stage modules; see each _run_* function) + +Outputs: + - (delegates to per-stage modules; see each _run_* function) + +Core Responsibilities: + - Set up sys.path so pipeline/ and configs/ are importable from any cwd + - Implement _run_ingest, _run_process, _run_embed, _run_export + - Collect per-phase wall-clock timings and pass to reporter + - Dispatch run(subcommand, mode) → correct stage(s) + +Key Assumptions: + - Called by main.py; never run directly + - Modules are imported lazily inside each _run_* to avoid circular deps + +Failure Modes: + - sys.exit(1) on AsciiDocChunker failure or unknown subcommand + - ModuleNotFoundError if .venv is not activated before running + +Notes: + - Lazy imports (inside _run_*) keep startup time fast for --dry-run + - Phase timings (seconds) are accumulated in _TIMINGS and passed to + reporter.generate_markdown_report() during _run_export. +""" + +import subprocess +import sys +import time +from pathlib import Path + +# sys.path setup: pipeline/ and configs/ must be importable from any cwd. +_TOOL_DIR = Path(__file__).parent.resolve() # llm-extraction/ + +if str(_TOOL_DIR) not in sys.path: + sys.path.insert(0, str(_TOOL_DIR)) + +from configs.config import ( # noqa: E402 (after sys.path setup) + logger, + ISA_MANUAL_DIR, + ISA_MANUAL_REPO_URL, + OUTPUT_DIR, + DATA_DIR, + CHUNKS_PATH, +) + +# Accumulates wall-clock seconds per phase; passed to the reporter. +_TIMINGS: dict[str, float] = {} + + +# --------------------------------------------------------------------------- +# Internal timing helper +# --------------------------------------------------------------------------- + +def _timed(phase: str): + """Context manager that records wall-clock duration into _TIMINGS.""" + import contextlib + + @contextlib.contextmanager + def _ctx(): + t0 = time.perf_counter() + try: + yield + finally: + _TIMINGS[phase] = time.perf_counter() - t0 + return _ctx() + + +# --------------------------------------------------------------------------- +# Stage: ingest +# --------------------------------------------------------------------------- + +def _run_ingest() -> None: + """Clone riscv-isa-manual on first run; fetch + reset to HEAD on subsequent runs.""" + logger.info("=== ingest: riscv-isa-manual ===") + DATA_DIR.mkdir(parents=True, exist_ok=True) + + with _timed("ingest"): + if not ISA_MANUAL_DIR.exists(): + logger.info(f"Cloning ISA manual into {ISA_MANUAL_DIR} …") + subprocess.run( + ["git", "clone", "--depth=1", ISA_MANUAL_REPO_URL, str(ISA_MANUAL_DIR)], + check=True, + ) + else: + logger.info(f"ISA manual already present at {ISA_MANUAL_DIR}; pulling latest …") + subprocess.run( + ["git", "-C", str(ISA_MANUAL_DIR), "fetch", "--depth=1", "origin", "main"], + check=True, + ) + subprocess.run( + ["git", "-C", str(ISA_MANUAL_DIR), "reset", "--hard", "origin/main"], + check=True, + ) + + logger.info("ingest: complete.") + + +# --------------------------------------------------------------------------- +# Stage: process +# --------------------------------------------------------------------------- + +def _run_process() -> None: + """ + Run both ingest chunkers: + 1. AsciiDocChunker — chunks the ISA manual prose, then removes the clone. + 2. UDBChunker — chunks param/csr/ext YAML schemas from the repo. + """ + logger.info("=== process: spec chunking ===") + OUTPUT_DIR.mkdir(parents=True, exist_ok=True) + + # ── 1. AsciiDoc chunker ────────────────────────────────────────────────── + from pipeline.ingest.chunker_adoc import AsciiDocChunker # noqa: PLC0415 + + with _timed("process_adoc"): + chunker = AsciiDocChunker(ISA_MANUAL_DIR) + success = chunker.run() + + if not success: + logger.error("process: AsciiDocChunker reported a failure.") + sys.exit(1) + + import shutil + if ISA_MANUAL_DIR.exists(): + shutil.rmtree(ISA_MANUAL_DIR) + logger.info(f"Cleaned up {ISA_MANUAL_DIR}") + + # ── 2. UDB YAML chunker ────────────────────────────────────────────────── + logger.info("=== process: UDB YAML chunking ===") + from pipeline.ingest.chunker_udb import UDBChunker # noqa: PLC0415 + + with _timed("process_udb"): + udb_chunker = UDBChunker() + udb_chunker.run() + + logger.info("process: complete.") + + +# --------------------------------------------------------------------------- +# Stage: embed +# --------------------------------------------------------------------------- + +def _run_embed(mode: str = "rag") -> None: + """ + Build ChromaDB vector index from combined AsciiDoc + UDB chunks. + Loads pre-computed chunks from data/output/udb_chunks.json and + data/output/chunks_repo.json via the storage modules. + """ + logger.info(f"=== embed: vector database (mode={mode}) ===") + + import json + from pipeline.storage.embedder import embed_texts # noqa: PLC0415 + from pipeline.storage.chroma_store import upsert_chunks, reset_collection # noqa: PLC0415 + + with _timed("embed"): + all_chunks: list[dict] = [] + + # 1. Load AsciiDoc chunks + if CHUNKS_REPO_PATH.exists(): + with open(CHUNKS_REPO_PATH, encoding="utf-8") as fh: + repo = json.load(fh) + adoc_chunks = [c for entry in repo for c in entry.get("chunks", [])] + all_chunks.extend(adoc_chunks) + logger.info(f"embed: {len(adoc_chunks)} AsciiDoc chunks loaded.") + else: + logger.warning(f"Chunks file not found: {CHUNKS_REPO_PATH}. Run 'process' first.") + + # 2. Load UDB chunks + udb_chunks_path = OUTPUT_DIR / "udb_chunks.json" + if udb_chunks_path.exists(): + udb_chunks = json.loads(udb_chunks_path.read_text(encoding="utf-8")) + all_chunks.extend(udb_chunks) + logger.info(f"embed: {len(udb_chunks)} UDB chunks loaded.") + else: + logger.warning(f"UDB chunks not found: {udb_chunks_path}. Run 'process' first.") + + if not all_chunks: + logger.warning("No chunks to embed. Skipping.") + return + + texts = [c.get("text", "") for c in all_chunks] + logger.info(f"embed: generating embeddings for {len(all_chunks)} total chunks …") + embeddings = embed_texts(texts) + + # Full re-index on 'analysis' mode; incremental upsert on 'rag'. + if mode == "analysis": + reset_collection() + + upsert = upsert_chunks(all_chunks, embeddings) + logger.info(f"embed: {upsert} chunks upserted into ChromaDB.") + + logger.info("embed: complete.") + + +# --------------------------------------------------------------------------- +# Stage: export +# --------------------------------------------------------------------------- + +def _run_export(mode: str = "rag") -> None: + """ + Generate a full evaluation Markdown report: + - per-phase timing stats + - confidence histograms (AsciiDoc + UDB) + - parameter class / type distribution tables + - unknown-class sample table for manual review + Output → data/evaluation/pipeline_report_.md + """ + logger.info(f"=== export (mode={mode}) ===") + + from pipeline.export.reporter import generate_markdown_report # noqa: PLC0415 + + report_path = generate_markdown_report(timings=_TIMINGS) + logger.info(f"export: report written → {report_path}") + logger.info("export: complete.") + + +# --------------------------------------------------------------------------- +# Dispatcher +# --------------------------------------------------------------------------- + +def run(subcommand: str, mode: str = "rag") -> None: + """Dispatch subcommand to the correct pipeline stage(s).""" + dispatch = { + "ingest": lambda: _run_ingest(), + "process": lambda: _run_process(), + "embed": lambda: _run_embed(mode=mode), + "export": lambda: _run_export(mode=mode), + "all": lambda: ( + _run_ingest(), + _run_process(), + _run_embed(mode=mode), + _run_export(mode=mode), + ), + } + + handler = dispatch.get(subcommand) + if handler is None: + logger.error(f"Unknown subcommand: {subcommand!r}") + sys.exit(1) + + handler() + logger.info(f"Pipeline '{subcommand}' finished successfully.") \ No newline at end of file diff --git a/tools/llm-extraction/requirements.txt b/tools/llm-extraction/requirements.txt new file mode 100644 index 0000000000..c8737ed229 --- /dev/null +++ b/tools/llm-extraction/requirements.txt @@ -0,0 +1,12 @@ +# requirements.txt — RISC-V UDB LLM-extraction pipeline +# Pin minor versions for reproducibility; bump deliberately on dependency audits. +# pathlib is part of the Python 3.4+ standard library — no install needed. + +ruamel.yaml +pyyaml +tqdm +chromadb +sentence-transformers +rich +pandas +