diff --git a/backends/cpp_hart_gen/CMakeLists.txt b/backends/cpp_hart_gen/CMakeLists.txt
index 0d1fd4fdfc..f0b1037ca5 100644
--- a/backends/cpp_hart_gen/CMakeLists.txt
+++ b/backends/cpp_hart_gen/CMakeLists.txt
@@ -235,6 +235,13 @@ add_executable(test_version
 target_include_directories(test_version PUBLIC ${CMAKE_SOURCE_DIR}/include)
 target_link_libraries(test_version PRIVATE hart Catch2::Catch2WithMain)
 
+add_executable(test_regfile
+  ${CMAKE_SOURCE_DIR}/test/test_regfile.cpp
+  ${CMAKE_SOURCE_DIR}/src/NotificationHandler.cpp
+)
+target_include_directories(test_regfile PUBLIC ${CMAKE_SOURCE_DIR}/include)
+target_link_libraries(test_regfile PRIVATE hart Catch2::Catch2WithMain)
+
 # add_executable(test_decode
 #   ${CMAKE_SOURCE_DIR}/test/test_decode.cpp
 # )
@@ -244,6 +251,7 @@ target_link_libraries(test_version PRIVATE hart Catch2::Catch2WithMain)
 include(CTest)
 include(Catch)
 catch_discover_tests(test_bits_directed)
+catch_discover_tests(test_regfile)
 
 foreach (random_test IN LISTS RANDOM_TESTS)
   catch_discover_tests(${random_test})
diff --git a/backends/cpp_hart_gen/cpp/include/udb/hart.hpp b/backends/cpp_hart_gen/cpp/include/udb/hart.hpp
index a77585f218..ea1be23e34 100644
--- a/backends/cpp_hart_gen/cpp/include/udb/hart.hpp
+++ b/backends/cpp_hart_gen/cpp/include/udb/hart.hpp
@@ -329,6 +329,19 @@ namespace udb {
     virtual uint64_t xreg(unsigned num) const = 0;
     virtual void set_xreg(unsigned num, uint64_t value) = 0;
 
+    virtual uint64_t freg(unsigned num) const {
+      throw std::runtime_error("No F register file in this configuration");
+    }
+    virtual void set_freg(unsigned num, uint64_t value) {
+      throw std::runtime_error("No F register file in this configuration");
+    }
+    virtual uint64_t vreg(unsigned num) const {
+      throw std::runtime_error("No V register file in this configuration");
+    }
+    virtual void set_vreg(unsigned num, uint64_t value) {
+      throw std::runtime_error("No V register file in this configuration");
+    }
+
     virtual CsrBase* csr(unsigned address) = 0;
     virtual const CsrBase* csr(unsigned address) const = 0;
 
diff --git a/backends/cpp_hart_gen/cpp/include/udb/inst.hpp b/backends/cpp_hart_gen/cpp/include/udb/inst.hpp
index 7f5233fdc6..bdb8239d61 100644
--- a/backends/cpp_hart_gen/cpp/include/udb/inst.hpp
+++ b/backends/cpp_hart_gen/cpp/include/udb/inst.hpp
@@ -73,7 +73,39 @@ namespace udb {
       F29 = 61,
       F30 = 62,
       F31 = 63,
-      INVALID = 64
+      V0 = 64,
+      V1 = 65,
+      V2 = 66,
+      V3 = 67,
+      V4 = 68,
+      V5 = 69,
+      V6 = 70,
+      V7 = 71,
+      V8 = 72,
+      V9 = 73,
+      V10 = 74,
+      V11 = 75,
+      V12 = 76,
+      V13 = 77,
+      V14 = 78,
+      V15 = 79,
+      V16 = 80,
+      V17 = 81,
+      V18 = 82,
+      V19 = 83,
+      V20 = 84,
+      V21 = 85,
+      V22 = 86,
+      V23 = 87,
+      V24 = 88,
+      V25 = 89,
+      V26 = 90,
+      V27 = 91,
+      V28 = 92,
+      V29 = 93,
+      V30 = 94,
+      V31 = 95,
+      INVALID = 96
     };
 
     Reg(Enum r) : m_reg(r) {}
@@ -82,6 +114,16 @@ namespace udb {
     template <typename BitsClass>
       requires (BitsClass::IsABits)
     Reg(const BitsClass& r, bool is_fp = false) : m_reg(Enum(is_fp ? r.get() + 32 : r.get())) {}
+
+    template <typename T>
+    static Reg from_rf_index(T idx, uint64_t base) {
+      if constexpr (requires { T::IsABits; }) {
+        return Reg(Enum(idx.get() + base));
+      } else {
+        return Reg(Enum(static_cast<uint64_t>(idx) + base));
+      }
+    }
+
     operator Enum() const { return m_reg; }
     bool operator==(const Reg &other) const { return m_reg == other.m_reg; }
     bool operator==(Enum other) const { return m_reg == other; }
@@ -92,16 +134,18 @@ namespace udb {
 
     bool is_int() const { return m_reg <= X31; }
     bool is_fp() const { return m_reg >= F0 && m_reg <= F31; }
+    bool is_vec() const { return m_reg >= V0 && m_reg <= V31; }
 
     uint64_t get_num() const {
       uint64_t num = static_cast<uint64_t>(m_reg);
-      return (m_reg <= X31) ? num : num - 32;  // NOLINT
+      if (m_reg <= X31) return num;
+      if (m_reg <= F31) return num - 32u;  // NOLINT
+      return num - 64u;  // V  // NOLINT
     }
 
     std::string to_string(uint64_t size = 64) const {
-      if (is_fp()) {
-        return "f" + std::to_string(get_num());
-      }
+      if (is_fp()) return "f" + std::to_string(get_num());
+      if (is_vec()) return "v" + std::to_string(get_num());
       return "x" + std::to_string(get_num());
     }
 
diff --git a/backends/cpp_hart_gen/cpp/src/iss.cpp b/backends/cpp_hart_gen/cpp/src/iss.cpp
index 1e0e5f7f5f..fcdf3be8d5 100644
--- a/backends/cpp_hart_gen/cpp/src/iss.cpp
+++ b/backends/cpp_hart_gen/cpp/src/iss.cpp
@@ -26,7 +26,6 @@
 #define RISCV_REG_PC        0x20
 #define RISCV_REG_FPR_FIRST 0x21
 #define RISCV_REG_FPR_LAST  0x40
-#define RISCV_REG_FPR_LAST  0x40
 #define RISCV_REG_CSR_FIRST 0x41
 #define RISCV_REG_CSR_LAST  0x1040
 
@@ -419,8 +418,14 @@ int InstructionSetSimulator::OnReadSingleRegister(int reg, uint64_t& value)
     value = m_pHart->pc();
   else if (reg >= RISCV_REG_FPR_FIRST && reg <= RISCV_REG_FPR_LAST)
   {
-    //no FP so far
-    return -1;
+    try
+    {
+      value = m_pHart->freg(reg - RISCV_REG_FPR_FIRST);
+    }
+    catch(...)
+    {
+      return -1;
+    }
   }
   else if (reg >= RISCV_REG_CSR_FIRST && reg <= RISCV_REG_CSR_LAST)
   {
@@ -456,8 +461,14 @@ int InstructionSetSimulator::OnWriteSingleRegister(int reg, uint64_t& value)
     m_pHart->set_next_pc(value);
   else if (reg >= RISCV_REG_FPR_FIRST && reg <= RISCV_REG_FPR_LAST)
   {
-    //no FP so far
-    return -1;
+    try
+    {
+      m_pHart->set_freg(reg - RISCV_REG_FPR_FIRST, value);
+    }
+    catch(...)
+    {
+      return -1;
+    }
   }
   else if (reg >= RISCV_REG_CSR_FIRST && reg <= RISCV_REG_CSR_LAST)
   {
diff --git a/backends/cpp_hart_gen/cpp/test/test_regfile.cpp b/backends/cpp_hart_gen/cpp/test/test_regfile.cpp
new file mode 100644
index 0000000000..bf154373e4
--- /dev/null
+++ b/backends/cpp_hart_gen/cpp/test/test_regfile.cpp
@@ -0,0 +1,179 @@
+// Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+// SPDX-License-Identifier: BSD-3-Clause-Clear
+
+// Tests for register file storage and accessor generation (Layer 4a–4c).
+
+#include <catch2/catch_test_macros.hpp>
+#include <udb/hart_factory.hxx>
+#include <udb/iss_soc_model.hpp>
+#include <stdexcept>
+
+// Use the rv64-riscv-tests config (known-working fully-configured rv64 with F extension).
+static const std::string cfg_yaml = R"(
+$schema: https://riscv.org/udb/schemas/config_schema-0.1.0.json
+kind: architecture configuration
+type: fully configured
+name: rv64-riscv-tests
+description: For register file testing
+
+implemented_extensions:
+  - [Sm, "1.11.0"]
+  - [Smstateen, "1.0.0"]
+  - [I, "2.1"]
+  - [C, "2.0"]
+  - [M, "2.0"]
+  - [Zicsr, "2.0"]
+  - [Zicntr, "2.0"]
+  - [Smrnmi, "1.0"]
+  - [S, "1.11.0"]
+  - [U, "1.0.0"]
+  - [Zifencei, "2.0.0"]
+  - [Sv39, "1.11.0"]
+  - [Zca, "1.0.0"]
+  - [F, "2.2.0"]
+
+params:
+  MXLEN: 64
+  MARCHID_IMPLEMENTED: true
+  ARCH_ID_VALUE: 1
+  MIMPID_IMPLEMENTED: true
+  IMP_ID_VALUE: 0
+  VENDOR_ID_BANK: 1
+  VENDOR_ID_OFFSET: 1
+  MISALIGNED_LDST: true
+  MISALIGNED_LDST_EXCEPTION_PRIORITY: low
+  MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE: 4
+  MISALIGNED_SPLIT_STRATEGY: sequential_bytes
+  PRECISE_SYNCHRONOUS_EXCEPTIONS: true
+  TRAP_ON_ECALL_FROM_M: true
+  TRAP_ON_EBREAK: true
+  M_MODE_ENDIANNESS: little
+  TRAP_ON_ILLEGAL_WLRL: true
+  TRAP_ON_UNIMPLEMENTED_INSTRUCTION: true
+  TRAP_ON_RESERVED_INSTRUCTION: true
+  TRAP_ON_UNIMPLEMENTED_CSR: true
+  REPORT_VA_IN_MTVAL_ON_BREAKPOINT: true
+  REPORT_VA_IN_MTVAL_ON_LOAD_MISALIGNED: true
+  REPORT_VA_IN_MTVAL_ON_STORE_AMO_MISALIGNED: true
+  REPORT_VA_IN_MTVAL_ON_INSTRUCTION_MISALIGNED: true
+  REPORT_VA_IN_MTVAL_ON_LOAD_ACCESS_FAULT: true
+  REPORT_VA_IN_MTVAL_ON_STORE_AMO_ACCESS_FAULT: true
+  REPORT_VA_IN_MTVAL_ON_INSTRUCTION_ACCESS_FAULT: true
+  REPORT_ENCODING_IN_MTVAL_ON_ILLEGAL_INSTRUCTION: true
+  MTVAL_WIDTH: 32
+  PMA_GRANULARITY: 12
+  PHYS_ADDR_WIDTH: 57
+  MISA_CSR_IMPLEMENTED: true
+  MTVEC_ACCESS: rw
+  MTVEC_MODES: [0, 1]
+  MTVEC_BASE_ALIGNMENT_DIRECT: 4
+  MTVEC_BASE_ALIGNMENT_VECTORED: 4
+  MTVEC_ILLEGAL_WRITE_BEHAVIOR: retain
+  MUTABLE_MISA_C: false
+  MUTABLE_MISA_M: false
+  TIME_CSR_IMPLEMENTED: false
+  MUTABLE_MISA_S: false
+  ASID_WIDTH: 5
+  S_MODE_ENDIANNESS: little
+  SXLEN: [64]
+  REPORT_VA_IN_MTVAL_ON_LOAD_PAGE_FAULT: true
+  REPORT_VA_IN_MTVAL_ON_STORE_AMO_PAGE_FAULT: true
+  REPORT_VA_IN_MTVAL_ON_INSTRUCTION_PAGE_FAULT: true
+  REPORT_VA_IN_STVAL_ON_BREAKPOINT: true
+  REPORT_VA_IN_STVAL_ON_LOAD_MISALIGNED: true
+  REPORT_VA_IN_STVAL_ON_STORE_AMO_MISALIGNED: true
+  REPORT_VA_IN_STVAL_ON_INSTRUCTION_MISALIGNED: true
+  REPORT_VA_IN_STVAL_ON_LOAD_ACCESS_FAULT: true
+  REPORT_VA_IN_STVAL_ON_STORE_AMO_ACCESS_FAULT: true
+  REPORT_VA_IN_STVAL_ON_INSTRUCTION_ACCESS_FAULT: true
+  REPORT_VA_IN_STVAL_ON_LOAD_PAGE_FAULT: true
+  REPORT_VA_IN_STVAL_ON_STORE_AMO_PAGE_FAULT: true
+  REPORT_VA_IN_STVAL_ON_INSTRUCTION_PAGE_FAULT: true
+  REPORT_ENCODING_IN_STVAL_ON_ILLEGAL_INSTRUCTION: true
+  STVAL_WIDTH: 32
+  MCOUNTENABLE_EN: [false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false]
+  SCOUNTENABLE_EN: [false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false]
+  COUNTINHIBIT_EN: [false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false]
+  STVEC_MODE_DIRECT: true
+  STVEC_MODE_VECTORED: true
+  SATP_MODE_BARE: true
+  TRAP_ON_ECALL_FROM_S: true
+  TRAP_ON_ECALL_FROM_U: true
+  MSTATUS_VS_LEGAL_VALUES: [0]
+  MSTATUS_FS_LEGAL_VALUES: [3, 2, 1, 0]
+  MSTATUS_TVM_IMPLEMENTED: false
+  NUM_PMP_ENTRIES: 16
+  PMP_GRANULARITY: 12
+  MUTABLE_MISA_U: false
+  U_MODE_ENDIANNESS: little
+  UXLEN: [64]
+  MSTATEEN_ENVCFG_TYPE: rw
+  HW_MSTATUS_FS_DIRTY_UPDATE: precise
+  MUTABLE_MISA_F: false
+  HPM_COUNTER_EN: [false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false]
+  MCOUNTINHIBIT_IMPLEMENTED: true
+)";
+
+// ---------------------------------------------------------------------------
+// X register file tests (Layer 4a–4c)
+// ---------------------------------------------------------------------------
+
+TEST_CASE("X register storage has 32 entries", "[regfile]") {
+  udb::IssSocModel soc(1024 * 1024, 0);
+  auto* hart = udb::HartFactory::create("rv64", 0, cfg_yaml, soc);
+  // Write a known value to x31, verify it round-trips; index 32 throws.
+  REQUIRE_NOTHROW(hart->set_xreg(31, 42));
+  REQUIRE(hart->xreg(31) == 42);
+  REQUIRE_THROWS_AS(hart->xreg(32), std::out_of_range);
+  delete hart;
+}
+
+TEST_CASE("x0 is zero after reset", "[regfile]") {
+  udb::IssSocModel soc(1024 * 1024, 0);
+  auto* hart = udb::HartFactory::create("rv64", 0, cfg_yaml, soc);
+  REQUIRE(hart->xreg(0) == 0);
+  delete hart;
+}
+
+TEST_CASE("writing to x0 leaves it zero (arch_write)", "[regfile]") {
+  udb::IssSocModel soc(1024 * 1024, 0);
+  auto* hart = udb::HartFactory::create("rv64", 0, cfg_yaml, soc);
+  hart->set_xreg(0, 42);
+  REQUIRE(hart->xreg(0) == 0);
+  delete hart;
+}
+
+TEST_CASE("xreg throws out_of_range for index >= 32", "[regfile]") {
+  udb::IssSocModel soc(1024 * 1024, 0);
+  auto* hart = udb::HartFactory::create("rv64", 0, cfg_yaml, soc);
+  REQUIRE_THROWS_AS(hart->set_xreg(32, 0), std::out_of_range);
+  delete hart;
+}
+
+// ---------------------------------------------------------------------------
+// F register file tests (Layer 4d: hart.hpp adds virtual freg() to HartBase)
+// ---------------------------------------------------------------------------
+
+TEST_CASE("F register storage has 32 entries", "[regfile]") {
+  udb::IssSocModel soc(1024 * 1024, 0);
+  auto* hart = udb::HartFactory::create("rv64", 0, cfg_yaml, soc);
+  REQUIRE_NOTHROW(hart->set_freg(31, 0xdeadbeef));
+  REQUIRE(hart->freg(31) == 0xdeadbeef);
+  REQUIRE_THROWS_AS(hart->freg(32), std::out_of_range);
+  delete hart;
+}
+
+TEST_CASE("freg round-trips a written value", "[regfile]") {
+  udb::IssSocModel soc(1024 * 1024, 0);
+  auto* hart = udb::HartFactory::create("rv64", 0, cfg_yaml, soc);
+  hart->set_freg(0, 0x3f800000);
+  REQUIRE(hart->freg(0) == 0x3f800000);
+  delete hart;
+}
+
+TEST_CASE("freg throws out_of_range for index >= 32", "[regfile]") {
+  udb::IssSocModel soc(1024 * 1024, 0);
+  auto* hart = udb::HartFactory::create("rv64", 0, cfg_yaml, soc);
+  REQUIRE_THROWS_AS(hart->set_freg(32, 0), std::out_of_range);
+  delete hart;
+}
diff --git a/backends/cpp_hart_gen/lib/gen_cpp.rb b/backends/cpp_hart_gen/lib/gen_cpp.rb
index ca32d13548..f096fd6812 100644
--- a/backends/cpp_hart_gen/lib/gen_cpp.rb
+++ b/backends/cpp_hart_gen/lib/gen_cpp.rb
@@ -873,9 +873,12 @@ def gen_cpp(symtab, indent = 0, indent_spaces: 2)
           "#{' ' * indent}#{var.gen_cpp(symtab, 0, indent_spaces:)}.at(#{index.gen_cpp(symtab, 0)})"
         end
       else
-        if var.text_value.start_with?("X")
-          #"#{' '*indent}#{var.gen_cpp(symtab, 0, indent_spaces:)}[#{index.gen_cpp(symtab, 0, indent_spaces:)}]"
-          "#{' ' * indent} __UDB_HART->_xreg(#{index.gen_cpp(symtab, 0, indent_spaces:)})"
+        var_type = var.type(symtab)
+        if var_type.kind == :array &&
+           var_type.sub_type.is_a?(Idl::RegFileElementType) &&
+           var_type.qualifiers.include?(:global)
+          rf_name = var_type.sub_type.name.downcase
+          "#{' ' * indent}__UDB_HART->_#{rf_name}reg(#{index.gen_cpp(symtab, 0, indent_spaces:)})"
         else
           "#{' ' * indent}#{var.gen_cpp(symtab, 0, indent_spaces:)}.at(#{index.gen_cpp(symtab, 0, indent_spaces:)}.get())"
         end
@@ -928,9 +931,12 @@ def gen_cpp(symtab, indent = 0, indent_spaces: 2)
   class AryElementAssignmentAst < AstNode
     sig { override.params(symtab: SymbolTable, indent: Integer, indent_spaces: Integer).returns(String) }
     def gen_cpp(symtab, indent = 0, indent_spaces: 2)
-      if lhs.is_a?(Idl::IdAst) && lhs.name == "X"
-        #"#{' '*indent}  #{lhs.gen_cpp(symtab, 0, indent_spaces:)}[#{idx.gen_cpp(symtab, 0, indent_spaces:)}] = #{rhs.gen_cpp(symtab, 0, indent_spaces:)}"
-        "#{' ' * indent}__UDB_HART->_set_xreg( #{idx.gen_cpp(symtab, 0, indent_spaces:)}, #{rhs.gen_cpp(symtab, 0, indent_spaces:)})"
+      lhs_type = lhs.type(symtab)
+      if lhs_type.kind == :array &&
+         lhs_type.sub_type.is_a?(Idl::RegFileElementType) &&
+         lhs_type.qualifiers.include?(:global)
+        rf_name = lhs_type.sub_type.name.downcase
+        "#{' ' * indent}__UDB_HART->_set_#{rf_name}reg( #{idx.gen_cpp(symtab, 0, indent_spaces:)}, #{rhs.gen_cpp(symtab, 0, indent_spaces:)})"
       elsif lhs.type(symtab).kind == :bits
         "#{' ' * indent}#{lhs.gen_cpp(symtab, 0, indent_spaces:)}.setBit(#{idx.gen_cpp(symtab, 0, indent_spaces:)}, #{rhs.gen_cpp(symtab, 0, indent_spaces:)})"
       else
diff --git a/backends/cpp_hart_gen/lib/template_helpers.rb b/backends/cpp_hart_gen/lib/template_helpers.rb
index 01fd3669ee..7fdac58da8 100644
--- a/backends/cpp_hart_gen/lib/template_helpers.rb
+++ b/backends/cpp_hart_gen/lib/template_helpers.rb
@@ -156,6 +156,53 @@ def quot_str(val)
         val
       end
     end
+
+    # C++ width string for a register file element type (e.g. "64" or "VLEN").
+    # Used in template parameters like PossiblyUnknownBits<WIDTH>.
+    def rf_elem_width(rf)
+      width = rf.eval_register_length(cfg_arch)
+      width.is_a?(String) ? width : width.to_s
+    end
+
+    # Compile an IDL expression string to an AST node that responds to gen_cpp.
+    def compile_idl_expr(idl_str)
+      cfg_arch.idl_compiler.compile_expression(idl_str, cfg_arch.symtab)
+    end
+
+    # IDL Type for one register file element (Bits<WIDTH>).
+    def rf_elem_type(rf)
+      width = rf.eval_register_length(cfg_arch)
+      Idl::Type.new(:bits, width: width.is_a?(String) ? rf.max_register_length : width)
+    end
+
+    def gen_arch_read_cpp(entry) = idl_body_to_cpp(entry.arch_read)
+    def gen_arch_write_cpp(entry) = idl_body_to_cpp(entry.arch_write)
+
+    # True if the named register file (e.g. "F") has register_class: floating_point.
+    def rf_floating_point?(rf_name)
+      cfg_arch.register_files.find { |rf| rf.name == rf_name }&.register_class == "floating_point"
+    end
+
+    # Returns the base offset into udb::Reg::Enum for the named register file.
+    # Must match the enum layout in backends/cpp_hart_gen/cpp/include/udb/inst.hpp.
+    RF_ENUM_BASES = { "X" => 0, "F" => 32, "V" => 64 }.freeze
+    def rf_enum_base(rf_name)
+      RF_ENUM_BASES.fetch(rf_name) { raise "No Reg::Enum base defined for register file '#{rf_name}'" }
+    end
+
+    # All register files defined for this architecture.
+    # The ISS generates storage and accessors for all register files since
+    # for a partially-configured arch, any extension may be present.
+    def applicable_register_files
+      cfg_arch.register_files
+    end
+
+    private
+
+    def idl_body_to_cpp(body)
+      expr_str = body.strip.sub(/\Areturn\s+/, "").sub(/;\z/, "").strip
+      compile_idl_expr(expr_str).gen_cpp(cfg_arch.symtab, 0)
+    end
   end
 
   class TemplateEnv
diff --git a/backends/cpp_hart_gen/tasks.rake b/backends/cpp_hart_gen/tasks.rake
index 138922afd3..c84638a6f7 100644
--- a/backends/cpp_hart_gen/tasks.rake
+++ b/backends/cpp_hart_gen/tasks.rake
@@ -204,6 +204,7 @@ rule %r{#{CPP_HART_GEN_DST}/[^/]+/build/Makefile} => [
     "-S#{CPP_HART_GEN_DST}/#{build_name}",
     "-B#{CPP_HART_GEN_DST}/#{build_name}/build",
     "-DCMAKE_CXX_COMPILER=#{$root}/bin/g++",
+    "-DCOVERAGE_COMMAND=#{$root}/bin/gcov",
     "-DCONFIG_LIST=\"#{ENV['CONFIG'].gsub(',', ';')}\"",
     "-DCMAKE_EXPORT_COMPILE_COMMANDS=ON",
     "-DCMAKE_BUILD_TYPE=#{cmake_build_type}",
@@ -420,6 +421,7 @@ namespace :test do
     Dir.chdir "#{CPP_HART_GEN_DST}/#{build_name}/build" do
       sh "make -j #{$jobs} test_bits_directed"
       sh "make -j #{$jobs} test_bits_random"
+      sh "make -j #{$jobs} test_regfile"
       sh "ctest -T coverage -T test"
     end
   end
diff --git a/backends/cpp_hart_gen/templates/hart.hxx.erb b/backends/cpp_hart_gen/templates/hart.hxx.erb
index a0df0e6224..10284716b7 100644
--- a/backends/cpp_hart_gen/templates/hart.hxx.erb
+++ b/backends/cpp_hart_gen/templates/hart.hxx.erb
@@ -79,10 +79,10 @@ namespace udb {
     public:
       <%- cfg_arch.globals.each do |global| -%>
       <%- if global.is_a?(Idl::GlobalWithInitializationAst) -%>
-      <%- if global.type(cfg_arch.symtab).const? -%>
-      static <%= global.type(cfg_arch.symtab).const? ? 'constexpr ' : '' %><%= global.type(cfg_arch.symtab).to_cxx %> <%= global.id %> = <%= global.rhs.gen_cpp(cfg_arch.symtab, 0) %>;
+      <%- if global.is_a?(Idl::GlobalWithInitializationAst) && global.type(cfg_arch.symtab).const? && global.rhs.const_eval?(cfg_arch.symtab) -%>
+      static constexpr <%= global.type(cfg_arch.symtab).to_cxx %> <%= global.id %> = <%= global.rhs.gen_cpp(cfg_arch.symtab, 0) %>;
       <%- else -%>
-      static <%= global.type(cfg_arch.symtab).to_cxx %> <%= global.id %>;
+      static <%= global.type(cfg_arch.symtab).to_cxx.gsub("const ", "") %> <%= global.id %>;
       <%- end -%>
       <%- else -%>
       static <%= global.type(cfg_arch.symtab).to_cxx %> <%= global.id %>;
@@ -94,13 +94,18 @@ namespace udb {
       static constexpr unsigned MXLEN = <%= cfg_arch.mxlen.nil? ? 64 : cfg_arch.mxlen %>;
       using XReg = Bits<MXLEN>;
 
+#define __UDB_FUNC_CALL this->
       <%= hart_name -%>(uint64_t hart_id, SocType& soc, const Config& cfg)
         : HartBase<SocType>(hart_id, soc, cfg),
           m_params(cfg),
-          <%- if cfg_arch.mxlen.nil? -%>
-          m_xregs {
-            <%- 32.times do |i| -%>
-            { WidthArg(m_params.MXLEN.value()) },
+          <%- applicable_register_files.each do |rf| -%>
+          <%- rf_name = rf.name.downcase -%>
+          <%- width = rf.eval_register_length(cfg_arch) -%>
+          <%- next unless width.is_a?(String) -%>
+          <%- param_name = width -%>
+          m_<%= rf_name %>regs {
+            <%- rf.registers.count.times do -%>
+            PossiblyUnknownRuntimeBits<<%= rf.max_register_length %>>{ WidthArg(m_params.<%= param_name %>.has_value() ? static_cast<uint64_t>(m_params.<%= param_name %>.value().get()) : static_cast<uint64_t>(<%= rf.max_register_length %>)) },
             <%- end -%>
           },
           <%- end -%>
@@ -127,7 +132,14 @@ namespace udb {
             <%- end -%>
           }
       {
-        m_xregs[0] = 0_b; // set x0
+        <%- applicable_register_files.each do |rf| -%>
+        <%- rf_name = rf.name.downcase -%>
+        <%- rf.registers.each do |r| -%>
+        <%- next if r.reset_value.nil? -%>
+        <%- reset_cpp = compile_idl_expr(r.reset_value).gen_cpp(cfg_arch.symtab, 0) -%>
+        m_<%= rf_name %>regs[<%= r.index %>] = <%= reset_cpp %>;
+        <%- end -%>
+        <%- end -%>
       }
 
       void reset(uint64_t reset_pc) override {
@@ -137,7 +149,7 @@ namespace udb {
 
         <%- cfg_arch.globals.each do |global| -%>
         <%- if global.is_a?(Idl::GlobalWithInitializationAst) -%>
-        <%- next if global.type(cfg_arch.symtab).const? -%>
+        <%- next if global.type(cfg_arch.symtab).const? && global.rhs.const_eval?(cfg_arch.symtab) -%>
         <%- lhs_t = global.type(cfg_arch.symtab) -%>
         <%- rhs_t = global.rhs.type(cfg_arch.symtab) -%>
         <%- rhs_cpp = global.rhs.gen_cpp(cfg_arch.symtab, 0) -%>
@@ -154,6 +166,7 @@ namespace udb {
 
         m_csrs.reset();
       }
+#undef __UDB_FUNC_CALL
 
       bool implemented_version_Q_(const ExtensionName& ext, const VersionRequirement& req) const override
       {
@@ -323,40 +336,74 @@ namespace udb {
 
       unsigned mxlen() override { return MXLEN; }
 
-      uint64_t xreg(unsigned num) const override {
-        if (num >= 32) {
-          throw std::out_of_range("X register indices are 0 - 31, inclusive");
+      <%- applicable_register_files.each do |rf| -%>
+      <%- rf_name = rf.name.downcase -%>
+      <%- bits_width = rf_elem_width(rf) -%>
+      <%- rf_width = rf.eval_register_length(cfg_arch) -%>
+      <%- is_runtime_width = rf_width.is_a?(String) -%>
+      <%- accessor_type = is_runtime_width ? "PossiblyUnknownRuntimeBits<#{rf.max_register_length}>" : "PossiblyUnknownBits<#{bits_width}>" -%>
+      <%- setter_param_type = is_runtime_width ? "_PossiblyUnknownRuntimeBits<#{rf.max_register_length}, false>" : "_PossiblyUnknownBits<#{bits_width}, false>" -%>
+      <%- entries_with_read = rf.registers.select { |r| r.arch_read } -%>
+      <%- entries_with_write = rf.registers.select { |r| r.arch_write } -%>
+
+      uint64_t <%= rf_name %>reg(unsigned num) const override {
+        if (num >= <%= rf.registers.count %>) {
+          throw std::out_of_range("<%= rf.name %> register indices are 0 - <%= rf.registers.count - 1 %>, inclusive");
         }
-        return _xreg(num).get();
+        <%- if is_runtime_width -%>
+        return static_cast<uint64_t>(_<%= rf_name %>reg(num).get().get_ui());
+        <%- else -%>
+        return _<%= rf_name %>reg(num).get();
+        <%- end -%>
       }
 
-      PossiblyUnknownBits<MXLEN> _xreg(unsigned num) const {
-        return m_xregs[num];
+      <%= accessor_type %> _<%= rf_name %>reg(unsigned num) const {
+        <%- if entries_with_read.any? -%>
+        switch (num) {
+          <%- entries_with_read.each do |r| -%>
+          case <%= r.index %>: return <%= accessor_type %>(<%= gen_arch_read_cpp(r) %>);
+          <%- end -%>
+          default: return m_<%= rf_name %>regs[num];
+        }
+        <%- else -%>
+        return m_<%= rf_name %>regs[num];
+        <%- end -%>
       }
 
       template <template <unsigned, bool> class BitsClass, unsigned N, bool Signed>
         requires (BitsType<BitsClass<N, Signed>>)
-      PossiblyUnknownBits<MXLEN> _xreg(const BitsClass<N, Signed>& num) const {
-        return m_xregs[num.get()];
+      <%= accessor_type %> _<%= rf_name %>reg(const BitsClass<N, Signed>& num) const {
+        return _<%= rf_name %>reg(static_cast<unsigned>(num.get()));
       }
 
-
-      // XRegister<MXLEN>& xregRef(unsigned num) { return m_xregs[num]; }
-
-      void set_xreg(unsigned num, uint64_t value) override {
-        if (num >= 32) {
-          throw std::out_of_range("X register indices are 0 - 31, inclusive");
+      void set_<%= rf_name %>reg(unsigned num, uint64_t value) override {
+        if (num >= <%= rf.registers.count %>) {
+          throw std::out_of_range("<%= rf.name %> register indices are 0 - <%= rf.registers.count - 1 %>, inclusive");
         }
-        _set_xreg(Bits<8>{num}, Bits<MXLEN>{value});
+        <%- if is_runtime_width -%>
+        _set_<%= rf_name %>reg(Bits<8>{num}, <%= accessor_type %>{value});
+        <%- else -%>
+        _set_<%= rf_name %>reg(Bits<8>{num}, Bits<<%= bits_width %>>{value});
+        <%- end -%>
       }
 
       template < template <unsigned, bool> class IdxType, unsigned IdxN, bool IdxSigned >
         requires (BitsType<IdxType<IdxN, IdxSigned>>)
-      void _set_xreg(const IdxType<IdxN, IdxSigned>& num, const _PossiblyUnknownBits<MXLEN, false>& value) {
-        if (num != 0_b) {
-          m_xregs[static_cast<unsigned>(num.get())] = value;
+      void _set_<%= rf_name %>reg(const IdxType<IdxN, IdxSigned>& num, const <%= setter_param_type %>& value) {
+        <%- if entries_with_write.any? -%>
+        auto to_store = value;
+        switch (static_cast<unsigned>(num.get())) {
+          <%- entries_with_write.each do |r| -%>
+          case <%= r.index %>: to_store = <%= gen_arch_write_cpp(r) %>; break;
+          <%- end -%>
+          default: break;
         }
+        m_<%= rf_name %>regs[static_cast<unsigned>(num.get())] = to_store;
+        <%- else -%>
+        m_<%= rf_name %>regs[static_cast<unsigned>(num.get())] = value;
+        <%- end -%>
       }
+      <%- end -%>
 
       void printState(FILE* out = stdout) const override;
 
@@ -487,10 +534,11 @@ namespace udb {
 
       <%= name_of(:params, cfg_arch) %> m_params;
 
-      <%- if cfg_arch.mxlen.nil? -%>
-      std::array<PossiblyUnknownRuntimeBits<64>, 32> m_xregs;
-      <%- else -%>
-      std::array<PossiblyUnknownBits<MXLEN>, 32> m_xregs;
+      <%- applicable_register_files.each do |rf| -%>
+      <%- rf_name = rf.name.downcase -%>
+      <%- width = rf.eval_register_length(cfg_arch) -%>
+      <%- cpp_type = width.is_a?(String) ? "PossiblyUnknownRuntimeBits<#{rf.max_register_length}>" : "PossiblyUnknownBits<#{width}>" -%>
+      std::array<<%= cpp_type %>, <%= rf.registers.count %>> m_<%= rf_name %>regs;
       <%- end -%>
 
       <%= name_of(:csr_container, cfg_arch) %><SocType> m_csrs;
diff --git a/backends/cpp_hart_gen/templates/hart_impl.hxx.erb b/backends/cpp_hart_gen/templates/hart_impl.hxx.erb
index 8a4aefdc24..7c3b25191f 100644
--- a/backends/cpp_hart_gen/templates/hart_impl.hxx.erb
+++ b/backends/cpp_hart_gen/templates/hart_impl.hxx.erb
@@ -13,27 +13,28 @@ using namespace std::literals;
 namespace udb {
 
   <%- cfg_arch.globals.each do |global| -%>
-  <%- next if global.type(cfg_arch.symtab).const? -%>
+  <%- next if global.is_a?(Idl::GlobalWithInitializationAst) && global.type(cfg_arch.symtab).const? && global.rhs.const_eval?(cfg_arch.symtab) -%>
   template <SocModel SocType>
-  <%= global.type(cfg_arch.symtab).to_cxx %> <%= name_of(:hart, cfg_arch) %><SocType>::<%= global.id %>;
+  <%= global.type(cfg_arch.symtab).to_cxx.gsub("const ", "") %> <%= name_of(:hart, cfg_arch) %><SocType>::<%= global.id %>;
   <%- end -%>
 
   template <SocModel SocType>
   void udb::<%= name_of(:hart, cfg_arch) %><SocType>::printState(FILE* out) const {
     fmt::print(out, "Hart %u:\n", this->m_hart_id);
-    if constexpr (sizeof(XReg) == 8) {
-      fmt::print(out, "PC: {:#18x}\n", m_pc);
-      for (int i=0; i<16; i++) {
-        fmt::print(out, "x{:2}: {:#18x}\tx{:2}: {:#18x}\n", i, _xreg(i), i + 16, _xreg(16 + 1));
-      }
-    } else if constexpr (sizeof(XReg) == 4) {
-      fmt::print(out, "PC: {:#10x}\n", m_pc);
-      for (int i=0; i<16; i++) {
-        fmt::print(out, "x{:2}: {:#10x}\tx{:2}: {:#10x}\n", i, _xreg(i), i + 16, _xreg(16 + 1));
-      }
-    } else {
-      udb_assert(false, "unsupported xlen");
+    fmt::print(out, "PC: {:#x}\n", m_pc.get());
+    <%- applicable_register_files.each do |rf| -%>
+    <%- rf_name = rf.name.downcase -%>
+    <%- rf_width = rf.eval_register_length(cfg_arch) -%>
+    <%- is_rt_width = rf_width.is_a?(String) -%>
+    fmt::print(out, "<%= rf.name %> registers:\n");
+    for (unsigned i = 0; i < <%= rf.registers.count %>; i++) {
+      <%- if is_rt_width -%>
+      fmt::print(out, "<%= rf_name %>{}: {:#x}\n", i, static_cast<uint64_t>(_<%= rf_name %>reg(i).get().get_ui()));
+      <%- else -%>
+      fmt::print(out, "<%= rf_name %>{}: {:#x}\n", i, _<%= rf_name %>reg(i).get());
+      <%- end -%>
     }
+    <%- end -%>
   }
 
 #define __UDB_CONST_GLOBAL(global_name) <%= name_of(:hart, cfg_arch) %><SocType>::global_name
diff --git a/backends/cpp_hart_gen/templates/inst.hxx.erb b/backends/cpp_hart_gen/templates/inst.hxx.erb
index 953c1bcb1b..94042a0d7a 100644
--- a/backends/cpp_hart_gen/templates/inst.hxx.erb
+++ b/backends/cpp_hart_gen/templates/inst.hxx.erb
@@ -201,7 +201,7 @@ namespace udb {
             <%- begin -%>
         <%- src_regs = pruned_ast.find_src_registers(symtab) %>
         <%- symtab.release -%>
-        return {<%= src_regs.map { |r| r.is_a?(Integer) ? "{Reg::X#{r}}" : "{Reg(#{r})}" }.join(", ") %>};
+        return {<%= src_regs.map { |rf_name, idx| idx.is_a?(Integer) ? "{Reg::#{rf_name}#{idx}}" : "{Reg::from_rf_index(#{idx}, #{rf_enum_base(rf_name)}u)}" }.join(", ") %>};
       <%- rescue Idl::ComplexRegDetermination -%>
         throw ComplexRegDetermination();
       <%- end -%>
@@ -211,7 +211,7 @@ namespace udb {
             <%- begin -%>
         <%- src_regs = pruned_ast.find_src_registers(symtab) %>
         <%- symtab.release -%>
-        return {<%= src_regs.map { |r| r.is_a?(Integer) ? "{Reg::X#{r}}" : "{Reg(#{r})}" }.join(", ") %>};
+        return {<%= src_regs.map { |rf_name, idx| idx.is_a?(Integer) ? "{Reg::#{rf_name}#{idx}}" : "{Reg::from_rf_index(#{idx}, #{rf_enum_base(rf_name)}u)}" }.join(", ") %>};
       <%- rescue Idl::ComplexRegDetermination -%>
         throw ComplexRegDetermination();
       <%- end -%>
@@ -222,7 +222,7 @@ namespace udb {
             <%- begin -%>
         <%- src_regs = pruned_ast.find_src_registers(symtab) %>
         <%- symtab.release -%>
-        return {<%= src_regs.map { |r| r.is_a?(Integer) ? "{Reg::X#{r}}" : "{Reg(#{r})}" }.join(", ") %>};
+        return {<%= src_regs.map { |rf_name, idx| idx.is_a?(Integer) ? "{Reg::#{rf_name}#{idx}}" : "{Reg::from_rf_index(#{idx}, #{rf_enum_base(rf_name)}u)}" }.join(", ") %>};
       <%- rescue Idl::ComplexRegDetermination -%>
         throw ComplexRegDetermination();
       <%- end -%>
@@ -232,7 +232,7 @@ namespace udb {
             <%- begin -%>
         <%- src_regs = pruned_ast.find_src_registers(symtab) %>
         <%- symtab.release -%>
-        return {<%= src_regs.map { |r| r.is_a?(Integer) ? "{Reg::X#{r}}" : "{Reg(#{r})}" }.join(", ") %>};
+        return {<%= src_regs.map { |rf_name, idx| idx.is_a?(Integer) ? "{Reg::#{rf_name}#{idx}}" : "{Reg::from_rf_index(#{idx}, #{rf_enum_base(rf_name)}u)}" }.join(", ") %>};
       <%- rescue Idl::ComplexRegDetermination -%>
         throw ComplexRegDetermination();
       <%- end -%>
@@ -253,7 +253,7 @@ namespace udb {
             <%- begin -%>
         <%- dst_regs = pruned_ast.find_dst_registers(symtab) %>
         <%- symtab.release -%>
-        return {<%= dst_regs.map { |r| r.is_a?(Integer) ? "{Reg::X#{r}}" : "{Reg(#{r})}" }.join(", ") %>};
+        return {<%= dst_regs.map { |rf_name, idx| idx.is_a?(Integer) ? "{Reg::#{rf_name}#{idx}}" : "{Reg::from_rf_index(#{idx}, #{rf_enum_base(rf_name)}u)}" }.join(", ") %>};
       <%- rescue Idl::ComplexRegDetermination -%>
         throw ComplexRegDetermination();
       <%- end -%>
@@ -263,7 +263,7 @@ namespace udb {
             <%- begin -%>
         <%- dst_regs = pruned_ast.find_dst_registers(symtab) %>
         <%- symtab.release -%>
-        return {<%= dst_regs.map { |r| r.is_a?(Integer) ? "{Reg::X#{r}}" : "{Reg(#{r})}" }.join(", ") %>};
+        return {<%= dst_regs.map { |rf_name, idx| idx.is_a?(Integer) ? "{Reg::#{rf_name}#{idx}}" : "{Reg::from_rf_index(#{idx}, #{rf_enum_base(rf_name)}u)}" }.join(", ") %>};
       <%- rescue Idl::ComplexRegDetermination -%>
         throw ComplexRegDetermination();
       <%- end -%>
@@ -274,7 +274,7 @@ namespace udb {
             <%- begin -%>
         <%- dst_regs = pruned_ast.find_dst_registers(symtab) %>
         <%- symtab.release -%>
-        return {<%= dst_regs.map { |r| r.is_a?(Integer) ? "{Reg::X#{r}}" : "{Reg(#{r})}" }.join(", ") %>};
+        return {<%= dst_regs.map { |rf_name, idx| idx.is_a?(Integer) ? "{Reg::#{rf_name}#{idx}}" : "{Reg::from_rf_index(#{idx}, #{rf_enum_base(rf_name)}u)}" }.join(", ") %>};
       <%- rescue Idl::ComplexRegDetermination -%>
         throw ComplexRegDetermination();
       <%- end -%>
@@ -284,7 +284,7 @@ namespace udb {
             <%- begin -%>
         <%- dst_regs = pruned_ast.find_dst_registers(symtab) %>
         <%- symtab.release -%>
-        return {<%= dst_regs.map { |r| r.is_a?(Integer) ? "{Reg::X#{r}}" : "{Reg(#{r})}" }.join(", ") %>};
+        return {<%= dst_regs.map { |rf_name, idx| idx.is_a?(Integer) ? "{Reg::#{rf_name}#{idx}}" : "{Reg::from_rf_index(#{idx}, #{rf_enum_base(rf_name)}u)}" }.join(", ") %>};
       <%- rescue Idl::ComplexRegDetermination -%>
         throw ComplexRegDetermination();
       <%- end -%>
diff --git a/spec/schemas/register_file_schema.json b/spec/schemas/register_file_schema.json
index a7e511d967..f6e4835eb8 100644
--- a/spec/schemas/register_file_schema.json
+++ b/spec/schemas/register_file_schema.json
@@ -27,6 +27,10 @@
         "when": {
           "$ref": "schema_defs.json#/$defs/requires_entry"
         },
+        "reset_value": {
+          "type": "string",
+          "description": "IDL literal expression for the reset value (e.g., '0'). Omit if reset state is unknown."
+        },
         "arch_read()": {
           "type": "string",
           "description": "Function describing the architecturally defined read behavior. Use this for architecturally mandated effects (e.g., x0 always reads as zero)."
@@ -74,7 +78,7 @@
         "name",
         "long_name",
         "description",
-        "register_length",
+        "register_length()",
         "registers"
       ],
       "additionalProperties": false,
@@ -103,8 +107,9 @@
           "type": "string",
           "enum": ["general_purpose", "floating_point", "vector"]
         },
-        "register_length": {
-          "$ref": "schema_defs.json#/$defs/bit_length_value"
+        "register_length()": {
+          "type": "string",
+          "description": "IDL function body returning the register width in bits. May reference params (MXLEN, VLEN) or implemented?(). Example: 'return MXLEN;'"
         },
         "registers": {
           "type": "array",
diff --git a/spec/std/isa/inst/F/fadd.s.yaml b/spec/std/isa/inst/F/fadd.s.yaml
index 31afcfed6f..30ad2e9e55 100644
--- a/spec/std/isa/inst/F/fadd.s.yaml
+++ b/spec/std/isa/inst/F/fadd.s.yaml
@@ -34,19 +34,19 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
   RoundingMode mode = rm_to_mode(rm, $encoding);
-  Bits<32> a = f[fs1];
-  Bits<32> b = f[fs2];
+  Bits<32> a = F[fs1];
+  Bits<32> b = F[fs2];
 
   if (implemented?(ExtensionName::D)) {
     # check for incorrectly NaN-boxed inputs
-    if (f[fs1][63:32] != 32'hffffffff) {
+    if (F[fs1][63:32] != 32'hffffffff) {
       a = SP_CANONICAL_NAN;
     }
-    if (f[fs2][63:32] != 32'hffffffff) {
+    if (F[fs2][63:32] != 32'hffffffff) {
       b = SP_CANONICAL_NAN;
     }
   }
 
-  f[fd] = f32_add(a, b, mode);
+  F[fd] = f32_add(a, b, mode);
 
   mark_f_state_dirty();
diff --git a/spec/std/isa/inst/F/fclass.s.yaml b/spec/std/isa/inst/F/fclass.s.yaml
index acdc112af3..48c15dfa80 100644
--- a/spec/std/isa/inst/F/fclass.s.yaml
+++ b/spec/std/isa/inst/F/fclass.s.yaml
@@ -51,11 +51,11 @@ data_independent_timing: false
 operation(): |
   check_f_ok($encoding);
 
-  Bits<32> sp_value = f[fs1][31:0];
+  Bits<32> sp_value = F[fs1][31:0];
 
   if (implemented?(ExtensionName::D)) {
     # check for an incorrectly NaN-boxed value
-    if (f[fs1][63:32] != 32'hffffffff) {
+    if (F[fs1][63:32] != 32'hffffffff) {
       sp_value = SP_CANONICAL_NAN;
     }
   }
diff --git a/spec/std/isa/inst/F/fcvt.l.s.yaml b/spec/std/isa/inst/F/fcvt.l.s.yaml
index a70eb2ee49..b381b2858e 100644
--- a/spec/std/isa/inst/F/fcvt.l.s.yaml
+++ b/spec/std/isa/inst/F/fcvt.l.s.yaml
@@ -34,4 +34,4 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
   RoundingMode rounding_mode = rm_to_mode(rm, $encoding);
-  X[xd] = f32_to_i64(f[fs1], rounding_mode);
+  X[xd] = f32_to_i64(F[fs1], rounding_mode);
diff --git a/spec/std/isa/inst/F/fcvt.lu.s.yaml b/spec/std/isa/inst/F/fcvt.lu.s.yaml
index a00f4283c0..080c0d34e5 100644
--- a/spec/std/isa/inst/F/fcvt.lu.s.yaml
+++ b/spec/std/isa/inst/F/fcvt.lu.s.yaml
@@ -34,4 +34,4 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
   RoundingMode rounding_mode = rm_to_mode(rm, $encoding);
-  X[xd] = f32_to_ui64(f[fs1], rounding_mode);
+  X[xd] = f32_to_ui64(F[fs1], rounding_mode);
diff --git a/spec/std/isa/inst/F/fcvt.s.l.yaml b/spec/std/isa/inst/F/fcvt.s.l.yaml
index 6de5a3e842..302786a25b 100644
--- a/spec/std/isa/inst/F/fcvt.s.l.yaml
+++ b/spec/std/isa/inst/F/fcvt.s.l.yaml
@@ -34,5 +34,5 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
   RoundingMode rounding_mode = rm_to_mode(rm, $encoding);
-  f[fd] = i64_to_f32(X[xs1], rounding_mode);
+  F[fd] = i64_to_f32(X[xs1], rounding_mode);
   mark_f_state_dirty();
diff --git a/spec/std/isa/inst/F/fcvt.s.lu.yaml b/spec/std/isa/inst/F/fcvt.s.lu.yaml
index 929c0bdf59..75aec1bee2 100644
--- a/spec/std/isa/inst/F/fcvt.s.lu.yaml
+++ b/spec/std/isa/inst/F/fcvt.s.lu.yaml
@@ -33,5 +33,5 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
   RoundingMode rounding_mode = rm_to_mode(rm, $encoding);
-  f[fd] = ui64_to_f32(X[xs1], rounding_mode);
+  F[fd] = ui64_to_f32(X[xs1], rounding_mode);
   mark_f_state_dirty();
diff --git a/spec/std/isa/inst/F/fcvt.s.w.yaml b/spec/std/isa/inst/F/fcvt.s.w.yaml
index c15770ae09..4d1c645e2b 100644
--- a/spec/std/isa/inst/F/fcvt.s.w.yaml
+++ b/spec/std/isa/inst/F/fcvt.s.w.yaml
@@ -41,5 +41,5 @@ data_independent_timing: false
 operation(): |
   check_f_ok($encoding);
   RoundingMode rounding_mode = rm_to_mode(rm, $encoding);
-  f[fd] = i32_to_f32(X[xs1], rounding_mode);
+  F[fd] = i32_to_f32(X[xs1], rounding_mode);
   mark_f_state_dirty();
diff --git a/spec/std/isa/inst/F/fcvt.s.wu.yaml b/spec/std/isa/inst/F/fcvt.s.wu.yaml
index c4140a987c..48e9c526aa 100644
--- a/spec/std/isa/inst/F/fcvt.s.wu.yaml
+++ b/spec/std/isa/inst/F/fcvt.s.wu.yaml
@@ -41,5 +41,5 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
   RoundingMode rounding_mode = rm_to_mode(rm, $encoding);
-  f[fd] = ui32_to_f32(X[xs1], rounding_mode);
+  F[fd] = ui32_to_f32(X[xs1], rounding_mode);
   mark_f_state_dirty();
diff --git a/spec/std/isa/inst/F/fcvt.w.s.yaml b/spec/std/isa/inst/F/fcvt.w.s.yaml
index 8b16449fa0..67e0b8f04f 100644
--- a/spec/std/isa/inst/F/fcvt.w.s.yaml
+++ b/spec/std/isa/inst/F/fcvt.w.s.yaml
@@ -60,4 +60,4 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
   RoundingMode rounding_mode = rm_to_mode(rm, $encoding);
-  X[xd] = $signed(f32_to_i32(f[fs1], rounding_mode));
+  X[xd] = $signed(f32_to_i32(F[fs1], rounding_mode));
diff --git a/spec/std/isa/inst/F/fcvt.wu.s.yaml b/spec/std/isa/inst/F/fcvt.wu.s.yaml
index 2fbbb06bb9..08ec02c1cb 100644
--- a/spec/std/isa/inst/F/fcvt.wu.s.yaml
+++ b/spec/std/isa/inst/F/fcvt.wu.s.yaml
@@ -59,4 +59,4 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
   RoundingMode rounding_mode = rm_to_mode(rm, $encoding);
-  X[xd] = $signed(f32_to_ui32(f[fs1], rounding_mode));
+  X[xd] = $signed(f32_to_ui32(F[fs1], rounding_mode));
diff --git a/spec/std/isa/inst/F/fdiv.s.yaml b/spec/std/isa/inst/F/fdiv.s.yaml
index 6c2321a967..09ac1b9fef 100644
--- a/spec/std/isa/inst/F/fdiv.s.yaml
+++ b/spec/std/isa/inst/F/fdiv.s.yaml
@@ -34,5 +34,5 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
   RoundingMode mode = rm_to_mode(rm, $encoding);
-  f[fd] = f32_div(f[fs1], f[fs2], mode);
+  F[fd] = f32_div(F[fs1], F[fs2], mode);
   mark_f_state_dirty();
diff --git a/spec/std/isa/inst/F/feq.s.yaml b/spec/std/isa/inst/F/feq.s.yaml
index f54968e0e8..afc7b4e55d 100644
--- a/spec/std/isa/inst/F/feq.s.yaml
+++ b/spec/std/isa/inst/F/feq.s.yaml
@@ -34,8 +34,8 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
 
-  Bits<32> sp_value_a = f[fs1][31:0];
-  Bits<32> sp_value_b = f[fs2][31:0];
+  Bits<32> sp_value_a = F[fs1][31:0];
+  Bits<32> sp_value_b = F[fs2][31:0];
 
   if (is_sp_nan?(sp_value_a) || is_sp_nan?(sp_value_b)) {
     if (is_sp_signaling_nan?(sp_value_a) || is_sp_signaling_nan?(sp_value_b)) {
diff --git a/spec/std/isa/inst/F/fle.s.yaml b/spec/std/isa/inst/F/fle.s.yaml
index 3c79cdcd82..9b65d12c2b 100644
--- a/spec/std/isa/inst/F/fle.s.yaml
+++ b/spec/std/isa/inst/F/fle.s.yaml
@@ -34,8 +34,8 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
 
-  Bits<32> sp_value_a = f[fs1][31:0];
-  Bits<32> sp_value_b = f[fs2][31:0];
+  Bits<32> sp_value_a = F[fs1][31:0];
+  Bits<32> sp_value_b = F[fs2][31:0];
   Bits<1> sign_a = sp_value_a[31];
   Bits<1> sign_b = sp_value_b[31];
 
diff --git a/spec/std/isa/inst/F/fleq.s.yaml b/spec/std/isa/inst/F/fleq.s.yaml
index c584de332b..997a3006fa 100644
--- a/spec/std/isa/inst/F/fleq.s.yaml
+++ b/spec/std/isa/inst/F/fleq.s.yaml
@@ -32,8 +32,8 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
 
-  Bits<32> sp_value_a = f[fs1][31:0];
-  Bits<32> sp_value_b = f[fs2][31:0];
+  Bits<32> sp_value_a = F[fs1][31:0];
+  Bits<32> sp_value_b = F[fs2][31:0];
 
   if (is_sp_nan?(sp_value_a) || is_sp_nan?(sp_value_b)) {
     # Quiet comparison: only set NV for signaling NaN
diff --git a/spec/std/isa/inst/F/flt.s.yaml b/spec/std/isa/inst/F/flt.s.yaml
index 0c6b197871..e3e5a57fb0 100644
--- a/spec/std/isa/inst/F/flt.s.yaml
+++ b/spec/std/isa/inst/F/flt.s.yaml
@@ -34,8 +34,8 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
 
-  Bits<32> sp_value_a = f[fs1][31:0];
-  Bits<32> sp_value_b = f[fs2][31:0];
+  Bits<32> sp_value_a = F[fs1][31:0];
+  Bits<32> sp_value_b = F[fs2][31:0];
   Bits<1> sign_a = sp_value_a[31];
   Bits<1> sign_b = sp_value_b[31];
 
diff --git a/spec/std/isa/inst/F/fltq.s.yaml b/spec/std/isa/inst/F/fltq.s.yaml
index 181c43dc1f..e87142847f 100644
--- a/spec/std/isa/inst/F/fltq.s.yaml
+++ b/spec/std/isa/inst/F/fltq.s.yaml
@@ -32,8 +32,8 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
 
-  Bits<32> sp_value_a = f[fs1][31:0];
-  Bits<32> sp_value_b = f[fs2][31:0];
+  Bits<32> sp_value_a = F[fs1][31:0];
+  Bits<32> sp_value_b = F[fs2][31:0];
 
   if (is_sp_nan?(sp_value_a) || is_sp_nan?(sp_value_b)) {
     # Quiet comparison: only set NV for signaling NaN
diff --git a/spec/std/isa/inst/F/flw.yaml b/spec/std/isa/inst/F/flw.yaml
index 5bff7b0abf..bb48244d8f 100644
--- a/spec/std/isa/inst/F/flw.yaml
+++ b/spec/std/isa/inst/F/flw.yaml
@@ -38,9 +38,9 @@ operation(): |
   Bits<32> sp_value = read_memory(32, virtual_address, $encoding);
 
   if (implemented?(ExtensionName::D)) {
-    f[fd] = nan_box(32, 64, sp_value);
+    F[fd] = nan_box(32, 64, sp_value);
   } else {
-    f[fd] = sp_value;
+    F[fd] = sp_value;
   }
 
   mark_f_state_dirty();
diff --git a/spec/std/isa/inst/F/fmadd.s.yaml b/spec/std/isa/inst/F/fmadd.s.yaml
index 41691d0d5b..c629f19429 100644
--- a/spec/std/isa/inst/F/fmadd.s.yaml
+++ b/spec/std/isa/inst/F/fmadd.s.yaml
@@ -35,5 +35,5 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
   RoundingMode mode = rm_to_mode(rm, $encoding);
-  f[fd] = f32_muladd(f[fs1], f[fs2], f[fs3], F32MulAddOp::Softfloat_mulAdd_addC, mode);
+  F[fd] = f32_muladd(F[fs1], F[fs2], F[fs3], F32MulAddOp::Softfloat_mulAdd_addC, mode);
   mark_f_state_dirty();
diff --git a/spec/std/isa/inst/F/fmax.s.yaml b/spec/std/isa/inst/F/fmax.s.yaml
index 0503f50ea5..cd97264b33 100644
--- a/spec/std/isa/inst/F/fmax.s.yaml
+++ b/spec/std/isa/inst/F/fmax.s.yaml
@@ -41,8 +41,8 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
 
-  Bits<32> sp_value_a = f[fs1][31:0];
-  Bits<32> sp_value_b = f[fs2][31:0];
+  Bits<32> sp_value_a = F[fs1][31:0];
+  Bits<32> sp_value_b = F[fs2][31:0];
 
   if (is_sp_nan?(sp_value_a) || is_sp_nan?(sp_value_b)) {
     if (is_sp_signaling_nan?(sp_value_a) || is_sp_signaling_nan?(sp_value_b)) {
@@ -50,11 +50,11 @@ operation(): |
     }
     # If both are NaN, return canonical NaN; otherwise return the non-NaN operand
     if (is_sp_nan?(sp_value_a) && is_sp_nan?(sp_value_b)) {
-      f[fd] = SP_CANONICAL_NAN;
+      F[fd] = SP_CANONICAL_NAN;
     } else if (is_sp_nan?(sp_value_a)) {
-      f[fd] = sp_value_b;
+      F[fd] = sp_value_b;
     } else {
-      f[fd] = sp_value_a;
+      F[fd] = sp_value_a;
     }
   } else {
     Boolean sign_a = sp_value_a[31] == 1;
@@ -66,6 +66,6 @@ operation(): |
     } else {
       a_lt_b = (sp_value_a != sp_value_b) && (sign_a != (sp_value_a < sp_value_b));
     }
-    f[fd] = a_lt_b ? sp_value_b : sp_value_a;
+    F[fd] = a_lt_b ? sp_value_b : sp_value_a;
   }
   mark_f_state_dirty();
diff --git a/spec/std/isa/inst/F/fmin.s.yaml b/spec/std/isa/inst/F/fmin.s.yaml
index 81847043b4..66c7c4e22c 100644
--- a/spec/std/isa/inst/F/fmin.s.yaml
+++ b/spec/std/isa/inst/F/fmin.s.yaml
@@ -41,8 +41,8 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
 
-  Bits<32> sp_value_a = f[fs1][31:0];
-  Bits<32> sp_value_b = f[fs2][31:0];
+  Bits<32> sp_value_a = F[fs1][31:0];
+  Bits<32> sp_value_b = F[fs2][31:0];
 
   if (is_sp_nan?(sp_value_a) || is_sp_nan?(sp_value_b)) {
     if (is_sp_signaling_nan?(sp_value_a) || is_sp_signaling_nan?(sp_value_b)) {
@@ -50,11 +50,11 @@ operation(): |
     }
     # If both are NaN, return canonical NaN; otherwise return the non-NaN operand
     if (is_sp_nan?(sp_value_a) && is_sp_nan?(sp_value_b)) {
-      f[fd] = SP_CANONICAL_NAN;
+      F[fd] = SP_CANONICAL_NAN;
     } else if (is_sp_nan?(sp_value_a)) {
-      f[fd] = sp_value_b;
+      F[fd] = sp_value_b;
     } else {
-      f[fd] = sp_value_a;
+      F[fd] = sp_value_a;
     }
   } else {
     Boolean sign_a = sp_value_a[31] == 1;
@@ -66,6 +66,6 @@ operation(): |
     } else {
       a_lt_b = (sp_value_a != sp_value_b) && (sign_a != (sp_value_a < sp_value_b));
     }
-    f[fd] = a_lt_b ? sp_value_a : sp_value_b;
+    F[fd] = a_lt_b ? sp_value_a : sp_value_b;
   }
   mark_f_state_dirty();
diff --git a/spec/std/isa/inst/F/fmsub.s.yaml b/spec/std/isa/inst/F/fmsub.s.yaml
index 26e4509b22..1aa2633ad5 100644
--- a/spec/std/isa/inst/F/fmsub.s.yaml
+++ b/spec/std/isa/inst/F/fmsub.s.yaml
@@ -35,5 +35,5 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
   RoundingMode mode = rm_to_mode(rm, $encoding);
-  f[fd] = f32_muladd(f[fs1], f[fs2], f[fs3], F32MulAddOp::Softfloat_mulAdd_subC, mode);
+  F[fd] = f32_muladd(F[fs1], F[fs2], F[fs3], F32MulAddOp::Softfloat_mulAdd_subC, mode);
   mark_f_state_dirty();
diff --git a/spec/std/isa/inst/F/fmul.s.yaml b/spec/std/isa/inst/F/fmul.s.yaml
index bb17209b2d..c4f5558f0a 100644
--- a/spec/std/isa/inst/F/fmul.s.yaml
+++ b/spec/std/isa/inst/F/fmul.s.yaml
@@ -34,5 +34,5 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
   RoundingMode mode = rm_to_mode(rm, $encoding);
-  f[fd] = f32_mul(f[fs1], f[fs2], mode);
+  F[fd] = f32_mul(F[fs1], F[fs2], mode);
   mark_f_state_dirty();
diff --git a/spec/std/isa/inst/F/fmv.w.x.yaml b/spec/std/isa/inst/F/fmv.w.x.yaml
index d8cc297abb..57c061109a 100644
--- a/spec/std/isa/inst/F/fmv.w.x.yaml
+++ b/spec/std/isa/inst/F/fmv.w.x.yaml
@@ -34,9 +34,9 @@ operation(): |
   Bits<32> sp_value = X[xs1][31:0];
 
   if (implemented?(ExtensionName::D)) {
-    f[fd] = nan_box(32, 64, sp_value);
+    F[fd] = nan_box(32, 64, sp_value);
   } else {
-    f[fd] = sp_value;
+    F[fd] = sp_value;
   }
 
   mark_f_state_dirty();
diff --git a/spec/std/isa/inst/F/fmv.x.w.yaml b/spec/std/isa/inst/F/fmv.x.w.yaml
index 1a542808aa..094c1904e2 100644
--- a/spec/std/isa/inst/F/fmv.x.w.yaml
+++ b/spec/std/isa/inst/F/fmv.x.w.yaml
@@ -32,4 +32,4 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
 
-  X[xd] = sext(f[fs1][31:0], 32);
+  X[xd] = sext(F[fs1][31:0], 32);
diff --git a/spec/std/isa/inst/F/fnmadd.s.yaml b/spec/std/isa/inst/F/fnmadd.s.yaml
index aeebdeee04..1efbe7fb40 100644
--- a/spec/std/isa/inst/F/fnmadd.s.yaml
+++ b/spec/std/isa/inst/F/fnmadd.s.yaml
@@ -38,6 +38,6 @@ operation(): |
   RoundingMode mode = rm_to_mode(rm, $encoding);
   # fnmadd: -(fs1 * fs2) - fs3 = -(fs1 * fs2) + (-fs3)
   # Negate fs3 by flipping its sign bit, then use subProd op
-  Bits<32> fs3_negated = f[fs3][31:0] ^ 32'h80000000;
-  f[fd] = f32_muladd(f[fs1], f[fs2], fs3_negated, F32MulAddOp::Softfloat_mulAdd_subProd, mode);
+  Bits<32> fs3_negated = F[fs3][31:0] ^ 32'h80000000;
+  F[fd] = f32_muladd(F[fs1], F[fs2], fs3_negated, F32MulAddOp::Softfloat_mulAdd_subProd, mode);
   mark_f_state_dirty();
diff --git a/spec/std/isa/inst/F/fnmsub.s.yaml b/spec/std/isa/inst/F/fnmsub.s.yaml
index 1a87eda5ac..82d4349bbd 100644
--- a/spec/std/isa/inst/F/fnmsub.s.yaml
+++ b/spec/std/isa/inst/F/fnmsub.s.yaml
@@ -36,5 +36,5 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
   RoundingMode mode = rm_to_mode(rm, $encoding);
-  f[fd] = f32_muladd(f[fs1], f[fs2], f[fs3], F32MulAddOp::Softfloat_mulAdd_subProd, mode);
+  F[fd] = f32_muladd(F[fs1], F[fs2], F[fs3], F32MulAddOp::Softfloat_mulAdd_subProd, mode);
   mark_f_state_dirty();
diff --git a/spec/std/isa/inst/F/fsgnj.s.yaml b/spec/std/isa/inst/F/fsgnj.s.yaml
index 65eadefd57..ab2bee9910 100644
--- a/spec/std/isa/inst/F/fsgnj.s.yaml
+++ b/spec/std/isa/inst/F/fsgnj.s.yaml
@@ -39,12 +39,12 @@ pseudoinstructions:
 operation(): |
   check_f_ok($encoding);
 
-  Bits<32> sp_value = {f[fs2][31], f[fs1][30:0]};
+  Bits<32> sp_value = {F[fs2][31], F[fs1][30:0]};
 
   if (implemented?(ExtensionName::D)) {
-    f[fd] = nan_box(32, 64, sp_value);
+    F[fd] = nan_box(32, 64, sp_value);
   } else {
-    f[fd] = sp_value;
+    F[fd] = sp_value;
   }
 
   mark_f_state_dirty();
diff --git a/spec/std/isa/inst/F/fsgnjn.s.yaml b/spec/std/isa/inst/F/fsgnjn.s.yaml
index 0647d8d125..1839276132 100644
--- a/spec/std/isa/inst/F/fsgnjn.s.yaml
+++ b/spec/std/isa/inst/F/fsgnjn.s.yaml
@@ -38,12 +38,12 @@ pseudoinstructions:
 operation(): |
   check_f_ok($encoding);
 
-  Bits<32> sp_value = {~f[fs2][31], f[fs1][30:0]};
+  Bits<32> sp_value = {~F[fs2][31], F[fs1][30:0]};
 
   if (implemented?(ExtensionName::D)) {
-    f[fd] = nan_box(32, 64, sp_value);
+    F[fd] = nan_box(32, 64, sp_value);
   } else {
-    f[fd] = sp_value;
+    F[fd] = sp_value;
   }
 
   mark_f_state_dirty();
diff --git a/spec/std/isa/inst/F/fsgnjx.s.yaml b/spec/std/isa/inst/F/fsgnjx.s.yaml
index 01febc1d7e..d4f2213652 100644
--- a/spec/std/isa/inst/F/fsgnjx.s.yaml
+++ b/spec/std/isa/inst/F/fsgnjx.s.yaml
@@ -37,12 +37,12 @@ pseudoinstructions:
 operation(): |
   check_f_ok($encoding);
 
-  Bits<32> sp_value = {f[fs1][31] ^ f[fs2][31], f[fs1][30:0]};
+  Bits<32> sp_value = {F[fs1][31] ^ F[fs2][31], F[fs1][30:0]};
 
   if (implemented?(ExtensionName::D)) {
-    f[fd] = nan_box(32, 64, sp_value);
+    F[fd] = nan_box(32, 64, sp_value);
   } else {
-    f[fd] = sp_value;
+    F[fd] = sp_value;
   }
 
   mark_f_state_dirty();
diff --git a/spec/std/isa/inst/F/fsqrt.s.yaml b/spec/std/isa/inst/F/fsqrt.s.yaml
index 9f8ce5bfad..aeadd35860 100644
--- a/spec/std/isa/inst/F/fsqrt.s.yaml
+++ b/spec/std/isa/inst/F/fsqrt.s.yaml
@@ -31,5 +31,5 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
   RoundingMode mode = rm_to_mode(rm, $encoding);
-  f[fd] = f32_sqrt(f[fs1], mode);
+  F[fd] = f32_sqrt(F[fs1], mode);
   mark_f_state_dirty();
diff --git a/spec/std/isa/inst/F/fsub.s.yaml b/spec/std/isa/inst/F/fsub.s.yaml
index f34baefc4d..9bd3dda2d5 100644
--- a/spec/std/isa/inst/F/fsub.s.yaml
+++ b/spec/std/isa/inst/F/fsub.s.yaml
@@ -33,4 +33,4 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
   RoundingMode mode = rm_to_mode(rm, $encoding);
-  f[fd] = f32_sub(f[fs1], f[fs2], mode);
+  F[fd] = f32_sub(F[fs1], F[fs2], mode);
diff --git a/spec/std/isa/inst/F/fsw.yaml b/spec/std/isa/inst/F/fsw.yaml
index a39ccb2534..ac8bde655f 100644
--- a/spec/std/isa/inst/F/fsw.yaml
+++ b/spec/std/isa/inst/F/fsw.yaml
@@ -35,4 +35,4 @@ operation(): |
 
   XReg virtual_address = X[xs1] + $signed(imm);
 
-  write_memory(32, virtual_address, f[fs2][31:0], $encoding);
+  write_memory(32, virtual_address, F[fs2][31:0], $encoding);
diff --git a/spec/std/isa/inst/V/vadd.vv.yaml b/spec/std/isa/inst/V/vadd.vv.yaml
index 3dfb3b40d4..c337ffecfb 100644
--- a/spec/std/isa/inst/V/vadd.vv.yaml
+++ b/spec/std/isa/inst/V/vadd.vv.yaml
@@ -47,7 +47,7 @@ operation(): |
   for (U32 i = CSR[vstart].VALUE; i < CSR[vl].VALUE; i++) {
     U32 start_bit_pos = i * state.sew;
     U32 end_bit_pos = start_bit_pos + state.sew - 1;
-    v[vd][end_bit_pos:start_bit_pos] = v[vs2][end_bit_pos:start_bit_pos] + v[vs1][end_bit_pos:start_bit_pos];
+    V[vd][end_bit_pos:start_bit_pos] = V[vs2][end_bit_pos:start_bit_pos] + V[vs1][end_bit_pos:start_bit_pos];
   }
 
   CSR[vstart].VALUE = 0;
diff --git a/spec/std/isa/inst/V/vle8.v.yaml b/spec/std/isa/inst/V/vle8.v.yaml
index 5e8afd18e8..f4d933f45a 100644
--- a/spec/std/isa/inst/V/vle8.v.yaml
+++ b/spec/std/isa/inst/V/vle8.v.yaml
@@ -34,6 +34,5 @@ operation(): |
   for (U32 i = CSR[vstart].VALUE; i < CSR[vl].VALUE; i++) {
     U32 start_bit_pos = i * 8;
     U32 end_bit_pos = start_bit_pos + 7;
-
-    v[vd][end_bit_pos:start_bit_pos] = read_memory(8, virtual_address + i, $encoding)[7:0];
+    V[vd][end_bit_pos:start_bit_pos] = read_memory(8, virtual_address + i, $encoding)[7:0];
   }
diff --git a/spec/std/isa/inst/V/vmv.v.i.yaml b/spec/std/isa/inst/V/vmv.v.i.yaml
index ac7458001b..6750dd0f04 100644
--- a/spec/std/isa/inst/V/vmv.v.i.yaml
+++ b/spec/std/isa/inst/V/vmv.v.i.yaml
@@ -55,7 +55,7 @@ operation(): |
     U32 end_bit_pos = start_bit_pos + state.sew - 1;
 
     # Write the sign-extended immediate (truncated to SEW bits) to the element
-    v[vd][end_bit_pos:start_bit_pos] = sext_imm[state.sew-1:0];
+    V[vd][end_bit_pos:start_bit_pos] = sext_imm[state.sew-1:0];
   }
 
   CSR[vstart].VALUE = 0;
diff --git a/spec/std/isa/inst/V/vmv.x.s.yaml b/spec/std/isa/inst/V/vmv.x.s.yaml
index 72173bc1aa..315ef2184c 100644
--- a/spec/std/isa/inst/V/vmv.x.s.yaml
+++ b/spec/std/isa/inst/V/vmv.x.s.yaml
@@ -34,6 +34,6 @@ operation(): |
   VectorState state = vector_state();
 
   # vmv.x.s copies element 0 of vs2 to xd, sign-extending to XLEN
-  X[xd] = $signed(v[vs2][state.sew-1:0]);
+  X[xd] = $signed(V[vs2][state.sew-1:0]);
 
   CSR[vstart].VALUE = 0;
diff --git a/spec/std/isa/inst/V/vse8.v.yaml b/spec/std/isa/inst/V/vse8.v.yaml
index 75b08ffc7e..3dbe211d86 100644
--- a/spec/std/isa/inst/V/vse8.v.yaml
+++ b/spec/std/isa/inst/V/vse8.v.yaml
@@ -34,5 +34,5 @@ operation(): |
   for (U32 i = CSR[vstart].VALUE; i < CSR[vl].VALUE; i++) {
     U32 start_bit_pos = i * 8;
     U32 end_bit_pos = start_bit_pos + 7;
-    write_memory(8, virtual_address + i, v[vs3][end_bit_pos:start_bit_pos], $encoding);
+    write_memory(8, virtual_address + i, V[vs3][end_bit_pos:start_bit_pos], $encoding);
   }
diff --git a/spec/std/isa/inst/Zcd/c.fld.yaml b/spec/std/isa/inst/Zcd/c.fld.yaml
index 121b002e6f..a53217e686 100644
--- a/spec/std/isa/inst/Zcd/c.fld.yaml
+++ b/spec/std/isa/inst/Zcd/c.fld.yaml
@@ -38,4 +38,4 @@ operation(): |
 
   XReg virtual_address = X[creg2reg(xs1)] + imm;
 
-  f[fd] = sext(read_memory(64, virtual_address, $encoding), 64);
+  F[fd] = sext(read_memory(64, virtual_address, $encoding), 64);
diff --git a/spec/std/isa/inst/Zcd/c.fldsp.yaml b/spec/std/isa/inst/Zcd/c.fldsp.yaml
index 36bde7df9d..af357d3fb5 100644
--- a/spec/std/isa/inst/Zcd/c.fldsp.yaml
+++ b/spec/std/isa/inst/Zcd/c.fldsp.yaml
@@ -39,4 +39,4 @@ operation(): |
 
   XReg virtual_address = X[2] + imm;
 
-  f[fd] = read_memory(64, virtual_address, $encoding);
+  F[fd] = read_memory(64, virtual_address, $encoding);
diff --git a/spec/std/isa/inst/Zcd/c.fsdsp.yaml b/spec/std/isa/inst/Zcd/c.fsdsp.yaml
index 4e6b7125d9..8df79dbceb 100644
--- a/spec/std/isa/inst/Zcd/c.fsdsp.yaml
+++ b/spec/std/isa/inst/Zcd/c.fsdsp.yaml
@@ -39,4 +39,4 @@ operation(): |
 
   XReg virtual_address = X[2] + imm;
 
-  write_memory(64, virtual_address, f[fs2][63:0], $encoding);
+  write_memory(64, virtual_address, F[fs2][63:0], $encoding);
diff --git a/spec/std/isa/inst/Zcf/c.flwsp.yaml b/spec/std/isa/inst/Zcf/c.flwsp.yaml
index 08b49ce52d..6edf3c307f 100644
--- a/spec/std/isa/inst/Zcf/c.flwsp.yaml
+++ b/spec/std/isa/inst/Zcf/c.flwsp.yaml
@@ -39,4 +39,4 @@ operation(): |
 
   XReg virtual_address = X[2] + imm;
 
-  f[fd] = read_memory(32, virtual_address, $encoding);
+  F[fd] = read_memory(32, virtual_address, $encoding);
diff --git a/spec/std/isa/inst/Zcf/c.fswsp.yaml b/spec/std/isa/inst/Zcf/c.fswsp.yaml
index b493b50958..4c668bbceb 100644
--- a/spec/std/isa/inst/Zcf/c.fswsp.yaml
+++ b/spec/std/isa/inst/Zcf/c.fswsp.yaml
@@ -39,4 +39,4 @@ operation(): |
 
   XReg virtual_address = X[2] + imm;
 
-  write_memory(32, virtual_address, f[fs2][31:0], $encoding);
+  write_memory(32, virtual_address, F[fs2][31:0], $encoding);
diff --git a/spec/std/isa/inst/Zfa/fround.s.yaml b/spec/std/isa/inst/Zfa/fround.s.yaml
index 567b261ec0..39c7d7818d 100644
--- a/spec/std/isa/inst/Zfa/fround.s.yaml
+++ b/spec/std/isa/inst/Zfa/fround.s.yaml
@@ -37,5 +37,5 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
   RoundingMode rounding_mode = rm_to_mode(rm, $encoding);
-  f[fd] = round_f32_to_integral(f[fs1], rounding_mode);
+  F[fd] = round_f32_to_integral(F[fs1], rounding_mode);
   mark_f_state_dirty();
diff --git a/spec/std/isa/inst/Zfh/fcvt.h.s.yaml b/spec/std/isa/inst/Zfh/fcvt.h.s.yaml
index d74b9c6ff2..d2992b37ed 100644
--- a/spec/std/isa/inst/Zfh/fcvt.h.s.yaml
+++ b/spec/std/isa/inst/Zfh/fcvt.h.s.yaml
@@ -39,7 +39,7 @@ access:
 operation(): |
   check_f_ok($encoding);
 
-  Bits<16> hp_value = f[fs1][15:0];
+  Bits<16> hp_value = F[fs1][15:0];
 
   Bits<1> sign = hp_value[15];
   Bits<5> exp = hp_value[14:10];
@@ -50,22 +50,22 @@ operation(): |
       if ((hp_value & 0x0200) != 0) {
         set_fp_flag(FpFlag::NV);
       }
-      f[fd] = HP_CANONICAL_NAN;
+      F[fd] = HP_CANONICAL_NAN;
     } else {
-      f[fd] = packToF32UI(sign, 0xFF, 0);
+      F[fd] = packToF32UI(sign, 0xFF, 0);
     }
   } else {
     if (exp != 0) {
       if (frac != 0) {
-        f[fd] = packToF32UI(sign, 0, 0);
+        F[fd] = packToF32UI(sign, 0, 0);
       } else {
         Bits<6> norm_exp;
         (norm_exp, frac) = softfloat_normSubnormalF16Sig( frac );
         exp = norm_exp - 1;
-        f[fd] = packToF32UI(sign, exp + 0x70, frac << 13);
+        F[fd] = packToF32UI(sign, exp + 0x70, frac << 13);
       }
     } else {
-      f[fd] = packToF32UI(sign, exp + 0x70, frac << 13);
+      F[fd] = packToF32UI(sign, exp + 0x70, frac << 13);
     }
   }
 
diff --git a/spec/std/isa/inst/Zfh/fcvt.s.h.yaml b/spec/std/isa/inst/Zfh/fcvt.s.h.yaml
index 8f72d65048..e290b55a12 100644
--- a/spec/std/isa/inst/Zfh/fcvt.s.h.yaml
+++ b/spec/std/isa/inst/Zfh/fcvt.s.h.yaml
@@ -36,7 +36,7 @@ access:
 operation(): |
   check_f_ok($encoding);
 
-  Bits<32> sp_value = f[fs1][31:0];
+  Bits<32> sp_value = F[fs1][31:0];
 
   Bits<1> sign = sp_value[31];
   Bits<8> exp = sp_value[30:23];
@@ -47,9 +47,9 @@ operation(): |
       if ((sp_value & 0x00400000) != 0) {
         set_fp_flag(FpFlag::NV);
       }
-      f[fd] = nan_box(16, FLEN, HP_CANONICAL_NAN);
+      F[fd] = nan_box(16, FLEN, HP_CANONICAL_NAN);
     } else {
-      f[fd] = nan_box(16, FLEN, packToF16UI( sign, 0x1F, 0 ));
+      F[fd] = nan_box(16, FLEN, packToF16UI( sign, 0x1F, 0 ));
     }
   } else {
 
@@ -58,10 +58,10 @@ operation(): |
     # is OR-red with the sticky
     Bits<16> frac16 = (frac >> 9) | ((frac & 0x1ff) != 0 ? 1 : 0);
     if ((exp | frac16) == 0) {
-      f[fd] = nan_box(16, FLEN, packToF16UI( sign, 0, 0 ));
+      F[fd] = nan_box(16, FLEN, packToF16UI( sign, 0, 0 ));
     } else {
       assert(false, "TODO: implement roundPackToF16");
-      # f[fd] = soffloat_roundPackToF16(sign, exp - 0x71, frac16 | 0x4000);
+      # F[fd] = soffloat_roundPackToF16(sign, exp - 0x71, frac16 | 0x4000);
     }
 
   }
diff --git a/spec/std/isa/inst/Zfh/flh.yaml b/spec/std/isa/inst/Zfh/flh.yaml
index 7fbb2d1983..1d3ed6aff3 100644
--- a/spec/std/isa/inst/Zfh/flh.yaml
+++ b/spec/std/isa/inst/Zfh/flh.yaml
@@ -39,6 +39,6 @@ operation(): |
 
   Bits<16> hp_value = read_memory(16, virtual_address, $encoding);
 
-  f[fd] = nan_box(16, FLEN, hp_value);
+  F[fd] = nan_box(16, FLEN, hp_value);
 
   mark_f_state_dirty();
diff --git a/spec/std/isa/inst/Zfh/fmv.h.x.yaml b/spec/std/isa/inst/Zfh/fmv.h.x.yaml
index 4bb564bcc7..ef3078b092 100644
--- a/spec/std/isa/inst/Zfh/fmv.h.x.yaml
+++ b/spec/std/isa/inst/Zfh/fmv.h.x.yaml
@@ -33,6 +33,6 @@ operation(): |
 
   Bits<16> hp_value = X[xs1][15:0];
 
-  f[fd] = nan_box(16, FLEN, hp_value);
+  F[fd] = nan_box(16, FLEN, hp_value);
 
   mark_f_state_dirty();
diff --git a/spec/std/isa/inst/Zfh/fmv.x.h.yaml b/spec/std/isa/inst/Zfh/fmv.x.h.yaml
index 11ecb5fcee..cd64d4ba9e 100644
--- a/spec/std/isa/inst/Zfh/fmv.x.h.yaml
+++ b/spec/std/isa/inst/Zfh/fmv.x.h.yaml
@@ -35,4 +35,4 @@ access:
 operation(): |
   check_f_ok($encoding);
 
-  X[xd] = sext(f[fs1][15:0], 16);
+  X[xd] = sext(F[fs1][15:0], 16);
diff --git a/spec/std/isa/inst/Zfh/fsh.yaml b/spec/std/isa/inst/Zfh/fsh.yaml
index d9a5ec69b1..a87b4ec2cc 100644
--- a/spec/std/isa/inst/Zfh/fsh.yaml
+++ b/spec/std/isa/inst/Zfh/fsh.yaml
@@ -40,6 +40,6 @@ operation(): |
 
   XReg virtual_address = X[xs1] + $signed(imm);
 
-  Bits<16> hp_value = f[fs2][15:0];
+  Bits<16> hp_value = F[fs2][15:0];
 
   write_memory(16, virtual_address, hp_value, $encoding);
diff --git a/spec/std/isa/isa/fp.idl b/spec/std/isa/isa/fp.idl
index 54b5f83bc0..dd8c5f9a60 100644
--- a/spec/std/isa/isa/fp.idl
+++ b/spec/std/isa/isa/fp.idl
@@ -9,11 +9,7 @@
 # Files in berkely-softfloat-3 repository are licensed under BSD-3-clause.
 
 # floating point register file
-U32 FLEN = 64; # implemented?(ExtensionName::D) ? 7'd64 : 7'd32;
-Bits<FLEN> f[32] = [0, 0, 0, 0, 0, 0, 0, 0,
-                    0, 0, 0, 0, 0, 0, 0, 0,
-                    0, 0, 0, 0, 0, 0, 0, 0,
-                    0, 0, 0, 0, 0, 0, 0, 0];
+U32 FLEN = implemented?(ExtensionName::Q) ? 8'd128 : (implemented?(ExtensionName::D) ? 7'd64 : 7'd32);
 
 # FP constants
 Bits<32> SP_POS_INF       = 32'b0_11111111_00000000000000000000000;
diff --git a/spec/std/isa/isa/vec.idl b/spec/std/isa/isa/vec.idl
index 995d6de4d9..8f3f898d7f 100644
--- a/spec/std/isa/isa/vec.idl
+++ b/spec/std/isa/isa/vec.idl
@@ -11,8 +11,7 @@
 #   - integer arith (vadd/vsub/vrsub(.vv,.vx,.vi), compare, min, max)
 #   - integer widening arith ()
 
-# the vector register file
-Bits<128> v[32];
+# the vector register file is populated by the symtab from V.yaml
 
 enum VectorLmulType {
   Divide
diff --git a/spec/std/isa/param/VLEN.yaml b/spec/std/isa/param/VLEN.yaml
index f6e3a0a940..19aaf1cb05 100644
--- a/spec/std/isa/param/VLEN.yaml
+++ b/spec/std/isa/param/VLEN.yaml
@@ -11,6 +11,8 @@ description: |
 long_name: TODO
 schema:
   type: integer
+  minimum: 32
+  maximum: 65536
 #    requirements:
 #      idl(): |
 #        -> (VLEN >= ELEN) && (VLEN <='h10000) && (popcount(VLEN) == 1);
diff --git a/spec/std/isa/register_file/F.yaml b/spec/std/isa/register_file/F.yaml
index c628a362d0..f23f4a6a89 100644
--- a/spec/std/isa/register_file/F.yaml
+++ b/spec/std/isa/register_file/F.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) Animesh Agarwal
 # SPDX-License-Identifier: BSD-3-Clause-Clear
 
-# yaml-language-server: $schema=../../../../schemas/register_file_schema.json
+# yaml-language-server: $schema=../../../schemas/register_file_schema.json
 
 $schema: register_file_schema.json#
 kind: register_file
@@ -13,7 +13,8 @@ description: |
   participates in the standard calling convention defined by the RISC-V ABI spec.
 definedBy: F
 register_class: floating_point
-register_length: FLEN
+register_length(): |
+  return implemented?(ExtensionName::Q) ? 128 : (implemented?(ExtensionName::D) ? 64 : 32);
 registers:
   - name: f0
     abi_mnemonics: [ft0]
diff --git a/spec/std/isa/register_file/V.yaml b/spec/std/isa/register_file/V.yaml
index d2802916a6..731e8a61f4 100644
--- a/spec/std/isa/register_file/V.yaml
+++ b/spec/std/isa/register_file/V.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) Animesh Agarwal
 # SPDX-License-Identifier: BSD-3-Clause-Clear
 
-# yaml-language-server: $schema=../../../../schemas/register_file_schema.json
+# yaml-language-server: $schema=../../../schemas/register_file_schema.json
 
 $schema: register_file_schema.json#
 kind: register_file
@@ -14,7 +14,7 @@ description: |
   participate in argument passing or return values.
 definedBy: V
 register_class: vector
-register_length: VLEN
+register_length(): return VLEN;
 registers:
   - name: v0
     caller_saved: true
diff --git a/spec/std/isa/register_file/X.yaml b/spec/std/isa/register_file/X.yaml
index 0d48db7463..78ce96d878 100644
--- a/spec/std/isa/register_file/X.yaml
+++ b/spec/std/isa/register_file/X.yaml
@@ -14,11 +14,12 @@ description: |
   visible integer state used by the calling convention and execution environment.
 definedBy: I
 register_class: general_purpose
-register_length: MXLEN
+register_length(): return MXLEN;
 registers:
   - name: x0
     abi_mnemonics: [zero]
     roles: [zero]
+    reset_value: "0"
     description: |
       Register x0 is hardwired with all bits equal to 0.
     arch_read(): |
diff --git a/tools/ruby-gems/idlc/lib/idlc/ast.rb b/tools/ruby-gems/idlc/lib/idlc/ast.rb
index 5c98463401..b8c29b5b89 100644
--- a/tools/ruby-gems/idlc/lib/idlc/ast.rb
+++ b/tools/ruby-gems/idlc/lib/idlc/ast.rb
@@ -1411,9 +1411,13 @@ def add_global_symbols(symtab)
 
       enums.each { |g| g.add_symbol(symtab); }
       bitfields.each { |g| g.add_symbol(symtab) }
+      # Functions must be registered before globals so that global variable
+      # initializers can call functions (e.g. FLEN = implemented?(...) ? 64 : 32).
+      # FunctionDefAst#add_symbol only stores the FunctionType; it does not
+      # evaluate the body, so adding functions before globals is safe.
+      functions.each { |g| g.add_symbol(symtab) }
       globals.each { |g| g.add_symbol(symtab) }
       structs.each { |g| g.add_symbol(symtab) }
-      functions.each { |g| g.add_symbol(symtab) }
     end
 
     # replaces an include statement with the ast in that file, making
@@ -2528,7 +2532,12 @@ class AryElementAccessAst < AstNode
 
     sig { override.params(symtab: SymbolTable).returns(T::Boolean) }
     def const_eval?(symtab)
-      if var.is_a?(IdAst) && var.name == "X"
+      var_type = begin
+        var.type(symtab)
+      rescue AstNode::TypeError, AstNode::InternalError
+        nil
+      end
+      if var_type.is_a?(Type) && var_type.kind == :array && var_type.sub_type.is_a?(RegFileElementType) && var_type.qualifiers.include?(:global)
         false
       else
         var.const_eval?(symtab) && index.const_eval?(symtab)
@@ -2593,7 +2602,12 @@ def value(symtab)
       if var.type(symtab).integral?
         (var_val >> index.value(symtab)) & 1
       else
-        value_error "X registers are not compile-time-known" if var.text_value == "X"
+        var_type = begin
+          var.type(symtab)
+        rescue AstNode::TypeError, AstNode::InternalError
+          nil
+        end
+        value_error "Register file registers are not compile-time-known" if var_type.is_a?(Type) && var_type.kind == :array && var_type.sub_type.is_a?(RegFileElementType) && var_type.qualifiers.include?(:global)
 
         # internal_error "Not an array" unless ary.type.kind == :array
 
@@ -2638,7 +2652,12 @@ class AryRangeAccessAst < AstNode
     sig { override.params(symtab: SymbolTable).returns(T::Boolean) }
     def const_eval?(symtab)
       v = var
-      if v.is_a?(IdAst) && v.name == "X"
+      var_type = begin
+        v.type(symtab)
+      rescue AstNode::TypeError, AstNode::InternalError
+        nil
+      end
+      if var_type.is_a?(Type) && var_type.kind == :array && var_type.sub_type.is_a?(RegFileElementType) && var_type.qualifiers.include?(:global)
         false
       else
         v.const_eval?(symtab) && msb.const_eval?(symtab).const_eval? && lsb.const_eval?(symtab)
@@ -5351,6 +5370,10 @@ def type(symtab) = expression.type(symtab)
     # @!macro value
     def value(symtab) = expression.value(symtab)
 
+    def max_value(symtab) = expression.max_value(symtab)
+
+    def min_value(symtab) = expression.min_value(symtab)
+
     # @!macro to_idl
     sig { override.returns(String) }
     def to_idl = "(#{expression.to_idl})"
@@ -6455,6 +6478,34 @@ def values(symtab)
       end
     end
 
+    # @!macro max_value
+    def max_value(symtab)
+      value_result = value_try do
+        cond = condition.value(symtab)
+        return cond ? true_expression.max_value(symtab) : false_expression.max_value(symtab)
+      end
+      value_else(value_result) do
+        t = true_expression.max_value(symtab)
+        f = false_expression.max_value(symtab)
+        return :unknown if t == :unknown || f == :unknown
+        [t, f].max
+      end
+    end
+
+    # @!macro min_value
+    def min_value(symtab)
+      value_result = value_try do
+        cond = condition.value(symtab)
+        return cond ? true_expression.min_value(symtab) : false_expression.min_value(symtab)
+      end
+      value_else(value_result) do
+        t = true_expression.min_value(symtab)
+        f = false_expression.min_value(symtab)
+        return :unknown if t == :unknown || f == :unknown
+        [t, f].min
+      end
+    end
+
     # @!macro to_idl
     sig { override.returns(String) }
     def to_idl = "#{condition.to_idl} ? #{true_expression.to_idl} : #{false_expression.to_idl}"
diff --git a/tools/ruby-gems/idlc/lib/idlc/cli.rb b/tools/ruby-gems/idlc/lib/idlc/cli.rb
index 27a14736fc..3bce0e8e43 100644
--- a/tools/ruby-gems/idlc/lib/idlc/cli.rb
+++ b/tools/ruby-gems/idlc/lib/idlc/cli.rb
@@ -12,6 +12,15 @@
 require "yaml"
 
 module Idl
+  # Minimal register-file descriptor used by the CLI when no architecture is configured.
+  # Provides the interface that SymbolTable.new(register_files:) expects.
+  DefaultXRegisterFile = Struct.new(:name, :register_length, :registers) do
+    def self.build(xlen = 64)
+      registers = Array.new(32) { |i| Struct.new(:name).new("x#{i}") }
+      new("X", "return #{xlen};", registers)
+    end
+  end
+
   class Cli
     extend Forwardable
     def_delegators :@runner,
@@ -48,7 +57,7 @@ def do_eval(args, options)
       end
 
       compiler = Compiler.new
-      symtab = SymbolTable.new
+      symtab = SymbolTable.new(register_files: [DefaultXRegisterFile.build])
 
       add_defines(compiler, symtab)
       expr_ast = compiler.compile_expression(args[0], symtab)
@@ -104,7 +113,7 @@ def do_compile(args, options)
 
     def do_tc_inst(args, options, vars)
       compiler = Compiler.new
-      symtab = SymbolTable.new
+      symtab = SymbolTable.new(register_files: [DefaultXRegisterFile.build])
 
       add_defines(compiler, symtab)
       symtab.push(nil)
diff --git a/tools/ruby-gems/idlc/lib/idlc/passes/find_src_registers.rb b/tools/ruby-gems/idlc/lib/idlc/passes/find_src_registers.rb
index 7125dd129b..afd45d7edb 100644
--- a/tools/ruby-gems/idlc/lib/idlc/passes/find_src_registers.rb
+++ b/tools/ruby-gems/idlc/lib/idlc/passes/find_src_registers.rb
@@ -80,16 +80,20 @@ def find_dst_registers(symtab)
   class AryElementAccessAst
     def find_src_registers(symtab)
       value_result = value_try do
-        if var.text_value == "X"
-          return [index.value(symtab)]
+        var_type = var.type(symtab) rescue nil
+        if var_type&.kind == :array && var_type.sub_type.is_a?(RegFileElementType) && var_type.qualifiers.include?(:global)
+          rf_name = var_type.sub_type.name
+          return [[rf_name, index.value(symtab)]]
         else
           return []
         end
       end
       value_else(value_result) do
-        if var.text_value == "X"
+        var_type = var.type(symtab) rescue nil
+        if var_type&.kind == :array && var_type.sub_type.is_a?(RegFileElementType) && var_type.qualifiers.include?(:global)
+          rf_name = var_type.sub_type.name
           if index.type(symtab).const?
-            return [index.gen_cpp(symtab, 0)]
+            return [[rf_name, index.gen_cpp(symtab, 0)]]
           else
             raise ComplexRegDetermination
           end
@@ -116,11 +120,23 @@ def find_dst_registers(symtab)
       end
 
       value_result = value_try do
-        return [reg_idx.value(symtab)]
+        var_type = lhs.type(symtab) rescue nil
+        if var_type&.kind == :array && var_type.sub_type.is_a?(RegFileElementType) && var_type.qualifiers.include?(:global)
+          rf_name = var_type.sub_type.name
+          return [[rf_name, reg_idx.value(symtab)]]
+        else
+          return []
+        end
       end
       value_else(value_result) do
-        if reg_idx.type(symtab).const?
-          return [reg_idx.gen_cpp(symtab, 0)]
+        var_type = lhs.type(symtab) rescue nil
+        if var_type&.kind == :array && var_type.sub_type.is_a?(RegFileElementType) && var_type.qualifiers.include?(:global)
+          rf_name = var_type.sub_type.name
+          if reg_idx.type(symtab).const?
+            return [[rf_name, reg_idx.gen_cpp(symtab, 0)]]
+          else
+            raise ComplexRegDetermination
+          end
         else
           raise ComplexRegDetermination
         end
diff --git a/tools/ruby-gems/idlc/lib/idlc/symbol_table.rb b/tools/ruby-gems/idlc/lib/idlc/symbol_table.rb
index b5322e4bf6..c1224bfaba 100644
--- a/tools/ruby-gems/idlc/lib/idlc/symbol_table.rb
+++ b/tools/ruby-gems/idlc/lib/idlc/symbol_table.rb
@@ -208,10 +208,12 @@ def params_hash
         builtin_funcs: T.nilable(BuiltinFunctionCallbacks),
         csrs: T::Array[Csr],
         params: T::Array[RuntimeParam],
-        name: String
+        name: String,
+        register_files: T::Array[T.untyped],
+        register_file_max_widths: T::Hash[String, Integer]
       ).void
     }
-    def initialize(mxlen: nil, possible_xlens_cb: nil, builtin_global_vars: [], builtin_enums: [], builtin_funcs: nil, csrs: [], params: [], name: "")
+    def initialize(mxlen: nil, possible_xlens_cb: nil, builtin_global_vars: [], builtin_enums: [], builtin_funcs: nil, csrs: [], params: [], name: "", register_files: [], register_file_max_widths: {})
       @mutex = Thread::Mutex.new
       @mxlen = mxlen
       @possible_xlens_cb = possible_xlens_cb
@@ -221,11 +223,6 @@ def initialize(mxlen: nil, possible_xlens_cb: nil, builtin_global_vars: [], buil
 
       # builtin types
       @scopes = [{
-        "X" => Var.new(
-          "X",
-          Type.new(:array, sub_type: XregType.new(@mxlen.nil? ? 64 : @mxlen), width: 32, qualifiers: [:global])
-        ),
-        "XReg" => XregType.new(@mxlen.nil? ? 64 : @mxlen),
         "Boolean" => Type.new(:boolean),
         "true" => Var.new(
           "true",
@@ -237,8 +234,29 @@ def initialize(mxlen: nil, possible_xlens_cb: nil, builtin_global_vars: [], buil
           Type.new(:boolean),
           false
         )
-
       }]
+      # @params must be set before the register_files loop so that param schema
+      # max lookups (used to compute int_width for dynamic-width register files)
+      # can access @params without triggering a cfg_arch.symtab circular dependency.
+      @params = params
+
+      # Register file globals (X, F, V, etc.) from YAML-derived register file objects.
+      # Each RF provides: .name (String), .register_length (IDL body String), .registers.count (Integer).
+      register_files.each do |rf|
+        int_width = if register_file_max_widths.key?(rf.name)
+          register_file_max_widths[rf.name]
+        else
+          # Fallback for callers without pre-computed widths (CLI, tests with literal-width RFs).
+          # eval_register_length_idl handles literals ("return 64;") and simple MXLEN references.
+          w = eval_register_length_idl(rf.register_length)
+          w.is_a?(Integer) ? w : raise("Cannot determine max register width for '#{rf.name}'. " \
+                                        "Pass register_file_max_widths: to SymbolTable.new.")
+        end
+        elem_type = RegFileElementType.new(rf.name, int_width, max_width: int_width)
+        array_type = Type.new(:array, sub_type: elem_type, width: rf.registers.count, qualifiers: [:global])
+        @scopes[0][rf.name] = Var.new(rf.name, array_type)
+        @scopes[0]["#{rf.name}Reg"] = elem_type
+      end
       builtin_global_vars.each do |v|
         add!(v.name, v)
       end
@@ -248,12 +266,35 @@ def initialize(mxlen: nil, possible_xlens_cb: nil, builtin_global_vars: [], buil
       @builtin_funcs = builtin_funcs
       @csrs = csrs
       @csr_hash = @csrs.map { |csr| [csr.name.freeze, csr].freeze }.to_h.freeze
-      @params = params
 
       # set up the global clone that be used as a mutable table
       @global_clone_pool = T.let([], T::Array[SymbolTable])
     end
 
+    # Compile and evaluate the IDL function body string that defines register width.
+    # Returns an Integer if statically known, or the expression string if dynamic.
+    # @param idl_body [String] e.g. "return 64;" or "return MXLEN;"
+    #
+    # NOTE: The body-stripping logic here (strip 'return', strip ';', match literal/MXLEN)
+    # is intentionally duplicated in Udb::RegisterFile#register_length_expr and
+    # Udb::RegisterFile#eval_register_length (udb gem). Changes here must be mirrored there.
+    # idlc cannot depend on udb (udb depends on idlc), so a shared utility is not possible
+    # without an additional gem layer.
+    def eval_register_length_idl(idl_body)
+      # Strip 'return' and ';'
+      expr = idl_body.strip.sub(/\Areturn\s+/, "").sub(/;\z/, "").strip
+      case expr
+      when /\A\d+\z/
+        expr.to_i
+      when /\AMXLEN\z/
+        @mxlen || 64
+      else
+        # Dynamic parameter — return the parameter name as a String
+        expr
+      end
+    end
+    private :eval_register_length_idl
+
     # @return [String] inspection string
     sig { returns(String) }
     def inspect
diff --git a/tools/ruby-gems/idlc/lib/idlc/type.rb b/tools/ruby-gems/idlc/lib/idlc/type.rb
index b92d818273..1f6e6240ca 100644
--- a/tools/ruby-gems/idlc/lib/idlc/type.rb
+++ b/tools/ruby-gems/idlc/lib/idlc/type.rb
@@ -963,19 +963,24 @@ def argument_name(index, func_call_ast)
     def body = @func_def_ast.body
   end
 
-  # XReg is really a Bits<> type, so we override it just to get
-  # prettier prints
-  class XregType < Type
-    def initialize(xlen)
-      super(:bits, width: xlen, max_width: 64)
-    end
+  # General-purpose register file element type.
+  # Represents the type of one element in a named register file (e.g. F, V, X).
+  class RegFileElementType < Type
+    attr_reader :name
 
-    def to_s
-      "XReg"
+    def initialize(name, width, max_width: nil)
+      super(:bits, width:, max_width: max_width || width)
+      @name = name
     end
 
-    def to_cxx
-      "XReg"
+    def to_s = "#{name}Reg"
+    def to_cxx = "#{name}Reg"
+  end
+
+  # XReg is really a Bits<> type -- keep as a named alias for backwards compatibility
+  class XregType < RegFileElementType
+    def initialize(xlen)
+      super("X", xlen, max_width: 64)
     end
   end
 
diff --git a/tools/ruby-gems/idlc/test/helpers.rb b/tools/ruby-gems/idlc/test/helpers.rb
index 626f52c9bd..e4f83c3245 100644
--- a/tools/ruby-gems/idlc/test/helpers.rb
+++ b/tools/ruby-gems/idlc/test/helpers.rb
@@ -6,6 +6,23 @@
 
 require "ostruct"
 
+# Minimal mock register entry
+MockRegEntry = Struct.new(:name)
+
+# Minimal mock register file that satisfies SymbolTable's register_files interface.
+# Used to provide X (and other) register files in test symtab setup.
+class MockRegFile
+  attr_reader :name, :register_length, :registers
+
+  def initialize(name, register_length_idl, count)
+    @name = name
+    @register_length = register_length_idl
+    @registers = Array.new(count) { |i| MockRegEntry.new("#{name.downcase}#{i}") }
+  end
+end
+
+DEFAULT_X_REGISTER_FILE = MockRegFile.new("X", "return MXLEN;", 32)
+
 # Extension mock that returns an extension name
 class Xmockension
   attr_reader :name
@@ -64,7 +81,7 @@ def exists? = true
     def reset_value = @val.nil? ? "UNDEFINED_LEGAL" : @val
   end
   def setup
-    @symtab = Idl::SymbolTable.new
+    @symtab = Idl::SymbolTable.new(register_files: [DEFAULT_X_REGISTER_FILE])
     @compiler = Idl::Compiler.new
     @mock_csr_field_class = MockCsrFieldClass
   end
diff --git a/tools/ruby-gems/idlc/test/run.rb b/tools/ruby-gems/idlc/test/run.rb
index 741c30c202..ee3a10e0c0 100644
--- a/tools/ruby-gems/idlc/test/run.rb
+++ b/tools/ruby-gems/idlc/test/run.rb
@@ -44,3 +44,4 @@
 require_relative "test_variables"
 require_relative "test_control_flow"
 require_relative "test_reserved_words"
+require_relative "test_register_files"
diff --git a/tools/ruby-gems/idlc/test/test_register_files.rb b/tools/ruby-gems/idlc/test/test_register_files.rb
new file mode 100644
index 0000000000..34e2288329
--- /dev/null
+++ b/tools/ruby-gems/idlc/test/test_register_files.rb
@@ -0,0 +1,176 @@
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# typed: false
+# frozen_string_literal: true
+
+require "minitest/autorun"
+
+require "idlc"
+require "idlc/passes/find_src_registers"
+require_relative "helpers"
+
+$root ||= (Pathname.new(__FILE__) / ".." / ".." / ".." / "..").realpath
+
+# Minimal mock register entry for testing
+MockRegisterEntry = Struct.new(:name)
+
+# Minimal mock register file for testing
+class MockRegisterFile
+  attr_reader :name, :register_length
+
+  def initialize(name, register_length_idl, count)
+    @name = name
+    @register_length = register_length_idl
+    @registers = Array.new(count) { |i| MockRegisterEntry.new("#{name.downcase}#{i}") }
+  end
+
+  def registers = @registers
+end
+
+# Tests for register file generalization in the IDL symbol table and type system.
+#
+# These tests drive the implementation of:
+#   - Idl::RegFileElementType (replaces XregType, generalized for any register file)
+#   - SymbolTable.new(register_files: [...]) parameter
+#   - find_src_registers / find_dst_registers returning [rf_name, index] pairs
+class TestRegisterFiles < Minitest::Test
+  def setup
+    @mock_f_rf = MockRegisterFile.new("F", "return 64;", 32)
+    @mock_v_rf = MockRegisterFile.new("V", "return VLEN;", 32)
+    @compiler = Idl::Compiler.new
+  end
+
+  # Verify that SymbolTable.new(register_files: [...]) registers:
+  #   - "F" as a global array var whose sub_type is a RegFileElementType named "F"
+  #   - "FReg" as a RegFileElementType
+  def test_regfile_globals_registered
+    symtab = Idl::SymbolTable.new(register_files: [@mock_f_rf])
+
+    f_var = symtab.get("F")
+    refute_nil f_var, "Expected 'F' to be defined in symtab"
+    assert_equal :array, f_var.type.kind
+    assert_equal 32, f_var.type.width
+    assert f_var.type.qualifiers.include?(:global), "Expected :global qualifier on F"
+
+    sub = f_var.type.sub_type
+    assert_instance_of Idl::RegFileElementType, sub, "Expected sub_type to be RegFileElementType"
+    assert_equal "F", sub.name
+    assert_equal 64, sub.width
+
+    freg_type = symtab.get("FReg")
+    refute_nil freg_type, "Expected 'FReg' to be defined in symtab"
+    assert_instance_of Idl::RegFileElementType, freg_type
+  end
+
+  # Verify that IDL code `FReg v = F[rs1];` type-checks when F is registered.
+  def test_regfile_element_access_typechecks
+    symtab = Idl::SymbolTable.new(
+      register_files: [@mock_f_rf],
+      builtin_global_vars: [
+        Idl::Var.new("rs1", Idl::Type.new(:bits, width: 5))
+      ]
+    )
+
+    ast = @compiler.compile_func_body(
+      "FReg v = F[rs1]; return v;",
+      symtab:,
+      return_type: Idl::Type.new(:bits, width: 64),
+      no_rescue: true,
+      input_file: ""
+    )
+    refute_nil ast
+  end
+
+  # Verify that IDL code `F[rd] = v;` type-checks when F is registered.
+  def test_regfile_element_write_typechecks
+    symtab = Idl::SymbolTable.new(
+      register_files: [@mock_f_rf],
+      builtin_global_vars: [
+        Idl::Var.new("rd", Idl::Type.new(:bits, width: 5)),
+        Idl::Var.new("v", Idl::Type.new(:bits, width: 64))
+      ]
+    )
+
+    ast = @compiler.compile_func_body(
+      "F[rd] = v;",
+      symtab:,
+      return_type: Idl::VoidType,
+      no_rescue: true,
+      input_file: ""
+    )
+    refute_nil ast
+  end
+
+  # Verify that F[0] is not a compile-time constant (register reads are runtime-only).
+  def test_regfile_not_const_eval
+    symtab = Idl::SymbolTable.new(register_files: [@mock_f_rf])
+
+    m = @compiler.parser.parse("F[0]", root: :expression)
+    refute_nil m
+    ast = m.to_ast
+
+    refute ast.const_eval?(symtab), "F[0] should not be compile-time-evaluable"
+  end
+
+  # Verify find_src_registers returns [[rf_name, index]] pairs for F register reads.
+  def test_regfile_find_src_registers
+    symtab = Idl::SymbolTable.new(
+      register_files: [@mock_f_rf],
+      builtin_global_vars: [
+        Idl::Var.new("rs1", Idl::Type.new(:bits, width: 5), 3),
+        Idl::Var.new("rd", Idl::Type.new(:bits, width: 5), 7)
+      ]
+    )
+
+    m = @compiler.parser.parse("F[rs1]", root: :expression)
+    refute_nil m
+    ast = m.to_ast
+
+    srcs = ast.find_src_registers(symtab)
+    assert_equal [["F", 3]], srcs, "Expected find_src_registers to return [[\"F\", 3]]"
+  end
+
+  # Verify find_dst_registers returns [[rf_name, index]] pairs for F register writes.
+  def test_regfile_find_dst_registers
+    # Need a statement context for assignment
+    symtab = Idl::SymbolTable.new(
+      register_files: [@mock_f_rf],
+      builtin_global_vars: [
+        Idl::Var.new("rd", Idl::Type.new(:bits, width: 5), 7),
+        Idl::Var.new("v", Idl::Type.new(:bits, width: 64))
+      ]
+    )
+
+    m = @compiler.parser.parse("F[rd] = v;", root: :statement)
+    refute_nil m
+    ast = m.to_ast
+
+    dsts = ast.find_dst_registers(symtab)
+    assert_equal [["F", 7]], dsts, "Expected find_dst_registers to return [[\"F\", 7]]"
+  end
+
+  # Regression test: X register file still works after generalization.
+  def test_x_register_still_works
+    # X is populated via register_files: in the new implementation,
+    # but still appears as a global array of XReg (now RegFileElementType named "X")
+    mock_x_rf = MockRegisterFile.new("X", "return MXLEN;", 32)
+    symtab = Idl::SymbolTable.new(mxlen: 64, register_files: [mock_x_rf])
+
+    x_var = symtab.get("X")
+    refute_nil x_var, "X should still be in symtab"
+    assert_equal :array, x_var.type.kind
+    assert_equal 32, x_var.type.width
+    assert x_var.type.qualifiers.include?(:global)
+
+    sub = x_var.type.sub_type
+    assert_instance_of Idl::RegFileElementType, sub
+    assert_equal "X", sub.name
+    assert_equal 64, sub.width
+
+    # Check that XReg type alias still exists
+    xreg_type = symtab.get("XReg")
+    refute_nil xreg_type
+    assert_instance_of Idl::RegFileElementType, xreg_type
+  end
+end
diff --git a/tools/ruby-gems/idlc/test/test_values.rb b/tools/ruby-gems/idlc/test/test_values.rb
index c0ab36b3fc..473c73530b 100644
--- a/tools/ruby-gems/idlc/test/test_values.rb
+++ b/tools/ruby-gems/idlc/test/test_values.rb
@@ -68,3 +68,48 @@ def test_to_s
     assert_equal "31'b1111111111111111111x11111111111", tmp.to_s
   end
 end
+
+# Tests for TernaryOperatorExpressionAst#max_value and #min_value.
+# These support the max-register-width derivation used when removing
+# the max_register_length: field from register file YAML.
+class TestTernaryMaxMinValue < Minitest::Test
+  def setup
+    @compiler = Idl::Compiler.new
+    # Symtab with a boolean variable that has no compile-time value, so ternary
+    # conditions referencing it will be unknown at compile time.
+    @symtab = Idl::SymbolTable.new(
+      register_files: [DEFAULT_X_REGISTER_FILE],
+      builtin_global_vars: [
+        Idl::Var.new("flag", Idl::Type.new(:boolean))
+      ]
+    )
+  end
+
+  def compile(expr)
+    @compiler.compile_expression(expr, @symtab, pass_error: true)
+  end
+
+  # Unknown condition → max_value returns the larger of the two literal branches
+  def test_max_value_unknown_condition
+    ast = compile("flag ? 64 : 32")
+    assert_equal 64, ast.max_value(@symtab)
+  end
+
+  # Unknown condition → min_value returns the smaller branch
+  def test_min_value_unknown_condition
+    ast = compile("flag ? 64 : 32")
+    assert_equal 32, ast.min_value(@symtab)
+  end
+
+  # Known-true condition → max_value follows the true branch only
+  def test_max_value_known_true_condition
+    ast = compile("true ? 32 : 64")
+    assert_equal 32, ast.max_value(@symtab)
+  end
+
+  # Known-false condition → max_value follows the false branch only
+  def test_max_value_known_false_condition
+    ast = compile("false ? 32 : 64")
+    assert_equal 64, ast.max_value(@symtab)
+  end
+end
diff --git a/tools/ruby-gems/udb/lib/udb/architecture.rb b/tools/ruby-gems/udb/lib/udb/architecture.rb
index 00ed369534..ba2ca3baa5 100644
--- a/tools/ruby-gems/udb/lib/udb/architecture.rb
+++ b/tools/ruby-gems/udb/lib/udb/architecture.rb
@@ -125,7 +125,7 @@ def validate(resolver, show_progress: true)
       },
       {
         fn_name: "register_file",
-        arch_dir: "register",
+        arch_dir: "register_file",
         klass: RegisterFile,
         kind: DatabaseObject::Kind::RegisterFile
       },
diff --git a/tools/ruby-gems/udb/lib/udb/cfg_arch.rb b/tools/ruby-gems/udb/lib/udb/cfg_arch.rb
index 547eb2c6f8..21fee21795 100644
--- a/tools/ruby-gems/udb/lib/udb/cfg_arch.rb
+++ b/tools/ruby-gems/udb/lib/udb/cfg_arch.rb
@@ -204,7 +204,19 @@ def symtab
         begin
           @symtab = create_symtab
 
-          global_ast.add_global_symbols(@symtab)
+          # Guard against re-entrant solver calls from within add_global_symbols.
+          # Global initializers (e.g. FLEN) may call implemented?(), which triggers
+          # prohibited_ext?() and the Z3 solver chain. If those calls see @symtab is
+          # already set (partial), they'd use an incomplete symtab and fail.
+          # A depth counter (rather than a boolean) is used so that if this block
+          # ever nests (e.g. create_symtab is called recursively in the future),
+          # the inner ensure does not prematurely clear the guard for the outer block.
+          @constructing_symtab_depth = (@constructing_symtab_depth || 0) + 1
+          begin
+            global_ast.add_global_symbols(@symtab)
+          ensure
+            @constructing_symtab_depth -= 1
+          end
 
           @symtab.deep_freeze
           raise if @symtab.name.nil?
@@ -213,6 +225,11 @@ def symtab
         end
     end
 
+    # @return [Boolean] true while add_global_symbols is running inside symtab construction
+    # Used by implemented? callback to avoid triggering the Z3 solver on a partial symtab.
+    sig { returns(T::Boolean) }
+    def constructing_symtab? = (@constructing_symtab_depth || 0) > 0
+
     sig { returns(Idl::IsaAst) }
     def global_ast
       @global_ast ||=
@@ -488,6 +505,11 @@ def symtab_callbacks
               # we can know if it is implemented, but not if it's not implemented for a partially configured
               if ext?(ext_name)
                 true
+              elsif constructing_symtab?
+                # During symtab construction (add_global_symbols), the Z3 solver is not
+                # available because the symtab is partial. Return nil (unknown) so that
+                # value_try falls back to storing the global with nil (no compile-time value).
+                nil
               elsif prohibited_ext?(ext_name)
                 false
               else
@@ -504,6 +526,9 @@ def symtab_callbacks
               # we can know if it is implemented, but not if it's not implemented for a partially configured
               if ext?(ext_name, [version])
                 true
+              elsif constructing_symtab?
+                # Same guard as for implemented? above.
+                nil
               elsif prohibited_ext?(ext_name)
                 false
               else
@@ -583,6 +608,33 @@ def create_symtab
       end
       pb.finish
 
+      # Build a bootstrap symtab and compute RF max widths before constructing the real
+      # symtab. The bootstrap needs add_global_symbols so that implemented?() is a known
+      # function (required for type_check to pass). Running it under @constructing_symtab=true
+      # ensures implemented?() returns nil → value_error during value evaluation, which
+      # causes TernaryOperatorExpressionAst#max_value to explore both branches.
+      bootstrap_st = Idl::SymbolTable.new(
+        mxlen:,
+        builtin_global_vars: final_param_vars,
+        builtin_enums: symtab_enums,
+        builtin_funcs: symtab_callbacks,
+        params: all_params,
+        name: "#{@name}/bootstrap",
+        register_files: []
+      )
+      rf_max_widths = begin
+        @constructing_symtab_depth = (@constructing_symtab_depth || 0) + 1
+        global_ast.add_global_symbols(bootstrap_st)
+        register_files.each_with_object({}) do |rf, h|
+          node = @idl_compiler.compile_expression(rf.register_length_expr, bootstrap_st, pass_error: true)
+          max = node.max_value(bootstrap_st)
+          raise "Cannot determine max width for register file '#{rf.name}'" if max == :unknown
+          h[rf.name] = Integer(max)
+        end
+      ensure
+        @constructing_symtab_depth -= 1
+      end
+
       Idl::SymbolTable.new(
         mxlen:,
         possible_xlens_cb: proc { possible_xlens },
@@ -591,7 +643,9 @@ def create_symtab
         builtin_enums: symtab_enums,
         name: @name,
         csrs:,
-        params: all_params
+        params: all_params,
+        register_files: register_files,
+        register_file_max_widths: rf_max_widths
       )
     end
     private :create_symtab
diff --git a/tools/ruby-gems/udb/lib/udb/obj/register_file.rb b/tools/ruby-gems/udb/lib/udb/obj/register_file.rb
index c473936b84..53212e3b36 100644
--- a/tools/ruby-gems/udb/lib/udb/obj/register_file.rb
+++ b/tools/ruby-gems/udb/lib/udb/obj/register_file.rb
@@ -49,6 +49,12 @@ def name = @data.fetch("name")
     sig { returns(T::Array[String]) }
     def abi_mnemonics = @data.fetch("abi_mnemonics", [])
 
+    sig { returns(T.nilable(String)) }
+    def reset_value = @data["reset_value"]
+
+    sig { returns(RegisterFile) }
+    def register_file = @file
+
     sig { returns(T.any(Integer, String)) }
     def index = @index
 
@@ -97,8 +103,63 @@ def when_condition
     end
   end
 
-  sig { returns(T.any(Integer, String)) }
-  def register_length = @data.fetch("register_length")
+  # Returns the IDL function body string for the register_length() field.
+  # e.g. "return MXLEN;" or "return implemented?(ExtensionName::D) ? 64 : 32;"
+  sig { returns(String) }
+  def register_length = @data.fetch("register_length()")
+
+  # Returns the stripped IDL expression (no 'return' keyword or trailing semicolon).
+  sig { returns(String) }
+  def register_length_expr
+    register_length.strip.sub(/\Areturn\s+/, "").sub(/;\z/, "").strip
+  end
+
+  # Evaluate the register_length() IDL body against the given cfg_arch parameter context.
+  # Returns an Integer if the width is statically determined, or a String param name
+  # if the width depends on a runtime parameter (e.g. "VLEN").
+  sig { params(cfg_arch: ConfiguredArchitecture).returns(T.any(Integer, String)) }
+  def eval_register_length(cfg_arch)
+    expr = register_length_expr
+
+    # Literal integer
+    return Integer(expr) if expr =~ /\A\d+\z/
+
+    # Simple MXLEN reference
+    if expr == "MXLEN"
+      mxlen = cfg_arch.mxlen
+      return mxlen || "MXLEN"  # Return String "MXLEN" for dynamic-XLEN configs
+    end
+
+    # Check for a fixed parameter
+    fixed = cfg_arch.params_with_value.find { |p| p.name == expr }
+    return T.cast(fixed.value, Integer).to_i if fixed
+
+    # Check if it's a free parameter name
+    free = cfg_arch.params_without_value.find { |p| p.name == expr }
+    return expr if free
+
+    # Complex expression — fall back to the architectural maximum.
+    max_register_length
+  end
+
+  # Maximum value register_length() can return across all valid configurations.
+  # Derived by compiling the register_length() expression against the full symtab
+  # and calling max_value — unknown conditions (e.g. implemented?) cause the ternary
+  # to return the max of both branches.
+  sig { returns(Integer) }
+  def max_register_length
+    @max_register_length ||= _compute_max_register_length
+  end
+
+  private def _compute_max_register_length
+    node = cfg_arch.idl_compiler.compile_expression(
+      register_length_expr, cfg_arch.symtab, pass_error: true
+    )
+    max = node.max_value(cfg_arch.symtab)
+    raise "Cannot determine max_register_length for register file '#{name}' " \
+          "(register_length() expression: '#{register_length_expr}')" if max == :unknown
+    Integer(max)
+  end
 
   sig { returns(T.nilable(String)) }
   def summary = @data["summary"]
diff --git a/tools/ruby-gems/udb/test/run.rb b/tools/ruby-gems/udb/test/run.rb
index e50f28e18a..e514c1e10a 100644
--- a/tools/ruby-gems/udb/test/run.rb
+++ b/tools/ruby-gems/udb/test/run.rb
@@ -17,3 +17,4 @@
 require_relative "test_mmr_schema"
 require_relative "test_yaml_loader"
 require_relative "test_z3"
+require_relative "test_register_file_obj"
diff --git a/tools/ruby-gems/udb/test/test_register_file_obj.rb b/tools/ruby-gems/udb/test/test_register_file_obj.rb
new file mode 100644
index 0000000000..124b7694f0
--- /dev/null
+++ b/tools/ruby-gems/udb/test/test_register_file_obj.rb
@@ -0,0 +1,123 @@
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# typed: false
+# frozen_string_literal: true
+
+require_relative "test_helper"
+
+require "ostruct"
+require "concurrent"
+require "sorbet-runtime"
+require "udb/obj/register_file"
+require "udb/cfg_arch"
+
+# Tests for RegisterFile Ruby object model changes needed for register file consolidation.
+#
+# These tests drive Step 4 of the implementation:
+#   - register_length() IDL function body field (replaces static register_length field)
+#   - RegisterFile#eval_register_length(cfg_arch) -> Integer or String param name
+#   - RegisterFile#max_register_length -> Integer architectural maximum
+#   - RegisterEntry#reset_value -> IDL literal string or nil
+#   - RegisterEntry#register_file -> parent RegisterFile back-reference
+class TestRegisterFileObj < Minitest::Test
+  include Udb
+
+  # Build a mock ConfiguredArchitecture that is-a real ConfiguredArchitecture (Sorbet passes),
+  # but with minimal state. Uses allocate to bypass the complex constructor.
+  def make_cfg_arch(mxlen: 64, free_params: [])
+    arch = Udb::ConfiguredArchitecture.allocate
+    arch.instance_variable_set(:@mxlen, mxlen)
+    arch.instance_variable_set(:@objects, Concurrent::Hash.new)
+    arch.instance_variable_set(:@object_hashes, Concurrent::Hash.new)
+
+    # Inject test-only methods to answer what eval_register_length needs
+    mxlen_val = mxlen
+    free_params_names = free_params
+    arch.define_singleton_method(:mxlen) { mxlen_val }
+    arch.define_singleton_method(:param_values) { mxlen_val ? { "MXLEN" => mxlen_val } : {} }
+    arch.define_singleton_method(:params_with_value) do
+      mxlen_val ? [OpenStruct.new(name: "MXLEN", value: mxlen_val)] : []
+    end
+    arch.define_singleton_method(:params_without_value) do
+      free_params_names.map { |n| OpenStruct.new(name: n) }
+    end
+    arch
+  end
+
+  # Build a minimal RegisterFile from a data hash using a real ConfiguredArchitecture
+  # instance (bypasses Sorbet type check by using a genuine subtype).
+  def make_rf(data_overrides = {})
+    base = {
+      "name" => "X",
+      "kind" => "register_file",
+      "long_name" => "General Purpose Registers",
+      "register_length()" => "return MXLEN;",
+      "registers" => [
+        {
+          "name" => "x0",
+          "reset_value" => "0",
+          "arch_read()" => "return 0;",
+          "arch_write(value)" => "return 0;"
+        },
+        {
+          "name" => "x1"
+        }
+      ]
+    }.merge(data_overrides)
+    arch = make_cfg_arch(mxlen: 64)
+    RegisterFile.new(base, Pathname.new("/mock/register_file/X.yaml"), arch)
+  end
+
+  # register_length() IDL body should be returned as a string
+  def test_register_length_idl_string
+    rf = make_rf
+    assert_equal "return MXLEN;", rf.register_length,
+      "Expected register_length to return the IDL body string"
+  end
+
+  # eval_register_length with MXLEN=64 cfg_arch should return Integer 64
+  def test_eval_register_length_integer
+    rf = make_rf
+    cfg_arch = make_cfg_arch(mxlen: 64)
+    result = rf.eval_register_length(cfg_arch)
+    assert_equal 64, result,
+      "Expected eval_register_length to return 64 for MXLEN=64 cfg_arch"
+  end
+
+  # eval_register_length for V with free VLEN should return String "VLEN"
+  def test_eval_register_length_param_string
+    rf = make_rf(
+      "name" => "V",
+      "long_name" => "Vector Registers",
+      "register_length()" => "return VLEN;",
+      "registers" => Array.new(32) { |i| { "name" => "v#{i}" } }
+    )
+    cfg_arch = make_cfg_arch(mxlen: nil, free_params: ["VLEN"])
+    result = rf.eval_register_length(cfg_arch)
+    assert_equal "VLEN", result,
+      "Expected eval_register_length to return param name string when VLEN is free"
+  end
+
+  # reset_value present in YAML (x0 entry) should be returned as a string
+  def test_reset_value_present
+    rf = make_rf
+    assert_equal "0", rf.registers[0].reset_value,
+      "Expected x0 reset_value to be '0'"
+  end
+
+  # reset_value absent from YAML (x1 entry) should return nil
+  def test_reset_value_absent
+    rf = make_rf
+    assert_nil rf.registers[1].reset_value,
+      "Expected x1 reset_value to be nil when not specified"
+  end
+
+  # registers[0].register_file should be the parent RegisterFile object
+  def test_register_file_back_ref
+    rf = make_rf
+    entry = rf.registers[0]
+    assert_same rf, entry.register_file,
+      "Expected register_file to return the parent RegisterFile"
+  end
+end