From 87f8bb34d629163563515a82102c48b722ab9058 Mon Sep 17 00:00:00 2001 From: guan jian <148229859+rez5427@users.noreply.github.com> Date: Tue, 8 Oct 2024 21:28:12 +0800 Subject: [PATCH] Fix mask and disassembly typos in Vector extension Fix incorrect use of `vm_val` instead of `mask`, and a copy/paste error for the `vsox*` disassembly. Co-authored-by: Yui5427 <785369607@qq.com> --- model/riscv_insts_vext_mem.sail | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/model/riscv_insts_vext_mem.sail b/model/riscv_insts_vext_mem.sail index 001ad44d..cc816130 100644 --- a/model/riscv_insts_vext_mem.sail +++ b/model/riscv_insts_vext_mem.sail @@ -146,7 +146,7 @@ function process_vlsegff (nf, vm, vd, load_width_bytes, rs1, EMUL_pow, num_elem) var trimmed : bool = false; foreach (i from 0 to (num_elem - 1)) { if not(trimmed) then { - if vm_val[i] then { /* active segments */ + if mask[i] then { /* active segments */ foreach (j from 0 to (nf - 1)) { let elem_offset = (i * nf + j) * load_width_bytes; match ext_data_get_addr(rs1, to_bits(xlen, elem_offset), Read(Data), load_width_bytes) { @@ -247,7 +247,7 @@ function process_vsseg (nf, vm, vs3, load_width_bytes, rs1, EMUL_pow, num_elem) let mask : vector('n, bool) = init_masked_source(num_elem, EMUL_pow, vm_val); foreach (i from 0 to (num_elem - 1)) { - if vm_val[i] then { /* active segments */ + if mask[i] then { /* active segments */ vstart = to_bits(16, i); foreach (j from 0 to (nf - 1)) { let elem_offset = (i * nf + j) * load_width_bytes; @@ -622,7 +622,7 @@ function clause execute(VSOXSEGTYPE(nf, vm, vs2, rs1, width, vs3)) = { process_vsxseg(nf_int, vm, vs3, EEW_index_bytes, EEW_data_bytes, EMUL_index_pow, EMUL_data_pow, rs1, vs2, num_elem, 3) } -mapping clause assembly = VSUXSEGTYPE(nf, vm, vs2, rs1, width, vs3) +mapping clause assembly = VSOXSEGTYPE(nf, vm, vs2, rs1, width, vs3) <-> "vsox" ^ nfields_string(nf) ^ "ei" ^ vlewidth_bitsnumberstr(width) ^ ".v" ^ spc() ^ vreg_name(vs3) ^ sep() ^ "(" ^ reg_name(rs1) ^ ")" ^ sep() ^ reg_name(vs2) ^ maybe_vmask(vm) /* ***************** Vector Load Unit-Stride Whole Register (vm=0b1, mop=0b00, lumop=0b01000) ****************** */