TODO: kernel IPL handling

[robertlipe]

The VAX IPL levels map to x86 interrupts somewhat cleanly, but not so well to RISC-V. Once we really reach our stride of having disk, display, terminals, and such going, we need to preserve the spl(x) and split() functionality in a way that approximately maps to RISC-V interrupt controllers. (Bonus points for working on both GD32V and K210, even if only one core awake.)

The terms are described pretty well at http://osr600doc.sco.com/en/man/html.D3/spl.D3.html I think disk, tty, base, timeout, split are probably the highpoint.